llvm · arsenm · May 30, 2025 · May 29, 2025
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -2322,7 +2322,7 @@ void AsmPrinter::emitGlobalIFunc(Module &M, const GlobalIFunc &GI) {
   }
 
   if (!TM.getTargetTriple().isOSBinFormatMachO() || !getIFuncMCSubtargetInfo())
-    llvm::report_fatal_error("IFuncs are not supported on this platform");
+    reportFatalUsageError("IFuncs are not supported on this platform");
 
   // On Darwin platforms, emit a manually-constructed .symbol_resolver that
   // implements the symbol resolution duties of the IFunc.

diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -632,7 +632,7 @@ void LiveVariables::analyze(MachineFunction &mf) {
   // LiveVariables to improve compilation time and eliminate bizarre pass
   // dependencies. Until then, we can't change much in -O0.
   if (!MRI->isSSA())
-    report_fatal_error("regalloc=... not currently supported with -O0");
+    reportFatalUsageError("regalloc=... not currently supported with -O0");
 
   analyzePHINodes(mf);
 

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -349,7 +349,7 @@ bool SelectionDAGISelLegacy::runOnMachineFunction(MachineFunction &MF) {
 
   // Do some sanity-checking on the command-line options.
   if (EnableFastISelAbort && !Selector->TM.Options.EnableFastISel)
-    report_fatal_error("-fast-isel-abort > 0 requires -fast-isel");
+    reportFatalUsageError("-fast-isel-abort > 0 requires -fast-isel");
 
   // Decide what flavour of variable location debug-info will be used, before
   // we change the optimisation level.
@@ -424,7 +424,7 @@ SelectionDAGISelPass::run(MachineFunction &MF,
 
   // Do some sanity-checking on the command-line options.
   if (EnableFastISelAbort && !Selector->TM.Options.EnableFastISel)
-    report_fatal_error("-fast-isel-abort > 0 requires -fast-isel");
+    reportFatalUsageError("-fast-isel-abort > 0 requires -fast-isel");
 
   // Decide what flavour of variable location debug-info will be used, before
   // we change the optimisation level.
@@ -797,7 +797,7 @@ static void reportFastISelFailure(MachineFunction &MF,
     R << (" (in function: " + MF.getName() + ")").str();
 
   if (ShouldAbort)
-    report_fatal_error(Twine(R.getMsg()));
+    reportFatalUsageError(Twine(R.getMsg()));
 
   ORE.emit(R);
   LLVM_DEBUG(dbgs() << R.getMsg() << "\n");

diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp
@@ -421,8 +421,8 @@ static const PassInfo *getPassInfo(StringRef PassName) {
   const PassRegistry &PR = *PassRegistry::getPassRegistry();
   const PassInfo *PI = PR.getPassInfo(PassName);
   if (!PI)
-    report_fatal_error(Twine('\"') + Twine(PassName) +
-                       Twine("\" pass is not registered."));
+    reportFatalUsageError(Twine('\"') + Twine(PassName) +
+                          Twine("\" pass is not registered."));
   return PI;
 }
 
@@ -438,7 +438,7 @@ getPassNameAndInstanceNum(StringRef PassName) {
 
   unsigned InstanceNum = 0;
   if (!InstanceNumStr.empty() && InstanceNumStr.getAsInteger(10, InstanceNum))
-    report_fatal_error("invalid pass instance specifier " + PassName);
+    reportFatalUsageError("invalid pass instance specifier " + PassName);
 
   return std::make_pair(Name, InstanceNum);
 }
@@ -465,11 +465,11 @@ void TargetPassConfig::setStartStopPasses() {
   StopBefore = getPassIDFromName(StopBeforeName);
   StopAfter = getPassIDFromName(StopAfterName);
   if (StartBefore && StartAfter)
-    report_fatal_error(Twine(StartBeforeOptName) + Twine(" and ") +
-                       Twine(StartAfterOptName) + Twine(" specified!"));
+    reportFatalUsageError(Twine(StartBeforeOptName) + Twine(" and ") +
+                          Twine(StartAfterOptName) + Twine(" specified!"));
   if (StopBefore && StopAfter)
-    report_fatal_error(Twine(StopBeforeOptName) + Twine(" and ") +
-                       Twine(StopAfterOptName) + Twine(" specified!"));
+    reportFatalUsageError(Twine(StopBeforeOptName) + Twine(" and ") +
+                          Twine(StopAfterOptName) + Twine(" specified!"));
   Started = (StartAfter == nullptr) && (StartBefore == nullptr);
 }
 
@@ -635,9 +635,9 @@ CodeGenTargetMachineImpl::createPassConfig(PassManagerBase &PM) {
 
 TargetPassConfig::TargetPassConfig()
   : ImmutablePass(ID) {
-  report_fatal_error("Trying to construct TargetPassConfig without a target "
-                     "machine. Scheduling a CodeGen pass without a target "
-                     "triple set?");
+  reportFatalUsageError("trying to construct TargetPassConfig without a target "
+                        "machine. Scheduling a CodeGen pass without a target "
+                        "triple set?");
 }
 
 bool TargetPassConfig::willCompleteCodeGenPipeline() {
@@ -738,7 +738,7 @@ void TargetPassConfig::addPass(Pass *P) {
   if (StartAfter == PassID && StartAfterCount++ == StartAfterInstanceNum)
     Started = true;
   if (Stopped && !Started)
-    report_fatal_error("Cannot stop compilation after pass that is not run");
+    reportFatalUsageError("Cannot stop compilation after pass that is not run");
 }
 
 /// Add a CodeGen pass at this point in the pipeline after checking for target
@@ -1408,7 +1408,8 @@ bool TargetPassConfig::isCustomizedRegAlloc() {
 bool TargetPassConfig::addRegAssignAndRewriteFast() {
   if (RegAlloc != (RegisterRegAlloc::FunctionPassCtor)&useDefaultRegisterAllocator &&
       RegAlloc != (RegisterRegAlloc::FunctionPassCtor)&createFastRegisterAllocator)
-    report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
+    reportFatalUsageError(
+        "Must use fast (default) register allocator for unoptimized regalloc.");
 
   addPass(createRegAllocPass(false));
 

diff --git a/llvm/test/CodeGen/AArch64/fast-isel-sp-adjust.ll b/llvm/test/CodeGen/AArch64/fast-isel-sp-adjust.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -O0 -fast-isel -mtriple=aarch64-apple-ios -o - %s | FileCheck %s
-; RUN: not --crash llc -O0 -mtriple=aarch64-apple-ios -o /dev/null -fast-isel -fast-isel-abort=3 %s 2> %t
+; RUN: not llc -O0 -mtriple=aarch64-apple-ios -o /dev/null -fast-isel -fast-isel-abort=3 %s 2> %t
 ; RUN: FileCheck %s --check-prefix=CHECK-ERRORS < %t
 
 ; The issue here is that FastISel cannot emit an ADDrr where one of the inputs

diff --git a/llvm/test/CodeGen/Generic/llc-start-stop-instance-errors.ll b/llvm/test/CodeGen/Generic/llc-start-stop-instance-errors.ll
@@ -1,4 +1,4 @@
-; RUN: not --crash llc -debug-pass=Structure -stop-after=dead-mi-elimination,arst %s -o /dev/null 2>&1 \
+; RUN: not llc -debug-pass=Structure -stop-after=dead-mi-elimination,arst %s -o /dev/null 2>&1 \
 ; RUN:   | FileCheck -check-prefix=NOT-NUM %s
 
 ; NOT-NUM: LLVM ERROR: invalid pass instance specifier dead-mi-elimination,arst
diff --git a/llvm/test/CodeGen/Generic/llc-start-stop.ll b/llvm/test/CodeGen/Generic/llc-start-stop.ll
@@ -29,16 +29,16 @@
 ; START-BEFORE: Loop Strength Reduction
 ; START-BEFORE-NEXT: {{Loop Terminator Folding|Basic Alias Analysis \(stateless AA impl\)}}
 
-; RUN: not --crash llc < %s -start-before=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-START-BEFORE
-; RUN: not --crash llc < %s -stop-before=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-STOP-BEFORE
-; RUN: not --crash llc < %s -start-after=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-START-AFTER
-; RUN: not --crash llc < %s -stop-after=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-STOP-AFTER
+; RUN: not llc < %s -start-before=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-START-BEFORE
+; RUN: not llc < %s -stop-before=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-STOP-BEFORE
+; RUN: not llc < %s -start-after=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-START-AFTER
+; RUN: not llc < %s -stop-after=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-STOP-AFTER
 ; NONEXISTENT-START-BEFORE: "nonexistent" pass is not registered.
 ; NONEXISTENT-STOP-BEFORE: "nonexistent" pass is not registered.
 ; NONEXISTENT-START-AFTER: "nonexistent" pass is not registered.
 ; NONEXISTENT-STOP-AFTER: "nonexistent" pass is not registered.
 
-; RUN: not --crash llc < %s -start-before=loop-reduce -start-after=loop-reduce -o /dev/null 2>&1 | FileCheck %s -check-prefix=DOUBLE-START
-; RUN: not --crash llc < %s -stop-before=loop-reduce -stop-after=loop-reduce -o /dev/null 2>&1 | FileCheck %s -check-prefix=DOUBLE-STOP
+; RUN: not llc < %s -start-before=loop-reduce -start-after=loop-reduce -o /dev/null 2>&1 | FileCheck %s -check-prefix=DOUBLE-START
+; RUN: not llc < %s -stop-before=loop-reduce -stop-after=loop-reduce -o /dev/null 2>&1 | FileCheck %s -check-prefix=DOUBLE-STOP
 ; DOUBLE-START: start-before and start-after specified!
 ; DOUBLE-STOP: stop-before and stop-after specified!
diff --git a/llvm/test/CodeGen/Generic/opt-codegen-no-target-machine.ll b/llvm/test/CodeGen/Generic/opt-codegen-no-target-machine.ll
@@ -1,3 +1,3 @@
-; RUN: not --crash opt %s -dwarf-eh-prepare -o - 2>&1 | FileCheck %s
+; RUN: not opt %s -dwarf-eh-prepare -o - 2>&1 | FileCheck %s
 
-; CHECK: Trying to construct TargetPassConfig without a target machine. Scheduling a CodeGen pass without a target triple set?
+; CHECK: LLVM ERROR: trying to construct TargetPassConfig without a target machine. Scheduling a CodeGen pass without a target triple set?
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll b/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll
@@ -1,13 +1,13 @@
-; RUN: not --crash llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+fp64 \
-; RUN:         -O0 -relocation-model=pic -fast-isel-abort=3 < %s
+; RUN: not llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+fp64 \
+; RUN:         -O0 -relocation-model=pic -fast-isel-abort=3 -filetype=null %s 2>&1 | FileCheck %s
 
 ; Check that FastISel aborts when we have 64bit FPU registers. FastISel currently
 ; supports AFGR64 only, which uses paired 32 bit registers.
 
+; CHECK: LLVM ERROR: FastISel didn't lower all arguments: i1 (double) (in function: f)
+
 define zeroext i1 @f(double %value) {
 entry:
-; CHECK-LABEL: f:
-; CHECK: sdc1
   %value.addr = alloca double, align 8
   store double %value, ptr %value.addr, align 8
   ret i1 false

diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll
@@ -1,8 +1,9 @@
-; RUN: not --crash llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+soft-float \
-; RUN:         -O0 -fast-isel-abort=3 -relocation-model=pic < %s
+; RUN: not llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+soft-float \
+; RUN:         -O0 -fast-isel-abort=3 -relocation-model=pic < %s 2>&1 | FileCheck %s
 
 ; Test that FastISel aborts instead of trying to lower arguments for soft-float.
 
+; CHECK: LLVM ERROR: FastISel didn't lower all arguments: void (double) (in function: __signbit)
 define void @__signbit(double %__x) {
 entry:
   %__x.addr = alloca double, align 8

diff --git a/llvm/test/CodeGen/X86/fast-isel-args-fail2.ll b/llvm/test/CodeGen/X86/fast-isel-args-fail2.ll
@@ -1,4 +1,6 @@
-; RUN: not --crash llc < %s -fast-isel -fast-isel-abort=2 -mtriple=x86_64-apple-darwin10
+; RUN: not llc < %s -fast-isel -fast-isel-abort=2 -mtriple=x86_64-apple-darwin10 2>&1 | FileCheck %s
+
+; CHECK: LLVM ERROR: FastISel didn't lower all arguments: ptr (ptr) (in function: args_fail)
 
 %struct.s0 = type { x86_fp80, x86_fp80 }