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[llvm-exegesis] Ignore the instructions for which InstrDesc.getSchedClass() == 0 #143840
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This allows llvm-exegesis to skip instructions that lack scheduling information, avoiding invalid benchmarking. e.g. `InstB` in RISC-V.
@llvm/pr-subscribers-tools-llvm-exegesis @llvm/pr-subscribers-tablegen Author: Jim Lin (tclin914) ChangesThis allows llvm-exegesis to skip instructions that lack scheduling Full diff: https://github.com/llvm/llvm-project/pull/143840.diff 3 Files Affected:
diff --git a/llvm/include/llvm/MC/MCInstrDesc.h b/llvm/include/llvm/MC/MCInstrDesc.h
index 8c70925d4780e..69d8e03fb79bd 100644
--- a/llvm/include/llvm/MC/MCInstrDesc.h
+++ b/llvm/include/llvm/MC/MCInstrDesc.h
@@ -188,6 +188,7 @@ enum Flag {
Trap,
VariadicOpsAreDefs,
Authenticated,
+ HasNoSchedulingInfo,
};
} // namespace MCID
@@ -430,6 +431,11 @@ class MCInstrDesc {
return Flags & (1ULL << MCID::Authenticated);
}
+ /// Return true if this instruction has no scheduling info.
+ bool hasNoSchedulingInfo() const {
+ return Flags & (1ULL << MCID::HasNoSchedulingInfo);
+ }
+
//===--------------------------------------------------------------------===//
// Side Effect Analysis
//===--------------------------------------------------------------------===//
diff --git a/llvm/tools/llvm-exegesis/lib/Target.cpp b/llvm/tools/llvm-exegesis/lib/Target.cpp
index 68d19514bedb2..9eb8f4d11bfb3 100644
--- a/llvm/tools/llvm-exegesis/lib/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/Target.cpp
@@ -45,6 +45,8 @@ ExegesisTarget::getIgnoredOpcodeReasonOrNull(const LLVMState &State,
return "Unsupported opcode: isBranch/isIndirectBranch";
if (InstrDesc.isCall() || InstrDesc.isReturn())
return "Unsupported opcode: isCall/isReturn";
+ if (InstrDesc.hasNoSchedulingInfo())
+ return "Unsupported opcode: hasNoSchedulingInfo";
return nullptr;
}
diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp
index e72055b0b5037..06113cff3a350 100644
--- a/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -1199,6 +1199,8 @@ void InstrInfoEmitter::emitRecord(
OS << "|(1ULL<<MCID::VariadicOpsAreDefs)";
if (Inst.isAuthenticated)
OS << "|(1ULL<<MCID::Authenticated)";
+ if (Inst.hasNoSchedulingInfo)
+ OS << "|(1ULL<<MCID::HasNoSchedulingInfo)";
// Emit all of the target-specific flags...
const BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
|
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I also agree that we should probably check if MCInstrDesc::getSchedClass()
is zero or not instead. Because if I'm not mistaken, you can actually have an instruction that lacks scheduling info without hasNoSchedulingInfo
being true (as long as CompleteModel
is false).
Also, could you add a test?
Done. Thanks. |
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LGTM.
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LGTM, good catch.
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nit: could you rename this test to unsupported-opcode.test
? Having a .s that is not actually an assembly file feels a bit weird to me.
…lass() == 0 (llvm#143840) This allows llvm-exegesis to skip instructions that lack scheduling information, avoiding invalid benchmarking. e.g. `InstB` in RISC-V.
This allows llvm-exegesis to skip instructions that lack scheduling
information, avoiding invalid benchmarking. e.g.
InstB
in RISC-V.