[Object][AMDGPU] Support REL relocations #143966
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
|
@llvm/pr-subscribers-backend-amdgpu @llvm/pr-subscribers-llvm-binary-utilities Author: Scott Linder (slinder1) ChangesFull diff: https://github.com/llvm/llvm-project/pull/143966.diff 3 Files Affected:
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 174a497c51b26..4aea702a702ab 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -2709,7 +2709,8 @@ The following relocation types are supported:
the ``mesa3d`` OS, which does not support ``R_AMDGPU_ABS64``.
There is no current OS loader support for 32-bit programs and so
-``R_AMDGPU_ABS32`` is not used.
+``R_AMDGPU_ABS32`` is only generated for static relocations, for example to
+implement some DWARF32 forms.
.. _amdgpu-loaded-code-object-path-uniform-resource-identifier:
diff --git a/llvm/lib/Object/RelocationResolver.cpp b/llvm/lib/Object/RelocationResolver.cpp
index 8cf748aa5681c..b6318bbe3ab74 100644
--- a/llvm/lib/Object/RelocationResolver.cpp
+++ b/llvm/lib/Object/RelocationResolver.cpp
@@ -274,11 +274,13 @@ static bool supportsAmdgpu(uint64_t Type) {
}
static uint64_t resolveAmdgpu(uint64_t Type, uint64_t Offset, uint64_t S,
- uint64_t /*LocData*/, int64_t Addend) {
+ uint64_t LocData, int64_t Addend) {
+ assert((LocData == 0 || Addend == 0) &&
+ "one of LocData and Addend must be 0");
switch (Type) {
case ELF::R_AMDGPU_ABS32:
case ELF::R_AMDGPU_ABS64:
- return S + Addend;
+ return S + LocData + Addend;
default:
llvm_unreachable("Invalid relocation type");
}
diff --git a/llvm/test/DebugInfo/AMDGPU/dwarfdump-rel.yaml b/llvm/test/DebugInfo/AMDGPU/dwarfdump-rel.yaml
new file mode 100644
index 0000000000000..23b7f087e9570
--- /dev/null
+++ b/llvm/test/DebugInfo/AMDGPU/dwarfdump-rel.yaml
@@ -0,0 +1,86 @@
+# RUN: yaml2obj %s -o %t
+# RUN: llvm-dwarfdump -i %t | FileCheck %s
+
+# Test REL relocation handling for AMDGPU
+
+# CHECK: DW_TAG_compile_unit
+# CHECK: DW_AT_producer ("dxc")
+# CHECK: DW_AT_name (".\\example.hlsl")
+# CHECK: DW_AT_str_offsets_base (0x00000008)
+
+--- !ELF
+FileHeader:
+ Class: ELFCLASS64
+ Data: ELFDATA2LSB
+ OSABI: ELFOSABI_AMDGPU_PAL
+ Type: ET_REL
+ Machine: EM_AMDGPU
+ Flags: [ EF_AMDGPU_MACH_AMDGCN_GFX1201 ]
+ SectionHeaderStringTable: .strtab
+Sections:
+ - Name: .debug_abbrev
+ Type: SHT_PROGBITS
+ AddressAlign: 0x1
+ Content: 01110125251305032572171017110B120673178C0117000000
+ - Name: .debug_info
+ Type: SHT_PROGBITS
+ AddressAlign: 0x1
+ Content: 23000000050001080000000001000400010800000000000000005C000000080000000C00000000
+ - Name: .debug_str_offsets
+ Type: SHT_PROGBITS
+ AddressAlign: 0x1
+ Content: 0C000000050000000000000004000000
+ - Name: .rel.debug_info
+ Type: SHT_REL
+ Flags: [ SHF_INFO_LINK ]
+ Link: .symtab
+ AddressAlign: 0x8
+ Info: .debug_info
+ Relocations:
+ - Offset: 0x8
+ Symbol: .debug_abbrev
+ Type: R_AMDGPU_ABS32
+ - Offset: 0x11
+ Symbol: .debug_str_offsets
+ Type: R_AMDGPU_ABS32
+ - Name: .rel.debug_str_offsets
+ Type: SHT_REL
+ Flags: [ SHF_INFO_LINK ]
+ Link: .symtab
+ AddressAlign: 0x8
+ Info: .debug_str_offsets
+ Relocations:
+ - Offset: 0x8
+ Symbol: .debug_str
+ Type: R_AMDGPU_ABS32
+ - Offset: 0xC
+ Symbol: .debug_str
+ Type: R_AMDGPU_ABS32
+ - Type: SectionHeaderTable
+ Sections:
+ - Name: .strtab
+ - Name: .debug_abbrev
+ - Name: .debug_info
+ - Name: .rel.debug_info
+ - Name: .debug_str_offsets
+ - Name: .rel.debug_str_offsets
+ - Name: .debug_str
+ - Name: .symtab
+Symbols:
+ - Name: .debug_abbrev
+ Type: STT_SECTION
+ Section: .debug_abbrev
+ - Name: .debug_info
+ Type: STT_SECTION
+ Section: .debug_info
+ - Name: .debug_str_offsets
+ Type: STT_SECTION
+ Section: .debug_str_offsets
+ - Name: .debug_str
+ Type: STT_SECTION
+ Section: .debug_str
+DWARF:
+ debug_str:
+ - 'dxc'
+ - '.\example.hlsl'
+...
|
|
@llvm/pr-subscribers-debuginfo Author: Scott Linder (slinder1) ChangesFull diff: https://github.com/llvm/llvm-project/pull/143966.diff 3 Files Affected:
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 174a497c51b26..4aea702a702ab 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -2709,7 +2709,8 @@ The following relocation types are supported:
the ``mesa3d`` OS, which does not support ``R_AMDGPU_ABS64``.
There is no current OS loader support for 32-bit programs and so
-``R_AMDGPU_ABS32`` is not used.
+``R_AMDGPU_ABS32`` is only generated for static relocations, for example to
+implement some DWARF32 forms.
.. _amdgpu-loaded-code-object-path-uniform-resource-identifier:
diff --git a/llvm/lib/Object/RelocationResolver.cpp b/llvm/lib/Object/RelocationResolver.cpp
index 8cf748aa5681c..b6318bbe3ab74 100644
--- a/llvm/lib/Object/RelocationResolver.cpp
+++ b/llvm/lib/Object/RelocationResolver.cpp
@@ -274,11 +274,13 @@ static bool supportsAmdgpu(uint64_t Type) {
}
static uint64_t resolveAmdgpu(uint64_t Type, uint64_t Offset, uint64_t S,
- uint64_t /*LocData*/, int64_t Addend) {
+ uint64_t LocData, int64_t Addend) {
+ assert((LocData == 0 || Addend == 0) &&
+ "one of LocData and Addend must be 0");
switch (Type) {
case ELF::R_AMDGPU_ABS32:
case ELF::R_AMDGPU_ABS64:
- return S + Addend;
+ return S + LocData + Addend;
default:
llvm_unreachable("Invalid relocation type");
}
diff --git a/llvm/test/DebugInfo/AMDGPU/dwarfdump-rel.yaml b/llvm/test/DebugInfo/AMDGPU/dwarfdump-rel.yaml
new file mode 100644
index 0000000000000..23b7f087e9570
--- /dev/null
+++ b/llvm/test/DebugInfo/AMDGPU/dwarfdump-rel.yaml
@@ -0,0 +1,86 @@
+# RUN: yaml2obj %s -o %t
+# RUN: llvm-dwarfdump -i %t | FileCheck %s
+
+# Test REL relocation handling for AMDGPU
+
+# CHECK: DW_TAG_compile_unit
+# CHECK: DW_AT_producer ("dxc")
+# CHECK: DW_AT_name (".\\example.hlsl")
+# CHECK: DW_AT_str_offsets_base (0x00000008)
+
+--- !ELF
+FileHeader:
+ Class: ELFCLASS64
+ Data: ELFDATA2LSB
+ OSABI: ELFOSABI_AMDGPU_PAL
+ Type: ET_REL
+ Machine: EM_AMDGPU
+ Flags: [ EF_AMDGPU_MACH_AMDGCN_GFX1201 ]
+ SectionHeaderStringTable: .strtab
+Sections:
+ - Name: .debug_abbrev
+ Type: SHT_PROGBITS
+ AddressAlign: 0x1
+ Content: 01110125251305032572171017110B120673178C0117000000
+ - Name: .debug_info
+ Type: SHT_PROGBITS
+ AddressAlign: 0x1
+ Content: 23000000050001080000000001000400010800000000000000005C000000080000000C00000000
+ - Name: .debug_str_offsets
+ Type: SHT_PROGBITS
+ AddressAlign: 0x1
+ Content: 0C000000050000000000000004000000
+ - Name: .rel.debug_info
+ Type: SHT_REL
+ Flags: [ SHF_INFO_LINK ]
+ Link: .symtab
+ AddressAlign: 0x8
+ Info: .debug_info
+ Relocations:
+ - Offset: 0x8
+ Symbol: .debug_abbrev
+ Type: R_AMDGPU_ABS32
+ - Offset: 0x11
+ Symbol: .debug_str_offsets
+ Type: R_AMDGPU_ABS32
+ - Name: .rel.debug_str_offsets
+ Type: SHT_REL
+ Flags: [ SHF_INFO_LINK ]
+ Link: .symtab
+ AddressAlign: 0x8
+ Info: .debug_str_offsets
+ Relocations:
+ - Offset: 0x8
+ Symbol: .debug_str
+ Type: R_AMDGPU_ABS32
+ - Offset: 0xC
+ Symbol: .debug_str
+ Type: R_AMDGPU_ABS32
+ - Type: SectionHeaderTable
+ Sections:
+ - Name: .strtab
+ - Name: .debug_abbrev
+ - Name: .debug_info
+ - Name: .rel.debug_info
+ - Name: .debug_str_offsets
+ - Name: .rel.debug_str_offsets
+ - Name: .debug_str
+ - Name: .symtab
+Symbols:
+ - Name: .debug_abbrev
+ Type: STT_SECTION
+ Section: .debug_abbrev
+ - Name: .debug_info
+ Type: STT_SECTION
+ Section: .debug_info
+ - Name: .debug_str_offsets
+ Type: STT_SECTION
+ Section: .debug_str_offsets
+ - Name: .debug_str
+ Type: STT_SECTION
+ Section: .debug_str
+DWARF:
+ debug_str:
+ - 'dxc'
+ - '.\example.hlsl'
+...
|
|
Looks good, though ideally there is some description why you need REL for static relocations. REL static relocations are constrained and turned out to be a bad choice for EM_ARM |
Fair enough, is a description in the commit message OK? The rationale is just that shaders compiled with DXC/LLPC generate these relocations, and even if that changed today there are conceivably old binaries which it would be nice to handle in tooling. The friction to support it and the maintenance cost long term both seem incredibly low as well, considering other targets like ARM support both REL/RELA static relocations behind the same interface. |
MaskRay
approved these changes
Jun 14, 2025
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Shaders compiled with DXC/LLPC generate these relocations, and even if that changes in the future we want to handle existing binaries. The friction to support this and the maintenance cost long term both seem incredibly low, considering other targets like ARM support both REL/RELA static relocations behind the same interface.