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Merged
merged 1 commit into from
Jun 15, 2025
Merged

[RISCV] Remove B and Zbc extension from Andes series cpus. #144022

merged 1 commit into from
Jun 15, 2025

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tclin914
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The Andes CPU is configurable with optional extensions. The minimal required extension set does not include B and Zbc extensions. So we decided to remove them.

@llvmbot llvmbot added clang Clang issues not falling into any other category backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' labels Jun 13, 2025
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llvmbot commented Jun 13, 2025 •
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@llvm/pr-subscribers-clang-driver

@llvm/pr-subscribers-backend-risc-v

Author: Jim Lin (tclin914)

Changes

The Andes CPU is configurable with optional extensions. The minimal required extension set does not include B and Zbc extensions. So we decided to remove them.

Full diff: https://github.com/llvm/llvm-project/pull/144022.diff

7 Files Affected:

  • (modified) clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c (-5)
  • (modified) clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c (-4)
  • (modified) clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c (-5)
  • (modified) clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c (-4)
  • (modified) clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c (-4)
  • (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (-8)
  • (modified) llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s (+1-1)
diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c
index d8b3848d84520..b63800d72144a 100644
--- a/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c
+++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c
@@ -10,7 +10,6 @@
 // CHECK-NEXT:     f                    2.2       'F' (Single-Precision Floating-Point)
 // CHECK-NEXT:     d                    2.2       'D' (Double-Precision Floating-Point)
 // CHECK-NEXT:     c                    2.0       'C' (Compressed Instructions)
-// CHECK-NEXT:     b                    1.0       'B' (the collection of the Zba, Zbb, Zbs extensions)
 // CHECK-NEXT:     zicsr                2.0       'Zicsr' (CSRs)
 // CHECK-NEXT:     zifencei             2.0       'Zifencei' (fence.i)
 // CHECK-NEXT:     zmmul                1.0       'Zmmul' (Integer Multiplication)
@@ -19,10 +18,6 @@
 // CHECK-NEXT:     zca                  1.0       'Zca' (part of the C extension, excluding compressed floating point loads/stores)
 // CHECK-NEXT:     zcd                  1.0       'Zcd' (Compressed Double-Precision Floating-Point Instructions)
 // CHECK-NEXT:     zcf                  1.0       'Zcf' (Compressed Single-Precision Floating-Point Instructions)
-// CHECK-NEXT:     zba                  1.0       'Zba' (Address Generation Instructions)
-// CHECK-NEXT:     zbb                  1.0       'Zbb' (Basic Bit-Manipulation)
-// CHECK-NEXT:     zbc                  1.0       'Zbc' (Carry-Less Multiplication)
-// CHECK-NEXT:     zbs                  1.0       'Zbs' (Single-Bit Instructions)
 // CHECK-NEXT:     xandesperf           5.0       'XAndesPerf' (Andes Performance Extension)
 // CHECK-EMPTY:
 // CHECK-NEXT: Experimental extensions
diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c
index a0a1c35911409..f16228d0188d5 100644
--- a/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c
+++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c
@@ -10,7 +10,6 @@
 // CHECK-NEXT:     f                    2.2       'F' (Single-Precision Floating-Point)
 // CHECK-NEXT:     d                    2.2       'D' (Double-Precision Floating-Point)
 // CHECK-NEXT:     c                    2.0       'C' (Compressed Instructions)
-// CHECK-NEXT:     b                    1.0       'B' (the collection of the Zba, Zbb, Zbs extensions)
 // CHECK-NEXT:     zicsr                2.0       'Zicsr' (CSRs)
 // CHECK-NEXT:     zifencei             2.0       'Zifencei' (fence.i)
 // CHECK-NEXT:     zmmul                1.0       'Zmmul' (Integer Multiplication)
@@ -19,9 +18,6 @@
 // CHECK-NEXT:     zca                  1.0       'Zca' (part of the C extension, excluding compressed floating point loads/stores)
 // CHECK-NEXT:     zcd                  1.0       'Zcd' (Compressed Double-Precision Floating-Point Instructions)
 // CHECK-NEXT:     zcf                  1.0       'Zcf' (Compressed Single-Precision Floating-Point Instructions)
-// CHECK-NEXT:     zba                  1.0       'Zba' (Address Generation Instructions)
-// CHECK-NEXT:     zbb                  1.0       'Zbb' (Basic Bit-Manipulation)
-// CHECK-NEXT:     zbs                  1.0       'Zbs' (Single-Bit Instructions)
 // CHECK-NEXT:     xandesperf           5.0       'XAndesPerf' (Andes Performance Extension)
 // CHECK-EMPTY:
 // CHECK-NEXT: Experimental extensions
diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c
index 3f933ecd8ac83..424c4afbbba44 100644
--- a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c
+++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c
@@ -10,7 +10,6 @@
 // CHECK-NEXT:     f                    2.2       'F' (Single-Precision Floating-Point)
 // CHECK-NEXT:     d                    2.2       'D' (Double-Precision Floating-Point)
 // CHECK-NEXT:     c                    2.0       'C' (Compressed Instructions)
-// CHECK-NEXT:     b                    1.0       'B' (the collection of the Zba, Zbb, Zbs extensions)
 // CHECK-NEXT:     zicsr                2.0       'Zicsr' (CSRs)
 // CHECK-NEXT:     zifencei             2.0       'Zifencei' (fence.i)
 // CHECK-NEXT:     zmmul                1.0       'Zmmul' (Integer Multiplication)
@@ -18,10 +17,6 @@
 // CHECK-NEXT:     zalrsc               1.0       'Zalrsc' (Load-Reserved/Store-Conditional)
 // CHECK-NEXT:     zca                  1.0       'Zca' (part of the C extension, excluding compressed floating point loads/stores)
 // CHECK-NEXT:     zcd                  1.0       'Zcd' (Compressed Double-Precision Floating-Point Instructions)
-// CHECK-NEXT:     zba                  1.0       'Zba' (Address Generation Instructions)
-// CHECK-NEXT:     zbb                  1.0       'Zbb' (Basic Bit-Manipulation)
-// CHECK-NEXT:     zbc                  1.0       'Zbc' (Carry-Less Multiplication)
-// CHECK-NEXT:     zbs                  1.0       'Zbs' (Single-Bit Instructions)
 // CHECK-NEXT:     xandesperf           5.0       'XAndesPerf' (Andes Performance Extension)
 // CHECK-EMPTY:
 // CHECK-NEXT: Experimental extensions
diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c
index 6460d701411bc..c00cc60640f62 100644
--- a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c
+++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c
@@ -10,7 +10,6 @@
 // CHECK-NEXT:     f                    2.2       'F' (Single-Precision Floating-Point)
 // CHECK-NEXT:     d                    2.2       'D' (Double-Precision Floating-Point)
 // CHECK-NEXT:     c                    2.0       'C' (Compressed Instructions)
-// CHECK-NEXT:     b                    1.0       'B' (the collection of the Zba, Zbb, Zbs extensions)
 // CHECK-NEXT:     zicsr                2.0       'Zicsr' (CSRs)
 // CHECK-NEXT:     zifencei             2.0       'Zifencei' (fence.i)
 // CHECK-NEXT:     zmmul                1.0       'Zmmul' (Integer Multiplication)
@@ -18,9 +17,6 @@
 // CHECK-NEXT:     zalrsc               1.0       'Zalrsc' (Load-Reserved/Store-Conditional)
 // CHECK-NEXT:     zca                  1.0       'Zca' (part of the C extension, excluding compressed floating point loads/stores)
 // CHECK-NEXT:     zcd                  1.0       'Zcd' (Compressed Double-Precision Floating-Point Instructions)
-// CHECK-NEXT:     zba                  1.0       'Zba' (Address Generation Instructions)
-// CHECK-NEXT:     zbb                  1.0       'Zbb' (Basic Bit-Manipulation)
-// CHECK-NEXT:     zbs                  1.0       'Zbs' (Single-Bit Instructions)
 // CHECK-NEXT:     xandesperf           5.0       'XAndesPerf' (Andes Performance Extension)
 // CHECK-EMPTY:
 // CHECK-NEXT: Experimental extensions
diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c
index 4d9c514b756e6..7dc1383c9666a 100644
--- a/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c
+++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c
@@ -10,7 +10,6 @@
 // CHECK-NEXT:     f                    2.2       'F' (Single-Precision Floating-Point)
 // CHECK-NEXT:     d                    2.2       'D' (Double-Precision Floating-Point)
 // CHECK-NEXT:     c                    2.0       'C' (Compressed Instructions)
-// CHECK-NEXT:     b                    1.0       'B' (the collection of the Zba, Zbb, Zbs extensions)
 // CHECK-NEXT:     zicsr                2.0       'Zicsr' (CSRs)
 // CHECK-NEXT:     zifencei             2.0       'Zifencei' (fence.i)
 // CHECK-NEXT:     zmmul                1.0       'Zmmul' (Integer Multiplication)
@@ -19,9 +18,6 @@
 // CHECK-NEXT:     zca                  1.0       'Zca' (part of the C extension, excluding compressed floating point loads/stores)
 // CHECK-NEXT:     zcd                  1.0       'Zcd' (Compressed Double-Precision Floating-Point Instructions)
 // CHECK-NEXT:     zcf                  1.0       'Zcf' (Compressed Single-Precision Floating-Point Instructions)
-// CHECK-NEXT:     zba                  1.0       'Zba' (Address Generation Instructions)
-// CHECK-NEXT:     zbb                  1.0       'Zbb' (Basic Bit-Manipulation)
-// CHECK-NEXT:     zbs                  1.0       'Zbs' (Single-Bit Instructions)
 // CHECK-NEXT:     xandesperf           5.0       'XAndesPerf' (Andes Performance Extension)
 // CHECK-EMPTY:
 // CHECK-NEXT: Experimental extensions
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index de6f0ecfce737..ea353a44fed41 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -703,8 +703,6 @@ def ANDES_A25 : RISCVProcessorModel<"andes-a25",
                                      FeatureStdExtF,
                                      FeatureStdExtD,
                                      FeatureStdExtC,
-                                     FeatureStdExtB,
-                                     FeatureStdExtZbc,
                                      FeatureVendorXAndesPerf]>;
 
 def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
@@ -718,8 +716,6 @@ def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
                                       FeatureStdExtF,
                                       FeatureStdExtD,
                                       FeatureStdExtC,
-                                      FeatureStdExtB,
-                                      FeatureStdExtZbc,
                                       FeatureVendorXAndesPerf]>;
 
 def ANDES_45 : RISCVTuneProcessorModel<"andes-45-series",
@@ -736,7 +732,6 @@ def ANDES_N45 : RISCVProcessorModel<"andes-n45",
                                      FeatureStdExtF,
                                      FeatureStdExtD,
                                      FeatureStdExtC,
-                                     FeatureStdExtB,
                                      FeatureVendorXAndesPerf]>;
 
 def ANDES_NX45 : RISCVProcessorModel<"andes-nx45",
@@ -750,7 +745,6 @@ def ANDES_NX45 : RISCVProcessorModel<"andes-nx45",
                                       FeatureStdExtF,
                                       FeatureStdExtD,
                                       FeatureStdExtC,
-                                      FeatureStdExtB,
                                       FeatureVendorXAndesPerf]>;
 
 def ANDES_A45 : RISCVProcessorModel<"andes-a45",
@@ -764,7 +758,6 @@ def ANDES_A45 : RISCVProcessorModel<"andes-a45",
                                      FeatureStdExtF,
                                      FeatureStdExtD,
                                      FeatureStdExtC,
-                                     FeatureStdExtB,
                                      FeatureVendorXAndesPerf]>;
 
 def ANDES_AX45 : RISCVProcessorModel<"andes-ax45",
@@ -778,5 +771,4 @@ def ANDES_AX45 : RISCVProcessorModel<"andes-ax45",
                                       FeatureStdExtF,
                                       FeatureStdExtD,
                                       FeatureStdExtC,
-                                      FeatureStdExtB,
                                       FeatureVendorXAndesPerf]>;
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s
index f6dc6eef3f0ff..d90dce8c5c3fc 100644
--- a/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-nx45 -mattr=+zbc -timeline -iterations=1 < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-nx45 -mattr=+b,+zbc -timeline -iterations=1 < %s | FileCheck %s
 
 # Two ALUs without dependency can be dispatched in the same cycle.
 add a0, a0, a0

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llvmbot commented Jun 13, 2025

@llvm/pr-subscribers-clang

Author: Jim Lin (tclin914)

Changes

The Andes CPU is configurable with optional extensions. The minimal required extension set does not include B and Zbc extensions. So we decided to remove them.

Full diff: https://github.com/llvm/llvm-project/pull/144022.diff

7 Files Affected:

  • (modified) clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c (-5)
  • (modified) clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c (-4)
  • (modified) clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c (-5)
  • (modified) clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c (-4)
  • (modified) clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c (-4)
  • (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (-8)
  • (modified) llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s (+1-1)
diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c
index d8b3848d84520..b63800d72144a 100644
--- a/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c
+++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c
@@ -10,7 +10,6 @@
 // CHECK-NEXT:     f                    2.2       'F' (Single-Precision Floating-Point)
 // CHECK-NEXT:     d                    2.2       'D' (Double-Precision Floating-Point)
 // CHECK-NEXT:     c                    2.0       'C' (Compressed Instructions)
-// CHECK-NEXT:     b                    1.0       'B' (the collection of the Zba, Zbb, Zbs extensions)
 // CHECK-NEXT:     zicsr                2.0       'Zicsr' (CSRs)
 // CHECK-NEXT:     zifencei             2.0       'Zifencei' (fence.i)
 // CHECK-NEXT:     zmmul                1.0       'Zmmul' (Integer Multiplication)
@@ -19,10 +18,6 @@
 // CHECK-NEXT:     zca                  1.0       'Zca' (part of the C extension, excluding compressed floating point loads/stores)
 // CHECK-NEXT:     zcd                  1.0       'Zcd' (Compressed Double-Precision Floating-Point Instructions)
 // CHECK-NEXT:     zcf                  1.0       'Zcf' (Compressed Single-Precision Floating-Point Instructions)
-// CHECK-NEXT:     zba                  1.0       'Zba' (Address Generation Instructions)
-// CHECK-NEXT:     zbb                  1.0       'Zbb' (Basic Bit-Manipulation)
-// CHECK-NEXT:     zbc                  1.0       'Zbc' (Carry-Less Multiplication)
-// CHECK-NEXT:     zbs                  1.0       'Zbs' (Single-Bit Instructions)
 // CHECK-NEXT:     xandesperf           5.0       'XAndesPerf' (Andes Performance Extension)
 // CHECK-EMPTY:
 // CHECK-NEXT: Experimental extensions
diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c
index a0a1c35911409..f16228d0188d5 100644
--- a/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c
+++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c
@@ -10,7 +10,6 @@
 // CHECK-NEXT:     f                    2.2       'F' (Single-Precision Floating-Point)
 // CHECK-NEXT:     d                    2.2       'D' (Double-Precision Floating-Point)
 // CHECK-NEXT:     c                    2.0       'C' (Compressed Instructions)
-// CHECK-NEXT:     b                    1.0       'B' (the collection of the Zba, Zbb, Zbs extensions)
 // CHECK-NEXT:     zicsr                2.0       'Zicsr' (CSRs)
 // CHECK-NEXT:     zifencei             2.0       'Zifencei' (fence.i)
 // CHECK-NEXT:     zmmul                1.0       'Zmmul' (Integer Multiplication)
@@ -19,9 +18,6 @@
 // CHECK-NEXT:     zca                  1.0       'Zca' (part of the C extension, excluding compressed floating point loads/stores)
 // CHECK-NEXT:     zcd                  1.0       'Zcd' (Compressed Double-Precision Floating-Point Instructions)
 // CHECK-NEXT:     zcf                  1.0       'Zcf' (Compressed Single-Precision Floating-Point Instructions)
-// CHECK-NEXT:     zba                  1.0       'Zba' (Address Generation Instructions)
-// CHECK-NEXT:     zbb                  1.0       'Zbb' (Basic Bit-Manipulation)
-// CHECK-NEXT:     zbs                  1.0       'Zbs' (Single-Bit Instructions)
 // CHECK-NEXT:     xandesperf           5.0       'XAndesPerf' (Andes Performance Extension)
 // CHECK-EMPTY:
 // CHECK-NEXT: Experimental extensions
diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c
index 3f933ecd8ac83..424c4afbbba44 100644
--- a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c
+++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c
@@ -10,7 +10,6 @@
 // CHECK-NEXT:     f                    2.2       'F' (Single-Precision Floating-Point)
 // CHECK-NEXT:     d                    2.2       'D' (Double-Precision Floating-Point)
 // CHECK-NEXT:     c                    2.0       'C' (Compressed Instructions)
-// CHECK-NEXT:     b                    1.0       'B' (the collection of the Zba, Zbb, Zbs extensions)
 // CHECK-NEXT:     zicsr                2.0       'Zicsr' (CSRs)
 // CHECK-NEXT:     zifencei             2.0       'Zifencei' (fence.i)
 // CHECK-NEXT:     zmmul                1.0       'Zmmul' (Integer Multiplication)
@@ -18,10 +17,6 @@
 // CHECK-NEXT:     zalrsc               1.0       'Zalrsc' (Load-Reserved/Store-Conditional)
 // CHECK-NEXT:     zca                  1.0       'Zca' (part of the C extension, excluding compressed floating point loads/stores)
 // CHECK-NEXT:     zcd                  1.0       'Zcd' (Compressed Double-Precision Floating-Point Instructions)
-// CHECK-NEXT:     zba                  1.0       'Zba' (Address Generation Instructions)
-// CHECK-NEXT:     zbb                  1.0       'Zbb' (Basic Bit-Manipulation)
-// CHECK-NEXT:     zbc                  1.0       'Zbc' (Carry-Less Multiplication)
-// CHECK-NEXT:     zbs                  1.0       'Zbs' (Single-Bit Instructions)
 // CHECK-NEXT:     xandesperf           5.0       'XAndesPerf' (Andes Performance Extension)
 // CHECK-EMPTY:
 // CHECK-NEXT: Experimental extensions
diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c
index 6460d701411bc..c00cc60640f62 100644
--- a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c
+++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c
@@ -10,7 +10,6 @@
 // CHECK-NEXT:     f                    2.2       'F' (Single-Precision Floating-Point)
 // CHECK-NEXT:     d                    2.2       'D' (Double-Precision Floating-Point)
 // CHECK-NEXT:     c                    2.0       'C' (Compressed Instructions)
-// CHECK-NEXT:     b                    1.0       'B' (the collection of the Zba, Zbb, Zbs extensions)
 // CHECK-NEXT:     zicsr                2.0       'Zicsr' (CSRs)
 // CHECK-NEXT:     zifencei             2.0       'Zifencei' (fence.i)
 // CHECK-NEXT:     zmmul                1.0       'Zmmul' (Integer Multiplication)
@@ -18,9 +17,6 @@
 // CHECK-NEXT:     zalrsc               1.0       'Zalrsc' (Load-Reserved/Store-Conditional)
 // CHECK-NEXT:     zca                  1.0       'Zca' (part of the C extension, excluding compressed floating point loads/stores)
 // CHECK-NEXT:     zcd                  1.0       'Zcd' (Compressed Double-Precision Floating-Point Instructions)
-// CHECK-NEXT:     zba                  1.0       'Zba' (Address Generation Instructions)
-// CHECK-NEXT:     zbb                  1.0       'Zbb' (Basic Bit-Manipulation)
-// CHECK-NEXT:     zbs                  1.0       'Zbs' (Single-Bit Instructions)
 // CHECK-NEXT:     xandesperf           5.0       'XAndesPerf' (Andes Performance Extension)
 // CHECK-EMPTY:
 // CHECK-NEXT: Experimental extensions
diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c
index 4d9c514b756e6..7dc1383c9666a 100644
--- a/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c
+++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c
@@ -10,7 +10,6 @@
 // CHECK-NEXT:     f                    2.2       'F' (Single-Precision Floating-Point)
 // CHECK-NEXT:     d                    2.2       'D' (Double-Precision Floating-Point)
 // CHECK-NEXT:     c                    2.0       'C' (Compressed Instructions)
-// CHECK-NEXT:     b                    1.0       'B' (the collection of the Zba, Zbb, Zbs extensions)
 // CHECK-NEXT:     zicsr                2.0       'Zicsr' (CSRs)
 // CHECK-NEXT:     zifencei             2.0       'Zifencei' (fence.i)
 // CHECK-NEXT:     zmmul                1.0       'Zmmul' (Integer Multiplication)
@@ -19,9 +18,6 @@
 // CHECK-NEXT:     zca                  1.0       'Zca' (part of the C extension, excluding compressed floating point loads/stores)
 // CHECK-NEXT:     zcd                  1.0       'Zcd' (Compressed Double-Precision Floating-Point Instructions)
 // CHECK-NEXT:     zcf                  1.0       'Zcf' (Compressed Single-Precision Floating-Point Instructions)
-// CHECK-NEXT:     zba                  1.0       'Zba' (Address Generation Instructions)
-// CHECK-NEXT:     zbb                  1.0       'Zbb' (Basic Bit-Manipulation)
-// CHECK-NEXT:     zbs                  1.0       'Zbs' (Single-Bit Instructions)
 // CHECK-NEXT:     xandesperf           5.0       'XAndesPerf' (Andes Performance Extension)
 // CHECK-EMPTY:
 // CHECK-NEXT: Experimental extensions
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index de6f0ecfce737..ea353a44fed41 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -703,8 +703,6 @@ def ANDES_A25 : RISCVProcessorModel<"andes-a25",
                                      FeatureStdExtF,
                                      FeatureStdExtD,
                                      FeatureStdExtC,
-                                     FeatureStdExtB,
-                                     FeatureStdExtZbc,
                                      FeatureVendorXAndesPerf]>;
 
 def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
@@ -718,8 +716,6 @@ def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
                                       FeatureStdExtF,
                                       FeatureStdExtD,
                                       FeatureStdExtC,
-                                      FeatureStdExtB,
-                                      FeatureStdExtZbc,
                                       FeatureVendorXAndesPerf]>;
 
 def ANDES_45 : RISCVTuneProcessorModel<"andes-45-series",
@@ -736,7 +732,6 @@ def ANDES_N45 : RISCVProcessorModel<"andes-n45",
                                      FeatureStdExtF,
                                      FeatureStdExtD,
                                      FeatureStdExtC,
-                                     FeatureStdExtB,
                                      FeatureVendorXAndesPerf]>;
 
 def ANDES_NX45 : RISCVProcessorModel<"andes-nx45",
@@ -750,7 +745,6 @@ def ANDES_NX45 : RISCVProcessorModel<"andes-nx45",
                                       FeatureStdExtF,
                                       FeatureStdExtD,
                                       FeatureStdExtC,
-                                      FeatureStdExtB,
                                       FeatureVendorXAndesPerf]>;
 
 def ANDES_A45 : RISCVProcessorModel<"andes-a45",
@@ -764,7 +758,6 @@ def ANDES_A45 : RISCVProcessorModel<"andes-a45",
                                      FeatureStdExtF,
                                      FeatureStdExtD,
                                      FeatureStdExtC,
-                                     FeatureStdExtB,
                                      FeatureVendorXAndesPerf]>;
 
 def ANDES_AX45 : RISCVProcessorModel<"andes-ax45",
@@ -778,5 +771,4 @@ def ANDES_AX45 : RISCVProcessorModel<"andes-ax45",
                                       FeatureStdExtF,
                                       FeatureStdExtD,
                                       FeatureStdExtC,
-                                      FeatureStdExtB,
                                       FeatureVendorXAndesPerf]>;
diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s
index f6dc6eef3f0ff..d90dce8c5c3fc 100644
--- a/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s
+++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-nx45 -mattr=+zbc -timeline -iterations=1 < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-nx45 -mattr=+b,+zbc -timeline -iterations=1 < %s | FileCheck %s
 
 # Two ALUs without dependency can be dispatched in the same cycle.
 add a0, a0, a0

@tclin914 tclin914 force-pushed the andes-remove-b-extension branch from 3ac3e3e to f1fdf9d Compare June 13, 2025 06:11
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Not related to this PR, but I'd like to raise the question here:

For configurable cores, what is the best way to specify the features? -mcpu is meant to support the base configuration, but how can we specify the additional optional extensions? Apparently, failing back to -march is silly.

My thought is: can we support -march/-mcpu where the values can be {cpu}(_ext)*? Will such use be problematic?

@lenary
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lenary commented Jun 13, 2025

I think this feature is really tough, the arm/aarch64 backends have got too much complexity from similar features, mostly because their cpus have all their optional features enabled by default.

I think if you can only enable additional extensions, that proposed syntax would probably work.

Previously, we mostly punted on this for e.g. hazard3, by only adding a -mcpu= option for what was actually taped out, rather than adding the configurable option. I don't know how that works for sifive/andes products that are also configurable.

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topperc commented Jun 13, 2025 •
edited
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I think this feature is really tough, the arm/aarch64 backends have got too much complexity from similar features, mostly because their cpus have all their optional features enabled by default.

I think if you can only enable additional extensions, that proposed syntax would probably work.

Previously, we mostly punted on this for e.g. hazard3, by only adding a -mcpu= option for what was actually taped out, rather than adding the configurable option. I don't know how that works for sifive/andes products that are also configurable.

The SiFive processors in LLVM are closer to a "standard" or most common configuration than a "minimal" configuration.

@tclin914
[RISCV] Remove B and Zbc extension from Andes series cpus.
9ac0064 
The Andes CPU is configurable with optional extensions. The minimal
required extension set does not include `B` and `Zbc` extensions.
So we decided to remove them.
@tclin914
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Not related to this PR, but I'd like to raise the question here:

For configurable cores, what is the best way to specify the features? -mcpu is meant to support the base configuration, but how can we specify the additional optional extensions? Apparently, failing back to -march is silly.

My thought is: can we support -march/-mcpu where the values can be {cpu}(_ext)*? Will such use be problematic?

Unfortunately, we have to suggest our users to specify both -march and -mcpu when their processor includes additional optional extensions. Ideally, we hope that code generated using -mcpu alone would always be compatible with processors that have varying configurations.

@tclin914 tclin914 force-pushed the andes-remove-b-extension branch from f1fdf9d to 9ac0064 Compare June 15, 2025 03:37
@tclin914 tclin914 merged commit 24c8d90 into llvm:main Jun 15, 2025
5 of 7 checks passed
@tclin914 tclin914 deleted the andes-remove-b-extension branch June 15, 2025 03:38
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llvm-ci commented Jun 15, 2025

LLVM Buildbot has detected a new failure on builder clang-x64-windows-msvc running on windows-gcebot2 while building clang,llvm at step 4 "annotate".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/63/builds/7094

Here is the relevant piece of the build log for the reference 
Step 4 (annotate) failure: 'python ../llvm-zorg/zorg/buildbot/builders/annotated/clang-windows.py ...' (failure)
...
[79/81] Running the Clang regression tests
llvm-lit.py: C:\b\slave\clang-x64-windows-msvc\llvm-project\llvm\utils\lit\lit\llvm\config.py:57: note: using lit tools: C:\Program Files\Git\usr\bin
llvm-lit.py: C:\b\slave\clang-x64-windows-msvc\llvm-project\llvm\utils\lit\lit\llvm\config.py:520: note: using clang: c:\b\slave\clang-x64-windows-msvc\build\stage1\bin\clang.exe
llvm-lit.py: C:\b\slave\clang-x64-windows-msvc\llvm-project\llvm\utils\lit\lit\llvm\subst.py:126: note: Did not find cir-opt in C:\b\slave\clang-x64-windows-msvc\build\stage1\bin;C:\b\slave\clang-x64-windows-msvc\build\stage1\bin
llvm-lit.py: C:\b\slave\clang-x64-windows-msvc\llvm-project\llvm\utils\lit\lit\llvm\config.py:520: note: using ld.lld: c:\b\slave\clang-x64-windows-msvc\build\stage1\bin\ld.lld.exe
llvm-lit.py: C:\b\slave\clang-x64-windows-msvc\llvm-project\llvm\utils\lit\lit\llvm\config.py:520: note: using lld-link: c:\b\slave\clang-x64-windows-msvc\build\stage1\bin\lld-link.exe
llvm-lit.py: C:\b\slave\clang-x64-windows-msvc\llvm-project\llvm\utils\lit\lit\llvm\config.py:520: note: using ld64.lld: c:\b\slave\clang-x64-windows-msvc\build\stage1\bin\ld64.lld.exe
llvm-lit.py: C:\b\slave\clang-x64-windows-msvc\llvm-project\llvm\utils\lit\lit\llvm\config.py:520: note: using wasm-ld: c:\b\slave\clang-x64-windows-msvc\build\stage1\bin\wasm-ld.exe
-- Testing: 22233 tests, 32 workers --
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: Driver/print-enabled-extensions/riscv-andes-ax45.c (17393 of 22233)
******************** TEST 'Clang :: Driver/print-enabled-extensions/riscv-andes-ax45.c' FAILED ********************
Exit Code: 1

Command Output (stdout):
--
# RUN: at line 1
c:\b\slave\clang-x64-windows-msvc\build\stage1\bin\clang.exe --target=riscv64 -mcpu=andes-ax45 --print-enabled-extensions | c:\b\slave\clang-x64-windows-msvc\build\stage1\bin\filecheck.exe C:\b\slave\clang-x64-windows-msvc\llvm-project\clang\test\Driver\print-enabled-extensions\riscv-andes-ax45.c
# executed command: 'c:\b\slave\clang-x64-windows-msvc\build\stage1\bin\clang.exe' --target=riscv64 -mcpu=andes-ax45 --print-enabled-extensions
# .---command stderr------------
# | clang version 21.0.0git (https://github.com/llvm/llvm-project.git 24c8d900c47edeefb85643a06bc32235d9f42ea3)
# | Target: riscv64--
# | Thread model: posix
# | InstalledDir: C:\b\slave\clang-x64-windows-msvc\build\stage1\bin
# `-----------------------------
# executed command: 'c:\b\slave\clang-x64-windows-msvc\build\stage1\bin\filecheck.exe' 'C:\b\slave\clang-x64-windows-msvc\llvm-project\clang\test\Driver\print-enabled-extensions\riscv-andes-ax45.c'
# .---command stderr------------
# | C:\b\slave\clang-x64-windows-msvc\llvm-project\clang\test\Driver\print-enabled-extensions\riscv-andes-ax45.c:13:16: error: CHECK-NEXT: is not on the line after the previous match
# | // CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
# |                ^
# | <stdin>:11:2: note: 'next' match was here
# |  zicsr 2.0 'Zicsr' (CSRs)
# |  ^
# | <stdin>:9:37: note: previous match ended here
# |  c 2.0 'C' (Compressed Instructions)
# |                                     ^
# | <stdin>:10:1: note: non-matching line after previous match is here
# |  b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
# | ^
# | 
# | Input file: <stdin>
# | Check file: C:\b\slave\clang-x64-windows-msvc\llvm-project\clang\test\Driver\print-enabled-extensions\riscv-andes-ax45.c
# | 
# | -dump-input=help explains the following input dump.
# | 
# | Input was:
# | <<<<<<
# |          .
# |          .
Step 8 (stage 1 check) failure: stage 1 check (failure)
...
[79/81] Running the Clang regression tests
llvm-lit.py: C:\b\slave\clang-x64-windows-msvc\llvm-project\llvm\utils\lit\lit\llvm\config.py:57: note: using lit tools: C:\Program Files\Git\usr\bin
llvm-lit.py: C:\b\slave\clang-x64-windows-msvc\llvm-project\llvm\utils\lit\lit\llvm\config.py:520: note: using clang: c:\b\slave\clang-x64-windows-msvc\build\stage1\bin\clang.exe
llvm-lit.py: C:\b\slave\clang-x64-windows-msvc\llvm-project\llvm\utils\lit\lit\llvm\subst.py:126: note: Did not find cir-opt in C:\b\slave\clang-x64-windows-msvc\build\stage1\bin;C:\b\slave\clang-x64-windows-msvc\build\stage1\bin
llvm-lit.py: C:\b\slave\clang-x64-windows-msvc\llvm-project\llvm\utils\lit\lit\llvm\config.py:520: note: using ld.lld: c:\b\slave\clang-x64-windows-msvc\build\stage1\bin\ld.lld.exe
llvm-lit.py: C:\b\slave\clang-x64-windows-msvc\llvm-project\llvm\utils\lit\lit\llvm\config.py:520: note: using lld-link: c:\b\slave\clang-x64-windows-msvc\build\stage1\bin\lld-link.exe
llvm-lit.py: C:\b\slave\clang-x64-windows-msvc\llvm-project\llvm\utils\lit\lit\llvm\config.py:520: note: using ld64.lld: c:\b\slave\clang-x64-windows-msvc\build\stage1\bin\ld64.lld.exe
llvm-lit.py: C:\b\slave\clang-x64-windows-msvc\llvm-project\llvm\utils\lit\lit\llvm\config.py:520: note: using wasm-ld: c:\b\slave\clang-x64-windows-msvc\build\stage1\bin\wasm-ld.exe
-- Testing: 22233 tests, 32 workers --
Testing:  0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90
FAIL: Clang :: Driver/print-enabled-extensions/riscv-andes-ax45.c (17393 of 22233)
******************** TEST 'Clang :: Driver/print-enabled-extensions/riscv-andes-ax45.c' FAILED ********************
Exit Code: 1

Command Output (stdout):
--
# RUN: at line 1
c:\b\slave\clang-x64-windows-msvc\build\stage1\bin\clang.exe --target=riscv64 -mcpu=andes-ax45 --print-enabled-extensions | c:\b\slave\clang-x64-windows-msvc\build\stage1\bin\filecheck.exe C:\b\slave\clang-x64-windows-msvc\llvm-project\clang\test\Driver\print-enabled-extensions\riscv-andes-ax45.c
# executed command: 'c:\b\slave\clang-x64-windows-msvc\build\stage1\bin\clang.exe' --target=riscv64 -mcpu=andes-ax45 --print-enabled-extensions
# .---command stderr------------
# | clang version 21.0.0git (https://github.com/llvm/llvm-project.git 24c8d900c47edeefb85643a06bc32235d9f42ea3)
# | Target: riscv64--
# | Thread model: posix
# | InstalledDir: C:\b\slave\clang-x64-windows-msvc\build\stage1\bin
# `-----------------------------
# executed command: 'c:\b\slave\clang-x64-windows-msvc\build\stage1\bin\filecheck.exe' 'C:\b\slave\clang-x64-windows-msvc\llvm-project\clang\test\Driver\print-enabled-extensions\riscv-andes-ax45.c'
# .---command stderr------------
# | C:\b\slave\clang-x64-windows-msvc\llvm-project\clang\test\Driver\print-enabled-extensions\riscv-andes-ax45.c:13:16: error: CHECK-NEXT: is not on the line after the previous match
# | // CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
# |                ^
# | <stdin>:11:2: note: 'next' match was here
# |  zicsr 2.0 'Zicsr' (CSRs)
# |  ^
# | <stdin>:9:37: note: previous match ended here
# |  c 2.0 'C' (Compressed Instructions)
# |                                     ^
# | <stdin>:10:1: note: non-matching line after previous match is here
# |  b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
# | ^
# | 
# | Input file: <stdin>
# | Check file: C:\b\slave\clang-x64-windows-msvc\llvm-project\clang\test\Driver\print-enabled-extensions\riscv-andes-ax45.c
# | 
# | -dump-input=help explains the following input dump.
# | 
# | Input was:
# | <<<<<<
# |          .
# |          .

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llvm-ci commented Jun 15, 2025

LLVM Buildbot has detected a new failure on builder clang-s390x-linux running on systemz-1 while building clang,llvm at step 5 "ninja check 1".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/42/builds/4981

Here is the relevant piece of the build log for the reference 
Step 5 (ninja check 1) failure: stage 1 checked (failure)
******************** TEST 'Clang :: Driver/print-enabled-extensions/riscv-andes-a45.c' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
/home/uweigand/sandbox/buildbot/clang-s390x-linux/stage1/bin/clang --target=riscv32 -mcpu=andes-a45 --print-enabled-extensions | /home/uweigand/sandbox/buildbot/clang-s390x-linux/stage1/bin/FileCheck /home/uweigand/sandbox/buildbot/clang-s390x-linux/llvm/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c # RUN: at line 1
+ /home/uweigand/sandbox/buildbot/clang-s390x-linux/stage1/bin/FileCheck /home/uweigand/sandbox/buildbot/clang-s390x-linux/llvm/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c
+ /home/uweigand/sandbox/buildbot/clang-s390x-linux/stage1/bin/clang --target=riscv32 -mcpu=andes-a45 --print-enabled-extensions
clang version 21.0.0git (https://github.com/llvm/llvm-project.git 24c8d900c47edeefb85643a06bc32235d9f42ea3)
Target: riscv32--
Thread model: posix
InstalledDir: /home/uweigand/sandbox/buildbot/clang-s390x-linux/stage1/bin
Build config: +assertions
/home/uweigand/sandbox/buildbot/clang-s390x-linux/llvm/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c:13:16: error: CHECK-NEXT: is not on the line after the previous match
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
               ^
<stdin>:11:2: note: 'next' match was here
 zicsr 2.0 'Zicsr' (CSRs)
 ^
<stdin>:9:37: note: previous match ended here
 c 2.0 'C' (Compressed Instructions)
                                    ^
<stdin>:10:1: note: non-matching line after previous match is here
 b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
^

Input file: <stdin>
Check file: /home/uweigand/sandbox/buildbot/clang-s390x-linux/llvm/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c

-dump-input=help explains the following input dump.

Input was:
<<<<<<
         .
         .
         .
         6:  a 2.1 'A' (Atomic Instructions) 
         7:  f 2.2 'F' (Single-Precision Floating-Point) 
         8:  d 2.2 'D' (Double-Precision Floating-Point) 
         9:  c 2.0 'C' (Compressed Instructions) 
        10:  b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) 
        11:  zicsr 2.0 'Zicsr' (CSRs) 
next:13      !~~~~~~~~~~~~~~~~~~~~~~~  error: match on wrong line
        12:  zifencei 2.0 'Zifencei' (fence.i) 
        13:  zmmul 1.0 'Zmmul' (Integer Multiplication) 
        14:  zaamo 1.0 'Zaamo' (Atomic Memory Operations) 
        15:  zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional) 
        16:  zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores) 
         .
         .
...

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llvm-ci commented Jun 15, 2025

LLVM Buildbot has detected a new failure on builder clang-s390x-linux-lnt running on systemz-1 while building clang,llvm at step 7 "ninja check 1".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/136/builds/4265

Here is the relevant piece of the build log for the reference 
Step 7 (ninja check 1) failure: stage 1 checked (failure)
******************** TEST 'Clang :: Driver/print-enabled-extensions/riscv-andes-a45.c' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
/home/uweigand/sandbox/buildbot/clang-s390x-linux-lnt/stage1/bin/clang --target=riscv32 -mcpu=andes-a45 --print-enabled-extensions | /home/uweigand/sandbox/buildbot/clang-s390x-linux-lnt/stage1/bin/FileCheck /home/uweigand/sandbox/buildbot/clang-s390x-linux-lnt/llvm/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c # RUN: at line 1
+ /home/uweigand/sandbox/buildbot/clang-s390x-linux-lnt/stage1/bin/clang --target=riscv32 -mcpu=andes-a45 --print-enabled-extensions
+ /home/uweigand/sandbox/buildbot/clang-s390x-linux-lnt/stage1/bin/FileCheck /home/uweigand/sandbox/buildbot/clang-s390x-linux-lnt/llvm/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c
clang version 21.0.0git (https://github.com/llvm/llvm-project.git 24c8d900c47edeefb85643a06bc32235d9f42ea3)
Target: riscv32--
Thread model: posix
InstalledDir: /home/uweigand/sandbox/buildbot/clang-s390x-linux-lnt/stage1/bin
Build config: +assertions
/home/uweigand/sandbox/buildbot/clang-s390x-linux-lnt/llvm/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c:13:16: error: CHECK-NEXT: is not on the line after the previous match
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
               ^
<stdin>:11:2: note: 'next' match was here
 zicsr 2.0 'Zicsr' (CSRs)
 ^
<stdin>:9:37: note: previous match ended here
 c 2.0 'C' (Compressed Instructions)
                                    ^
<stdin>:10:1: note: non-matching line after previous match is here
 b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
^

Input file: <stdin>
Check file: /home/uweigand/sandbox/buildbot/clang-s390x-linux-lnt/llvm/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c

-dump-input=help explains the following input dump.

Input was:
<<<<<<
         .
         .
         .
         6:  a 2.1 'A' (Atomic Instructions) 
         7:  f 2.2 'F' (Single-Precision Floating-Point) 
         8:  d 2.2 'D' (Double-Precision Floating-Point) 
         9:  c 2.0 'C' (Compressed Instructions) 
        10:  b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) 
        11:  zicsr 2.0 'Zicsr' (CSRs) 
next:13      !~~~~~~~~~~~~~~~~~~~~~~~  error: match on wrong line
        12:  zifencei 2.0 'Zifencei' (fence.i) 
        13:  zmmul 1.0 'Zmmul' (Integer Multiplication) 
        14:  zaamo 1.0 'Zaamo' (Atomic Memory Operations) 
        15:  zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional) 
        16:  zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores) 
         .
         .
...

@lenary
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lenary commented Jun 15, 2025

Not related to this PR, but I'd like to raise the question here:
For configurable cores, what is the best way to specify the features? -mcpu is meant to support the base configuration, but how can we specify the additional optional extensions? Apparently, failing back to -march is silly.
My thought is: can we support -march/-mcpu where the values can be {cpu}(_ext)*? Will such use be problematic?

Unfortunately, we have to suggest our users to specify both -march and -mcpu when their processor includes additional optional extensions. Ideally, we hope that code generated using -mcpu alone would always be compatible with processors that have varying configurations.

This is the same trade-off that I would choose, but I understand why others have gone a different way.

My hope would be that the combination of -march= and -mtune= would be equivalent to -mcpu=, so if you added more features to -march=, you'd still get the code generation you want (scheduling, optimisations, etc) but also the additional instructions that you asked for. I think we've worked out how to model this well in the RISC-V backend, but I haven't examined how -mtune= is treated fully.

@topperc
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topperc commented Jun 15, 2025

Not related to this PR, but I'd like to raise the question here:

For configurable cores, what is the best way to specify the features? -mcpu is meant to support the base configuration, but how can we specify the additional optional extensions? Apparently, failing back to -march is silly.

My thought is: can we support -march/-mcpu where the values can be {cpu}(_ext)*? Will such use be problematic?

Unfortunately, we have to suggest our users to specify both -march and -mcpu when their processor includes additional optional extensions. Ideally, we hope that code generated using -mcpu alone would always be compatible with processors that have varying configurations.

This is the same trade-off that I would choose, but I understand why others have gone a different way.

X86 has a similar issue. -march=haswell enables AVX2, but the cheaper haswell CPUs branded as Pentium instead of Core, don't support AVX2.

My hope would be that the combination of -march= and -mtune= would be equivalent to -mcpu=, so if you added more features to -march=, you'd still get the code generation you want (scheduling, optimisations, etc) but also the additional instructions that you asked for. I think we've worked out how to model this well in the RISC-V backend, but I haven't examined how -mtune= is treated fully.

There are some mcpu that we enable unaligned memory access for but there is no equivalent march+mtune. You have to use the no-strict-align options too.

AaronBallman added a commit that referenced this pull request Jun 16, 2025
@AaronBallman
Revert "[RISCV] Remove B and Zbc extension from Andes series cpus. (#…
d644265 
…144022)"

This reverts commit 24c8d90.
@AaronBallman AaronBallman mentioned this pull request Jun 16, 2025
Merged
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This has been failing post-commit CI for two days, so I've put up a patch to revert the changes: #144402

AaronBallman added a commit that referenced this pull request Jun 16, 2025
@AaronBallman
Revert "[RISCV] Remove B and Zbc extension from Andes series cpus." (#…
f83d09a 
…144402)

Reverts #144022

This has been failing postcommit CI for two days:
https://lab.llvm.org/buildbot/#/builders/63
llvm-sync bot pushed a commit to arm/arm-toolchain that referenced this pull request Jun 16, 2025
@AaronBallman @github-actions
Automerge: Revert "[RISCV] Remove B and Zbc extension from Andes seri…
4e6416f 
…es cpus." (#144402)

Reverts llvm/llvm-project#144022

This has been failing postcommit CI for two days:
https://lab.llvm.org/buildbot/#/builders/63
searlmc1 pushed a commit to ROCm/llvm-project that referenced this pull request Jun 17, 2025
@AaronBallman @ronlieb
Revert "[RISCV] Remove B and Zbc extension from Andes series cpus." (l…
205cb36 
…lvm#144402)

Reverts llvm#144022

This has been failing postcommit CI for two days:
https://lab.llvm.org/buildbot/#/builders/63
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@lenary lenary lenary approved these changes

@mshockwave mshockwave Awaiting requested review from mshockwave

@topperc topperc Awaiting requested review from topperc

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