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[TableGen] Use range-based for loops (NFC) #144283
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kazutakahirata
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kazutakahirata:cleanup_20250615_range_for_llvm_TableGen
Jun 16, 2025
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[TableGen] Use range-based for loops (NFC) #144283
kazutakahirata
merged 1 commit into
llvm:main
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kazutakahirata:cleanup_20250615_range_for_llvm_TableGen
Jun 16, 2025
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@llvm/pr-subscribers-tablegen @llvm/pr-subscribers-backend-x86 Author: Kazu Hirata (kazutakahirata) ChangesFull diff: https://github.com/llvm/llvm-project/pull/144283.diff 8 Files Affected:
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index d33c0dba91fd8..810b35e65b310 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -1824,8 +1824,8 @@ bool TreePatternNode::UpdateNodeTypeFromInst(unsigned ResNo,
}
bool TreePatternNode::ContainsUnresolvedType(TreePattern &TP) const {
- for (unsigned i = 0, e = Types.size(); i != e; ++i)
- if (!TP.getInfer().isConcrete(Types[i], true))
+ for (const TypeSetByHwMode &Type : Types)
+ if (!TP.getInfer().isConcrete(Type, true))
return true;
for (const TreePatternNode &Child : children())
if (Child.ContainsUnresolvedType(TP))
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
index a5aadf2ee1138..64fec275faa68 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
@@ -747,8 +747,8 @@ class TreePatternNode : public RefCountedBase<TreePatternNode> {
/// hasChild - Return true if N is any of our children.
bool hasChild(const TreePatternNode *N) const {
- for (unsigned i = 0, e = Children.size(); i != e; ++i)
- if (Children[i].get() == N)
+ for (const TreePatternNodePtr &Child : Children)
+ if (Child.get() == N)
return true;
return false;
}
@@ -1171,9 +1171,9 @@ class CodeGenDAGPatterns {
}
const CodeGenIntrinsic &getIntrinsic(const Record *R) const {
- for (unsigned i = 0, e = Intrinsics.size(); i != e; ++i)
- if (Intrinsics[i].TheDef == R)
- return Intrinsics[i];
+ for (const CodeGenIntrinsic &Intrinsic : Intrinsics)
+ if (Intrinsic.TheDef == R)
+ return Intrinsic;
llvm_unreachable("Unknown intrinsic!");
}
@@ -1280,8 +1280,8 @@ class CodeGenDAGPatterns {
inline bool SDNodeInfo::ApplyTypeConstraints(TreePatternNode &N,
TreePattern &TP) const {
bool MadeChange = false;
- for (unsigned i = 0, e = TypeConstraints.size(); i != e; ++i)
- MadeChange |= TypeConstraints[i].ApplyTypeConstraint(N, *this, TP);
+ for (const SDTypeConstraint &TypeConstraint : TypeConstraints)
+ MadeChange |= TypeConstraint.ApplyTypeConstraint(N, *this, TP);
return MadeChange;
}
diff --git a/llvm/utils/TableGen/Common/CodeGenInstruction.h b/llvm/utils/TableGen/Common/CodeGenInstruction.h
index e38979af3909d..3a5abc55319b1 100644
--- a/llvm/utils/TableGen/Common/CodeGenInstruction.h
+++ b/llvm/utils/TableGen/Common/CodeGenInstruction.h
@@ -127,8 +127,7 @@ class CGIOperandList {
/// getTiedOperand - If this operand is tied to another one, return the
/// other operand number. Otherwise, return -1.
int getTiedRegister() const {
- for (unsigned j = 0, e = Constraints.size(); j != e; ++j) {
- const CGIOperandList::ConstraintInfo &CI = Constraints[j];
+ for (const CGIOperandList::ConstraintInfo &CI : Constraints) {
if (CI.isTied())
return CI.getTiedOperand();
}
diff --git a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
index 72954804b66f8..af7e43929bcf0 100644
--- a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
@@ -2232,13 +2232,10 @@ void PredTransitions::dump() const {
dbgs() << LS << SchedModels.getSchedRW(PC.RWIdx, PC.IsRead).Name << ":"
<< PC.Predicate->getName();
dbgs() << "},\n => {";
- for (SmallVectorImpl<SmallVector<unsigned, 4>>::const_iterator
- WSI = TI.WriteSequences.begin(),
- WSE = TI.WriteSequences.end();
- WSI != WSE; ++WSI) {
+ for (const auto &WS : TI.WriteSequences) {
dbgs() << "(";
ListSeparator LS;
- for (unsigned N : *WSI)
+ for (unsigned N : WS)
dbgs() << LS << SchedModels.getSchedWrite(N).Name;
dbgs() << "),";
}
diff --git a/llvm/utils/TableGen/Common/DAGISelMatcher.cpp b/llvm/utils/TableGen/Common/DAGISelMatcher.cpp
index 8780c4f5b61c2..3543bb5a55c64 100644
--- a/llvm/utils/TableGen/Common/DAGISelMatcher.cpp
+++ b/llvm/utils/TableGen/Common/DAGISelMatcher.cpp
@@ -286,11 +286,11 @@ void EmitNodeMatcherCommon::printImpl(raw_ostream &OS, indent Indent) const {
OS << (isa<MorphNodeToMatcher>(this) ? "MorphNodeTo: " : "EmitNode: ")
<< CGI.Namespace << "::" << CGI.TheDef->getName() << ": <todo flags> ";
- for (unsigned i = 0, e = VTs.size(); i != e; ++i)
- OS << ' ' << getEnumName(VTs[i]);
+ for (MVT::SimpleValueType VT : VTs)
+ OS << ' ' << getEnumName(VT);
OS << '(';
- for (unsigned i = 0, e = Operands.size(); i != e; ++i)
- OS << Operands[i] << ' ';
+ for (unsigned Operand : Operands)
+ OS << Operand << ' ';
OS << ")\n";
}
diff --git a/llvm/utils/TableGen/DAGISelMatcherGen.cpp b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
index afdb6879eede4..0039ff4f3e2d7 100644
--- a/llvm/utils/TableGen/DAGISelMatcherGen.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
@@ -526,23 +526,20 @@ void MatcherGen::EmitMatchCode(const TreePatternNode &N,
EmitOperatorMatchCode(N, NodeNoTypes);
// If there are node predicates for this node, generate their checks.
- for (unsigned i = 0, e = N.getPredicateCalls().size(); i != e; ++i) {
- const TreePredicateCall &Pred = N.getPredicateCalls()[i];
+ for (const TreePredicateCall &Pred : N.getPredicateCalls()) {
SmallVector<unsigned, 4> Operands;
if (Pred.Fn.usesOperands()) {
TreePattern *TP = Pred.Fn.getOrigPatFragRecord();
- for (unsigned i = 0; i < TP->getNumArgs(); ++i) {
- std::string Name =
- ("pred:" + Twine(Pred.Scope) + ":" + TP->getArgName(i)).str();
+ for (const std::string &Arg : TP->getArgList()) {
+ std::string Name = ("pred:" + Twine(Pred.Scope) + ":" + Arg).str();
Operands.push_back(getNamedArgumentSlot(Name));
}
}
AddMatcher(new CheckPredicateMatcher(Pred.Fn, Operands));
}
- for (unsigned i = 0, e = ResultsToTypeCheck.size(); i != e; ++i)
- AddMatcher(new CheckTypeMatcher(N.getSimpleType(ResultsToTypeCheck[i]),
- ResultsToTypeCheck[i]));
+ for (unsigned I : ResultsToTypeCheck)
+ AddMatcher(new CheckTypeMatcher(N.getSimpleType(I), I));
}
/// EmitMatcherCode - Generate the code that matches the predicate of this
@@ -836,8 +833,8 @@ void MatcherGen::EmitResultInstructionAsOperand(
// overridden, or which we aren't letting it override; emit the 'default
// ops' operands.
const DAGDefaultOperand &DefaultOp = CGP.getDefaultOperand(OperandNode);
- for (unsigned i = 0, e = DefaultOp.DefaultOps.size(); i != e; ++i)
- EmitResultOperand(*DefaultOp.DefaultOps[i], InstOps);
+ for (const TreePatternNodePtr &Op : DefaultOp.DefaultOps)
+ EmitResultOperand(*Op, InstOps);
continue;
}
@@ -886,10 +883,10 @@ void MatcherGen::EmitResultInstructionAsOperand(
if (isRoot && !PhysRegInputs.empty()) {
// Emit all of the CopyToReg nodes for the input physical registers. These
// occur in patterns like (mul:i8 AL:i8, GR8:i8:$src).
- for (unsigned i = 0, e = PhysRegInputs.size(); i != e; ++i) {
+ for (const auto &PhysRegInput : PhysRegInputs) {
const CodeGenRegister *Reg =
- CGP.getTargetInfo().getRegBank().getReg(PhysRegInputs[i].first);
- AddMatcher(new EmitCopyToRegMatcher(PhysRegInputs[i].second, Reg));
+ CGP.getTargetInfo().getRegBank().getReg(PhysRegInput.first);
+ AddMatcher(new EmitCopyToRegMatcher(PhysRegInput.second, Reg));
}
// Even if the node has no other glue inputs, the resultant node must be
@@ -977,8 +974,8 @@ void MatcherGen::EmitResultInstructionAsOperand(
NumFixedArityOperands, NextRecordedOperandNo));
// The non-chain and non-glue results of the newly emitted node get recorded.
- for (unsigned i = 0, e = ResultVTs.size(); i != e; ++i) {
- if (ResultVTs[i] == MVT::Other || ResultVTs[i] == MVT::Glue)
+ for (MVT::SimpleValueType ResultVT : ResultVTs) {
+ if (ResultVT == MVT::Other || ResultVT == MVT::Glue)
break;
OutputOps.push_back(NextRecordedOperandNo++);
}
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index bc1650a4acf0b..7d24c0f80cddb 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -726,11 +726,12 @@ void RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
// Output the rows.
OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1, 32)
<< " Rows[" << Rows.size() << "][" << SubRegIndicesSize << "] = {\n";
- for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
+ for (const auto &Row : Rows) {
OS << " { ";
- for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i)
- if (Rows[r][i])
- OS << Rows[r][i]->getQualifiedName() << ", ";
+ for (const llvm::CodeGenSubRegIndex *Elem :
+ ArrayRef(&Row[0], SubRegIndicesSize))
+ if (Elem)
+ OS << Elem->getQualifiedName() << ", ";
else
OS << "0, ";
OS << "},\n";
@@ -830,8 +831,7 @@ void RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS,
for (size_t s = 0, se = Sequences.size(); s != se; ++s) {
OS << " ";
const SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s];
- for (size_t p = 0, pe = Sequence.size(); p != pe; ++p) {
- const MaskRolPair &P = Sequence[p];
+ for (const MaskRolPair &P : Sequence) {
printMask(OS << "{ ", P.Mask);
OS << format(", %2u }, ", P.RotateLeft);
}
diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp
index 36f752a1ebe63..3c422a32dcaf7 100644
--- a/llvm/utils/TableGen/X86DisassemblerTables.cpp
+++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp
@@ -882,9 +882,9 @@ void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
N = ++OperandSetNum;
o << " { /* " << (OperandSetNum - 1) << " */\n";
- for (unsigned i = 0, e = OperandList.size(); i != e; ++i) {
- const char *Encoding = stringForOperandEncoding(OperandList[i].first);
- const char *Type = stringForOperandType(OperandList[i].second);
+ for (const auto &[Enc, Ty] : OperandList) {
+ const char *Encoding = stringForOperandEncoding(Enc);
+ const char *Type = stringForOperandType(Ty);
o << " { " << Encoding << ", " << Type << " },\n";
}
o << " },\n";
|
shiltian
approved these changes
Jun 16, 2025
jurahul
approved these changes
Jun 16, 2025
akuhlens
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to akuhlens/llvm-project
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Jun 24, 2025
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