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[AMDGPU] Use subtarget feature for v_lshl_add_u64 pattern. NFC. #144544

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Merged
merged 1 commit into from
Jun 17, 2025

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@jayfoad jayfoad commented Jun 17, 2025

Following on from #133723, use the new subtarget feature for the
selection pattern as well as for the instruction definition.

Following on from llvm#133723, use the new subtarget feature for the
selection pattern as well as for the instruction definition.
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llvmbot commented Jun 17, 2025

@llvm/pr-subscribers-backend-amdgpu

Author: Jay Foad (jayfoad)

Changes

Following on from #133723, use the new subtarget feature for the
selection pattern as well as for the instruction definition.


Full diff: https://github.com/llvm/llvm-project/pull/144544.diff

1 Files Affected:

  • (modified) llvm/lib/Target/AMDGPU/VOP3Instructions.td (+1-1)
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index a005e0245b8ff..f372101cb7b77 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -806,7 +806,7 @@ def : GCNPat<
  (DivergentBinFrag<mul> i32:$src0, IsPow2Plus1:$src1),
  (V_LSHL_ADD_U32_e64 i32:$src0, (i32 (Log2_32 imm:$src1)), i32:$src0)>;
 
-let SubtargetPredicate = isGFX940Plus in
+let SubtargetPredicate = HasLshlAddU64Inst in
 def : GCNPat<
   (ThreeOpFrag<shl_0_to_4, add> i64:$src0, i32:$src1, i64:$src2),
   (V_LSHL_ADD_U64_e64 VSrc_b64:$src0, VSrc_b32:$src1, VSrc_b64:$src2)

@jayfoad jayfoad merged commit a5f5f12 into llvm:main Jun 17, 2025
8 of 9 checks passed
@jayfoad jayfoad deleted the v-lshl-add-u64-pattern branch June 17, 2025 15:46
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3 participants