[WIP][RISCV] Update SpacemiT X60 vector scheduling model with measured latencies

[mikhailramalho]

WIP: This PR incrementally updates the scheduling model based on real hardware measurements, but it's not ready to be reviewed yet

Updates the SpacemiT X60 scheduling model with actual latencies measured on BPi-F3 hardware.

Changes:

• Added 4 new latency classes: ArithLat (4,4,5,8), CarryLat (4,4,8,9), MaskLat (4,6,10,18), WideLat (4,5,8,8)
• Updated latencies for ~13 instruction categories, including basic ALU, comparisons, carry ops, division, FP operations

Completed:

• Basic integer ALU, min/max, saturating/averaging arithmetic
• Carry operations, mask operations, comparisons
• Integer/FP division (split simple/complex)
• Widening operations, FP scalar operations

Missing:

• Integer multiply (complex SEW-dependent)
• FP arithmetic .vv variants
• FP FMA operations
• FP conversions and reductions
• Vector loads/stores

Known Issues:

• WriteVIALU includes both arithmetic and logical ops (using ArithLat compromise)
• Some operations grouped together use worst-case latency

There is a 2% regression on x264 with this version of the code.