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Wolfram70
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sivan-shani
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[MLIR][NVVM] Rename cvt Ops to convert (llvm#140868)
This patch renames the cvt Ops and related structures to `convert` in the NVVM dialect to be more descriptive.
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6 files changed

+108
-107
lines changed

6 files changed

+108
-107
lines changed

‎mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -1110,7 +1110,7 @@ def SaturationModeAttr : EnumAttr<NVVM_Dialect, SaturationMode, "sat_mode"> {
11101110
let assemblyFormat = "`<` $value `>`";
11111111
}
11121112

1113-
def NVVM_CvtFloatToTF32Op : NVVM_Op<"cvt.float.to.tf32"> {
1113+
def NVVM_ConvertFloatToTF32Op : NVVM_Op<"convert.float.to.tf32"> {
11141114
let summary = "Convert the given float input to TF32";
11151115
let description = [{
11161116
This Op converts the given f32 input to tf32.
@@ -1139,24 +1139,24 @@ def NVVM_CvtFloatToTF32Op : NVVM_Op<"cvt.float.to.tf32"> {
11391139
}];
11401140

11411141
string llvmBuilder = [{
1142-
auto intId = NVVM::CvtFloatToTF32Op::getIntrinsicID($rnd, $sat, $relu);
1142+
auto intId = NVVM::ConvertFloatToTF32Op::getIntrinsicID($rnd, $sat, $relu);
11431143
$res = createIntrinsicCall(builder, intId, {$src});
11441144
}];
11451145
}
11461146

1147-
def CVTFP6E2M3 : I32EnumAttrCase<"E2M3", 0, "e2m3">;
1148-
def CVTFP6E3M2 : I32EnumAttrCase<"E3M2", 1, "e3m2">;
1147+
def ConvertFP6E2M3 : I32EnumAttrCase<"E2M3", 0, "e2m3">;
1148+
def ConvertFP6E3M2 : I32EnumAttrCase<"E3M2", 1, "e3m2">;
11491149

1150-
def CVTFP6Type : I32EnumAttr<"CVTFP6Type", "NVVM CVTFP6Type kind",
1151-
[CVTFP6E2M3, CVTFP6E3M2]> {
1150+
def ConvertFP6Type : I32EnumAttr<"ConvertFP6Type", "NVVM ConvertFP6Type kind",
1151+
[ConvertFP6E2M3, ConvertFP6E3M2]> {
11521152
let genSpecializedAttr = 0;
11531153
let cppNamespace = "::mlir::NVVM";
11541154
}
1155-
def CVTFP6TypeAttr : EnumAttr<NVVM_Dialect, CVTFP6Type, "cvt_fp6_type"> {
1155+
def ConvertFP6TypeAttr : EnumAttr<NVVM_Dialect, ConvertFP6Type, "convert_fp6_type"> {
11561156
let assemblyFormat = "`<` $value `>`";
11571157
}
11581158

1159-
def NVVM_CvtF32x2ToF6x2Op : NVVM_Op<"cvt.f32x2.to.f6x2"> {
1159+
def NVVM_ConvertF32x2ToF6x2Op : NVVM_Op<"convert.f32x2.to.f6x2"> {
11601160
let summary = "Convert a pair of float inputs to f6x2";
11611161
let description = [{
11621162
This Op converts each of the given float inputs to the specified fp6 type.
@@ -1176,19 +1176,19 @@ def NVVM_CvtF32x2ToF6x2Op : NVVM_Op<"cvt.f32x2.to.f6x2"> {
11761176

11771177
let results = (outs AnyTypeOf<[I16, VectorOfLengthAndType<[2], [I8]>]>:$dst);
11781178
let arguments = (ins
1179-
CVTFP6TypeAttr:$type,
1179+
ConvertFP6TypeAttr:$type,
11801180
F32:$a,
11811181
F32:$b,
11821182
DefaultValuedAttr<BoolAttr, "false">:$relu);
11831183
let assemblyFormat = "$type $a `,` $b attr-dict `:` type($dst)";
11841184

11851185
let extraClassDeclaration = [{
1186-
static llvm::Intrinsic::ID getIntrinsicID(NVVM::CVTFP6Type,
1186+
static llvm::Intrinsic::ID getIntrinsicID(NVVM::ConvertFP6Type,
11871187
bool hasRelu);
11881188
}];
11891189

11901190
string llvmBuilder = [{
1191-
auto intId = NVVM::CvtF32x2ToF6x2Op::getIntrinsicID($type, $relu);
1191+
auto intId = NVVM::ConvertF32x2ToF6x2Op::getIntrinsicID($type, $relu);
11921192
llvm::Value *packedI16 = createIntrinsicCall(builder, intId, {$a, $b});
11931193
if(op.getDst().getType().isInteger(16))
11941194
$dst = packedI16;
@@ -1198,20 +1198,20 @@ def NVVM_CvtF32x2ToF6x2Op : NVVM_Op<"cvt.f32x2.to.f6x2"> {
11981198
}];
11991199
}
12001200

1201-
def CVTFP8E4M3 : I32EnumAttrCase<"E4M3", 0, "e4m3">;
1202-
def CVTFP8E5M2 : I32EnumAttrCase<"E5M2", 1, "e5m2">;
1203-
def CVTFP8UE8M0 : I32EnumAttrCase<"UE8M0", 2, "ue8m0">;
1201+
def ConvertFP8E4M3 : I32EnumAttrCase<"E4M3", 0, "e4m3">;
1202+
def ConvertFP8E5M2 : I32EnumAttrCase<"E5M2", 1, "e5m2">;
1203+
def ConvertFP8UE8M0 : I32EnumAttrCase<"UE8M0", 2, "ue8m0">;
12041204

1205-
def CVTFP8Type : I32EnumAttr<"CVTFP8Type", "NVVM CVTFP8Type kind",
1206-
[CVTFP8E4M3, CVTFP8E5M2, CVTFP8UE8M0]> {
1205+
def ConvertFP8Type : I32EnumAttr<"ConvertFP8Type", "NVVM ConvertFP8Type kind",
1206+
[ConvertFP8E4M3, ConvertFP8E5M2, ConvertFP8UE8M0]> {
12071207
let genSpecializedAttr = 0;
12081208
let cppNamespace = "::mlir::NVVM";
12091209
}
1210-
def CVTFP8TypeAttr : EnumAttr<NVVM_Dialect, CVTFP8Type, "cvt_fp8_type"> {
1210+
def ConvertFP8TypeAttr : EnumAttr<NVVM_Dialect, ConvertFP8Type, "convert_fp8_type"> {
12111211
let assemblyFormat = "`<` $value `>`";
12121212
}
12131213

1214-
def NVVM_CvtF32x2ToF8x2Op : NVVM_Op<"cvt.f32x2.to.f8x2"> {
1214+
def NVVM_ConvertF32x2ToF8x2Op : NVVM_Op<"convert.f32x2.to.f8x2"> {
12151215
let summary = "Convert a pair of float inputs to f8x2";
12161216
let description = [{
12171217
This Op converts each of the given float inputs to the specified fp8 type.
@@ -1232,7 +1232,7 @@ def NVVM_CvtF32x2ToF8x2Op : NVVM_Op<"cvt.f32x2.to.f8x2"> {
12321232
let hasVerifier = 1;
12331233
let results = (outs AnyTypeOf<[I16, VectorOfLengthAndType<[2], [I8]>]>:$dst);
12341234
let arguments = (ins
1235-
CVTFP8TypeAttr:$type,
1235+
ConvertFP8TypeAttr:$type,
12361236
F32:$a,
12371237
F32:$b,
12381238
DefaultValuedAttr<FPRoundingModeAttr, "FPRoundingMode::NONE">:$rnd,
@@ -1241,14 +1241,14 @@ def NVVM_CvtF32x2ToF8x2Op : NVVM_Op<"cvt.f32x2.to.f8x2"> {
12411241
let assemblyFormat = "$type $a `,` $b attr-dict `:` type($dst)";
12421242

12431243
let extraClassDeclaration = [{
1244-
static llvm::Intrinsic::ID getIntrinsicID(NVVM::CVTFP8Type to,
1244+
static llvm::Intrinsic::ID getIntrinsicID(NVVM::ConvertFP8Type to,
12451245
NVVM::FPRoundingMode rnd,
12461246
NVVM::SaturationMode sat,
12471247
bool hasRelu);
12481248
}];
12491249

12501250
string llvmBuilder = [{
1251-
auto intId = NVVM::CvtF32x2ToF8x2Op::getIntrinsicID($type, $rnd, $sat, $relu);
1251+
auto intId = NVVM::ConvertF32x2ToF8x2Op::getIntrinsicID($type, $rnd, $sat, $relu);
12521252
llvm::Value *packedI16 = createIntrinsicCall(builder, intId, {$a, $b});
12531253
if(op.getDst().getType().isInteger(16))
12541254
$dst = packedI16;
@@ -1258,7 +1258,7 @@ def NVVM_CvtF32x2ToF8x2Op : NVVM_Op<"cvt.f32x2.to.f8x2"> {
12581258
}];
12591259
}
12601260

1261-
def NVVM_CvtF16x2ToF8x2Op : NVVM_Op<"cvt.f16x2.to.f8x2"> {
1261+
def NVVM_ConvertF16x2ToF8x2Op : NVVM_Op<"convert.f16x2.to.f8x2"> {
12621262
let summary = "Convert an f16x2 input to f8x2";
12631263
let description = [{
12641264
This Op converts the given f16 inputs in an f16x2 vector to the specified
@@ -1280,18 +1280,18 @@ def NVVM_CvtF16x2ToF8x2Op : NVVM_Op<"cvt.f16x2.to.f8x2"> {
12801280
let hasVerifier = 1;
12811281
let results = (outs AnyTypeOf<[I16, VectorOfLengthAndType<[2], [I8]>]>:$dst);
12821282
let arguments = (ins
1283-
CVTFP8TypeAttr:$type,
1283+
ConvertFP8TypeAttr:$type,
12841284
VectorOfLengthAndType<[2], [F16]>:$a,
12851285
DefaultValuedAttr<BoolAttr, "false">:$relu);
12861286
let assemblyFormat = "$type $a attr-dict `:` type($a) `->` type($dst)";
12871287

12881288
let extraClassDeclaration = [{
1289-
static llvm::Intrinsic::ID getIntrinsicID(NVVM::CVTFP8Type to,
1289+
static llvm::Intrinsic::ID getIntrinsicID(NVVM::ConvertFP8Type to,
12901290
bool hasRelu);
12911291
}];
12921292

12931293
string llvmBuilder = [{
1294-
auto intId = NVVM::CvtF16x2ToF8x2Op::getIntrinsicID($type, $relu);
1294+
auto intId = NVVM::ConvertF16x2ToF8x2Op::getIntrinsicID($type, $relu);
12951295
llvm::Value *packedI16 = createIntrinsicCall(builder, intId, {$a});
12961296
if(op.getDst().getType().isInteger(16))
12971297
$dst = packedI16;
@@ -1301,7 +1301,7 @@ def NVVM_CvtF16x2ToF8x2Op : NVVM_Op<"cvt.f16x2.to.f8x2"> {
13011301
}];
13021302
}
13031303

1304-
def NVVM_CvtBF16x2ToF8x2Op : NVVM_Op<"cvt.bf16x2.to.f8x2"> {
1304+
def NVVM_ConvertBF16x2ToF8x2Op : NVVM_Op<"convert.bf16x2.to.f8x2"> {
13051305
let summary = "Convert a pair of bf16 inputs to f8x2";
13061306
let description = [{
13071307
This Op converts the given bf16 inputs in a bf16x2 vector to the specified
@@ -1323,7 +1323,7 @@ def NVVM_CvtBF16x2ToF8x2Op : NVVM_Op<"cvt.bf16x2.to.f8x2"> {
13231323
let hasVerifier = 1;
13241324
let results = (outs AnyTypeOf<[I16, VectorOfLengthAndType<[2], [I8]>]>:$dst);
13251325
let arguments = (ins
1326-
CVTFP8TypeAttr:$type,
1326+
ConvertFP8TypeAttr:$type,
13271327
VectorOfLengthAndType<[2], [BF16]>:$a,
13281328
DefaultValuedAttr<FPRoundingModeAttr, "FPRoundingMode::NONE">:$rnd,
13291329
DefaultValuedAttr<SaturationModeAttr, "SaturationMode::NONE">:$sat);
@@ -1335,7 +1335,7 @@ def NVVM_CvtBF16x2ToF8x2Op : NVVM_Op<"cvt.bf16x2.to.f8x2"> {
13351335
}];
13361336

13371337
string llvmBuilder = [{
1338-
auto intId = NVVM::CvtBF16x2ToF8x2Op::getIntrinsicID($rnd, $sat);
1338+
auto intId = NVVM::ConvertBF16x2ToF8x2Op::getIntrinsicID($rnd, $sat);
13391339
llvm::Value *packedI16 = createIntrinsicCall(builder, intId, {$a});
13401340
if(op.getDst().getType().isInteger(16))
13411341
$dst = packedI16;

‎mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp

Lines changed: 32 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,7 @@ LogicalResult CpAsyncBulkTensorReduceOp::verify() {
118118
getLoc());
119119
}
120120

121-
LogicalResult CvtFloatToTF32Op::verify() {
121+
LogicalResult ConvertFloatToTF32Op::verify() {
122122
using RndMode = NVVM::FPRoundingMode;
123123
switch (getRnd()) {
124124
case RndMode::RNA:
@@ -130,12 +130,12 @@ LogicalResult CvtFloatToTF32Op::verify() {
130130
break;
131131
default:
132132
return emitError(
133-
"Only {rn,rz,rna} rounding modes supported for CvtFloatToTF32Op.");
133+
"Only {rn,rz,rna} rounding modes supported for ConvertFloatToTF32Op.");
134134
}
135135
return success();
136136
}
137137

138-
LogicalResult CvtF32x2ToF8x2Op::verify() {
138+
LogicalResult ConvertF32x2ToF8x2Op::verify() {
139139
using RndMode = NVVM::FPRoundingMode;
140140
using SatMode = NVVM::SaturationMode;
141141

@@ -147,16 +147,16 @@ LogicalResult CvtF32x2ToF8x2Op::verify() {
147147
bool hasRelu = getRelu();
148148

149149
switch (getType()) {
150-
case CVTFP8Type::E4M3:
151-
case CVTFP8Type::E5M2:
150+
case ConvertFP8Type::E4M3:
151+
case ConvertFP8Type::E5M2:
152152
if (!isRoundingModeRN)
153153
return emitOpError("Only RN rounding mode is supported for conversions "
154154
"from f32x2 to .e4m3x2 or .e5m2x2 types");
155155
if (!isSatFinite)
156156
return emitOpError("Only SATFINITE saturation mode is supported for "
157157
"conversions from f32x2 to .e4m3x2 or .e5m2x2 types");
158158
break;
159-
case CVTFP8Type::UE8M0:
159+
case ConvertFP8Type::UE8M0:
160160
if (!(isRoundingModeRZ || isRoundingModeRP))
161161
return emitOpError("Only RZ or RP rounding modes are supported for "
162162
"conversions from f32x2 to .ue8m0x2 type");
@@ -167,18 +167,18 @@ LogicalResult CvtF32x2ToF8x2Op::verify() {
167167
return success();
168168
}
169169

170-
LogicalResult CvtF16x2ToF8x2Op::verify() {
171-
if (getType() == CVTFP8Type::UE8M0)
170+
LogicalResult ConvertF16x2ToF8x2Op::verify() {
171+
if (getType() == ConvertFP8Type::UE8M0)
172172
return emitOpError("Only .e4m3 or .e5m2 types are supported for "
173173
"conversions from f16x2 to f8x2.");
174174

175175
return success();
176176
}
177177

178-
LogicalResult CvtBF16x2ToF8x2Op::verify() {
178+
LogicalResult ConvertBF16x2ToF8x2Op::verify() {
179179
using RndMode = NVVM::FPRoundingMode;
180180

181-
if (getType() != CVTFP8Type::UE8M0)
181+
if (getType() != ConvertFP8Type::UE8M0)
182182
return emitOpError(
183183
"Only .ue8m0 type is supported for conversions from bf16x2 to f8x2.");
184184

@@ -1385,9 +1385,9 @@ llvm::Intrinsic::ID CpAsyncBulkTensorReduceOp::getIntrinsicID(
13851385
hasSatFinite ? CVT_F2TF32_ID_IMPL(rnd, relu, sf) \
13861386
: CVT_F2TF32_ID_IMPL(rnd, relu, )
13871387

1388-
llvm::Intrinsic::ID CvtFloatToTF32Op::getIntrinsicID(NVVM::FPRoundingMode rnd,
1389-
NVVM::SaturationMode sat,
1390-
bool hasRelu) {
1388+
llvm::Intrinsic::ID
1389+
ConvertFloatToTF32Op::getIntrinsicID(NVVM::FPRoundingMode rnd,
1390+
NVVM::SaturationMode sat, bool hasRelu) {
13911391
using RndMode = NVVM::FPRoundingMode;
13921392
bool hasSatFinite = (sat == NVVM::SaturationMode::SATFINITE);
13931393
switch (rnd) {
@@ -1406,14 +1406,15 @@ llvm::Intrinsic::ID CvtFloatToTF32Op::getIntrinsicID(NVVM::FPRoundingMode rnd,
14061406
has_relu ? llvm::Intrinsic::nvvm_ff_to_##type##_rn_relu_satfinite \
14071407
: llvm::Intrinsic::nvvm_ff_to_##type##_rn_satfinite
14081408

1409-
llvm::Intrinsic::ID CvtF32x2ToF6x2Op::getIntrinsicID(NVVM::CVTFP6Type type,
1410-
bool hasRelu) {
1409+
llvm::Intrinsic::ID
1410+
ConvertF32x2ToF6x2Op::getIntrinsicID(NVVM::ConvertFP6Type type, bool hasRelu) {
14111411
switch (type) {
1412-
case NVVM::CVTFP6Type::E2M3:
1412+
case NVVM::ConvertFP6Type::E2M3:
14131413
return GET_F32x2_TO_F6x2_ID(e2m3x2, hasRelu);
1414-
case NVVM::CVTFP6Type::E3M2:
1414+
case NVVM::ConvertFP6Type::E3M2:
14151415
return GET_F32x2_TO_F6x2_ID(e3m2x2, hasRelu);
14161416
}
1417+
llvm_unreachable("Invalid conversion in ConvertF32x2ToF6x2Op");
14171418
}
14181419

14191420
#define GET_F32x2_TO_F8X2_US_ID(rnd, has_satf) \
@@ -1424,20 +1425,20 @@ llvm::Intrinsic::ID CvtF32x2ToF6x2Op::getIntrinsicID(NVVM::CVTFP6Type type,
14241425
has_relu ? llvm::Intrinsic::nvvm_ff_to_##type##_rn_relu \
14251426
: llvm::Intrinsic::nvvm_ff_to_##type##_rn
14261427

1427-
llvm::Intrinsic::ID CvtF32x2ToF8x2Op::getIntrinsicID(NVVM::CVTFP8Type type,
1428-
NVVM::FPRoundingMode rnd,
1429-
NVVM::SaturationMode sat,
1430-
bool hasRelu) {
1428+
llvm::Intrinsic::ID
1429+
ConvertF32x2ToF8x2Op::getIntrinsicID(NVVM::ConvertFP8Type type,
1430+
NVVM::FPRoundingMode rnd,
1431+
NVVM::SaturationMode sat, bool hasRelu) {
14311432
bool hasSatFinite = (sat == NVVM::SaturationMode::SATFINITE);
14321433
bool hasRoundingModeRZ = (rnd == NVVM::FPRoundingMode::RZ);
14331434
bool hasRoundingModeRP = (rnd == NVVM::FPRoundingMode::RP);
14341435

14351436
switch (type) {
1436-
case NVVM::CVTFP8Type::E4M3:
1437+
case NVVM::ConvertFP8Type::E4M3:
14371438
return GET_F32x2_TO_F8X2_S_ID(e4m3x2, hasRelu);
1438-
case NVVM::CVTFP8Type::E5M2:
1439+
case NVVM::ConvertFP8Type::E5M2:
14391440
return GET_F32x2_TO_F8X2_S_ID(e5m2x2, hasRelu);
1440-
case NVVM::CVTFP8Type::UE8M0:
1441+
case NVVM::ConvertFP8Type::UE8M0:
14411442
if (hasRoundingModeRZ)
14421443
return GET_F32x2_TO_F8X2_US_ID(rz, hasSatFinite);
14431444
else if (hasRoundingModeRP)
@@ -1450,15 +1451,15 @@ llvm::Intrinsic::ID CvtF32x2ToF8x2Op::getIntrinsicID(NVVM::CVTFP8Type type,
14501451
has_relu ? llvm::Intrinsic::nvvm_f16x2_to_##type##_rn_relu \
14511452
: llvm::Intrinsic::nvvm_f16x2_to_##type##_rn
14521453

1453-
llvm::Intrinsic::ID CvtF16x2ToF8x2Op::getIntrinsicID(NVVM::CVTFP8Type type,
1454-
bool hasRelu) {
1454+
llvm::Intrinsic::ID
1455+
ConvertF16x2ToF8x2Op::getIntrinsicID(NVVM::ConvertFP8Type type, bool hasRelu) {
14551456
switch (type) {
1456-
case NVVM::CVTFP8Type::E4M3:
1457+
case NVVM::ConvertFP8Type::E4M3:
14571458
return GET_F16x2_TO_F8X2_ID(e4m3x2, hasRelu);
1458-
case NVVM::CVTFP8Type::E5M2:
1459+
case NVVM::ConvertFP8Type::E5M2:
14591460
return GET_F16x2_TO_F8X2_ID(e5m2x2, hasRelu);
14601461
default:
1461-
llvm_unreachable("Invalid CVTFP8Type for CvtF16x2ToF8x2Op");
1462+
llvm_unreachable("Invalid ConvertFP8Type for CvtF16x2ToF8x2Op");
14621463
}
14631464
}
14641465

@@ -1467,8 +1468,8 @@ llvm::Intrinsic::ID CvtF16x2ToF8x2Op::getIntrinsicID(NVVM::CVTFP8Type type,
14671468
: llvm::Intrinsic::nvvm_bf16x2_to_ue8m0x2_##rnd
14681469

14691470
llvm::Intrinsic::ID
1470-
CvtBF16x2ToF8x2Op::getIntrinsicID(NVVM::FPRoundingMode rnd,
1471-
NVVM::SaturationMode sat) {
1471+
ConvertBF16x2ToF8x2Op::getIntrinsicID(NVVM::FPRoundingMode rnd,
1472+
NVVM::SaturationMode sat) {
14721473
bool hasSatFinite = (sat == NVVM::SaturationMode::SATFINITE);
14731474
switch (rnd) {
14741475
case NVVM::FPRoundingMode::RZ:

‎mlir/test/Target/LLVMIR/nvvm/cvt_fp6x2.mlir renamed to ‎mlir/test/Target/LLVMIR/nvvm/convert_fp6x2.mlir

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3,19 +3,19 @@
33
// CHECK-LABEL: @convert_f32x2_to_fp6x2_packed
44
llvm.func @convert_f32x2_to_fp6x2_packed(%srcA : f32, %srcB : f32) {
55
//CHECK: %{{.*}} = call i16 @llvm.nvvm.ff.to.e2m3x2.rn.satfinite(float %{{.*}}, float %{{.*}})
6-
%res1 = nvvm.cvt.f32x2.to.f6x2 <e2m3> %srcA, %srcB : i16
6+
%res1 = nvvm.convert.f32x2.to.f6x2 <e2m3> %srcA, %srcB : i16
77
//CHECK: %{{.*}} = call i16 @llvm.nvvm.ff.to.e3m2x2.rn.satfinite(float %{{.*}}, float %{{.*}})
8-
%res2 = nvvm.cvt.f32x2.to.f6x2 <e3m2> %srcA, %srcB : i16
8+
%res2 = nvvm.convert.f32x2.to.f6x2 <e3m2> %srcA, %srcB : i16
99
llvm.return
1010
}
1111

1212
// CHECK-LABEL: @convert_f32x2_to_fp6x2_vector
1313
llvm.func @convert_f32x2_to_fp6x2_vector(%srcA : f32, %srcB : f32) {
1414
//CHECK: %[[res0:.*]] = call i16 @llvm.nvvm.ff.to.e2m3x2.rn.satfinite(float %{{.*}}, float %{{.*}})
1515
//CHECK-NEXT: %{{.*}} = bitcast i16 %[[res0]] to <2 x i8>
16-
%res1 = nvvm.cvt.f32x2.to.f6x2 <e2m3> %srcA, %srcB : vector<2xi8>
16+
%res1 = nvvm.convert.f32x2.to.f6x2 <e2m3> %srcA, %srcB : vector<2xi8>
1717
//CHECK: %[[res1:.*]] = call i16 @llvm.nvvm.ff.to.e3m2x2.rn.satfinite(float %{{.*}}, float %{{.*}})
1818
//CHECK-NEXT: %{{.*}} = bitcast i16 %[[res1]] to <2 x i8>
19-
%res2 = nvvm.cvt.f32x2.to.f6x2 <e3m2> %srcA, %srcB : vector<2xi8>
19+
%res2 = nvvm.convert.f32x2.to.f6x2 <e3m2> %srcA, %srcB : vector<2xi8>
2020
llvm.return
2121
}

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