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CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems

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🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.


The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

Popular repositories Loading

  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4.2k 617

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.4k 1.2k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.5k 227

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1.1k 334

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 861 228

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 738 180

Repositories

Showing 10 of 109 repositories
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    SystemVerilog 12 Apache-2.0 9 37 9 Updated Mar 20, 2025
  • Caliptra Public

    Caliptra IP and firmware for integrated Root of Trust block

    270 Apache-2.0 40 41 5 Updated Mar 20, 2025
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    SystemVerilog 84 Apache-2.0 47 88 14 Updated Mar 20, 2025
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    Rust 108 Apache-2.0 52 123 55 Updated Mar 20, 2025
  • chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4,201 Apache-2.0 617 325 (1 issue needs help) 149 Updated Mar 20, 2025
  • t1 Public
    Scala 257 Apache-2.0 34 20 29 Updated Mar 20, 2025
  • chisel-interface Public

    The 'missing header' for Chisel

    Nix 18 2 0 0 Updated Mar 20, 2025
  • rvdecoderdb Public

    The Scala parser to parse riscv/riscv-opcodes generate

    Nix 15 6 1 2 Updated Mar 20, 2025
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    C++ 35 LGPL-3.0 649 0 0 Updated Mar 20, 2025
  • sv-tests-results Public

    Output of the sv-tests runs.

    HTML 5 3 0 0 Updated Mar 20, 2025