This page is subject to change as long as this message is present. Anything could added, removed, or modified at any time.
I've decided I'm currently interested in compiler design.
This page is subject to change as long as this message is present. Anything could added, removed, or modified at any time.
I've decided I'm currently interested in compiler design.
Pipelined MIPS CPU, suitable for the Computer Organization course of Beihang University in 2023 fall semester.
Verilog 3
Action that automatically builds the latest VisionFive 2 firmware (OpenSBI + U-Boot), for personal use.