SystemVerilog compiler and language services

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Modern C++ Programming Course (C++03/11/14/17/20/23/26)

Free and Open Source Requirements Management TooL

UVM 1.2 port to Python

Verilator open-source SystemVerilog simulator and lint system

DPI module for UART-based console interaction with Verilator simulations

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

Library for controlling Lego Boost with Web Bluetooth API

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

KLayout Main Sources

An innovative Verilog-A compiler

Verilog-A simulation models

Demo package for the WaveForms SDK Getting Started guide and multiple test scripts for different instruments.

FastHenry is the premium inductance solver originally developed at M.I.T. on Unix platform. A de-facto golden reference standard, FastHenry extracts the inductances and resistances of any arbitrary…

FasterCap is a powerful three- and two-dimensional capactiance extraction program.

OpenSCAD gear generator.

ADC Performance Survey 1997-2024 (ISSCC & VLSI Circuit Symposium)

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Python wrapper for the Polarion WSDL API

Icarus Verilog

Ultralightweight JSON parser in ANSI C

Unit testing for cocotb

Material for OpenROAD Tutorial at DAC 2020