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inRedcrafter/verilog2factorio (press backspace or delete to remove)

Hi! I have hit this assert a few times now: https://github.com/Redcrafter/verilog2factorio/blob/1b23979d0abaf8e86bede7cbb6888b8485a6e9f6/src/nodes/SDFFE.ts#L34 Is there a reason you did not handle inverting ...
  • varkokonyi
  • Opened 
    on Feb 2
  • #25

Right now, it seems like the generated blueprint operates on specific signals on circuit wires (wooden box and the V signal). This is fine for doing general computations where the signal type doesn t matter, ...
enhancement
wontfix
  • kotarou3
  • 1
  • Opened 
    on Mar 24, 2022
  • #24

I ve tried several variations on this code, but never gotten compiled combinators with the expected behavior. module priority(input clock, input [9:0] prevPriority, input [9:0] f, input complete, output ...
bug
  • DaleStan
  • 1
  • Opened 
    on May 23, 2021
  • #17

In some cases the compiler might try to construct overlong wires. I have two guesses for why this might be happening: - This only happens for constant combinators. Since they don t line up with the ...
bug
invalid
  • MDFL64
  • 4
  • Opened 
    on Apr 27, 2021
  • #11

Compiling the same file twice does not necessarily produce the same results. This may make it difficult to reproduce or debug errors. I assume the culprit is the randomness in the simulator. Maybe using ...
bug
  • MDFL64
  • 2
  • Opened 
    on Apr 27, 2021
  • #10

An absolutely wonderful project you have here! I was poking around to see if it could work with one of my Verilog projects (https://github.com/wordandahalf/XDN/), but it fails without an easily diagnosable ...
bug
  • wordandahalf
  • 6
  • Opened 
    on Apr 26, 2021
  • #9

  • mohas
  • 1
  • Opened 
    on Apr 25, 2021
  • #8
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