The Ultra-Low Power RISC-V Core

130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design

Administrative repository for the Integrated Matrix Extension Task Group

TTS Towards Human-Sounding Speech

List of several designs I have been working through the years to avoid re-designing it again

Collection of different designs for clock domain crossing

Demo: how to create a custom EBRICK

educational microarchitectures for risc-v isa

Hammer: Highly Agile Masks Made Effortlessly from RTL

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

RTL, Cmodel, and testbench for NVDLA

CORE-V Family of RISC-V Cores

The Wildcat RISC-V

VeeR EH1 core

A dependency management tool for hardware projects.

RISC-V RV64GC emulator designed for RTL co-simulation

RISC-V Debug Support for our PULP RISC-V Cores

Qflow full end-to-end digital synthesis flow for ASIC designs

Linux on LiteX-VexRiscv

Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from https://github.com/shioyadan/Konata/releases

Fork of OpenOCD that has RISC-V support

Small footprint and configurable DRAM core

RISC-V Open Source Supervisor Binary Interface

Build your hardware, easily!