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CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).

🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。

Flexible Intermediate Representation for RTL

Rocket Chip Generator

A FPGA friendly 32 bit RISC-V CPU implementation

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

RISC-V Cores, SoC platforms and SoCs

IC design and development should be faster，simpler and more reliable

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

PicoRV32 - A Size-Optimized RISC-V CPU

PrIM (Processing-In-Memory benchmarks) is the first benchmark suite for a real-world processing-in-memory (PIM) architecture. PrIM is developed to evaluate, analyze, and characterize the first publ…

Open-source high-performance RISC-V processor

Examples of DPU programs using the UPMEM DPU SDK

Generic FIFO implementation with optional FWFT

DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator

A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the…

A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combines a widely-used simulator for out-of-order and in-order pr…

PIMSim is a Process-In-Memory Simulator with the compatibility of GEM5 full-system simulation.

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Verilog AXI components for FPGA implementation

HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.

Code used in

Latex code for making neural networks diagrams

The RIFFA development repository (development fork)

由图灵的猫开发，基于开源GPT2.0的初代创作型人工智能 | 可扩展、可进化

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

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