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[MIR] Add comments to INLINEASM immediate flag MachineOperands
Summary: The INLINEASM MIR instructions use immediate operands to encode the values of some operands. The MachineInstr pretty printer function already handles those operands and prints human readable annotations instead of the immediates. This patch adds similar annotations to the output of the MIRPrinter, however uses the new MIROperandComment feature. Reviewers: SjoerdMeijer, arsenm, efriedma Reviewed By: arsenm Subscribers: qcolombet, sdardis, jvesely, wdng, nhaehnle, hiraditya, jrtc27, atanasyan, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78088
1 parent 43e2460 commit 1a3e89a

28 files changed

+239
-115
lines changed

‎llvm/include/llvm/CodeGen/TargetInstrInfo.h

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1310,11 +1310,9 @@ class TargetInstrInfo : public MCInstrInfo {
13101310
virtual bool isPredicated(const MachineInstr &MI) const { return false; }
13111311

13121312
// Returns a MIRPrinter comment for this machine operand.
1313-
virtual std::string createMIROperandComment(const MachineInstr &MI,
1314-
const MachineOperand &Op,
1315-
unsigned OpIdx) const {
1316-
return std::string();
1317-
};
1313+
virtual std::string
1314+
createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
1315+
unsigned OpIdx, const TargetRegisterInfo *TRI) const;
13181316

13191317
/// Returns true if the instruction is a
13201318
/// terminator instruction that has not been predicated.

‎llvm/include/llvm/IR/InlineAsm.h

Lines changed: 91 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@
1717

1818
#include "llvm/ADT/StringRef.h"
1919
#include "llvm/IR/Value.h"
20+
#include "llvm/Support/ErrorHandling.h"
2021
#include <cassert>
2122
#include <string>
2223
#include <vector>
@@ -359,6 +360,96 @@ class InlineAsm final : public Value {
359360
RC = High - 1;
360361
return true;
361362
}
363+
364+
static std::vector<StringRef> getExtraInfoNames(unsigned ExtraInfo) {
365+
std::vector<StringRef> Result;
366+
if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
367+
Result.push_back("sideeffect");
368+
if (ExtraInfo & InlineAsm::Extra_MayLoad)
369+
Result.push_back("mayload");
370+
if (ExtraInfo & InlineAsm::Extra_MayStore)
371+
Result.push_back("maystore");
372+
if (ExtraInfo & InlineAsm::Extra_IsConvergent)
373+
Result.push_back("isconvergent");
374+
if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
375+
Result.push_back("alignstack");
376+
377+
AsmDialect Dialect =
378+
InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect));
379+
380+
if (Dialect == InlineAsm::AD_ATT)
381+
Result.push_back("attdialect");
382+
if (Dialect == InlineAsm::AD_Intel)
383+
Result.push_back("inteldialect");
384+
385+
return Result;
386+
}
387+
388+
static StringRef getKindName(unsigned Kind) {
389+
switch (Kind) {
390+
case InlineAsm::Kind_RegUse:
391+
return "reguse";
392+
case InlineAsm::Kind_RegDef:
393+
return "regdef";
394+
case InlineAsm::Kind_RegDefEarlyClobber:
395+
return "regdef-ec";
396+
case InlineAsm::Kind_Clobber:
397+
return "clobber";
398+
case InlineAsm::Kind_Imm:
399+
return "imm";
400+
case InlineAsm::Kind_Mem:
401+
return "mem";
402+
default:
403+
llvm_unreachable("Unknown operand kind");
404+
}
405+
}
406+
407+
static StringRef getMemConstraintName(unsigned Constraint) {
408+
switch (Constraint) {
409+
case InlineAsm::Constraint_es:
410+
return "es";
411+
case InlineAsm::Constraint_i:
412+
return "i";
413+
case InlineAsm::Constraint_m:
414+
return "m";
415+
case InlineAsm::Constraint_o:
416+
return "o";
417+
case InlineAsm::Constraint_v:
418+
return "v";
419+
case InlineAsm::Constraint_Q:
420+
return "Q";
421+
case InlineAsm::Constraint_R:
422+
return "R";
423+
case InlineAsm::Constraint_S:
424+
return "S";
425+
case InlineAsm::Constraint_T:
426+
return "T";
427+
case InlineAsm::Constraint_Um:
428+
return "Um";
429+
case InlineAsm::Constraint_Un:
430+
return "Un";
431+
case InlineAsm::Constraint_Uq:
432+
return "Uq";
433+
case InlineAsm::Constraint_Us:
434+
return "Us";
435+
case InlineAsm::Constraint_Ut:
436+
return "Ut";
437+
case InlineAsm::Constraint_Uv:
438+
return "Uv";
439+
case InlineAsm::Constraint_Uy:
440+
return "Uy";
441+
case InlineAsm::Constraint_X:
442+
return "X";
443+
case InlineAsm::Constraint_Z:
444+
return "Z";
445+
case InlineAsm::Constraint_ZC:
446+
return "ZC";
447+
case InlineAsm::Constraint_Zy:
448+
return "Zy";
449+
default:
450+
llvm_unreachable("Unknown memory constraint");
451+
}
452+
}
362453
};
363454

364455
} // end namespace llvm

‎llvm/lib/CodeGen/MIRPrinter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -860,7 +860,7 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
860860
bool ShouldPrintRegisterTies, LLT TypeToPrint,
861861
bool PrintDef) {
862862
const MachineOperand &Op = MI.getOperand(OpIdx);
863-
std::string MOComment = TII->createMIROperandComment(MI, Op, OpIdx);
863+
std::string MOComment = TII->createMIROperandComment(MI, Op, OpIdx, TRI);
864864

865865
switch (Op.getType()) {
866866
case MachineOperand::MO_Immediate:

‎llvm/lib/CodeGen/MachineInstr.cpp

Lines changed: 3 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -1669,15 +1669,8 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
16691669
// Pretty print the inline asm operand descriptor.
16701670
OS << '$' << AsmOpCount++;
16711671
unsigned Flag = MO.getImm();
1672-
switch (InlineAsm::getKind(Flag)) {
1673-
case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1674-
case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1675-
case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1676-
case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1677-
case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1678-
case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1679-
default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1680-
}
1672+
OS << ":[";
1673+
OS << InlineAsm::getKindName(InlineAsm::getKind(Flag));
16811674

16821675
unsigned RCID = 0;
16831676
if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
@@ -1690,29 +1683,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
16901683

16911684
if (InlineAsm::isMemKind(Flag)) {
16921685
unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1693-
switch (MCID) {
1694-
case InlineAsm::Constraint_es: OS << ":es"; break;
1695-
case InlineAsm::Constraint_i: OS << ":i"; break;
1696-
case InlineAsm::Constraint_m: OS << ":m"; break;
1697-
case InlineAsm::Constraint_o: OS << ":o"; break;
1698-
case InlineAsm::Constraint_v: OS << ":v"; break;
1699-
case InlineAsm::Constraint_Q: OS << ":Q"; break;
1700-
case InlineAsm::Constraint_R: OS << ":R"; break;
1701-
case InlineAsm::Constraint_S: OS << ":S"; break;
1702-
case InlineAsm::Constraint_T: OS << ":T"; break;
1703-
case InlineAsm::Constraint_Um: OS << ":Um"; break;
1704-
case InlineAsm::Constraint_Un: OS << ":Un"; break;
1705-
case InlineAsm::Constraint_Uq: OS << ":Uq"; break;
1706-
case InlineAsm::Constraint_Us: OS << ":Us"; break;
1707-
case InlineAsm::Constraint_Ut: OS << ":Ut"; break;
1708-
case InlineAsm::Constraint_Uv: OS << ":Uv"; break;
1709-
case InlineAsm::Constraint_Uy: OS << ":Uy"; break;
1710-
case InlineAsm::Constraint_X: OS << ":X"; break;
1711-
case InlineAsm::Constraint_Z: OS << ":Z"; break;
1712-
case InlineAsm::Constraint_ZC: OS << ":ZC"; break;
1713-
case InlineAsm::Constraint_Zy: OS << ":Zy"; break;
1714-
default: OS << ":?"; break;
1715-
}
1686+
OS << ":" << InlineAsm::getMemConstraintName(MCID);
17161687
}
17171688

17181689
unsigned TiedTo = 0;

‎llvm/lib/CodeGen/TargetInstrInfo.cpp

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1322,4 +1322,60 @@ bool TargetInstrInfo::getInsertSubregInputs(
13221322
return true;
13231323
}
13241324

1325+
// Returns a MIRPrinter comment for this machine operand.
1326+
std::string TargetInstrInfo::createMIROperandComment(
1327+
const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,
1328+
const TargetRegisterInfo *TRI) const {
1329+
1330+
if (!MI.isInlineAsm())
1331+
return "";
1332+
1333+
std::string Flags;
1334+
raw_string_ostream OS(Flags);
1335+
1336+
if (OpIdx == InlineAsm::MIOp_ExtraInfo) {
1337+
// Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1338+
unsigned ExtraInfo = Op.getImm();
1339+
bool First = true;
1340+
for (StringRef Info : InlineAsm::getExtraInfoNames(ExtraInfo)) {
1341+
if (!First)
1342+
OS << " ";
1343+
First = false;
1344+
OS << Info;
1345+
}
1346+
1347+
return OS.str();
1348+
}
1349+
1350+
int FlagIdx = MI.findInlineAsmFlagIdx(OpIdx);
1351+
if (FlagIdx < 0 || (unsigned)FlagIdx != OpIdx)
1352+
return "";
1353+
1354+
assert(Op.isImm() && "Expected flag operand to be an immediate");
1355+
// Pretty print the inline asm operand descriptor.
1356+
unsigned Flag = Op.getImm();
1357+
unsigned Kind = InlineAsm::getKind(Flag);
1358+
OS << InlineAsm::getKindName(Kind);
1359+
1360+
unsigned RCID = 0;
1361+
if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1362+
InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1363+
if (TRI) {
1364+
OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1365+
} else
1366+
OS << ":RC" << RCID;
1367+
}
1368+
1369+
if (InlineAsm::isMemKind(Flag)) {
1370+
unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1371+
OS << ":" << InlineAsm::getMemConstraintName(MCID);
1372+
}
1373+
1374+
unsigned TiedTo = 0;
1375+
if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1376+
OS << " tiedto:$" << TiedTo;
1377+
1378+
return OS.str();
1379+
}
1380+
13251381
TargetInstrInfo::PipelinerLoopInfo::~PipelinerLoopInfo() {}

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -495,10 +495,17 @@ bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const {
495495
return PIdx != -1 && MI.getOperand(PIdx).getImm() != ARMCC::AL;
496496
}
497497

498-
std::string ARMBaseInstrInfo::createMIROperandComment(const MachineInstr &MI,
499-
const MachineOperand &Op,
500-
unsigned OpIdx) const {
501-
// Only support immediates for now.
498+
std::string ARMBaseInstrInfo::createMIROperandComment(
499+
const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,
500+
const TargetRegisterInfo *TRI) const {
501+
502+
// First, let's see if there is a generic comment for this operand
503+
std::string GenericComment =
504+
TargetInstrInfo::createMIROperandComment(MI, Op, OpIdx, TRI);
505+
if (!GenericComment.empty())
506+
return GenericComment;
507+
508+
// If not, check if we have an immediate operand.
502509
if (Op.getType() != MachineOperand::MO_Immediate)
503510
return std::string();
504511

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.h

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -152,9 +152,10 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
152152
bool isPredicated(const MachineInstr &MI) const override;
153153

154154
// MIR printer helper function to annotate Operands with a comment.
155-
std::string createMIROperandComment(const MachineInstr &MI,
156-
const MachineOperand &Op,
157-
unsigned OpIdx) const override;
155+
std::string
156+
createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
157+
unsigned OpIdx,
158+
const TargetRegisterInfo *TRI) const override;
158159

159160
ARMCC::CondCodes getPredicate(const MachineInstr &MI) const {
160161
int PIdx = MI.findFirstPredOperandIdx();

‎llvm/test/CodeGen/AArch64/seqpairspill.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ body: |
1616
%1 : xseqpairsclass = IMPLICIT_DEF
1717
%2 : gpr64common = IMPLICIT_DEF
1818
%0 = CASPALX %0, %1, %2
19-
INLINEASM &" ", 0, 0, implicit def dead $x0, implicit def dead $x1, implicit def dead $x2, implicit def dead $x3, implicit def dead $x4, implicit def dead $x5, implicit def dead $x6, implicit def dead $x7, implicit def dead $x8, implicit def dead $x9, implicit def dead $x10, implicit def dead $x11, implicit def dead $x12, implicit def dead $x13, implicit def dead $x14, implicit def dead $x15, implicit def dead $x16, implicit def dead $x17, implicit def dead $x18, implicit def dead $x19, implicit def dead $x20, implicit def dead $x21, implicit def dead $x22, implicit def dead $x23, implicit def dead $x24, implicit def dead $x25, implicit def dead $x26, implicit def dead $x27, implicit def dead $x28, implicit def dead $fp, implicit def dead $lr
19+
INLINEASM &" ", 0, 12, implicit def dead $x0, implicit def dead $x1, implicit def dead $x2, implicit def dead $x3, implicit def dead $x4, implicit def dead $x5, implicit def dead $x6, implicit def dead $x7, implicit def dead $x8, implicit def dead $x9, implicit def dead $x10, implicit def dead $x11, implicit def dead $x12, implicit def dead $x13, implicit def dead $x14, implicit def dead $x15, implicit def dead $x16, implicit def dead $x17, implicit def dead $x18, implicit def dead $x19, implicit def dead $x20, implicit def dead $x21, implicit def dead $x22, implicit def dead $x23, implicit def dead $x24, implicit def dead $x25, implicit def dead $x26, implicit def dead $x27, implicit def dead $x28, implicit def dead $fp, implicit def dead $lr
2020
$xzr = COPY %0.sube64
2121
$xzr = COPY %0.subo64
2222
...
@@ -36,7 +36,7 @@ body: |
3636
%1 : wseqpairsclass = IMPLICIT_DEF
3737
%2 : gpr64common = IMPLICIT_DEF
3838
%0 = CASPALW %0, %1, %2
39-
INLINEASM &" ", 0, 0, implicit def dead $x0, implicit def dead $x1, implicit def dead $x2, implicit def dead $x3, implicit def dead $x4, implicit def dead $x5, implicit def dead $x6, implicit def dead $x7, implicit def dead $x8, implicit def dead $x9, implicit def dead $x10, implicit def dead $x11, implicit def dead $x12, implicit def dead $x13, implicit def dead $x14, implicit def dead $x15, implicit def dead $x16, implicit def dead $x17, implicit def dead $x18, implicit def dead $x19, implicit def dead $x20, implicit def dead $x21, implicit def dead $x22, implicit def dead $x23, implicit def dead $x24, implicit def dead $x25, implicit def dead $x26, implicit def dead $x27, implicit def dead $x28, implicit def dead $fp, implicit def dead $lr
39+
INLINEASM &" ", 0, 12, implicit def dead $x0, implicit def dead $x1, implicit def dead $x2, implicit def dead $x3, implicit def dead $x4, implicit def dead $x5, implicit def dead $x6, implicit def dead $x7, implicit def dead $x8, implicit def dead $x9, implicit def dead $x10, implicit def dead $x11, implicit def dead $x12, implicit def dead $x13, implicit def dead $x14, implicit def dead $x15, implicit def dead $x16, implicit def dead $x17, implicit def dead $x18, implicit def dead $x19, implicit def dead $x20, implicit def dead $x21, implicit def dead $x22, implicit def dead $x23, implicit def dead $x24, implicit def dead $x25, implicit def dead $x26, implicit def dead $x27, implicit def dead $x28, implicit def dead $fp, implicit def dead $lr
4040
$xzr = COPY %0.sube32
4141
$xzr = COPY %0.subo32
4242
...

‎llvm/test/CodeGen/AMDGPU/endpgm-dce.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -331,7 +331,7 @@ body: |
331331
%1 = IMPLICIT_DEF
332332
$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
333333
%2:sreg_64 = IMPLICIT_DEF
334-
INLINEASM &"", 0, 0
334+
INLINEASM &"", 0
335335
S_ENDPGM 0
336336
...
337337

@@ -353,6 +353,6 @@ body: |
353353
%1 = IMPLICIT_DEF
354354
$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
355355
%2:sreg_64 = IMPLICIT_DEF
356-
INLINEASM &"", 1, 0
356+
INLINEASM &"", 1
357357
S_ENDPGM 0
358358
...

‎llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,7 @@ body: |
7373
# (1) %0.sub0 + %0.sub0 and (2) %0.sub1 + %0.sub1
7474
# Check that renaming (2) does not inadvertently rename (1).
7575
# CHECK-LABEL: name: test2
76-
# CHECK: INLINEASM &"", 32, 327690, def undef %0.sub0, 327690, def dead %1.sub1, 2147483657, undef %0.sub0(tied-def 3), 2147549193, %1.sub1(tied-def 5)
76+
# CHECK: INLINEASM &"", 32 /* isconvergent attdialect */, 327690 /* regdef:SReg_1_XEXEC_with_sub0 */, def undef %0.sub0, 327690 /* regdef:SReg_1_XEXEC_with_sub0 */, def dead %1.sub1, 2147483657 /* reguse tiedto:$0 */, undef %0.sub0(tied-def 3), 2147549193 /* reguse tiedto:$1 */, %1.sub1(tied-def 5)
7777
name: test2
7878
body: |
7979
bb.0:

‎llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ body: |
3333
; CHECK: dead %9:vreg_128 = DS_READ_B128_gfx9 [[V_ADD_U32_e32_]], 0, 0, implicit $exec
3434
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
3535
; CHECK: undef %11.sub1:vreg_512 = COPY [[COPY]].sub1
36-
; CHECK: INLINEASM &"", 1, 851978, def dead [[COPY1]], 851978, def dead [[COPY]].sub1, 2147483657, [[COPY1]], 2147549193, [[COPY]].sub1
36+
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def dead [[COPY1]], 851978 /* regdef:VRegOrLds_32 */, def dead [[COPY]].sub1, 2147483657 /* reguse tiedto:$0 */, [[COPY1]], 2147549193 /* reguse tiedto:$1 */, [[COPY]].sub1
3737
; CHECK: %11.sub0:vreg_512 = COPY [[COPY]].sub0
3838
; CHECK: %11.sub3:vreg_512 = COPY [[COPY]].sub3
3939
; CHECK: dead %10:vgpr_32 = V_ADD_I32_e32 4, [[V_MOV_B32_e32_1]], implicit-def dead $vcc, implicit $exec

‎llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -36,18 +36,18 @@ body: |
3636
; CHECK: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
3737
; CHECK: bb.1:
3838
; CHECK: successors: %bb.1(0x80000000)
39-
; CHECK: INLINEASM &"", 1, 851978, def dead %11
39+
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def dead %11
4040
; CHECK: GLOBAL_STORE_DWORD undef %12:vreg_64, [[BUFFER_LOAD_DWORD_OFFEN]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
4141
; CHECK: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
4242
; CHECK: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
4343
; CHECK: [[DS_READ_B64_gfx9_:%[0-9]+]]:vreg_64 = DS_READ_B64_gfx9 undef %14:vgpr_32, 0, 0, implicit $exec :: (load 8, addrspace 3)
44-
; CHECK: INLINEASM &"def $0 $1", 1, 851978, def %15, 851978, def %16
44+
; CHECK: INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def %15, 851978 /* regdef:VRegOrLds_32 */, def %16
4545
; CHECK: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec
4646
; CHECK: [[DS_READ_B32_gfx9_1:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec
4747
; CHECK: [[DS_READ_B32_gfx9_2:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 undef %20:vgpr_32, 0, 0, implicit $exec
48-
; CHECK: INLINEASM &"def $0 $1", 1, 851978, def %21, 851978, def %22
48+
; CHECK: INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def %21, 851978 /* regdef:VRegOrLds_32 */, def %22
4949
; CHECK: [[DS_READ_B32_gfx9_3:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec
50-
; CHECK: INLINEASM &"", 1, 851978, def dead [[V_MOV_B32_e32_2]], 851978, def dead [[V_MOV_B32_e32_3]], 851977, [[DS_READ_B64_gfx9_]].sub0, 2147483657, [[V_MOV_B32_e32_2]](tied-def 3), 2147549193, [[V_MOV_B32_e32_3]](tied-def 5), 851977, %15, 851977, %16, 851977, [[DS_READ_B32_gfx9_1]], 851977, [[DS_READ_B32_gfx9_]], 851977, [[DS_READ_B32_gfx9_3]], 851977, [[DS_READ_B32_gfx9_2]]
50+
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def dead [[V_MOV_B32_e32_2]], 851978 /* regdef:VRegOrLds_32 */, def dead [[V_MOV_B32_e32_3]], 851977 /* reguse:VRegOrLds_32 */, [[DS_READ_B64_gfx9_]].sub0, 2147483657 /* reguse tiedto:$0 */, [[V_MOV_B32_e32_2]](tied-def 3), 2147549193 /* reguse tiedto:$1 */, [[V_MOV_B32_e32_3]](tied-def 5), 851977 /* reguse:VRegOrLds_32 */, %15, 851977 /* reguse:VRegOrLds_32 */, %16, 851977 /* reguse:VRegOrLds_32 */, [[DS_READ_B32_gfx9_1]], 851977 /* reguse:VRegOrLds_32 */, [[DS_READ_B32_gfx9_]], 851977 /* reguse:VRegOrLds_32 */, [[DS_READ_B32_gfx9_3]], 851977 /* reguse:VRegOrLds_32 */, [[DS_READ_B32_gfx9_2]]
5151
; CHECK: %5.sub1:vreg_64 = COPY [[V_MOV_B32_e32_]]
5252
; CHECK: DS_WRITE_B32_gfx9 undef %28:vgpr_32, %21, 0, 0, implicit $exec :: (store 4, addrspace 3)
5353
; CHECK: DS_WRITE_B32_gfx9 undef %29:vgpr_32, %22, 0, 0, implicit $exec :: (store 4, addrspace 3)
@@ -69,7 +69,7 @@ body: |
6969
; CHECK: undef %42.sub0:sgpr_64 = V_READFIRSTLANE_B32 %38.sub0, implicit $exec
7070
; CHECK: %42.sub1:sgpr_64 = V_READFIRSTLANE_B32 %40.sub1, implicit $exec
7171
; CHECK: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %42, 0, 0, 0 :: (load 4, addrspace 1)
72-
; CHECK: INLINEASM &"", 1
72+
; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */
7373
; CHECK: [[DS_READ_B32_gfx9_4:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 undef %45:vgpr_32, 0, 0, implicit $exec :: (load 4, addrspace 3)
7474
; CHECK: GLOBAL_STORE_DWORD undef %46:vreg_64, [[DS_READ_B32_gfx9_4]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
7575
; CHECK: %31.sub0:vreg_64 = COPY [[S_LOAD_DWORD_IMM]], implicit $exec

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