@@ -2574,8 +2574,6 @@ LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
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assert (NumOps <= 3 && " expected instrution with 1 result and 1-3 sources" );
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- LLT GCDTys[3 ];
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- LLT LCMTys[3 ];
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SmallVector<Register, 8 > ExtractedRegs[3 ];
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SmallVector<Register, 8 > Parts;
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@@ -2584,11 +2582,11 @@ LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
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for (int I = 0 ; I != NumOps; ++I) {
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Register SrcReg = MI.getOperand (I + 1 ).getReg ();
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LLT SrcTy = MRI.getType (SrcReg);
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- GCDTys[I] = extractGCDType (ExtractedRegs[I], SrcTy, NarrowTy, SrcReg);
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+ LLT GCDTy = extractGCDType (ExtractedRegs[I], SrcTy, NarrowTy, SrcReg);
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// Build a sequence of NarrowTy pieces in ExtractedRegs for this operand.
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- LCMTys[I] = buildLCMMergePieces (SrcTy, NarrowTy, GCDTys [I],
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- ExtractedRegs[I], TargetOpcode::G_ANYEXT);
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+ buildLCMMergePieces (SrcTy, NarrowTy, GCDTy, ExtractedRegs [I],
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+ TargetOpcode::G_ANYEXT);
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}
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SmallVector<Register, 8 > ResultRegs;
@@ -2620,7 +2618,9 @@ LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
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ResultRegs.append (NumUndefParts, MIRBuilder.buildUndef (NarrowTy).getReg (0 ));
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// Extract the possibly padded result to the original result register.
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- buildWidenedRemergeToDst (DstReg, LCMTys[0 ], ResultRegs);
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+ LLT DstTy = MRI.getType (DstReg);
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+ LLT LCMTy = getLCMType (DstTy, NarrowTy);
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+ buildWidenedRemergeToDst (DstReg, LCMTy, ResultRegs);
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MI.eraseFromParent ();
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return Legalized;
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