Skip to content
View MEESAM749's full-sized avatar
  • Rawalpindi/Islamabad

Highlights

  • Pro

Block or report MEESAM749

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
MEESAM749/README.md

👋 Hi, I'm Meesam!

🔹 Passionate about Embedded Systems & Hardware Development
🔹 Exploring Microcontrollers, FPGAs, and Low-Level Programming
🔹 Open to collaborating on Embedded Systems projects

📩 Reach me at: mmeesamtammar@gmail.com

🚀 Currently working on:
RISC-V Pipelined Processor Simulation in Verilog

Pinned Loading

  1. ESP32-Home-Underground-Water-Pump-Automation-System Public

    Automating an underground water pump using LoRa modules.

    C++ 1

  2. Single-Cycle-Non-Pipelined-MIPS-32-Processor Public

    This is a simulation of the MIPS32 Single Cycle Processor on Xilinx ISE written in Verilog.

    C 1

  3. Hospital-Emergency-Department-Simulator Public

    A satistical model based software to simulate a real emergency department to optimize resource allocation. Written in C++.

    C++

  4. RISC-V-PipelinedProcessor Public

    RISC-V Pipelined Processor simulation in Verilog on Xilinx ISE

    HTML 1

  5. DigitalClockWithAlarm Public

    This is a hardware implementation of a basic digital clock using logic gates and some counter ICs and a clock generator.