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[DAGCombiner] Don't fold zext_vector_inreg/sext_vector_inreg(undef) to undef. Fold to 0.
zext_vector_inreg needs to produces 0s in the extended bits and sext_vector_inreg needs to produce upper bits that are all the same. So we should fold them to a 0 vector instead of undef. Fixes PR46585.
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2 files changed

+5
-3
lines changed

2 files changed

+5
-3
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llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11086,8 +11086,9 @@ SDValue DAGCombiner::visitSIGN_EXTEND_VECTOR_INREG(SDNode *N) {
1108611086
SDValue N0 = N->getOperand(0);
1108711087
EVT VT = N->getValueType(0);
1108811088

11089+
// sext_vector_inreg(undef) = 0 because the top bit will all be the same.
1108911090
if (N0.isUndef())
11090-
return DAG.getUNDEF(VT);
11091+
return DAG.getConstant(0, SDLoc(N), VT);
1109111092

1109211093
if (SDValue Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes))
1109311094
return Res;
@@ -11102,8 +11103,9 @@ SDValue DAGCombiner::visitZERO_EXTEND_VECTOR_INREG(SDNode *N) {
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SDValue N0 = N->getOperand(0);
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EVT VT = N->getValueType(0);
1110411105

11106+
// zext_vector_inreg(undef) = 0 because the top bits will be zero.
1110511107
if (N0.isUndef())
11106-
return DAG.getUNDEF(VT);
11108+
return DAG.getConstant(0, SDLoc(N), VT);
1110711109

1110811110
if (SDValue Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes))
1110911111
return Res;

llvm/test/CodeGen/X86/pr46585.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
define void @spam() local_unnamed_addr {
88
; CHECK-LABEL: spam:
99
; CHECK: ## %bb.0: ## %bb
10-
; CHECK-NEXT: pmovmskb %xmm0, %eax
10+
; CHECK-NEXT: xorl %eax, %eax
1111
; CHECK-NEXT: testb %al, %al
1212
; CHECK-NEXT: je LBB0_2
1313
; CHECK-NEXT: ## %bb.1: ## %bb9

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