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Revert "[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics"
This reverts commit 030d334. This commit is causing build failures
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llvm/include/llvm/CodeGen/MachineScheduler.h

Lines changed: 36 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -656,15 +656,15 @@ class ResourceSegments {
656656
///
657657
/// Consider an instruction that uses resources X0, X1 and X2 as follows:
658658
///
659-
/// X0 X1 X1 X2 +--------+-------------+--------------+
660-
/// |Resource|AcquireAtCycle|ReleaseAtCycle|
661-
/// +--------+-------------+--------------+
662-
/// | X0 | 0 | 1 |
663-
/// +--------+-------------+--------------+
664-
/// | X1 | 1 | 3 |
665-
/// +--------+-------------+--------------+
666-
/// | X2 | 3 | 4 |
667-
/// +--------+-------------+--------------+
659+
/// X0 X1 X1 X2 +--------+------------+------+
660+
/// |Resource|StartAtCycle|Cycles|
661+
/// +--------+------------+------+
662+
/// | X0 | 0 | 1 |
663+
/// +--------+------------+------+
664+
/// | X1 | 1 | 3 |
665+
/// +--------+------------+------+
666+
/// | X2 | 3 | 4 |
667+
/// +--------+------------+------+
668668
///
669669
/// If we can schedule the instruction at cycle C, we need to
670670
/// compute the interval of the resource as follows:
@@ -685,7 +685,7 @@ class ResourceSegments {
685685
/// of an instruction that can be scheduled at cycle C in top-down
686686
/// scheduling is:
687687
///
688-
/// [C+AcquireAtCycle, C+ReleaseAtCycle)
688+
/// [C+StartAtCycle, C+Cycles)
689689
///
690690
///
691691
/// # BOTTOM UP SCHEDULING
@@ -709,28 +709,28 @@ class ResourceSegments {
709709
/// of an instruction that can be scheduled at cycle C in bottom-up
710710
/// scheduling is:
711711
///
712-
/// [C-ReleaseAtCycle+1, C-AcquireAtCycle+1)
712+
/// [C-Cycle+1, C-StartAtCycle+1)
713713
///
714714
///
715715
/// NOTE: In both cases, the number of cycles booked by a
716-
/// resources is the value (ReleaseAtCycle - AcquireAtCycle).
717-
static IntervalTy getResourceIntervalBottom(unsigned C, unsigned AcquireAtCycle,
718-
unsigned ReleaseAtCycle) {
719-
return std::make_pair<long, long>((long)C - (long)ReleaseAtCycle + 1L,
720-
(long)C - (long)AcquireAtCycle + 1L);
716+
/// resources is the value (Cycle - StartAtCycles).
717+
static IntervalTy getResourceIntervalBottom(unsigned C, unsigned StartAtCycle,
718+
unsigned Cycle) {
719+
return std::make_pair<long, long>((long)C - (long)Cycle + 1L,
720+
(long)C - (long)StartAtCycle + 1L);
721721
}
722-
static IntervalTy getResourceIntervalTop(unsigned C, unsigned AcquireAtCycle,
723-
unsigned ReleaseAtCycle) {
724-
return std::make_pair<long, long>((long)C + (long)AcquireAtCycle,
725-
(long)C + (long)ReleaseAtCycle);
722+
static IntervalTy getResourceIntervalTop(unsigned C, unsigned StartAtCycle,
723+
unsigned Cycle) {
724+
return std::make_pair<long, long>((long)C + (long)StartAtCycle,
725+
(long)C + (long)Cycle);
726726
}
727727

728728
private:
729729
/// Finds the first cycle in which a resource can be allocated.
730730
///
731731
/// The function uses the \param IntervalBuider [*] to build a
732732
/// resource interval [a, b[ out of the input parameters \param
733-
/// CurrCycle, \param AcquireAtCycle and \param ReleaseAtCycle.
733+
/// CurrCycle, \param StartAtCycle and \param Cycle.
734734
///
735735
/// The function then loops through the intervals in the ResourceSegments
736736
/// and shifts the interval [a, b[ and the ReturnCycle to the
@@ -744,7 +744,7 @@ class ResourceSegments {
744744
/// c 1 2 3 4 5 6 7 8 9 10 ... ---> (time
745745
/// flow)
746746
/// ResourceSegments... [---) [-------) [-----------)
747-
/// c [1 3[ -> AcquireAtCycle=1, ReleaseAtCycle=3
747+
/// c [1 3[ -> StartAtCycle=1, Cycles=3
748748
/// ++c [1 3)
749749
/// ++c [1 3)
750750
/// ++c [1 3)
@@ -772,25 +772,24 @@ class ResourceSegments {
772772
/// [*] See \ref `getResourceIntervalTop` and
773773
/// \ref `getResourceIntervalBottom` to see how such resource intervals
774774
/// are built.
775-
unsigned getFirstAvailableAt(
776-
unsigned CurrCycle, unsigned AcquireAtCycle, unsigned ReleaseAtCycle,
777-
std::function<IntervalTy(unsigned, unsigned, unsigned)> IntervalBuilder)
778-
const;
775+
unsigned
776+
getFirstAvailableAt(unsigned CurrCycle, unsigned StartAtCycle, unsigned Cycle,
777+
std::function<IntervalTy(unsigned, unsigned, unsigned)>
778+
IntervalBuilder) const;
779779

780780
public:
781781
/// getFirstAvailableAtFromBottom and getFirstAvailableAtFromTop
782782
/// should be merged in a single function in which a function that
783783
/// creates the `NewInterval` is passed as a parameter.
784784
unsigned getFirstAvailableAtFromBottom(unsigned CurrCycle,
785-
unsigned AcquireAtCycle,
786-
unsigned ReleaseAtCycle) const {
787-
return getFirstAvailableAt(CurrCycle, AcquireAtCycle, ReleaseAtCycle,
785+
unsigned StartAtCycle,
786+
unsigned Cycle) const {
787+
return getFirstAvailableAt(CurrCycle, StartAtCycle, Cycle,
788788
getResourceIntervalBottom);
789789
}
790-
unsigned getFirstAvailableAtFromTop(unsigned CurrCycle,
791-
unsigned AcquireAtCycle,
792-
unsigned ReleaseAtCycle) const {
793-
return getFirstAvailableAt(CurrCycle, AcquireAtCycle, ReleaseAtCycle,
790+
unsigned getFirstAvailableAtFromTop(unsigned CurrCycle, unsigned StartAtCycle,
791+
unsigned Cycle) const {
792+
return getFirstAvailableAt(CurrCycle, StartAtCycle, Cycle,
794793
getResourceIntervalTop);
795794
}
796795

@@ -1007,13 +1006,13 @@ class SchedBoundary {
10071006
unsigned getLatencyStallCycles(SUnit *SU);
10081007

10091008
unsigned getNextResourceCycleByInstance(unsigned InstanceIndex,
1010-
unsigned ReleaseAtCycle,
1011-
unsigned AcquireAtCycle);
1009+
unsigned Cycles,
1010+
unsigned StartAtCycle);
10121011

10131012
std::pair<unsigned, unsigned> getNextResourceCycle(const MCSchedClassDesc *SC,
10141013
unsigned PIdx,
1015-
unsigned ReleaseAtCycle,
1016-
unsigned AcquireAtCycle);
1014+
unsigned Cycles,
1015+
unsigned StartAtCycle);
10171016

10181017
bool isUnbufferedGroup(unsigned PIdx) const {
10191018
return SchedModel->getProcResource(PIdx)->SubUnitsIdxBegin &&

llvm/include/llvm/CodeGen/MachineTraceMetrics.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -143,7 +143,7 @@ class MachineTraceMetrics : public MachineFunctionPass {
143143
/// The getResources() function above must have been called first.
144144
///
145145
/// These numbers have already been scaled by SchedModel.getResourceFactor().
146-
ArrayRef<unsigned> getProcReleaseAtCycles(unsigned MBBNum) const;
146+
ArrayRef<unsigned> getProcResourceCycles(unsigned MBBNum) const;
147147

148148
/// A virtual register or regunit required by a basic block or its trace
149149
/// successors.
@@ -404,9 +404,9 @@ class MachineTraceMetrics : public MachineFunctionPass {
404404
// Cycles consumed on each processor resource per block.
405405
// The number of processor resource kinds is constant for a given subtarget,
406406
// but it is not known at compile time. The number of cycles consumed by
407-
// block B on processor resource R is at ProcReleaseAtCycles[B*Kinds + R]
407+
// block B on processor resource R is at ProcResourceCycles[B*Kinds + R]
408408
// where Kinds = SchedModel.getNumProcResourceKinds().
409-
SmallVector<unsigned, 0> ProcReleaseAtCycles;
409+
SmallVector<unsigned, 0> ProcResourceCycles;
410410

411411
// One ensemble per strategy.
412412
Ensemble

llvm/include/llvm/MC/MCSchedule.h

Lines changed: 11 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -60,21 +60,24 @@ struct MCProcResourceDesc {
6060

6161
/// Identify one of the processor resource kinds consumed by a
6262
/// particular scheduling class for the specified number of cycles.
63+
/// TODO: consider renaming the field `StartAtCycle` and `Cycles` to
64+
/// `AcquireAtCycle` and `ReleaseAtCycle` respectively, to stress the
65+
/// fact that resource allocation is now represented as an interval,
66+
/// relatively to the issue cycle of the instruction.
6367
struct MCWriteProcResEntry {
6468
uint16_t ProcResourceIdx;
6569
/// Cycle at which the resource will be released by an instruction,
6670
/// relatively to the cycle in which the instruction is issued
6771
/// (assuming no stalls inbetween).
68-
uint16_t ReleaseAtCycle;
69-
/// Cycle at which the resource will be aquired by an instruction,
72+
uint16_t Cycles;
73+
/// Cycle at which the resource will be grabbed by an instruction,
7074
/// relatively to the cycle in which the instruction is issued
7175
/// (assuming no stalls inbetween).
72-
uint16_t AcquireAtCycle;
76+
uint16_t StartAtCycle;
7377

7478
bool operator==(const MCWriteProcResEntry &Other) const {
75-
return ProcResourceIdx == Other.ProcResourceIdx &&
76-
ReleaseAtCycle == Other.ReleaseAtCycle &&
77-
AcquireAtCycle == Other.AcquireAtCycle;
79+
return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles &&
80+
StartAtCycle == Other.StartAtCycle;
7881
}
7982
};
8083

@@ -223,12 +226,12 @@ struct MCExtraProcessorInfo {
223226
/// consistent. Inaccuracies arise when instructions have different execution
224227
/// delays relative to each other, in addition to their intrinsic latency. Those
225228
/// special cases can be handled by TableGen constructs such as, ReadAdvance,
226-
/// which reduces latency when reading data, and ReleaseAtCycles, which consumes
229+
/// which reduces latency when reading data, and ResourceCycles, which consumes
227230
/// a processor resource when writing data for a number of abstract
228231
/// cycles.
229232
///
230233
/// TODO: One tool currently missing is the ability to add a delay to
231-
/// ReleaseAtCycles. That would be easy to add and would likely cover all cases
234+
/// ResourceCycles. That would be easy to add and would likely cover all cases
232235
/// currently handled by the legacy itinerary tables.
233236
///
234237
/// A note on out-of-order execution and, more generally, instruction

llvm/include/llvm/MCA/HWEventListener.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ class HWInstructionEvent {
6363
// ResourceRef::second is a bitmask of the referenced sub-unit of the resource.
6464
using ResourceRef = std::pair<uint64_t, uint64_t>;
6565

66-
using ResourceUse = std::pair<ResourceRef, ReleaseAtCycles>;
66+
using ResourceUse = std::pair<ResourceRef, ResourceCycles>;
6767

6868
class HWInstructionIssuedEvent : public HWInstructionEvent {
6969
public:

llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -430,7 +430,7 @@ class ResourceManager {
430430

431431
void issueInstruction(
432432
const InstrDesc &Desc,
433-
SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &Pipes);
433+
SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &Pipes);
434434

435435
void cycleEvent(SmallVectorImpl<ResourceRef> &ResourcesFreed);
436436

llvm/include/llvm/MCA/HardwareUnits/Scheduler.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -136,7 +136,7 @@ class Scheduler : public HardwareUnit {
136136
/// Issue an instruction without updating the ready queue.
137137
void issueInstructionImpl(
138138
InstRef &IR,
139-
SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &Pipes);
139+
SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &Pipes);
140140

141141
// Identify instructions that have finished executing, and remove them from
142142
// the IssuedSet. References to executed instructions are added to input
@@ -202,7 +202,7 @@ class Scheduler : public HardwareUnit {
202202
/// result of this event.
203203
void issueInstruction(
204204
InstRef &IR,
205-
SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &Used,
205+
SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &Used,
206206
SmallVectorImpl<InstRef> &Pending,
207207
SmallVectorImpl<InstRef> &Ready);
208208

llvm/include/llvm/MCA/Support.h

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -48,12 +48,12 @@ template <typename T> char InstructionError<T>::ID;
4848
/// number of resources, are kept separate. This is used by the
4949
/// ResourcePressureView to calculate the average resource cycles
5050
/// per instruction/iteration.
51-
class ReleaseAtCycles {
51+
class ResourceCycles {
5252
unsigned Numerator, Denominator;
5353

5454
public:
55-
ReleaseAtCycles() : Numerator(0), Denominator(1) {}
56-
ReleaseAtCycles(unsigned Cycles, unsigned ResourceUnits = 1)
55+
ResourceCycles() : Numerator(0), Denominator(1) {}
56+
ResourceCycles(unsigned Cycles, unsigned ResourceUnits = 1)
5757
: Numerator(Cycles), Denominator(ResourceUnits) {}
5858

5959
operator double() const {
@@ -67,7 +67,7 @@ class ReleaseAtCycles {
6767
// Add the components of RHS to this instance. Instead of calculating
6868
// the final value here, we keep track of the numerator and denominator
6969
// separately, to reduce floating point error.
70-
ReleaseAtCycles &operator+=(const ReleaseAtCycles &RHS);
70+
ResourceCycles &operator+=(const ResourceCycles &RHS);
7171
};
7272

7373
/// Populates vector Masks with processor resource masks.
@@ -105,7 +105,7 @@ inline unsigned getResourceStateIndex(uint64_t Mask) {
105105
/// Compute the reciprocal block throughput from a set of processor resource
106106
/// cycles. The reciprocal block throughput is computed as the MAX between:
107107
/// - NumMicroOps / DispatchWidth
108-
/// - ProcReleaseAtCycles / #ProcResourceUnits (for every consumed resource).
108+
/// - ProcResourceCycles / #ProcResourceUnits (for every consumed resource).
109109
double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth,
110110
unsigned NumMicroOps,
111111
ArrayRef<unsigned> ProcResourceUsage);

llvm/include/llvm/Target/TargetSchedule.td

Lines changed: 7 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -147,7 +147,7 @@ class ProcResourceKind;
147147
// changes this to an in-order issue/dispatch resource. In this case,
148148
// the scheduler counts down from the cycle that the instruction
149149
// issues in-order, forcing a stall whenever a subsequent instruction
150-
// requires the same resource until the number of ReleaseAtCycles
150+
// requires the same resource until the number of ResourceCycles
151151
// specified in WriteRes expire. Setting BufferSize=1 changes this to
152152
// an in-order latency resource. In this case, the scheduler models
153153
// producer/consumer stalls between instructions that use the
@@ -254,14 +254,8 @@ class WriteSequence<list<SchedWrite> writes, int rep = 1> : SchedWrite {
254254
// SchedModel ties these resources to a processor.
255255
class ProcWriteResources<list<ProcResourceKind> resources> {
256256
list<ProcResourceKind> ProcResources = resources;
257-
/// Cycle at which the resource will be released by an instruction,
258-
/// relatively to the cycle in which the instruction is issued
259-
/// (assuming no stalls inbetween).
260-
list<int> ReleaseAtCycles = [];
261-
/// Cycle at which the resource will be aquired by an instruction,
262-
/// relatively to the cycle in which the instruction is issued
263-
/// (assuming no stalls inbetween).
264-
list<int> AcquireAtCycles = [];
257+
list<int> ResourceCycles = [];
258+
list<int> StartAtCycles = [];
265259
int Latency = 1;
266260
int NumMicroOps = 1;
267261
bit BeginGroup = false;
@@ -291,12 +285,12 @@ class ProcWriteResources<list<ProcResourceKind> resources> {
291285
// itinerary classes to the subtarget's SchedWrites.
292286
//
293287
// ProcResources indicates the set of resources consumed by the write.
294-
// Optionally, ReleaseAtCycles indicates the number of cycles the
295-
// resource is consumed. Each ReleaseAtCycles item is paired with the
296-
// ProcResource item at the same position in its list. ReleaseAtCycles
288+
// Optionally, ResourceCycles indicates the number of cycles the
289+
// resource is consumed. Each ResourceCycles item is paired with the
290+
// ProcResource item at the same position in its list. ResourceCycles
297291
// can be `[]`: in that case, all resources are consumed for a single
298292
// cycle, regardless of latency, which models a fully pipelined processing
299-
// unit. A value of 0 for ReleaseAtCycles means that the resource must
293+
// unit. A value of 0 for ResourceCycles means that the resource must
300294
// be available but is not consumed, which is only relevant for
301295
// unbuffered resources.
302296
//

llvm/lib/CodeGen/MachinePipeliner.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1039,7 +1039,7 @@ struct FuncUnitSorter {
10391039
for (const MCWriteProcResEntry &PRE :
10401040
make_range(STI->getWriteProcResBegin(SCDesc),
10411041
STI->getWriteProcResEnd(SCDesc))) {
1042-
if (!PRE.ReleaseAtCycle)
1042+
if (!PRE.Cycles)
10431043
continue;
10441044
const MCProcResourceDesc *ProcResource =
10451045
STI->getSchedModel().getProcResource(PRE.ProcResourceIdx);
@@ -1082,7 +1082,7 @@ struct FuncUnitSorter {
10821082
for (const MCWriteProcResEntry &PRE :
10831083
make_range(STI->getWriteProcResBegin(SCDesc),
10841084
STI->getWriteProcResEnd(SCDesc))) {
1085-
if (!PRE.ReleaseAtCycle)
1085+
if (!PRE.Cycles)
10861086
continue;
10871087
Resources[PRE.ProcResourceIdx]++;
10881088
}
@@ -3092,7 +3092,7 @@ void ResourceManager::reserveResources(const MCSchedClassDesc *SCDesc,
30923092
assert(!UseDFA);
30933093
for (const MCWriteProcResEntry &PRE : make_range(
30943094
STI->getWriteProcResBegin(SCDesc), STI->getWriteProcResEnd(SCDesc)))
3095-
for (int C = Cycle; C < Cycle + PRE.ReleaseAtCycle; ++C)
3095+
for (int C = Cycle; C < Cycle + PRE.Cycles; ++C)
30963096
++MRT[positiveModulo(C, InitiationInterval)][PRE.ProcResourceIdx];
30973097

30983098
for (int C = Cycle; C < Cycle + SCDesc->NumMicroOps; ++C)
@@ -3104,7 +3104,7 @@ void ResourceManager::unreserveResources(const MCSchedClassDesc *SCDesc,
31043104
assert(!UseDFA);
31053105
for (const MCWriteProcResEntry &PRE : make_range(
31063106
STI->getWriteProcResBegin(SCDesc), STI->getWriteProcResEnd(SCDesc)))
3107-
for (int C = Cycle; C < Cycle + PRE.ReleaseAtCycle; ++C)
3107+
for (int C = Cycle; C < Cycle + PRE.Cycles; ++C)
31083108
--MRT[positiveModulo(C, InitiationInterval)][PRE.ProcResourceIdx];
31093109

31103110
for (int C = Cycle; C < Cycle + SCDesc->NumMicroOps; ++C)
@@ -3220,10 +3220,10 @@ int ResourceManager::calculateResMII() const {
32203220
if (SwpDebugResource) {
32213221
const MCProcResourceDesc *Desc =
32223222
SM.getProcResource(PRE.ProcResourceIdx);
3223-
dbgs() << Desc->Name << ": " << PRE.ReleaseAtCycle << ", ";
3223+
dbgs() << Desc->Name << ": " << PRE.Cycles << ", ";
32243224
}
32253225
});
3226-
ResourceCount[PRE.ProcResourceIdx] += PRE.ReleaseAtCycle;
3226+
ResourceCount[PRE.ProcResourceIdx] += PRE.Cycles;
32273227
}
32283228
LLVM_DEBUG(if (SwpDebugResource) dbgs() << "\n");
32293229
}

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