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[AMDGPU][DOC][NFC] Added GFX1030 assembler syntax description
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‎llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst

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**************************************************
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====================================================================================
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Syntax of Core GFX10 Instructions
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Syntax of GFX10 RDNA1 Instructions
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====================================================================================
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.. contents::
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Introduction
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============
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This document describes the syntax of *core* GFX10 instructions.
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This document describes the syntax of GFX10 RDNA1 (gfx1010) instructions.
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Notation
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========

‎llvm/docs/AMDGPU/AMDGPUAsmGFX1011.rst

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This document describes the syntax of *instructions specific to gfx1011 and gfx1012*.
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For a description of other gfx1011 and gfx1012 instructions see :doc:`Syntax of Core GFX10 Instructions<AMDGPUAsmGFX10>`.
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For a description of other gfx1011 and gfx1012 instructions see :doc:`Syntax of GFX10 RDNA1 Instructions<AMDGPUAsmGFX10>`.
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Notation
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========

‎llvm/docs/AMDGPU/AMDGPUAsmGFX1030.rst

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‎llvm/docs/AMDGPU/gfx1030_attr.rst

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_attr:
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attr
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====
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Interpolation attribute and channel:
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============== ===================================
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Syntax Description
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============== ===================================
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attr{0..32}.x Attribute 0..32 with *x* channel.
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attr{0..32}.y Attribute 0..32 with *y* channel.
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attr{0..32}.z Attribute 0..32 with *z* channel.
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attr{0..32}.w Attribute 0..32 with *w* channel.
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============== ===================================
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Examples:
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.. parsed-literal::
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v_interp_p1_f32 v1, v0, attr0.x
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v_interp_p1_f32 v1, v0, attr32.w

‎llvm/docs/AMDGPU/gfx1030_dst.rst

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_dst:
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dst
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===
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This is an input operand. It may optionally serve as a destination if :ref:`glc<amdgpu_synid_glc>` is specified.

‎llvm/docs/AMDGPU/gfx1030_fx_operand.rst

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_fx_operand:
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FX Operand
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==========
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This is an *f32* or *f16* operand depending on instruction modifiers:
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* Operand size is controlled by :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
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* Location of 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.

‎llvm/docs/AMDGPU/gfx1030_hwreg.rst

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_hwreg:
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hwreg
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=====
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Bits of a hardware register being accessed.
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The bits of this operand have the following meaning:
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======= ===================== ============
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Bits Description Value Range
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======= ===================== ============
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5:0 Register *id*. 0..63
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10:6 First bit *offset*. 0..31
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15:11 *Size* in bits. 1..32
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======= ===================== ============
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This operand may be specified as one of the following:
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* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
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* An *hwreg* value described below.
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==================================== ============================================================================
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Hwreg Value Syntax Description
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==================================== ============================================================================
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hwreg({0..63}) All bits of a register indicated by its *id*.
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hwreg(<*name*>) All bits of a register indicated by its *name*.
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hwreg({0..63}, {0..31}, {1..32}) Register bits indicated by register *id*, first bit *offset* and *size*.
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hwreg(<*name*>, {0..31}, {1..32}) Register bits indicated by register *name*, first bit *offset* and *size*.
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==================================== ============================================================================
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Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
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or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
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Defined register *names* include:
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==================== ==========================================
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Name Description
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==================== ==========================================
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HW_REG_MODE Shader writeable mode bits.
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HW_REG_STATUS Shader read-only status.
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HW_REG_TRAPSTS Trap status.
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HW_REG_HW_ID1 Id of wave, simd, compute unit, etc.
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HW_REG_HW_ID2 Id of queue, pipeline, etc.
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HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
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HW_REG_LDS_ALLOC Per-wave LDS allocation.
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HW_REG_IB_STS Counters of outstanding instructions.
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HW_REG_SH_MEM_BASES Memory aperture.
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HW_REG_TBA_LO tba_lo register.
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HW_REG_TBA_HI tba_hi register.
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HW_REG_TMA_LO tma_lo register.
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HW_REG_TMA_HI tma_hi register.
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HW_REG_FLAT_SCR_LO flat_scratch_lo register.
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HW_REG_FLAT_SCR_HI flat_scratch_hi register.
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HW_REG_POPS_PACKER pops_packer register.
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HW_REG_SHADER_CYCLES Current graphics clock counter value.
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==================== ==========================================
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Examples:
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.. parsed-literal::
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reg = 1
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offset = 2
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size = 4
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hwreg_enc = reg | (offset << 6) | ((size - 1) << 11)
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s_getreg_b32 s2, 0x1881
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s_getreg_b32 s2, hwreg_enc // the same as above
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s_getreg_b32 s2, hwreg(1, 2, 4) // the same as above
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s_getreg_b32 s2, hwreg(reg, offset, size) // the same as above
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s_getreg_b32 s2, hwreg(15)
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s_getreg_b32 s2, hwreg(51, 1, 31)
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s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)

‎llvm/docs/AMDGPU/gfx1030_imm16_73139a.rst

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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_imm16_73139a:
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imm16
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=====
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An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.

‎llvm/docs/AMDGPU/gfx1030_imm16_a04fb3.rst

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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_imm16_a04fb3:
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imm16
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=====
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An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535.

‎llvm/docs/AMDGPU/gfx1030_label.rst

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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx1030_label:
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label
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=====
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A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.
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This operand may be specified as one of the following:
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* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
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* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
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Examples:
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.. parsed-literal::
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offset = 30
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label_1:
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label_2 = . + 4
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s_branch 32
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s_branch offset + 2
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s_branch label_1
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s_branch label_2
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s_branch label_3
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s_branch label_4
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label_3 = label_2 + 4
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label_4:

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