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Auto-generate test checks for tests affected by D141060
These files had manual CHECK lines which make the diff from D141060 very difficult to review.
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13 files changed

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-265
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13 files changed

+675
-265
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‎llvm/test/CodeGen/AArch64/arm64_32-gep-sink.ll

Lines changed: 39 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,19 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
12
; RUN: opt -codegenprepare -mtriple=arm64_32-apple-ios %s -S -o - | FileCheck %s
23

34
define void @test_simple_sink(ptr %base, i64 %offset) {
4-
; CHECK-LABEL: @test_simple_sink
5-
; CHECK: next:
6-
; CHECK: [[ADDR8:%.*]] = getelementptr i8, ptr %base, i64 %offset
7-
; CHECK: load volatile i1, ptr [[ADDR8]]
5+
; CHECK-LABEL: define void @test_simple_sink(
6+
; CHECK-SAME: ptr [[BASE:%.*]], i64 [[OFFSET:%.*]]) {
7+
; CHECK-NEXT: [[ADDR:%.*]] = getelementptr i1, ptr [[BASE]], i64 [[OFFSET]]
8+
; CHECK-NEXT: [[TST:%.*]] = load i1, ptr [[ADDR]], align 1
9+
; CHECK-NEXT: br i1 [[TST]], label [[NEXT:%.*]], label [[END:%.*]]
10+
; CHECK: next:
11+
; CHECK-NEXT: [[SUNKADDR:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[OFFSET]]
12+
; CHECK-NEXT: [[TMP1:%.*]] = load volatile i1, ptr [[SUNKADDR]], align 1
13+
; CHECK-NEXT: ret void
14+
; CHECK: end:
15+
; CHECK-NEXT: ret void
16+
;
817
%addr = getelementptr i1, ptr %base, i64 %offset
918
%tst = load i1, ptr %addr
1019
br i1 %tst, label %next, label %end
@@ -18,10 +27,18 @@ end:
1827
}
1928

2029
define void @test_inbounds_sink(ptr %base, i64 %offset) {
21-
; CHECK-LABEL: @test_inbounds_sink
22-
; CHECK: next:
23-
; CHECK: [[ADDR8:%.*]] = getelementptr inbounds i8, ptr %base, i64 %offset
24-
; CHECK: load volatile i1, ptr [[ADDR8]]
30+
; CHECK-LABEL: define void @test_inbounds_sink(
31+
; CHECK-SAME: ptr [[BASE:%.*]], i64 [[OFFSET:%.*]]) {
32+
; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i1, ptr [[BASE]], i64 [[OFFSET]]
33+
; CHECK-NEXT: [[TST:%.*]] = load i1, ptr [[ADDR]], align 1
34+
; CHECK-NEXT: br i1 [[TST]], label [[NEXT:%.*]], label [[END:%.*]]
35+
; CHECK: next:
36+
; CHECK-NEXT: [[SUNKADDR:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[OFFSET]]
37+
; CHECK-NEXT: [[TMP1:%.*]] = load volatile i1, ptr [[SUNKADDR]], align 1
38+
; CHECK-NEXT: ret void
39+
; CHECK: end:
40+
; CHECK-NEXT: ret void
41+
;
2542
%addr = getelementptr inbounds i1, ptr %base, i64 %offset
2643
%tst = load i1, ptr %addr
2744
br i1 %tst, label %next, label %end
@@ -36,10 +53,20 @@ end:
3653

3754
; No address derived via an add can be guaranteed inbounds
3855
define void @test_add_sink(ptr %base, i64 %offset) {
39-
; CHECK-LABEL: @test_add_sink
40-
; CHECK: next:
41-
; CHECK: [[ADDR8:%.*]] = getelementptr i8, ptr %base, i64 %offset
42-
; CHECK: load volatile i1, ptr [[ADDR8]]
56+
; CHECK-LABEL: define void @test_add_sink(
57+
; CHECK-SAME: ptr [[BASE:%.*]], i64 [[OFFSET:%.*]]) {
58+
; CHECK-NEXT: [[BASE64:%.*]] = ptrtoint ptr [[BASE]] to i64
59+
; CHECK-NEXT: [[ADDR64:%.*]] = add nuw nsw i64 [[BASE64]], [[OFFSET]]
60+
; CHECK-NEXT: [[ADDR:%.*]] = inttoptr i64 [[ADDR64]] to ptr
61+
; CHECK-NEXT: [[TST:%.*]] = load i1, ptr [[ADDR]], align 1
62+
; CHECK-NEXT: br i1 [[TST]], label [[NEXT:%.*]], label [[END:%.*]]
63+
; CHECK: next:
64+
; CHECK-NEXT: [[SUNKADDR:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[OFFSET]]
65+
; CHECK-NEXT: [[TMP1:%.*]] = load volatile i1, ptr [[SUNKADDR]], align 1
66+
; CHECK-NEXT: ret void
67+
; CHECK: end:
68+
; CHECK-NEXT: ret void
69+
;
4370
%base64 = ptrtoint ptr %base to i64
4471
%addr64 = add nsw nuw i64 %base64, %offset
4572
%addr = inttoptr i64 %addr64 to ptr

‎llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-constexpr-alias.ll

Lines changed: 35 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals --include-generated-funcs --version 3
12
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-lower-ctor-dtor %s | FileCheck %s
23

34
; Make sure we emit code for constructor entries that aren't direct
@@ -16,29 +17,38 @@
1617

1718
@foo.alias = hidden alias void (), ptr @foo
1819

19-
;.
20-
; CHECK: @__init_array_start = external addrspace(1) constant [0 x ptr addrspace(1)]
21-
; CHECK: @__init_array_end = external addrspace(1) constant [0 x ptr addrspace(1)]
22-
; CHECK: @__fini_array_start = external addrspace(1) constant [0 x ptr addrspace(1)]
23-
; CHECK: @__fini_array_end = external addrspace(1) constant [0 x ptr addrspace(1)]
24-
; CHECK: @llvm.used = appending global [2 x ptr] [ptr @amdgcn.device.init, ptr @amdgcn.device.fini], section "llvm.metadata"
25-
; CHECK: @foo.alias = hidden alias void (), ptr @foo
26-
;.
2720
define void @foo() {
28-
; CHECK-LABEL: @foo(
29-
; CHECK-NEXT: ret void
30-
;
3121
ret void
3222
}
3323

3424
define void @bar() addrspace(1) {
35-
; CHECK-LABEL: @bar(
36-
; CHECK-NEXT: ret void
37-
;
3825
ret void
3926
}
4027

41-
; CHECK-LABEL: define weak_odr amdgpu_kernel void @amdgcn.device.init()
28+
29+
30+
;.
31+
; CHECK: @[[LLVM_GLOBAL_CTORS:[a-zA-Z0-9_$"\\.-]+]] = appending addrspace(1) global [2 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 1, ptr @foo.alias, ptr null }, { i32, ptr, ptr } { i32 1, ptr inttoptr (i64 4096 to ptr), ptr null }]
32+
; CHECK: @[[LLVM_GLOBAL_DTORS:[a-zA-Z0-9_$"\\.-]+]] = appending addrspace(1) global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 1, ptr addrspacecast (ptr addrspace(1) @bar to ptr), ptr null }]
33+
; CHECK: @[[__INIT_ARRAY_START:[a-zA-Z0-9_$"\\.-]+]] = external addrspace(1) constant [0 x ptr addrspace(1)]
34+
; CHECK: @[[__INIT_ARRAY_END:[a-zA-Z0-9_$"\\.-]+]] = external addrspace(1) constant [0 x ptr addrspace(1)]
35+
; CHECK: @[[__FINI_ARRAY_START:[a-zA-Z0-9_$"\\.-]+]] = external addrspace(1) constant [0 x ptr addrspace(1)]
36+
; CHECK: @[[__FINI_ARRAY_END:[a-zA-Z0-9_$"\\.-]+]] = external addrspace(1) constant [0 x ptr addrspace(1)]
37+
; CHECK: @[[LLVM_USED:[a-zA-Z0-9_$"\\.-]+]] = appending global [2 x ptr] [ptr @amdgcn.device.init, ptr @amdgcn.device.fini], section "llvm.metadata"
38+
; CHECK: @[[FOO_ALIAS:[a-zA-Z0-9_$"\\.-]+]] = hidden alias void (), ptr @foo
39+
;.
40+
; CHECK-LABEL: define void @foo(
41+
; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
42+
; CHECK-NEXT: ret void
43+
;
44+
;
45+
; CHECK-LABEL: define void @bar(
46+
; CHECK-SAME: ) addrspace(1) #[[ATTR0]] {
47+
; CHECK-NEXT: ret void
48+
;
49+
;
50+
; CHECK-LABEL: define weak_odr amdgpu_kernel void @amdgcn.device.init(
51+
; CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
4252
; CHECK-NEXT: entry:
4353
; CHECK-NEXT: br i1 icmp ne (ptr addrspace(1) @__init_array_start, ptr addrspace(1) @__init_array_end), label [[WHILE_ENTRY:%.*]], label [[WHILE_END:%.*]]
4454
; CHECK: while.entry:
@@ -50,8 +60,10 @@ define void @bar() addrspace(1) {
5060
; CHECK-NEXT: br i1 [[END]], label [[WHILE_END]], label [[WHILE_ENTRY]]
5161
; CHECK: while.end:
5262
; CHECK-NEXT: ret void
53-
54-
; CHECK-LABEL: define weak_odr amdgpu_kernel void @amdgcn.device.fini()
63+
;
64+
;
65+
; CHECK-LABEL: define weak_odr amdgpu_kernel void @amdgcn.device.fini(
66+
; CHECK-SAME: ) #[[ATTR2:[0-9]+]] {
5567
; CHECK-NEXT: entry:
5668
; CHECK-NEXT: br i1 icmp ne (ptr addrspace(1) @__fini_array_start, ptr addrspace(1) @__fini_array_end), label [[WHILE_ENTRY:%.*]], label [[WHILE_END:%.*]]
5769
; CHECK: while.entry:
@@ -63,6 +75,9 @@ define void @bar() addrspace(1) {
6375
; CHECK-NEXT: br i1 [[END]], label [[WHILE_END]], label [[WHILE_ENTRY]]
6476
; CHECK: while.end:
6577
; CHECK-NEXT: ret void
66-
67-
; CHECK: attributes #[[ATTR0:[0-9]+]] = { "amdgpu-flat-work-group-size"="1,1" "device-init" }
68-
; CHECK: attributes #[[ATTR1:[0-9]+]] = { "amdgpu-flat-work-group-size"="1,1" "device-fini" }
78+
;
79+
;.
80+
; CHECK: attributes #[[ATTR0]] = { "target-cpu"="gfx900" }
81+
; CHECK: attributes #[[ATTR1]] = { "amdgpu-flat-work-group-size"="1,1" "device-init" }
82+
; CHECK: attributes #[[ATTR2]] = { "amdgpu-flat-work-group-size"="1,1" "device-fini" }
83+
;.

‎llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll

Lines changed: 51 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals --include-generated-funcs --version 3
12
; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-ctor-dtor < %s | FileCheck %s
23
; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-ctor-dtor < %s | FileCheck %s
34

@@ -11,39 +12,9 @@
1112
@llvm.global_ctors = appending addrspace(1) global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 1, ptr @foo, ptr null }]
1213
@llvm.global_dtors = appending addrspace(1) global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 1, ptr @bar, ptr null }]
1314

14-
; CHECK: @__init_array_start = external addrspace(1) constant [0 x ptr addrspace(1)]
15-
; CHECK: @__init_array_end = external addrspace(1) constant [0 x ptr addrspace(1)]
16-
; CHECK: @__fini_array_start = external addrspace(1) constant [0 x ptr addrspace(1)]
17-
; CHECK: @__fini_array_end = external addrspace(1) constant [0 x ptr addrspace(1)]
18-
; CHECK: @llvm.used = appending global [2 x ptr] [ptr @amdgcn.device.init, ptr @amdgcn.device.fini]
1915

20-
; CHECK-LABEL: define weak_odr amdgpu_kernel void @amdgcn.device.init() #0
21-
; CHECK-NEXT: entry:
22-
; CHECK-NEXT: br i1 icmp ne (ptr addrspace(1) @__init_array_start, ptr addrspace(1) @__init_array_end), label [[WHILE_ENTRY:%.*]], label [[WHILE_END:%.*]]
23-
; CHECK: while.entry:
24-
; CHECK-NEXT: [[PTR:%.*]] = phi ptr addrspace(1) [ @__init_array_start, [[ENTRY:%.*]] ], [ [[NEXT:%.*]], [[WHILE_ENTRY]] ]
25-
; CHECK-NEXT: [[CALLBACK:%.*]] = load ptr, ptr addrspace(1) [[PTR]], align 8
26-
; CHECK-NEXT: call void [[CALLBACK]]()
27-
; CHECK-NEXT: [[NEXT]] = getelementptr ptr addrspace(1), ptr addrspace(1) [[PTR]], i64 1
28-
; CHECK-NEXT: [[END:%.*]] = icmp eq ptr addrspace(1) [[NEXT]], @__init_array_end
29-
; CHECK-NEXT: br i1 [[END]], label [[WHILE_END]], label [[WHILE_ENTRY]]
30-
; CHECK: while.end:
31-
; CHECK-NEXT: ret void
3216

33-
; CHECK-LABEL: define weak_odr amdgpu_kernel void @amdgcn.device.fini() #1
34-
; CHECK-NEXT: entry:
35-
; CHECK-NEXT: br i1 icmp ne (ptr addrspace(1) @__fini_array_start, ptr addrspace(1) @__fini_array_end), label [[WHILE_ENTRY:%.*]], label [[WHILE_END:%.*]]
36-
; CHECK: while.entry:
37-
; CHECK-NEXT: [[PTR:%.*]] = phi ptr addrspace(1) [ @__fini_array_start, [[ENTRY:%.*]] ], [ [[NEXT:%.*]], [[WHILE_ENTRY]] ]
38-
; CHECK-NEXT: [[CALLBACK:%.*]] = load ptr, ptr addrspace(1) [[PTR]], align 8
39-
; CHECK-NEXT: call void [[CALLBACK]]()
40-
; CHECK-NEXT: [[NEXT]] = getelementptr ptr addrspace(1), ptr addrspace(1) [[PTR]], i64 1
41-
; CHECK-NEXT: [[END:%.*]] = icmp eq ptr addrspace(1) [[NEXT]], @__fini_array_end
42-
; CHECK-NEXT: br i1 [[END]], label [[WHILE_END]], label [[WHILE_ENTRY]]
43-
; CHECK: while.end:
44-
; CHECK-NEXT: ret void
4517

46-
; CHECK-NOT: amdgcn.device.
4718

4819
; VISIBILITY: FUNC WEAK PROTECTED {{.*}} amdgcn.device.init
4920
; VISIBILITY: OBJECT WEAK DEFAULT {{.*}} amdgcn.device.init.kd
@@ -73,5 +44,53 @@ define internal void @bar() {
7344
ret void
7445
}
7546

76-
; CHECK: attributes #0 = { "amdgpu-flat-work-group-size"="1,1" "device-init" }
77-
; CHECK: attributes #1 = { "amdgpu-flat-work-group-size"="1,1" "device-fini" }
47+
;.
48+
; CHECK: @[[LLVM_GLOBAL_CTORS:[a-zA-Z0-9_$"\\.-]+]] = appending addrspace(1) global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 1, ptr @foo, ptr null }]
49+
; CHECK: @[[LLVM_GLOBAL_DTORS:[a-zA-Z0-9_$"\\.-]+]] = appending addrspace(1) global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 1, ptr @bar, ptr null }]
50+
; CHECK: @[[__INIT_ARRAY_START:[a-zA-Z0-9_$"\\.-]+]] = external addrspace(1) constant [0 x ptr addrspace(1)]
51+
; CHECK: @[[__INIT_ARRAY_END:[a-zA-Z0-9_$"\\.-]+]] = external addrspace(1) constant [0 x ptr addrspace(1)]
52+
; CHECK: @[[__FINI_ARRAY_START:[a-zA-Z0-9_$"\\.-]+]] = external addrspace(1) constant [0 x ptr addrspace(1)]
53+
; CHECK: @[[__FINI_ARRAY_END:[a-zA-Z0-9_$"\\.-]+]] = external addrspace(1) constant [0 x ptr addrspace(1)]
54+
; CHECK: @[[LLVM_USED:[a-zA-Z0-9_$"\\.-]+]] = appending global [2 x ptr] [ptr @amdgcn.device.init, ptr @amdgcn.device.fini], section "llvm.metadata"
55+
;.
56+
; CHECK-LABEL: define internal void @foo() {
57+
; CHECK-NEXT: ret void
58+
;
59+
;
60+
; CHECK-LABEL: define internal void @bar() {
61+
; CHECK-NEXT: ret void
62+
;
63+
;
64+
; CHECK-LABEL: define weak_odr amdgpu_kernel void @amdgcn.device.init(
65+
; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
66+
; CHECK-NEXT: entry:
67+
; CHECK-NEXT: br i1 icmp ne (ptr addrspace(1) @__init_array_start, ptr addrspace(1) @__init_array_end), label [[WHILE_ENTRY:%.*]], label [[WHILE_END:%.*]]
68+
; CHECK: while.entry:
69+
; CHECK-NEXT: [[PTR:%.*]] = phi ptr addrspace(1) [ @__init_array_start, [[ENTRY:%.*]] ], [ [[NEXT:%.*]], [[WHILE_ENTRY]] ]
70+
; CHECK-NEXT: [[CALLBACK:%.*]] = load ptr, ptr addrspace(1) [[PTR]], align 8
71+
; CHECK-NEXT: call void [[CALLBACK]]()
72+
; CHECK-NEXT: [[NEXT]] = getelementptr ptr addrspace(1), ptr addrspace(1) [[PTR]], i64 1
73+
; CHECK-NEXT: [[END:%.*]] = icmp eq ptr addrspace(1) [[NEXT]], @__init_array_end
74+
; CHECK-NEXT: br i1 [[END]], label [[WHILE_END]], label [[WHILE_ENTRY]]
75+
; CHECK: while.end:
76+
; CHECK-NEXT: ret void
77+
;
78+
;
79+
; CHECK-LABEL: define weak_odr amdgpu_kernel void @amdgcn.device.fini(
80+
; CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
81+
; CHECK-NEXT: entry:
82+
; CHECK-NEXT: br i1 icmp ne (ptr addrspace(1) @__fini_array_start, ptr addrspace(1) @__fini_array_end), label [[WHILE_ENTRY:%.*]], label [[WHILE_END:%.*]]
83+
; CHECK: while.entry:
84+
; CHECK-NEXT: [[PTR:%.*]] = phi ptr addrspace(1) [ @__fini_array_start, [[ENTRY:%.*]] ], [ [[NEXT:%.*]], [[WHILE_ENTRY]] ]
85+
; CHECK-NEXT: [[CALLBACK:%.*]] = load ptr, ptr addrspace(1) [[PTR]], align 8
86+
; CHECK-NEXT: call void [[CALLBACK]]()
87+
; CHECK-NEXT: [[NEXT]] = getelementptr ptr addrspace(1), ptr addrspace(1) [[PTR]], i64 1
88+
; CHECK-NEXT: [[END:%.*]] = icmp eq ptr addrspace(1) [[NEXT]], @__fini_array_end
89+
; CHECK-NEXT: br i1 [[END]], label [[WHILE_END]], label [[WHILE_ENTRY]]
90+
; CHECK: while.end:
91+
; CHECK-NEXT: ret void
92+
;
93+
;.
94+
; CHECK: attributes #[[ATTR0]] = { "amdgpu-flat-work-group-size"="1,1" "device-init" }
95+
; CHECK: attributes #[[ATTR1]] = { "amdgpu-flat-work-group-size"="1,1" "device-fini" }
96+
;.

‎llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-merge.ll

Lines changed: 14 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,24 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
12
; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s
23
; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s
34

45
@a = internal unnamed_addr addrspace(3) global [64 x i32] undef, align 4
56
@b = internal unnamed_addr addrspace(3) global [64 x i32] undef, align 4
67

7-
; CHECK-LABEL: @no_clobber_ds_load_stores_x2_preexisting_aa
8-
; CHECK: store i32 1, ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x2_preexisting_aa.lds, align 16, !tbaa !1, !noalias !6
9-
; CHECK: %val.a = load i32, ptr addrspace(3) %gep.a, align 4, !tbaa !1, !noalias !6
10-
; CHECK: store i32 2, ptr addrspace(3) getelementptr inbounds (%llvm.amdgcn.kernel.no_clobber_ds_load_stores_x2_preexisting_aa.lds.t, ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x2_preexisting_aa.lds, i32 0, i32 1), align 16, !tbaa !1, !noalias !6
11-
; CHECK: %val.b = load i32, ptr addrspace(3) %gep.b, align 4, !tbaa !1, !noalias !6
12-
138
define amdgpu_kernel void @no_clobber_ds_load_stores_x2_preexisting_aa(ptr addrspace(1) %arg, i32 %i) {
9+
; CHECK-LABEL: define amdgpu_kernel void @no_clobber_ds_load_stores_x2_preexisting_aa(
10+
; CHECK-SAME: ptr addrspace(1) [[ARG:%.*]], i32 [[I:%.*]]) #[[ATTR0:[0-9]+]] {
11+
; CHECK-NEXT: bb:
12+
; CHECK-NEXT: store i32 1, ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x2_preexisting_aa.lds, align 16, !tbaa [[TBAA1:![0-9]+]], !noalias !6
13+
; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x2_preexisting_aa.lds, i32 0, i32 [[I]]
14+
; CHECK-NEXT: [[VAL_A:%.*]] = load i32, ptr addrspace(3) [[GEP_A]], align 4, !tbaa [[TBAA1]], !noalias !6
15+
; CHECK-NEXT: store i32 2, ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_NO_CLOBBER_DS_LOAD_STORES_X2_PREEXISTING_AA_LDS_T:%.*]], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x2_preexisting_aa.lds, i32 0, i32 1), align 16, !tbaa [[TBAA1]], !noalias !6
16+
; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_NO_CLOBBER_DS_LOAD_STORES_X2_PREEXISTING_AA_LDS_T]], ptr addrspace(3) @llvm.amdgcn.kernel.no_clobber_ds_load_stores_x2_preexisting_aa.lds, i32 0, i32 1), i32 0, i32 [[I]]
17+
; CHECK-NEXT: [[VAL_B:%.*]] = load i32, ptr addrspace(3) [[GEP_B]], align 4, !tbaa [[TBAA1]], !noalias !6
18+
; CHECK-NEXT: [[VAL:%.*]] = add i32 [[VAL_A]], [[VAL_B]]
19+
; CHECK-NEXT: store i32 [[VAL]], ptr addrspace(1) [[ARG]], align 4
20+
; CHECK-NEXT: ret void
21+
;
1422
bb:
1523
store i32 1, ptr addrspace(3) @a, align 4, !alias.scope !0, !noalias !3, !tbaa !5
1624
%gep.a = getelementptr inbounds [64 x i32], ptr addrspace(3) @a, i32 0, i32 %i

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