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[AArch64][GISel] Add handling for G_VECREDUCE_FMAXIMUM and G_VECREDUCE_FMINIMUM
This is a lot of copy-pasting for the existing handling of G_VECREDUCE_FMAX/G_VECREDUCE_FMIN to add handling for G_VECREDUCE_FMAXIMUM/G_VECREDUCE_FMINIMUM in the same way. Differential Revision: https://reviews.llvm.org/D156615
1 parent 660fded commit a3f2751

18 files changed

+666
-299
lines changed

‎llvm/docs/GlobalISel/GenericOpcode.rst

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -655,10 +655,10 @@ G_VECREDUCE_FADD, G_VECREDUCE_FMUL
655655

656656
These reductions are relaxed variants which may reduce the elements in any order.
657657

658-
G_VECREDUCE_FMAX, G_VECREDUCE_FMIN
658+
G_VECREDUCE_FMAX, G_VECREDUCE_FMIN, G_VECREDUCE_FMAXIMUM, G_VECREDUCE_FMINIMUM
659659
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
660660

661-
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
661+
FMIN/FMAX/FMINIMUM/FMAXIMUM nodes can have flags, for NaN/NoNaN variants.
662662

663663

664664
Integer/bitwise reductions

‎llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -409,6 +409,8 @@ class GVecReduce : public GenericMachineInstr {
409409
case TargetOpcode::G_VECREDUCE_FMUL:
410410
case TargetOpcode::G_VECREDUCE_FMAX:
411411
case TargetOpcode::G_VECREDUCE_FMIN:
412+
case TargetOpcode::G_VECREDUCE_FMAXIMUM:
413+
case TargetOpcode::G_VECREDUCE_FMINIMUM:
412414
case TargetOpcode::G_VECREDUCE_ADD:
413415
case TargetOpcode::G_VECREDUCE_MUL:
414416
case TargetOpcode::G_VECREDUCE_AND:
@@ -441,6 +443,12 @@ class GVecReduce : public GenericMachineInstr {
441443
case TargetOpcode::G_VECREDUCE_FMIN:
442444
ScalarOpc = TargetOpcode::G_FMINNUM;
443445
break;
446+
case TargetOpcode::G_VECREDUCE_FMAXIMUM:
447+
ScalarOpc = TargetOpcode::G_FMAXIMUM;
448+
break;
449+
case TargetOpcode::G_VECREDUCE_FMINIMUM:
450+
ScalarOpc = TargetOpcode::G_FMINIMUM;
451+
break;
444452
case TargetOpcode::G_VECREDUCE_ADD:
445453
ScalarOpc = TargetOpcode::G_ADD;
446454
break;

‎llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1973,6 +1973,19 @@ class MachineIRBuilder {
19731973
MachineInstrBuilder buildVecReduceFMin(const DstOp &Dst, const SrcOp &Src) {
19741974
return buildInstr(TargetOpcode::G_VECREDUCE_FMIN, {Dst}, {Src});
19751975
}
1976+
1977+
/// Build and insert \p Res = G_VECREDUCE_FMAXIMUM \p Src
1978+
MachineInstrBuilder buildVecReduceFMaximum(const DstOp &Dst,
1979+
const SrcOp &Src) {
1980+
return buildInstr(TargetOpcode::G_VECREDUCE_FMAXIMUM, {Dst}, {Src});
1981+
}
1982+
1983+
/// Build and insert \p Res = G_VECREDUCE_FMINIMUM \p Src
1984+
MachineInstrBuilder buildVecReduceFMinimum(const DstOp &Dst,
1985+
const SrcOp &Src) {
1986+
return buildInstr(TargetOpcode::G_VECREDUCE_FMINIMUM, {Dst}, {Src});
1987+
}
1988+
19761989
/// Build and insert \p Res = G_VECREDUCE_ADD \p Src
19771990
MachineInstrBuilder buildVecReduceAdd(const DstOp &Dst, const SrcOp &Src) {
19781991
return buildInstr(TargetOpcode::G_VECREDUCE_ADD, {Dst}, {Src});

‎llvm/include/llvm/CodeGen/GlobalISel/Utils.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,8 @@ class APFloat;
5757
case TargetOpcode::G_VECREDUCE_FMUL: \
5858
case TargetOpcode::G_VECREDUCE_FMAX: \
5959
case TargetOpcode::G_VECREDUCE_FMIN: \
60+
case TargetOpcode::G_VECREDUCE_FMAXIMUM: \
61+
case TargetOpcode::G_VECREDUCE_FMINIMUM: \
6062
case TargetOpcode::G_VECREDUCE_ADD: \
6163
case TargetOpcode::G_VECREDUCE_MUL: \
6264
case TargetOpcode::G_VECREDUCE_AND: \
@@ -72,6 +74,8 @@ class APFloat;
7274
case TargetOpcode::G_VECREDUCE_FMUL: \
7375
case TargetOpcode::G_VECREDUCE_FMAX: \
7476
case TargetOpcode::G_VECREDUCE_FMIN: \
77+
case TargetOpcode::G_VECREDUCE_FMAXIMUM: \
78+
case TargetOpcode::G_VECREDUCE_FMINIMUM: \
7579
case TargetOpcode::G_VECREDUCE_ADD: \
7680
case TargetOpcode::G_VECREDUCE_MUL: \
7781
case TargetOpcode::G_VECREDUCE_AND: \

‎llvm/include/llvm/Support/TargetOpcodes.def

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -811,6 +811,8 @@ HANDLE_TARGET_OPCODE(G_VECREDUCE_FADD)
811811
HANDLE_TARGET_OPCODE(G_VECREDUCE_FMUL)
812812
HANDLE_TARGET_OPCODE(G_VECREDUCE_FMAX)
813813
HANDLE_TARGET_OPCODE(G_VECREDUCE_FMIN)
814+
HANDLE_TARGET_OPCODE(G_VECREDUCE_FMAXIMUM)
815+
HANDLE_TARGET_OPCODE(G_VECREDUCE_FMINIMUM)
814816
HANDLE_TARGET_OPCODE(G_VECREDUCE_ADD)
815817
HANDLE_TARGET_OPCODE(G_VECREDUCE_MUL)
816818
HANDLE_TARGET_OPCODE(G_VECREDUCE_AND)

‎llvm/include/llvm/Target/GenericOpcodes.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1398,6 +1398,8 @@ def G_VECREDUCE_FMUL : VectorReduction;
13981398

13991399
def G_VECREDUCE_FMAX : VectorReduction;
14001400
def G_VECREDUCE_FMIN : VectorReduction;
1401+
def G_VECREDUCE_FMAXIMUM : VectorReduction;
1402+
def G_VECREDUCE_FMINIMUM : VectorReduction;
14011403

14021404
def G_VECREDUCE_ADD : VectorReduction;
14031405
def G_VECREDUCE_MUL : VectorReduction;

‎llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -165,6 +165,8 @@ def : GINodeEquiv<G_LLROUND, llround>;
165165
def : GINodeEquiv<G_VECREDUCE_FADD, vecreduce_fadd>;
166166
def : GINodeEquiv<G_VECREDUCE_FMAX, vecreduce_fmax>;
167167
def : GINodeEquiv<G_VECREDUCE_FMIN, vecreduce_fmin>;
168+
def : GINodeEquiv<G_VECREDUCE_FMAXIMUM, vecreduce_fmaximum>;
169+
def : GINodeEquiv<G_VECREDUCE_FMINIMUM, vecreduce_fminimum>;
168170

169171
def : GINodeEquiv<G_STRICT_FADD, strict_fadd>;
170172
def : GINodeEquiv<G_STRICT_FSUB, strict_fsub>;

‎llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1797,6 +1797,10 @@ unsigned IRTranslator::getSimpleIntrinsicOpcode(Intrinsic::ID ID) {
17971797
return TargetOpcode::G_VECREDUCE_FMIN;
17981798
case Intrinsic::vector_reduce_fmax:
17991799
return TargetOpcode::G_VECREDUCE_FMAX;
1800+
case Intrinsic::vector_reduce_fminimum:
1801+
return TargetOpcode::G_VECREDUCE_FMINIMUM;
1802+
case Intrinsic::vector_reduce_fmaximum:
1803+
return TargetOpcode::G_VECREDUCE_FMAXIMUM;
18001804
case Intrinsic::vector_reduce_add:
18011805
return TargetOpcode::G_VECREDUCE_ADD;
18021806
case Intrinsic::vector_reduce_mul:

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2649,6 +2649,8 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
26492649
}
26502650
case TargetOpcode::G_VECREDUCE_FMIN:
26512651
case TargetOpcode::G_VECREDUCE_FMAX:
2652+
case TargetOpcode::G_VECREDUCE_FMINIMUM:
2653+
case TargetOpcode::G_VECREDUCE_FMAXIMUM:
26522654
if (TypeIdx != 0)
26532655
return UnableToLegalize;
26542656
Observer.changingInstr(MI);

‎llvm/lib/CodeGen/MachineVerifier.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1720,6 +1720,8 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
17201720
case TargetOpcode::G_VECREDUCE_FMUL:
17211721
case TargetOpcode::G_VECREDUCE_FMAX:
17221722
case TargetOpcode::G_VECREDUCE_FMIN:
1723+
case TargetOpcode::G_VECREDUCE_FMAXIMUM:
1724+
case TargetOpcode::G_VECREDUCE_FMINIMUM:
17231725
case TargetOpcode::G_VECREDUCE_ADD:
17241726
case TargetOpcode::G_VECREDUCE_MUL:
17251727
case TargetOpcode::G_VECREDUCE_AND:

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -850,7 +850,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
850850
.clampMaxNumElements(1, s32, 4)
851851
.lower();
852852

853-
getActionDefinitionsBuilder({G_VECREDUCE_FMIN, G_VECREDUCE_FMAX})
853+
getActionDefinitionsBuilder({G_VECREDUCE_FMIN, G_VECREDUCE_FMAX,
854+
G_VECREDUCE_FMINIMUM, G_VECREDUCE_FMAXIMUM})
854855
.legalFor({{s32, v4s32}, {s32, v2s32}, {s64, v2s64}})
855856
.legalIf([=](const LegalityQuery &Query) {
856857
const auto &Ty = Query.Types[1];

‎llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -996,6 +996,8 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
996996
case TargetOpcode::G_VECREDUCE_FMUL:
997997
case TargetOpcode::G_VECREDUCE_FMAX:
998998
case TargetOpcode::G_VECREDUCE_FMIN:
999+
case TargetOpcode::G_VECREDUCE_FMAXIMUM:
1000+
case TargetOpcode::G_VECREDUCE_FMINIMUM:
9991001
case TargetOpcode::G_VECREDUCE_ADD:
10001002
case TargetOpcode::G_VECREDUCE_MUL:
10011003
case TargetOpcode::G_VECREDUCE_AND:

‎llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-reductions.ll

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,8 @@ define double @fmul_fast(double %start, <4 x double> %vec) {
6666

6767
declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)
6868
declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
69+
declare float @llvm.vector.reduce.fmaximum.v4f32(<4 x float>)
70+
declare float @llvm.vector.reduce.fminimum.v4f32(<4 x float>)
6971

7072
define float @fmax(<4 x float> %vec) {
7173
; CHECK-LABEL: name: fmax
@@ -106,6 +108,45 @@ define float @fmin_nnan(<4 x float> %vec) {
106108
ret float %res
107109
}
108110

111+
define float @fmaximum(<4 x float> %vec) {
112+
; CHECK-LABEL: name: fmaximum
113+
; CHECK: bb.1 (%ir-block.0):
114+
; CHECK: liveins: $q0
115+
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
116+
; CHECK: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
117+
; CHECK: [[VECREDUCE_FMAX:%[0-9]+]]:_(s32) = G_VECREDUCE_FMAXIMUM [[BITCAST]](<4 x s32>)
118+
; CHECK: $s0 = COPY [[VECREDUCE_FMAX]](s32)
119+
; CHECK: RET_ReallyLR implicit $s0
120+
%res = call float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> %vec)
121+
ret float %res
122+
}
123+
124+
define float @fminimum(<4 x float> %vec) {
125+
; CHECK-LABEL: name: fminimum
126+
; CHECK: bb.1 (%ir-block.0):
127+
; CHECK: liveins: $q0
128+
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
129+
; CHECK: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
130+
; CHECK: [[VECREDUCE_FMIN:%[0-9]+]]:_(s32) = G_VECREDUCE_FMINIMUM [[BITCAST]](<4 x s32>)
131+
; CHECK: $s0 = COPY [[VECREDUCE_FMIN]](s32)
132+
; CHECK: RET_ReallyLR implicit $s0
133+
%res = call float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %vec)
134+
ret float %res
135+
}
136+
137+
define float @fminimum_nnan(<4 x float> %vec) {
138+
; CHECK-LABEL: name: fminimum_nnan
139+
; CHECK: bb.1 (%ir-block.0):
140+
; CHECK: liveins: $q0
141+
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
142+
; CHECK: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
143+
; CHECK: [[VECREDUCE_FMIN:%[0-9]+]]:_(s32) = nnan G_VECREDUCE_FMINIMUM [[BITCAST]](<4 x s32>)
144+
; CHECK: $s0 = COPY [[VECREDUCE_FMIN]](s32)
145+
; CHECK: RET_ReallyLR implicit $s0
146+
%res = call nnan float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %vec)
147+
ret float %res
148+
}
149+
109150
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
110151

111152
define i32 @add(<4 x i32> %vec) {

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-fminmax.mir

Lines changed: 93 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,93 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -O0 -mtriple=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s
3+
4+
---
5+
name: fmin_v2s32
6+
tracksRegLiveness: true
7+
body: |
8+
bb.1:
9+
liveins: $d0
10+
11+
; CHECK-LABEL: name: fmin_v2s32
12+
; CHECK: liveins: $d0
13+
; CHECK-NEXT: {{ $}}
14+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
15+
; CHECK-NEXT: [[VECREDUCE_FMIN:%[0-9]+]]:_(s32) = G_VECREDUCE_FMIN [[COPY]](<2 x s32>)
16+
; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMIN]](s32)
17+
; CHECK-NEXT: RET_ReallyLR implicit $s0
18+
%0:_(<2 x s32>) = COPY $d0
19+
%1:_(s32) = G_VECREDUCE_FMIN %0(<2 x s32>)
20+
$s0 = COPY %1(s32)
21+
RET_ReallyLR implicit $s0
22+
23+
...
24+
---
25+
name: fmax_v8s16
26+
tracksRegLiveness: true
27+
body: |
28+
bb.1:
29+
liveins: $q0
30+
31+
; CHECK-LABEL: name: fmax_v8s16
32+
; CHECK: liveins: $q0
33+
; CHECK-NEXT: {{ $}}
34+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
35+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s16>), [[UV1:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
36+
; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV]](<4 x s16>)
37+
; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV1]](<4 x s16>)
38+
; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:_(<4 x s32>) = G_FMAXNUM [[FPEXT]], [[FPEXT1]]
39+
; CHECK-NEXT: [[VECREDUCE_FMAX:%[0-9]+]]:_(s32) = G_VECREDUCE_FMAX [[FMAXNUM]](<4 x s32>)
40+
; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[VECREDUCE_FMAX]](s32)
41+
; CHECK-NEXT: $h0 = COPY [[FPTRUNC]](s16)
42+
; CHECK-NEXT: RET_ReallyLR implicit $h0
43+
%0:_(<8 x s16>) = COPY $q0
44+
%1:_(s16) = G_VECREDUCE_FMAX %0(<8 x s16>)
45+
$h0 = COPY %1(s16)
46+
RET_ReallyLR implicit $h0
47+
48+
...
49+
---
50+
name: fminimum_v2s32
51+
tracksRegLiveness: true
52+
body: |
53+
bb.1:
54+
liveins: $d0
55+
56+
; CHECK-LABEL: name: fminimum_v2s32
57+
; CHECK: liveins: $d0
58+
; CHECK-NEXT: {{ $}}
59+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
60+
; CHECK-NEXT: [[VECREDUCE_FMINIMUM:%[0-9]+]]:_(s32) = G_VECREDUCE_FMINIMUM [[COPY]](<2 x s32>)
61+
; CHECK-NEXT: $s0 = COPY [[VECREDUCE_FMINIMUM]](s32)
62+
; CHECK-NEXT: RET_ReallyLR implicit $s0
63+
%0:_(<2 x s32>) = COPY $d0
64+
%1:_(s32) = G_VECREDUCE_FMINIMUM %0(<2 x s32>)
65+
$s0 = COPY %1(s32)
66+
RET_ReallyLR implicit $s0
67+
68+
...
69+
---
70+
name: fmaximum_v8s16
71+
tracksRegLiveness: true
72+
body: |
73+
bb.1:
74+
liveins: $q0
75+
76+
; CHECK-LABEL: name: fmaximum_v8s16
77+
; CHECK: liveins: $q0
78+
; CHECK-NEXT: {{ $}}
79+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
80+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s16>), [[UV1:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
81+
; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV]](<4 x s16>)
82+
; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV1]](<4 x s16>)
83+
; CHECK-NEXT: [[FMAXIMUM:%[0-9]+]]:_(<4 x s32>) = G_FMAXIMUM [[FPEXT]], [[FPEXT1]]
84+
; CHECK-NEXT: [[VECREDUCE_FMAXIMUM:%[0-9]+]]:_(s32) = G_VECREDUCE_FMAXIMUM [[FMAXIMUM]](<4 x s32>)
85+
; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[VECREDUCE_FMAXIMUM]](s32)
86+
; CHECK-NEXT: $h0 = COPY [[FPTRUNC]](s16)
87+
; CHECK-NEXT: RET_ReallyLR implicit $h0
88+
%0:_(<8 x s16>) = COPY $q0
89+
%1:_(s16) = G_VECREDUCE_FMAXIMUM %0(<8 x s16>)
90+
$h0 = COPY %1(s16)
91+
RET_ReallyLR implicit $h0
92+
93+
...

‎llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -726,6 +726,14 @@
726726
# DEBUG-NEXT: G_VECREDUCE_FMIN (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
727727
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
728728
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
729+
# DEBUG-NEXT: G_VECREDUCE_FMAXIMUM (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
730+
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
731+
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
732+
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
733+
# DEBUG-NEXT: G_VECREDUCE_FMINIMUM (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
734+
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
735+
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
736+
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
729737
# DEBUG-NEXT: G_VECREDUCE_ADD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
730738
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
731739
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected

‎llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-reductions.mir

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,3 +41,24 @@ body: |
4141
RET_ReallyLR implicit $w0
4242
4343
...
44+
---
45+
name: fmaximum_v4s32
46+
legalized: true
47+
tracksRegLiveness: true
48+
body: |
49+
bb.1:
50+
liveins: $q0
51+
52+
; CHECK-LABEL: name: fmaximum_v4s32
53+
; CHECK: liveins: $q0
54+
; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
55+
; CHECK: [[VECREDUCE_FMAXIMUM:%[0-9]+]]:fpr(s32) = G_VECREDUCE_FMAXIMUM [[COPY]](<4 x s32>)
56+
; CHECK: $w0 = COPY [[VECREDUCE_FMAXIMUM]](s32)
57+
; CHECK: RET_ReallyLR implicit $w0
58+
%0:_(<4 x s32>) = COPY $q0
59+
%1:_(s32) = G_VECREDUCE_FMAXIMUM %0(<4 x s32>)
60+
$w0 = COPY %1(s32)
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RET_ReallyLR implicit $w0
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...
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