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[AMDGPU] Update ASAN tests with update_test_checks. (llvm#68688)
Update existing tests to make further reviews on AMDGPU address sanitizer checks easier.
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‎llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll

Lines changed: 25 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1,34 +1,36 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
12
; RUN: opt < %s -passes=asan -S | FileCheck %s
23
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8"
34
target triple = "amdgcn-amd-amdhsa"
45

56
@x = addrspace(4) global [2 x i32] zeroinitializer, align 4
67

78
define protected amdgpu_kernel void @constant_load(i64 %i) sanitize_address {
8-
entry:
9-
; CHECK-LABEL: @constant_load
10-
; CHECK-NOT: load
11-
;
12-
; CHECK: %[[LOAD_ADDR:[^ ]*]] = ptrtoint ptr addrspace(4) %a to i64
13-
; CHECK: lshr i64 %[[LOAD_ADDR]], 3
14-
; CHECK: add i64 %{{.*}}, 2147450880
15-
; CHECK: %[[LOAD_SHADOW_PTR:[^ ]*]] = inttoptr
16-
; CHECK: %[[LOAD_SHADOW:[^ ]*]] = load i8, ptr %[[LOAD_SHADOW_PTR]]
17-
; CHECK: icmp ne i8
18-
; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
19-
;
20-
; CHECK: add i64 %{{.*}}, 3
21-
; CHECK: trunc i64 %{{.*}} to i8
22-
; CHECK: icmp sge i8 %{{.*}}, %[[LOAD_SHADOW]]
23-
; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
9+
; CHECK-LABEL: define protected amdgpu_kernel void @constant_load(
10+
; CHECK-SAME: i64 [[I:%.*]]) #[[ATTR0:[0-9]+]] {
11+
; CHECK-NEXT: entry:
12+
; CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(4) @x, i64 0, i64 [[I]]
13+
; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(4) [[A]] to i64
14+
; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3
15+
; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880
16+
; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
17+
; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1
18+
; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0
19+
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP12:%.*]], !prof [[PROF1:![0-9]+]]
20+
; CHECK: 6:
21+
; CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP0]], 7
22+
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 3
23+
; CHECK-NEXT: [[TMP9:%.*]] = trunc i64 [[TMP8]] to i8
24+
; CHECK-NEXT: [[TMP10:%.*]] = icmp sge i8 [[TMP9]], [[TMP4]]
25+
; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12]]
26+
; CHECK: 11:
27+
; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP0]]) #[[ATTR3:[0-9]+]]
28+
; CHECK-NEXT: unreachable
29+
; CHECK: 12:
30+
; CHECK-NEXT: [[Q:%.*]] = load i32, ptr addrspace(4) [[A]], align 4
31+
; CHECK-NEXT: ret void
2432
;
25-
; The crash block reports the error.
26-
; CHECK: call void @__asan_report_load4(i64 %[[LOAD_ADDR]])
27-
; CHECK: unreachable
28-
;
29-
; The actual load.
30-
; CHECK: load i32, ptr addrspace(4) %a
31-
; CHECK: ret void
33+
entry:
3234

3335
%a = getelementptr inbounds [2 x i32], ptr addrspace(4) @x, i64 0, i64 %i
3436
%q = load i32, ptr addrspace(4) %a, align 4

‎llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll

Lines changed: 65 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -1,74 +1,82 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
12
; RUN: opt < %s -passes=asan -S | FileCheck %s
23
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8"
34
target triple = "amdgcn-amd-amdhsa"
45

56
define protected amdgpu_kernel void @generic_store(ptr addrspace(1) %p, i32 %i) sanitize_address {
6-
entry:
7-
; CHECK-LABEL: @generic_store
8-
; CHECK-NOT: store
9-
; CHECK: %[[GENERIC_ADDR:[^ ]*]] = addrspacecast ptr addrspace(1) %p to ptr
10-
; CHECK: call i1 @llvm.amdgcn.is.shared(ptr %[[GENERIC_ADDR]])
11-
; CHECK: call i1 @llvm.amdgcn.is.private(ptr %[[GENERIC_ADDR]])
12-
; CHECK: or
13-
; CHECK: xor i1 %{{.*}}, true
14-
; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
15-
;
16-
; CHECK: %[[STORE_ADDR:[^ ]*]] = ptrtoint ptr %q to i64
17-
; CHECK: lshr i64 %[[STORE_ADDR]], 3
18-
; CHECK: add i64 %{{.*}}, 2147450880
19-
; CHECK: %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr
20-
; CHECK: %[[STORE_SHADOW:[^ ]*]] = load i8, ptr %[[STORE_SHADOW_PTR]]
21-
; CHECK: icmp ne i8
22-
; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
23-
;
24-
; CHECK: add i64 %{{.*}}, 3
25-
; CHECK: trunc i64 %{{.*}} to i8
26-
; CHECK: icmp sge i8 %{{.*}}, %[[STORE_SHADOW]]
27-
; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
7+
; CHECK-LABEL: define protected amdgpu_kernel void @generic_store(
8+
; CHECK-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0:[0-9]+]] {
9+
; CHECK-NEXT: entry:
10+
; CHECK-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr
11+
; CHECK-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])
12+
; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])
13+
; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]
14+
; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
15+
; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP18:%.*]]
16+
; CHECK: 4:
17+
; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64
18+
; CHECK-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3
19+
; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880
20+
; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
21+
; CHECK-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
22+
; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0
23+
; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP17:%.*]], !prof [[PROF0:![0-9]+]]
24+
; CHECK: 11:
25+
; CHECK-NEXT: [[TMP12:%.*]] = and i64 [[TMP5]], 7
26+
; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP12]], 3
27+
; CHECK-NEXT: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i8
28+
; CHECK-NEXT: [[TMP15:%.*]] = icmp sge i8 [[TMP14]], [[TMP9]]
29+
; CHECK-NEXT: br i1 [[TMP15]], label [[TMP16:%.*]], label [[TMP17]]
30+
; CHECK: 16:
31+
; CHECK-NEXT: call void @__asan_report_store4(i64 [[TMP5]]) #[[ATTR3:[0-9]+]]
32+
; CHECK-NEXT: unreachable
33+
; CHECK: 17:
34+
; CHECK-NEXT: br label [[TMP18]]
35+
; CHECK: 18:
36+
; CHECK-NEXT: store i32 0, ptr [[Q]], align 4
37+
; CHECK-NEXT: ret void
2838
;
29-
; The crash block reports the error.
30-
; CHECK: call void @__asan_report_store4(i64 %[[STORE_ADDR]])
31-
; CHECK: unreachable
32-
;
33-
; The actual store.
34-
; CHECK: store i32 0, ptr %q
35-
; CHECK: ret void
39+
entry:
3640

3741
%q = addrspacecast ptr addrspace(1) %p to ptr
3842
store i32 0, ptr %q, align 4
3943
ret void
4044
}
4145

4246
define protected amdgpu_kernel void @generic_load(ptr addrspace(1) %p, i32 %i) sanitize_address {
43-
entry:
44-
; CHECK-LABEL: @generic_load
45-
; CHECK-NOT: load
46-
; CHECK: call i1 @llvm.amdgcn.is.shared(ptr %[[GENERIC_ADDR]])
47-
; CHECK: call i1 @llvm.amdgcn.is.private(ptr %[[GENERIC_ADDR]])
48-
; CHECK: or
49-
; CHECK: xor i1 %{{.*}}, true
50-
; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
51-
;
52-
; CHECK: %[[STORE_ADDR:[^ ]*]] = ptrtoint ptr %q to i64
53-
; CHECK: lshr i64 %[[STORE_ADDR]], 3
54-
; CHECK: add i64 %{{.*}}, 2147450880
55-
; CHECK: %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr
56-
; CHECK: %[[STORE_SHADOW:[^ ]*]] = load i8, ptr %[[STORE_SHADOW_PTR]]
57-
; CHECK: icmp ne i8
58-
; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
59-
;
60-
; CHECK: add i64 %{{.*}}, 3
61-
; CHECK: trunc i64 %{{.*}} to i8
62-
; CHECK: icmp sge i8 %{{.*}}, %[[STORE_SHADOW]]
63-
; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
47+
; CHECK-LABEL: define protected amdgpu_kernel void @generic_load(
48+
; CHECK-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0]] {
49+
; CHECK-NEXT: entry:
50+
; CHECK-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr
51+
; CHECK-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])
52+
; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])
53+
; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]
54+
; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true
55+
; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP18:%.*]]
56+
; CHECK: 4:
57+
; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64
58+
; CHECK-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3
59+
; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880
60+
; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
61+
; CHECK-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
62+
; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0
63+
; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP17:%.*]], !prof [[PROF0]]
64+
; CHECK: 11:
65+
; CHECK-NEXT: [[TMP12:%.*]] = and i64 [[TMP5]], 7
66+
; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP12]], 3
67+
; CHECK-NEXT: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i8
68+
; CHECK-NEXT: [[TMP15:%.*]] = icmp sge i8 [[TMP14]], [[TMP9]]
69+
; CHECK-NEXT: br i1 [[TMP15]], label [[TMP16:%.*]], label [[TMP17]]
70+
; CHECK: 16:
71+
; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP5]]) #[[ATTR3]]
72+
; CHECK-NEXT: unreachable
73+
; CHECK: 17:
74+
; CHECK-NEXT: br label [[TMP18]]
75+
; CHECK: 18:
76+
; CHECK-NEXT: [[R:%.*]] = load i32, ptr [[Q]], align 4
77+
; CHECK-NEXT: ret void
6478
;
65-
; The crash block reports the error.
66-
; CHECK: call void @__asan_report_load4(i64 %[[STORE_ADDR]])
67-
; CHECK: unreachable
68-
;
69-
; The actual store.
70-
; CHECK: load i32, ptr %q
71-
; CHECK: ret void
79+
entry:
7280

7381
%q = addrspacecast ptr addrspace(1) %p to ptr
7482
%r = load i32, ptr %q, align 4

‎llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll

Lines changed: 47 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -1,62 +1,63 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
12
; RUN: opt < %s -passes=asan -S | FileCheck %s
23
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8"
34
target triple = "amdgcn-amd-amdhsa"
45

56
define protected amdgpu_kernel void @global_store(ptr addrspace(1) %p, i32 %i) sanitize_address {
6-
entry:
7-
; CHECK-LABEL: @global_store
8-
; CHECK-NOT: store
9-
;
10-
; CHECK: %[[STORE_ADDR:[^ ]*]] = ptrtoint ptr addrspace(1) %p to i64
11-
; CHECK: lshr i64 %[[STORE_ADDR]], 3
12-
; CHECK: add i64 %{{.*}}, 2147450880
13-
; CHECK: %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr
14-
; CHECK: %[[STORE_SHADOW:[^ ]*]] = load i8, ptr %[[STORE_SHADOW_PTR]]
15-
; CHECK: icmp ne i8
16-
; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
17-
;
18-
; CHECK: add i64 %{{.*}}, 3
19-
; CHECK: trunc i64 %{{.*}} to i8
20-
; CHECK: icmp sge i8 %{{.*}}, %[[STORE_SHADOW]]
21-
; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
7+
; CHECK-LABEL: define protected amdgpu_kernel void @global_store(
8+
; CHECK-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0:[0-9]+]] {
9+
; CHECK-NEXT: entry:
10+
; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P]] to i64
11+
; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3
12+
; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880
13+
; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
14+
; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1
15+
; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0
16+
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP12:%.*]], !prof [[PROF0:![0-9]+]]
17+
; CHECK: 6:
18+
; CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP0]], 7
19+
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 3
20+
; CHECK-NEXT: [[TMP9:%.*]] = trunc i64 [[TMP8]] to i8
21+
; CHECK-NEXT: [[TMP10:%.*]] = icmp sge i8 [[TMP9]], [[TMP4]]
22+
; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12]]
23+
; CHECK: 11:
24+
; CHECK-NEXT: call void @__asan_report_store4(i64 [[TMP0]]) #[[ATTR3:[0-9]+]]
25+
; CHECK-NEXT: unreachable
26+
; CHECK: 12:
27+
; CHECK-NEXT: store i32 0, ptr addrspace(1) [[P]], align 4
28+
; CHECK-NEXT: ret void
2229
;
23-
; The crash block reports the error.
24-
; CHECK: call void @__asan_report_store4(i64 %[[STORE_ADDR]])
25-
; CHECK: unreachable
26-
;
27-
; The actual store.
28-
; CHECK: store i32 0, ptr addrspace(1) %p
29-
; CHECK: ret void
30+
entry:
3031

3132
store i32 0, ptr addrspace(1) %p, align 4
3233
ret void
3334
}
3435

3536
define protected amdgpu_kernel void @global_load(ptr addrspace(1) %p, i32 %i) sanitize_address {
36-
entry:
37-
; CHECK-LABEL: @global_load
38-
; CHECK-NOT: load
39-
;
40-
; CHECK: %[[LOAD_ADDR:[^ ]*]] = ptrtoint ptr addrspace(1) %p to i64
41-
; CHECK: lshr i64 %[[LOAD_ADDR]], 3
42-
; CHECK: add i64 %{{.*}}, 2147450880
43-
; CHECK: %[[LOAD_SHADOW_PTR:[^ ]*]] = inttoptr
44-
; CHECK: %[[LOAD_SHADOW:[^ ]*]] = load i8, ptr %[[LOAD_SHADOW_PTR]]
45-
; CHECK: icmp ne i8
46-
; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
47-
;
48-
; CHECK: add i64 %{{.*}}, 3
49-
; CHECK: trunc i64 %{{.*}} to i8
50-
; CHECK: icmp sge i8 %{{.*}}, %[[LOAD_SHADOW]]
51-
; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}
37+
; CHECK-LABEL: define protected amdgpu_kernel void @global_load(
38+
; CHECK-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0]] {
39+
; CHECK-NEXT: entry:
40+
; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(1) [[P]] to i64
41+
; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3
42+
; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 2147450880
43+
; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
44+
; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP3]], align 1
45+
; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0
46+
; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP12:%.*]], !prof [[PROF0]]
47+
; CHECK: 6:
48+
; CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP0]], 7
49+
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 3
50+
; CHECK-NEXT: [[TMP9:%.*]] = trunc i64 [[TMP8]] to i8
51+
; CHECK-NEXT: [[TMP10:%.*]] = icmp sge i8 [[TMP9]], [[TMP4]]
52+
; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP12]]
53+
; CHECK: 11:
54+
; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP0]]) #[[ATTR3]]
55+
; CHECK-NEXT: unreachable
56+
; CHECK: 12:
57+
; CHECK-NEXT: [[Q:%.*]] = load i32, ptr addrspace(1) [[P]], align 4
58+
; CHECK-NEXT: ret void
5259
;
53-
; The crash block reports the error.
54-
; CHECK: call void @__asan_report_load4(i64 %[[LOAD_ADDR]])
55-
; CHECK: unreachable
56-
;
57-
; The actual load.
58-
; CHECK: load i32, ptr addrspace(1) %p
59-
; CHECK: ret void
60+
entry:
6061

6162
%q = load i32, ptr addrspace(1) %p, align 4
6263
ret void

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