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huihzhanghuihzhang
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Revert "Reland "[AArch64] Fix data race on RegisterBank initialization.""
This reverts commit 8e1ca94. New failing at http://lab.llvm.org:8011/builders/clang-armv7-linux-build-cache/builds/25929 I did reproduce and pass the previous failure at http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-autoconf/builds/46803/steps/annotate/logs/stdio
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‎llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp

Lines changed: 88 additions & 91 deletions
Original file line numberDiff line numberDiff line change
@@ -38,58 +38,58 @@ using namespace llvm;
3838

3939
AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
4040
: AArch64GenRegisterBankInfo() {
41-
static llvm::once_flag InitializeRegisterBankFlag;
42-
43-
static auto InitializeRegisterBankOnce = [this](const TargetRegisterInfo &TRI) {
44-
// We have only one set of register banks, whatever the subtarget
45-
// is. Therefore, the initialization of the RegBanks table should be
46-
// done only once. Indeed the table of all register banks
47-
// (AArch64::RegBanks) is unique in the compiler. At some point, it
48-
// will get tablegen'ed and the whole constructor becomes empty.
49-
50-
const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
51-
(void)RBGPR;
52-
assert(&AArch64::GPRRegBank == &RBGPR &&
53-
"The order in RegBanks is messed up");
54-
55-
const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
56-
(void)RBFPR;
57-
assert(&AArch64::FPRRegBank == &RBFPR &&
58-
"The order in RegBanks is messed up");
59-
60-
const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID);
61-
(void)RBCCR;
62-
assert(&AArch64::CCRegBank == &RBCCR &&
63-
"The order in RegBanks is messed up");
64-
65-
// The GPR register bank is fully defined by all the registers in
66-
// GR64all + its subclasses.
67-
assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
68-
"Subclass not added?");
69-
assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit");
70-
71-
// The FPR register bank is fully defined by all the registers in
72-
// GR64all + its subclasses.
73-
assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
74-
"Subclass not added?");
75-
assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
76-
"Subclass not added?");
77-
assert(RBFPR.getSize() == 512 &&
78-
"FPRs should hold up to 512-bit via QQQQ sequence");
79-
80-
assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
81-
"Class not added?");
82-
assert(RBCCR.getSize() == 32 && "CCR should hold up to 32-bit");
83-
84-
// Check that the TableGen'ed like file is in sync we our expectations.
85-
// First, the Idx.
86-
assert(checkPartialMappingIdx(PMI_FirstGPR, PMI_LastGPR,
87-
{PMI_GPR32, PMI_GPR64}) &&
88-
"PartialMappingIdx's are incorrectly ordered");
89-
assert(checkPartialMappingIdx(PMI_FirstFPR, PMI_LastFPR,
90-
{PMI_FPR16, PMI_FPR32, PMI_FPR64, PMI_FPR128,
91-
PMI_FPR256, PMI_FPR512}) &&
92-
"PartialMappingIdx's are incorrectly ordered");
41+
static bool AlreadyInit = false;
42+
// We have only one set of register banks, whatever the subtarget
43+
// is. Therefore, the initialization of the RegBanks table should be
44+
// done only once. Indeed the table of all register banks
45+
// (AArch64::RegBanks) is unique in the compiler. At some point, it
46+
// will get tablegen'ed and the whole constructor becomes empty.
47+
if (AlreadyInit)
48+
return;
49+
AlreadyInit = true;
50+
51+
const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
52+
(void)RBGPR;
53+
assert(&AArch64::GPRRegBank == &RBGPR &&
54+
"The order in RegBanks is messed up");
55+
56+
const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
57+
(void)RBFPR;
58+
assert(&AArch64::FPRRegBank == &RBFPR &&
59+
"The order in RegBanks is messed up");
60+
61+
const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID);
62+
(void)RBCCR;
63+
assert(&AArch64::CCRegBank == &RBCCR && "The order in RegBanks is messed up");
64+
65+
// The GPR register bank is fully defined by all the registers in
66+
// GR64all + its subclasses.
67+
assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
68+
"Subclass not added?");
69+
assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit");
70+
71+
// The FPR register bank is fully defined by all the registers in
72+
// GR64all + its subclasses.
73+
assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
74+
"Subclass not added?");
75+
assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
76+
"Subclass not added?");
77+
assert(RBFPR.getSize() == 512 &&
78+
"FPRs should hold up to 512-bit via QQQQ sequence");
79+
80+
assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
81+
"Class not added?");
82+
assert(RBCCR.getSize() == 32 && "CCR should hold up to 32-bit");
83+
84+
// Check that the TableGen'ed like file is in sync we our expectations.
85+
// First, the Idx.
86+
assert(checkPartialMappingIdx(PMI_FirstGPR, PMI_LastGPR,
87+
{PMI_GPR32, PMI_GPR64}) &&
88+
"PartialMappingIdx's are incorrectly ordered");
89+
assert(checkPartialMappingIdx(PMI_FirstFPR, PMI_LastFPR,
90+
{PMI_FPR16, PMI_FPR32, PMI_FPR64, PMI_FPR128,
91+
PMI_FPR256, PMI_FPR512}) &&
92+
"PartialMappingIdx's are incorrectly ordered");
9393
// Now, the content.
9494
// Check partial mapping.
9595
#define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB) \
@@ -99,14 +99,14 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
9999
#Idx " is incorrectly initialized"); \
100100
} while (false)
101101

102-
CHECK_PARTIALMAP(PMI_GPR32, 0, 32, RBGPR);
103-
CHECK_PARTIALMAP(PMI_GPR64, 0, 64, RBGPR);
104-
CHECK_PARTIALMAP(PMI_FPR16, 0, 16, RBFPR);
105-
CHECK_PARTIALMAP(PMI_FPR32, 0, 32, RBFPR);
106-
CHECK_PARTIALMAP(PMI_FPR64, 0, 64, RBFPR);
107-
CHECK_PARTIALMAP(PMI_FPR128, 0, 128, RBFPR);
108-
CHECK_PARTIALMAP(PMI_FPR256, 0, 256, RBFPR);
109-
CHECK_PARTIALMAP(PMI_FPR512, 0, 512, RBFPR);
102+
CHECK_PARTIALMAP(PMI_GPR32, 0, 32, RBGPR);
103+
CHECK_PARTIALMAP(PMI_GPR64, 0, 64, RBGPR);
104+
CHECK_PARTIALMAP(PMI_FPR16, 0, 16, RBFPR);
105+
CHECK_PARTIALMAP(PMI_FPR32, 0, 32, RBFPR);
106+
CHECK_PARTIALMAP(PMI_FPR64, 0, 64, RBFPR);
107+
CHECK_PARTIALMAP(PMI_FPR128, 0, 128, RBFPR);
108+
CHECK_PARTIALMAP(PMI_FPR256, 0, 256, RBFPR);
109+
CHECK_PARTIALMAP(PMI_FPR512, 0, 512, RBFPR);
110110

111111
// Check value mapping.
112112
#define CHECK_VALUEMAP_IMPL(RBName, Size, Offset) \
@@ -119,14 +119,14 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
119119

120120
#define CHECK_VALUEMAP(RBName, Size) CHECK_VALUEMAP_IMPL(RBName, Size, 0)
121121

122-
CHECK_VALUEMAP(GPR, 32);
123-
CHECK_VALUEMAP(GPR, 64);
124-
CHECK_VALUEMAP(FPR, 16);
125-
CHECK_VALUEMAP(FPR, 32);
126-
CHECK_VALUEMAP(FPR, 64);
127-
CHECK_VALUEMAP(FPR, 128);
128-
CHECK_VALUEMAP(FPR, 256);
129-
CHECK_VALUEMAP(FPR, 512);
122+
CHECK_VALUEMAP(GPR, 32);
123+
CHECK_VALUEMAP(GPR, 64);
124+
CHECK_VALUEMAP(FPR, 16);
125+
CHECK_VALUEMAP(FPR, 32);
126+
CHECK_VALUEMAP(FPR, 64);
127+
CHECK_VALUEMAP(FPR, 128);
128+
CHECK_VALUEMAP(FPR, 256);
129+
CHECK_VALUEMAP(FPR, 512);
130130

131131
// Check the value mapping for 3-operands instructions where all the operands
132132
// map to the same value mapping.
@@ -137,13 +137,13 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
137137
CHECK_VALUEMAP_IMPL(RBName, Size, 2); \
138138
} while (false)
139139

140-
CHECK_VALUEMAP_3OPS(GPR, 32);
141-
CHECK_VALUEMAP_3OPS(GPR, 64);
142-
CHECK_VALUEMAP_3OPS(FPR, 32);
143-
CHECK_VALUEMAP_3OPS(FPR, 64);
144-
CHECK_VALUEMAP_3OPS(FPR, 128);
145-
CHECK_VALUEMAP_3OPS(FPR, 256);
146-
CHECK_VALUEMAP_3OPS(FPR, 512);
140+
CHECK_VALUEMAP_3OPS(GPR, 32);
141+
CHECK_VALUEMAP_3OPS(GPR, 64);
142+
CHECK_VALUEMAP_3OPS(FPR, 32);
143+
CHECK_VALUEMAP_3OPS(FPR, 64);
144+
CHECK_VALUEMAP_3OPS(FPR, 128);
145+
CHECK_VALUEMAP_3OPS(FPR, 256);
146+
CHECK_VALUEMAP_3OPS(FPR, 512);
147147

148148
#define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size) \
149149
do { \
@@ -165,14 +165,14 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
165165
\
166166
} while (false)
167167

168-
CHECK_VALUEMAP_CROSSREGCPY(GPR, GPR, 32);
169-
CHECK_VALUEMAP_CROSSREGCPY(GPR, FPR, 32);
170-
CHECK_VALUEMAP_CROSSREGCPY(GPR, GPR, 64);
171-
CHECK_VALUEMAP_CROSSREGCPY(GPR, FPR, 64);
172-
CHECK_VALUEMAP_CROSSREGCPY(FPR, FPR, 32);
173-
CHECK_VALUEMAP_CROSSREGCPY(FPR, GPR, 32);
174-
CHECK_VALUEMAP_CROSSREGCPY(FPR, FPR, 64);
175-
CHECK_VALUEMAP_CROSSREGCPY(FPR, GPR, 64);
168+
CHECK_VALUEMAP_CROSSREGCPY(GPR, GPR, 32);
169+
CHECK_VALUEMAP_CROSSREGCPY(GPR, FPR, 32);
170+
CHECK_VALUEMAP_CROSSREGCPY(GPR, GPR, 64);
171+
CHECK_VALUEMAP_CROSSREGCPY(GPR, FPR, 64);
172+
CHECK_VALUEMAP_CROSSREGCPY(FPR, FPR, 32);
173+
CHECK_VALUEMAP_CROSSREGCPY(FPR, GPR, 32);
174+
CHECK_VALUEMAP_CROSSREGCPY(FPR, FPR, 64);
175+
CHECK_VALUEMAP_CROSSREGCPY(FPR, GPR, 64);
176176

177177
#define CHECK_VALUEMAP_FPEXT(DstSize, SrcSize) \
178178
do { \
@@ -193,15 +193,12 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
193193
\
194194
} while (false)
195195

196-
CHECK_VALUEMAP_FPEXT(32, 16);
197-
CHECK_VALUEMAP_FPEXT(64, 16);
198-
CHECK_VALUEMAP_FPEXT(64, 32);
199-
CHECK_VALUEMAP_FPEXT(128, 64);
196+
CHECK_VALUEMAP_FPEXT(32, 16);
197+
CHECK_VALUEMAP_FPEXT(64, 16);
198+
CHECK_VALUEMAP_FPEXT(64, 32);
199+
CHECK_VALUEMAP_FPEXT(128, 64);
200200

201-
assert(verify(TRI) && "Invalid register bank information");
202-
};
203-
204-
llvm::call_once(InitializeRegisterBankFlag, InitializeRegisterBankOnce, TRI);
201+
assert(verify(TRI) && "Invalid register bank information");
205202
}
206203

207204
unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A,

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