-
Notifications
You must be signed in to change notification settings - Fork 13.1k
Pull requests: llvm/llvm-project
Author
Label
Projects
Milestones
Reviews
Assignee
Sort
Pull requests list
[RISCV] Use templates to reduce duplicated code for assembler operand predicates.
backend:RISC-V
#133351
opened Mar 28, 2025 by
topperc
[RISCV] Add MC layer support for XSfmm*.
backend:RISC-V
clang:driver
'clang' and 'clang++' user-facing binaries. Not 'clang-cl'
clang
Clang issues not falling into any other category
mc
Machine (object) code
#133031
opened Mar 26, 2025 by
topperc
[TableGen] Validate the shift amount for !srl, !shl, and !sra operators.
tablegen
#132492
opened Mar 21, 2025 by
topperc
[RISCV] Move vendor extensions after standard extensions in RISCVDisassembler::getInstruction16.
backend:RISC-V
#130821
opened Mar 11, 2025 by
topperc
[VP][RISCV] Add a vp.load.ff intrinsic for fault only first load.
backend:RISC-V
llvm:ir
llvm:SelectionDAG
SelectionDAGISel as well
[SelectionDAG] Use size_t for ResNo in SDValue.
llvm:SelectionDAG
SelectionDAGISel as well
#104660
opened Aug 17, 2024 by
topperc
[LegalizeDAG][X86][AArch64][LoongArch] Freeze index when converting extract_elt/extract_subvector to load/store on stack.
backend:AArch64
backend:loongarch
backend:X86
llvm:SelectionDAG
SelectionDAGISel as well
#88985
opened Apr 16, 2024 by
topperc
[DAGCombiner][X86][WIP] Combine (build_vector (load X))->(vecty (load X))
backend:X86
llvm:SelectionDAG
SelectionDAGISel as well
#88753
opened Apr 15, 2024 by
topperc
[LegalizeTypes][X86][PowerPC] Use shift by 1 instead of adding a value to itself to double.
backend:PowerPC
backend:X86
llvm:SelectionDAG
SelectionDAGISel as well
#86857
opened Mar 27, 2024 by
topperc
[InstCombine] Teach tryFactorization to treat a disjoint Or like an Add.
llvm:transforms
#75691
opened Dec 16, 2023 by
topperc
ProTip!
Exclude everything labeled
bug
with -label:bug.