[MSan] Separated PPC32 va_arg helper from PPC64 #131827
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* Added VarArgPowerPC32Helper; * Updated MemorySanitizer ppc32 tests to represent PowerPC32Helper behaviour;
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@llvm/pr-subscribers-llvm-transforms Author: None (k-kashapov) ChangesWith more understanding of PowerPC32 ABI we've rewritten the @vitalybuka @EugeneZelenko please review Patch is 48.39 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/131827.diff 4 Files Affected:
diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
index 49c8d384dfe73..f60606535fa41 100644
--- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
@@ -581,7 +581,8 @@ class MemorySanitizer {
friend struct VarArgHelperBase;
friend struct VarArgAMD64Helper;
friend struct VarArgAArch64Helper;
- friend struct VarArgPowerPCHelper;
+ friend struct VarArgPowerPC64Helper;
+ friend struct VarArgPowerPC32Helper;
friend struct VarArgSystemZHelper;
friend struct VarArgI386Helper;
friend struct VarArgGenericHelper;
@@ -6271,14 +6272,14 @@ struct VarArgAArch64Helper : public VarArgHelperBase {
}
};
-/// PowerPC-specific implementation of VarArgHelper.
-struct VarArgPowerPCHelper : public VarArgHelperBase {
+/// PowerPC64-specific implementation of VarArgHelper.
+struct VarArgPowerPC64Helper : public VarArgHelperBase {
AllocaInst *VAArgTLSCopy = nullptr;
Value *VAArgSize = nullptr;
- VarArgPowerPCHelper(Function &F, MemorySanitizer &MS,
- MemorySanitizerVisitor &MSV, unsigned VAListTagSize)
- : VarArgHelperBase(F, MS, MSV, VAListTagSize) {}
+ VarArgPowerPC64Helper(Function &F, MemorySanitizer &MS,
+ MemorySanitizerVisitor &MSV)
+ : VarArgHelperBase(F, MS, MSV, /*VAListTagSize=*/8) {}
void visitCallBase(CallBase &CB, IRBuilder<> &IRB) override {
// For PowerPC, we need to deal with alignment of stack arguments -
@@ -6292,15 +6293,10 @@ struct VarArgPowerPCHelper : public VarArgHelperBase {
// Parameter save area starts at 48 bytes from frame pointer for ABIv1,
// and 32 bytes for ABIv2. This is usually determined by target
// endianness, but in theory could be overridden by function attribute.
- if (TargetTriple.isPPC64()) {
- if (TargetTriple.isPPC64ELFv2ABI())
- VAArgBase = 32;
- else
- VAArgBase = 48;
- } else {
- // Parameter save area is 8 bytes from frame pointer in PPC32
- VAArgBase = 8;
- }
+ if (TargetTriple.isPPC64ELFv2ABI())
+ VAArgBase = 32;
+ else
+ VAArgBase = 48;
unsigned VAArgOffset = VAArgBase;
const DataLayout &DL = F.getDataLayout();
for (const auto &[ArgNo, A] : llvm::enumerate(CB.args())) {
@@ -6402,11 +6398,6 @@ struct VarArgPowerPCHelper : public VarArgHelperBase {
Value *VAListTag = OrigInst->getArgOperand(0);
Value *RegSaveAreaPtrPtr = IRB.CreatePtrToInt(VAListTag, MS.IntptrTy);
- // In PPC32 va_list_tag is a struct, whereas in PPC64 it's a pointer
- if (!TargetTriple.isPPC64()) {
- RegSaveAreaPtrPtr =
- IRB.CreateAdd(RegSaveAreaPtrPtr, ConstantInt::get(MS.IntptrTy, 8));
- }
RegSaveAreaPtrPtr = IRB.CreateIntToPtr(RegSaveAreaPtrPtr, MS.PtrTy);
Value *RegSaveAreaPtr = IRB.CreateLoad(MS.PtrTy, RegSaveAreaPtrPtr);
@@ -6423,6 +6414,195 @@ struct VarArgPowerPCHelper : public VarArgHelperBase {
}
};
+/// PowerPC32-specific implementation of VarArgHelper.
+struct VarArgPowerPC32Helper : public VarArgHelperBase {
+ AllocaInst *VAArgTLSCopy = nullptr;
+ Value *VAArgSize = nullptr;
+
+ VarArgPowerPC32Helper(Function &F, MemorySanitizer &MS,
+ MemorySanitizerVisitor &MSV)
+ : VarArgHelperBase(F, MS, MSV, /*VAListTagSize=*/12) {}
+
+ void visitCallBase(CallBase &CB, IRBuilder<> &IRB) override {
+ unsigned VAArgBase;
+ Triple TargetTriple(F.getParent()->getTargetTriple());
+ // Parameter save area is 8 bytes from frame pointer in PPC32
+ VAArgBase = 8;
+ unsigned VAArgOffset = VAArgBase;
+ const DataLayout &DL = F.getDataLayout();
+ unsigned IntptrSize = DL.getTypeStoreSize(IRB.getInt32Ty());
+ for (const auto &[ArgNo, A] : llvm::enumerate(CB.args())) {
+ bool IsFixed = ArgNo < CB.getFunctionType()->getNumParams();
+ bool IsByVal = CB.paramHasAttr(ArgNo, Attribute::ByVal);
+ if (IsByVal) {
+ assert(A->getType()->isPointerTy());
+ Type *RealTy = CB.getParamByValType(ArgNo);
+ uint64_t ArgSize = DL.getTypeAllocSize(RealTy);
+ Align ArgAlign = CB.getParamAlign(ArgNo).value_or(Align(IntptrSize));
+ if (ArgAlign < IntptrSize)
+ ArgAlign = Align(IntptrSize);
+ VAArgOffset = alignTo(VAArgOffset, ArgAlign);
+ if (!IsFixed) {
+ Value *Base =
+ getShadowPtrForVAArgument(IRB, VAArgOffset - VAArgBase, ArgSize);
+ if (Base) {
+ Value *AShadowPtr, *AOriginPtr;
+ std::tie(AShadowPtr, AOriginPtr) =
+ MSV.getShadowOriginPtr(A, IRB, IRB.getInt8Ty(),
+ kShadowTLSAlignment, /*isStore*/ false);
+
+ IRB.CreateMemCpy(Base, kShadowTLSAlignment, AShadowPtr,
+ kShadowTLSAlignment, ArgSize);
+ }
+ }
+ VAArgOffset += alignTo(ArgSize, Align(IntptrSize));
+ } else {
+ Value *Base;
+ Type *ArgTy = A->getType();
+
+ // On PPC 32 floating point variable arguments are stored in separate
+ // area: fp_save_area = reg_save_area + 4*8. We do not copy shaodow for
+ // them as they will be found when checking call arguments.
+ if (!ArgTy->isFloatingPointTy()) {
+ uint64_t ArgSize = DL.getTypeAllocSize(ArgTy);
+ Align ArgAlign = Align(IntptrSize);
+ if (ArgTy->isArrayTy()) {
+ // Arrays are aligned to element size, except for long double
+ // arrays, which are aligned to 8 bytes.
+ Type *ElementTy = ArgTy->getArrayElementType();
+ if (!ElementTy->isPPC_FP128Ty())
+ ArgAlign = Align(DL.getTypeAllocSize(ElementTy));
+ } else if (ArgTy->isVectorTy()) {
+ // Vectors are naturally aligned.
+ ArgAlign = Align(ArgSize);
+ }
+ if (ArgAlign < IntptrSize)
+ ArgAlign = Align(IntptrSize);
+ VAArgOffset = alignTo(VAArgOffset, ArgAlign);
+ if (DL.isBigEndian()) {
+ // Adjusting the shadow for argument with size < IntptrSize to match
+ // the placement of bits in big endian system
+ if (ArgSize < IntptrSize)
+ VAArgOffset += (IntptrSize - ArgSize);
+ }
+ if (!IsFixed) {
+ Base = getShadowPtrForVAArgument(IRB, VAArgOffset - VAArgBase,
+ ArgSize);
+ if (Base)
+ IRB.CreateAlignedStore(MSV.getShadow(A), Base,
+ kShadowTLSAlignment);
+ }
+ VAArgOffset += ArgSize;
+ VAArgOffset = alignTo(VAArgOffset, Align(IntptrSize));
+ }
+ }
+ }
+
+ Constant *TotalVAArgSize =
+ ConstantInt::get(IRB.getInt32Ty(), VAArgOffset - VAArgBase);
+ // Here using VAArgOverflowSizeTLS as VAArgSizeTLS to avoid creation of
+ // a new class member i.e. it is the total size of all VarArgs.
+ IRB.CreateStore(TotalVAArgSize, MS.VAArgOverflowSizeTLS);
+ }
+
+ void finalizeInstrumentation() override {
+ assert(!VAArgSize && !VAArgTLSCopy &&
+ "finalizeInstrumentation called twice");
+ IRBuilder<> IRB(MSV.FnPrologueEnd);
+ VAArgSize = IRB.CreateLoad(IRB.getInt32Ty(), MS.VAArgOverflowSizeTLS);
+ Value *CopySize = VAArgSize;
+
+ if (!VAStartInstrumentationList.empty()) {
+ // If there is a va_start in this function, make a backup copy of
+ // va_arg_tls somewhere in the function entry block.
+
+ VAArgTLSCopy = IRB.CreateAlloca(Type::getInt8Ty(*MS.C), CopySize);
+ VAArgTLSCopy->setAlignment(kShadowTLSAlignment);
+ IRB.CreateMemSet(VAArgTLSCopy, Constant::getNullValue(IRB.getInt8Ty()),
+ CopySize, kShadowTLSAlignment, false);
+
+ Value *SrcSize = IRB.CreateBinaryIntrinsic(
+ Intrinsic::umin, CopySize,
+ ConstantInt::get(IRB.getInt32Ty(), kParamTLSSize));
+ IRB.CreateMemCpy(VAArgTLSCopy, kShadowTLSAlignment, MS.VAArgTLS,
+ kShadowTLSAlignment, SrcSize);
+ }
+
+ // Instrument va_start.
+ // Copy va_list shadow from the backup copy of the TLS contents.
+ Triple TargetTriple(F.getParent()->getTargetTriple());
+ for (CallInst *OrigInst : VAStartInstrumentationList) {
+ NextNodeIRBuilder IRB(OrigInst);
+ Value *VAListTag = OrigInst->getArgOperand(0);
+ Value *RegSaveAreaPtrPtr =
+ IRB.CreatePtrToInt(VAListTag, IRB.getInt32Ty());
+ Value *RegSaveAreaSize = CopySize;
+
+ // In PPC32 va_list_tag is a struct
+ RegSaveAreaPtrPtr = IRB.CreateAdd(RegSaveAreaPtrPtr,
+ ConstantInt::get(IRB.getInt32Ty(), 8));
+
+ // On PPC 32 reg_save_area can only hold 32 bytes of data
+ RegSaveAreaSize = IRB.CreateBinaryIntrinsic(
+ Intrinsic::umin, CopySize, ConstantInt::get(IRB.getInt32Ty(), 32));
+
+ RegSaveAreaPtrPtr = IRB.CreateIntToPtr(RegSaveAreaPtrPtr, MS.PtrTy);
+ Value *RegSaveAreaPtr = IRB.CreateLoad(MS.PtrTy, RegSaveAreaPtrPtr);
+
+ const DataLayout &DL = F.getDataLayout();
+ unsigned IntptrSize = DL.getTypeStoreSize(IRB.getInt32Ty());
+ const Align Alignment = Align(IntptrSize);
+
+ { // Copy reg save area
+ Value *RegSaveAreaShadowPtr, *RegSaveAreaOriginPtr;
+ std::tie(RegSaveAreaShadowPtr, RegSaveAreaOriginPtr) =
+ MSV.getShadowOriginPtr(RegSaveAreaPtr, IRB, IRB.getInt8Ty(),
+ Alignment, /*isStore*/ true);
+ IRB.CreateMemCpy(RegSaveAreaShadowPtr, Alignment, VAArgTLSCopy,
+ Alignment, RegSaveAreaSize);
+
+ RegSaveAreaShadowPtr =
+ IRB.CreatePtrToInt(RegSaveAreaShadowPtr, IRB.getInt32Ty());
+ Value *FPSaveArea = IRB.CreateAdd(
+ RegSaveAreaShadowPtr, ConstantInt::get(IRB.getInt32Ty(), 32));
+ FPSaveArea = IRB.CreateIntToPtr(FPSaveArea, MS.PtrTy);
+ // We fill fp shadow with zeroes as uninitialized fp args should have
+ // been found during call base check
+ IRB.CreateMemSet(FPSaveArea, ConstantInt::getNullValue(IRB.getInt8Ty()),
+ ConstantInt::get(IRB.getInt32Ty(), 32), Alignment);
+ }
+
+ { // Copy overflow area
+ // RegSaveAreaSize is min(CopySize, 32) -> no overflow can occur
+ Value *OverflowAreaSize = IRB.CreateSub(CopySize, RegSaveAreaSize);
+
+ Value *OverflowAreaPtrPtr =
+ IRB.CreatePtrToInt(VAListTag, IRB.getInt32Ty());
+ OverflowAreaPtrPtr = IRB.CreateAdd(
+ OverflowAreaPtrPtr, ConstantInt::get(IRB.getInt32Ty(), 4));
+ OverflowAreaPtrPtr = IRB.CreateIntToPtr(OverflowAreaPtrPtr, MS.PtrTy);
+
+ Value *OverflowAreaPtr = IRB.CreateLoad(MS.PtrTy, OverflowAreaPtrPtr);
+
+ Value *OverflowAreaShadowPtr, *OverflowAreaOriginPtr;
+ std::tie(OverflowAreaShadowPtr, OverflowAreaOriginPtr) =
+ MSV.getShadowOriginPtr(OverflowAreaPtr, IRB, IRB.getInt8Ty(),
+ Alignment, /*isStore*/ true);
+
+ Value *OverflowVAArgTLSCopyPtr =
+ IRB.CreatePtrToInt(VAArgTLSCopy, IRB.getInt32Ty());
+ OverflowVAArgTLSCopyPtr =
+ IRB.CreateAdd(OverflowVAArgTLSCopyPtr, RegSaveAreaSize);
+
+ OverflowVAArgTLSCopyPtr =
+ IRB.CreateIntToPtr(OverflowVAArgTLSCopyPtr, MS.PtrTy);
+ IRB.CreateMemCpy(OverflowAreaShadowPtr, Alignment,
+ OverflowVAArgTLSCopyPtr, Alignment, OverflowAreaSize);
+ }
+ }
+ }
+};
+
/// SystemZ-specific implementation of VarArgHelper.
struct VarArgSystemZHelper : public VarArgHelperBase {
static const unsigned SystemZGpOffset = 16;
@@ -6946,10 +7126,10 @@ static VarArgHelper *CreateVarArgHelper(Function &Func, MemorySanitizer &Msan,
// On PowerPC32 VAListTag is a struct
// {char, char, i16 padding, char *, char *}
if (TargetTriple.isPPC32())
- return new VarArgPowerPCHelper(Func, Msan, Visitor, /*VAListTagSize=*/12);
+ return new VarArgPowerPC32Helper(Func, Msan, Visitor);
if (TargetTriple.isPPC64())
- return new VarArgPowerPCHelper(Func, Msan, Visitor, /*VAListTagSize=*/8);
+ return new VarArgPowerPC64Helper(Func, Msan, Visitor);
if (TargetTriple.isRISCV32())
return new VarArgRISCVHelper(Func, Msan, Visitor, /*VAListTagSize=*/4);
diff --git a/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/kernel-ppcle.ll b/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/kernel-ppcle.ll
index bbf6842cd82c9..2a66097f2f2ff 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/kernel-ppcle.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/kernel-ppcle.ll
@@ -22,7 +22,7 @@ define void @Store1(ptr %p, i8 %x) sanitize_memory {
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PARAM_ORIGIN]] to i64
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[VA_ARG_OVERFLOW_SIZE]], align 4
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PARAM_SHADOW]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 8
; CHECK-NEXT: [[_MSARG1:%.*]] = inttoptr i64 [[TMP8]] to ptr
@@ -76,7 +76,7 @@ define void @Store2(ptr %p, i16 %x) sanitize_memory {
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PARAM_ORIGIN]] to i64
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[VA_ARG_OVERFLOW_SIZE]], align 4
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PARAM_SHADOW]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 8
; CHECK-NEXT: [[_MSARG1:%.*]] = inttoptr i64 [[TMP8]] to ptr
@@ -130,7 +130,7 @@ define void @Store4(ptr %p, i32 %x) sanitize_memory {
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PARAM_ORIGIN]] to i64
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[VA_ARG_OVERFLOW_SIZE]], align 4
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PARAM_SHADOW]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 8
; CHECK-NEXT: [[_MSARG1:%.*]] = inttoptr i64 [[TMP8]] to ptr
@@ -184,7 +184,7 @@ define void @Store8(ptr %p, i64 %x) sanitize_memory {
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PARAM_ORIGIN]] to i64
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[VA_ARG_OVERFLOW_SIZE]], align 4
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PARAM_SHADOW]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 8
; CHECK-NEXT: [[_MSARG1:%.*]] = inttoptr i64 [[TMP8]] to ptr
@@ -241,7 +241,7 @@ define void @Store16(ptr %p, i128 %x) sanitize_memory {
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PARAM_ORIGIN]] to i64
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[VA_ARG_OVERFLOW_SIZE]], align 4
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PARAM_SHADOW]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 8
; CHECK-NEXT: [[_MSARG1:%.*]] = inttoptr i64 [[TMP8]] to ptr
@@ -300,7 +300,7 @@ define i8 @Load1(ptr %p) sanitize_memory {
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PARAM_ORIGIN]] to i64
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[VA_ARG_OVERFLOW_SIZE]], align 4
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]
@@ -342,7 +342,7 @@ define i16 @Load2(ptr %p) sanitize_memory {
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PARAM_ORIGIN]] to i64
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[VA_ARG_OVERFLOW_SIZE]], align 4
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]
@@ -384,7 +384,7 @@ define i32 @Load4(ptr %p) sanitize_memory {
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PARAM_ORIGIN]] to i64
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[VA_ARG_OVERFLOW_SIZE]], align 4
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]
@@ -426,7 +426,7 @@ define i64 @Load8(ptr %p) sanitize_memory {
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PARAM_ORIGIN]] to i64
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[VA_ARG_OVERFLOW_SIZE]], align 4
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]
@@ -468,7 +468,7 @@ define i128 @Load16(ptr %p) sanitize_memory {
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PARAM_ORIGIN]] to i64
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[VA_ARG_OVERFLOW_SIZE]], align 4
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]
diff --git a/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppc.ll b/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppc.ll
index d05b11f3f050d..45929e91cfed7 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppc.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppc.ll
@@ -7,11 +7,11 @@ target triple = "powerpc--linux"
define i32 @foo(i32 %guard, ...) {
; CHECK-LABEL: define i32 @foo(
; CHECK-SAME: i32 [[GUARD:%.*]], ...) {
-; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP3:%.*]] = alloca i8, i64 [[TMP2]], align 8
-; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP3]], i8 0, i64 [[TMP2]], i1 false)
-; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 800)
-; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP3]], ptr align 8 @__msan_va_arg_tls, i64 [[TMP4]], i1 false)
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_va_arg_overflow_size_tls, align 4
+; CHECK-NEXT: [[TMP2:%.*]] = alloca i8, i32 [[TMP1]], align 8
+; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 8 [[TMP2]], i8 0, i32 [[TMP1]], i1 false)
+; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP1]], i32 800)
+; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[TMP2]], ptr align 8 @__msan_va_arg_tls, i32 ...
[truncated]
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@llvm/pr-subscribers-compiler-rt-sanitizer Author: None (k-kashapov) ChangesWith more understanding of PowerPC32 ABI we've rewritten the @vitalybuka @EugeneZelenko please review Patch is 48.39 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/131827.diff 4 Files Affected:
diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
index 49c8d384dfe73..f60606535fa41 100644
--- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
@@ -581,7 +581,8 @@ class MemorySanitizer {
friend struct VarArgHelperBase;
friend struct VarArgAMD64Helper;
friend struct VarArgAArch64Helper;
- friend struct VarArgPowerPCHelper;
+ friend struct VarArgPowerPC64Helper;
+ friend struct VarArgPowerPC32Helper;
friend struct VarArgSystemZHelper;
friend struct VarArgI386Helper;
friend struct VarArgGenericHelper;
@@ -6271,14 +6272,14 @@ struct VarArgAArch64Helper : public VarArgHelperBase {
}
};
-/// PowerPC-specific implementation of VarArgHelper.
-struct VarArgPowerPCHelper : public VarArgHelperBase {
+/// PowerPC64-specific implementation of VarArgHelper.
+struct VarArgPowerPC64Helper : public VarArgHelperBase {
AllocaInst *VAArgTLSCopy = nullptr;
Value *VAArgSize = nullptr;
- VarArgPowerPCHelper(Function &F, MemorySanitizer &MS,
- MemorySanitizerVisitor &MSV, unsigned VAListTagSize)
- : VarArgHelperBase(F, MS, MSV, VAListTagSize) {}
+ VarArgPowerPC64Helper(Function &F, MemorySanitizer &MS,
+ MemorySanitizerVisitor &MSV)
+ : VarArgHelperBase(F, MS, MSV, /*VAListTagSize=*/8) {}
void visitCallBase(CallBase &CB, IRBuilder<> &IRB) override {
// For PowerPC, we need to deal with alignment of stack arguments -
@@ -6292,15 +6293,10 @@ struct VarArgPowerPCHelper : public VarArgHelperBase {
// Parameter save area starts at 48 bytes from frame pointer for ABIv1,
// and 32 bytes for ABIv2. This is usually determined by target
// endianness, but in theory could be overridden by function attribute.
- if (TargetTriple.isPPC64()) {
- if (TargetTriple.isPPC64ELFv2ABI())
- VAArgBase = 32;
- else
- VAArgBase = 48;
- } else {
- // Parameter save area is 8 bytes from frame pointer in PPC32
- VAArgBase = 8;
- }
+ if (TargetTriple.isPPC64ELFv2ABI())
+ VAArgBase = 32;
+ else
+ VAArgBase = 48;
unsigned VAArgOffset = VAArgBase;
const DataLayout &DL = F.getDataLayout();
for (const auto &[ArgNo, A] : llvm::enumerate(CB.args())) {
@@ -6402,11 +6398,6 @@ struct VarArgPowerPCHelper : public VarArgHelperBase {
Value *VAListTag = OrigInst->getArgOperand(0);
Value *RegSaveAreaPtrPtr = IRB.CreatePtrToInt(VAListTag, MS.IntptrTy);
- // In PPC32 va_list_tag is a struct, whereas in PPC64 it's a pointer
- if (!TargetTriple.isPPC64()) {
- RegSaveAreaPtrPtr =
- IRB.CreateAdd(RegSaveAreaPtrPtr, ConstantInt::get(MS.IntptrTy, 8));
- }
RegSaveAreaPtrPtr = IRB.CreateIntToPtr(RegSaveAreaPtrPtr, MS.PtrTy);
Value *RegSaveAreaPtr = IRB.CreateLoad(MS.PtrTy, RegSaveAreaPtrPtr);
@@ -6423,6 +6414,195 @@ struct VarArgPowerPCHelper : public VarArgHelperBase {
}
};
+/// PowerPC32-specific implementation of VarArgHelper.
+struct VarArgPowerPC32Helper : public VarArgHelperBase {
+ AllocaInst *VAArgTLSCopy = nullptr;
+ Value *VAArgSize = nullptr;
+
+ VarArgPowerPC32Helper(Function &F, MemorySanitizer &MS,
+ MemorySanitizerVisitor &MSV)
+ : VarArgHelperBase(F, MS, MSV, /*VAListTagSize=*/12) {}
+
+ void visitCallBase(CallBase &CB, IRBuilder<> &IRB) override {
+ unsigned VAArgBase;
+ Triple TargetTriple(F.getParent()->getTargetTriple());
+ // Parameter save area is 8 bytes from frame pointer in PPC32
+ VAArgBase = 8;
+ unsigned VAArgOffset = VAArgBase;
+ const DataLayout &DL = F.getDataLayout();
+ unsigned IntptrSize = DL.getTypeStoreSize(IRB.getInt32Ty());
+ for (const auto &[ArgNo, A] : llvm::enumerate(CB.args())) {
+ bool IsFixed = ArgNo < CB.getFunctionType()->getNumParams();
+ bool IsByVal = CB.paramHasAttr(ArgNo, Attribute::ByVal);
+ if (IsByVal) {
+ assert(A->getType()->isPointerTy());
+ Type *RealTy = CB.getParamByValType(ArgNo);
+ uint64_t ArgSize = DL.getTypeAllocSize(RealTy);
+ Align ArgAlign = CB.getParamAlign(ArgNo).value_or(Align(IntptrSize));
+ if (ArgAlign < IntptrSize)
+ ArgAlign = Align(IntptrSize);
+ VAArgOffset = alignTo(VAArgOffset, ArgAlign);
+ if (!IsFixed) {
+ Value *Base =
+ getShadowPtrForVAArgument(IRB, VAArgOffset - VAArgBase, ArgSize);
+ if (Base) {
+ Value *AShadowPtr, *AOriginPtr;
+ std::tie(AShadowPtr, AOriginPtr) =
+ MSV.getShadowOriginPtr(A, IRB, IRB.getInt8Ty(),
+ kShadowTLSAlignment, /*isStore*/ false);
+
+ IRB.CreateMemCpy(Base, kShadowTLSAlignment, AShadowPtr,
+ kShadowTLSAlignment, ArgSize);
+ }
+ }
+ VAArgOffset += alignTo(ArgSize, Align(IntptrSize));
+ } else {
+ Value *Base;
+ Type *ArgTy = A->getType();
+
+ // On PPC 32 floating point variable arguments are stored in separate
+ // area: fp_save_area = reg_save_area + 4*8. We do not copy shaodow for
+ // them as they will be found when checking call arguments.
+ if (!ArgTy->isFloatingPointTy()) {
+ uint64_t ArgSize = DL.getTypeAllocSize(ArgTy);
+ Align ArgAlign = Align(IntptrSize);
+ if (ArgTy->isArrayTy()) {
+ // Arrays are aligned to element size, except for long double
+ // arrays, which are aligned to 8 bytes.
+ Type *ElementTy = ArgTy->getArrayElementType();
+ if (!ElementTy->isPPC_FP128Ty())
+ ArgAlign = Align(DL.getTypeAllocSize(ElementTy));
+ } else if (ArgTy->isVectorTy()) {
+ // Vectors are naturally aligned.
+ ArgAlign = Align(ArgSize);
+ }
+ if (ArgAlign < IntptrSize)
+ ArgAlign = Align(IntptrSize);
+ VAArgOffset = alignTo(VAArgOffset, ArgAlign);
+ if (DL.isBigEndian()) {
+ // Adjusting the shadow for argument with size < IntptrSize to match
+ // the placement of bits in big endian system
+ if (ArgSize < IntptrSize)
+ VAArgOffset += (IntptrSize - ArgSize);
+ }
+ if (!IsFixed) {
+ Base = getShadowPtrForVAArgument(IRB, VAArgOffset - VAArgBase,
+ ArgSize);
+ if (Base)
+ IRB.CreateAlignedStore(MSV.getShadow(A), Base,
+ kShadowTLSAlignment);
+ }
+ VAArgOffset += ArgSize;
+ VAArgOffset = alignTo(VAArgOffset, Align(IntptrSize));
+ }
+ }
+ }
+
+ Constant *TotalVAArgSize =
+ ConstantInt::get(IRB.getInt32Ty(), VAArgOffset - VAArgBase);
+ // Here using VAArgOverflowSizeTLS as VAArgSizeTLS to avoid creation of
+ // a new class member i.e. it is the total size of all VarArgs.
+ IRB.CreateStore(TotalVAArgSize, MS.VAArgOverflowSizeTLS);
+ }
+
+ void finalizeInstrumentation() override {
+ assert(!VAArgSize && !VAArgTLSCopy &&
+ "finalizeInstrumentation called twice");
+ IRBuilder<> IRB(MSV.FnPrologueEnd);
+ VAArgSize = IRB.CreateLoad(IRB.getInt32Ty(), MS.VAArgOverflowSizeTLS);
+ Value *CopySize = VAArgSize;
+
+ if (!VAStartInstrumentationList.empty()) {
+ // If there is a va_start in this function, make a backup copy of
+ // va_arg_tls somewhere in the function entry block.
+
+ VAArgTLSCopy = IRB.CreateAlloca(Type::getInt8Ty(*MS.C), CopySize);
+ VAArgTLSCopy->setAlignment(kShadowTLSAlignment);
+ IRB.CreateMemSet(VAArgTLSCopy, Constant::getNullValue(IRB.getInt8Ty()),
+ CopySize, kShadowTLSAlignment, false);
+
+ Value *SrcSize = IRB.CreateBinaryIntrinsic(
+ Intrinsic::umin, CopySize,
+ ConstantInt::get(IRB.getInt32Ty(), kParamTLSSize));
+ IRB.CreateMemCpy(VAArgTLSCopy, kShadowTLSAlignment, MS.VAArgTLS,
+ kShadowTLSAlignment, SrcSize);
+ }
+
+ // Instrument va_start.
+ // Copy va_list shadow from the backup copy of the TLS contents.
+ Triple TargetTriple(F.getParent()->getTargetTriple());
+ for (CallInst *OrigInst : VAStartInstrumentationList) {
+ NextNodeIRBuilder IRB(OrigInst);
+ Value *VAListTag = OrigInst->getArgOperand(0);
+ Value *RegSaveAreaPtrPtr =
+ IRB.CreatePtrToInt(VAListTag, IRB.getInt32Ty());
+ Value *RegSaveAreaSize = CopySize;
+
+ // In PPC32 va_list_tag is a struct
+ RegSaveAreaPtrPtr = IRB.CreateAdd(RegSaveAreaPtrPtr,
+ ConstantInt::get(IRB.getInt32Ty(), 8));
+
+ // On PPC 32 reg_save_area can only hold 32 bytes of data
+ RegSaveAreaSize = IRB.CreateBinaryIntrinsic(
+ Intrinsic::umin, CopySize, ConstantInt::get(IRB.getInt32Ty(), 32));
+
+ RegSaveAreaPtrPtr = IRB.CreateIntToPtr(RegSaveAreaPtrPtr, MS.PtrTy);
+ Value *RegSaveAreaPtr = IRB.CreateLoad(MS.PtrTy, RegSaveAreaPtrPtr);
+
+ const DataLayout &DL = F.getDataLayout();
+ unsigned IntptrSize = DL.getTypeStoreSize(IRB.getInt32Ty());
+ const Align Alignment = Align(IntptrSize);
+
+ { // Copy reg save area
+ Value *RegSaveAreaShadowPtr, *RegSaveAreaOriginPtr;
+ std::tie(RegSaveAreaShadowPtr, RegSaveAreaOriginPtr) =
+ MSV.getShadowOriginPtr(RegSaveAreaPtr, IRB, IRB.getInt8Ty(),
+ Alignment, /*isStore*/ true);
+ IRB.CreateMemCpy(RegSaveAreaShadowPtr, Alignment, VAArgTLSCopy,
+ Alignment, RegSaveAreaSize);
+
+ RegSaveAreaShadowPtr =
+ IRB.CreatePtrToInt(RegSaveAreaShadowPtr, IRB.getInt32Ty());
+ Value *FPSaveArea = IRB.CreateAdd(
+ RegSaveAreaShadowPtr, ConstantInt::get(IRB.getInt32Ty(), 32));
+ FPSaveArea = IRB.CreateIntToPtr(FPSaveArea, MS.PtrTy);
+ // We fill fp shadow with zeroes as uninitialized fp args should have
+ // been found during call base check
+ IRB.CreateMemSet(FPSaveArea, ConstantInt::getNullValue(IRB.getInt8Ty()),
+ ConstantInt::get(IRB.getInt32Ty(), 32), Alignment);
+ }
+
+ { // Copy overflow area
+ // RegSaveAreaSize is min(CopySize, 32) -> no overflow can occur
+ Value *OverflowAreaSize = IRB.CreateSub(CopySize, RegSaveAreaSize);
+
+ Value *OverflowAreaPtrPtr =
+ IRB.CreatePtrToInt(VAListTag, IRB.getInt32Ty());
+ OverflowAreaPtrPtr = IRB.CreateAdd(
+ OverflowAreaPtrPtr, ConstantInt::get(IRB.getInt32Ty(), 4));
+ OverflowAreaPtrPtr = IRB.CreateIntToPtr(OverflowAreaPtrPtr, MS.PtrTy);
+
+ Value *OverflowAreaPtr = IRB.CreateLoad(MS.PtrTy, OverflowAreaPtrPtr);
+
+ Value *OverflowAreaShadowPtr, *OverflowAreaOriginPtr;
+ std::tie(OverflowAreaShadowPtr, OverflowAreaOriginPtr) =
+ MSV.getShadowOriginPtr(OverflowAreaPtr, IRB, IRB.getInt8Ty(),
+ Alignment, /*isStore*/ true);
+
+ Value *OverflowVAArgTLSCopyPtr =
+ IRB.CreatePtrToInt(VAArgTLSCopy, IRB.getInt32Ty());
+ OverflowVAArgTLSCopyPtr =
+ IRB.CreateAdd(OverflowVAArgTLSCopyPtr, RegSaveAreaSize);
+
+ OverflowVAArgTLSCopyPtr =
+ IRB.CreateIntToPtr(OverflowVAArgTLSCopyPtr, MS.PtrTy);
+ IRB.CreateMemCpy(OverflowAreaShadowPtr, Alignment,
+ OverflowVAArgTLSCopyPtr, Alignment, OverflowAreaSize);
+ }
+ }
+ }
+};
+
/// SystemZ-specific implementation of VarArgHelper.
struct VarArgSystemZHelper : public VarArgHelperBase {
static const unsigned SystemZGpOffset = 16;
@@ -6946,10 +7126,10 @@ static VarArgHelper *CreateVarArgHelper(Function &Func, MemorySanitizer &Msan,
// On PowerPC32 VAListTag is a struct
// {char, char, i16 padding, char *, char *}
if (TargetTriple.isPPC32())
- return new VarArgPowerPCHelper(Func, Msan, Visitor, /*VAListTagSize=*/12);
+ return new VarArgPowerPC32Helper(Func, Msan, Visitor);
if (TargetTriple.isPPC64())
- return new VarArgPowerPCHelper(Func, Msan, Visitor, /*VAListTagSize=*/8);
+ return new VarArgPowerPC64Helper(Func, Msan, Visitor);
if (TargetTriple.isRISCV32())
return new VarArgRISCVHelper(Func, Msan, Visitor, /*VAListTagSize=*/4);
diff --git a/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/kernel-ppcle.ll b/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/kernel-ppcle.ll
index bbf6842cd82c9..2a66097f2f2ff 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/kernel-ppcle.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/kernel-ppcle.ll
@@ -22,7 +22,7 @@ define void @Store1(ptr %p, i8 %x) sanitize_memory {
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PARAM_ORIGIN]] to i64
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[VA_ARG_OVERFLOW_SIZE]], align 4
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PARAM_SHADOW]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 8
; CHECK-NEXT: [[_MSARG1:%.*]] = inttoptr i64 [[TMP8]] to ptr
@@ -76,7 +76,7 @@ define void @Store2(ptr %p, i16 %x) sanitize_memory {
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PARAM_ORIGIN]] to i64
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[VA_ARG_OVERFLOW_SIZE]], align 4
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PARAM_SHADOW]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 8
; CHECK-NEXT: [[_MSARG1:%.*]] = inttoptr i64 [[TMP8]] to ptr
@@ -130,7 +130,7 @@ define void @Store4(ptr %p, i32 %x) sanitize_memory {
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PARAM_ORIGIN]] to i64
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[VA_ARG_OVERFLOW_SIZE]], align 4
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PARAM_SHADOW]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 8
; CHECK-NEXT: [[_MSARG1:%.*]] = inttoptr i64 [[TMP8]] to ptr
@@ -184,7 +184,7 @@ define void @Store8(ptr %p, i64 %x) sanitize_memory {
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PARAM_ORIGIN]] to i64
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[VA_ARG_OVERFLOW_SIZE]], align 4
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PARAM_SHADOW]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 8
; CHECK-NEXT: [[_MSARG1:%.*]] = inttoptr i64 [[TMP8]] to ptr
@@ -241,7 +241,7 @@ define void @Store16(ptr %p, i128 %x) sanitize_memory {
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PARAM_ORIGIN]] to i64
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[VA_ARG_OVERFLOW_SIZE]], align 4
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PARAM_SHADOW]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 8
; CHECK-NEXT: [[_MSARG1:%.*]] = inttoptr i64 [[TMP8]] to ptr
@@ -300,7 +300,7 @@ define i8 @Load1(ptr %p) sanitize_memory {
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PARAM_ORIGIN]] to i64
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[VA_ARG_OVERFLOW_SIZE]], align 4
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]
@@ -342,7 +342,7 @@ define i16 @Load2(ptr %p) sanitize_memory {
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PARAM_ORIGIN]] to i64
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[VA_ARG_OVERFLOW_SIZE]], align 4
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]
@@ -384,7 +384,7 @@ define i32 @Load4(ptr %p) sanitize_memory {
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PARAM_ORIGIN]] to i64
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[VA_ARG_OVERFLOW_SIZE]], align 4
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]
@@ -426,7 +426,7 @@ define i64 @Load8(ptr %p) sanitize_memory {
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PARAM_ORIGIN]] to i64
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[VA_ARG_OVERFLOW_SIZE]], align 4
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]
@@ -468,7 +468,7 @@ define i128 @Load16(ptr %p) sanitize_memory {
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PARAM_ORIGIN]] to i64
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
-; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[VA_ARG_OVERFLOW_SIZE]], align 4
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]
diff --git a/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppc.ll b/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppc.ll
index d05b11f3f050d..45929e91cfed7 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppc.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppc.ll
@@ -7,11 +7,11 @@ target triple = "powerpc--linux"
define i32 @foo(i32 %guard, ...) {
; CHECK-LABEL: define i32 @foo(
; CHECK-SAME: i32 [[GUARD:%.*]], ...) {
-; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP3:%.*]] = alloca i8, i64 [[TMP2]], align 8
-; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP3]], i8 0, i64 [[TMP2]], i1 false)
-; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 800)
-; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP3]], ptr align 8 @__msan_va_arg_tls, i64 [[TMP4]], i1 false)
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_va_arg_overflow_size_tls, align 4
+; CHECK-NEXT: [[TMP2:%.*]] = alloca i8, i32 [[TMP1]], align 8
+; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 8 [[TMP2]], i8 0, i32 [[TMP1]], i1 false)
+; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP1]], i32 800)
+; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 8 [[TMP2]], ptr align 8 @__msan_va_arg_tls, i32 ...
[truncated]
|
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With more understanding of PowerPC32 ABI we've rewritten the
VarArgPowerPC32Helper.New implementation fills shadow for both
reg_save_areaandoverflow_arg_area.It does not copy shadow for floating-point arguments, as they are stored in a separate space.
This implementation does not fully support passing arguments
byVal. This will be fixed in future PRs.Tests were also updated via
llvm/utils/update_test_checks.py.@vitalybuka @EugeneZelenko please review