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[llvm-mca] Simplify code in class Scheduler. NFCI
llvm-svn: 347985
1 parent 5ac37f4 commit d20cdcc

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4 files changed

+18
-18
lines changed

4 files changed

+18
-18
lines changed

llvm/tools/llvm-mca/include/HardwareUnits/LSUnit.h

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@ namespace llvm {
2424
namespace mca {
2525

2626
class InstRef;
27+
class Scheduler;
2728

2829
/// A Load/Store Unit implementing a load and store queues.
2930
///
@@ -110,7 +111,7 @@ class LSUnit : public HardwareUnit {
110111
//
111112
// This class doesn't know about the latency of a load instruction. So, it
112113
// conservatively/pessimistically assumes that the latency of a load opcode
113-
// matches the instruction latency.
114+
// matches the instruction latency.
114115
//
115116
// FIXME: In the absence of cache misses (i.e. L1I/L1D/iTLB/dTLB hits/misses),
116117
// and load/store conflicts, the latency of a load is determined by the depth
@@ -195,7 +196,7 @@ class LSUnit : public HardwareUnit {
195196
// becomes available to the users. At that point, the load no longer needs to
196197
// be tracked by the load queue.
197198
// FIXME: For simplicity, we optimistically assume a similar behavior for
198-
// store instructions. In practice, store operation don't tend to leave the
199+
// store instructions. In practice, store operations don't tend to leave the
199200
// store queue until they reach the 'Retired' stage (See PR39830).
200201
void onInstructionExecuted(const InstRef &IR);
201202
};

llvm/tools/llvm-mca/include/HardwareUnits/Scheduler.h

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -85,7 +85,7 @@ class DefaultSchedulerStrategy : public SchedulerStrategy {
8585
/// transition (i.e. from state IS_READY, to state IS_EXECUTING). An Instruction
8686
/// leaves the IssuedSet when it reaches the write-back stage.
8787
class Scheduler : public HardwareUnit {
88-
LSUnit *LSU;
88+
LSUnit &LSU;
8989

9090
// Instruction selection strategy for this Scheduler.
9191
std::unique_ptr<SchedulerStrategy> Strategy;
@@ -117,16 +117,15 @@ class Scheduler : public HardwareUnit {
117117
void promoteToReadySet(SmallVectorImpl<InstRef> &Ready);
118118

119119
public:
120-
Scheduler(const MCSchedModel &Model, LSUnit *Lsu)
121-
: LSU(Lsu), Resources(make_unique<ResourceManager>(Model)) {
122-
initializeStrategy(nullptr);
123-
}
124-
Scheduler(const MCSchedModel &Model, LSUnit *Lsu,
120+
Scheduler(const MCSchedModel &Model, LSUnit &Lsu)
121+
: Scheduler(Model, Lsu, nullptr) {}
122+
123+
Scheduler(const MCSchedModel &Model, LSUnit &Lsu,
125124
std::unique_ptr<SchedulerStrategy> SelectStrategy)
126-
: LSU(Lsu), Resources(make_unique<ResourceManager>(Model)) {
127-
initializeStrategy(std::move(SelectStrategy));
128-
}
129-
Scheduler(std::unique_ptr<ResourceManager> RM, LSUnit *Lsu,
125+
: Scheduler(make_unique<ResourceManager>(Model), Lsu,
126+
std::move(SelectStrategy)) {}
127+
128+
Scheduler(std::unique_ptr<ResourceManager> RM, LSUnit &Lsu,
130129
std::unique_ptr<SchedulerStrategy> SelectStrategy)
131130
: LSU(Lsu), Resources(std::move(RM)) {
132131
initializeStrategy(std::move(SelectStrategy));

llvm/tools/llvm-mca/lib/Context.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ Context::createDefaultPipeline(const PipelineOptions &Opts, InstrBuilder &IB,
3737
auto PRF = llvm::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
3838
auto LSU = llvm::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
3939
Opts.StoreQueueSize, Opts.AssumeNoAlias);
40-
auto HWS = llvm::make_unique<Scheduler>(SM, LSU.get());
40+
auto HWS = llvm::make_unique<Scheduler>(SM, *LSU);
4141

4242
// Create the pipeline stages.
4343
auto Fetch = llvm::make_unique<EntryStage>(SrcMgr);

llvm/tools/llvm-mca/lib/HardwareUnits/Scheduler.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ Scheduler::Status Scheduler::isAvailable(const InstRef &IR) const {
5151
}
5252

5353
// Give lower priority to LSUnit stall events.
54-
switch (LSU->isAvailable(IR)) {
54+
switch (LSU.isAvailable(IR)) {
5555
case LSUnit::LSU_LQUEUE_FULL:
5656
return Scheduler::SC_LOAD_QUEUE_FULL;
5757
case LSUnit::LSU_SQUEUE_FULL:
@@ -80,7 +80,7 @@ void Scheduler::issueInstructionImpl(
8080
if (IS->isExecuting())
8181
IssuedSet.emplace_back(IR);
8282
else if (IS->isExecuted())
83-
LSU->onInstructionExecuted(IR);
83+
LSU.onInstructionExecuted(IR);
8484
}
8585

8686
// Release the buffered resources and issue the instruction.
@@ -170,7 +170,7 @@ void Scheduler::updateIssuedSet(SmallVectorImpl<InstRef> &Executed) {
170170
}
171171

172172
// Instruction IR has completed execution.
173-
LSU->onInstructionExecuted(IR);
173+
LSU.onInstructionExecuted(IR);
174174
Executed.emplace_back(IR);
175175
++RemovedElements;
176176
IR.invalidate();
@@ -213,7 +213,7 @@ void Scheduler::dispatch(const InstRef &IR) {
213213
// If necessary, reserve queue entries in the load-store unit (LSU).
214214
bool IsMemOp = Desc.MayLoad || Desc.MayStore;
215215
if (IsMemOp)
216-
LSU->dispatch(IR);
216+
LSU.dispatch(IR);
217217

218218
if (!isReady(IR)) {
219219
LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding #" << IR << " to the WaitSet\n");
@@ -238,7 +238,7 @@ void Scheduler::dispatch(const InstRef &IR) {
238238
bool Scheduler::isReady(const InstRef &IR) const {
239239
const InstrDesc &Desc = IR.getInstruction()->getDesc();
240240
bool IsMemOp = Desc.MayLoad || Desc.MayStore;
241-
return IR.getInstruction()->isReady() && (!IsMemOp || LSU->isReady(IR));
241+
return IR.getInstruction()->isReady() && (!IsMemOp || LSU.isReady(IR));
242242
}
243243

244244
} // namespace mca

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