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[Subtarget] Merge ProcSched and ProcDesc arrays in MCSubtargetInfo into a single array.
These arrays are both keyed by CPU name and go into the same tablegenerated file. Merge them so we only need to store keys once. This also removes a weird space saving quirk where we used the ProcDesc.size() to create to build an ArrayRef for ProcSched. Differential Revision: https://reviews.llvm.org/D58939 llvm-svn: 355431
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6 files changed

+23
-78
lines changed

6 files changed

+23
-78
lines changed

llvm/include/llvm/CodeGen/TargetSubtargetInfo.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,6 @@ class TargetSubtargetInfo : public MCSubtargetInfo {
6464
TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
6565
ArrayRef<SubtargetFeatureKV> PF,
6666
ArrayRef<SubtargetSubTypeKV> PD,
67-
const SubtargetInfoKV *ProcSched,
6867
const MCWriteProcResEntry *WPR,
6968
const MCWriteLatencyEntry *WL,
7069
const MCReadAdvanceEntry *RA, const InstrStage *IS,

llvm/include/llvm/MC/MCSubtargetInfo.h

Lines changed: 1 addition & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,7 @@ struct SubtargetFeatureKV {
5454
struct SubtargetSubTypeKV {
5555
const char *Key; ///< K-V key string
5656
FeatureBitArray Implies; ///< K-V bit mask
57+
const MCSchedModel *SchedModel;
5758

5859
/// Compare routine for std::lower_bound
5960
bool operator<(StringRef S) const {
@@ -66,24 +67,6 @@ struct SubtargetSubTypeKV {
6667
}
6768
};
6869

69-
//===----------------------------------------------------------------------===//
70-
71-
/// Used to provide key value pairs for CPU and arbitrary pointers.
72-
struct SubtargetInfoKV {
73-
const char *Key; ///< K-V key string
74-
const void *Value; ///< K-V pointer value
75-
76-
/// Compare routine for std::lower_bound
77-
bool operator<(StringRef S) const {
78-
return StringRef(Key) < S;
79-
}
80-
81-
/// Compare routine for std::is_sorted.
82-
bool operator<(const SubtargetInfoKV &Other) const {
83-
return StringRef(Key) < StringRef(Other.Key);
84-
}
85-
};
86-
8770
//===----------------------------------------------------------------------===//
8871
///
8972
/// Generic base class for all target subtargets.
@@ -95,7 +78,6 @@ class MCSubtargetInfo {
9578
ArrayRef<SubtargetSubTypeKV> ProcDesc; // Processor descriptions
9679

9780
// Scheduler machine model
98-
const SubtargetInfoKV *ProcSchedModels;
9981
const MCWriteProcResEntry *WriteProcResTable;
10082
const MCWriteLatencyEntry *WriteLatencyTable;
10183
const MCReadAdvanceEntry *ReadAdvanceTable;
@@ -111,7 +93,6 @@ class MCSubtargetInfo {
11193
MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
11294
ArrayRef<SubtargetFeatureKV> PF,
11395
ArrayRef<SubtargetSubTypeKV> PD,
114-
const SubtargetInfoKV *ProcSched,
11596
const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
11697
const MCReadAdvanceEntry *RA, const InstrStage *IS,
11798
const unsigned *OC, const unsigned *FP);

llvm/lib/CodeGen/TargetSubtargetInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -17,10 +17,10 @@ using namespace llvm;
1717
TargetSubtargetInfo::TargetSubtargetInfo(
1818
const Triple &TT, StringRef CPU, StringRef FS,
1919
ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetSubTypeKV> PD,
20-
const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
20+
const MCWriteProcResEntry *WPR,
2121
const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
2222
const InstrStage *IS, const unsigned *OC, const unsigned *FP)
23-
: MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
23+
: MCSubtargetInfo(TT, CPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) {
2424
}
2525

2626
TargetSubtargetInfo::~TargetSubtargetInfo() = default;

llvm/lib/MC/MCSubtargetInfo.cpp

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -176,11 +176,11 @@ void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef FS) {
176176
MCSubtargetInfo::MCSubtargetInfo(
177177
const Triple &TT, StringRef C, StringRef FS,
178178
ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetSubTypeKV> PD,
179-
const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
179+
const MCWriteProcResEntry *WPR,
180180
const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
181181
const InstrStage *IS, const unsigned *OC, const unsigned *FP)
182182
: TargetTriple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD),
183-
ProcSchedModels(ProcSched), WriteProcResTable(WPR), WriteLatencyTable(WL),
183+
WriteProcResTable(WPR), WriteLatencyTable(WL),
184184
ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
185185
InitMCProcessorInfo(CPU, FS);
186186
}
@@ -238,25 +238,21 @@ bool MCSubtargetInfo::checkFeatures(StringRef FS) const {
238238
}
239239

240240
const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
241-
assert(ProcSchedModels && "Processor machine model not available!");
242-
243-
ArrayRef<SubtargetInfoKV> SchedModels(ProcSchedModels, ProcDesc.size());
244-
245-
assert(std::is_sorted(SchedModels.begin(), SchedModels.end()) &&
241+
assert(std::is_sorted(ProcDesc.begin(), ProcDesc.end()) &&
246242
"Processor machine model table is not sorted");
247243

248244
// Find entry
249-
auto Found =
250-
std::lower_bound(SchedModels.begin(), SchedModels.end(), CPU);
251-
if (Found == SchedModels.end() || StringRef(Found->Key) != CPU) {
245+
const SubtargetSubTypeKV *CPUEntry = Find(CPU, ProcDesc);
246+
247+
if (!CPUEntry) {
252248
if (CPU != "help") // Don't error if the user asked for help.
253249
errs() << "'" << CPU
254250
<< "' is not a recognized processor for this target"
255251
<< " (ignoring processor)\n";
256252
return MCSchedModel::GetDefaultSchedModel();
257253
}
258-
assert(Found->Value && "Missing processor SchedModel value");
259-
return *(const MCSchedModel *)Found->Value;
254+
assert(CPUEntry->SchedModel && "Missing processor SchedModel value");
255+
return *CPUEntry->SchedModel;
260256
}
261257

262258
InstrItineraryData

llvm/unittests/CodeGen/MachineInstrTest.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ class BogusSubtarget : public TargetSubtargetInfo {
4747
public:
4848
BogusSubtarget(TargetMachine &TM)
4949
: TargetSubtargetInfo(Triple(""), "", "", {}, {}, nullptr, nullptr,
50-
nullptr, nullptr, nullptr, nullptr, nullptr),
50+
nullptr, nullptr, nullptr, nullptr),
5151
FL(), TL(TM) {}
5252
~BogusSubtarget() override {}
5353

llvm/utils/TableGen/SubtargetEmitter.cpp

Lines changed: 11 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -271,8 +271,10 @@ SubtargetEmitter::CPUKeyValues(raw_ostream &OS,
271271

272272
printFeatureMask(OS, FeatureList, FeatureMap);
273273

274-
// The {{}} is for the "implies" section of this data structure.
275-
OS << " },\n";
274+
// Emit the scheduler model pointer.
275+
const std::string &ProcModelName =
276+
SchedModels.getModelForProc(Processor).ModelName;
277+
OS << ", &" << ProcModelName << " },\n";
276278
}
277279

278280
// End processor table
@@ -1386,33 +1388,6 @@ void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) {
13861388
}
13871389
}
13881390

1389-
//
1390-
// EmitProcessorLookup - generate cpu name to sched model lookup tables.
1391-
//
1392-
void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) {
1393-
// Gather and sort processor information
1394-
std::vector<Record*> ProcessorList =
1395-
Records.getAllDerivedDefinitions("Processor");
1396-
llvm::sort(ProcessorList, LessRecordFieldName());
1397-
1398-
// Begin processor->sched model table
1399-
OS << "\n";
1400-
OS << "// Sorted (by key) array of sched model for CPU subtype.\n"
1401-
<< "extern const llvm::SubtargetInfoKV " << Target
1402-
<< "ProcSchedKV[] = {\n";
1403-
// For each processor
1404-
for (Record *Processor : ProcessorList) {
1405-
StringRef Name = Processor->getValueAsString("Name");
1406-
const std::string &ProcModelName =
1407-
SchedModels.getModelForProc(Processor).ModelName;
1408-
1409-
// Emit as { "cpu", procinit },
1410-
OS << " { \"" << Name << "\", (const void *)&" << ProcModelName << " },\n";
1411-
}
1412-
// End processor->sched model table
1413-
OS << "};\n";
1414-
}
1415-
14161391
//
14171392
// EmitSchedModel - Emits all scheduling model tables, folding common patterns.
14181393
//
@@ -1441,12 +1416,10 @@ void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) {
14411416
}
14421417
EmitSchedClassTables(SchedTables, OS);
14431418

1419+
OS << "\n#undef DBGFIELD\n";
1420+
14441421
// Emit the processor machine model
14451422
EmitProcessorModels(OS);
1446-
// Emit the processor lookup data
1447-
EmitProcessorLookup(OS);
1448-
1449-
OS << "\n#undef DBGFIELD";
14501423
}
14511424

14521425
static void emitPredicateProlog(const RecordKeeper &Records, raw_ostream &OS) {
@@ -1759,12 +1732,11 @@ void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) {
17591732
OS << " " << Target << "GenMCSubtargetInfo(const Triple &TT, \n"
17601733
<< " StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,\n"
17611734
<< " ArrayRef<SubtargetSubTypeKV> PD,\n"
1762-
<< " const SubtargetInfoKV *ProcSched,\n"
17631735
<< " const MCWriteProcResEntry *WPR,\n"
17641736
<< " const MCWriteLatencyEntry *WL,\n"
17651737
<< " const MCReadAdvanceEntry *RA, const InstrStage *IS,\n"
17661738
<< " const unsigned *OC, const unsigned *FP) :\n"
1767-
<< " MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched,\n"
1739+
<< " MCSubtargetInfo(TT, CPU, FS, PF, PD,\n"
17681740
<< " WPR, WL, RA, IS, OC, FP) { }\n\n"
17691741
<< " unsigned resolveVariantSchedClass(unsigned SchedClass,\n"
17701742
<< " const MCInst *MI, unsigned CPUID) const override {\n"
@@ -1824,10 +1796,10 @@ void SubtargetEmitter::run(raw_ostream &OS) {
18241796
#endif
18251797
unsigned NumFeatures = FeatureKeyValues(OS, FeatureMap);
18261798
OS << "\n";
1827-
unsigned NumProcs = CPUKeyValues(OS, FeatureMap);
1828-
OS << "\n";
18291799
EmitSchedModel(OS);
18301800
OS << "\n";
1801+
unsigned NumProcs = CPUKeyValues(OS, FeatureMap);
1802+
OS << "\n";
18311803
#if 0
18321804
OS << "} // end anonymous namespace\n\n";
18331805
#endif
@@ -1848,8 +1820,7 @@ void SubtargetEmitter::run(raw_ostream &OS) {
18481820
else
18491821
OS << "None, ";
18501822
OS << '\n'; OS.indent(22);
1851-
OS << Target << "ProcSchedKV, "
1852-
<< Target << "WriteProcResTable, "
1823+
OS << Target << "WriteProcResTable, "
18531824
<< Target << "WriteLatencyTable, "
18541825
<< Target << "ReadAdvanceTable, ";
18551826
OS << '\n'; OS.indent(22);
@@ -1916,7 +1887,6 @@ void SubtargetEmitter::run(raw_ostream &OS) {
19161887
OS << "namespace llvm {\n";
19171888
OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n";
19181889
OS << "extern const llvm::SubtargetSubTypeKV " << Target << "SubTypeKV[];\n";
1919-
OS << "extern const llvm::SubtargetInfoKV " << Target << "ProcSchedKV[];\n";
19201890
OS << "extern const llvm::MCWriteProcResEntry "
19211891
<< Target << "WriteProcResTable[];\n";
19221892
OS << "extern const llvm::MCWriteLatencyEntry "
@@ -1942,8 +1912,7 @@ void SubtargetEmitter::run(raw_ostream &OS) {
19421912
else
19431913
OS << "None, ";
19441914
OS << '\n'; OS.indent(24);
1945-
OS << Target << "ProcSchedKV, "
1946-
<< Target << "WriteProcResTable, "
1915+
OS << Target << "WriteProcResTable, "
19471916
<< Target << "WriteLatencyTable, "
19481917
<< Target << "ReadAdvanceTable, ";
19491918
OS << '\n'; OS.indent(24);

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