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[X86] In matchBitExtract, place all of the new nodes before Node's position in the DAG for the topological sort.
We were using OrigNBits, but that put all the nodes before the node we used to start the control computation. This caused some node earlier than the sequence we inserted to be selected before the sequence we created. We want our new sequence to be selected first since it depends on OrigNBits. I don't have a test case. Found by reviewing the code. llvm-svn: 356979
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llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -3008,30 +3008,29 @@ bool X86DAGToDAGISel::matchBitExtract(SDNode *Node) {
30083008
assert(XVT == MVT::i64 && "Expected truncation from i64");
30093009
}
30103010

3011-
SDValue OrigNBits = NBits;
30123011
// Truncate the shift amount.
30133012
NBits = CurDAG->getNode(ISD::TRUNCATE, DL, MVT::i8, NBits);
3014-
insertDAGNode(*CurDAG, OrigNBits, NBits);
3013+
insertDAGNode(*CurDAG, SDValue(Node, 0), NBits);
30153014

30163015
// Insert 8-bit NBits into lowest 8 bits of 32-bit register.
30173016
// All the other bits are undefined, we do not care about them.
30183017
SDValue ImplDef = SDValue(
30193018
CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::i32), 0);
3020-
insertDAGNode(*CurDAG, OrigNBits, ImplDef);
3019+
insertDAGNode(*CurDAG, SDValue(Node, 0), ImplDef);
30213020
NBits = CurDAG->getTargetInsertSubreg(X86::sub_8bit, DL, MVT::i32, ImplDef,
30223021
NBits);
3023-
insertDAGNode(*CurDAG, OrigNBits, NBits);
3022+
insertDAGNode(*CurDAG, SDValue(Node, 0), NBits);
30243023

30253024
if (Subtarget->hasBMI2()) {
30263025
// Great, just emit the the BZHI..
30273026
if (XVT != MVT::i32) {
30283027
// But have to place the bit count into the wide-enough register first.
30293028
SDValue ImplDef = SDValue(
30303029
CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, XVT), 0);
3031-
insertDAGNode(*CurDAG, OrigNBits, ImplDef);
3030+
insertDAGNode(*CurDAG, SDValue(Node, 0), ImplDef);
30323031
NBits = CurDAG->getTargetInsertSubreg(X86::sub_32bit, DL, XVT, ImplDef,
30333032
NBits);
3034-
insertDAGNode(*CurDAG, OrigNBits, NBits);
3033+
insertDAGNode(*CurDAG, SDValue(Node, 0), NBits);
30353034
}
30363035

30373036
SDValue Extract = CurDAG->getNode(X86ISD::BZHI, DL, XVT, X, NBits);
@@ -3050,7 +3049,7 @@ bool X86DAGToDAGISel::matchBitExtract(SDNode *Node) {
30503049
// This makes the low 8 bits to be zero.
30513050
SDValue C8 = CurDAG->getConstant(8, DL, MVT::i8);
30523051
SDValue Control = CurDAG->getNode(ISD::SHL, DL, MVT::i32, NBits, C8);
3053-
insertDAGNode(*CurDAG, OrigNBits, Control);
3052+
insertDAGNode(*CurDAG, SDValue(Node, 0), Control);
30543053

30553054
// If the 'X' is *logically* shifted, we can fold that shift into 'control'.
30563055
if (X.getOpcode() == ISD::SRL) {
@@ -3068,17 +3067,17 @@ bool X86DAGToDAGISel::matchBitExtract(SDNode *Node) {
30683067

30693068
// And now 'or' these low 8 bits of shift amount into the 'control'.
30703069
Control = CurDAG->getNode(ISD::OR, DL, MVT::i32, Control, ShiftAmt);
3071-
insertDAGNode(*CurDAG, OrigNBits, Control);
3070+
insertDAGNode(*CurDAG, SDValue(Node, 0), Control);
30723071
}
30733072

30743073
// But have to place the 'control' into the wide-enough register first.
30753074
if (XVT != MVT::i32) {
30763075
SDValue ImplDef =
30773076
SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, XVT), 0);
3078-
insertDAGNode(*CurDAG, OrigNBits, ImplDef);
3077+
insertDAGNode(*CurDAG, SDValue(Node, 0), ImplDef);
30793078
Control = CurDAG->getTargetInsertSubreg(X86::sub_32bit, DL, XVT, ImplDef,
30803079
Control);
3081-
insertDAGNode(*CurDAG, OrigNBits, Control);
3080+
insertDAGNode(*CurDAG, SDValue(Node, 0), Control);
30823081
}
30833082

30843083
// And finally, form the BEXTR itself.

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