@@ -3008,30 +3008,29 @@ bool X86DAGToDAGISel::matchBitExtract(SDNode *Node) {
3008
3008
assert (XVT == MVT::i64 && " Expected truncation from i64" );
3009
3009
}
3010
3010
3011
- SDValue OrigNBits = NBits;
3012
3011
// Truncate the shift amount.
3013
3012
NBits = CurDAG->getNode (ISD::TRUNCATE, DL, MVT::i8 , NBits);
3014
- insertDAGNode (*CurDAG, OrigNBits , NBits);
3013
+ insertDAGNode (*CurDAG, SDValue (Node, 0 ) , NBits);
3015
3014
3016
3015
// Insert 8-bit NBits into lowest 8 bits of 32-bit register.
3017
3016
// All the other bits are undefined, we do not care about them.
3018
3017
SDValue ImplDef = SDValue (
3019
3018
CurDAG->getMachineNode (TargetOpcode::IMPLICIT_DEF, DL, MVT::i32 ), 0 );
3020
- insertDAGNode (*CurDAG, OrigNBits , ImplDef);
3019
+ insertDAGNode (*CurDAG, SDValue (Node, 0 ) , ImplDef);
3021
3020
NBits = CurDAG->getTargetInsertSubreg (X86::sub_8bit, DL, MVT::i32 , ImplDef,
3022
3021
NBits);
3023
- insertDAGNode (*CurDAG, OrigNBits , NBits);
3022
+ insertDAGNode (*CurDAG, SDValue (Node, 0 ) , NBits);
3024
3023
3025
3024
if (Subtarget->hasBMI2 ()) {
3026
3025
// Great, just emit the the BZHI..
3027
3026
if (XVT != MVT::i32 ) {
3028
3027
// But have to place the bit count into the wide-enough register first.
3029
3028
SDValue ImplDef = SDValue (
3030
3029
CurDAG->getMachineNode (TargetOpcode::IMPLICIT_DEF, DL, XVT), 0 );
3031
- insertDAGNode (*CurDAG, OrigNBits , ImplDef);
3030
+ insertDAGNode (*CurDAG, SDValue (Node, 0 ) , ImplDef);
3032
3031
NBits = CurDAG->getTargetInsertSubreg (X86::sub_32bit, DL, XVT, ImplDef,
3033
3032
NBits);
3034
- insertDAGNode (*CurDAG, OrigNBits , NBits);
3033
+ insertDAGNode (*CurDAG, SDValue (Node, 0 ) , NBits);
3035
3034
}
3036
3035
3037
3036
SDValue Extract = CurDAG->getNode (X86ISD::BZHI, DL, XVT, X, NBits);
@@ -3050,7 +3049,7 @@ bool X86DAGToDAGISel::matchBitExtract(SDNode *Node) {
3050
3049
// This makes the low 8 bits to be zero.
3051
3050
SDValue C8 = CurDAG->getConstant (8 , DL, MVT::i8 );
3052
3051
SDValue Control = CurDAG->getNode (ISD::SHL, DL, MVT::i32 , NBits, C8);
3053
- insertDAGNode (*CurDAG, OrigNBits , Control);
3052
+ insertDAGNode (*CurDAG, SDValue (Node, 0 ) , Control);
3054
3053
3055
3054
// If the 'X' is *logically* shifted, we can fold that shift into 'control'.
3056
3055
if (X.getOpcode () == ISD::SRL) {
@@ -3068,17 +3067,17 @@ bool X86DAGToDAGISel::matchBitExtract(SDNode *Node) {
3068
3067
3069
3068
// And now 'or' these low 8 bits of shift amount into the 'control'.
3070
3069
Control = CurDAG->getNode (ISD::OR, DL, MVT::i32 , Control, ShiftAmt);
3071
- insertDAGNode (*CurDAG, OrigNBits , Control);
3070
+ insertDAGNode (*CurDAG, SDValue (Node, 0 ) , Control);
3072
3071
}
3073
3072
3074
3073
// But have to place the 'control' into the wide-enough register first.
3075
3074
if (XVT != MVT::i32 ) {
3076
3075
SDValue ImplDef =
3077
3076
SDValue (CurDAG->getMachineNode (TargetOpcode::IMPLICIT_DEF, DL, XVT), 0 );
3078
- insertDAGNode (*CurDAG, OrigNBits , ImplDef);
3077
+ insertDAGNode (*CurDAG, SDValue (Node, 0 ) , ImplDef);
3079
3078
Control = CurDAG->getTargetInsertSubreg (X86::sub_32bit, DL, XVT, ImplDef,
3080
3079
Control);
3081
- insertDAGNode (*CurDAG, OrigNBits , Control);
3080
+ insertDAGNode (*CurDAG, SDValue (Node, 0 ) , Control);
3082
3081
}
3083
3082
3084
3083
// And finally, form the BEXTR itself.
0 commit comments