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AMDGPU/GlobalISel: Fix non-power-of-2 select
llvm-svn: 357762
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llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

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@@ -486,6 +486,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
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.clampMaxNumElements(0, LocalPtr, 2)
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.clampMaxNumElements(0, PrivatePtr, 2)
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.scalarize(0)
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.widenScalarToNextPow2(0)
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.legalIf(all(isPointer(0), typeIs(1, S1)));
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// TODO: Only the low 4/5/6 bits of the shift amount are observed, so we can

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir

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@@ -49,6 +49,34 @@ body: |
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...
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---
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name: test_select_s48
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: test_select_s48
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
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; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
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; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C1]](s64)
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; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[C2]](s64)
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; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
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; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[SELECT]](s64)
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; CHECK: $vgpr0_vgpr1 = COPY [[COPY3]](s64)
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%0:_(s32) = G_CONSTANT i32 0
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%1:_(s32) = COPY $vgpr0
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%2:_(s1) = G_ICMP intpred(ne), %0, %1
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%3:_(s48) = G_CONSTANT i48 1
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%4:_(s48) = G_CONSTANT i48 2
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%5:_(s48) = G_SELECT %2, %3, %4
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%6:_(s64) = G_ANYEXT %5
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$vgpr0_vgpr1 = COPY %6
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...
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---
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name: test_select_s16
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body: |

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