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GlobalISel: Implement fewerElementsVector for phi
llvm-svn: 355048
1 parent 72bcf15 commit d3093c2

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5 files changed

+386
-9
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5 files changed

+386
-9
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -186,6 +186,9 @@ class LegalizerHelper {
186186
LegalizeResult
187187
fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
188188

189+
LegalizeResult fewerElementsVectorPhi(MachineInstr &MI,
190+
unsigned TypeIdx, LLT NarrowTy);
191+
189192
LegalizeResult moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
190193
LLT MoreTy);
191194

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 85 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -34,8 +34,10 @@ using namespace LegalizeActions;
3434
/// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
3535
/// with any leftover piece as type \p LeftoverTy
3636
///
37-
/// Returns -1 if the breakdown is not satisfiable.
38-
static int getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
37+
/// Returns -1 in the first element of the pair if the breakdown is not
38+
/// satisfiable.
39+
static std::pair<int, int>
40+
getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
3941
assert(!LeftoverTy.isValid() && "this is an out argument");
4042

4143
unsigned Size = OrigTy.getSizeInBits();
@@ -45,18 +47,19 @@ static int getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
4547
assert(Size > NarrowSize);
4648

4749
if (LeftoverSize == 0)
48-
return NumParts;
50+
return {NumParts, 0};
4951

5052
if (NarrowTy.isVector()) {
5153
unsigned EltSize = OrigTy.getScalarSizeInBits();
5254
if (LeftoverSize % EltSize != 0)
53-
return -1;
55+
return {-1, -1};
5456
LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
5557
} else {
5658
LeftoverTy = LLT::scalar(LeftoverSize);
5759
}
5860

59-
return NumParts;
61+
int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits();
62+
return std::make_pair(NumParts, NumLeftover);
6063
}
6164

6265
LegalizerHelper::LegalizerHelper(MachineFunction &MF,
@@ -1759,10 +1762,12 @@ LegalizerHelper::fewerElementsVectorMultiEltType(
17591762
LLT DstTy = MRI.getType(DstReg);
17601763
LLT LeftoverTy0;
17611764

1765+
int NumParts, NumLeftover;
17621766
// All of the operands need to have the same number of elements, so if we can
17631767
// determine a type breakdown for the result type, we can for all of the
17641768
// source types.
1765-
int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0);
1769+
std::tie(NumParts, NumLeftover)
1770+
= getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0);
17661771
if (NumParts < 0)
17671772
return UnableToLegalize;
17681773

@@ -2017,6 +2022,73 @@ LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx,
20172022
return Legalized;
20182023
}
20192024

2025+
LegalizerHelper::LegalizeResult
2026+
LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2027+
LLT NarrowTy) {
2028+
const unsigned DstReg = MI.getOperand(0).getReg();
2029+
LLT PhiTy = MRI.getType(DstReg);
2030+
LLT LeftoverTy;
2031+
2032+
// All of the operands need to have the same number of elements, so if we can
2033+
// determine a type breakdown for the result type, we can for all of the
2034+
// source types.
2035+
int NumParts, NumLeftover;
2036+
std::tie(NumParts, NumLeftover)
2037+
= getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy);
2038+
if (NumParts < 0)
2039+
return UnableToLegalize;
2040+
2041+
SmallVector<unsigned, 4> DstRegs, LeftoverDstRegs;
2042+
SmallVector<MachineInstrBuilder, 4> NewInsts;
2043+
2044+
const int TotalNumParts = NumParts + NumLeftover;
2045+
2046+
// Insert the new phis in the result block first.
2047+
for (int I = 0; I != TotalNumParts; ++I) {
2048+
LLT Ty = I < NumParts ? NarrowTy : LeftoverTy;
2049+
unsigned PartDstReg = MRI.createGenericVirtualRegister(Ty);
2050+
NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI)
2051+
.addDef(PartDstReg));
2052+
if (I < NumParts)
2053+
DstRegs.push_back(PartDstReg);
2054+
else
2055+
LeftoverDstRegs.push_back(PartDstReg);
2056+
}
2057+
2058+
MachineBasicBlock *MBB = MI.getParent();
2059+
MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI());
2060+
insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs);
2061+
2062+
SmallVector<unsigned, 4> PartRegs, LeftoverRegs;
2063+
2064+
// Insert code to extract the incoming values in each predecessor block.
2065+
for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2066+
PartRegs.clear();
2067+
LeftoverRegs.clear();
2068+
2069+
unsigned SrcReg = MI.getOperand(I).getReg();
2070+
MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2071+
MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2072+
2073+
LLT Unused;
2074+
if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs,
2075+
LeftoverRegs))
2076+
return UnableToLegalize;
2077+
2078+
// Add the newly created operand splits to the existing instructions. The
2079+
// odd-sized pieces are ordered after the requested NarrowTyArg sized
2080+
// pieces.
2081+
for (int J = 0; J != TotalNumParts; ++J) {
2082+
MachineInstrBuilder MIB = NewInsts[J];
2083+
MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]);
2084+
MIB.addMBB(&OpMBB);
2085+
}
2086+
}
2087+
2088+
MI.eraseFromParent();
2089+
return Legalized;
2090+
}
2091+
20202092
LegalizerHelper::LegalizeResult
20212093
LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx,
20222094
LLT NarrowTy) {
@@ -2038,14 +2110,17 @@ LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx,
20382110
LLT ValTy = MRI.getType(ValReg);
20392111

20402112
int NumParts = -1;
2113+
int NumLeftover = -1;
20412114
LLT LeftoverTy;
20422115
SmallVector<unsigned, 8> NarrowRegs, NarrowLeftoverRegs;
20432116
if (IsLoad) {
2044-
NumParts = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy);
2117+
std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy);
20452118
} else {
20462119
if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs,
2047-
NarrowLeftoverRegs))
2120+
NarrowLeftoverRegs)) {
20482121
NumParts = NarrowRegs.size();
2122+
NumLeftover = NarrowLeftoverRegs.size();
2123+
}
20492124
}
20502125

20512126
if (NumParts == -1)
@@ -2169,6 +2244,8 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
21692244
return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy);
21702245
case G_SELECT:
21712246
return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy);
2247+
case G_PHI:
2248+
return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy);
21722249
case G_LOAD:
21732250
case G_STORE:
21742251
return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -159,6 +159,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
159159
.legalFor(AddrSpaces32)
160160
.clampScalar(0, S32, S256)
161161
.widenScalarToNextPow2(0, 32)
162+
.clampMaxNumElements(0, S32, 16)
162163
.moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
163164
.legalIf(isPointer(0));
164165

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir

Lines changed: 203 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s
2+
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck %s
33

44
---
55
name: test_phi_s32
@@ -391,6 +391,208 @@ body: |
391391
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %5
392392
S_SETPC_B64 undef $sgpr30_sgpr31
393393
394+
...
395+
---
396+
name: test_phi_v8s32
397+
tracksRegLiveness: true
398+
399+
body: |
400+
; CHECK-LABEL: name: test_phi_v8s32
401+
; CHECK: bb.0:
402+
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
403+
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8
404+
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
405+
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr8
406+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
407+
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
408+
; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
409+
; CHECK: G_BR %bb.2
410+
; CHECK: bb.1:
411+
; CHECK: successors: %bb.2(0x80000000)
412+
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<8 x s32>)
413+
; CHECK: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<8 x s32>)
414+
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV]], [[UV8]]
415+
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[UV9]]
416+
; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[UV2]], [[UV10]]
417+
; CHECK: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UV3]], [[UV11]]
418+
; CHECK: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[UV4]], [[UV12]]
419+
; CHECK: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[UV13]]
420+
; CHECK: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[UV6]], [[UV14]]
421+
; CHECK: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[UV7]], [[UV15]]
422+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32), [[ADD2]](s32), [[ADD3]](s32), [[ADD4]](s32), [[ADD5]](s32), [[ADD6]](s32), [[ADD7]](s32)
423+
; CHECK: G_BR %bb.2
424+
; CHECK: bb.2:
425+
; CHECK: [[PHI:%[0-9]+]]:_(<8 x s32>) = G_PHI [[COPY]](<8 x s32>), %bb.0, [[BUILD_VECTOR]](<8 x s32>), %bb.1
426+
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[PHI]](<8 x s32>)
427+
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
428+
bb.0:
429+
successors: %bb.1, %bb.2
430+
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $vgpr8
431+
432+
%0:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
433+
%1:_(s32) = COPY $vgpr8
434+
%2:_(s32) = G_CONSTANT i32 0
435+
%3:_(s1) = G_ICMP intpred(eq), %1, %2
436+
G_BRCOND %3, %bb.1
437+
G_BR %bb.2
438+
439+
bb.1:
440+
successors: %bb.2
441+
442+
%4:_(<8 x s32>) = G_ADD %0, %0
443+
G_BR %bb.2
444+
445+
bb.2:
446+
%5:_(<8 x s32>) = G_PHI %0, %bb.0, %4, %bb.1
447+
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %5
448+
S_SETPC_B64 undef $sgpr30_sgpr31
449+
450+
...
451+
---
452+
name: test_phi_v16s32
453+
tracksRegLiveness: true
454+
455+
body: |
456+
; CHECK-LABEL: name: test_phi_v16s32
457+
; CHECK: bb.0:
458+
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
459+
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
460+
; CHECK: [[DEF:%[0-9]+]]:_(<16 x s32>) = G_IMPLICIT_DEF
461+
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr4
462+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
463+
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
464+
; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
465+
; CHECK: G_BR %bb.2
466+
; CHECK: bb.1:
467+
; CHECK: successors: %bb.2(0x80000000)
468+
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<16 x s32>)
469+
; CHECK: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<16 x s32>)
470+
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV]], [[UV16]]
471+
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[UV17]]
472+
; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[UV2]], [[UV18]]
473+
; CHECK: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UV3]], [[UV19]]
474+
; CHECK: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[UV4]], [[UV20]]
475+
; CHECK: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[UV21]]
476+
; CHECK: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[UV6]], [[UV22]]
477+
; CHECK: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[UV7]], [[UV23]]
478+
; CHECK: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[UV8]], [[UV24]]
479+
; CHECK: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[UV9]], [[UV25]]
480+
; CHECK: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[UV10]], [[UV26]]
481+
; CHECK: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UV11]], [[UV27]]
482+
; CHECK: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UV12]], [[UV28]]
483+
; CHECK: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[UV13]], [[UV29]]
484+
; CHECK: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[UV14]], [[UV30]]
485+
; CHECK: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UV15]], [[UV31]]
486+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32), [[ADD2]](s32), [[ADD3]](s32), [[ADD4]](s32), [[ADD5]](s32), [[ADD6]](s32), [[ADD7]](s32), [[ADD8]](s32), [[ADD9]](s32), [[ADD10]](s32), [[ADD11]](s32), [[ADD12]](s32), [[ADD13]](s32), [[ADD14]](s32), [[ADD15]](s32)
487+
; CHECK: G_BR %bb.2
488+
; CHECK: bb.2:
489+
; CHECK: [[PHI:%[0-9]+]]:_(<16 x s32>) = G_PHI [[DEF]](<16 x s32>), %bb.0, [[BUILD_VECTOR]](<16 x s32>), %bb.1
490+
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[PHI]](<16 x s32>)
491+
bb.0:
492+
successors: %bb.1, %bb.2
493+
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
494+
495+
%0:_(<16 x s32>) = G_IMPLICIT_DEF
496+
%1:_(s32) = COPY $vgpr4
497+
%2:_(s32) = G_CONSTANT i32 0
498+
%3:_(s1) = G_ICMP intpred(eq), %1, %2
499+
G_BRCOND %3, %bb.1
500+
G_BR %bb.2
501+
502+
bb.1:
503+
successors: %bb.2
504+
505+
%4:_(<16 x s32>) = G_ADD %0, %0
506+
G_BR %bb.2
507+
508+
bb.2:
509+
%5:_(<16 x s32>) = G_PHI %0, %bb.0, %4, %bb.1
510+
S_SETPC_B64 undef $sgpr30_sgpr31, implicit %5
511+
512+
...
513+
514+
---
515+
name: test_phi_v32s32
516+
tracksRegLiveness: true
517+
518+
body: |
519+
; CHECK-LABEL: name: test_phi_v32s32
520+
; CHECK: bb.0:
521+
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
522+
; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
523+
; CHECK: [[DEF:%[0-9]+]]:_(<16 x s32>) = G_IMPLICIT_DEF
524+
; CHECK: [[DEF1:%[0-9]+]]:_(<16 x s32>) = G_IMPLICIT_DEF
525+
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s32>) = G_CONCAT_VECTORS [[DEF]](<16 x s32>), [[DEF1]](<16 x s32>)
526+
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr4
527+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
528+
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
529+
; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
530+
; CHECK: G_BR %bb.2
531+
; CHECK: bb.1:
532+
; CHECK: successors: %bb.2(0x80000000)
533+
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<32 x s32>)
534+
; CHECK: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32), [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32), [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32), [[UV40:%[0-9]+]]:_(s32), [[UV41:%[0-9]+]]:_(s32), [[UV42:%[0-9]+]]:_(s32), [[UV43:%[0-9]+]]:_(s32), [[UV44:%[0-9]+]]:_(s32), [[UV45:%[0-9]+]]:_(s32), [[UV46:%[0-9]+]]:_(s32), [[UV47:%[0-9]+]]:_(s32), [[UV48:%[0-9]+]]:_(s32), [[UV49:%[0-9]+]]:_(s32), [[UV50:%[0-9]+]]:_(s32), [[UV51:%[0-9]+]]:_(s32), [[UV52:%[0-9]+]]:_(s32), [[UV53:%[0-9]+]]:_(s32), [[UV54:%[0-9]+]]:_(s32), [[UV55:%[0-9]+]]:_(s32), [[UV56:%[0-9]+]]:_(s32), [[UV57:%[0-9]+]]:_(s32), [[UV58:%[0-9]+]]:_(s32), [[UV59:%[0-9]+]]:_(s32), [[UV60:%[0-9]+]]:_(s32), [[UV61:%[0-9]+]]:_(s32), [[UV62:%[0-9]+]]:_(s32), [[UV63:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<32 x s32>)
535+
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV]], [[UV32]]
536+
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[UV33]]
537+
; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[UV2]], [[UV34]]
538+
; CHECK: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UV3]], [[UV35]]
539+
; CHECK: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[UV4]], [[UV36]]
540+
; CHECK: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[UV5]], [[UV37]]
541+
; CHECK: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[UV6]], [[UV38]]
542+
; CHECK: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[UV7]], [[UV39]]
543+
; CHECK: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[UV8]], [[UV40]]
544+
; CHECK: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[UV9]], [[UV41]]
545+
; CHECK: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[UV10]], [[UV42]]
546+
; CHECK: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[UV11]], [[UV43]]
547+
; CHECK: [[ADD12:%[0-9]+]]:_(s32) = G_ADD [[UV12]], [[UV44]]
548+
; CHECK: [[ADD13:%[0-9]+]]:_(s32) = G_ADD [[UV13]], [[UV45]]
549+
; CHECK: [[ADD14:%[0-9]+]]:_(s32) = G_ADD [[UV14]], [[UV46]]
550+
; CHECK: [[ADD15:%[0-9]+]]:_(s32) = G_ADD [[UV15]], [[UV47]]
551+
; CHECK: [[ADD16:%[0-9]+]]:_(s32) = G_ADD [[UV16]], [[UV48]]
552+
; CHECK: [[ADD17:%[0-9]+]]:_(s32) = G_ADD [[UV17]], [[UV49]]
553+
; CHECK: [[ADD18:%[0-9]+]]:_(s32) = G_ADD [[UV18]], [[UV50]]
554+
; CHECK: [[ADD19:%[0-9]+]]:_(s32) = G_ADD [[UV19]], [[UV51]]
555+
; CHECK: [[ADD20:%[0-9]+]]:_(s32) = G_ADD [[UV20]], [[UV52]]
556+
; CHECK: [[ADD21:%[0-9]+]]:_(s32) = G_ADD [[UV21]], [[UV53]]
557+
; CHECK: [[ADD22:%[0-9]+]]:_(s32) = G_ADD [[UV22]], [[UV54]]
558+
; CHECK: [[ADD23:%[0-9]+]]:_(s32) = G_ADD [[UV23]], [[UV55]]
559+
; CHECK: [[ADD24:%[0-9]+]]:_(s32) = G_ADD [[UV24]], [[UV56]]
560+
; CHECK: [[ADD25:%[0-9]+]]:_(s32) = G_ADD [[UV25]], [[UV57]]
561+
; CHECK: [[ADD26:%[0-9]+]]:_(s32) = G_ADD [[UV26]], [[UV58]]
562+
; CHECK: [[ADD27:%[0-9]+]]:_(s32) = G_ADD [[UV27]], [[UV59]]
563+
; CHECK: [[ADD28:%[0-9]+]]:_(s32) = G_ADD [[UV28]], [[UV60]]
564+
; CHECK: [[ADD29:%[0-9]+]]:_(s32) = G_ADD [[UV29]], [[UV61]]
565+
; CHECK: [[ADD30:%[0-9]+]]:_(s32) = G_ADD [[UV30]], [[UV62]]
566+
; CHECK: [[ADD31:%[0-9]+]]:_(s32) = G_ADD [[UV31]], [[UV63]]
567+
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32), [[ADD2]](s32), [[ADD3]](s32), [[ADD4]](s32), [[ADD5]](s32), [[ADD6]](s32), [[ADD7]](s32), [[ADD8]](s32), [[ADD9]](s32), [[ADD10]](s32), [[ADD11]](s32), [[ADD12]](s32), [[ADD13]](s32), [[ADD14]](s32), [[ADD15]](s32), [[ADD16]](s32), [[ADD17]](s32), [[ADD18]](s32), [[ADD19]](s32), [[ADD20]](s32), [[ADD21]](s32), [[ADD22]](s32), [[ADD23]](s32), [[ADD24]](s32), [[ADD25]](s32), [[ADD26]](s32), [[ADD27]](s32), [[ADD28]](s32), [[ADD29]](s32), [[ADD30]](s32), [[ADD31]](s32)
568+
; CHECK: [[UV64:%[0-9]+]]:_(<16 x s32>), [[UV65:%[0-9]+]]:_(<16 x s32>) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<32 x s32>)
569+
; CHECK: G_BR %bb.2
570+
; CHECK: bb.2:
571+
; CHECK: [[PHI:%[0-9]+]]:_(<16 x s32>) = G_PHI [[DEF]](<16 x s32>), %bb.0, [[UV64]](<16 x s32>), %bb.1
572+
; CHECK: [[PHI1:%[0-9]+]]:_(<16 x s32>) = G_PHI [[DEF1]](<16 x s32>), %bb.0, [[UV65]](<16 x s32>), %bb.1
573+
; CHECK: [[CONCAT_VECTORS1:%[0-9]+]]:_(<32 x s32>) = G_CONCAT_VECTORS [[PHI]](<16 x s32>), [[PHI1]](<16 x s32>)
574+
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[CONCAT_VECTORS1]](<32 x s32>)
575+
bb.0:
576+
successors: %bb.1, %bb.2
577+
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4
578+
579+
%0:_(<32 x s32>) = G_IMPLICIT_DEF
580+
%1:_(s32) = COPY $vgpr4
581+
%2:_(s32) = G_CONSTANT i32 0
582+
%3:_(s1) = G_ICMP intpred(eq), %1, %2
583+
G_BRCOND %3, %bb.1
584+
G_BR %bb.2
585+
586+
bb.1:
587+
successors: %bb.2
588+
589+
%4:_(<32 x s32>) = G_ADD %0, %0
590+
G_BR %bb.2
591+
592+
bb.2:
593+
%5:_(<32 x s32>) = G_PHI %0, %bb.0, %4, %bb.1
594+
S_SETPC_B64 undef $sgpr30_sgpr31, implicit %5
595+
394596
...
395597
---
396598
name: test_phi_s64

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