rustc_target: RISC-V: add base I-related important extensions

[a4lg]

Of ratified RISC-V features defined, this commit adds extensions satisfying following criteria:

• Formerly a part of the I extension and splitted thereafter (now ratified as I + Zifencei + Zicsr + Zicntr + Zihpm) or
• Dicoverable from newer versions of the Linux kernel and implemented as a part of std_detect's feature (Zihintpause) and
• Available on LLVM 18.

This is based on the latest ratified ISA Manuals (version 20240411).

LLVM Definitions:

• Zifencei
• Zicsr
• Zicntr
• Zihpm
• Zihintpause

Additional (1):
One of those, Zicsr, is a dependency of many other ISA extensions and this commit adds correct dependencies to Zicsr.

Additional (2):
In RISC-V, G is an abbreviation of following extensions:

• I
• M
• A
• F
• D
• Zicsr (although implied by F)
• Zifencei

and all RISC-V targets with the G abbreviation and targets for Android / VxWorks are updated accordingly.

Note:

Android will require RVA22 (likely RVA22U64) and some more extensions, which is a superset of RV64GC. For VxWorks, all BSPs currently distributed by Wind River are for boards with RV64GC (this commit also updates riscv32-wrs-vxworks though).

---

This is the version 4.
Ztso in the original proposal is removed on the PR version 2 due to the minimum LLVM version (non-experimental Ztso requires LLVM 19 while minimum LLVM version of Rust is 18). This is not back in PR version 3 and 4 after noticing adding Ztso is possible by checking host LLVM version because PR version 3 introduces compiler target changes (and adding more extensions would complicate the problems; sorry Zihintpause).

Version 4:

• Fixed some commit messages,
• Added Android / VxWorks targets to imply G and
• Added an implication from Zve32x to Zicsr (which makes all vector extension subsets to imply Zicsr)
  since rustc_target: Add more RISC-V vector-related features and use zvl*b target features in vector ABI check #138742 is now merged.

Related:

• Tracking issue for RFC 2045: improving #[target_feature] #44839
  (riscv_target_feature)
• Tracking Issue for RISC-V Ratified Extensions Intrinsics #114544
  (This PR can be a prerequisite of resolving a part of that tracking issue)
• rustc_target: Add more RISC-V vector-related features and use zvl*b target features in vector ABI check #138742
  (Touches the same place and vector extensions depend on Zicsr)

NOT Related but linked:

• Some -Ctarget-features must be restrained on RISCV #132618
  (This PR won't be blocked by this issue since none of those extensions do not change the ABI)

@rustbot r? @Amanieu
@rustbot label +T-compiler +O-riscv +A-target-feature

[rustbot]

These commits modify compiler targets.
(See the Target Tier Policy.)

[taiki-e]

and all targets with either "riscv32gc" or "riscv64gc" are updated accordingly.

I think the following two that do not include extension names in the target name are also actually riscv64gc.

rust/compiler/rustc_target/src/spec/targets/riscv64_linux_android.rs

Line 22 in 48994b1

features: "+m,+a,+f,+d,+c,+zba,+zbb,+zbs,+v".into(),

rust/compiler/rustc_target/src/spec/targets/riscv64_wrs_vxworks.rs

Line 19 in 48994b1

features: "+m,+a,+f,+d,+c".into(),

[Amanieu]

@a4lg Could you update the 2 targets mentioned by @taiki-e. Then this should be good to merge.

[a4lg]

@taiki-e I wasn't sure whether this is okay as RV64G.
@Amanieu Okay, I'll update that, too.

[a4lg]

Confirmed.
Android will require RVA22 + vector + vector crypto extensions (I could not confirm which vector crypto extensions), which is a superset of RV(32|64)GCV.
I could not confirm minimum requirements of VxWorks but at least all BSPs currently supplied by Wind River are for boards with RV64GC (archive).

[Amanieu]

@bors r+

[bors]

📌 Commit 6f40f0c has been approved by Amanieu

It is now in the queue for this repository.

[a4lg]

Reflected the changes (mainly based on the reviews but with an additional implication that is enabled by now merged #138742) and... thanks for approving!