drivers: intc_wch_pfic: correct/optimize interrupt disable logic #91230
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The IRER registers are write-only and clear the enable bit for the provided interrupt. Use a direct write instead of a read/modify/write sequence to avoid generating a bogus read access and improve performance Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
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nzmichaelh
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Jun 9, 2025
| void arch_irq_disable(unsigned int irq) | ||
| { | ||
| PFIC->IRER[irq / 32] |= 1 << (irq % 32); | ||
| PFIC->IRER[irq / 32] = 1 << (irq % 32); |
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Thanks! While you're here, could you also change this to BIT(irq % 32)
Updated intc_wch_pfic driver to use BIT() macro for clarity. Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
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nzmichaelh
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VynDragon
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The IRER registers are write-only and clear the enable bit for the provided interrupt. Use a direct write instead of a read/modify/write sequence to avoid generating a bogus read access and improve performance