soc: sensry: fix irq enable/disable #91235
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@tswaehn can you comment here? Or maybe share the relevant portion of the reference manual? thanks! |
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To be honest, from documentation point of view - your fix is 100% correct. the registers are both write-only. So the reading before writing is absolutely non-sense. I m running the changes on hardware and update comments here, ... |
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@tswaehn thanks! Let me put this out of draft then, since at least it doesn't look to be complete nonsense :) |
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moreover, the inversion for clear is incorrect and that should also fix with your commit. |
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@tswaehn it looks like you might need to ask to be added as a collaborator in the GH organization, your +1 should be counting towards approval and showing up as green, but it doesn't. |
| uint32_t current = sys_read32(SY1XX_ARCHI_FC_ITC_ADDR + SY1XX_ARCHI_ITC_MASK_SET_OFFSET); | ||
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| sys_write32(current | (1 << (idx & 0x1f)), | ||
| sys_write32(BIT(idx & 0x1f), |
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not for this PR but this mask should have a define, also the parenthesis on SY1XX_ARCHI_REF_CLOCK and SY1XX_ARCHI_PER_CLOCK and redundant
removed redundant parentheses Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
SET/CLR registers are write-only so trying to read/modify/write is inefficient & illegal Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
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SET/CLR registers are write-only so trying to read/modify/write is inefficient & illegal
@tswaehn just curious if this fix is correct - it was a suggestion I got while experimenting with LLMs on the codebase, but since it doesn't seem the ganymed documentation is public, it's hard to tell if it's correct :)