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This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.

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Abdelrahman1810/SPI_Slave_with_Single_Port_RAM

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This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.

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rtl verilog finite-state-machine synthesis vivado systemverilog questasim testbench rtl-design

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