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@openrisc

OpenRISC

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  1. mor1kx Public

    mor1kx - an OpenRISC 1000 processor IP core

    Verilog 529 150

  2. or1k_marocchino Public

    Forked from bandvig/or1k_marocchino

    OpenRISC processor IP core based on Tomasulo algorithm

    Verilog 32 11

  3. doc Public

    Misc documentation and specifications

    12 10

Repositories

Showing 10 of 35 repositories
  • openrisc.github.io Public

    Source for openrisc.io

    HTML 13 10 0 0 Updated Apr 21, 2025
  • linux Public Forked from skristiansson/linux

    Linux kernel source tree

    C 30 57,712 0 0 Updated Apr 20, 2025
  • ompic Public Forked from stffrdhrn/ompic

    Open Multi-Processor Interrupt Controller - for OpenRISC

    Verilog 6 7 0 1 Updated Apr 19, 2025
  • or1k-toolchain-build Public Forked from stffrdhrn/or1k-toolchain-build

    OpenRISC toolchain build scripts

    Shell 0 6 0 0 Updated Apr 1, 2025
  • newlib Public

    newlib OpenRISC development

    C 25 GPL-2.0 24 4 0 Updated Mar 30, 2025
  • or1k-gcc Public

    GCC port for OpenRISC 1000

    23 GPL-2.0 36 0 0 Updated Mar 29, 2025
  • mor1kx Public

    mor1kx - an OpenRISC 1000 processor IP core

    Verilog 529 150 32 5 Updated Mar 29, 2025
  • or1ksim Public

    The OpenRISC 1000 architectural simulator

    C 74 GPL-3.0 44 4 2 Updated Aug 26, 2024
  • or1k-tcltools Public Forked from fjullien/or1k-tcltools
    Tcl 2 8 0 0 Updated Aug 14, 2024
  • or1k-headers Public

    OR1K Common Headers

    Python 0 2 0 0 Updated Aug 14, 2024
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