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rv32i

Here are 127 public repositories matching this topic...

ultraembedded / riscv

RISC-V CPU Core (RV32IM)

asic cpu fpga verification verilog pipeline-processor risc-v rv32i verilator riscv-linux rv32im

Updated Sep 18, 2021
Verilog

shecc

sysprog21 / shecc

A self-hosting and educational C optimizing compiler

c linux arm compiler riscv qemu armv7 cross-compiler elf self-hosting risc-v compiler-optimization rv32i rv32im ssa-form

Updated Feb 27, 2025
C

ultraembedded / biriscv

32-bit Superscalar RISC-V CPU

linux asic cpu fpga verilog xilinx superscalar in-order risc-v branch-prediction coremark rv32i verilator riscv-linux rv32im artix-7 pipelined-processors

Updated Sep 18, 2021
Verilog

syntacore / scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

core riscv rtl ip verilog risc-v rv32i rv32e rv32imc rv32emc

Updated Nov 15, 2024
SystemVerilog

WangXuan95 / USTC-RVSoC

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

cpu fpga riscv rtl verilog systemverilog soc risc-v rv32i softcore

Updated Sep 14, 2023
SystemVerilog

rafaelcalcada / rvx

RISC-V microcontroller IP core developed in Verilog

microcontroller cpu gpio core processor riscv spi uart mcu steel risc-v rv32i system-on-chip zicsr

Updated Mar 20, 2025
Verilog

stnolting / riscv-gcc-prebuilt

📦 Prebuilt RISC-V GCC toolchains for x64 Linux.

linux gcc riscv risc-v prebuilt-binaries rv32i neorv32

Updated Feb 22, 2025
Shell

AngeloJacobo / RISC-V

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

cpu riscv verilog formal-verification risc-v rv32i rv32 5-stage-pipeline

Updated Dec 17, 2023
Verilog

maikmerten / spu32

Small Processing Unit 32: A compact RV32I CPU written in Verilog

fpga verilog icestorm risc-v ice40 rv32i system-on-chip risc-processor

Updated May 30, 2022
C

aignacio / nox

RISC-V Nox core

risc-v rv32i

Updated Jul 26, 2024
C

rv32emu-legacy

sysprog21 / rv32emu-legacy

RISC-V RV32I[MA] emulator with ELF support

emulator risc-v rv32i elf-parser

Updated Oct 21, 2020
C

panda5mt / KyogenRV

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

fpga intel chisel riscv chisel3 altera risc-v rv32i avalon-mm

Updated Apr 11, 2021
Scala

FelipeFFerreira / ITA-CORES

RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32

framework asic chip risc-v rv32i physical-design physical-design-automation femtorv32

Updated Nov 16, 2023
Verilog

HaDes-V

tscheipel / HaDes-V

HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.

processor-architecture pipelines riscv vivado systemverilog computer-architecture gtkwave system-verilog university-course risc-v c-programming rv32i open-education verilator open-educational-resources processor-design assembly-programming hardware-software-codesign microcontroller-design

Updated Jan 28, 2025
SystemVerilog

martinKindall / risc-v-single-cycle

A Single Cycle Risc-V 32 bit CPU

riscv systemverilog basys3 rv32i riscv32 basys3-fpga riscv-assembly single-cycle-processor

Updated Feb 11, 2023
SystemVerilog

rob-ng15 / Silice-Playground

Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice

fpga forth risc-v rv32i j1-cpu de10nano rv32 rv32im rv32imc ulx3s fomu

Updated Jul 2, 2023
C

riscv-atom

saursin / riscv-atom

An open-source 32-bit RISC-V soft-core processor

microcontroller embedded cpu fpga core processor riscv verilog mcu soc risc-v soft-core rv32i system-on-chip riscv32 riscv-processor

Updated Feb 27, 2025
C++

calint / tang-nano-9k--riscv--cache-psram

RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card

systemverilog risc-v rv32i softcore tang-nano-9k

Updated Mar 20, 2025
SystemVerilog

accomdemy / accomdemy_rv32i

伴伴學 RISC-V RV32I Architecture CPU

riscv rv32i

Updated Sep 23, 2022
Verilog

dpretet / friscv

RISCV CPU implementation in SystemVerilog

asic fpga assembler riscv verilog systemverilog fpga-soc risc-v rv32i crossbar axi4 axi4-protocol asic-design riscv-cpu

Updated Oct 8, 2024
SystemVerilog

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