From 95ccd229c01775615f7633d2cd8c7183db7dbae9 Mon Sep 17 00:00:00 2001 From: xunanbin Date: Thu, 5 Sep 2019 11:36:01 +0800 Subject: [PATCH 01/15] Synchronize codes for OP7Pro_O2_BETA_1 and OP7_O2_BETA_1 kernel device tree source code for OnePlus7 and OnePlus7 Pro Change-Id: Ibd40bb9d8413031a55de902e5a9dabfc66212c76 --- .gitignore | 20 + AndroidKernel.mk | 19 +- Documentation/Changes | 455 +- Documentation/aoe/autoload.sh | 0 Documentation/aoe/status.sh | 0 Documentation/aoe/udev-install.sh | 0 .../arm/Samsung/clksrc-change-registers.awk | 0 .../devicetree/bindings/arm/msm/msm.txt | 9 - .../devicetree/bindings/arm/msm/qcom,osm.txt | 3 +- .../bindings/arm/msm/subsystem_notif_virt.txt | 49 - .../bindings/batterydata/batterydata.txt | 6 - .../devicetree/bindings/clock/qcom,camcc.txt | 3 +- .../bindings/clock/qcom,debugcc.txt | 3 +- .../devicetree/bindings/clock/qcom,dispcc.txt | 3 +- .../devicetree/bindings/clock/qcom,gcc.txt | 1 - .../devicetree/bindings/clock/qcom,gpucc.txt | 3 +- .../devicetree/bindings/clock/qcom,npucc.txt | 2 +- .../devicetree/bindings/clock/qcom,rpmh.txt | 3 +- .../devicetree/bindings/clock/qcom,scc.txt | 2 +- .../bindings/clock/qcom,videocc.txt | 3 +- .../bindings/display/msm/sde-lease.txt | 28 - .../devicetree/bindings/dma/qcom_gpi.txt | 6 - .../bindings/drm/msm/mdss-dsi-panel.txt | 2 - .../devicetree/bindings/drm/msm/sde-dsi.txt | 3 +- .../devicetree/bindings/iommu/arm,smmu.txt | 7 - .../bindings/media/video/msm-cam-csiphy.txt | 3 +- .../bindings/media/video/msm-cam-ppi.txt | 102 - .../devicetree/bindings/mhi/msm_mhi_dev.txt | 17 - .../devicetree/bindings/pci/msm_pcie.txt | 2 - .../bindings/pinctrl/qcom,sm6150-pinctrl | 6 - .../power/supply/qcom/oneplus_fastchg.txt | 42 + .../bindings/power/supply/qcom/qpnp-qg.txt | 15 - .../bindings/power/supply/qcom/qpnp-smb5.txt | 13 - .../devicetree/bindings/sound/qcom,hsi2s.txt | 10 +- .../bindings/sound/qcom-audio-dev.txt | 234 - .../devicetree/bindings/sound/tfa98xx.txt | 23 + .../devicetree/bindings/sound/tlv320aic3x.txt | 3 +- .../devicetree/bindings/sound/wcd_codec.txt | 155 +- .../bindings/spmi/qcom,viospmi-pmic-arb.txt | 38 - .../bindings/thermal/qcom-bcl-pmic5.txt | 12 +- .../devicetree/bindings/usb/msm-ssusb.txt | 2 - .../devicetree/bindings/usb/qcom,msm-phy.txt | 6 +- .../devicetree/bindings/vendor-prefixes.txt | 3 + .../filesystems/cifs/winucase_convert.pl | 0 Documentation/s390/config3270.sh | 0 Documentation/sphinx/kernel_include.py | 0 Documentation/sphinx/parse-headers.pl | 0 Documentation/sphinx/rstFlatTable.py | 0 Documentation/target/target-export-device | 0 Documentation/target/tcm_mod_builder.py | 0 Makefile | 3 +- arch/arm/boot/dts/qcom | 1 - arch/arm/boot/dts/qcom/Makefile | 344 + .../dts/qcom/OP-fg-batterydata-3700mah.dtsi | 144 + .../dts/qcom/OP-fg-batterydata-3800mah.dtsi | 144 + .../dts/qcom/OP-fg-batterydata-4000mah.dtsi | 145 + .../dts/qcom/OP-fg-batterydata-4085mah.dtsi | 145 + .../boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi | 55 + .../boot/dts/qcom/apq8016-sbc-soc-pins.dtsi | 89 + arch/arm/boot/dts/qcom/apq8016-sbc.dts | 21 + arch/arm/boot/dts/qcom/apq8016-sbc.dtsi | 502 + .../boot/dts/qcom/apq8096-db820c-pins.dtsi | 39 + .../dts/qcom/apq8096-db820c-pmic-pins.dtsi | 52 + arch/arm/boot/dts/qcom/apq8096-db820c.dts | 21 + arch/arm/boot/dts/qcom/apq8096-db820c.dtsi | 307 + arch/arm/boot/dts/qcom/atoll-coresight.dtsi | 2979 ++++ arch/arm/boot/dts/qcom/atoll-gdsc.dtsi | 162 + .../boot/dts/qcom/atoll-idp-overlay.dts} | 4 +- .../boot/dts/qcom/atoll-idp.dts} | 4 +- .../boot/dts/qcom/atoll-idp.dtsi} | 8 - arch/arm/boot/dts/qcom/atoll-ion.dtsi | 41 + arch/arm/boot/dts/qcom/atoll-pinctrl.dtsi | 250 + arch/arm/boot/dts/qcom/atoll-pm.dtsi | 170 + arch/arm/boot/dts/qcom/atoll-qrd-overlay.dts | 23 + .../boot/dts/qcom/atoll-qrd.dts} | 8 +- arch/arm/boot/dts/qcom/atoll-qrd.dtsi | 14 + arch/arm/boot/dts/qcom/atoll-qupv3.dtsi | 62 + .../boot/dts/qcom/atoll-rumi-overlay.dts} | 8 +- arch/arm/boot/dts/qcom/atoll-rumi.dts | 22 + arch/arm/boot/dts/qcom/atoll-rumi.dtsi | 144 + .../boot/dts/qcom/atoll-stub-regulator.dtsi | 405 + arch/arm/boot/dts/qcom/atoll-thermal.dtsi | 621 + arch/arm/boot/dts/qcom/atoll-usb.dtsi | 372 + arch/arm/boot/dts/qcom/atoll-vidc.dtsi | 106 + .../arm/boot/dts/qcom/atoll.dts | 15 +- arch/arm/boot/dts/qcom/atoll.dtsi | 2486 +++ arch/arm/boot/dts/qcom/dm-verity-boot.dtsi | 28 + .../dts/qcom/dsi-panel-ext-bridge-1080p.dtsi | 52 + .../qcom/dsi-panel-ext-bridge-hdmi-1080p.dtsi | 52 + ...l-hx83112a-truly-singlemipi-fhd-video.dtsi | 159 + .../qcom/dsi-panel-hx8394d-720p-video.dtsi | 99 + ...dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi | 247 + ...i-panel-nt35597-truly-dsc-wqxga-video.dtsi | 233 + ...anel-nt35597-truly-dualmipi-wqxga-cmd.dtsi | 226 + ...el-nt35597-truly-dualmipi-wqxga-video.dtsi | 213 + .../dsi-panel-nt35695b-truly-fhd-cmd.dtsi | 188 + .../dsi-panel-nt35695b-truly-fhd-video.dtsi | 184 + .../dsi-panel-nt36672-truly-fhd-video.dtsi | 282 + ...panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi | 87 + ...nel-rm69298-truly-amoled-fhd-plus-cmd.dtsi | 330 + ...l-rm69298-truly-amoled-fhd-plus-video.dtsi | 330 + ...m69299-visionox-amoled-fhd-plus-video.dtsi | 75 + ...anel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi | 141 + .../qcom/dsi-panel-samsung_oneplus_dsc.dtsi | 2665 ++++ .../qcom/dsi-panel-samsung_s6e3fc2x01.dtsi | 435 + .../dsi-panel-samsung_sofef00_m_video.dtsi | 103 + .../dts/qcom/dsi-panel-sharp-1080p-cmd.dtsi | 86 + .../dts/qcom/dsi-panel-sharp-dsc-4k-cmd.dtsi | 103 + .../qcom/dsi-panel-sharp-dsc-4k-video.dtsi | 96 + .../dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi | 93 + .../dsi-panel-sharp-dualdsi-wqhd-video.dtsi | 89 + .../dsi-panel-sharp-dualmipi-1080p-120hz.dtsi | 633 + ...si-panel-sharp-split-link-wuxga-video.dtsi | 74 + arch/arm/boot/dts/qcom/dsi-panel-sim-cmd.dtsi | 220 + .../dts/qcom/dsi-panel-sim-dsc375-cmd.dtsi | 286 + .../dts/qcom/dsi-panel-sim-dualmipi-cmd.dtsi | 146 + .../dsi-panel-sim-dualmipi-dsc375-cmd.dtsi | 281 + .../qcom/dsi-panel-sim-dualmipi-video.dtsi | 70 + .../dts/qcom/dsi-panel-sim-sec-hd-cmd.dtsi | 75 + .../boot/dts/qcom/dsi-panel-sim-video.dtsi | 69 + ...panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi | 111 + ...dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi | 130 + ...i-panel-sw43404-amoled-dsc-wqhd-video.dtsi | 95 + .../dts/qcom/dsi-panel-td4328-1080p-cmd.dtsi | 177 + .../qcom/dsi-panel-td4328-1080p-video.dtsi | 172 + ...panel-td4330-truly-singlemipi-fhd-cmd.dtsi | 316 + ...nel-td4330-truly-singlemipi-fhd-video.dtsi | 315 + .../fg-gen4-batterydata-alium-3600mah.dtsi | 154 + ...fg-gen4-batterydata-mlp466076-3250mah.dtsi | 149 + .../boot/dts/qcom/guacamole-overlay-dvt.dts | 43 + .../boot/dts/qcom/guacamole-overlay-evt1.dts | 39 + .../qcom/guacamole-overlay-evt2-second.dts | 40 + .../boot/dts/qcom/guacamole-overlay-evt2.dts | 40 + .../boot/dts/qcom/guacamole-overlay-evt3.dts | 41 + .../boot/dts/qcom/guacamole-overlay-pvt.dts | 44 + .../boot/dts/qcom/guacamole-overlay-t0.dts | 39 + .../dts/qcom/guacamole-sdx50m-overlay-dvt.dts | 46 + .../qcom/guacamole-sdx50m-overlay-evt1.dts | 44 + .../qcom/guacamole-sdx50m-overlay-evt2.dts | 45 + .../dts/qcom/guacamole-sdx50m-overlay-pvt.dts | 47 + .../dts/qcom/guacamole-sdx50m-overlay-t0.dts | 43 + arch/arm/boot/dts/qcom/guacamole.dtsi | 166 + arch/arm/boot/dts/qcom/guacamole_dvt.dtsi | 1 + arch/arm/boot/dts/qcom/guacamole_evt1.dtsi | 2 + arch/arm/boot/dts/qcom/guacamole_evt2.dtsi | 2 + arch/arm/boot/dts/qcom/guacamole_evt3.dtsi | 2 + arch/arm/boot/dts/qcom/guacamole_pvt.dtsi | 1 + arch/arm/boot/dts/qcom/guacamole_sdx50m.dtsi | 17 + arch/arm/boot/dts/qcom/guacamole_sm8150.dtsi | 8 + arch/arm/boot/dts/qcom/guacamole_t0.dtsi | 99 + .../boot/dts/qcom/guacamoleb-overlay-dvt.dts | 39 + .../boot/dts/qcom/guacamoleb-overlay-evt.dts | 39 + .../boot/dts/qcom/guacamoleb-overlay-pvt.dts | 39 + .../boot/dts/qcom/guacamoleb-overlay-t0.dts | 39 + arch/arm/boot/dts/qcom/guacamoleb.dtsi | 490 + arch/arm/boot/dts/qcom/guacamoleb_dvt.dtsi | 1 + arch/arm/boot/dts/qcom/guacamoleb_evt.dtsi | 1 + arch/arm/boot/dts/qcom/guacamoleb_pvt.dtsi | 1 + arch/arm/boot/dts/qcom/guacamoleb_sm8150.dtsi | 7 + arch/arm/boot/dts/qcom/guacamoleb_t0.dtsi | 4 + .../qcom/guacamoles-sdx50m-overlay-dvt.dts | 45 + .../qcom/guacamoles-sdx50m-overlay-evt.dts | 45 + .../qcom/guacamoles-sdx50m-overlay-pvt.dts | 45 + .../dts/qcom/guacamoles-sdx50m-overlay-t0.dts | 44 + arch/arm/boot/dts/qcom/guacamoles_sdx50m.dtsi | 11 + .../boot/dts/qcom/guacamoles_sdx50m_dvt.dtsi | 2 + .../boot/dts/qcom/guacamoles_sdx50m_evt.dtsi | 1 + .../boot/dts/qcom/guacamoles_sdx50m_pvt.dtsi | 1 + .../boot/dts/qcom/guacamoles_sdx50m_t0.dtsi | 1 + arch/arm/boot/dts/qcom/ipq8074-hk01.dts | 52 + arch/arm/boot/dts/qcom/ipq8074.dtsi | 194 + .../arm/boot/dts/qcom/msm-arm-smmu-atoll.dtsi | 204 + .../boot/dts/qcom/msm-arm-smmu-qcs405.dtsi | 92 + .../boot/dts/qcom/msm-arm-smmu-sdmmagpie.dtsi | 358 + .../boot/dts/qcom/msm-arm-smmu-sdmshrike.dtsi | 444 + .../dts/qcom/msm-arm-smmu-sdxprairie.dtsi | 102 + .../boot/dts/qcom/msm-arm-smmu-sm6150.dtsi | 317 + .../boot/dts/qcom/msm-arm-smmu-sm8150-v2.dtsi | 406 + .../boot/dts/qcom/msm-arm-smmu-sm8150.dtsi | 420 + .../boot/dts/qcom/msm-arm-smmu-trinket.dtsi | 280 + arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi | 738 + arch/arm/boot/dts/qcom/msm-qvr-external.dtsi | 21 + arch/arm/boot/dts/qcom/msm-rdbg.dtsi | 35 + arch/arm/boot/dts/qcom/msm-wsa881x.dtsi | 77 + arch/arm/boot/dts/qcom/msm8916-mtp.dts | 22 + arch/arm/boot/dts/qcom/msm8916-mtp.dtsi | 35 + arch/arm/boot/dts/qcom/msm8916-pins.dtsi | 736 + arch/arm/boot/dts/qcom/msm8916.dtsi | 1461 ++ .../dts/qcom/msm8992-bullhead-rev-101.dts | 41 + arch/arm/boot/dts/qcom/msm8992-pins.dtsi | 38 + arch/arm/boot/dts/qcom/msm8992.dtsi | 237 + .../boot/dts/qcom/msm8994-angler-rev-101.dts | 40 + arch/arm/boot/dts/qcom/msm8994-pins.dtsi | 38 + arch/arm/boot/dts/qcom/msm8994.dtsi | 216 + arch/arm/boot/dts/qcom/msm8996-mtp.dts | 21 + arch/arm/boot/dts/qcom/msm8996-mtp.dtsi | 30 + arch/arm/boot/dts/qcom/msm8996-pins.dtsi | 303 + arch/arm/boot/dts/qcom/msm8996.dtsi | 925 ++ .../boot/dts/qcom/pm6125-rpm-regulator.dtsi | 505 + arch/arm/boot/dts/qcom/pm6125.dtsi | 224 + arch/arm/boot/dts/qcom/pm6150.dtsi | 665 + arch/arm/boot/dts/qcom/pm6150l.dtsi | 514 + arch/arm/boot/dts/qcom/pm6155.dtsi | 175 + arch/arm/boot/dts/qcom/pm8004.dtsi | 20 + arch/arm/boot/dts/qcom/pm8008.dtsi | 117 + arch/arm/boot/dts/qcom/pm8009.dtsi | 47 + arch/arm/boot/dts/qcom/pm8150.dtsi | 194 + arch/arm/boot/dts/qcom/pm8150b.dtsi | 703 + arch/arm/boot/dts/qcom/pm8150l.dtsi | 516 + arch/arm/boot/dts/qcom/pm8195.dtsi | 251 + arch/arm/boot/dts/qcom/pm8916.dtsi | 143 + arch/arm/boot/dts/qcom/pm8994.dtsi | 71 + arch/arm/boot/dts/qcom/pmi632.dtsi | 737 + arch/arm/boot/dts/qcom/pmi8994.dtsi | 37 + .../boot/dts/qcom/pms405-rpm-regulator.dtsi | 317 + arch/arm/boot/dts/qcom/pms405.dtsi | 207 + arch/arm/boot/dts/qcom/pmxprairie.dtsi | 209 + arch/arm/boot/dts/qcom/qcs401-iot-sku1.dts | 81 + arch/arm/boot/dts/qcom/qcs401.dtsi | 48 + .../boot/dts/qcom/qcs403-ext-pll-audio.dtsi | 29 + arch/arm/boot/dts/qcom/qcs403-iot-sku1.dts | 88 + arch/arm/boot/dts/qcom/qcs403-iot-sku2.dts | 124 + arch/arm/boot/dts/qcom/qcs403-iot-sku3.dts | 150 + arch/arm/boot/dts/qcom/qcs403-iot-sku4.dts | 126 + arch/arm/boot/dts/qcom/qcs403.dtsi | 61 + .../dts/qcom/qcs405-amic-audio-overlay.dtsi | 40 + .../boot/dts/qcom/qcs405-audio-overlay.dtsi | 103 + arch/arm/boot/dts/qcom/qcs405-audio.dtsi | 193 + arch/arm/boot/dts/qcom/qcs405-blsp.dtsi | 526 + arch/arm/boot/dts/qcom/qcs405-bus.dtsi | 895 ++ .../dts/qcom/qcs405-circular-pca9956.dtsi | 246 + arch/arm/boot/dts/qcom/qcs405-coresight.dtsi | 1089 ++ arch/arm/boot/dts/qcom/qcs405-cpu.dtsi | 192 + .../dts/qcom/qcs405-csra1-audio-overlay.dtsi} | 4 +- .../boot/dts/qcom/qcs405-csra1.dtsi} | 4 +- .../dts/qcom/qcs405-csra6-audio-overlay.dtsi | 145 + arch/arm/boot/dts/qcom/qcs405-csra6.dtsi | 95 + .../dts/qcom/qcs405-csra8-audio-overlay.dtsi | 150 + arch/arm/boot/dts/qcom/qcs405-csra8.dtsi | 118 + arch/arm/boot/dts/qcom/qcs405-gdsc.dtsi | 29 + .../boot/dts/qcom/qcs405-geni-ir-overlay.dtsi | 35 + arch/arm/boot/dts/qcom/qcs405-gpu.dtsi | 187 + arch/arm/boot/dts/qcom/qcs405-ion.dtsi | 43 + .../boot/dts/qcom/qcs405-iot-sku1.dts} | 8 +- arch/arm/boot/dts/qcom/qcs405-iot-sku10.dts | 62 + arch/arm/boot/dts/qcom/qcs405-iot-sku11.dts | 79 + .../boot/dts/qcom/qcs405-iot-sku12.dts} | 8 +- arch/arm/boot/dts/qcom/qcs405-iot-sku2.dts | 192 + .../boot/dts/qcom/qcs405-iot-sku3.dts} | 8 +- .../boot/dts/qcom/qcs405-iot-sku4.dts} | 8 +- arch/arm/boot/dts/qcom/qcs405-iot-sku5.dts | 97 + arch/arm/boot/dts/qcom/qcs405-iot-sku6.dts | 72 + arch/arm/boot/dts/qcom/qcs405-iot-sku7.dts | 63 + .../boot/dts/qcom/qcs405-iot-sku8.dts} | 12 +- .../boot/dts/qcom/qcs405-iot-sku9.dts} | 6 +- .../boot/dts/qcom/qcs405-linear-pca9956.dtsi | 250 + arch/arm/boot/dts/qcom/qcs405-lpi.dtsi | 484 + .../arm/boot/dts/qcom/qcs405-mdss-panels.dtsi | 31 + arch/arm/boot/dts/qcom/qcs405-mdss-pll.dtsi | 126 + arch/arm/boot/dts/qcom/qcs405-mdss.dtsi | 466 + arch/arm/boot/dts/qcom/qcs405-mhi.dtsi | 716 + .../dts/qcom/qcs405-nowcd-audio-overlay.dtsi | 85 + arch/arm/boot/dts/qcom/qcs405-pcie.dtsi | 138 + arch/arm/boot/dts/qcom/qcs405-pinctrl.dtsi | 2478 +++ arch/arm/boot/dts/qcom/qcs405-pm.dtsi | 140 + arch/arm/boot/dts/qcom/qcs405-regulator.dtsi | 383 + arch/arm/boot/dts/qcom/qcs405-rumi.dts | 27 + arch/arm/boot/dts/qcom/qcs405-rumi.dtsi | 134 + .../boot/dts/qcom/qcs405-stub-regulator.dtsi | 194 + arch/arm/boot/dts/qcom/qcs405-tasha.dtsi | 113 + .../dts/qcom/qcs405-tdm-audio-overlay.dtsi | 87 + arch/arm/boot/dts/qcom/qcs405-thermal.dtsi | 417 + arch/arm/boot/dts/qcom/qcs405-usb.dtsi | 216 + arch/arm/boot/dts/qcom/qcs405-va-bolero.dtsi | 38 + .../dts/qcom/qcs405-wsa-audio-overlay.dtsi | 127 + arch/arm/boot/dts/qcom/qcs405-wsa-bolero.dtsi | 40 + arch/arm/boot/dts/qcom/qcs405-wsa881x.dtsi | 61 + arch/arm/boot/dts/qcom/qcs405.dtsi | 1691 ++ arch/arm/boot/dts/qcom/qcs410-iot-overlay.dts | 23 + arch/arm/boot/dts/qcom/qcs410-iot.dts | 22 + arch/arm/boot/dts/qcom/qcs410-iot.dtsi | 165 + arch/arm/boot/dts/qcom/qcs410.dts | 21 + arch/arm/boot/dts/qcom/qcs410.dtsi | 137 + .../dts/qcom/qcs610-camera-sensor-idp.dtsi | 98 + arch/arm/boot/dts/qcom/qcs610-iot-overlay.dts | 25 + arch/arm/boot/dts/qcom/qcs610-iot.dts | 26 + arch/arm/boot/dts/qcom/qcs610-iot.dtsi | 447 + arch/arm/boot/dts/qcom/qcs610.dts | 21 + arch/arm/boot/dts/qcom/qcs610.dtsi | 29 + .../qcom/qg-batterydata-alium-3600mah.dtsi | 1048 ++ .../qcom/qg-batterydata-ascent-3450mah.dtsi | 1042 ++ .../qg-batterydata-mlp356477-2800mah.dtsi | 1044 ++ .../qg-batterydata-mlp466076-3200mah.dtsi | 1044 ++ arch/arm/boot/dts/qcom/quin-vm-common.dtsi | 251 + arch/arm/boot/dts/qcom/rgb-panel-st7789v.dtsi | 30 + .../boot/dts/qcom/sa515m-ccard-pcie-ep.dts | 46 + .../arm/boot/dts/qcom/sa515m-ccard-usb-ep.dts | 22 + arch/arm/boot/dts/qcom/sa515m-ccard.dts | 22 + arch/arm/boot/dts/qcom/sa515m-ccard.dtsi | 132 + .../boot/dts/qcom/sa6155-adp-air-overlay.dts | 25 + arch/arm/boot/dts/qcom/sa6155-adp-air.dts | 21 + arch/arm/boot/dts/qcom/sa6155-adp-air.dtsi | 267 + .../boot/dts/qcom/sa6155-adp-star-overlay.dts | 25 + arch/arm/boot/dts/qcom/sa6155-adp-star.dts | 21 + arch/arm/boot/dts/qcom/sa6155-adp-star.dtsi | 275 + arch/arm/boot/dts/qcom/sa6155-audio.dtsi | 597 + arch/arm/boot/dts/qcom/sa6155-cnss.dtsi | 223 + arch/arm/boot/dts/qcom/sa6155-display.dtsi | 227 + arch/arm/boot/dts/qcom/sa6155-pcie.dtsi | 253 + arch/arm/boot/dts/qcom/sa6155-pmic.dtsi | 319 + arch/arm/boot/dts/qcom/sa6155-regulator.dtsi | 537 + arch/arm/boot/dts/qcom/sa6155.dts | 22 + arch/arm/boot/dts/qcom/sa6155.dtsi | 485 + .../boot/dts/qcom/sa6155p-adp-air-overlay.dts | 26 + arch/arm/boot/dts/qcom/sa6155p-adp-air.dts | 22 + .../dts/qcom/sa6155p-adp-star-overlay.dts | 26 + arch/arm/boot/dts/qcom/sa6155p-adp-star.dts | 22 + .../dts/qcom/sa6155p-v2-adp-air-overlay.dts | 26 + arch/arm/boot/dts/qcom/sa6155p-v2-adp-air.dts | 22 + .../dts/qcom/sa6155p-v2-adp-star-overlay.dts | 26 + .../arm/boot/dts/qcom/sa6155p-v2-adp-star.dts | 22 + arch/arm/boot/dts/qcom/sa6155p-vm-pcie.dtsi | 245 + .../arm/boot/dts/qcom/sa6155p-vm-pinctrl.dtsi | 1783 +++ arch/arm/boot/dts/qcom/sa6155p-vm-qupv3.dtsi | 450 + arch/arm/boot/dts/qcom/sa6155p-vm-usb.dtsi | 404 + arch/arm/boot/dts/qcom/sa6155p-vm.dts | 52 + arch/arm/boot/dts/qcom/sa6155p-vm.dtsi | 351 + arch/arm/boot/dts/qcom/sa6155p.dts | 22 + arch/arm/boot/dts/qcom/sa6155p.dtsi | 517 + .../dts/qcom/sa8155-adp-alcor-display.dtsi | 91 + .../dts/qcom/sa8155-adp-alcor-overlay.dts | 23 + arch/arm/boot/dts/qcom/sa8155-adp-alcor.dts | 22 + arch/arm/boot/dts/qcom/sa8155-adp-alcor.dtsi | 98 + arch/arm/boot/dts/qcom/sa8155-adp-common.dtsi | 249 + .../dts/qcom/sa8155-adp-star-display.dtsi | 319 + .../boot/dts/qcom/sa8155-adp-star-overlay.dts | 25 + arch/arm/boot/dts/qcom/sa8155-adp-star.dts | 22 + arch/arm/boot/dts/qcom/sa8155-adp-star.dtsi | 52 + arch/arm/boot/dts/qcom/sa8155-audio.dtsi | 614 + .../boot/dts/qcom/sa8155-camera-sensor.dtsi | 143 + arch/arm/boot/dts/qcom/sa8155-cnss.dtsi | 350 + .../boot/dts/qcom/sa8155-pmic-overlay.dtsi | 125 + arch/arm/boot/dts/qcom/sa8155-regulator.dtsi | 726 + arch/arm/boot/dts/qcom/sa8155-v1.dtsi | 21 + .../dts/qcom/sa8155-v2-adp-air-overlay.dts | 24 + arch/arm/boot/dts/qcom/sa8155-v2-adp-air.dts | 23 + arch/arm/boot/dts/qcom/sa8155-v2-adp-star.dts | 22 + arch/arm/boot/dts/qcom/sa8155-v2.dts | 26 + arch/arm/boot/dts/qcom/sa8155-v2.dtsi | 147 + arch/arm/boot/dts/qcom/sa8155-vm-audio.dtsi | 534 + arch/arm/boot/dts/qcom/sa8155-vm-la-mt.dts | 30 + arch/arm/boot/dts/qcom/sa8155-vm-lv-mt.dts | 59 + arch/arm/boot/dts/qcom/sa8155-vm-lv.dts | 47 + arch/arm/boot/dts/qcom/sa8155-vm-mhi.dtsi | 551 + arch/arm/boot/dts/qcom/sa8155-vm-pcie.dtsi | 279 + arch/arm/boot/dts/qcom/sa8155-vm-pinctrl.dtsi | 25 + arch/arm/boot/dts/qcom/sa8155-vm-qupv3.dtsi | 960 ++ arch/arm/boot/dts/qcom/sa8155-vm-usb.dtsi | 542 + arch/arm/boot/dts/qcom/sa8155-vm.dts | 43 + arch/arm/boot/dts/qcom/sa8155-vm.dtsi | 496 + arch/arm/boot/dts/qcom/sa8155.dts | 26 + arch/arm/boot/dts/qcom/sa8155.dtsi | 610 + .../dts/qcom/sa8155p-adp-alcor-overlay.dts | 23 + arch/arm/boot/dts/qcom/sa8155p-adp-alcor.dts | 23 + .../dts/qcom/sa8155p-adp-star-overlay.dts | 25 + arch/arm/boot/dts/qcom/sa8155p-adp-star.dts | 22 + .../dts/qcom/sa8155p-v2-adp-air-overlay.dts | 24 + arch/arm/boot/dts/qcom/sa8155p-v2-adp-air.dts | 23 + .../arm/boot/dts/qcom/sa8155p-v2-adp-star.dts | 22 + arch/arm/boot/dts/qcom/sa8155p-v2.dts | 26 + arch/arm/boot/dts/qcom/sa8155p-v2.dtsi | 19 + arch/arm/boot/dts/qcom/sa8155p.dts | 26 + arch/arm/boot/dts/qcom/sa8155p.dtsi | 20 + arch/arm/boot/dts/qcom/sa8195-pmic.dtsi | 121 + arch/arm/boot/dts/qcom/sa8195-vm.dts | 38 + arch/arm/boot/dts/qcom/sa8195-vm.dtsi | 207 + .../dts/qcom/sa8195p-adp-star-display.dtsi | 306 + .../dts/qcom/sa8195p-adp-star-overlay.dts | 23 + arch/arm/boot/dts/qcom/sa8195p-adp-star.dts | 22 + arch/arm/boot/dts/qcom/sa8195p-adp-star.dtsi | 36 + arch/arm/boot/dts/qcom/sa8195p-pcie.dtsi | 805 + arch/arm/boot/dts/qcom/sa8195p-regulator.dtsi | 850 + arch/arm/boot/dts/qcom/sa8195p.dts | 22 + arch/arm/boot/dts/qcom/sa8195p.dtsi | 108 + .../boot/dts/qcom/sdmmagpie-atp-overlay.dts | 32 + arch/arm/boot/dts/qcom/sdmmagpie-atp.dts | 22 + arch/arm/boot/dts/qcom/sdmmagpie-atp.dtsi | 387 + .../dts/qcom/sdmmagpie-audio-overlay.dtsi | 32 + arch/arm/boot/dts/qcom/sdmmagpie-audio.dtsi | 18 + .../boot/dts/qcom/sdmmagpie-bus.dtsi} | 1108 +- .../dts/qcom/sdmmagpie-camera-sensor-idp.dtsi | 617 + .../qcom/sdmmagpie-camera-sensor-qrd.dtsi} | 219 +- arch/arm/boot/dts/qcom/sdmmagpie-camera.dtsi | 1241 ++ .../boot/dts/qcom/sdmmagpie-coresight.dtsi | 2721 ++++ .../sdmmagpie-dual-display-idp-overlay.dts | 40 + .../dts/qcom/sdmmagpie-dual-display-idp.dts | 35 + .../sdmmagpie-ext-codec-audio-overlay.dtsi | 26 + .../sdmmagpie-external-codec-idp-overlay.dts | 28 + .../dts/qcom/sdmmagpie-external-codec-idp.dts | 24 + .../dts/qcom/sdmmagpie-external-codec.dtsi | 14 + arch/arm/boot/dts/qcom/sdmmagpie-gdsc.dtsi | 230 + arch/arm/boot/dts/qcom/sdmmagpie-gpu.dtsi | 608 + .../boot/dts/qcom/sdmmagpie-idp-overlay.dts | 31 + arch/arm/boot/dts/qcom/sdmmagpie-idp.dts | 26 + arch/arm/boot/dts/qcom/sdmmagpie-idp.dtsi | 432 + arch/arm/boot/dts/qcom/sdmmagpie-ion.dtsi | 62 + arch/arm/boot/dts/qcom/sdmmagpie-npu.dtsi | 191 + arch/arm/boot/dts/qcom/sdmmagpie-pinctrl.dtsi | 1683 ++ arch/arm/boot/dts/qcom/sdmmagpie-pm.dtsi | 170 + .../boot/dts/qcom/sdmmagpie-qrd-overlay.dts | 70 + arch/arm/boot/dts/qcom/sdmmagpie-qrd.dts | 22 + arch/arm/boot/dts/qcom/sdmmagpie-qrd.dtsi | 431 + arch/arm/boot/dts/qcom/sdmmagpie-qupv3.dtsi | 565 + .../boot/dts/qcom/sdmmagpie-regulator.dtsi} | 777 +- .../boot/dts/qcom/sdmmagpie-rumi-overlay.dts | 26 + arch/arm/boot/dts/qcom/sdmmagpie-rumi.dts | 22 + arch/arm/boot/dts/qcom/sdmmagpie-rumi.dtsi | 192 + .../boot/dts/qcom/sdmmagpie-sde-display.dtsi | 742 + .../boot/dts/qcom/sdmmagpie-sde-pll.dtsi} | 35 +- arch/arm/boot/dts/qcom/sdmmagpie-sde.dtsi | 690 + .../dts/qcom/sdmmagpie-stub-regulator.dtsi | 352 + .../dts/qcom/sdmmagpie-thermal-overlay.dtsi | 182 + arch/arm/boot/dts/qcom/sdmmagpie-thermal.dtsi | 1912 +++ arch/arm/boot/dts/qcom/sdmmagpie-usb.dtsi | 375 + .../dts/qcom/sdmmagpie-usbc-idp-overlay.dts | 26 + arch/arm/boot/dts/qcom/sdmmagpie-usbc-idp.dts | 23 + .../arm/boot/dts/qcom/sdmmagpie-usbc-idp.dtsi | 19 + arch/arm/boot/dts/qcom/sdmmagpie-vidc.dtsi | 219 + arch/arm/boot/dts/qcom/sdmmagpie.dts | 22 + arch/arm/boot/dts/qcom/sdmmagpie.dtsi | 3472 ++++ .../boot/dts/qcom/sdmmagpiep-atp-overlay.dts | 26 + arch/arm/boot/dts/qcom/sdmmagpiep-atp.dts | 22 + .../boot/dts/qcom/sdmmagpiep-idp-overlay.dts | 26 + arch/arm/boot/dts/qcom/sdmmagpiep-idp.dts | 22 + .../boot/dts/qcom/sdmmagpiep-qrd-overlay.dts | 25 + arch/arm/boot/dts/qcom/sdmmagpiep-qrd.dts | 22 + arch/arm/boot/dts/qcom/sdmmagpiep.dts | 22 + arch/arm/boot/dts/qcom/sdmmagpiep.dtsi | 19 + .../dts/qcom/sdmshrike-audio-overlay.dtsi | 307 + arch/arm/boot/dts/qcom/sdmshrike-bus.dtsi | 2148 +++ .../boot/dts/qcom/sdmshrike-cdp-overlay.dts | 26 + arch/arm/boot/dts/qcom/sdmshrike-cdp.dts | 22 + arch/arm/boot/dts/qcom/sdmshrike-cdp.dtsi | 123 + arch/arm/boot/dts/qcom/sdmshrike-gdsc.dtsi | 60 + arch/arm/boot/dts/qcom/sdmshrike-gpu.dtsi | 393 + arch/arm/boot/dts/qcom/sdmshrike-ion.dtsi | 65 + .../boot/dts/qcom/sdmshrike-mtp-overlay.dts | 26 + arch/arm/boot/dts/qcom/sdmshrike-mtp.dts | 22 + arch/arm/boot/dts/qcom/sdmshrike-mtp.dtsi | 156 + arch/arm/boot/dts/qcom/sdmshrike-pinctrl.dtsi | 4246 +++++ .../boot/dts/qcom/sdmshrike-pmic-overlay.dtsi | 111 + arch/arm/boot/dts/qcom/sdmshrike-qupv3.dtsi | 989 ++ .../boot/dts/qcom/sdmshrike-regulators.dtsi | 971 ++ arch/arm/boot/dts/qcom/sdmshrike-rumi.dts | 23 + arch/arm/boot/dts/qcom/sdmshrike-rumi.dtsi | 73 + .../boot/dts/qcom/sdmshrike-sde-display.dtsi | 615 + arch/arm/boot/dts/qcom/sdmshrike-sde-pll.dtsi | 92 + arch/arm/boot/dts/qcom/sdmshrike-sde.dtsi | 717 + arch/arm/boot/dts/qcom/sdmshrike-smp2p.dtsi | 96 + .../dts/qcom/sdmshrike-thermal-overlay.dtsi | 166 + arch/arm/boot/dts/qcom/sdmshrike-thermal.dtsi | 1367 ++ .../boot/dts/qcom/sdmshrike-usb.dtsi} | 93 +- arch/arm/boot/dts/qcom/sdmshrike-v2-mtp.dts | 22 + arch/arm/boot/dts/qcom/sdmshrike-v2.dts | 22 + arch/arm/boot/dts/qcom/sdmshrike-v2.dtsi | 262 + arch/arm/boot/dts/qcom/sdmshrike.dts | 22 + arch/arm/boot/dts/qcom/sdmshrike.dtsi | 2513 +++ arch/arm/boot/dts/qcom/sdx-audio-lpass.dtsi | 345 + arch/arm/boot/dts/qcom/sdx-wsa881x.dtsi | 45 + .../boot/dts/qcom/sdx5xm-external-soc.dtsi | 59 + arch/arm/boot/dts/qcom/sdxprairie-aqc.dtsi | 95 + .../dts/qcom/sdxprairie-audio-overlay.dtsi | 143 + arch/arm/boot/dts/qcom/sdxprairie-audio.dtsi | 55 + arch/arm/boot/dts/qcom/sdxprairie-blsp.dtsi | 572 + arch/arm/boot/dts/qcom/sdxprairie-bus.dtsi | 958 ++ arch/arm/boot/dts/qcom/sdxprairie-cdp-256.dts | 31 + .../arm/boot/dts/qcom/sdxprairie-cdp-256.dtsi | 182 + .../qcom/sdxprairie-cdp-audio-overlay.dtsi | 22 + arch/arm/boot/dts/qcom/sdxprairie-cdp-cpe.dts | 24 + .../arm/boot/dts/qcom/sdxprairie-cdp-cpe.dtsi | 22 + .../boot/dts/qcom/sdxprairie-cdp.dts} | 20 +- arch/arm/boot/dts/qcom/sdxprairie-cdp.dtsi | 213 + .../boot/dts/qcom/sdxprairie-coresight.dtsi | 1283 ++ .../arm/boot/dts/qcom/sdxprairie-dsda-cdp.dts | 56 + .../arm/boot/dts/qcom/sdxprairie-dsda-mtp.dts | 56 + arch/arm/boot/dts/qcom/sdxprairie-gdsc.dtsi | 36 + arch/arm/boot/dts/qcom/sdxprairie-ion.dtsi | 41 + arch/arm/boot/dts/qcom/sdxprairie-mtp-256.dts | 31 + .../arm/boot/dts/qcom/sdxprairie-mtp-256.dtsi | 224 + arch/arm/boot/dts/qcom/sdxprairie-mtp-aqc.dts | 31 + .../qcom/sdxprairie-mtp-audio-overlay.dtsi | 22 + arch/arm/boot/dts/qcom/sdxprairie-mtp-cpe.dts | 55 + .../arm/boot/dts/qcom/sdxprairie-mtp-cpe.dtsi | 18 + arch/arm/boot/dts/qcom/sdxprairie-mtp.dts | 31 + arch/arm/boot/dts/qcom/sdxprairie-mtp.dtsi | 245 + .../boot/dts/qcom/sdxprairie-pcie-ep-mtp.dts | 24 + .../boot/dts/qcom/sdxprairie-pcie-ep-mtp.dtsi | 42 + arch/arm/boot/dts/qcom/sdxprairie-pcie.dtsi | 250 + .../arm/boot/dts/qcom/sdxprairie-pinctrl.dtsi | 1477 ++ arch/arm/boot/dts/qcom/sdxprairie-pm.dtsi | 102 + .../dts/qcom/sdxprairie-pmic-overlay.dtsi | 51 + .../boot/dts/qcom/sdxprairie-regulator.dtsi | 511 + arch/arm/boot/dts/qcom/sdxprairie-rumi.dts | 31 + arch/arm/boot/dts/qcom/sdxprairie-rumi.dtsi | 91 + .../arm/boot/dts/qcom/sdxprairie-thermal.dtsi | 428 + arch/arm/boot/dts/qcom/sdxprairie-usb.dtsi | 285 + arch/arm/boot/dts/qcom/sdxprairie-v2-cdp.dts | 23 + arch/arm/boot/dts/qcom/sdxprairie-v2-mtp.dts | 25 + arch/arm/boot/dts/qcom/sdxprairie-v2.dtsi | 31 + arch/arm/boot/dts/qcom/sdxprairie-wcd.dtsi | 80 + arch/arm/boot/dts/qcom/sdxprairie.dtsi | 1519 ++ arch/arm/boot/dts/qcom/skeleton.dtsi | 18 + arch/arm/boot/dts/qcom/skeleton64.dtsi | 15 + .../boot/dts/qcom/sm6150-audio-overlay.dtsi} | 386 +- arch/arm/boot/dts/qcom/sm6150-audio.dtsi | 155 + arch/arm/boot/dts/qcom/sm6150-bus.dtsi | 1850 +++ .../dts/qcom/sm6150-camera-sensor-adp.dtsi | 115 + .../dts/qcom/sm6150-camera-sensor-idp.dtsi | 624 + .../dts/qcom/sm6150-camera-sensor-qrd.dtsi | 364 + .../boot/dts/qcom/sm6150-camera.dtsi} | 620 +- .../sm6150-cmd-mode-display-idp-overlay.dts | 62 + .../dts/qcom/sm6150-cmd-mode-display-idp.dts | 22 + arch/arm/boot/dts/qcom/sm6150-coresight.dtsi | 2774 ++++ .../qcom/sm6150-ext-codec-audio-overlay.dtsi | 89 + .../sm6150-external-codec-idp-overlay.dts | 32 + .../dts/qcom/sm6150-external-codec-idp.dts | 24 + .../boot/dts/qcom/sm6150-external-codec.dtsi | 151 + arch/arm/boot/dts/qcom/sm6150-gdsc.dtsi | 213 + arch/arm/boot/dts/qcom/sm6150-gpu.dtsi | 651 + arch/arm/boot/dts/qcom/sm6150-idp-overlay.dts | 31 + arch/arm/boot/dts/qcom/sm6150-idp.dts | 23 + arch/arm/boot/dts/qcom/sm6150-idp.dtsi | 403 + .../sm6150-interposer-trinket-idp-overlay.dts | 29 + .../qcom/sm6150-interposer-trinket-idp.dts | 23 + .../qcom/sm6150-interposer-trinket-idp.dtsi | 130 + .../sm6150-interposer-trinket-qrd-overlay.dts | 23 + .../qcom/sm6150-interposer-trinket-qrd.dts | 23 + .../qcom/sm6150-interposer-trinket-qrd.dtsi | 182 + .../dts/qcom/sm6150-interposer-trinket.dts | 22 + .../dts/qcom/sm6150-interposer-trinket.dtsi | 54 + arch/arm/boot/dts/qcom/sm6150-ion.dtsi | 68 + .../boot/dts/qcom/sm6150-lpi.dtsi} | 260 +- arch/arm/boot/dts/qcom/sm6150-pinctrl.dtsi | 2263 +++ arch/arm/boot/dts/qcom/sm6150-pm.dtsi | 163 + .../sm6150-pm6125-interposer-trinket.dtsi | 721 + arch/arm/boot/dts/qcom/sm6150-qrd-overlay.dts | 67 + arch/arm/boot/dts/qcom/sm6150-qrd.dts | 22 + arch/arm/boot/dts/qcom/sm6150-qrd.dtsi | 291 + arch/arm/boot/dts/qcom/sm6150-qupv3.dtsi | 503 + arch/arm/boot/dts/qcom/sm6150-regulator.dtsi | 762 + .../arm/boot/dts/qcom/sm6150-rumi-overlay.dts | 26 + arch/arm/boot/dts/qcom/sm6150-rumi.dts | 23 + arch/arm/boot/dts/qcom/sm6150-rumi.dtsi | 206 + .../arm/boot/dts/qcom/sm6150-sde-display.dtsi | 548 + arch/arm/boot/dts/qcom/sm6150-sde-pll.dtsi | 83 + .../boot/dts/qcom/sm6150-sde.dtsi} | 389 +- .../boot/dts/qcom/sm6150-slpi-pinctrl.dtsi | 461 + .../boot/dts/qcom/sm6150-stub-regulator.dtsi | 345 + .../boot/dts/qcom/sm6150-thermal-overlay.dtsi | 182 + arch/arm/boot/dts/qcom/sm6150-thermal.dtsi | 2087 +++ arch/arm/boot/dts/qcom/sm6150-usb.dtsi | 436 + .../boot/dts/qcom/sm6150-usbc-idp-overlay.dts | 31 + arch/arm/boot/dts/qcom/sm6150-usbc-idp.dts | 23 + arch/arm/boot/dts/qcom/sm6150-usbc-idp.dtsi | 19 + .../qcom/sm6150-usbc-minidp-idp-overlay.dts | 32 + .../boot/dts/qcom/sm6150-usbc-minidp-idp.dts | 28 + arch/arm/boot/dts/qcom/sm6150-vidc.dtsi | 109 + arch/arm/boot/dts/qcom/sm6150-wcd.dtsi | 168 + arch/arm/boot/dts/qcom/sm6150.dts | 22 + arch/arm/boot/dts/qcom/sm6150.dtsi | 3245 ++++ .../arm/boot/dts/qcom/sm6150p-idp-overlay.dts | 31 + arch/arm/boot/dts/qcom/sm6150p-idp.dts | 22 + .../arm/boot/dts/qcom/sm6150p-qrd-overlay.dts | 26 + arch/arm/boot/dts/qcom/sm6150p-qrd.dts | 22 + arch/arm/boot/dts/qcom/sm6150p.dts | 22 + arch/arm/boot/dts/qcom/sm6150p.dtsi | 19 + .../boot/dts/qcom/sm8150-audio-overlay.dtsi | 355 + arch/arm/boot/dts/qcom/sm8150-audio.dtsi | 183 + arch/arm/boot/dts/qcom/sm8150-bus.dtsi | 2180 +++ .../dts/qcom/sm8150-camera-sensor-cdp.dtsi | 775 + .../dts/qcom/sm8150-camera-sensor-hdk.dtsi | 425 + .../dts/qcom/sm8150-camera-sensor-mtp.dtsi | 780 + .../dts/qcom/sm8150-camera-sensor-qrd.dtsi | 415 + arch/arm/boot/dts/qcom/sm8150-camera.dtsi | 1248 ++ .../dts/qcom/sm8150-cdp-audio-overlay.dtsi | 19 + arch/arm/boot/dts/qcom/sm8150-cdp-overlay.dts | 32 + arch/arm/boot/dts/qcom/sm8150-cdp.dts | 22 + arch/arm/boot/dts/qcom/sm8150-cdp.dtsi | 663 + arch/arm/boot/dts/qcom/sm8150-coresight.dtsi | 2795 ++++ arch/arm/boot/dts/qcom/sm8150-gdsc.dtsi | 267 + arch/arm/boot/dts/qcom/sm8150-gpu-v2.dtsi | 47 + arch/arm/boot/dts/qcom/sm8150-gpu.dtsi | 404 + arch/arm/boot/dts/qcom/sm8150-hdk-overlay.dts | 143 + arch/arm/boot/dts/qcom/sm8150-hdk.dts | 22 + arch/arm/boot/dts/qcom/sm8150-hdk.dtsi | 101 + arch/arm/boot/dts/qcom/sm8150-ion.dtsi | 74 + arch/arm/boot/dts/qcom/sm8150-mhi.dtsi | 1097 ++ .../dts/qcom/sm8150-mtp-audio-overlay.dtsi | 18 + arch/arm/boot/dts/qcom/sm8150-mtp-overlay.dts | 32 + arch/arm/boot/dts/qcom/sm8150-mtp.dts | 22 + arch/arm/boot/dts/qcom/sm8150-mtp.dtsi | 686 + arch/arm/boot/dts/qcom/sm8150-npu.dtsi | 204 + .../qcom/sm8150-oem-camera-guacamoleb.dtsi | 889 ++ .../boot/dts/qcom/sm8150-oem-camera-ov.dtsi | 854 + .../boot/dts/qcom/sm8150-oem-camera-t0.dtsi | 1055 ++ .../boot/dts/qcom/sm8150-oem-camera-v2.dtsi | 1035 ++ arch/arm/boot/dts/qcom/sm8150-oem-camera.dtsi | 968 ++ arch/arm/boot/dts/qcom/sm8150-oem.dtsi | 1340 ++ arch/arm/boot/dts/qcom/sm8150-pcie.dtsi | 824 + arch/arm/boot/dts/qcom/sm8150-pinctrl.dtsi | 4577 ++++++ arch/arm/boot/dts/qcom/sm8150-pm.dtsi | 122 + .../boot/dts/qcom/sm8150-pmic-overlay.dtsi | 145 + .../dts/qcom/sm8150-qrd-audio-overlay.dtsi | 57 + .../boot/dts/qcom/sm8150-qrd-dvt-overlay.dts | 28 + arch/arm/boot/dts/qcom/sm8150-qrd-dvt.dtsi | 29 + arch/arm/boot/dts/qcom/sm8150-qrd-overlay.dts | 28 + arch/arm/boot/dts/qcom/sm8150-qrd.dts | 22 + arch/arm/boot/dts/qcom/sm8150-qrd.dtsi | 687 + arch/arm/boot/dts/qcom/sm8150-qupv3.dtsi | 1081 ++ arch/arm/boot/dts/qcom/sm8150-regulator.dtsi | 1001 ++ .../arm/boot/dts/qcom/sm8150-rumi-overlay.dts | 27 + arch/arm/boot/dts/qcom/sm8150-rumi.dts | 23 + arch/arm/boot/dts/qcom/sm8150-rumi.dtsi | 163 + .../arm/boot/dts/qcom/sm8150-sde-display.dtsi | 949 ++ arch/arm/boot/dts/qcom/sm8150-sde-pll.dtsi | 96 + arch/arm/boot/dts/qcom/sm8150-sde.dtsi | 691 + .../qcom/sm8150-sdx50-camera-sensor-qrd.dtsi | 415 + .../dts/qcom/sm8150-sdx50m-audio-overlay.dtsi | 20 + .../dts/qcom/sm8150-sdx50m-cdp-overlay.dts | 31 + .../sm8150-sdx50m-mtp-2.5k-panel-overlay.dts | 66 + .../dts/qcom/sm8150-sdx50m-mtp-overlay.dts | 31 + .../dts/qcom/sm8150-sdx50m-qrd-overlay.dts | 32 + arch/arm/boot/dts/qcom/sm8150-sdx50m-qrd.dtsi | 733 + arch/arm/boot/dts/qcom/sm8150-sdx50m.dtsi | 605 + .../qcom/sm8150-sdxprairie-cdp-overlay.dts | 62 + .../qcom/sm8150-sdxprairie-mtp-overlay.dts | 64 + .../qcom/sm8150-sdxprairie-v2-cdp-overlay.dts | 66 + .../qcom/sm8150-sdxprairie-v2-mtp-overlay.dts | 66 + .../boot/dts/qcom/sm8150-sdxprairie-v2.dtsi | 18 + arch/arm/boot/dts/qcom/sm8150-sdxprairie.dtsi | 581 + .../boot/dts/qcom/sm8150-slpi-pinctrl.dtsi | 198 + arch/arm/boot/dts/qcom/sm8150-smp2p.dtsi | 154 + .../boot/dts/qcom/sm8150-thermal-overlay.dtsi | 302 + arch/arm/boot/dts/qcom/sm8150-thermal.dtsi | 1274 ++ arch/arm/boot/dts/qcom/sm8150-usb.dtsi | 586 + arch/arm/boot/dts/qcom/sm8150-v2-camera.dtsi | 340 + arch/arm/boot/dts/qcom/sm8150-v2-cdp.dts | 22 + arch/arm/boot/dts/qcom/sm8150-v2-mtp.dts | 22 + arch/arm/boot/dts/qcom/sm8150-v2-qrd-dvt.dts | 22 + arch/arm/boot/dts/qcom/sm8150-v2-qrd.dts | 22 + arch/arm/boot/dts/qcom/sm8150-v2-rumi.dts | 23 + arch/arm/boot/dts/qcom/sm8150-v2.dts | 22 + arch/arm/boot/dts/qcom/sm8150-v2.dtsi | 1358 ++ arch/arm/boot/dts/qcom/sm8150-vidc.dtsi | 139 + arch/arm/boot/dts/qcom/sm8150-wcd.dtsi | 235 + arch/arm/boot/dts/qcom/sm8150.dts | 22 + arch/arm/boot/dts/qcom/sm8150.dtsi | 4164 +++++ arch/arm/boot/dts/qcom/sm8150p-cdp.dts | 22 + arch/arm/boot/dts/qcom/sm8150p-hdk.dts | 22 + arch/arm/boot/dts/qcom/sm8150p-mtp.dts | 22 + arch/arm/boot/dts/qcom/sm8150p-qrd.dts | 22 + arch/arm/boot/dts/qcom/sm8150p-v2-cdp.dts | 22 + arch/arm/boot/dts/qcom/sm8150p-v2-mtp.dts | 22 + arch/arm/boot/dts/qcom/sm8150p-v2-qrd.dts | 22 + arch/arm/boot/dts/qcom/sm8150p-v2.dts | 22 + arch/arm/boot/dts/qcom/sm8150p-v2.dtsi | 19 + arch/arm/boot/dts/qcom/sm8150p.dts | 22 + arch/arm/boot/dts/qcom/sm8150p.dtsi | 19 + arch/arm/boot/dts/qcom/smb1355.dtsi | 56 + arch/arm/boot/dts/qcom/smb1390.dtsi | 72 + .../dts/qcom/spi-panel-st7789v2-qvga-cmd.dtsi | 50 + .../boot/dts/qcom/trinket-audio-overlay.dtsi | 463 + .../boot/dts/qcom/trinket-audio.dtsi} | 82 +- arch/arm/boot/dts/qcom/trinket-bus.dtsi | 1117 ++ .../dts/qcom/trinket-camera-sensor-idp.dtsi | 281 + .../dts/qcom/trinket-camera-sensor-qrd.dtsi | 230 + arch/arm/boot/dts/qcom/trinket-camera.dtsi | 803 + arch/arm/boot/dts/qcom/trinket-coresight.dtsi | 2316 +++ .../boot/dts/qcom/trinket-dp-idp-overlay.dts | 51 + arch/arm/boot/dts/qcom/trinket-dp-idp.dts | 44 + .../trinket-external-codec-idp-overlay.dts | 31 + .../dts/qcom/trinket-external-codec-idp.dts | 24 + arch/arm/boot/dts/qcom/trinket-gdsc.dtsi | 143 + arch/arm/boot/dts/qcom/trinket-gpu.dtsi | 279 + .../arm/boot/dts/qcom/trinket-idp-overlay.dts | 30 + arch/arm/boot/dts/qcom/trinket-idp.dts | 23 + arch/arm/boot/dts/qcom/trinket-idp.dtsi | 383 + arch/arm/boot/dts/qcom/trinket-ion.dtsi | 62 + arch/arm/boot/dts/qcom/trinket-pinctrl.dtsi | 1851 +++ arch/arm/boot/dts/qcom/trinket-pm.dtsi | 224 + .../arm/boot/dts/qcom/trinket-qrd-overlay.dts | 24 + arch/arm/boot/dts/qcom/trinket-qrd.dts | 23 + arch/arm/boot/dts/qcom/trinket-qrd.dtsi | 392 + arch/arm/boot/dts/qcom/trinket-qupv3.dtsi | 462 + arch/arm/boot/dts/qcom/trinket-regulator.dtsi | 372 + .../boot/dts/qcom/trinket-rumi-overlay.dts} | 28 +- arch/arm/boot/dts/qcom/trinket-rumi.dts | 24 + arch/arm/boot/dts/qcom/trinket-rumi.dtsi | 187 + .../boot/dts/qcom/trinket-sde-display.dtsi | 329 + arch/arm/boot/dts/qcom/trinket-sde-pll.dtsi | 85 + arch/arm/boot/dts/qcom/trinket-sde.dtsi | 563 + .../boot/dts/qcom/trinket-stub-regulator.dtsi | 280 + .../trinket-tasha-codec-audio-overlay.dtsi | 96 + .../boot/dts/qcom/trinket-tasha-codec.dtsi | 170 + .../dts/qcom/trinket-thermal-overlay.dtsi | 449 + arch/arm/boot/dts/qcom/trinket-thermal.dtsi | 2015 +++ arch/arm/boot/dts/qcom/trinket-usb.dtsi | 324 + ...rinket-usbc-external-codec-idp-overlay.dts | 29 + .../qcom/trinket-usbc-external-codec-idp.dts | 22 + .../dts/qcom/trinket-usbc-idp-overlay.dts | 30 + arch/arm/boot/dts/qcom/trinket-usbc-idp.dts | 23 + arch/arm/boot/dts/qcom/trinket-usbc-idp.dtsi | 19 + arch/arm/boot/dts/qcom/trinket-vidc.dtsi | 110 + .../dts/qcom/trinket-wcd.dtsi} | 34 +- arch/arm/boot/dts/qcom/trinket.dts | 22 + arch/arm/boot/dts/qcom/trinket.dtsi | 3147 ++++ arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts | 64 +- arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts | 64 +- arch/arm/boot/dts/sun8i-a33-et-q8-v1.6.dts | 51 +- arch/arm/boot/dts/sun8i-a33-ippo-q8h-v1.2.dts | 51 +- arch/arm/boot/install.sh | 0 arch/arm/configs/sa515m-perf_defconfig | 1 - arch/arm/configs/sa515m_defconfig | 1 - ...fconfig => sdxprairie-auto-perf_defconfig} | 6 - ...5m_defconfig => sdxprairie-auto_defconfig} | 6 - arch/arm/configs/sdxprairie-perf_defconfig | 465 +- arch/arm/configs/sdxprairie_defconfig | 494 +- arch/arm/configs/vendor/qcs403-perf_defconfig | 369 - arch/arm/configs/vendor/qcs405-perf_defconfig | 1 - arch/arm/configs/vendor/qcs405_defconfig | 1 - .../vendor/sdxprairie-auto-perf_defconfig} | 393 +- ...03_defconfig => sdxprairie-auto_defconfig} | 389 +- .../configs/vendor/sdxprairie-perf_defconfig | 5 - arch/arm/configs/vendor/sdxprairie_defconfig | 5 - arch/arm/mach-qcom/Kconfig | 38 +- arch/arm/mach-qcom/Makefile | 1 - arch/arm/mm/dma-mapping.c | 8 +- arch/arm/tools/syscallhdr.sh | 0 arch/arm/tools/syscallnr.sh | 0 arch/arm/tools/syscalltbl.sh | 0 arch/arm64/Kconfig | 11 +- arch/arm64/Kconfig.platforms | 10 - arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi | 443 +- arch/arm64/boot/dts/qcom/Makefile | 95 +- .../dts/qcom/OP-fg-batterydata-3700mah.dtsi | 144 + .../dts/qcom/OP-fg-batterydata-3800mah.dtsi | 144 + .../dts/qcom/OP-fg-batterydata-4000mah.dtsi | 145 + .../dts/qcom/OP-fg-batterydata-4085mah.dtsi | 145 + arch/arm64/boot/dts/qcom/atoll-coresight.dtsi | 2 +- arch/arm64/boot/dts/qcom/atoll-gdsc.dtsi | 30 +- .../arm64/boot/dts/qcom/atoll-idp-overlay.dts | 5 - arch/arm64/boot/dts/qcom/atoll-idp.dts | 4 - arch/arm64/boot/dts/qcom/atoll-idp.dtsi | 190 - arch/arm64/boot/dts/qcom/atoll-ion.dtsi | 15 - arch/arm64/boot/dts/qcom/atoll-pinctrl.dtsi | 1206 -- arch/arm64/boot/dts/qcom/atoll-qrd.dtsi | 176 - arch/arm64/boot/dts/qcom/atoll-qupv3.dtsi | 525 +- arch/arm64/boot/dts/qcom/atoll-rumi.dtsi | 25 +- .../boot/dts/qcom/atoll-sde-display.dtsi | 152 - arch/arm64/boot/dts/qcom/atoll-thermal.dtsi | 406 - arch/arm64/boot/dts/qcom/atoll-usb.dtsi | 6 +- arch/arm64/boot/dts/qcom/atoll-vidc.dtsi | 2 +- .../qcom/atoll-wcd937x-idp-audio-overlay.dtsi | 118 - arch/arm64/boot/dts/qcom/atoll.dtsi | 1113 +- .../qcom/dsi-panel-samsung_oneplus_dsc.dtsi | 2665 ++++ .../qcom/dsi-panel-samsung_s6e3fc2x01.dtsi | 435 + .../dsi-panel-samsung_sofef00_m_video.dtsi | 103 + .../qcom/dsi-panel-sharp-qsync-fhd-cmd.dtsi | 367 - .../qcom/dsi-panel-sharp-qsync-fhd-video.dtsi | 128 - .../qcom/dsi-panel-sharp-qsync-wqhd-cmd.dtsi | 470 - .../dsi-panel-sharp-qsync-wqhd-video.dtsi | 131 - .../boot/dts/qcom/guacamole-overlay-dvt.dts | 43 + .../boot/dts/qcom/guacamole-overlay-evt1.dts | 39 + .../qcom/guacamole-overlay-evt2-second.dts | 40 + .../boot/dts/qcom/guacamole-overlay-evt2.dts | 40 + .../boot/dts/qcom/guacamole-overlay-evt3.dts | 41 + .../boot/dts/qcom/guacamole-overlay-pvt.dts | 44 + .../boot/dts/qcom/guacamole-overlay-t0.dts | 39 + .../dts/qcom/guacamole-sdx50m-overlay-dvt.dts | 46 + .../qcom/guacamole-sdx50m-overlay-evt1.dts | 44 + .../qcom/guacamole-sdx50m-overlay-evt2.dts | 45 + .../dts/qcom/guacamole-sdx50m-overlay-pvt.dts | 47 + .../dts/qcom/guacamole-sdx50m-overlay-t0.dts | 43 + arch/arm64/boot/dts/qcom/guacamole.dtsi | 166 + arch/arm64/boot/dts/qcom/guacamole_dvt.dtsi | 1 + arch/arm64/boot/dts/qcom/guacamole_evt1.dtsi | 2 + arch/arm64/boot/dts/qcom/guacamole_evt2.dtsi | 2 + arch/arm64/boot/dts/qcom/guacamole_evt3.dtsi | 2 + arch/arm64/boot/dts/qcom/guacamole_pvt.dtsi | 1 + .../arm64/boot/dts/qcom/guacamole_sdx50m.dtsi | 17 + .../arm64/boot/dts/qcom/guacamole_sm8150.dtsi | 8 + arch/arm64/boot/dts/qcom/guacamole_t0.dtsi | 99 + .../boot/dts/qcom/guacamoleb-overlay-dvt.dts | 39 + .../boot/dts/qcom/guacamoleb-overlay-evt.dts | 39 + .../boot/dts/qcom/guacamoleb-overlay-pvt.dts | 39 + .../boot/dts/qcom/guacamoleb-overlay-t0.dts | 39 + arch/arm64/boot/dts/qcom/guacamoleb.dtsi | 490 + arch/arm64/boot/dts/qcom/guacamoleb_dvt.dtsi | 1 + arch/arm64/boot/dts/qcom/guacamoleb_evt.dtsi | 1 + arch/arm64/boot/dts/qcom/guacamoleb_pvt.dtsi | 1 + .../boot/dts/qcom/guacamoleb_sm8150.dtsi | 7 + arch/arm64/boot/dts/qcom/guacamoleb_t0.dtsi | 4 + .../qcom/guacamoles-sdx50m-overlay-dvt.dts | 45 + .../qcom/guacamoles-sdx50m-overlay-evt.dts | 45 + .../qcom/guacamoles-sdx50m-overlay-pvt.dts | 45 + .../dts/qcom/guacamoles-sdx50m-overlay-t0.dts | 44 + .../boot/dts/qcom/guacamoles_sdx50m.dtsi | 11 + .../boot/dts/qcom/guacamoles_sdx50m_dvt.dtsi | 2 + .../boot/dts/qcom/guacamoles_sdx50m_evt.dtsi | 1 + .../boot/dts/qcom/guacamoles_sdx50m_pvt.dtsi | 1 + .../boot/dts/qcom/guacamoles_sdx50m_t0.dtsi | 1 + .../boot/dts/qcom/msm-arm-smmu-atoll.dtsi | 102 - .../boot/dts/qcom/msm-arm-smmu-trinket.dtsi | 1 + arch/arm64/boot/dts/qcom/msm-audio-lpass.dtsi | 61 +- arch/arm64/boot/dts/qcom/pm6150.dtsi | 62 +- arch/arm64/boot/dts/qcom/pm6150l.dtsi | 62 +- arch/arm64/boot/dts/qcom/pm6155-vm.dtsi | 49 - arch/arm64/boot/dts/qcom/pm8150-vm.dtsi | 77 - arch/arm64/boot/dts/qcom/pm8150.dtsi | 5 +- arch/arm64/boot/dts/qcom/pm8150b.dtsi | 83 +- arch/arm64/boot/dts/qcom/pm8150l.dtsi | 60 +- arch/arm64/boot/dts/qcom/pmi632.dtsi | 68 +- arch/arm64/boot/dts/qcom/qcs401.dtsi | 28 +- arch/arm64/boot/dts/qcom/qcs403-iot-sku1.dts | 57 +- arch/arm64/boot/dts/qcom/qcs403-iot-sku2.dts | 55 + arch/arm64/boot/dts/qcom/qcs403-iot-sku3.dts | 53 + arch/arm64/boot/dts/qcom/qcs403-iot-sku4.dts | 53 + arch/arm64/boot/dts/qcom/qcs403.dtsi | 57 +- .../boot/dts/qcom/qcs405-linear-pca9956.dtsi | 4 + arch/arm64/boot/dts/qcom/qcs405-mhi.dtsi | 716 + arch/arm64/boot/dts/qcom/qcs405-pcie.dtsi | 6 +- .../arm64/boot/dts/qcom/qcs405-va-bolero.dtsi | 2 +- arch/arm64/boot/dts/qcom/qcs405.dtsi | 8 + .../qg-batterydata-atl466271_3300mAh.dtsi | 1054 -- arch/arm64/boot/dts/qcom/quin-vm-common.dtsi | 22 - .../boot/dts/qcom/sa515m-ccard-pcie-ep.dts | 4 - arch/arm64/boot/dts/qcom/sa515m-ccard.dtsi | 81 +- arch/arm64/boot/dts/qcom/sa6155-adp-air.dtsi | 4 +- arch/arm64/boot/dts/qcom/sa6155-adp-star.dtsi | 4 +- arch/arm64/boot/dts/qcom/sa6155-pmic.dtsi | 8 +- arch/arm64/boot/dts/qcom/sa6155.dtsi | 56 - arch/arm64/boot/dts/qcom/sa6155p-vm-usb.dtsi | 16 +- arch/arm64/boot/dts/qcom/sa6155p-vm.dts | 4 - arch/arm64/boot/dts/qcom/sa6155p-vm.dtsi | 152 +- arch/arm64/boot/dts/qcom/sa6155p.dtsi | 56 - arch/arm64/boot/dts/qcom/sa8155-vm-audio.dtsi | 36 +- .../boot/dts/qcom/sa8155-vm-pinctrl.dtsi | 447 - arch/arm64/boot/dts/qcom/sa8155-vm-usb.dtsi | 20 +- arch/arm64/boot/dts/qcom/sa8155-vm.dtsi | 244 +- arch/arm64/boot/dts/qcom/sa8155.dtsi | 56 - arch/arm64/boot/dts/qcom/sa8195-pmic.dtsi | 40 +- arch/arm64/boot/dts/qcom/sa8195-vm.dts | 8 - arch/arm64/boot/dts/qcom/sa8195-vm.dtsi | 112 +- .../arm64/boot/dts/qcom/sa8195p-adp-star.dtsi | 53 - arch/arm64/boot/dts/qcom/sa8195p.dtsi | 223 +- arch/arm64/boot/dts/qcom/sdmmagpie-idp.dtsi | 42 - .../boot/dts/qcom/sdmmagpie-sde-display.dtsi | 139 +- .../dts/qcom/sdmmagpie-thermal-overlay.dtsi | 31 +- arch/arm64/boot/dts/qcom/sdmmagpie-usb.dtsi | 3 - .../boot/dts/qcom/sdmshrike-pinctrl.dtsi | 71 - arch/arm64/boot/dts/qcom/sdmshrike-v2.dtsi | 131 - arch/arm64/boot/dts/qcom/sdmshrike.dtsi | 5 - .../boot/dts/qcom/sdxprairie-pcie-ep-mtp.dtsi | 4 - .../boot/dts/qcom/sdxprairie-pinctrl.dtsi | 27 - .../boot/dts/qcom/sdxprairie-regulator.dtsi | 9 - arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi | 1 - arch/arm64/boot/dts/qcom/sdxprairie.dtsi | 13 +- arch/arm64/boot/dts/qcom/sm6150-pinctrl.dtsi | 8 +- .../boot/dts/qcom/sm6150-thermal-overlay.dtsi | 31 +- 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.../vfe_hw/vfe_top/cam_vfe_camif_ver2.c | 31 +- .../isp_hw/vfe_hw/vfe_top/cam_vfe_fe_ver1.c | 14 +- .../isp_hw/vfe_hw/vfe_top/cam_vfe_rdi.c | 10 +- .../isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c | 90 +- .../msm/camera/cam_jpeg/cam_jpeg_context.c | 4 +- .../camera/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c | 25 +- .../jpeg_hw/jpeg_dma_hw/jpeg_dma_core.c | 3 +- .../jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c | 36 +- .../msm/camera/cam_lrme/cam_lrme_context.c | 4 +- .../cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c | 16 +- .../lrme_hw_mgr/lrme_hw/cam_lrme_hw_soc.c | 3 +- .../platform/msm/camera/cam_req_mgr/Makefile | 1 - .../msm/camera/cam_req_mgr/cam_mem_mgr.c | 75 +- .../msm/camera/cam_req_mgr/cam_req_mgr_core.c | 622 +- .../msm/camera/cam_req_mgr/cam_req_mgr_core.h | 26 +- .../msm/camera/cam_req_mgr/cam_req_mgr_dev.c | 37 +- .../cam_req_mgr/cam_req_mgr_interface.h | 4 +- .../msm/camera/cam_req_mgr/cam_req_mgr_util.c | 20 +- .../msm/camera/cam_req_mgr/cam_req_mgr_util.h | 4 +- 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.../include-prefixes/arm/omap3-cm-t3730.dts | 98 + .../include-prefixes/arm/omap3-cm-t3x.dtsi | 324 + .../include-prefixes/arm/omap3-cm-t3x30.dtsi | 131 + .../arm/omap3-cpu-thermal.dtsi | 20 + .../arm/omap3-devkit8000-common.dtsi | 370 + .../arm/omap3-devkit8000-lcd-common.dtsi | 73 + .../arm/omap3-devkit8000-lcd43.dts | 37 + .../arm/omap3-devkit8000-lcd70.dts | 37 + .../include-prefixes/arm/omap3-devkit8000.dts | 19 + .../include-prefixes/arm/omap3-evm-37xx.dts | 317 + .../arm/omap3-evm-common.dtsi | 194 + .../dtc/include-prefixes/arm/omap3-evm.dts | 21 + .../dtc/include-prefixes/arm/omap3-gta04.dtsi | 621 + .../include-prefixes/arm/omap3-gta04a3.dts | 48 + .../include-prefixes/arm/omap3-gta04a4.dts | 13 + .../include-prefixes/arm/omap3-gta04a5.dts | 17 + .../include-prefixes/arm/omap3-ha-common.dtsi | 88 + .../dtc/include-prefixes/arm/omap3-ha-lcd.dts | 165 + scripts/dtc/include-prefixes/arm/omap3-ha.dts | 28 + .../dtc/include-prefixes/arm/omap3-igep.dtsi | 250 + .../arm/omap3-igep0020-common.dtsi | 263 + .../arm/omap3-igep0020-rev-f.dts | 54 + .../include-prefixes/arm/omap3-igep0020.dts | 50 + .../arm/omap3-igep0030-common.dtsi | 105 + .../arm/omap3-igep0030-rev-g.dts | 76 + .../include-prefixes/arm/omap3-igep0030.dts | 62 + .../dtc/include-prefixes/arm/omap3-ldp.dts | 308 + .../arm/omap3-lilly-a83x.dtsi | 462 + .../arm/omap3-lilly-dbb056.dts | 170 + scripts/dtc/include-prefixes/arm/omap3-n9.dts | 73 + .../dtc/include-prefixes/arm/omap3-n900.dts | 1125 ++ .../include-prefixes/arm/omap3-n950-n9.dtsi | 487 + .../dtc/include-prefixes/arm/omap3-n950.dts | 187 + .../arm/omap3-overo-alto35-common.dtsi | 78 + .../arm/omap3-overo-alto35.dts | 22 + .../arm/omap3-overo-base.dtsi | 276 + .../arm/omap3-overo-chestnut43-common.dtsi | 68 + .../arm/omap3-overo-chestnut43.dts | 38 + .../arm/omap3-overo-common-dvi.dtsi | 111 + .../arm/omap3-overo-common-lcd35.dtsi | 166 + .../arm/omap3-overo-common-lcd43.dtsi | 178 + .../arm/omap3-overo-common-peripherals.dtsi | 95 + .../arm/omap3-overo-gallop43-common.dtsi | 58 + .../arm/omap3-overo-gallop43.dts | 38 + .../arm/omap3-overo-palo35-common.dtsi | 53 + .../arm/omap3-overo-palo35.dts | 37 + .../arm/omap3-overo-palo43-common.dtsi | 54 + .../arm/omap3-overo-palo43.dts | 38 + .../arm/omap3-overo-storm-alto35.dts | 21 + .../arm/omap3-overo-storm-chestnut43.dts | 38 + .../arm/omap3-overo-storm-gallop43.dts | 38 + .../arm/omap3-overo-storm-palo35.dts | 37 + .../arm/omap3-overo-storm-palo43.dts | 38 + .../arm/omap3-overo-storm-summit.dts | 30 + .../arm/omap3-overo-storm-tobi.dts | 22 + .../arm/omap3-overo-storm-tobiduo.dts | 21 + .../arm/omap3-overo-storm.dtsi | 35 + .../arm/omap3-overo-summit-common.dtsi | 32 + .../arm/omap3-overo-summit.dts | 30 + .../arm/omap3-overo-tobi-common.dtsi | 40 + .../include-prefixes/arm/omap3-overo-tobi.dts | 22 + .../arm/omap3-overo-tobiduo-common.dtsi | 62 + .../arm/omap3-overo-tobiduo.dts | 21 + .../dtc/include-prefixes/arm/omap3-overo.dtsi | 34 + .../arm/omap3-pandora-1ghz.dts | 70 + .../arm/omap3-pandora-600mhz.dts | 65 + .../arm/omap3-pandora-common.dtsi | 690 + .../arm/omap3-panel-sharp-ls037v7dw01.dtsi | 72 + .../include-prefixes/arm/omap3-sb-t35.dtsi | 138 + .../include-prefixes/arm/omap3-sbc-t3517.dts | 76 + .../include-prefixes/arm/omap3-sbc-t3530.dts | 48 + .../include-prefixes/arm/omap3-sbc-t3730.dts | 44 + .../dtc/include-prefixes/arm/omap3-sniper.dts | 254 + .../include-prefixes/arm/omap3-tao3530.dtsi | 348 + .../include-prefixes/arm/omap3-thunder.dts | 129 + .../dtc/include-prefixes/arm/omap3-zoom3.dts | 234 + scripts/dtc/include-prefixes/arm/omap3.dtsi | 851 + .../dtc/include-prefixes/arm/omap3430-sdp.dts | 197 + .../arm/omap3430es1-clocks.dtsi | 208 + .../arm/omap34xx-omap36xx-clocks.dtsi | 268 + .../dtc/include-prefixes/arm/omap34xx.dtsi | 84 + ...map36xx-am35xx-omap3430es2plus-clocks.dtsi | 242 + .../include-prefixes/arm/omap36xx-clocks.dtsi | 110 + .../arm/omap36xx-omap3430es2plus-clocks.dtsi | 198 + .../dtc/include-prefixes/arm/omap36xx.dtsi | 123 + .../include-prefixes/arm/omap3xxx-clocks.dtsi | 1665 ++ .../arm/omap4-cpu-thermal.dtsi | 41 + .../arm/omap4-droid4-xt894.dts | 594 + .../arm/omap4-duovero-parlor.dts | 195 + .../include-prefixes/arm/omap4-duovero.dtsi | 269 + .../dtc/include-prefixes/arm/omap4-kc1.dts | 182 + .../include-prefixes/arm/omap4-panda-a4.dts | 20 + .../arm/omap4-panda-common.dtsi | 566 + .../include-prefixes/arm/omap4-panda-es.dts | 73 + .../dtc/include-prefixes/arm/omap4-panda.dts | 16 + .../arm/omap4-sdp-es23plus.dts | 17 + .../dtc/include-prefixes/arm/omap4-sdp.dts | 705 + .../arm/omap4-var-dvk-om44.dts | 71 + .../arm/omap4-var-om44customboard.dtsi | 235 + .../arm/omap4-var-som-om44-wlan.dtsi | 78 + .../arm/omap4-var-som-om44.dtsi | 346 + .../arm/omap4-var-stk-om44.dts | 17 + scripts/dtc/include-prefixes/arm/omap4.dtsi | 1046 ++ .../include-prefixes/arm/omap443x-clocks.dtsi | 18 + .../dtc/include-prefixes/arm/omap443x.dtsi | 78 + .../dtc/include-prefixes/arm/omap4460.dtsi | 97 + .../include-prefixes/arm/omap446x-clocks.dtsi | 27 + .../include-prefixes/arm/omap44xx-clocks.dtsi | 1633 ++ .../arm/omap5-board-common.dtsi | 749 + .../dtc/include-prefixes/arm/omap5-cm-t54.dts | 685 + .../arm/omap5-core-thermal.dtsi | 28 + .../arm/omap5-gpu-thermal.dtsi | 28 + .../include-prefixes/arm/omap5-igep0050.dts | 139 + .../include-prefixes/arm/omap5-sbc-t54.dts | 52 + .../dtc/include-prefixes/arm/omap5-uevm.dts | 203 + scripts/dtc/include-prefixes/arm/omap5.dtsi | 1141 ++ .../include-prefixes/arm/omap54xx-clocks.dtsi | 1396 ++ .../arm/orion5x-kuroboxpro.dts | 127 + .../arm/orion5x-lacie-d2-network.dts | 236 + .../orion5x-lacie-ethernet-disk-mini-v2.dts | 174 + .../arm/orion5x-linkstation-lschl.dts | 171 + .../arm/orion5x-linkstation-lsgl.dts | 91 + .../arm/orion5x-linkstation-lswtgl.dts | 151 + .../arm/orion5x-linkstation.dtsi | 180 + .../include-prefixes/arm/orion5x-lswsgl.dts | 276 + .../arm/orion5x-maxtor-shared-storage-2.dts | 178 + .../arm/orion5x-mv88f5181.dtsi | 49 + .../arm/orion5x-mv88f5182.dtsi | 45 + .../arm/orion5x-netgear-wnr854t.dts | 251 + .../arm/orion5x-rd88f5182-nas.dts | 177 + scripts/dtc/include-prefixes/arm/orion5x.dtsi | 241 + .../arm/owl-s500-guitar-bb-rev-b.dts | 26 + .../include-prefixes/arm/owl-s500-guitar.dtsi | 22 + .../dtc/include-prefixes/arm/owl-s500.dtsi | 186 + scripts/dtc/include-prefixes/arm/ox810se.dtsi | 338 + scripts/dtc/include-prefixes/arm/ox820.dtsi | 298 + .../include-prefixes/arm/picoxcell-pc3x2.dtsi | 249 + .../include-prefixes/arm/picoxcell-pc3x3.dtsi | 365 + .../arm/picoxcell-pc7302-pc3x2.dts | 86 + .../arm/picoxcell-pc7302-pc3x3.dts | 92 + scripts/dtc/include-prefixes/arm/pm9g45.dts | 173 + .../dtc/include-prefixes/arm/prima2-evb.dts | 37 + scripts/dtc/include-prefixes/arm/prima2.dtsi | 840 + .../include-prefixes/arm/pxa168-aspenite.dts | 38 + scripts/dtc/include-prefixes/arm/pxa168.dtsi | 158 + scripts/dtc/include-prefixes/arm/pxa25x.dtsi | 117 + scripts/dtc/include-prefixes/arm/pxa27x.dtsi | 181 + scripts/dtc/include-prefixes/arm/pxa2xx.dtsi | 152 + scripts/dtc/include-prefixes/arm/pxa3xx.dtsi | 256 + .../dtc/include-prefixes/arm/pxa910-dkb.dts | 175 + scripts/dtc/include-prefixes/arm/pxa910.dtsi | 175 + .../arm/qcom-apq8060-dragonboard.dts | 965 ++ .../qcom-apq8064-arrow-sd-600eval-pins.dtsi | 53 + .../arm/qcom-apq8064-arrow-sd-600eval.dts | 415 + .../arm/qcom-apq8064-asus-nexus7-flo.dts | 359 + .../arm/qcom-apq8064-cm-qs600.dts | 246 + .../arm/qcom-apq8064-ifc6410.dts | 381 + .../arm/qcom-apq8064-pins.dtsi | 325 + .../arm/qcom-apq8064-sony-xperia-yuga.dts | 402 + .../arm/qcom-apq8064-v2.0.dtsi | 2 + .../include-prefixes/arm/qcom-apq8064.dtsi | 1719 ++ .../arm/qcom-apq8074-dragonboard.dts | 346 + .../arm/qcom-apq8084-ifc6540.dts | 34 + .../include-prefixes/arm/qcom-apq8084-mtp.dts | 23 + .../include-prefixes/arm/qcom-apq8084.dtsi | 523 + .../arm/qcom-ipq4019-ap.dk01.1-c1.dts | 22 + .../arm/qcom-ipq4019-ap.dk01.1.dtsi | 105 + .../include-prefixes/arm/qcom-ipq4019.dtsi | 380 + .../arm/qcom-ipq8064-ap148.dts | 103 + .../arm/qcom-ipq8064-v1.0.dtsi | 2 + .../include-prefixes/arm/qcom-ipq8064.dtsi | 370 + .../arm/qcom-mdm9615-wp8548-mangoh-green.dts | 281 + .../arm/qcom-mdm9615-wp8548.dtsi | 170 + .../include-prefixes/arm/qcom-mdm9615.dtsi | 557 + .../arm/qcom-msm8660-surf.dts | 78 + .../include-prefixes/arm/qcom-msm8660.dtsi | 548 + .../include-prefixes/arm/qcom-msm8960-cdp.dts | 354 + .../include-prefixes/arm/qcom-msm8960.dtsi | 325 + .../qcom-msm8974-lge-nexus5-hammerhead.dts | 294 + .../arm/qcom-msm8974-sony-xperia-honami.dts | 460 + .../include-prefixes/arm/qcom-msm8974.dtsi | 1134 ++ .../dtc/include-prefixes/arm/qcom-pm8841.dtsi | 37 + .../dtc/include-prefixes/arm/qcom-pm8941.dtsi | 210 + .../include-prefixes/arm/qcom-pma8084.dtsi | 119 + .../dtc/include-prefixes/arm/qcom/Makefile | 344 + .../arm/qcom/OP-fg-batterydata-3700mah.dtsi | 144 + .../arm/qcom/OP-fg-batterydata-3800mah.dtsi | 144 + .../arm/qcom/OP-fg-batterydata-4000mah.dtsi | 145 + .../arm/qcom/OP-fg-batterydata-4085mah.dtsi | 145 + .../arm/qcom/apq8016-sbc-pmic-pins.dtsi | 55 + .../arm/qcom/apq8016-sbc-soc-pins.dtsi | 89 + .../include-prefixes/arm/qcom/apq8016-sbc.dts | 21 + .../arm/qcom/apq8016-sbc.dtsi | 502 + .../arm/qcom/apq8096-db820c-pins.dtsi | 39 + .../arm/qcom/apq8096-db820c-pmic-pins.dtsi | 52 + .../arm/qcom/apq8096-db820c.dts | 21 + .../arm/qcom/apq8096-db820c.dtsi | 307 + .../arm/qcom/atoll-coresight.dtsi | 2979 ++++ .../include-prefixes/arm/qcom/atoll-gdsc.dtsi | 162 + .../arm/qcom/atoll-idp-overlay.dts | 6 +- .../include-prefixes/arm/qcom/atoll-idp.dts | 5 +- .../include-prefixes/arm/qcom/atoll-idp.dtsi | 107 + .../include-prefixes/arm/qcom/atoll-ion.dtsi | 41 + .../arm/qcom/atoll-pinctrl.dtsi | 250 + .../include-prefixes/arm/qcom/atoll-pm.dtsi | 170 + .../arm/qcom/atoll-qrd-overlay.dts | 23 + .../include-prefixes/arm/qcom/atoll-qrd.dts | 22 + .../include-prefixes/arm/qcom/atoll-qrd.dtsi | 14 + .../arm/qcom/atoll-qupv3.dtsi | 62 + .../arm/qcom/atoll-rumi-overlay.dts | 25 + .../include-prefixes/arm/qcom/atoll-rumi.dts | 22 + .../include-prefixes/arm/qcom/atoll-rumi.dtsi | 144 + .../arm/qcom/atoll-stub-regulator.dtsi | 405 + .../arm/qcom/atoll-thermal.dtsi | 621 + .../include-prefixes/arm/qcom/atoll-usb.dtsi | 372 + .../include-prefixes/arm/qcom/atoll-vidc.dtsi | 106 + .../dtc/include-prefixes/arm/qcom/atoll.dts | 22 + .../dtc/include-prefixes/arm/qcom/atoll.dtsi | 2486 +++ .../arm/qcom/dm-verity-boot.dtsi | 28 + .../arm/qcom/dsi-panel-ext-bridge-1080p.dtsi | 52 + .../qcom/dsi-panel-ext-bridge-hdmi-1080p.dtsi | 52 + ...l-hx83112a-truly-singlemipi-fhd-video.dtsi | 159 + .../qcom/dsi-panel-hx8394d-720p-video.dtsi | 99 + ...dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi | 247 + ...i-panel-nt35597-truly-dsc-wqxga-video.dtsi | 233 + ...anel-nt35597-truly-dualmipi-wqxga-cmd.dtsi | 226 + ...el-nt35597-truly-dualmipi-wqxga-video.dtsi | 213 + .../dsi-panel-nt35695b-truly-fhd-cmd.dtsi | 188 + .../dsi-panel-nt35695b-truly-fhd-video.dtsi | 184 + .../dsi-panel-nt36672-truly-fhd-video.dtsi | 282 + ...panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi | 87 + ...nel-rm69298-truly-amoled-fhd-plus-cmd.dtsi | 330 + ...l-rm69298-truly-amoled-fhd-plus-video.dtsi | 330 + ...m69299-visionox-amoled-fhd-plus-video.dtsi | 75 + ...anel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi | 141 + .../arm/qcom/dsi-panel-samsung_findx_dsc.dtsi | 177 + .../qcom/dsi-panel-samsung_oneplus_dsc.dtsi | 2665 ++++ .../qcom/dsi-panel-samsung_s6e3fc2x01.dtsi | 435 + .../dsi-panel-samsung_sofef00_m_video.dtsi | 103 + ...-panel-samsung_sofef03f_m_fhd_dsc_cmd.dtsi | 848 + .../arm/qcom/dsi-panel-sharp-1080p-cmd.dtsi | 86 + .../arm/qcom/dsi-panel-sharp-dsc-4k-cmd.dtsi | 103 + .../qcom/dsi-panel-sharp-dsc-4k-video.dtsi | 96 + .../dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi | 93 + .../dsi-panel-sharp-dualdsi-wqhd-video.dtsi | 89 + .../dsi-panel-sharp-dualmipi-1080p-120hz.dtsi | 633 + ...si-panel-sharp-split-link-wuxga-video.dtsi | 74 + .../arm/qcom/dsi-panel-sim-cmd.dtsi | 220 + .../arm/qcom/dsi-panel-sim-dsc375-cmd.dtsi | 286 + .../arm/qcom/dsi-panel-sim-dualmipi-cmd.dtsi | 146 + .../dsi-panel-sim-dualmipi-dsc375-cmd.dtsi | 281 + .../qcom/dsi-panel-sim-dualmipi-video.dtsi | 70 + .../arm/qcom/dsi-panel-sim-sec-hd-cmd.dtsi | 75 + .../arm/qcom/dsi-panel-sim-video.dtsi | 69 + ...panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi | 111 + ...dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi | 130 + ...i-panel-sw43404-amoled-dsc-wqhd-video.dtsi | 95 + .../arm/qcom/dsi-panel-td4328-1080p-cmd.dtsi | 177 + .../qcom/dsi-panel-td4328-1080p-video.dtsi | 172 + ...panel-td4330-truly-singlemipi-fhd-cmd.dtsi | 316 + ...nel-td4330-truly-singlemipi-fhd-video.dtsi | 315 + .../fg-gen4-batterydata-alium-3600mah.dtsi | 154 + ...fg-gen4-batterydata-mlp466076-3250mah.dtsi | 149 + .../arm/qcom/guacamole-overlay-dvt.dts | 43 + .../arm/qcom/guacamole-overlay-evt1.dts | 39 + .../qcom/guacamole-overlay-evt2-second.dts | 40 + .../arm/qcom/guacamole-overlay-evt2.dts | 40 + .../arm/qcom/guacamole-overlay-evt3.dts | 41 + .../arm/qcom/guacamole-overlay-pvt.dts | 44 + .../arm/qcom/guacamole-overlay-t0.dts | 39 + .../arm/qcom/guacamole-sdx50m-overlay-dvt.dts | 46 + .../qcom/guacamole-sdx50m-overlay-evt1.dts | 44 + .../qcom/guacamole-sdx50m-overlay-evt2.dts | 45 + .../arm/qcom/guacamole-sdx50m-overlay-pvt.dts | 47 + .../arm/qcom/guacamole-sdx50m-overlay-t0.dts | 43 + .../include-prefixes/arm/qcom/guacamole.dtsi | 166 + .../arm/qcom/guacamole_dvt.dtsi | 1 + .../arm/qcom/guacamole_evt1.dtsi | 2 + .../arm/qcom/guacamole_evt2.dtsi | 2 + .../arm/qcom/guacamole_evt3.dtsi | 2 + .../arm/qcom/guacamole_pvt.dtsi | 1 + .../arm/qcom/guacamole_sdx50m.dtsi | 17 + .../arm/qcom/guacamole_sm8150.dtsi | 8 + .../arm/qcom/guacamole_t0.dtsi | 99 + .../arm/qcom/guacamoleb-overlay-dvt.dts | 39 + .../arm/qcom/guacamoleb-overlay-evt.dts | 39 + .../arm/qcom/guacamoleb-overlay-pvt.dts | 39 + .../arm/qcom/guacamoleb-overlay-t0.dts | 39 + .../include-prefixes/arm/qcom/guacamoleb.dtsi | 490 + .../arm/qcom/guacamoleb_dvt.dtsi | 1 + .../arm/qcom/guacamoleb_evt.dtsi | 1 + .../arm/qcom/guacamoleb_pvt.dtsi | 1 + .../arm/qcom/guacamoleb_sm8150.dtsi | 7 + .../arm/qcom/guacamoleb_t0.dtsi | 4 + .../qcom/guacamoles-sdx50m-overlay-dvt.dts | 45 + .../qcom/guacamoles-sdx50m-overlay-evt.dts | 45 + .../qcom/guacamoles-sdx50m-overlay-pvt.dts | 45 + .../arm/qcom/guacamoles-sdx50m-overlay-t0.dts | 44 + .../arm/qcom/guacamoles_sdx50m.dtsi | 11 + .../arm/qcom/guacamoles_sdx50m_dvt.dtsi | 2 + .../arm/qcom/guacamoles_sdx50m_evt.dtsi | 1 + .../arm/qcom/guacamoles_sdx50m_pvt.dtsi | 1 + .../arm/qcom/guacamoles_sdx50m_t0.dtsi | 1 + .../arm/qcom/ipq8074-hk01.dts | 52 + .../include-prefixes/arm/qcom/ipq8074.dtsi | 194 + .../arm/qcom/msm-arm-smmu-atoll.dtsi | 204 + .../arm/qcom/msm-arm-smmu-qcs405.dtsi | 92 + .../arm/qcom/msm-arm-smmu-sdmmagpie.dtsi | 358 + .../arm/qcom/msm-arm-smmu-sdmshrike.dtsi | 444 + .../arm/qcom/msm-arm-smmu-sdxprairie.dtsi | 102 + .../arm/qcom/msm-arm-smmu-sm6150.dtsi | 317 + .../arm/qcom/msm-arm-smmu-sm8150-v2.dtsi | 406 + .../arm/qcom/msm-arm-smmu-sm8150.dtsi | 420 + .../arm/qcom/msm-arm-smmu-trinket.dtsi | 280 + .../arm/qcom/msm-audio-lpass.dtsi | 738 + .../arm/qcom/msm-qvr-external.dtsi | 21 + .../include-prefixes/arm/qcom/msm-rdbg.dtsi | 35 + .../arm/qcom/msm-wsa881x.dtsi | 77 + .../include-prefixes/arm/qcom/msm8916-mtp.dts | 22 + .../arm/qcom/msm8916-mtp.dtsi | 35 + .../arm/qcom/msm8916-pins.dtsi | 736 + .../include-prefixes/arm/qcom/msm8916.dtsi | 1461 ++ .../arm/qcom/msm8992-bullhead-rev-101.dts | 41 + .../arm/qcom/msm8992-pins.dtsi | 38 + .../include-prefixes/arm/qcom/msm8992.dtsi | 237 + .../arm/qcom/msm8994-angler-rev-101.dts | 40 + .../arm/qcom/msm8994-pins.dtsi | 38 + .../include-prefixes/arm/qcom/msm8994.dtsi | 216 + .../include-prefixes/arm/qcom/msm8996-mtp.dts | 21 + .../arm/qcom/msm8996-mtp.dtsi | 30 + .../arm/qcom/msm8996-pins.dtsi | 303 + .../include-prefixes/arm/qcom/msm8996.dtsi | 925 ++ .../arm/qcom/pm6125-rpm-regulator.dtsi | 505 + .../dtc/include-prefixes/arm/qcom/pm6125.dtsi | 224 + .../dtc/include-prefixes/arm/qcom/pm6150.dtsi | 665 + .../include-prefixes/arm/qcom/pm6150l.dtsi | 514 + .../dtc/include-prefixes/arm/qcom/pm6155.dtsi | 175 + .../dtc/include-prefixes/arm/qcom/pm8004.dtsi | 20 + .../dtc/include-prefixes/arm/qcom/pm8008.dtsi | 117 + .../dtc/include-prefixes/arm/qcom/pm8009.dtsi | 47 + .../dtc/include-prefixes/arm/qcom/pm8150.dtsi | 194 + .../include-prefixes/arm/qcom/pm8150b.dtsi | 703 + .../include-prefixes/arm/qcom/pm8150l.dtsi | 516 + .../dtc/include-prefixes/arm/qcom/pm8195.dtsi | 251 + .../dtc/include-prefixes/arm/qcom/pm8916.dtsi | 143 + .../dtc/include-prefixes/arm/qcom/pm8994.dtsi | 71 + .../dtc/include-prefixes/arm/qcom/pmi632.dtsi | 737 + .../include-prefixes/arm/qcom/pmi8994.dtsi | 37 + .../arm/qcom/pms405-rpm-regulator.dtsi | 317 + .../dtc/include-prefixes/arm/qcom/pms405.dtsi | 207 + .../include-prefixes/arm/qcom/pmxprairie.dtsi | 209 + .../arm/qcom/qcs401-iot-sku1.dts | 81 + .../dtc/include-prefixes/arm/qcom/qcs401.dtsi | 48 + .../arm/qcom/qcs403-ext-pll-audio.dtsi | 29 + .../arm/qcom/qcs403-iot-sku1.dts | 88 + .../arm/qcom/qcs403-iot-sku2.dts | 124 + .../arm/qcom/qcs403-iot-sku3.dts | 150 + .../arm/qcom/qcs403-iot-sku4.dts | 126 + .../dtc/include-prefixes/arm/qcom/qcs403.dtsi | 61 + .../arm/qcom/qcs405-amic-audio-overlay.dtsi | 40 + .../arm/qcom/qcs405-audio-overlay.dtsi | 103 + .../arm/qcom/qcs405-audio.dtsi | 193 + .../arm/qcom/qcs405-blsp.dtsi | 526 + .../include-prefixes/arm/qcom/qcs405-bus.dtsi | 895 ++ .../arm/qcom/qcs405-circular-pca9956.dtsi | 246 + .../arm/qcom/qcs405-coresight.dtsi | 1089 ++ .../include-prefixes/arm/qcom/qcs405-cpu.dtsi | 192 + .../arm/qcom/qcs405-csra1-audio-overlay.dtsi | 134 + .../arm/qcom/qcs405-csra1.dtsi | 34 + .../arm/qcom/qcs405-csra6-audio-overlay.dtsi | 145 + .../arm/qcom/qcs405-csra6.dtsi | 95 + .../arm/qcom/qcs405-csra8-audio-overlay.dtsi | 150 + .../arm/qcom/qcs405-csra8.dtsi | 118 + .../arm/qcom/qcs405-gdsc.dtsi | 29 + .../arm/qcom/qcs405-geni-ir-overlay.dtsi | 35 + .../include-prefixes/arm/qcom/qcs405-gpu.dtsi | 187 + .../include-prefixes/arm/qcom/qcs405-ion.dtsi | 43 + .../arm/qcom/qcs405-iot-sku1.dts | 74 +- .../arm/qcom/qcs405-iot-sku10.dts | 62 + .../arm/qcom/qcs405-iot-sku11.dts | 79 + .../arm/qcom/qcs405-iot-sku12.dts | 36 + .../arm/qcom/qcs405-iot-sku2.dts | 192 + .../arm/qcom/qcs405-iot-sku3.dts | 8 +- .../arm/qcom/qcs405-iot-sku4.dts | 85 + .../arm/qcom/qcs405-iot-sku5.dts | 97 + .../arm/qcom/qcs405-iot-sku6.dts | 72 + .../arm/qcom/qcs405-iot-sku7.dts | 63 + .../arm/qcom/qcs405-iot-sku8.dts | 25 +- .../arm/qcom/qcs405-iot-sku9.dts | 73 + .../arm/qcom/qcs405-linear-pca9956.dtsi | 250 + .../include-prefixes/arm/qcom/qcs405-lpi.dtsi | 484 + .../arm/qcom/qcs405-mdss-panels.dtsi | 31 + .../arm/qcom/qcs405-mdss-pll.dtsi | 126 + .../arm/qcom/qcs405-mdss.dtsi | 466 + .../include-prefixes/arm/qcom/qcs405-mhi.dtsi | 716 + .../arm/qcom/qcs405-nowcd-audio-overlay.dtsi | 85 + .../arm/qcom/qcs405-pcie.dtsi | 138 + .../arm/qcom/qcs405-pinctrl.dtsi | 2478 +++ .../include-prefixes/arm/qcom/qcs405-pm.dtsi | 140 + .../arm/qcom/qcs405-regulator.dtsi | 383 + .../include-prefixes/arm/qcom/qcs405-rumi.dts | 27 + .../arm/qcom/qcs405-rumi.dtsi | 134 + .../arm/qcom/qcs405-stub-regulator.dtsi | 194 + .../arm/qcom/qcs405-tasha.dtsi | 113 + .../arm/qcom/qcs405-tdm-audio-overlay.dtsi | 87 + .../arm/qcom/qcs405-thermal.dtsi | 417 + .../include-prefixes/arm/qcom/qcs405-usb.dtsi | 216 + .../arm/qcom/qcs405-va-bolero.dtsi | 38 + .../arm/qcom/qcs405-wsa-audio-overlay.dtsi | 127 + .../arm/qcom/qcs405-wsa-bolero.dtsi | 40 + .../arm/qcom/qcs405-wsa881x.dtsi | 61 + .../dtc/include-prefixes/arm/qcom/qcs405.dtsi | 1691 ++ .../arm/qcom/qcs410-iot-overlay.dts | 23 + .../include-prefixes/arm/qcom/qcs410-iot.dts | 22 + .../include-prefixes/arm/qcom/qcs410-iot.dtsi | 165 + .../dtc/include-prefixes/arm/qcom/qcs410.dts | 21 + .../dtc/include-prefixes/arm/qcom/qcs410.dtsi | 137 + .../arm/qcom/qcs610-camera-sensor-idp.dtsi | 98 + .../arm/qcom/qcs610-iot-overlay.dts | 25 + .../include-prefixes/arm/qcom/qcs610-iot.dts | 26 + .../include-prefixes/arm/qcom/qcs610-iot.dtsi | 447 + .../dtc/include-prefixes/arm/qcom/qcs610.dts | 21 + .../dtc/include-prefixes/arm/qcom/qcs610.dtsi | 29 + .../qcom/qg-batterydata-alium-3600mah.dtsi | 1048 ++ .../qcom/qg-batterydata-ascent-3450mah.dtsi | 1042 ++ .../qg-batterydata-mlp356477-2800mah.dtsi | 1044 ++ .../qg-batterydata-mlp466076-3200mah.dtsi | 1044 ++ .../arm/qcom/quin-vm-common.dtsi | 251 + .../arm/qcom/rgb-panel-st7789v.dtsi | 30 + .../arm/qcom/sa515m-ccard-pcie-ep.dts | 46 + .../arm/qcom/sa515m-ccard-usb-ep.dts | 22 + .../arm/qcom/sa515m-ccard.dts | 22 + .../arm/qcom/sa515m-ccard.dtsi | 132 + .../arm/qcom/sa6155-adp-air-overlay.dts | 25 + .../arm/qcom/sa6155-adp-air.dts | 21 + .../arm/qcom/sa6155-adp-air.dtsi | 267 + .../arm/qcom/sa6155-adp-star-overlay.dts | 25 + .../arm/qcom/sa6155-adp-star.dts | 21 + .../arm/qcom/sa6155-adp-star.dtsi | 275 + .../arm/qcom/sa6155-audio.dtsi | 597 + .../arm/qcom/sa6155-cnss.dtsi | 223 + .../arm/qcom/sa6155-display.dtsi | 227 + .../arm/qcom/sa6155-pcie.dtsi | 253 + .../arm/qcom/sa6155-pmic.dtsi | 319 + .../arm/qcom/sa6155-regulator.dtsi | 537 + .../dtc/include-prefixes/arm/qcom/sa6155.dts | 22 + .../dtc/include-prefixes/arm/qcom/sa6155.dtsi | 485 + .../arm/qcom/sa6155p-adp-air-overlay.dts | 26 + .../arm/qcom/sa6155p-adp-air.dts | 22 + .../arm/qcom/sa6155p-adp-star-overlay.dts | 26 + .../arm/qcom/sa6155p-adp-star.dts | 22 + .../arm/qcom/sa6155p-v2-adp-air-overlay.dts | 26 + .../arm/qcom/sa6155p-v2-adp-air.dts | 22 + .../arm/qcom/sa6155p-v2-adp-star-overlay.dts | 26 + .../arm/qcom/sa6155p-v2-adp-star.dts | 22 + .../arm/qcom/sa6155p-vm-pcie.dtsi | 245 + .../arm/qcom/sa6155p-vm-pinctrl.dtsi | 1783 +++ .../arm/qcom/sa6155p-vm-qupv3.dtsi | 450 + .../arm/qcom/sa6155p-vm-usb.dtsi | 404 + .../include-prefixes/arm/qcom/sa6155p-vm.dts | 52 + .../include-prefixes/arm/qcom/sa6155p-vm.dtsi | 351 + .../dtc/include-prefixes/arm/qcom/sa6155p.dts | 22 + .../include-prefixes/arm/qcom/sa6155p.dtsi | 517 + .../arm/qcom/sa8155-adp-alcor-display.dtsi | 91 + .../arm/qcom/sa8155-adp-alcor-overlay.dts | 23 + .../arm/qcom/sa8155-adp-alcor.dts | 22 + .../arm/qcom/sa8155-adp-alcor.dtsi | 98 + .../arm/qcom/sa8155-adp-common.dtsi | 249 + .../arm/qcom/sa8155-adp-star-display.dtsi | 319 + .../arm/qcom/sa8155-adp-star-overlay.dts | 25 + .../arm/qcom/sa8155-adp-star.dts | 22 + .../arm/qcom/sa8155-adp-star.dtsi | 52 + .../arm/qcom/sa8155-audio.dtsi | 614 + .../arm/qcom/sa8155-camera-sensor.dtsi | 143 + .../arm/qcom/sa8155-cnss.dtsi | 350 + .../arm/qcom/sa8155-pmic-overlay.dtsi | 125 + .../arm/qcom/sa8155-regulator.dtsi | 726 + .../include-prefixes/arm/qcom/sa8155-v1.dtsi | 21 + .../arm/qcom/sa8155-v2-adp-air-overlay.dts | 24 + .../arm/qcom/sa8155-v2-adp-air.dts | 23 + .../arm/qcom/sa8155-v2-adp-star.dts | 22 + .../include-prefixes/arm/qcom/sa8155-v2.dts | 26 + .../include-prefixes/arm/qcom/sa8155-v2.dtsi | 147 + .../arm/qcom/sa8155-vm-audio.dtsi | 534 + .../arm/qcom/sa8155-vm-la-mt.dts | 30 + .../arm/qcom/sa8155-vm-lv-mt.dts | 59 + .../arm/qcom/sa8155-vm-lv.dts | 47 + .../arm/qcom/sa8155-vm-mhi.dtsi | 551 + .../arm/qcom/sa8155-vm-pcie.dtsi | 279 + .../arm/qcom/sa8155-vm-pinctrl.dtsi | 25 + .../arm/qcom/sa8155-vm-qupv3.dtsi | 960 ++ .../arm/qcom/sa8155-vm-usb.dtsi | 542 + .../include-prefixes/arm/qcom/sa8155-vm.dts | 43 + .../include-prefixes/arm/qcom/sa8155-vm.dtsi | 496 + .../dtc/include-prefixes/arm/qcom/sa8155.dts | 26 + .../dtc/include-prefixes/arm/qcom/sa8155.dtsi | 610 + .../arm/qcom/sa8155p-adp-alcor-overlay.dts | 23 + .../arm/qcom/sa8155p-adp-alcor.dts | 23 + .../arm/qcom/sa8155p-adp-star-overlay.dts | 25 + .../arm/qcom/sa8155p-adp-star.dts | 22 + .../arm/qcom/sa8155p-v2-adp-air-overlay.dts | 24 + .../arm/qcom/sa8155p-v2-adp-air.dts | 23 + .../arm/qcom/sa8155p-v2-adp-star.dts | 22 + .../include-prefixes/arm/qcom/sa8155p-v2.dts | 26 + .../include-prefixes/arm/qcom/sa8155p-v2.dtsi | 19 + .../dtc/include-prefixes/arm/qcom/sa8155p.dts | 26 + .../include-prefixes/arm/qcom/sa8155p.dtsi | 20 + .../arm/qcom/sa8195-pmic.dtsi | 121 + .../include-prefixes/arm/qcom/sa8195-vm.dts | 38 + .../include-prefixes/arm/qcom/sa8195-vm.dtsi | 207 + .../arm/qcom/sa8195p-adp-star-display.dtsi | 306 + .../arm/qcom/sa8195p-adp-star-overlay.dts | 23 + .../arm/qcom/sa8195p-adp-star.dts | 22 + .../arm/qcom/sa8195p-adp-star.dtsi | 36 + .../arm/qcom/sa8195p-pcie.dtsi | 805 + .../arm/qcom/sa8195p-regulator.dtsi | 850 + .../dtc/include-prefixes/arm/qcom/sa8195p.dts | 22 + .../include-prefixes/arm/qcom/sa8195p.dtsi | 108 + .../arm/qcom/sdmmagpie-atp-overlay.dts | 32 + .../arm/qcom/sdmmagpie-atp.dts | 22 + .../arm/qcom/sdmmagpie-atp.dtsi | 387 + .../arm/qcom/sdmmagpie-audio-overlay.dtsi | 32 + .../arm/qcom/sdmmagpie-audio.dtsi | 18 + .../arm/qcom/sdmmagpie-bus.dtsi | 2032 +++ .../arm/qcom/sdmmagpie-camera-sensor-idp.dtsi | 617 + .../arm/qcom/sdmmagpie-camera-sensor-qrd.dtsi | 169 +- .../arm/qcom/sdmmagpie-camera.dtsi | 1241 ++ .../arm/qcom/sdmmagpie-coresight.dtsi | 2721 ++++ .../sdmmagpie-dual-display-idp-overlay.dts | 40 + .../arm/qcom/sdmmagpie-dual-display-idp.dts | 35 + .../sdmmagpie-ext-codec-audio-overlay.dtsi | 26 + .../sdmmagpie-external-codec-idp-overlay.dts | 28 + .../arm/qcom/sdmmagpie-external-codec-idp.dts | 24 + .../arm/qcom/sdmmagpie-external-codec.dtsi | 14 + .../arm/qcom/sdmmagpie-gdsc.dtsi | 230 + .../arm/qcom/sdmmagpie-gpu.dtsi | 608 + .../arm/qcom/sdmmagpie-idp-overlay.dts | 31 + .../arm/qcom/sdmmagpie-idp.dts | 26 + .../arm/qcom/sdmmagpie-idp.dtsi | 432 + .../arm/qcom/sdmmagpie-ion.dtsi | 62 + .../arm/qcom/sdmmagpie-npu.dtsi | 191 + .../arm/qcom/sdmmagpie-pinctrl.dtsi | 1683 ++ .../arm/qcom/sdmmagpie-pm.dtsi | 170 + .../arm/qcom/sdmmagpie-qrd-overlay.dts | 70 + .../arm/qcom/sdmmagpie-qrd.dts | 22 + .../arm/qcom/sdmmagpie-qrd.dtsi | 431 + .../arm/qcom/sdmmagpie-qupv3.dtsi | 565 + .../arm/qcom/sdmmagpie-regulator.dtsi | 890 ++ .../arm/qcom/sdmmagpie-rumi-overlay.dts | 26 + .../arm/qcom/sdmmagpie-rumi.dts | 22 + .../arm/qcom/sdmmagpie-rumi.dtsi | 192 + .../arm/qcom/sdmmagpie-sde-display.dtsi | 742 + .../arm/qcom/sdmmagpie-sde-pll.dtsi | 114 + .../arm/qcom/sdmmagpie-sde.dtsi | 690 + .../arm/qcom/sdmmagpie-stub-regulator.dtsi | 352 + .../arm/qcom/sdmmagpie-thermal-overlay.dtsi | 182 + .../arm/qcom/sdmmagpie-thermal.dtsi | 1912 +++ .../arm/qcom/sdmmagpie-usb.dtsi | 375 + .../arm/qcom/sdmmagpie-usbc-idp-overlay.dts | 26 + .../arm/qcom/sdmmagpie-usbc-idp.dts | 23 + .../arm/qcom/sdmmagpie-usbc-idp.dtsi | 19 + .../arm/qcom/sdmmagpie-vidc.dtsi | 219 + .../include-prefixes/arm/qcom/sdmmagpie.dts | 22 + .../include-prefixes/arm/qcom/sdmmagpie.dtsi | 3472 ++++ .../arm/qcom/sdmmagpiep-atp-overlay.dts | 26 + .../arm/qcom/sdmmagpiep-atp.dts | 22 + .../arm/qcom/sdmmagpiep-idp-overlay.dts | 26 + .../arm/qcom/sdmmagpiep-idp.dts | 22 + .../arm/qcom/sdmmagpiep-qrd-overlay.dts | 25 + .../arm/qcom/sdmmagpiep-qrd.dts | 22 + .../include-prefixes/arm/qcom/sdmmagpiep.dts | 22 + .../include-prefixes/arm/qcom/sdmmagpiep.dtsi | 19 + .../arm/qcom/sdmshrike-audio-overlay.dtsi | 307 + .../arm/qcom/sdmshrike-bus.dtsi | 2148 +++ .../arm/qcom/sdmshrike-cdp-overlay.dts | 26 + .../arm/qcom/sdmshrike-cdp.dts | 22 + .../arm/qcom/sdmshrike-cdp.dtsi | 123 + .../arm/qcom/sdmshrike-gdsc.dtsi | 60 + .../arm/qcom/sdmshrike-gpu.dtsi | 393 + .../arm/qcom/sdmshrike-ion.dtsi | 65 + .../arm/qcom/sdmshrike-mtp-overlay.dts | 26 + .../arm/qcom/sdmshrike-mtp.dts | 22 + .../arm/qcom/sdmshrike-mtp.dtsi | 156 + .../arm/qcom/sdmshrike-pinctrl.dtsi | 4246 +++++ .../arm/qcom/sdmshrike-pmic-overlay.dtsi | 111 + .../arm/qcom/sdmshrike-qupv3.dtsi | 989 ++ .../arm/qcom/sdmshrike-regulators.dtsi | 971 ++ .../arm/qcom/sdmshrike-rumi.dts | 23 + .../arm/qcom/sdmshrike-rumi.dtsi | 73 + .../arm/qcom/sdmshrike-sde-display.dtsi | 615 + .../arm/qcom/sdmshrike-sde-pll.dtsi | 92 + .../arm/qcom/sdmshrike-sde.dtsi | 717 + .../arm/qcom/sdmshrike-smp2p.dtsi | 96 + .../arm/qcom/sdmshrike-thermal-overlay.dtsi | 166 + .../arm/qcom/sdmshrike-thermal.dtsi | 1367 ++ .../arm/qcom/sdmshrike-usb.dtsi | 242 + .../arm/qcom/sdmshrike-v2-mtp.dts | 22 + .../arm/qcom/sdmshrike-v2.dts | 22 + .../arm/qcom/sdmshrike-v2.dtsi | 262 + .../include-prefixes/arm/qcom/sdmshrike.dts | 22 + .../include-prefixes/arm/qcom/sdmshrike.dtsi | 2513 +++ .../arm/qcom/sdx-audio-lpass.dtsi | 345 + .../arm/qcom/sdx-wsa881x.dtsi | 45 + .../arm/qcom/sdx5xm-external-soc.dtsi | 59 + .../arm/qcom/sdxprairie-aqc.dtsi | 95 + .../arm/qcom/sdxprairie-audio-overlay.dtsi | 143 + .../arm/qcom/sdxprairie-audio.dtsi | 55 + .../arm/qcom/sdxprairie-blsp.dtsi | 572 + .../arm/qcom/sdxprairie-bus.dtsi | 958 ++ .../arm/qcom/sdxprairie-cdp-256.dts | 31 + .../arm/qcom/sdxprairie-cdp-256.dtsi | 182 + .../qcom/sdxprairie-cdp-audio-overlay.dtsi | 22 + .../arm/qcom/sdxprairie-cdp-cpe.dts | 24 + .../arm/qcom/sdxprairie-cdp-cpe.dtsi | 22 + .../arm/qcom/sdxprairie-cdp.dts | 31 + .../arm/qcom/sdxprairie-cdp.dtsi | 213 + .../arm/qcom/sdxprairie-coresight.dtsi | 1283 ++ .../arm/qcom/sdxprairie-dsda-cdp.dts | 56 + .../arm/qcom/sdxprairie-dsda-mtp.dts | 56 + .../arm/qcom/sdxprairie-gdsc.dtsi | 36 + .../arm/qcom/sdxprairie-ion.dtsi | 41 + .../arm/qcom/sdxprairie-mtp-256.dts | 31 + .../arm/qcom/sdxprairie-mtp-256.dtsi | 224 + .../arm/qcom/sdxprairie-mtp-aqc.dts | 31 + .../qcom/sdxprairie-mtp-audio-overlay.dtsi | 22 + .../arm/qcom/sdxprairie-mtp-cpe.dts | 55 + .../arm/qcom/sdxprairie-mtp-cpe.dtsi | 18 + .../arm/qcom/sdxprairie-mtp.dts | 31 + .../arm/qcom/sdxprairie-mtp.dtsi | 245 + .../arm/qcom/sdxprairie-pcie-ep-mtp.dts | 24 + .../arm/qcom/sdxprairie-pcie-ep-mtp.dtsi | 42 + .../arm/qcom/sdxprairie-pcie.dtsi | 250 + .../arm/qcom/sdxprairie-pinctrl.dtsi | 1477 ++ .../arm/qcom/sdxprairie-pm.dtsi | 102 + .../arm/qcom/sdxprairie-pmic-overlay.dtsi | 51 + .../arm/qcom/sdxprairie-regulator.dtsi | 511 + .../arm/qcom/sdxprairie-rumi.dts | 31 + .../arm/qcom/sdxprairie-rumi.dtsi | 91 + .../arm/qcom/sdxprairie-thermal.dtsi | 428 + .../arm/qcom/sdxprairie-usb.dtsi | 285 + .../arm/qcom/sdxprairie-v2-cdp.dts | 23 + .../arm/qcom/sdxprairie-v2-mtp.dts | 25 + .../arm/qcom/sdxprairie-v2.dtsi | 31 + .../arm/qcom/sdxprairie-wcd.dtsi | 80 + .../include-prefixes/arm/qcom/sdxprairie.dtsi | 1519 ++ .../include-prefixes/arm/qcom/skeleton.dtsi | 18 + .../include-prefixes/arm/qcom/skeleton64.dtsi | 15 + .../arm/qcom/sm6150-audio-overlay.dtsi | 505 + .../arm/qcom/sm6150-audio.dtsi | 155 + .../include-prefixes/arm/qcom/sm6150-bus.dtsi | 1850 +++ .../arm/qcom/sm6150-camera-sensor-adp.dtsi | 115 + .../arm/qcom/sm6150-camera-sensor-idp.dtsi | 624 + .../arm/qcom/sm6150-camera-sensor-qrd.dtsi | 364 + .../arm/qcom/sm6150-camera.dtsi | 1076 ++ .../sm6150-cmd-mode-display-idp-overlay.dts | 62 + .../arm/qcom/sm6150-cmd-mode-display-idp.dts | 22 + .../arm/qcom/sm6150-coresight.dtsi | 2774 ++++ .../qcom/sm6150-ext-codec-audio-overlay.dtsi | 89 + .../sm6150-external-codec-idp-overlay.dts | 32 + .../arm/qcom/sm6150-external-codec-idp.dts | 24 + .../arm/qcom/sm6150-external-codec.dtsi | 151 + .../arm/qcom/sm6150-gdsc.dtsi | 213 + .../include-prefixes/arm/qcom/sm6150-gpu.dtsi | 651 + .../arm/qcom/sm6150-idp-overlay.dts | 31 + .../include-prefixes/arm/qcom/sm6150-idp.dts | 23 + .../include-prefixes/arm/qcom/sm6150-idp.dtsi | 403 + .../sm6150-interposer-trinket-idp-overlay.dts | 29 + .../qcom/sm6150-interposer-trinket-idp.dts | 23 + .../qcom/sm6150-interposer-trinket-idp.dtsi | 130 + .../sm6150-interposer-trinket-qrd-overlay.dts | 23 + .../qcom/sm6150-interposer-trinket-qrd.dts | 23 + .../qcom/sm6150-interposer-trinket-qrd.dtsi | 182 + .../arm/qcom/sm6150-interposer-trinket.dts | 22 + .../arm/qcom/sm6150-interposer-trinket.dtsi | 54 + .../include-prefixes/arm/qcom/sm6150-ion.dtsi | 68 + .../include-prefixes/arm/qcom/sm6150-lpi.dtsi | 331 + .../arm/qcom/sm6150-pinctrl.dtsi | 2263 +++ .../include-prefixes/arm/qcom/sm6150-pm.dtsi | 163 + .../sm6150-pm6125-interposer-trinket.dtsi | 721 + .../arm/qcom/sm6150-qrd-overlay.dts | 67 + .../include-prefixes/arm/qcom/sm6150-qrd.dts | 22 + .../include-prefixes/arm/qcom/sm6150-qrd.dtsi | 291 + .../arm/qcom/sm6150-qupv3.dtsi | 503 + .../arm/qcom/sm6150-regulator.dtsi | 762 + .../arm/qcom/sm6150-rumi-overlay.dts | 26 + .../include-prefixes/arm/qcom/sm6150-rumi.dts | 23 + .../arm/qcom/sm6150-rumi.dtsi | 206 + .../arm/qcom/sm6150-sde-display.dtsi | 548 + .../arm/qcom/sm6150-sde-pll.dtsi | 83 + .../include-prefixes/arm/qcom/sm6150-sde.dtsi | 579 + .../arm/qcom/sm6150-slpi-pinctrl.dtsi | 461 + .../arm/qcom/sm6150-stub-regulator.dtsi | 345 + .../arm/qcom/sm6150-thermal-overlay.dtsi | 182 + .../arm/qcom/sm6150-thermal.dtsi | 2087 +++ .../include-prefixes/arm/qcom/sm6150-usb.dtsi | 436 + .../arm/qcom/sm6150-usbc-idp-overlay.dts | 31 + .../arm/qcom/sm6150-usbc-idp.dts | 23 + .../arm/qcom/sm6150-usbc-idp.dtsi | 19 + .../qcom/sm6150-usbc-minidp-idp-overlay.dts | 32 + .../arm/qcom/sm6150-usbc-minidp-idp.dts | 28 + .../arm/qcom/sm6150-vidc.dtsi | 109 + .../include-prefixes/arm/qcom/sm6150-wcd.dtsi | 168 + .../dtc/include-prefixes/arm/qcom/sm6150.dts | 22 + .../dtc/include-prefixes/arm/qcom/sm6150.dtsi | 3245 ++++ .../arm/qcom/sm6150p-idp-overlay.dts | 31 + .../include-prefixes/arm/qcom/sm6150p-idp.dts | 22 + .../arm/qcom/sm6150p-qrd-overlay.dts | 26 + .../include-prefixes/arm/qcom/sm6150p-qrd.dts | 22 + .../dtc/include-prefixes/arm/qcom/sm6150p.dts | 22 + .../include-prefixes/arm/qcom/sm6150p.dtsi | 19 + .../arm/qcom/sm8150-audio-overlay.dtsi | 355 + .../arm/qcom/sm8150-audio.dtsi | 183 + .../include-prefixes/arm/qcom/sm8150-bus.dtsi | 2180 +++ .../arm/qcom/sm8150-camera-sensor-cdp.dtsi | 775 + .../arm/qcom/sm8150-camera-sensor-hdk.dtsi | 425 + .../arm/qcom/sm8150-camera-sensor-mtp.dtsi | 780 + .../arm/qcom/sm8150-camera-sensor-qrd.dtsi | 415 + .../arm/qcom/sm8150-camera.dtsi | 1248 ++ .../arm/qcom/sm8150-cdp-audio-overlay.dtsi | 19 + .../arm/qcom/sm8150-cdp-overlay.dts | 32 + .../include-prefixes/arm/qcom/sm8150-cdp.dts | 22 + .../include-prefixes/arm/qcom/sm8150-cdp.dtsi | 663 + .../arm/qcom/sm8150-coresight.dtsi | 2795 ++++ .../arm/qcom/sm8150-gdsc.dtsi | 267 + .../arm/qcom/sm8150-gpu-v2.dtsi | 47 + .../include-prefixes/arm/qcom/sm8150-gpu.dtsi | 404 + .../arm/qcom/sm8150-hdk-overlay.dts | 143 + .../include-prefixes/arm/qcom/sm8150-hdk.dts | 22 + .../include-prefixes/arm/qcom/sm8150-hdk.dtsi | 101 + .../include-prefixes/arm/qcom/sm8150-ion.dtsi | 74 + .../include-prefixes/arm/qcom/sm8150-mhi.dtsi | 1097 ++ .../arm/qcom/sm8150-mtp-audio-overlay.dtsi | 18 + .../arm/qcom/sm8150-mtp-overlay.dts | 32 + .../include-prefixes/arm/qcom/sm8150-mtp.dts | 22 + .../include-prefixes/arm/qcom/sm8150-mtp.dtsi | 686 + .../include-prefixes/arm/qcom/sm8150-npu.dtsi | 204 + .../qcom/sm8150-oem-camera-guacamoleb.dtsi | 889 ++ .../arm/qcom/sm8150-oem-camera-ov.dtsi | 854 + .../arm/qcom/sm8150-oem-camera-t0.dtsi | 1055 ++ .../arm/qcom/sm8150-oem-camera-v2.dtsi | 1035 ++ .../arm/qcom/sm8150-oem-camera.dtsi | 968 ++ .../include-prefixes/arm/qcom/sm8150-oem.dtsi | 1358 ++ .../arm/qcom/sm8150-pcie.dtsi | 824 + .../arm/qcom/sm8150-pinctrl.dtsi | 4577 ++++++ .../include-prefixes/arm/qcom/sm8150-pm.dtsi | 122 + .../arm/qcom/sm8150-pmic-overlay.dtsi | 145 + .../arm/qcom/sm8150-qrd-audio-overlay.dtsi | 57 + .../arm/qcom/sm8150-qrd-dvt-overlay.dts | 28 + .../arm/qcom/sm8150-qrd-dvt.dtsi | 29 + .../arm/qcom/sm8150-qrd-overlay.dts | 28 + .../include-prefixes/arm/qcom/sm8150-qrd.dts | 22 + .../include-prefixes/arm/qcom/sm8150-qrd.dtsi | 687 + .../arm/qcom/sm8150-qupv3.dtsi | 1081 ++ .../arm/qcom/sm8150-regulator.dtsi | 1001 ++ .../arm/qcom/sm8150-rumi-overlay.dts | 27 + .../include-prefixes/arm/qcom/sm8150-rumi.dts | 23 + .../arm/qcom/sm8150-rumi.dtsi | 163 + .../arm/qcom/sm8150-sde-display.dtsi | 950 ++ .../arm/qcom/sm8150-sde-pll.dtsi | 96 + .../include-prefixes/arm/qcom/sm8150-sde.dtsi | 691 + .../qcom/sm8150-sdx50-camera-sensor-qrd.dtsi | 415 + .../arm/qcom/sm8150-sdx50m-audio-overlay.dtsi | 20 + .../arm/qcom/sm8150-sdx50m-cdp-overlay.dts | 31 + .../sm8150-sdx50m-mtp-2.5k-panel-overlay.dts | 66 + .../arm/qcom/sm8150-sdx50m-mtp-overlay.dts | 31 + .../arm/qcom/sm8150-sdx50m-qrd-overlay.dts | 32 + .../arm/qcom/sm8150-sdx50m-qrd.dtsi | 733 + .../arm/qcom/sm8150-sdx50m.dtsi | 605 + .../qcom/sm8150-sdxprairie-cdp-overlay.dts | 62 + .../qcom/sm8150-sdxprairie-mtp-overlay.dts | 64 + .../qcom/sm8150-sdxprairie-v2-cdp-overlay.dts | 66 + .../qcom/sm8150-sdxprairie-v2-mtp-overlay.dts | 66 + .../arm/qcom/sm8150-sdxprairie-v2.dtsi | 18 + .../arm/qcom/sm8150-sdxprairie.dtsi | 581 + .../arm/qcom/sm8150-slpi-pinctrl.dtsi | 198 + .../arm/qcom/sm8150-smp2p.dtsi | 154 + .../arm/qcom/sm8150-thermal-overlay.dtsi | 302 + .../arm/qcom/sm8150-thermal.dtsi | 1274 ++ .../include-prefixes/arm/qcom/sm8150-usb.dtsi | 586 + .../arm/qcom/sm8150-v2-camera.dtsi | 340 + .../arm/qcom/sm8150-v2-cdp.dts | 22 + .../arm/qcom/sm8150-v2-mtp.dts | 22 + .../arm/qcom/sm8150-v2-qrd-dvt.dts | 22 + .../arm/qcom/sm8150-v2-qrd.dts | 22 + .../arm/qcom/sm8150-v2-rumi.dts | 23 + .../include-prefixes/arm/qcom/sm8150-v2.dts | 22 + .../include-prefixes/arm/qcom/sm8150-v2.dtsi | 1358 ++ .../arm/qcom/sm8150-vidc.dtsi | 139 + .../include-prefixes/arm/qcom/sm8150-wcd.dtsi | 235 + .../dtc/include-prefixes/arm/qcom/sm8150.dts | 22 + .../dtc/include-prefixes/arm/qcom/sm8150.dtsi | 4164 +++++ .../include-prefixes/arm/qcom/sm8150p-cdp.dts | 22 + .../include-prefixes/arm/qcom/sm8150p-hdk.dts | 22 + .../include-prefixes/arm/qcom/sm8150p-mtp.dts | 22 + .../include-prefixes/arm/qcom/sm8150p-qrd.dts | 22 + .../arm/qcom/sm8150p-v2-cdp.dts | 22 + .../arm/qcom/sm8150p-v2-mtp.dts | 22 + .../arm/qcom/sm8150p-v2-qrd.dts | 22 + .../include-prefixes/arm/qcom/sm8150p-v2.dts | 22 + .../include-prefixes/arm/qcom/sm8150p-v2.dtsi | 19 + .../dtc/include-prefixes/arm/qcom/sm8150p.dts | 22 + .../include-prefixes/arm/qcom/sm8150p.dtsi | 19 + .../include-prefixes/arm/qcom/smb1355.dtsi | 56 + .../include-prefixes/arm/qcom/smb1390.dtsi | 72 + .../arm/qcom/spi-panel-st7789v2-qvga-cmd.dtsi | 50 + .../arm/qcom/trinket-audio-overlay.dtsi | 463 + .../arm/qcom/trinket-audio.dtsi | 149 + .../arm/qcom/trinket-bus.dtsi | 1117 ++ .../arm/qcom/trinket-camera-sensor-idp.dtsi | 281 + .../arm/qcom/trinket-camera-sensor-qrd.dtsi | 230 + .../arm/qcom/trinket-camera.dtsi | 803 + .../arm/qcom/trinket-coresight.dtsi | 2316 +++ .../arm/qcom/trinket-dp-idp-overlay.dts | 51 + .../arm/qcom/trinket-dp-idp.dts | 44 + .../trinket-external-codec-idp-overlay.dts | 31 + .../arm/qcom/trinket-external-codec-idp.dts | 24 + .../arm/qcom/trinket-gdsc.dtsi | 143 + .../arm/qcom/trinket-gpu.dtsi | 279 + .../arm/qcom/trinket-idp-overlay.dts | 30 + .../include-prefixes/arm/qcom/trinket-idp.dts | 23 + .../arm/qcom/trinket-idp.dtsi | 383 + .../arm/qcom/trinket-ion.dtsi | 62 + .../arm/qcom/trinket-pinctrl.dtsi | 1851 +++ .../include-prefixes/arm/qcom/trinket-pm.dtsi | 224 + .../arm/qcom/trinket-qrd-overlay.dts | 24 + .../include-prefixes/arm/qcom/trinket-qrd.dts | 23 + .../arm/qcom/trinket-qrd.dtsi | 392 + .../arm/qcom/trinket-qupv3.dtsi | 462 + .../arm/qcom/trinket-regulator.dtsi | 372 + .../arm/qcom/trinket-rumi-overlay.dts | 25 + .../arm/qcom/trinket-rumi.dts | 24 + .../arm/qcom/trinket-rumi.dtsi | 187 + .../arm/qcom/trinket-sde-display.dtsi | 329 + .../arm/qcom/trinket-sde-pll.dtsi | 85 + .../arm/qcom/trinket-sde.dtsi | 563 + .../arm/qcom/trinket-stub-regulator.dtsi | 280 + .../trinket-tasha-codec-audio-overlay.dtsi | 96 + .../arm/qcom/trinket-tasha-codec.dtsi | 170 + .../arm/qcom/trinket-thermal-overlay.dtsi | 449 + .../arm/qcom/trinket-thermal.dtsi | 2015 +++ .../arm/qcom/trinket-usb.dtsi | 324 + ...rinket-usbc-external-codec-idp-overlay.dts | 29 + .../qcom/trinket-usbc-external-codec-idp.dts | 22 + .../arm/qcom/trinket-usbc-idp-overlay.dts | 30 + .../arm/qcom/trinket-usbc-idp.dts | 23 + .../arm/qcom/trinket-usbc-idp.dtsi | 19 + .../arm/qcom/trinket-vidc.dtsi | 110 + .../arm/qcom/trinket-wcd.dtsi | 29 + .../dtc/include-prefixes/arm/qcom/trinket.dts | 22 + .../include-prefixes/arm/qcom/trinket.dtsi | 3147 ++++ .../include-prefixes/arm/r7s72100-genmai.dts | 151 + .../arm/r7s72100-gr-peach.dts | 66 + .../include-prefixes/arm/r7s72100-rskrza1.dts | 143 + .../dtc/include-prefixes/arm/r7s72100.dtsi | 669 + .../include-prefixes/arm/r8a73a4-ape6evm.dts | 251 + scripts/dtc/include-prefixes/arm/r8a73a4.dtsi | 903 ++ .../arm/r8a7740-armadillo800eva.dts | 320 + scripts/dtc/include-prefixes/arm/r8a7740.dtsi | 724 + .../arm/r8a7743-iwg20d-q7.dts | 56 + .../include-prefixes/arm/r8a7743-iwg20m.dtsi | 55 + .../include-prefixes/arm/r8a7743-sk-rzg1m.dts | 80 + scripts/dtc/include-prefixes/arm/r8a7743.dtsi | 806 + .../include-prefixes/arm/r8a7745-sk-rzg1e.dts | 75 + scripts/dtc/include-prefixes/arm/r8a7745.dtsi | 535 + .../include-prefixes/arm/r8a7778-bockw.dts | 232 + scripts/dtc/include-prefixes/arm/r8a7778.dtsi | 634 + .../include-prefixes/arm/r8a7779-marzen.dts | 254 + scripts/dtc/include-prefixes/arm/r8a7779.dtsi | 609 + .../include-prefixes/arm/r8a7790-lager.dts | 861 + scripts/dtc/include-prefixes/arm/r8a7790.dtsi | 1943 +++ .../include-prefixes/arm/r8a7791-koelsch.dts | 844 + .../include-prefixes/arm/r8a7791-porter.dts | 456 + scripts/dtc/include-prefixes/arm/r8a7791.dtsi | 1942 +++ .../include-prefixes/arm/r8a7792-blanche.dts | 330 + .../include-prefixes/arm/r8a7792-wheat.dts | 325 + scripts/dtc/include-prefixes/arm/r8a7792.dtsi | 1023 ++ .../dtc/include-prefixes/arm/r8a7793-gose.dts | 731 + scripts/dtc/include-prefixes/arm/r8a7793.dtsi | 1572 ++ .../dtc/include-prefixes/arm/r8a7794-alt.dts | 417 + .../dtc/include-prefixes/arm/r8a7794-silk.dts | 463 + scripts/dtc/include-prefixes/arm/r8a7794.dtsi | 1657 ++ .../arm/r8a77xx-aa104xd12-panel.dtsi | 42 + .../arm/r8a77xx-aa121td01-panel.dtsi | 42 + .../dtc/include-prefixes/arm/rk3036-evb.dts | 83 + .../dtc/include-prefixes/arm/rk3036-kylin.dts | 432 + scripts/dtc/include-prefixes/arm/rk3036.dtsi | 777 + .../include-prefixes/arm/rk3066a-bqcurie2.dts | 236 + .../arm/rk3066a-marsboard.dts | 243 + .../include-prefixes/arm/rk3066a-mk808.dts | 193 + .../include-prefixes/arm/rk3066a-rayeager.dts | 485 + scripts/dtc/include-prefixes/arm/rk3066a.dtsi | 727 + .../include-prefixes/arm/rk3188-px3-evb.dts | 326 + .../include-prefixes/arm/rk3188-radxarock.dts | 395 + scripts/dtc/include-prefixes/arm/rk3188.dtsi | 644 + .../dtc/include-prefixes/arm/rk3228-evb.dts | 106 + .../dtc/include-prefixes/arm/rk3229-evb.dts | 291 + scripts/dtc/include-prefixes/arm/rk3229.dtsi | 89 + scripts/dtc/include-prefixes/arm/rk322x.dtsi | 1093 ++ .../arm/rk3288-evb-act8846.dts | 225 + .../include-prefixes/arm/rk3288-evb-rk808.dts | 239 + .../dtc/include-prefixes/arm/rk3288-evb.dtsi | 441 + .../include-prefixes/arm/rk3288-fennec.dts | 386 + .../arm/rk3288-firefly-beta.dts | 71 + .../arm/rk3288-firefly-reload-core.dtsi | 309 + .../arm/rk3288-firefly-reload.dts | 418 + .../include-prefixes/arm/rk3288-firefly.dts | 71 + .../include-prefixes/arm/rk3288-firefly.dtsi | 611 + .../dtc/include-prefixes/arm/rk3288-miqi.dts | 462 + .../arm/rk3288-phycore-rdk.dts | 297 + .../arm/rk3288-phycore-som.dtsi | 476 + .../include-prefixes/arm/rk3288-popmetal.dts | 539 + .../dtc/include-prefixes/arm/rk3288-r89.dts | 424 + .../arm/rk3288-rock2-som.dtsi | 307 + .../arm/rk3288-rock2-square.dts | 286 + .../include-prefixes/arm/rk3288-tinker.dts | 540 + .../arm/rk3288-veyron-analog-audio.dtsi | 101 + .../arm/rk3288-veyron-brain.dts | 139 + .../arm/rk3288-veyron-chromebook.dtsi | 333 + .../arm/rk3288-veyron-jaq.dts | 213 + .../arm/rk3288-veyron-jerry.dts | 206 + .../arm/rk3288-veyron-mickey.dts | 250 + .../arm/rk3288-veyron-minnie.dts | 290 + .../arm/rk3288-veyron-pinky.dts | 135 + .../arm/rk3288-veyron-sdmmc.dtsi | 126 + .../arm/rk3288-veyron-speedy.dts | 179 + .../include-prefixes/arm/rk3288-veyron.dtsi | 584 + scripts/dtc/include-prefixes/arm/rk3288.dtsi | 1866 +++ scripts/dtc/include-prefixes/arm/rk3xxx.dtsi | 455 + .../dtc/include-prefixes/arm/rv1108-evb.dts | 259 + scripts/dtc/include-prefixes/arm/rv1108.dtsi | 801 + .../include-prefixes/arm/s3c2416-pinctrl.dtsi | 175 + .../include-prefixes/arm/s3c2416-smdk2416.dts | 85 + scripts/dtc/include-prefixes/arm/s3c2416.dtsi | 125 + scripts/dtc/include-prefixes/arm/s3c24xx.dtsi | 95 + scripts/dtc/include-prefixes/arm/s3c6400.dtsi | 41 + .../include-prefixes/arm/s3c6410-mini6410.dts | 224 + .../include-prefixes/arm/s3c6410-smdk6410.dts | 103 + scripts/dtc/include-prefixes/arm/s3c6410.dtsi | 57 + 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.../arm64/nvidia/tegra210-p2530.dtsi | 55 + .../arm64/nvidia/tegra210-p2571.dts | 1303 ++ .../arm64/nvidia/tegra210-p2595.dtsi | 1273 ++ .../arm64/nvidia/tegra210-p2597.dtsi | 1616 ++ .../arm64/nvidia/tegra210-smaug.dts | 1860 +++ .../arm64/nvidia/tegra210.dtsi | 1372 ++ .../dtc/include-prefixes/arm64/qcom/Makefile | 344 + .../arm64/qcom/OP-fg-batterydata-3700mah.dtsi | 144 + .../arm64/qcom/OP-fg-batterydata-3800mah.dtsi | 144 + .../arm64/qcom/OP-fg-batterydata-4000mah.dtsi | 145 + .../arm64/qcom/OP-fg-batterydata-4085mah.dtsi | 145 + .../arm64/qcom/apq8016-sbc-pmic-pins.dtsi | 55 + .../arm64/qcom/apq8016-sbc-soc-pins.dtsi | 89 + .../arm64/qcom/apq8016-sbc.dts | 21 + .../arm64/qcom/apq8016-sbc.dtsi | 502 + .../arm64/qcom/apq8096-db820c-pins.dtsi | 39 + .../arm64/qcom/apq8096-db820c-pmic-pins.dtsi | 52 + .../arm64/qcom/apq8096-db820c.dts | 21 + .../arm64/qcom/apq8096-db820c.dtsi | 307 + .../arm64/qcom/atoll-coresight.dtsi | 2979 ++++ .../arm64/qcom/atoll-gdsc.dtsi | 162 + .../arm64/qcom/atoll-idp-overlay.dts | 25 + .../include-prefixes/arm64/qcom/atoll-idp.dts | 22 + .../arm64/qcom/atoll-idp.dtsi | 107 + .../arm64/qcom/atoll-ion.dtsi | 41 + .../arm64/qcom/atoll-pinctrl.dtsi | 250 + .../include-prefixes/arm64/qcom/atoll-pm.dtsi | 170 + .../arm64/qcom/atoll-qrd-overlay.dts | 23 + .../include-prefixes/arm64/qcom/atoll-qrd.dts | 22 + .../arm64/qcom/atoll-qrd.dtsi | 14 + .../arm64/qcom/atoll-qupv3.dtsi | 62 + .../arm64/qcom/atoll-rumi-overlay.dts | 25 + .../arm64/qcom/atoll-rumi.dts | 22 + .../arm64/qcom/atoll-rumi.dtsi | 144 + .../arm64/qcom/atoll-stub-regulator.dtsi | 405 + .../arm64/qcom/atoll-thermal.dtsi | 621 + .../arm64/qcom/atoll-usb.dtsi | 372 + .../arm64/qcom/atoll-vidc.dtsi | 106 + .../dtc/include-prefixes/arm64/qcom/atoll.dts | 22 + .../include-prefixes/arm64/qcom/atoll.dtsi | 2486 +++ .../arm64/qcom/dm-verity-boot.dtsi | 28 + .../qcom/dsi-panel-ext-bridge-1080p.dtsi | 52 + .../qcom/dsi-panel-ext-bridge-hdmi-1080p.dtsi | 52 + ...l-hx83112a-truly-singlemipi-fhd-video.dtsi | 159 + .../qcom/dsi-panel-hx8394d-720p-video.dtsi | 99 + ...dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi | 247 + ...i-panel-nt35597-truly-dsc-wqxga-video.dtsi | 233 + ...anel-nt35597-truly-dualmipi-wqxga-cmd.dtsi | 226 + ...el-nt35597-truly-dualmipi-wqxga-video.dtsi | 213 + .../dsi-panel-nt35695b-truly-fhd-cmd.dtsi | 188 + .../dsi-panel-nt35695b-truly-fhd-video.dtsi | 184 + .../dsi-panel-nt36672-truly-fhd-video.dtsi | 282 + ...panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi | 87 + ...nel-rm69298-truly-amoled-fhd-plus-cmd.dtsi | 330 + ...l-rm69298-truly-amoled-fhd-plus-video.dtsi | 330 + ...m69299-visionox-amoled-fhd-plus-video.dtsi | 75 + ...anel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi | 141 + .../qcom/dsi-panel-samsung_findx_dsc.dtsi | 177 + .../qcom/dsi-panel-samsung_oneplus_dsc.dtsi | 2665 ++++ .../qcom/dsi-panel-samsung_s6e3fc2x01.dtsi | 435 + .../dsi-panel-samsung_sofef00_m_video.dtsi | 103 + ...-panel-samsung_sofef03f_m_fhd_dsc_cmd.dtsi | 848 + .../arm64/qcom/dsi-panel-sharp-1080p-cmd.dtsi | 86 + .../qcom/dsi-panel-sharp-dsc-4k-cmd.dtsi | 103 + .../qcom/dsi-panel-sharp-dsc-4k-video.dtsi | 96 + .../dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi | 93 + .../dsi-panel-sharp-dualdsi-wqhd-video.dtsi | 89 + .../dsi-panel-sharp-dualmipi-1080p-120hz.dtsi | 633 + ...si-panel-sharp-split-link-wuxga-video.dtsi | 74 + .../arm64/qcom/dsi-panel-sim-cmd.dtsi | 220 + .../arm64/qcom/dsi-panel-sim-dsc375-cmd.dtsi | 286 + .../qcom/dsi-panel-sim-dualmipi-cmd.dtsi | 146 + .../dsi-panel-sim-dualmipi-dsc375-cmd.dtsi | 281 + .../qcom/dsi-panel-sim-dualmipi-video.dtsi | 70 + .../arm64/qcom/dsi-panel-sim-sec-hd-cmd.dtsi | 75 + .../arm64/qcom/dsi-panel-sim-video.dtsi | 69 + ...panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi | 111 + ...dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi | 130 + ...i-panel-sw43404-amoled-dsc-wqhd-video.dtsi | 95 + .../qcom/dsi-panel-td4328-1080p-cmd.dtsi | 177 + .../qcom/dsi-panel-td4328-1080p-video.dtsi | 172 + ...panel-td4330-truly-singlemipi-fhd-cmd.dtsi | 316 + ...nel-td4330-truly-singlemipi-fhd-video.dtsi | 315 + .../fg-gen4-batterydata-alium-3600mah.dtsi | 154 + ...fg-gen4-batterydata-mlp466076-3250mah.dtsi | 149 + .../arm64/qcom/guacamole-overlay-dvt.dts | 43 + .../arm64/qcom/guacamole-overlay-evt1.dts | 39 + .../qcom/guacamole-overlay-evt2-second.dts | 40 + .../arm64/qcom/guacamole-overlay-evt2.dts | 40 + .../arm64/qcom/guacamole-overlay-evt3.dts | 41 + .../arm64/qcom/guacamole-overlay-pvt.dts | 44 + .../arm64/qcom/guacamole-overlay-t0.dts | 39 + .../qcom/guacamole-sdx50m-overlay-dvt.dts | 46 + .../qcom/guacamole-sdx50m-overlay-evt1.dts | 44 + .../qcom/guacamole-sdx50m-overlay-evt2.dts | 45 + .../qcom/guacamole-sdx50m-overlay-pvt.dts | 47 + .../qcom/guacamole-sdx50m-overlay-t0.dts | 43 + .../arm64/qcom/guacamole.dtsi | 166 + .../arm64/qcom/guacamole_dvt.dtsi | 1 + .../arm64/qcom/guacamole_evt1.dtsi | 2 + .../arm64/qcom/guacamole_evt2.dtsi | 2 + .../arm64/qcom/guacamole_evt3.dtsi | 2 + .../arm64/qcom/guacamole_pvt.dtsi | 1 + .../arm64/qcom/guacamole_sdx50m.dtsi | 17 + .../arm64/qcom/guacamole_sm8150.dtsi | 8 + .../arm64/qcom/guacamole_t0.dtsi | 99 + .../arm64/qcom/guacamoleb-overlay-dvt.dts | 39 + .../arm64/qcom/guacamoleb-overlay-evt.dts | 39 + .../arm64/qcom/guacamoleb-overlay-pvt.dts | 39 + .../arm64/qcom/guacamoleb-overlay-t0.dts | 39 + .../arm64/qcom/guacamoleb.dtsi | 490 + .../arm64/qcom/guacamoleb_dvt.dtsi | 1 + .../arm64/qcom/guacamoleb_evt.dtsi | 1 + .../arm64/qcom/guacamoleb_pvt.dtsi | 1 + .../arm64/qcom/guacamoleb_sm8150.dtsi | 7 + .../arm64/qcom/guacamoleb_t0.dtsi | 4 + .../qcom/guacamoles-sdx50m-overlay-dvt.dts | 45 + .../qcom/guacamoles-sdx50m-overlay-evt.dts | 45 + .../qcom/guacamoles-sdx50m-overlay-pvt.dts | 45 + .../qcom/guacamoles-sdx50m-overlay-t0.dts | 44 + .../arm64/qcom/guacamoles_sdx50m.dtsi | 11 + .../arm64/qcom/guacamoles_sdx50m_dvt.dtsi | 2 + .../arm64/qcom/guacamoles_sdx50m_evt.dtsi | 1 + .../arm64/qcom/guacamoles_sdx50m_pvt.dtsi | 1 + .../arm64/qcom/guacamoles_sdx50m_t0.dtsi | 1 + .../arm64/qcom/ipq8074-hk01.dts | 52 + .../include-prefixes/arm64/qcom/ipq8074.dtsi | 194 + .../arm64/qcom/msm-arm-smmu-atoll.dtsi | 204 + .../arm64/qcom/msm-arm-smmu-qcs405.dtsi | 92 + .../arm64/qcom/msm-arm-smmu-sdmmagpie.dtsi | 358 + .../arm64/qcom/msm-arm-smmu-sdmshrike.dtsi | 444 + .../arm64/qcom/msm-arm-smmu-sdxprairie.dtsi | 102 + .../arm64/qcom/msm-arm-smmu-sm6150.dtsi | 317 + .../arm64/qcom/msm-arm-smmu-sm8150-v2.dtsi | 406 + .../arm64/qcom/msm-arm-smmu-sm8150.dtsi | 420 + .../arm64/qcom/msm-arm-smmu-trinket.dtsi | 280 + .../arm64/qcom/msm-audio-lpass.dtsi | 738 + .../arm64/qcom/msm-qvr-external.dtsi | 21 + .../include-prefixes/arm64/qcom/msm-rdbg.dtsi | 35 + .../arm64/qcom/msm-wsa881x.dtsi | 77 + .../arm64/qcom/msm8916-mtp.dts | 22 + .../arm64/qcom/msm8916-mtp.dtsi | 35 + .../arm64/qcom/msm8916-pins.dtsi | 736 + .../include-prefixes/arm64/qcom/msm8916.dtsi | 1461 ++ .../arm64/qcom/msm8992-bullhead-rev-101.dts | 41 + .../arm64/qcom/msm8992-pins.dtsi | 38 + .../include-prefixes/arm64/qcom/msm8992.dtsi | 237 + .../arm64/qcom/msm8994-angler-rev-101.dts | 40 + .../arm64/qcom/msm8994-pins.dtsi | 38 + .../include-prefixes/arm64/qcom/msm8994.dtsi | 216 + .../arm64/qcom/msm8996-mtp.dts | 21 + .../arm64/qcom/msm8996-mtp.dtsi | 30 + .../arm64/qcom/msm8996-pins.dtsi | 303 + .../include-prefixes/arm64/qcom/msm8996.dtsi | 925 ++ .../arm64/qcom/pm6125-rpm-regulator.dtsi | 505 + .../include-prefixes/arm64/qcom/pm6125.dtsi | 224 + .../include-prefixes/arm64/qcom/pm6150.dtsi | 665 + .../include-prefixes/arm64/qcom/pm6150l.dtsi | 514 + .../include-prefixes/arm64/qcom/pm6155.dtsi | 175 + .../include-prefixes/arm64/qcom/pm8004.dtsi | 20 + .../include-prefixes/arm64/qcom/pm8008.dtsi | 117 + .../include-prefixes/arm64/qcom/pm8009.dtsi | 47 + .../include-prefixes/arm64/qcom/pm8150.dtsi | 194 + .../include-prefixes/arm64/qcom/pm8150b.dtsi | 703 + .../include-prefixes/arm64/qcom/pm8150l.dtsi | 516 + .../include-prefixes/arm64/qcom/pm8195.dtsi | 251 + .../include-prefixes/arm64/qcom/pm8916.dtsi | 143 + .../include-prefixes/arm64/qcom/pm8994.dtsi | 71 + .../include-prefixes/arm64/qcom/pmi632.dtsi | 737 + .../include-prefixes/arm64/qcom/pmi8994.dtsi | 37 + .../arm64/qcom/pms405-rpm-regulator.dtsi | 317 + .../include-prefixes/arm64/qcom/pms405.dtsi | 207 + .../arm64/qcom/pmxprairie.dtsi | 209 + .../arm64/qcom/qcs401-iot-sku1.dts | 81 + .../include-prefixes/arm64/qcom/qcs401.dtsi | 48 + .../arm64/qcom/qcs403-ext-pll-audio.dtsi | 29 + .../arm64/qcom/qcs403-iot-sku1.dts | 88 + .../arm64/qcom/qcs403-iot-sku2.dts | 124 + .../arm64/qcom/qcs403-iot-sku3.dts | 150 + .../arm64/qcom/qcs403-iot-sku4.dts | 126 + .../include-prefixes/arm64/qcom/qcs403.dtsi | 61 + .../arm64/qcom/qcs405-amic-audio-overlay.dtsi | 40 + .../arm64/qcom/qcs405-audio-overlay.dtsi | 103 + .../arm64/qcom/qcs405-audio.dtsi | 193 + .../arm64/qcom/qcs405-blsp.dtsi | 526 + .../arm64/qcom/qcs405-bus.dtsi | 895 ++ .../arm64/qcom/qcs405-circular-pca9956.dtsi | 246 + .../arm64/qcom/qcs405-coresight.dtsi | 1089 ++ .../arm64/qcom/qcs405-cpu.dtsi | 192 + .../qcom/qcs405-csra1-audio-overlay.dtsi | 134 + .../arm64/qcom/qcs405-csra1.dtsi | 34 + .../qcom/qcs405-csra6-audio-overlay.dtsi | 145 + .../arm64/qcom/qcs405-csra6.dtsi | 95 + .../qcom/qcs405-csra8-audio-overlay.dtsi | 150 + .../arm64/qcom/qcs405-csra8.dtsi | 118 + .../arm64/qcom/qcs405-gdsc.dtsi | 29 + .../arm64/qcom/qcs405-geni-ir-overlay.dtsi | 35 + .../arm64/qcom/qcs405-gpu.dtsi | 187 + .../arm64/qcom/qcs405-ion.dtsi | 43 + .../arm64/qcom/qcs405-iot-sku1.dts | 87 + .../arm64/qcom/qcs405-iot-sku10.dts | 62 + .../arm64/qcom/qcs405-iot-sku11.dts | 79 + .../arm64/qcom/qcs405-iot-sku12.dts | 36 + .../arm64/qcom/qcs405-iot-sku2.dts | 192 + .../arm64/qcom/qcs405-iot-sku3.dts | 8 +- .../arm64/qcom/qcs405-iot-sku4.dts | 85 + .../arm64/qcom/qcs405-iot-sku5.dts | 97 + .../arm64/qcom/qcs405-iot-sku6.dts | 72 + .../arm64/qcom/qcs405-iot-sku7.dts | 63 + .../arm64/qcom/qcs405-iot-sku8.dts | 63 + .../arm64/qcom/qcs405-iot-sku9.dts | 73 + .../arm64/qcom/qcs405-linear-pca9956.dtsi | 250 + .../arm64/qcom/qcs405-lpi.dtsi | 484 + .../arm64/qcom/qcs405-mdss-panels.dtsi | 31 + .../arm64/qcom/qcs405-mdss-pll.dtsi | 126 + .../arm64/qcom/qcs405-mdss.dtsi | 466 + .../arm64/qcom/qcs405-mhi.dtsi | 716 + .../qcom/qcs405-nowcd-audio-overlay.dtsi | 85 + .../arm64/qcom/qcs405-pcie.dtsi | 138 + .../arm64/qcom/qcs405-pinctrl.dtsi | 2478 +++ .../arm64/qcom/qcs405-pm.dtsi | 140 + .../arm64/qcom/qcs405-regulator.dtsi | 383 + .../arm64/qcom/qcs405-rumi.dts | 27 + .../arm64/qcom/qcs405-rumi.dtsi | 134 + .../arm64/qcom/qcs405-stub-regulator.dtsi | 194 + .../arm64/qcom/qcs405-tasha.dtsi | 113 + .../arm64/qcom/qcs405-tdm-audio-overlay.dtsi | 87 + .../arm64/qcom/qcs405-thermal.dtsi | 417 + .../arm64/qcom/qcs405-usb.dtsi | 216 + .../arm64/qcom/qcs405-va-bolero.dtsi | 38 + .../arm64/qcom/qcs405-wsa-audio-overlay.dtsi | 127 + .../arm64/qcom/qcs405-wsa-bolero.dtsi | 40 + .../arm64/qcom/qcs405-wsa881x.dtsi | 61 + .../include-prefixes/arm64/qcom/qcs405.dtsi | 1691 ++ .../arm64/qcom/qcs410-iot-overlay.dts | 23 + .../arm64/qcom/qcs410-iot.dts | 22 + .../arm64/qcom/qcs410-iot.dtsi | 165 + .../include-prefixes/arm64/qcom/qcs410.dts | 21 + .../include-prefixes/arm64/qcom/qcs410.dtsi | 137 + .../arm64/qcom/qcs610-camera-sensor-idp.dtsi | 98 + .../arm64/qcom/qcs610-iot-overlay.dts | 25 + .../arm64/qcom/qcs610-iot.dts | 26 + .../arm64/qcom/qcs610-iot.dtsi | 447 + .../include-prefixes/arm64/qcom/qcs610.dts | 21 + .../include-prefixes/arm64/qcom/qcs610.dtsi | 29 + .../qcom/qg-batterydata-alium-3600mah.dtsi | 1048 ++ .../qcom/qg-batterydata-ascent-3450mah.dtsi | 1042 ++ .../qg-batterydata-mlp356477-2800mah.dtsi | 1044 ++ .../qg-batterydata-mlp466076-3200mah.dtsi | 1044 ++ .../arm64/qcom/quin-vm-common.dtsi | 251 + .../arm64/qcom/rgb-panel-st7789v.dtsi | 30 + .../arm64/qcom/sa515m-ccard-pcie-ep.dts | 46 + .../arm64/qcom/sa515m-ccard-usb-ep.dts | 22 + .../arm64/qcom/sa515m-ccard.dts | 22 + .../arm64/qcom/sa515m-ccard.dtsi | 132 + .../arm64/qcom/sa6155-adp-air-overlay.dts | 25 + .../arm64/qcom/sa6155-adp-air.dts | 21 + .../arm64/qcom/sa6155-adp-air.dtsi | 267 + .../arm64/qcom/sa6155-adp-star-overlay.dts | 25 + .../arm64/qcom/sa6155-adp-star.dts | 21 + .../arm64/qcom/sa6155-adp-star.dtsi | 275 + .../arm64/qcom/sa6155-audio.dtsi | 597 + .../arm64/qcom/sa6155-cnss.dtsi | 223 + .../arm64/qcom/sa6155-display.dtsi | 227 + .../arm64/qcom/sa6155-pcie.dtsi | 253 + .../arm64/qcom/sa6155-pmic.dtsi | 319 + .../arm64/qcom/sa6155-regulator.dtsi | 537 + .../include-prefixes/arm64/qcom/sa6155.dts | 22 + .../include-prefixes/arm64/qcom/sa6155.dtsi | 485 + .../arm64/qcom/sa6155p-adp-air-overlay.dts | 26 + .../arm64/qcom/sa6155p-adp-air.dts | 22 + .../arm64/qcom/sa6155p-adp-star-overlay.dts | 26 + .../arm64/qcom/sa6155p-adp-star.dts | 22 + .../arm64/qcom/sa6155p-v2-adp-air-overlay.dts | 26 + .../arm64/qcom/sa6155p-v2-adp-air.dts | 22 + .../qcom/sa6155p-v2-adp-star-overlay.dts | 26 + .../arm64/qcom/sa6155p-v2-adp-star.dts | 22 + .../arm64/qcom/sa6155p-vm-pcie.dtsi | 245 + .../arm64/qcom/sa6155p-vm-pinctrl.dtsi | 1783 +++ .../arm64/qcom/sa6155p-vm-qupv3.dtsi | 450 + .../arm64/qcom/sa6155p-vm-usb.dtsi | 404 + .../arm64/qcom/sa6155p-vm.dts | 52 + .../arm64/qcom/sa6155p-vm.dtsi | 351 + .../include-prefixes/arm64/qcom/sa6155p.dts | 22 + .../include-prefixes/arm64/qcom/sa6155p.dtsi | 517 + .../arm64/qcom/sa8155-adp-alcor-display.dtsi | 91 + .../arm64/qcom/sa8155-adp-alcor-overlay.dts | 23 + .../arm64/qcom/sa8155-adp-alcor.dts | 22 + .../arm64/qcom/sa8155-adp-alcor.dtsi | 98 + .../arm64/qcom/sa8155-adp-common.dtsi | 249 + .../arm64/qcom/sa8155-adp-star-display.dtsi | 319 + .../arm64/qcom/sa8155-adp-star-overlay.dts | 25 + .../arm64/qcom/sa8155-adp-star.dts | 22 + .../arm64/qcom/sa8155-adp-star.dtsi | 52 + .../arm64/qcom/sa8155-audio.dtsi | 614 + .../arm64/qcom/sa8155-camera-sensor.dtsi | 143 + .../arm64/qcom/sa8155-cnss.dtsi | 350 + .../arm64/qcom/sa8155-pmic-overlay.dtsi | 125 + .../arm64/qcom/sa8155-regulator.dtsi | 726 + .../arm64/qcom/sa8155-v1.dtsi | 21 + .../arm64/qcom/sa8155-v2-adp-air-overlay.dts | 24 + .../arm64/qcom/sa8155-v2-adp-air.dts | 23 + .../arm64/qcom/sa8155-v2-adp-star.dts | 22 + .../include-prefixes/arm64/qcom/sa8155-v2.dts | 26 + .../arm64/qcom/sa8155-v2.dtsi | 147 + .../arm64/qcom/sa8155-vm-audio.dtsi | 534 + .../arm64/qcom/sa8155-vm-la-mt.dts | 30 + .../arm64/qcom/sa8155-vm-lv-mt.dts | 59 + .../arm64/qcom/sa8155-vm-lv.dts | 47 + .../arm64/qcom/sa8155-vm-mhi.dtsi | 551 + .../arm64/qcom/sa8155-vm-pcie.dtsi | 279 + .../arm64/qcom/sa8155-vm-pinctrl.dtsi | 25 + .../arm64/qcom/sa8155-vm-qupv3.dtsi | 960 ++ .../arm64/qcom/sa8155-vm-usb.dtsi | 542 + .../include-prefixes/arm64/qcom/sa8155-vm.dts | 43 + .../arm64/qcom/sa8155-vm.dtsi | 496 + .../include-prefixes/arm64/qcom/sa8155.dts | 26 + .../include-prefixes/arm64/qcom/sa8155.dtsi | 610 + .../arm64/qcom/sa8155p-adp-alcor-overlay.dts | 23 + .../arm64/qcom/sa8155p-adp-alcor.dts | 23 + .../arm64/qcom/sa8155p-adp-star-overlay.dts | 25 + .../arm64/qcom/sa8155p-adp-star.dts | 22 + .../arm64/qcom/sa8155p-v2-adp-air-overlay.dts | 24 + .../arm64/qcom/sa8155p-v2-adp-air.dts | 23 + .../arm64/qcom/sa8155p-v2-adp-star.dts | 22 + .../arm64/qcom/sa8155p-v2.dts | 26 + .../arm64/qcom/sa8155p-v2.dtsi | 19 + .../include-prefixes/arm64/qcom/sa8155p.dts | 26 + .../include-prefixes/arm64/qcom/sa8155p.dtsi | 20 + .../arm64/qcom/sa8195-pmic.dtsi | 121 + .../include-prefixes/arm64/qcom/sa8195-vm.dts | 38 + .../arm64/qcom/sa8195-vm.dtsi | 207 + .../arm64/qcom/sa8195p-adp-star-display.dtsi | 306 + .../arm64/qcom/sa8195p-adp-star-overlay.dts | 23 + .../arm64/qcom/sa8195p-adp-star.dts | 22 + .../arm64/qcom/sa8195p-adp-star.dtsi | 36 + .../arm64/qcom/sa8195p-pcie.dtsi | 805 + .../arm64/qcom/sa8195p-regulator.dtsi | 850 + .../include-prefixes/arm64/qcom/sa8195p.dts | 22 + .../include-prefixes/arm64/qcom/sa8195p.dtsi | 108 + .../arm64/qcom/sdmmagpie-atp-overlay.dts | 32 + .../arm64/qcom/sdmmagpie-atp.dts | 22 + .../arm64/qcom/sdmmagpie-atp.dtsi | 387 + .../arm64/qcom/sdmmagpie-audio-overlay.dtsi | 32 + .../arm64/qcom/sdmmagpie-audio.dtsi | 18 + .../arm64/qcom/sdmmagpie-bus.dtsi | 2032 +++ .../qcom/sdmmagpie-camera-sensor-idp.dtsi | 617 + .../qcom/sdmmagpie-camera-sensor-qrd.dtsi | 169 +- .../arm64/qcom/sdmmagpie-camera.dtsi | 1241 ++ .../arm64/qcom/sdmmagpie-coresight.dtsi | 2721 ++++ .../sdmmagpie-dual-display-idp-overlay.dts | 40 + .../arm64/qcom/sdmmagpie-dual-display-idp.dts | 35 + .../sdmmagpie-ext-codec-audio-overlay.dtsi | 26 + .../sdmmagpie-external-codec-idp-overlay.dts | 28 + .../qcom/sdmmagpie-external-codec-idp.dts | 24 + .../arm64/qcom/sdmmagpie-external-codec.dtsi | 14 + .../arm64/qcom/sdmmagpie-gdsc.dtsi | 230 + .../arm64/qcom/sdmmagpie-gpu.dtsi | 608 + .../arm64/qcom/sdmmagpie-idp-overlay.dts | 31 + .../arm64/qcom/sdmmagpie-idp.dts | 26 + .../arm64/qcom/sdmmagpie-idp.dtsi | 432 + .../arm64/qcom/sdmmagpie-ion.dtsi | 62 + .../arm64/qcom/sdmmagpie-npu.dtsi | 191 + .../arm64/qcom/sdmmagpie-pinctrl.dtsi | 1683 ++ .../arm64/qcom/sdmmagpie-pm.dtsi | 170 + .../arm64/qcom/sdmmagpie-qrd-overlay.dts | 70 + .../arm64/qcom/sdmmagpie-qrd.dts | 22 + .../arm64/qcom/sdmmagpie-qrd.dtsi | 431 + .../arm64/qcom/sdmmagpie-qupv3.dtsi | 565 + .../arm64/qcom/sdmmagpie-regulator.dtsi | 890 ++ .../arm64/qcom/sdmmagpie-rumi-overlay.dts | 26 + .../arm64/qcom/sdmmagpie-rumi.dts | 22 + .../arm64/qcom/sdmmagpie-rumi.dtsi | 192 + .../arm64/qcom/sdmmagpie-sde-display.dtsi | 742 + .../arm64/qcom/sdmmagpie-sde-pll.dtsi | 114 + .../arm64/qcom/sdmmagpie-sde.dtsi | 690 + .../arm64/qcom/sdmmagpie-stub-regulator.dtsi | 352 + .../arm64/qcom/sdmmagpie-thermal-overlay.dtsi | 182 + .../arm64/qcom/sdmmagpie-thermal.dtsi | 1912 +++ .../arm64/qcom/sdmmagpie-usb.dtsi | 375 + .../arm64/qcom/sdmmagpie-usbc-idp-overlay.dts | 26 + .../arm64/qcom/sdmmagpie-usbc-idp.dts | 23 + .../arm64/qcom/sdmmagpie-usbc-idp.dtsi | 19 + .../arm64/qcom/sdmmagpie-vidc.dtsi | 219 + .../include-prefixes/arm64/qcom/sdmmagpie.dts | 22 + .../arm64/qcom/sdmmagpie.dtsi | 3472 ++++ .../arm64/qcom/sdmmagpiep-atp-overlay.dts | 26 + .../arm64/qcom/sdmmagpiep-atp.dts | 22 + .../arm64/qcom/sdmmagpiep-idp-overlay.dts | 26 + .../arm64/qcom/sdmmagpiep-idp.dts | 22 + .../arm64/qcom/sdmmagpiep-qrd-overlay.dts | 25 + .../arm64/qcom/sdmmagpiep-qrd.dts | 22 + .../arm64/qcom/sdmmagpiep.dts | 22 + .../arm64/qcom/sdmmagpiep.dtsi | 19 + .../arm64/qcom/sdmshrike-audio-overlay.dtsi | 307 + .../arm64/qcom/sdmshrike-bus.dtsi | 2148 +++ .../arm64/qcom/sdmshrike-cdp-overlay.dts | 26 + .../arm64/qcom/sdmshrike-cdp.dts | 22 + .../arm64/qcom/sdmshrike-cdp.dtsi | 123 + .../arm64/qcom/sdmshrike-gdsc.dtsi | 60 + .../arm64/qcom/sdmshrike-gpu.dtsi | 393 + .../arm64/qcom/sdmshrike-ion.dtsi | 65 + .../arm64/qcom/sdmshrike-mtp-overlay.dts | 26 + .../arm64/qcom/sdmshrike-mtp.dts | 22 + .../arm64/qcom/sdmshrike-mtp.dtsi | 156 + .../arm64/qcom/sdmshrike-pinctrl.dtsi | 4246 +++++ .../arm64/qcom/sdmshrike-pmic-overlay.dtsi | 111 + .../arm64/qcom/sdmshrike-qupv3.dtsi | 989 ++ .../arm64/qcom/sdmshrike-regulators.dtsi | 971 ++ .../arm64/qcom/sdmshrike-rumi.dts | 23 + .../arm64/qcom/sdmshrike-rumi.dtsi | 73 + .../arm64/qcom/sdmshrike-sde-display.dtsi | 615 + .../arm64/qcom/sdmshrike-sde-pll.dtsi | 92 + .../arm64/qcom/sdmshrike-sde.dtsi | 717 + .../arm64/qcom/sdmshrike-smp2p.dtsi | 96 + .../arm64/qcom/sdmshrike-thermal-overlay.dtsi | 166 + .../arm64/qcom/sdmshrike-thermal.dtsi | 1367 ++ .../arm64/qcom/sdmshrike-usb.dtsi | 242 + .../arm64/qcom/sdmshrike-v2-mtp.dts | 22 + .../arm64/qcom/sdmshrike-v2.dts | 22 + .../arm64/qcom/sdmshrike-v2.dtsi | 262 + .../include-prefixes/arm64/qcom/sdmshrike.dts | 22 + .../arm64/qcom/sdmshrike.dtsi | 2513 +++ .../arm64/qcom/sdx-audio-lpass.dtsi | 345 + .../arm64/qcom/sdx-wsa881x.dtsi | 45 + .../arm64/qcom/sdx5xm-external-soc.dtsi | 59 + .../arm64/qcom/sdxprairie-aqc.dtsi | 95 + .../arm64/qcom/sdxprairie-audio-overlay.dtsi | 143 + .../arm64/qcom/sdxprairie-audio.dtsi | 55 + .../arm64/qcom/sdxprairie-blsp.dtsi | 572 + .../arm64/qcom/sdxprairie-bus.dtsi | 958 ++ .../arm64/qcom/sdxprairie-cdp-256.dts | 31 + .../arm64/qcom/sdxprairie-cdp-256.dtsi | 182 + .../qcom/sdxprairie-cdp-audio-overlay.dtsi | 22 + .../arm64/qcom/sdxprairie-cdp-cpe.dts | 24 + .../arm64/qcom/sdxprairie-cdp-cpe.dtsi | 22 + .../arm64/qcom/sdxprairie-cdp.dts | 31 + .../arm64/qcom/sdxprairie-cdp.dtsi | 213 + .../arm64/qcom/sdxprairie-coresight.dtsi | 1283 ++ .../arm64/qcom/sdxprairie-dsda-cdp.dts | 56 + .../arm64/qcom/sdxprairie-dsda-mtp.dts | 56 + .../arm64/qcom/sdxprairie-gdsc.dtsi | 36 + .../arm64/qcom/sdxprairie-ion.dtsi | 41 + .../arm64/qcom/sdxprairie-mtp-256.dts | 31 + .../arm64/qcom/sdxprairie-mtp-256.dtsi | 224 + .../arm64/qcom/sdxprairie-mtp-aqc.dts | 31 + .../qcom/sdxprairie-mtp-audio-overlay.dtsi | 22 + .../arm64/qcom/sdxprairie-mtp-cpe.dts | 55 + .../arm64/qcom/sdxprairie-mtp-cpe.dtsi | 18 + .../arm64/qcom/sdxprairie-mtp.dts | 31 + .../arm64/qcom/sdxprairie-mtp.dtsi | 245 + .../arm64/qcom/sdxprairie-pcie-ep-mtp.dts | 24 + .../arm64/qcom/sdxprairie-pcie-ep-mtp.dtsi | 42 + .../arm64/qcom/sdxprairie-pcie.dtsi | 250 + .../arm64/qcom/sdxprairie-pinctrl.dtsi | 1477 ++ .../arm64/qcom/sdxprairie-pm.dtsi | 102 + .../arm64/qcom/sdxprairie-pmic-overlay.dtsi | 51 + .../arm64/qcom/sdxprairie-regulator.dtsi | 511 + .../arm64/qcom/sdxprairie-rumi.dts | 31 + .../arm64/qcom/sdxprairie-rumi.dtsi | 91 + .../arm64/qcom/sdxprairie-thermal.dtsi | 428 + .../arm64/qcom/sdxprairie-usb.dtsi | 285 + .../arm64/qcom/sdxprairie-v2-cdp.dts | 23 + .../arm64/qcom/sdxprairie-v2-mtp.dts | 25 + .../arm64/qcom/sdxprairie-v2.dtsi | 31 + .../arm64/qcom/sdxprairie-wcd.dtsi | 80 + .../arm64/qcom/sdxprairie.dtsi | 1519 ++ .../include-prefixes/arm64/qcom/skeleton.dtsi | 18 + .../arm64/qcom/skeleton64.dtsi | 15 + .../arm64/qcom/sm6150-audio-overlay.dtsi | 505 + .../arm64/qcom/sm6150-audio.dtsi | 155 + .../arm64/qcom/sm6150-bus.dtsi | 1850 +++ .../arm64/qcom/sm6150-camera-sensor-adp.dtsi | 115 + .../arm64/qcom/sm6150-camera-sensor-idp.dtsi | 624 + .../arm64/qcom/sm6150-camera-sensor-qrd.dtsi | 364 + .../arm64/qcom/sm6150-camera.dtsi | 1076 ++ .../sm6150-cmd-mode-display-idp-overlay.dts | 62 + .../qcom/sm6150-cmd-mode-display-idp.dts | 22 + .../arm64/qcom/sm6150-coresight.dtsi | 2774 ++++ .../qcom/sm6150-ext-codec-audio-overlay.dtsi | 89 + .../sm6150-external-codec-idp-overlay.dts | 32 + .../arm64/qcom/sm6150-external-codec-idp.dts | 24 + .../arm64/qcom/sm6150-external-codec.dtsi | 151 + .../arm64/qcom/sm6150-gdsc.dtsi | 213 + .../arm64/qcom/sm6150-gpu.dtsi | 651 + .../arm64/qcom/sm6150-idp-overlay.dts | 31 + .../arm64/qcom/sm6150-idp.dts | 23 + .../arm64/qcom/sm6150-idp.dtsi | 403 + .../sm6150-interposer-trinket-idp-overlay.dts | 29 + .../qcom/sm6150-interposer-trinket-idp.dts | 23 + .../qcom/sm6150-interposer-trinket-idp.dtsi | 130 + .../sm6150-interposer-trinket-qrd-overlay.dts | 23 + .../qcom/sm6150-interposer-trinket-qrd.dts | 23 + .../qcom/sm6150-interposer-trinket-qrd.dtsi | 182 + .../arm64/qcom/sm6150-interposer-trinket.dts | 22 + .../arm64/qcom/sm6150-interposer-trinket.dtsi | 54 + .../arm64/qcom/sm6150-ion.dtsi | 68 + .../arm64/qcom/sm6150-lpi.dtsi | 331 + .../arm64/qcom/sm6150-pinctrl.dtsi | 2263 +++ .../arm64/qcom/sm6150-pm.dtsi | 163 + .../sm6150-pm6125-interposer-trinket.dtsi | 721 + .../arm64/qcom/sm6150-qrd-overlay.dts | 67 + .../arm64/qcom/sm6150-qrd.dts | 22 + .../arm64/qcom/sm6150-qrd.dtsi | 291 + .../arm64/qcom/sm6150-qupv3.dtsi | 503 + .../arm64/qcom/sm6150-regulator.dtsi | 762 + .../arm64/qcom/sm6150-rumi-overlay.dts | 26 + .../arm64/qcom/sm6150-rumi.dts | 23 + .../arm64/qcom/sm6150-rumi.dtsi | 206 + .../arm64/qcom/sm6150-sde-display.dtsi | 548 + .../arm64/qcom/sm6150-sde-pll.dtsi | 83 + .../arm64/qcom/sm6150-sde.dtsi | 579 + .../arm64/qcom/sm6150-slpi-pinctrl.dtsi | 461 + .../arm64/qcom/sm6150-stub-regulator.dtsi | 345 + .../arm64/qcom/sm6150-thermal-overlay.dtsi | 182 + .../arm64/qcom/sm6150-thermal.dtsi | 2087 +++ .../arm64/qcom/sm6150-usb.dtsi | 436 + .../arm64/qcom/sm6150-usbc-idp-overlay.dts | 31 + .../arm64/qcom/sm6150-usbc-idp.dts | 23 + .../arm64/qcom/sm6150-usbc-idp.dtsi | 19 + .../qcom/sm6150-usbc-minidp-idp-overlay.dts | 32 + .../arm64/qcom/sm6150-usbc-minidp-idp.dts | 28 + .../arm64/qcom/sm6150-vidc.dtsi | 109 + .../arm64/qcom/sm6150-wcd.dtsi | 168 + .../include-prefixes/arm64/qcom/sm6150.dts | 22 + .../include-prefixes/arm64/qcom/sm6150.dtsi | 3245 ++++ .../arm64/qcom/sm6150p-idp-overlay.dts | 31 + .../arm64/qcom/sm6150p-idp.dts | 22 + .../arm64/qcom/sm6150p-qrd-overlay.dts | 26 + .../arm64/qcom/sm6150p-qrd.dts | 22 + .../include-prefixes/arm64/qcom/sm6150p.dts | 22 + .../include-prefixes/arm64/qcom/sm6150p.dtsi | 19 + .../arm64/qcom/sm8150-audio-overlay.dtsi | 355 + .../arm64/qcom/sm8150-audio.dtsi | 183 + .../arm64/qcom/sm8150-bus.dtsi | 2180 +++ .../arm64/qcom/sm8150-camera-sensor-cdp.dtsi | 775 + .../arm64/qcom/sm8150-camera-sensor-hdk.dtsi | 425 + .../arm64/qcom/sm8150-camera-sensor-mtp.dtsi | 780 + .../arm64/qcom/sm8150-camera-sensor-qrd.dtsi | 415 + .../arm64/qcom/sm8150-camera.dtsi | 1248 ++ .../arm64/qcom/sm8150-cdp-audio-overlay.dtsi | 19 + .../arm64/qcom/sm8150-cdp-overlay.dts | 32 + .../arm64/qcom/sm8150-cdp.dts | 22 + .../arm64/qcom/sm8150-cdp.dtsi | 663 + .../arm64/qcom/sm8150-coresight.dtsi | 2795 ++++ .../arm64/qcom/sm8150-gdsc.dtsi | 267 + .../arm64/qcom/sm8150-gpu-v2.dtsi | 47 + .../arm64/qcom/sm8150-gpu.dtsi | 404 + .../arm64/qcom/sm8150-hdk-overlay.dts | 143 + .../arm64/qcom/sm8150-hdk.dts | 22 + .../arm64/qcom/sm8150-hdk.dtsi | 101 + .../arm64/qcom/sm8150-ion.dtsi | 74 + .../arm64/qcom/sm8150-mhi.dtsi | 1097 ++ .../arm64/qcom/sm8150-mtp-audio-overlay.dtsi | 18 + .../arm64/qcom/sm8150-mtp-overlay.dts | 32 + .../arm64/qcom/sm8150-mtp.dts | 22 + .../arm64/qcom/sm8150-mtp.dtsi | 686 + .../arm64/qcom/sm8150-npu.dtsi | 204 + .../qcom/sm8150-oem-camera-guacamoleb.dtsi | 889 ++ .../arm64/qcom/sm8150-oem-camera-ov.dtsi | 854 + .../arm64/qcom/sm8150-oem-camera-t0.dtsi | 1055 ++ .../arm64/qcom/sm8150-oem-camera-v2.dtsi | 1035 ++ .../arm64/qcom/sm8150-oem-camera.dtsi | 968 ++ .../arm64/qcom/sm8150-oem.dtsi | 1358 ++ .../arm64/qcom/sm8150-pcie.dtsi | 824 + .../arm64/qcom/sm8150-pinctrl.dtsi | 4577 ++++++ .../arm64/qcom/sm8150-pm.dtsi | 122 + .../arm64/qcom/sm8150-pmic-overlay.dtsi | 145 + .../arm64/qcom/sm8150-qrd-audio-overlay.dtsi | 57 + .../arm64/qcom/sm8150-qrd-dvt-overlay.dts | 28 + .../arm64/qcom/sm8150-qrd-dvt.dtsi | 29 + .../arm64/qcom/sm8150-qrd-overlay.dts | 28 + .../arm64/qcom/sm8150-qrd.dts | 22 + .../arm64/qcom/sm8150-qrd.dtsi | 687 + .../arm64/qcom/sm8150-qupv3.dtsi | 1081 ++ .../arm64/qcom/sm8150-regulator.dtsi | 1001 ++ .../arm64/qcom/sm8150-rumi-overlay.dts | 27 + .../arm64/qcom/sm8150-rumi.dts | 23 + .../arm64/qcom/sm8150-rumi.dtsi | 163 + .../arm64/qcom/sm8150-sde-display.dtsi | 950 ++ .../arm64/qcom/sm8150-sde-pll.dtsi | 96 + .../arm64/qcom/sm8150-sde.dtsi | 691 + .../qcom/sm8150-sdx50-camera-sensor-qrd.dtsi | 415 + .../qcom/sm8150-sdx50m-audio-overlay.dtsi | 20 + .../arm64/qcom/sm8150-sdx50m-cdp-overlay.dts | 31 + .../sm8150-sdx50m-mtp-2.5k-panel-overlay.dts | 66 + .../arm64/qcom/sm8150-sdx50m-mtp-overlay.dts | 31 + .../arm64/qcom/sm8150-sdx50m-qrd-overlay.dts | 32 + .../arm64/qcom/sm8150-sdx50m-qrd.dtsi | 733 + .../arm64/qcom/sm8150-sdx50m.dtsi | 605 + .../qcom/sm8150-sdxprairie-cdp-overlay.dts | 62 + .../qcom/sm8150-sdxprairie-mtp-overlay.dts | 64 + .../qcom/sm8150-sdxprairie-v2-cdp-overlay.dts | 66 + .../qcom/sm8150-sdxprairie-v2-mtp-overlay.dts | 66 + .../arm64/qcom/sm8150-sdxprairie-v2.dtsi | 18 + .../arm64/qcom/sm8150-sdxprairie.dtsi | 581 + .../arm64/qcom/sm8150-slpi-pinctrl.dtsi | 198 + .../arm64/qcom/sm8150-smp2p.dtsi | 154 + .../arm64/qcom/sm8150-thermal-overlay.dtsi | 302 + .../arm64/qcom/sm8150-thermal.dtsi | 1274 ++ .../arm64/qcom/sm8150-usb.dtsi | 586 + .../arm64/qcom/sm8150-v2-camera.dtsi | 340 + .../arm64/qcom/sm8150-v2-cdp.dts | 22 + .../arm64/qcom/sm8150-v2-mtp.dts | 22 + .../arm64/qcom/sm8150-v2-qrd-dvt.dts | 22 + .../arm64/qcom/sm8150-v2-qrd.dts | 22 + .../arm64/qcom/sm8150-v2-rumi.dts | 23 + .../include-prefixes/arm64/qcom/sm8150-v2.dts | 22 + .../arm64/qcom/sm8150-v2.dtsi | 1358 ++ .../arm64/qcom/sm8150-vidc.dtsi | 139 + .../arm64/qcom/sm8150-wcd.dtsi | 235 + .../include-prefixes/arm64/qcom/sm8150.dts | 22 + .../include-prefixes/arm64/qcom/sm8150.dtsi | 4164 +++++ .../arm64/qcom/sm8150p-cdp.dts | 22 + .../arm64/qcom/sm8150p-hdk.dts | 22 + .../arm64/qcom/sm8150p-mtp.dts | 22 + .../arm64/qcom/sm8150p-qrd.dts | 22 + .../arm64/qcom/sm8150p-v2-cdp.dts | 22 + .../arm64/qcom/sm8150p-v2-mtp.dts | 22 + .../arm64/qcom/sm8150p-v2-qrd.dts | 22 + .../arm64/qcom/sm8150p-v2.dts | 22 + .../arm64/qcom/sm8150p-v2.dtsi | 19 + .../include-prefixes/arm64/qcom/sm8150p.dts | 22 + .../include-prefixes/arm64/qcom/sm8150p.dtsi | 19 + .../include-prefixes/arm64/qcom/smb1355.dtsi | 56 + .../include-prefixes/arm64/qcom/smb1390.dtsi | 72 + .../qcom/spi-panel-st7789v2-qvga-cmd.dtsi | 50 + .../arm64/qcom/trinket-audio-overlay.dtsi | 463 + .../arm64/qcom/trinket-audio.dtsi | 149 + .../arm64/qcom/trinket-bus.dtsi | 1117 ++ .../arm64/qcom/trinket-camera-sensor-idp.dtsi | 281 + .../arm64/qcom/trinket-camera-sensor-qrd.dtsi | 230 + .../arm64/qcom/trinket-camera.dtsi | 803 + .../arm64/qcom/trinket-coresight.dtsi | 2316 +++ .../arm64/qcom/trinket-dp-idp-overlay.dts | 51 + .../arm64/qcom/trinket-dp-idp.dts | 44 + .../trinket-external-codec-idp-overlay.dts | 31 + .../arm64/qcom/trinket-external-codec-idp.dts | 24 + .../arm64/qcom/trinket-gdsc.dtsi | 143 + .../arm64/qcom/trinket-gpu.dtsi | 279 + .../arm64/qcom/trinket-idp-overlay.dts | 30 + .../arm64/qcom/trinket-idp.dts | 23 + .../arm64/qcom/trinket-idp.dtsi | 383 + .../arm64/qcom/trinket-ion.dtsi | 62 + .../arm64/qcom/trinket-pinctrl.dtsi | 1851 +++ .../arm64/qcom/trinket-pm.dtsi | 224 + .../arm64/qcom/trinket-qrd-overlay.dts | 24 + .../arm64/qcom/trinket-qrd.dts | 23 + .../arm64/qcom/trinket-qrd.dtsi | 392 + .../arm64/qcom/trinket-qupv3.dtsi | 462 + .../arm64/qcom/trinket-regulator.dtsi | 372 + .../arm64/qcom/trinket-rumi-overlay.dts | 25 + .../arm64/qcom/trinket-rumi.dts | 24 + .../arm64/qcom/trinket-rumi.dtsi | 187 + .../arm64/qcom/trinket-sde-display.dtsi | 329 + .../arm64/qcom/trinket-sde-pll.dtsi | 85 + .../arm64/qcom/trinket-sde.dtsi | 563 + .../arm64/qcom/trinket-stub-regulator.dtsi | 280 + .../trinket-tasha-codec-audio-overlay.dtsi | 96 + .../arm64/qcom/trinket-tasha-codec.dtsi | 170 + .../arm64/qcom/trinket-thermal-overlay.dtsi | 449 + .../arm64/qcom/trinket-thermal.dtsi | 2015 +++ .../arm64/qcom/trinket-usb.dtsi | 324 + ...rinket-usbc-external-codec-idp-overlay.dts | 29 + .../qcom/trinket-usbc-external-codec-idp.dts | 22 + .../arm64/qcom/trinket-usbc-idp-overlay.dts | 30 + .../arm64/qcom/trinket-usbc-idp.dts | 23 + .../arm64/qcom/trinket-usbc-idp.dtsi | 19 + .../arm64/qcom/trinket-vidc.dtsi | 110 + .../arm64/qcom/trinket-wcd.dtsi | 29 + .../include-prefixes/arm64/qcom/trinket.dts | 22 + .../include-prefixes/arm64/qcom/trinket.dtsi | 3147 ++++ .../include-prefixes/arm64/realtek/Makefile | 5 + .../arm64/realtek/rtd1295-zidoo-x9s.dts | 42 + .../arm64/realtek/rtd1295.dtsi | 131 + .../include-prefixes/arm64/renesas/Makefile | 9 + .../arm64/renesas/r8a7795-es1-h3ulcb.dts | 40 + .../arm64/renesas/r8a7795-es1-salvator-x.dts | 113 + .../arm64/renesas/r8a7795-es1.dtsi | 91 + .../arm64/renesas/r8a7795-h3ulcb.dts | 54 + .../arm64/renesas/r8a7795-salvator-x.dts | 113 + .../arm64/renesas/r8a7795-salvator-xs.dts | 109 + .../arm64/renesas/r8a7795.dtsi | 2173 +++ .../arm64/renesas/r8a7796-m3ulcb.dts | 42 + .../arm64/renesas/r8a7796-salvator-x.dts | 58 + .../arm64/renesas/r8a7796.dtsi | 1853 +++ .../arm64/renesas/r8a77995-draak.dts | 46 + .../arm64/renesas/r8a77995.dtsi | 155 + .../arm64/renesas/salvator-common.dtsi | 642 + .../arm64/renesas/salvator-x.dtsi | 30 + .../arm64/renesas/salvator-xs.dtsi | 30 + .../include-prefixes/arm64/renesas/ulcb.dtsi | 417 + .../include-prefixes/arm64/rockchip/Makefile | 17 + .../arm64/rockchip/rk3328-evb.dts | 238 + .../arm64/rockchip/rk3328-rock64.dts | 333 + .../arm64/rockchip/rk3328.dtsi | 1734 ++ .../arm64/rockchip/rk3368-evb-act8846.dts | 176 + .../arm64/rockchip/rk3368-evb.dtsi | 278 + .../arm64/rockchip/rk3368-geekbox.dts | 315 + .../arm64/rockchip/rk3368-orion-r68-meta.dts | 376 + .../arm64/rockchip/rk3368-px5-evb.dts | 311 + .../arm64/rockchip/rk3368-r88.dts | 371 + .../arm64/rockchip/rk3368.dtsi | 1224 ++ .../arm64/rockchip/rk3399-evb.dts | 263 + .../arm64/rockchip/rk3399-firefly.dts | 730 + .../arm64/rockchip/rk3399-gru-kevin.dts | 350 + .../arm64/rockchip/rk3399-gru.dtsi | 1137 ++ .../arm64/rockchip/rk3399-op1-opp.dtsi | 178 + .../arm64/rockchip/rk3399-opp.dtsi | 170 + .../arm64/rockchip/rk3399-puma-haikou.dts | 228 + .../arm64/rockchip/rk3399-puma.dtsi | 536 + .../rockchip/rk3399-sapphire-excavator.dts | 240 + .../arm64/rockchip/rk3399-sapphire.dtsi | 644 + .../arm64/rockchip/rk3399.dtsi | 2379 +++ .../include-prefixes/arm64/socionext/Makefile | 10 + .../arm64/socionext/uniphier-ld11-global.dts | 74 + .../arm64/socionext/uniphier-ld11-ref.dts | 64 + .../arm64/socionext/uniphier-ld11.dtsi | 410 + .../arm64/socionext/uniphier-ld20-global.dts | 56 + .../arm64/socionext/uniphier-ld20-ref.dts | 52 + .../arm64/socionext/uniphier-ld20.dtsi | 430 + .../arm64/socionext/uniphier-pinctrl.dtsi | 1 + .../arm64/socionext/uniphier-pxs3-ref.dts | 62 + .../arm64/socionext/uniphier-pxs3.dtsi | 367 + .../socionext/uniphier-ref-daughter.dtsi | 1 + .../socionext/uniphier-support-card.dtsi | 1 + .../dtc/include-prefixes/arm64/sprd/Makefile | 7 + .../arm64/sprd/sc9836-openphone.dts | 49 + .../include-prefixes/arm64/sprd/sc9836.dtsi | 218 + .../include-prefixes/arm64/sprd/sc9860.dtsi | 569 + .../include-prefixes/arm64/sprd/sharkl64.dtsi | 65 + .../arm64/sprd/sp9860g-1h10.dts | 56 + .../include-prefixes/arm64/sprd/whale2.dtsi | 71 + .../include-prefixes/arm64/xilinx/Makefile | 5 + .../arm64/xilinx/zynqmp-ep108-clk.dtsi | 136 + .../arm64/xilinx/zynqmp-ep108.dts | 143 + .../include-prefixes/arm64/xilinx/zynqmp.dtsi | 620 + .../dtc/include-prefixes/arm64/zte/Makefile | 6 + .../arm64/zte/zx296718-evb.dts | 144 + .../arm64/zte/zx296718-pcbox.dts | 143 + .../include-prefixes/arm64/zte/zx296718.dtsi | 627 + scripts/dtc/include-prefixes/c6x | 1 - scripts/dtc/include-prefixes/c6x/Makefile | 21 + scripts/dtc/include-prefixes/c6x/dsk6455.dts | 62 + scripts/dtc/include-prefixes/c6x/evmc6457.dts | 48 + scripts/dtc/include-prefixes/c6x/evmc6472.dts | 73 + scripts/dtc/include-prefixes/c6x/evmc6474.dts | 58 + scripts/dtc/include-prefixes/c6x/evmc6678.dts | 83 + scripts/dtc/include-prefixes/c6x/linked_dtb.S | 2 + .../dtc/include-prefixes/c6x/tms320c6455.dtsi | 97 + .../dtc/include-prefixes/c6x/tms320c6457.dtsi | 69 + .../dtc/include-prefixes/c6x/tms320c6472.dtsi | 135 + .../dtc/include-prefixes/c6x/tms320c6474.dtsi | 90 + .../dtc/include-prefixes/c6x/tms320c6678.dtsi | 147 + scripts/dtc/include-prefixes/cris | 1 - scripts/dtc/include-prefixes/cris/Makefile | 7 + .../dtc/include-prefixes/cris/artpec3.dtsi | 47 + scripts/dtc/include-prefixes/cris/dev88.dts | 68 + .../dtc/include-prefixes/cris/etraxfs.dtsi | 47 + scripts/dtc/include-prefixes/cris/p1343.dts | 77 + scripts/dtc/include-prefixes/dt-bindings | 1 - .../dt-bindings/arm/ux500_pm_domains.h | 15 + .../dt-bindings/clk/ti-dra7-atl.h | 40 + .../dt-bindings/clock/alphascale,asm9260.h | 97 + .../include-prefixes/dt-bindings/clock/at91.h | 23 + .../dt-bindings/clock/ath79-clk.h | 19 + .../dt-bindings/clock/axis,artpec6-clkctrl.h | 38 + .../dt-bindings/clock/bcm-cygnus.h | 74 + .../dt-bindings/clock/bcm-ns2.h | 72 + .../dt-bindings/clock/bcm-nsp.h | 51 + .../dt-bindings/clock/bcm-sr.h | 101 + .../dt-bindings/clock/bcm21664.h | 62 + .../dt-bindings/clock/bcm281xx.h | 77 + .../dt-bindings/clock/bcm2835-aux.h | 17 + .../dt-bindings/clock/bcm2835.h | 68 + .../dt-bindings/clock/berlin2.h | 46 + .../dt-bindings/clock/berlin2q.h | 33 + .../dt-bindings/clock/boston-clock.h | 14 + .../dt-bindings/clock/clps711x-clock.h | 27 + .../dt-bindings/clock/cortina,gemini-clock.h | 30 + .../dt-bindings/clock/efm32-cmu.h | 43 + .../dt-bindings/clock/exynos-audss-clk.h | 27 + .../dt-bindings/clock/exynos3250.h | 356 + .../dt-bindings/clock/exynos4.h | 275 + .../dt-bindings/clock/exynos5250.h | 182 + .../dt-bindings/clock/exynos5260-clk.h | 469 + .../dt-bindings/clock/exynos5410.h | 68 + .../dt-bindings/clock/exynos5420.h | 258 + .../dt-bindings/clock/exynos5433.h | 1412 ++ .../dt-bindings/clock/exynos5440.h | 44 + .../dt-bindings/clock/exynos7-clk.h | 207 + .../dt-bindings/clock/gxbb-aoclkc.h | 67 + .../dt-bindings/clock/gxbb-clkc.h | 118 + .../dt-bindings/clock/hi3516cv300-clock.h | 48 + .../dt-bindings/clock/hi3519-clock.h | 40 + .../dt-bindings/clock/hi3620-clock.h | 157 + .../dt-bindings/clock/hi3660-clock.h | 211 + .../dt-bindings/clock/hi6220-clock.h | 181 + .../dt-bindings/clock/hip04-clock.h | 35 + .../dt-bindings/clock/histb-clock.h | 73 + .../dt-bindings/clock/hix5hd2-clock.h | 85 + .../dt-bindings/clock/imx1-clock.h | 40 + .../dt-bindings/clock/imx21-clock.h | 80 + .../dt-bindings/clock/imx27-clock.h | 108 + .../dt-bindings/clock/imx5-clock.h | 219 + .../dt-bindings/clock/imx6qdl-clock.h | 276 + .../dt-bindings/clock/imx6sl-clock.h | 180 + .../dt-bindings/clock/imx6sx-clock.h | 280 + .../dt-bindings/clock/imx6ul-clock.h | 254 + .../dt-bindings/clock/imx7d-clock.h | 456 + .../dt-bindings/clock/jz4740-cgu.h | 38 + .../dt-bindings/clock/jz4780-cgu.h | 89 + .../dt-bindings/clock/lpc18xx-ccu.h | 74 + .../dt-bindings/clock/lpc18xx-cgu.h | 41 + .../dt-bindings/clock/lpc32xx-clock.h | 58 + .../dt-bindings/clock/lsi,axm5516-clks.h | 36 + .../dt-bindings/clock/marvell,mmp2.h | 76 + .../dt-bindings/clock/marvell,pxa168.h | 61 + .../dt-bindings/clock/marvell,pxa1928.h | 58 + .../dt-bindings/clock/marvell,pxa910.h | 59 + .../dt-bindings/clock/maxim,max77620.h | 21 + .../dt-bindings/clock/maxim,max77686.h | 23 + .../dt-bindings/clock/maxim,max77802.h | 22 + .../dt-bindings/clock/mdss-10nm-pll-clk.h | 63 + .../dt-bindings/clock/mdss-14nm-pll-clk.h | 49 + .../dt-bindings/clock/mdss-28nm-pll-clk.h | 39 + .../dt-bindings/clock/meson8b-clkc.h | 106 + .../dt-bindings/clock/microchip,pic32-clock.h | 42 + .../dt-bindings/clock/mpc512x-clock.h | 77 + .../dt-bindings/clock/mt2701-clk.h | 488 + .../dt-bindings/clock/mt6797-clk.h | 281 + .../dt-bindings/clock/mt8135-clk.h | 194 + .../dt-bindings/clock/mt8173-clk.h | 330 + .../dt-bindings/clock/omap4.h | 146 + .../dt-bindings/clock/oxsemi,ox810se.h | 30 + .../dt-bindings/clock/oxsemi,ox820.h | 40 + .../dt-bindings/clock/pistachio-clk.h | 183 + .../dt-bindings/clock/pxa-clock.h | 77 + .../dt-bindings/clock/qcom,aop-qmp.h | 29 + .../dt-bindings/clock/qcom,audio-ext-clk.h | 10 +- .../dt-bindings/clock/qcom,camcc-atoll.h | 100 + .../dt-bindings/clock/qcom,camcc-sdmmagpie.h | 113 + .../dt-bindings/clock/qcom,camcc-sdmshrike.h | 194 + .../dt-bindings/clock/qcom,camcc-sm6150.h | 90 + .../dt-bindings/clock/qcom,camcc-sm8150.h | 114 + .../dt-bindings/clock/qcom,cmn-blk-pll.h | 10 +- .../dt-bindings/clock/qcom,cpu-qcs405.h | 20 + .../dt-bindings/clock/qcom,cpu-sdxprairie.h | 20 + .../dt-bindings/clock/qcom,cpucc-sm8150.h | 38 + .../dt-bindings/clock/qcom,dispcc-atoll.h | 53 + .../dt-bindings/clock/qcom,dispcc-sdmmagpie.h | 62 + .../dt-bindings/clock/qcom,dispcc-sm6150.h | 50 + .../dt-bindings/clock/qcom,dispcc-sm8150.h | 82 + .../dt-bindings/clock/qcom,dispcc-trinket.h | 46 + .../dt-bindings/clock/qcom,gcc-apq8084.h | 357 + .../dt-bindings/clock/qcom,gcc-atoll.h | 178 + .../dt-bindings/clock/qcom,gcc-ipq4019.h | 169 + .../dt-bindings/clock/qcom,gcc-ipq806x.h | 295 + .../dt-bindings/clock/qcom,gcc-ipq8074.h | 152 + .../dt-bindings/clock/qcom,gcc-mdm9615.h | 329 + .../dt-bindings/clock/qcom,gcc-msm8660.h | 276 + .../dt-bindings/clock/qcom,gcc-msm8916.h | 187 + .../dt-bindings/clock/qcom,gcc-msm8960.h | 323 + .../dt-bindings/clock/qcom,gcc-msm8974.h | 327 + .../dt-bindings/clock/qcom,gcc-msm8994.h | 138 + .../dt-bindings/clock/qcom,gcc-msm8996.h | 358 + .../dt-bindings/clock/qcom,gcc-qcs405.h | 176 + .../dt-bindings/clock/qcom,gcc-sdmmagpie.h | 194 + .../dt-bindings/clock/qcom,gcc-sdmshrike.h | 309 + .../dt-bindings/clock/qcom,gcc-sdxprairie.h | 124 + .../dt-bindings/clock/qcom,gcc-sm6150.h | 220 + .../dt-bindings/clock/qcom,gcc-sm8150.h | 262 + .../dt-bindings/clock/qcom,gcc-trinket.h | 239 + .../dt-bindings/clock/qcom,gpucc-atoll.h | 40 + .../dt-bindings/clock/qcom,gpucc-sdmmagpie.h | 40 + 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33 + .../dt-bindings/reset/altr,rst-mgr-s10.h | 108 + .../dt-bindings/reset/altr,rst-mgr.h | 90 + .../reset/amlogic,meson-gxbb-reset.h | 210 + .../reset/amlogic,meson8b-clkc-reset.h | 27 + .../dt-bindings/reset/amlogic,meson8b-reset.h | 175 + .../dt-bindings/reset/cortina,gemini-reset.h | 37 + .../dt-bindings/reset/gxbb-aoclkc.h | 66 + .../dt-bindings/reset/hisi,hi6220-resets.h | 76 + .../dt-bindings/reset/imx7-reset.h | 62 + .../dt-bindings/reset/mt2701-resets.h | 90 + .../dt-bindings/reset/mt8135-resets.h | 64 + .../dt-bindings/reset/mt8173-resets.h | 63 + .../dt-bindings/reset/oxsemi,ox810se.h | 53 + .../dt-bindings/reset/oxsemi,ox820.h | 53 + .../dt-bindings/reset/pistachio-resets.h | 37 + .../dt-bindings/reset/qcom,gcc-apq8084.h | 109 + .../dt-bindings/reset/qcom,gcc-ipq806x.h | 175 + .../dt-bindings/reset/qcom,gcc-mdm9615.h | 136 + .../dt-bindings/reset/qcom,gcc-msm8660.h | 134 + .../dt-bindings/reset/qcom,gcc-msm8916.h | 108 + .../dt-bindings/reset/qcom,gcc-msm8960.h | 134 + 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.../dt-bindings/reset/sun9i-a80-usb.h | 56 + .../dt-bindings/reset/tegra124-car.h | 13 + .../dt-bindings/reset/tegra186-reset.h | 217 + .../dt-bindings/reset/tegra210-car.h | 14 + .../dt-bindings/reset/ti-syscon.h | 38 + .../dt-bindings/soc/qcom,dcc_v2.h | 20 + .../dt-bindings/soc/qcom,gsbi.h | 26 + .../dt-bindings/soc/qcom,tcs-mbox.h | 16 + .../dt-bindings/soc/rockchip,boot-mode.h | 16 + .../dt-bindings/soc/zte,pm_domains.h | 24 + .../dt-bindings/sound/apq8016-lpass.h | 10 + .../sound/audio-codec-port-types.h | 38 + .../dt-bindings/sound/audio-jack-events.h | 10 + .../dt-bindings/sound/cs35l32.h | 27 + .../dt-bindings/sound/cs42l42.h | 73 + .../dt-bindings/sound/fsl-imx-audmux.h | 57 + .../dt-bindings/sound/samsung-i2s.h | 9 + .../dt-bindings/sound/tas2552.h | 19 + .../dt-bindings/sound/tlv320aic31xx-micbias.h | 9 + .../include-prefixes/dt-bindings/spmi/spmi.h | 18 + .../dt-bindings/thermal/lm90.h | 13 + .../dt-bindings/thermal/qmi_thermal.h | 49 + .../dt-bindings/thermal/tegra124-soctherm.h | 20 + .../dt-bindings/thermal/thermal.h | 18 + .../dt-bindings/thermal/thermal_exynos.h | 28 + scripts/dtc/include-prefixes/h8300 | 1 - scripts/dtc/include-prefixes/h8300/Makefile | 16 + .../dtc/include-prefixes/h8300/edosk2674.dts | 108 + .../dtc/include-prefixes/h8300/h8300h_sim.dts | 97 + .../dtc/include-prefixes/h8300/h8s_sim.dts | 100 + scripts/dtc/include-prefixes/metag | 1 - scripts/dtc/include-prefixes/metag/Makefile | 22 + .../dtc/include-prefixes/metag/skeleton.dts | 10 + .../dtc/include-prefixes/metag/skeleton.dtsi | 15 + .../dtc/include-prefixes/metag/tz1090.dtsi | 108 + .../include-prefixes/metag/tz1090_generic.dts | 10 + scripts/dtc/include-prefixes/microblaze | 1 - .../dtc/include-prefixes/microblaze/Makefile | 19 + .../include-prefixes/microblaze/linked_dtb.S | 2 + .../include-prefixes/microblaze/system.dts | 366 + scripts/dtc/include-prefixes/mips | 1 - scripts/dtc/include-prefixes/mips/Makefile | 22 + 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100644 arch/arm/boot/dts/qcom/msm-arm-smmu-trinket.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm-qvr-external.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm-rdbg.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm-wsa881x.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm8916-mtp.dts create mode 100644 arch/arm/boot/dts/qcom/msm8916-mtp.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm8916-pins.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm8916.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm8992-bullhead-rev-101.dts create mode 100644 arch/arm/boot/dts/qcom/msm8992-pins.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm8992.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm8994-angler-rev-101.dts create mode 100644 arch/arm/boot/dts/qcom/msm8994-pins.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm8994.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm8996-mtp.dts create mode 100644 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100644 arch/arm/boot/dts/qcom/sa6155p-v2-adp-air.dts create mode 100644 arch/arm/boot/dts/qcom/sa6155p-v2-adp-star-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sa6155p-v2-adp-star.dts create mode 100644 arch/arm/boot/dts/qcom/sa6155p-vm-pcie.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa6155p-vm-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa6155p-vm-qupv3.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa6155p-vm-usb.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa6155p-vm.dts create mode 100644 arch/arm/boot/dts/qcom/sa6155p-vm.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa6155p.dts create mode 100644 arch/arm/boot/dts/qcom/sa6155p.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8155-adp-alcor-display.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8155-adp-alcor-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sa8155-adp-alcor.dts create mode 100644 arch/arm/boot/dts/qcom/sa8155-adp-alcor.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8155-adp-common.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8155-adp-star-display.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8155-adp-star-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sa8155-adp-star.dts create mode 100644 arch/arm/boot/dts/qcom/sa8155-adp-star.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8155-audio.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8155-camera-sensor.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8155-cnss.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8155-pmic-overlay.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8155-regulator.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8155-v1.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8155-v2-adp-air-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sa8155-v2-adp-air.dts create mode 100644 arch/arm/boot/dts/qcom/sa8155-v2-adp-star.dts create mode 100644 arch/arm/boot/dts/qcom/sa8155-v2.dts create mode 100644 arch/arm/boot/dts/qcom/sa8155-v2.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8155-vm-audio.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8155-vm-la-mt.dts create mode 100644 arch/arm/boot/dts/qcom/sa8155-vm-lv-mt.dts create mode 100644 arch/arm/boot/dts/qcom/sa8155-vm-lv.dts create mode 100644 arch/arm/boot/dts/qcom/sa8155-vm-mhi.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8155-vm-pcie.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8155-vm-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8155-vm-qupv3.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8155-vm-usb.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8155-vm.dts create mode 100644 arch/arm/boot/dts/qcom/sa8155-vm.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8155.dts create mode 100644 arch/arm/boot/dts/qcom/sa8155.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8155p-adp-alcor-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sa8155p-adp-alcor.dts create mode 100644 arch/arm/boot/dts/qcom/sa8155p-adp-star-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sa8155p-adp-star.dts create mode 100644 arch/arm/boot/dts/qcom/sa8155p-v2-adp-air-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sa8155p-v2-adp-air.dts create mode 100644 arch/arm/boot/dts/qcom/sa8155p-v2-adp-star.dts create mode 100644 arch/arm/boot/dts/qcom/sa8155p-v2.dts create mode 100644 arch/arm/boot/dts/qcom/sa8155p-v2.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8155p.dts create mode 100644 arch/arm/boot/dts/qcom/sa8155p.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8195-pmic.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8195-vm.dts create mode 100644 arch/arm/boot/dts/qcom/sa8195-vm.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8195p-adp-star-display.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8195p-adp-star-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sa8195p-adp-star.dts create mode 100644 arch/arm/boot/dts/qcom/sa8195p-adp-star.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8195p-pcie.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8195p-regulator.dtsi create mode 100644 arch/arm/boot/dts/qcom/sa8195p.dts create mode 100644 arch/arm/boot/dts/qcom/sa8195p.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-atp-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-atp.dts create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-atp.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-audio-overlay.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-audio.dtsi rename arch/{arm64/boot/dts/qcom/atoll-bus.dtsi => arm/boot/dts/qcom/sdmmagpie-bus.dtsi} (77%) create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-camera-sensor-idp.dtsi rename arch/{arm64/boot/dts/qcom/atoll-camera-sensor-qrd.dtsi => arm/boot/dts/qcom/sdmmagpie-camera-sensor-qrd.dtsi} (67%) create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-camera.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-coresight.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-dual-display-idp-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-dual-display-idp.dts create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-ext-codec-audio-overlay.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-external-codec-idp-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-external-codec-idp.dts create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-external-codec.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-gdsc.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-gpu.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-idp-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-idp.dts create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-idp.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-ion.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-npu.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-pm.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-qrd-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-qrd.dts create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-qrd.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-qupv3.dtsi rename arch/{arm64/boot/dts/qcom/atoll-regulator.dtsi => arm/boot/dts/qcom/sdmmagpie-regulator.dtsi} (55%) create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-rumi-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-rumi.dts create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-rumi.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-sde-display.dtsi rename arch/{arm64/boot/dts/qcom/atoll-sde-pll.dtsi => arm/boot/dts/qcom/sdmmagpie-sde-pll.dtsi} (71%) create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-sde.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-stub-regulator.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-thermal-overlay.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-thermal.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-usb.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-usbc-idp-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-usbc-idp.dts create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-usbc-idp.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie-vidc.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie.dts create mode 100644 arch/arm/boot/dts/qcom/sdmmagpie.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmmagpiep-atp-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sdmmagpiep-atp.dts create mode 100644 arch/arm/boot/dts/qcom/sdmmagpiep-idp-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sdmmagpiep-idp.dts create mode 100644 arch/arm/boot/dts/qcom/sdmmagpiep-qrd-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sdmmagpiep-qrd.dts create mode 100644 arch/arm/boot/dts/qcom/sdmmagpiep.dts create mode 100644 arch/arm/boot/dts/qcom/sdmmagpiep.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-audio-overlay.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-bus.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-cdp-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-cdp.dts create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-cdp.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-gdsc.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-gpu.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-ion.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-mtp-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-mtp.dts create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-mtp.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-pmic-overlay.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-qupv3.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-regulators.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-rumi.dts create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-rumi.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-sde-display.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-sde-pll.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-sde.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-smp2p.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-thermal-overlay.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-thermal.dtsi rename arch/{arm64/boot/dts/qcom/sa8195-vm-usb.dtsi => arm/boot/dts/qcom/sdmshrike-usb.dtsi} (68%) create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-v2-mtp.dts create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-v2.dts create mode 100644 arch/arm/boot/dts/qcom/sdmshrike-v2.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdmshrike.dts create mode 100644 arch/arm/boot/dts/qcom/sdmshrike.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdx-audio-lpass.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdx-wsa881x.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdx5xm-external-soc.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-aqc.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-audio-overlay.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-audio.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-blsp.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-bus.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-cdp-256.dts create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-cdp-256.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-cdp-audio-overlay.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-cdp-cpe.dts create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-cdp-cpe.dtsi rename arch/{arm64/boot/dts/qcom/qcs404-iot-sku6.dts => arm/boot/dts/qcom/sdxprairie-cdp.dts} (60%) create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-cdp.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-coresight.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-dsda-cdp.dts create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-dsda-mtp.dts create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-gdsc.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-ion.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-mtp-256.dts create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-mtp-256.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-mtp-aqc.dts create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-mtp-audio-overlay.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-mtp-cpe.dts create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-mtp-cpe.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-mtp.dts create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-mtp.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dts create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-pcie.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-pm.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-pmic-overlay.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-regulator.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-rumi.dts create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-rumi.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-thermal.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-usb.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-v2-cdp.dts create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-v2-mtp.dts create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-v2.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie-wcd.dtsi create mode 100644 arch/arm/boot/dts/qcom/sdxprairie.dtsi create mode 100644 arch/arm/boot/dts/qcom/skeleton.dtsi create mode 100644 arch/arm/boot/dts/qcom/skeleton64.dtsi rename arch/{arm64/boot/dts/qcom/atoll-audio-overlay.dtsi => arm/boot/dts/qcom/sm6150-audio-overlay.dtsi} (60%) create mode 100644 arch/arm/boot/dts/qcom/sm6150-audio.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-bus.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-camera-sensor-adp.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-camera-sensor-idp.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-camera-sensor-qrd.dtsi rename arch/{arm64/boot/dts/qcom/atoll-camera.dtsi => arm/boot/dts/qcom/sm6150-camera.dtsi} (76%) create mode 100644 arch/arm/boot/dts/qcom/sm6150-cmd-mode-display-idp-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sm6150-cmd-mode-display-idp.dts create mode 100644 arch/arm/boot/dts/qcom/sm6150-coresight.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-ext-codec-audio-overlay.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-external-codec-idp-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sm6150-external-codec-idp.dts create mode 100644 arch/arm/boot/dts/qcom/sm6150-external-codec.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-gdsc.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-gpu.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-idp-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sm6150-idp.dts create mode 100644 arch/arm/boot/dts/qcom/sm6150-idp.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-interposer-trinket-idp-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sm6150-interposer-trinket-idp.dts create mode 100644 arch/arm/boot/dts/qcom/sm6150-interposer-trinket-idp.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-interposer-trinket-qrd-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sm6150-interposer-trinket-qrd.dts create mode 100644 arch/arm/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-interposer-trinket.dts create mode 100644 arch/arm/boot/dts/qcom/sm6150-interposer-trinket.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-ion.dtsi rename arch/{arm64/boot/dts/qcom/atoll-lpi.dtsi => arm/boot/dts/qcom/sm6150-lpi.dtsi} (53%) create mode 100644 arch/arm/boot/dts/qcom/sm6150-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-pm.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-pm6125-interposer-trinket.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-qrd-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sm6150-qrd.dts create mode 100644 arch/arm/boot/dts/qcom/sm6150-qrd.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-qupv3.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-regulator.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-rumi-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sm6150-rumi.dts create mode 100644 arch/arm/boot/dts/qcom/sm6150-rumi.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-sde-display.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-sde-pll.dtsi rename arch/{arm64/boot/dts/qcom/atoll-sde.dtsi => arm/boot/dts/qcom/sm6150-sde.dtsi} (61%) create mode 100644 arch/arm/boot/dts/qcom/sm6150-slpi-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-stub-regulator.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-thermal-overlay.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-thermal.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-usb.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-usbc-idp-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sm6150-usbc-idp.dts create mode 100644 arch/arm/boot/dts/qcom/sm6150-usbc-idp.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-usbc-minidp-idp-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sm6150-usbc-minidp-idp.dts create mode 100644 arch/arm/boot/dts/qcom/sm6150-vidc.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150-wcd.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150.dts create mode 100644 arch/arm/boot/dts/qcom/sm6150.dtsi create mode 100644 arch/arm/boot/dts/qcom/sm6150p-idp-overlay.dts create mode 100644 arch/arm/boot/dts/qcom/sm6150p-idp.dts create mode 100644 arch/arm/boot/dts/qcom/sm6150p-qrd-overlay.dts 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scripts/dtc/include-prefixes/arm/qcom/qcs401-iot-sku1.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs401.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs403-ext-pll-audio.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs403-iot-sku1.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs403-iot-sku2.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs403-iot-sku3.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs403-iot-sku4.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs403.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-amic-audio-overlay.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-audio-overlay.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-audio.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-blsp.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-bus.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-circular-pca9956.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-coresight.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-cpu.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-csra1-audio-overlay.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-csra1.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-csra6-audio-overlay.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-csra6.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-csra8-audio-overlay.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-csra8.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-gdsc.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-geni-ir-overlay.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-gpu.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-ion.dtsi rename arch/arm64/boot/dts/qcom/qcs404-iot-sku3.dts => scripts/dtc/include-prefixes/arm/qcom/qcs405-iot-sku1.dts (60%) create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-iot-sku10.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-iot-sku11.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-iot-sku12.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-iot-sku2.dts rename arch/arm64/boot/dts/qcom/qcs401-iot-sku5.dts => scripts/dtc/include-prefixes/arm/qcom/qcs405-iot-sku3.dts (86%) create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-iot-sku4.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-iot-sku5.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-iot-sku6.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-iot-sku7.dts rename arch/arm64/boot/dts/qcom/qcs407-iot-sku3.dts => scripts/dtc/include-prefixes/arm/qcom/qcs405-iot-sku8.dts (73%) create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-iot-sku9.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-linear-pca9956.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-lpi.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-mdss-panels.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-mdss-pll.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-mdss.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-mhi.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-nowcd-audio-overlay.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-pcie.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-pinctrl.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-pm.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/qcs405-regulator.dtsi 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scripts/dtc/include-prefixes/arm/qcom/sa8155-pmic-overlay.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8155-regulator.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8155-v1.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8155-v2-adp-air-overlay.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8155-v2-adp-air.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8155-v2-adp-star.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8155-v2.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8155-v2.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8155-vm-audio.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8155-vm-la-mt.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8155-vm-lv-mt.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8155-vm-lv.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8155-vm-mhi.dtsi create mode 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create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8155p-v2-adp-air.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8155p-v2-adp-star.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8155p-v2.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8155p-v2.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8155p.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8155p.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8195-pmic.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8195-vm.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8195-vm.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8195p-adp-star-display.dtsi create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8195p-adp-star-overlay.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8195p-adp-star.dts create mode 100644 scripts/dtc/include-prefixes/arm/qcom/sa8195p-adp-star.dtsi create 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b/AndroidKernel.mk @@ -165,31 +165,14 @@ $(KERNEL_CONFIG): $(KERNEL_OUT) echo $(KERNEL_CONFIG_OVERRIDE) >> $(KERNEL_OUT)/.config; \ $(MAKE) -C $(TARGET_KERNEL_SOURCE) O=$(BUILD_ROOT_LOC)$(KERNEL_OUT) $(KERNEL_MAKE_ENV) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) $(real_cc) oldconfig; fi -ifeq ($(TARGET_KERNEL_APPEND_DTB), true) -TARGET_PREBUILT_INT_KERNEL_IMAGE := $(KERNEL_OUT)/arch/$(KERNEL_ARCH)/boot/Image -$(TARGET_PREBUILT_INT_KERNEL_IMAGE): $(KERNEL_USR) -$(TARGET_PREBUILT_INT_KERNEL_IMAGE): $(KERNEL_OUT) $(KERNEL_HEADERS_INSTALL) - $(hide) echo "Building kernel modules..." - $(MAKE) -C $(TARGET_KERNEL_SOURCE) O=$(BUILD_ROOT_LOC)$(KERNEL_OUT) $(KERNEL_MAKE_ENV) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) $(real_cc) $(KERNEL_CFLAGS) Image - $(MAKE) -C $(TARGET_KERNEL_SOURCE) O=$(BUILD_ROOT_LOC)$(KERNEL_OUT) $(KERNEL_MAKE_ENV) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) $(real_cc) $(KERNEL_CFLAGS) modules - $(MAKE) -C $(TARGET_KERNEL_SOURCE) O=$(BUILD_ROOT_LOC)$(KERNEL_OUT) INSTALL_MOD_PATH=$(BUILD_ROOT_LOC)../$(KERNEL_MODULES_INSTALL) INSTALL_MOD_STRIP=1 $(KERNEL_MAKE_ENV) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) $(real_cc) modules_install - $(mv-modules) - $(clean-module-folder) - -$(TARGET_PREBUILT_INT_KERNEL): $(TARGET_PREBUILT_INT_KERNEL_IMAGE) - $(hide) echo "Building kernel..." - $(hide) rm -rf $(KERNEL_OUT)/arch/$(KERNEL_ARCH)/boot/dts - $(MAKE) -C $(TARGET_KERNEL_SOURCE) O=$(BUILD_ROOT_LOC)$(KERNEL_OUT) $(KERNEL_MAKE_ENV) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) $(real_cc) $(KERNEL_CFLAGS) -else -TARGET_PREBUILT_INT_KERNEL_IMAGE := $(TARGET_PREBUILT_INT_KERNEL) $(TARGET_PREBUILT_INT_KERNEL): $(KERNEL_OUT) $(KERNEL_HEADERS_INSTALL) $(hide) echo "Building kernel..." + $(hide) rm -rf $(KERNEL_OUT)/arch/$(KERNEL_ARCH)/boot/dts $(MAKE) -C $(TARGET_KERNEL_SOURCE) O=$(BUILD_ROOT_LOC)$(KERNEL_OUT) $(KERNEL_MAKE_ENV) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) $(real_cc) $(KERNEL_CFLAGS) $(MAKE) -C $(TARGET_KERNEL_SOURCE) O=$(BUILD_ROOT_LOC)$(KERNEL_OUT) $(KERNEL_MAKE_ENV) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) $(real_cc) $(KERNEL_CFLAGS) modules $(MAKE) -C $(TARGET_KERNEL_SOURCE) O=$(BUILD_ROOT_LOC)$(KERNEL_OUT) INSTALL_MOD_PATH=$(BUILD_ROOT_LOC)../$(KERNEL_MODULES_INSTALL) INSTALL_MOD_STRIP=1 $(KERNEL_MAKE_ENV) ARCH=$(KERNEL_ARCH) CROSS_COMPILE=$(KERNEL_CROSS_COMPILE) $(real_cc) modules_install $(mv-modules) $(clean-module-folder) -endif $(KERNEL_HEADERS_INSTALL): $(KERNEL_OUT) $(hide) if [ ! -z "$(KERNEL_HEADER_DEFCONFIG)" ]; then \ diff --git a/Documentation/Changes b/Documentation/Changes deleted file mode 120000 index 7564ae1682ba..000000000000 --- a/Documentation/Changes +++ /dev/null @@ -1 +0,0 @@ -process/changes.rst \ No newline at end of file diff --git a/Documentation/Changes b/Documentation/Changes new file mode 100644 index 000000000000..73fcdcd52b87 --- /dev/null +++ b/Documentation/Changes @@ -0,0 +1,454 @@ +.. _changes: + +Minimal requirements to compile the Kernel +++++++++++++++++++++++++++++++++++++++++++ + +Intro +===== + +This document is designed to provide a list of the minimum levels of +software necessary to run the 4.x kernels. + +This document is originally based on my "Changes" file for 2.0.x kernels +and therefore owes credit to the same people as that file (Jared Mauch, +Axel Boldt, Alessandro Sigala, and countless other users all over the +'net). + +Current Minimal Requirements +**************************** + +Upgrade to at **least** these software revisions before thinking you've +encountered a bug! If you're unsure what version you're currently +running, the suggested command should tell you. + +Again, keep in mind that this list assumes you are already functionally +running a Linux kernel. Also, not all tools are necessary on all +systems; obviously, if you don't have any ISDN hardware, for example, +you probably needn't concern yourself with isdn4k-utils. + +====================== =============== ======================================== + Program Minimal version Command to check the version +====================== =============== ======================================== +GNU C 3.2 gcc --version +GNU make 3.81 make --version +binutils 2.20 ld -v +util-linux 2.10o fdformat --version +kmod 13 depmod -V +e2fsprogs 1.41.4 e2fsck -V +jfsutils 1.1.3 fsck.jfs -V +reiserfsprogs 3.6.3 reiserfsck -V +xfsprogs 2.6.0 xfs_db -V +squashfs-tools 4.0 mksquashfs -version +btrfs-progs 0.18 btrfsck +pcmciautils 004 pccardctl -V +quota-tools 3.09 quota -V +PPP 2.4.0 pppd --version +isdn4k-utils 3.1pre1 isdnctrl 2>&1|grep version +nfs-utils 1.0.5 showmount --version +procps 3.2.0 ps --version +oprofile 0.9 oprofiled --version +udev 081 udevd --version +grub 0.93 grub --version || grub-install --version +mcelog 0.6 mcelog --version +iptables 1.4.2 iptables -V +openssl & libcrypto 1.0.0 openssl version +bc 1.06.95 bc --version +Sphinx\ [#f1]_ 1.3 sphinx-build --version +====================== =============== ======================================== + +.. [#f1] Sphinx is needed only to build the Kernel documentation + +Kernel compilation +****************** + +GCC +--- + +The gcc version requirements may vary depending on the type of CPU in your +computer. + +Make +---- + +You will need GNU make 3.81 or later to build the kernel. + +Binutils +-------- + +The build system has, as of 4.13, switched to using thin archives (`ar T`) +rather than incremental linking (`ld -r`) for built-in.o intermediate steps. +This requires binutils 2.20 or newer. + +Perl +---- + +You will need perl 5 and the following modules: ``Getopt::Long``, +``Getopt::Std``, ``File::Basename``, and ``File::Find`` to build the kernel. + +BC +-- + +You will need bc to build kernels 3.10 and higher + + +OpenSSL +------- + +Module signing and external certificate handling use the OpenSSL program and +crypto library to do key creation and signature generation. + +You will need openssl to build kernels 3.7 and higher if module signing is +enabled. You will also need openssl development packages to build kernels 4.3 +and higher. + + +System utilities +**************** + +Architectural changes +--------------------- + +DevFS has been obsoleted in favour of udev +(http://www.kernel.org/pub/linux/utils/kernel/hotplug/) + +32-bit UID support is now in place. Have fun! + +Linux documentation for functions is transitioning to inline +documentation via specially-formatted comments near their +definitions in the source. These comments can be combined with ReST +files the Documentation/ directory to make enriched documentation, which can +then be converted to PostScript, HTML, LaTex, ePUB and PDF files. +In order to convert from ReST format to a format of your choice, you'll need +Sphinx. + +Util-linux +---------- + +New versions of util-linux provide ``fdisk`` support for larger disks, +support new options to mount, recognize more supported partition +types, have a fdformat which works with 2.4 kernels, and similar goodies. +You'll probably want to upgrade. + +Ksymoops +-------- + +If the unthinkable happens and your kernel oopses, you may need the +ksymoops tool to decode it, but in most cases you don't. +It is generally preferred to build the kernel with ``CONFIG_KALLSYMS`` so +that it produces readable dumps that can be used as-is (this also +produces better output than ksymoops). If for some reason your kernel +is not build with ``CONFIG_KALLSYMS`` and you have no way to rebuild and +reproduce the Oops with that option, then you can still decode that Oops +with ksymoops. + +Mkinitrd +-------- + +These changes to the ``/lib/modules`` file tree layout also require that +mkinitrd be upgraded. + +E2fsprogs +--------- + +The latest version of ``e2fsprogs`` fixes several bugs in fsck and +debugfs. Obviously, it's a good idea to upgrade. + +JFSutils +-------- + +The ``jfsutils`` package contains the utilities for the file system. +The following utilities are available: + +- ``fsck.jfs`` - initiate replay of the transaction log, and check + and repair a JFS formatted partition. + +- ``mkfs.jfs`` - create a JFS formatted partition. + +- other file system utilities are also available in this package. + +Reiserfsprogs +------------- + +The reiserfsprogs package should be used for reiserfs-3.6.x +(Linux kernels 2.4.x). It is a combined package and contains working +versions of ``mkreiserfs``, ``resize_reiserfs``, ``debugreiserfs`` and +``reiserfsck``. These utils work on both i386 and alpha platforms. + +Xfsprogs +-------- + +The latest version of ``xfsprogs`` contains ``mkfs.xfs``, ``xfs_db``, and the +``xfs_repair`` utilities, among others, for the XFS filesystem. It is +architecture independent and any version from 2.0.0 onward should +work correctly with this version of the XFS kernel code (2.6.0 or +later is recommended, due to some significant improvements). + +PCMCIAutils +----------- + +PCMCIAutils replaces ``pcmcia-cs``. It properly sets up +PCMCIA sockets at system startup and loads the appropriate modules +for 16-bit PCMCIA devices if the kernel is modularized and the hotplug +subsystem is used. + +Quota-tools +----------- + +Support for 32 bit uid's and gid's is required if you want to use +the newer version 2 quota format. Quota-tools version 3.07 and +newer has this support. Use the recommended version or newer +from the table above. + +Intel IA32 microcode +-------------------- + +A driver has been added to allow updating of Intel IA32 microcode, +accessible as a normal (misc) character device. If you are not using +udev you may need to:: + + mkdir /dev/cpu + mknod /dev/cpu/microcode c 10 184 + chmod 0644 /dev/cpu/microcode + +as root before you can use this. You'll probably also want to +get the user-space microcode_ctl utility to use with this. + +udev +---- + +``udev`` is a userspace application for populating ``/dev`` dynamically with +only entries for devices actually present. ``udev`` replaces the basic +functionality of devfs, while allowing persistent device naming for +devices. + +FUSE +---- + +Needs libfuse 2.4.0 or later. Absolute minimum is 2.3.0 but mount +options ``direct_io`` and ``kernel_cache`` won't work. + +Networking +********** + +General changes +--------------- + +If you have advanced network configuration needs, you should probably +consider using the network tools from ip-route2. + +Packet Filter / NAT +------------------- +The packet filtering and NAT code uses the same tools like the previous 2.4.x +kernel series (iptables). It still includes backwards-compatibility modules +for 2.2.x-style ipchains and 2.0.x-style ipfwadm. + +PPP +--- + +The PPP driver has been restructured to support multilink and to +enable it to operate over diverse media layers. If you use PPP, +upgrade pppd to at least 2.4.0. + +If you are not using udev, you must have the device file /dev/ppp +which can be made by:: + + mknod /dev/ppp c 108 0 + +as root. + +Isdn4k-utils +------------ + +Due to changes in the length of the phone number field, isdn4k-utils +needs to be recompiled or (preferably) upgraded. + +NFS-utils +--------- + +In ancient (2.4 and earlier) kernels, the nfs server needed to know +about any client that expected to be able to access files via NFS. This +information would be given to the kernel by ``mountd`` when the client +mounted the filesystem, or by ``exportfs`` at system startup. exportfs +would take information about active clients from ``/var/lib/nfs/rmtab``. + +This approach is quite fragile as it depends on rmtab being correct +which is not always easy, particularly when trying to implement +fail-over. Even when the system is working well, ``rmtab`` suffers from +getting lots of old entries that never get removed. + +With modern kernels we have the option of having the kernel tell mountd +when it gets a request from an unknown host, and mountd can give +appropriate export information to the kernel. This removes the +dependency on ``rmtab`` and means that the kernel only needs to know about +currently active clients. + +To enable this new functionality, you need to:: + + mount -t nfsd nfsd /proc/fs/nfsd + +before running exportfs or mountd. It is recommended that all NFS +services be protected from the internet-at-large by a firewall where +that is possible. + +mcelog +------ + +On x86 kernels the mcelog utility is needed to process and log machine check +events when ``CONFIG_X86_MCE`` is enabled. Machine check events are errors +reported by the CPU. Processing them is strongly encouraged. + +Kernel documentation +******************** + +Sphinx +------ + +Please see :ref:`sphinx_install` in ``Documentation/doc-guide/sphinx.rst`` +for details about Sphinx requirements. + +Getting updated software +======================== + +Kernel compilation +****************** + +gcc +--- + +- + +Make +---- + +- + +Binutils +-------- + +- + +OpenSSL +------- + +- + +System utilities +**************** + +Util-linux +---------- + +- + +Kmod +---- + +- +- + +Ksymoops +-------- + +- + +Mkinitrd +-------- + +- + +E2fsprogs +--------- + +- + +JFSutils +-------- + +- + +Reiserfsprogs +------------- + +- + +Xfsprogs +-------- + +- + +Pcmciautils +----------- + +- + +Quota-tools +----------- + +- + + +Intel P6 microcode +------------------ + +- + +udev +---- + +- + +FUSE +---- + +- + +mcelog +------ + +- + +Networking +********** + +PPP +--- + +- + +Isdn4k-utils +------------ + +- + +NFS-utils +--------- + +- + +Iptables +-------- + +- + +Ip-route2 +--------- + +- + +OProfile +-------- + +- + +NFS-Utils +--------- + +- + +Kernel documentation +******************** + +Sphinx +------ + +- diff --git a/Documentation/aoe/autoload.sh b/Documentation/aoe/autoload.sh old mode 100644 new mode 100755 diff --git a/Documentation/aoe/status.sh b/Documentation/aoe/status.sh old mode 100644 new mode 100755 diff --git a/Documentation/aoe/udev-install.sh b/Documentation/aoe/udev-install.sh old mode 100644 new mode 100755 diff --git a/Documentation/arm/Samsung/clksrc-change-registers.awk b/Documentation/arm/Samsung/clksrc-change-registers.awk old mode 100755 new mode 100644 diff --git a/Documentation/devicetree/bindings/arm/msm/msm.txt b/Documentation/devicetree/bindings/arm/msm/msm.txt index 750ef33e09f4..850bb51db595 100644 --- a/Documentation/devicetree/bindings/arm/msm/msm.txt +++ b/Documentation/devicetree/bindings/arm/msm/msm.txt @@ -62,12 +62,6 @@ SoCs: - QCS401 compatible = "qcom,qcs401" -- QCS404 - compatible = "qcom,qcs404" - -- QCS407 - compatible = "qcom,qcs407" - - SDXPRAIRIE compatible = "qcom,sdxprairie" @@ -201,8 +195,6 @@ compatible = "qcom,qcs405-rumi" compatible = "qcom,qcs405-iot" compatible = "qcom,qcs403-iot" compatible = "qcom,qcs401-iot" -compatible = "qcom,qcs404-iot" -compatible = "qcom,qcs407-iot" compatible = "qcom,sa8155-adp-star" compatible = "qcom,sa8155p-adp-star" compatible = "qcom,sa8195p-adp-star" @@ -231,7 +223,6 @@ compatible = "qcom,trinket-idp" compatible = "qcom,trinket-qrd" compatible = "qcom,atoll-rumi" compatible = "qcom,atoll-idp" -compatible = "qcom,atoll-atp" compatible = "qcom,atoll-qrd" compatible = "qcom,qcs610-iot" compatible = "qcom,qcs410-iot" diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt b/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt index 6a8128765ff7..4b6881370435 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt +++ b/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt @@ -12,8 +12,7 @@ Properties: Definition: must be "qcom,clk-cpu-osm" or "qcom,clk-cpu-osm-sdmshrike" or "qcom,clk-cpu-osm-sm6150" or "qcom,clk-cpu-osm-sdmmagpie" or - "qcom,clk-cpu-osm-trinket" or - "qcom,clk-cpu-osm-atoll". + "qcom,clk-cpu-osm-trinket". - reg Usage: required diff --git a/Documentation/devicetree/bindings/arm/msm/subsystem_notif_virt.txt b/Documentation/devicetree/bindings/arm/msm/subsystem_notif_virt.txt deleted file mode 100644 index 38e997797a04..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/subsystem_notif_virt.txt +++ /dev/null @@ -1,49 +0,0 @@ -Subsystem Notification Virtual Driver - -The guest VM uses this driver to communicate -subsystem state notifications to a backend driver -via the virtual device's registers. - -[Root level node] -Required Properties: --compatible : Should be "qcom,subsys-notif-virt" --reg : The start and size of the virtual device's - register set. --reg-names : Should be "vdev_base" for virtual device's - base address. - -[Child nodes] --subsys-names : The name of the subsystem that the - driver is registering to notifications for. --offset : The offset from the virtual device's register - base where the subsystem state will be written. --type : The type of the subsystem. - "virtual" - When the subsystem is loaded by the host VM - "native" - When the subsystem is loaded by the guest VM - -Required Property for "virtual" subsystem types: --interrupts : Tuple defining the interrupt which the driver must - register for to receive subsystem state notifications - from the backend. --interrupt-names: Must be "state-irq" - -Example: - - subsys_notif_virt: qcom,subsys_notif_virt@2D000000 { - compatible = "qcom,subsys-notif-virt"; - reg = <0x2D000000 0x400>; - reg-names = "vdev_base"; - adsp { - subsys-name = "adsp"; - interrupts = <0 43 0>; - interrupt-names = "state-irq"; - type = "virtual"; - offset = <0>; - }; - mpss { - subsys-name = "modem"; - type = "native"; - offset = <256>; - }; - }; - diff --git a/Documentation/devicetree/bindings/batterydata/batterydata.txt b/Documentation/devicetree/bindings/batterydata/batterydata.txt index 4509d6cfae21..8224139e7d8f 100644 --- a/Documentation/devicetree/bindings/batterydata/batterydata.txt +++ b/Documentation/devicetree/bindings/batterydata/batterydata.txt @@ -146,12 +146,6 @@ Profile data node optional properties: Element 1 - FV value for soft warm. - qcom,batt-age-level: Battery age level. This is used only when multiple profile loading is supported. -- qcom,soh-range: A tuple entry to specify the values of SOH range that - the battery profile has to be used for. This needs to - be specified along with "qcom,batt-age-level" for the - proper functionality. - Element 0 - SOH minimum level. - Element 1 - SOH maximum level. - qcom,taper-fcc: A bool property to enable gradual reduction in FCC in steps of pre-configured value, whenever step charging thresholds are crossed-over. diff --git a/Documentation/devicetree/bindings/clock/qcom,camcc.txt b/Documentation/devicetree/bindings/clock/qcom,camcc.txt index 09f03605f76d..a844d62b2ae5 100644 --- a/Documentation/devicetree/bindings/clock/qcom,camcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,camcc.txt @@ -8,8 +8,7 @@ Required properties : "qcom,camcc-sdmshrike", "qcom,camcc-sm6150", "qcom,camcc-sdmmagpie", - "qcom,camcc-sa6155", - "qcom,atoll-camcc". + "qcom,camcc-sa6155". - reg : shall contain base register location and length. - reg-names: names of registers listed in the same order as in the reg property. diff --git a/Documentation/devicetree/bindings/clock/qcom,debugcc.txt b/Documentation/devicetree/bindings/clock/qcom,debugcc.txt index 3e2c5d895210..500c7ef288e4 100644 --- a/Documentation/devicetree/bindings/clock/qcom,debugcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,debugcc.txt @@ -7,8 +7,7 @@ Required properties : "qcom,debugcc-sm6150", "qcom,debugcc-sdmmagpie" "qcom,debugcc-sdxprairie", - "qcom,debugcc-trinket", - "qcom,atoll-debugcc". + "qcom,debugcc-trinket". - qcom,gcc: phandle to the GCC device node. - qcom,videocc: phandle to the Video CC device node. - qcom,camcc: phandle to the Camera CC device node. diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.txt b/Documentation/devicetree/bindings/clock/qcom,dispcc.txt index dbfbf561b135..e8b6859e942f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc.txt @@ -9,8 +9,7 @@ Required properties : "qcom,dispcc-sdmmagpie", "qcom,dispcc-trinket", "qcom,dispcc-sdmshrike-v2", - "qcom,dispcc-sa6155", - "qcom,atoll-dispcc". + "qcom,dispcc-sa6155". - reg : Shall contain base register location and length. - reg-names: Address name. Must be "cc_base". - vdd_mm-supply: phandle to the MM_CX rail that needs to be voted on behalf diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt index 16bbfff1b777..8136c5458220 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt @@ -29,7 +29,6 @@ Required properties : "qcom,gcc-trinket" "qcom,gcc-sa6155" "qcom,gcc-sdxprairie-v2" - "qcom,atoll-gcc" - reg : shall contain base register location and length - #clock-cells : shall contain 1 diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt index ea6f76603020..f2d52ec58f59 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt @@ -8,8 +8,7 @@ Required properties : "qcom,gpucc-sm6150", "qcom,gpucc-sdmmagpie", "qcom,gpucc-trinket", - "qcom,gpucc-sa6155", - "qcom,atoll-gpucc". + "qcom,gpucc-sa6155". - reg : shall contain base register offset and size. - reg-names: names of registers listed in the same order as in the reg property. diff --git a/Documentation/devicetree/bindings/clock/qcom,npucc.txt b/Documentation/devicetree/bindings/clock/qcom,npucc.txt index ecd7d0d98fa4..d5e4ed6f0f9d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,npucc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,npucc.txt @@ -3,7 +3,7 @@ Qualcomm Technologies, Inc. NPU Clock & Reset Controller Binding Required properties : - compatible : must contain "qcom,npucc-sm8150" or "qcom,npucc-sm8150-v2" - or "qcom,npucc-sdmmagpie" or "qcom,atoll-npucc". + or "qcom,npucc-sdmmagpie". - reg : shall contain base register location and length. - reg-names: names of registers listed in the same order as in the reg property. diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmh.txt b/Documentation/devicetree/bindings/clock/qcom,rpmh.txt index a244c6376f11..ece6b9e5b769 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmh.txt +++ b/Documentation/devicetree/bindings/clock/qcom,rpmh.txt @@ -6,8 +6,7 @@ Required properties: "qcom,rpmh-clk-sm8150", "qcom,rpmh-clk-sdmshrike", "qcom,rpmh-clk-sdmmagpie" - "qcom,rpmh-clk-sdxprairie", - "qcom,rpmh-clk-atoll". + "qcom,rpmh-clk-sdxprairie". - #clock-cells: Must contain 1. - mboxes: List of RPMh mailbox phandle and channel identifier tuples. - mbox-names: List of names to identify the RPMh mailboxes used. diff --git a/Documentation/devicetree/bindings/clock/qcom,scc.txt b/Documentation/devicetree/bindings/clock/qcom,scc.txt index d60889ad94f2..d095b3eb57f3 100644 --- a/Documentation/devicetree/bindings/clock/qcom,scc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,scc.txt @@ -2,7 +2,7 @@ Qualcomm Technologies, Inc. Sensor Clock Controller Bindings Required properties: - compatible: shall contain "qcom,scc-sm8150" or "qcom,scc-sm8150-v2" or - "qcom,scc-sm6150" or "qcom,scc-sa6155" or "qcom,scc-sa8195". + "qcom,scc-sm6150" or qcom,scc-sa6155". - reg: shall contain base register location and length. - vdd_scc_cx-supply: the logic rail supply. - #clock-cells: shall contain 1. diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.txt b/Documentation/devicetree/bindings/clock/qcom,videocc.txt index 176a9876b167..2ba6e3b31fbc 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.txt @@ -3,8 +3,7 @@ Qualcomm Technologies, Inc. Video Clock & Reset Controller Bindings Required properties: - compatible: shall contain "qcom,videocc-sm8150" or "qcom,videocc-sm8150-v2" or "qcom,videocc-sm6150", "qcom,videocc-sdmmagpie" or - "qcom,videocc-trinket" or "qcom,videocc-sa6155" or - "qcom,atoll-videocc". + "qcom,videocc-trinket" or "qcom,videocc-sa6155". - reg: shall contain base register location and length. - reg-names: names of registers listed in the same order as in the reg property. - vdd_-supply: the logic rail supply which could be either MM or CX. diff --git a/Documentation/devicetree/bindings/display/msm/sde-lease.txt b/Documentation/devicetree/bindings/display/msm/sde-lease.txt deleted file mode 100644 index e165995c9f5b..000000000000 --- a/Documentation/devicetree/bindings/display/msm/sde-lease.txt +++ /dev/null @@ -1,28 +0,0 @@ -Qualcomm Technologies, Inc. SDE KMS LEASE - -Snapdragon Display Engine Lease registers with the Linux DRM/KMS framework to -facilitate DRM driver creation, publishing /dev/dri/card, n=1,2,... from -card0 with objects implicitly leased. - -Required properties -- compatible: Must be "qcom,sde-kms-lease". -- qcom,lease-connectors: Connector names leased to the card. -- qcom,lease-planes: Plane names leased to the card. - -Optional properties -- qcom,dev-name: Name of the lease device. - -Example: - card1: qcom,sde-kms-lease@0 { - compatible = "qcom,sde-kms-lease"; - qcom,dev-name = "msm_drm1"; - qcom,lease-connectors = "DSI-1"; - qcom,lease-planes = "plane-0", "plane-8"; - }; - - card2: qcom,sde-kms-lease@1 { - compatible = "qcom,sde-kms-lease"; - qcom,dev-name = "msm_drm2"; - qcom,lease-connectors = "DSI-2"; - qcom,lease-planes = "plane-1", "plane-9"; - }; diff --git a/Documentation/devicetree/bindings/dma/qcom_gpi.txt b/Documentation/devicetree/bindings/dma/qcom_gpi.txt index bb4a7ca3ae31..f1b4a429ed39 100644 --- a/Documentation/devicetree/bindings/dma/qcom_gpi.txt +++ b/Documentation/devicetree/bindings/dma/qcom_gpi.txt @@ -79,12 +79,6 @@ Main node properties: Value type: Array of Definition: Pair of values describing iova base and size to allocate. -Optional property: -- qcom,gpi-ee-offset - Usage: optional - Value type: u64 - Definition: Specifies the gsi ee register offset for the QUP. - ======== Example: ======== diff --git a/Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt b/Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt index 778e857769ca..d9e3c44b1a9c 100644 --- a/Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt +++ b/Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt @@ -143,8 +143,6 @@ Optional properties: 0 = default value - qcom,mdss-dsi-v-bottom-border: Vertical bottom border in pixel. 0 = default value -- qcom,mdss-dsi-overlap-pixels: Horizontal overlap pixels for certain panels. - 0 = default value - qcom,mdss-dsi-underflow-color: Specifies the controller settings for the panel under flow color. 0xff = default value. diff --git a/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt b/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt index 8bd956153384..74d9584c576a 100644 --- a/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt +++ b/Documentation/devicetree/bindings/drm/msm/sde-dsi.txt @@ -8,8 +8,7 @@ Required properties: - compatible: Should be "qcom,dsi-ctrl-hw-v". Supported versions include 1.4, 2.0 and 2.2. eg: qcom,dsi-ctrl-hw-v1.4, qcom,dsi-ctrl-hw-v2.0, - qcom,dsi-ctrl-hw-v2.2, qcom,dsi-ctrl-hw-v2.3, - qcom,dsi-ctrl-hw-v2.4 + qcom,dsi-ctrl-hw-v2.2, qcom,dsi-ctrl-hw-v2.3 And for dsi phy driver: qcom,dsi-phy-v0.0-hpm, qcom,dsi-phy-v0.0-lpm, qcom,dsi-phy-v1.0, qcom,dsi-phy-v2.0, diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index 7c9aa166ed71..48eef244060e 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt @@ -146,13 +146,6 @@ conditions. we can choose to have a single ASID associated with all domains for a context bank. -- qcom,testbus-version: - Testbus implementation is different in some hardware for eg some doesn't - have a separate register for programming tbu testbuses so, they share the - same register to program both tcu and tbu testbuses. on such hardware this - option can be used to specify the testbus version to support testbus interface. - Type is . - - clocks : List of clocks to be used during SMMU register access. See Documentation/devicetree/bindings/clock/clock-bindings.txt for information about the format. For each clock specified diff --git a/Documentation/devicetree/bindings/media/video/msm-cam-csiphy.txt b/Documentation/devicetree/bindings/media/video/msm-cam-csiphy.txt index a75935c1e3b8..0b00cc025f00 100644 --- a/Documentation/devicetree/bindings/media/video/msm-cam-csiphy.txt +++ b/Documentation/devicetree/bindings/media/video/msm-cam-csiphy.txt @@ -15,8 +15,7 @@ First Level Node - CSIPHY device Value type: Definition: Should be "qcom,csiphy-v1.0", "qcom,csiphy-v1.1", "qcom,csiphy-v1.2", - "qcom,csiphy-v1.2.2", "qcom,csiphy-v2.0", - "qcom,csiphy". + "qcom,csiphy-v2.0", "qcom,csiphy". - cell-index: csiphy hardware core index Usage: required diff --git a/Documentation/devicetree/bindings/media/video/msm-cam-ppi.txt b/Documentation/devicetree/bindings/media/video/msm-cam-ppi.txt deleted file mode 100644 index aeed60fa6055..000000000000 --- a/Documentation/devicetree/bindings/media/video/msm-cam-ppi.txt +++ /dev/null @@ -1,102 +0,0 @@ -* Qualcomm Technologies, Inc. MSM camera PPI - -======================= -Required Node Structure -======================= -The camera PPI node must be described in First level of device nodes. The -first level describe the overall PPI node structure. - -====================================== -First Level Node - PPI device -====================================== - -- compatible - Usage: required - Value type: - Definition: Should be "qcom,ppi-v1.0", - "qcom,ppi-v1.1", "qcom,ppi-v1.2", - "qcom,ppi-v2.0", "qcom,ppi". - -- cell-index: ppi hardware core index - Usage: required - Value type: - Definition: Should specify the Hardware index id. - -- reg - Usage: required - Value type: - Definition: offset and length of the register set - for the device for the ppi operating in - compatible mode. - -- reg-names - Usage: required - Value type: - Definition: Should specify relevant names to each - reg property defined. - -- reg-cam-base - Usage: required - Value type: - Definition: offset of PPI in camera hw block - -- interrupts - Usage: required - Value type: - Definition: Interrupt associated with PPI HW. - -- interrupt-names - Usage: required - Value type: - Definition: Name of the interrupt. - -- clock-names - Usage: required - Value type: - Definition: List of clock names required for PPI HW. - -- clock-rates - Usage: required - Value type: - Definition: List of clock rates in Hz for PPI HW. - -- clock-cntl-level - Usage: required - Value type: - Definition: All different clock level node can support. - -- clocks - Usage: required - Value type: - Definition: all clock phandle and source clocks. - -- regulator-names - Usage: required - Value type: - Definition: name of the voltage regulators required for the device. - -- gdscr-supply - Usage: required - Value type: - Definition: should contain gdsr regulator used for PPI clocks. - -Example: - qcom,ppi0@ace0000 { - cell-index = <0>; - compatible = "qcom,ppi170"; - reg-names = "ppi"; - reg = <0xace0000 0x200>; - reg-cam-base = <0xe0000>; - interrupt-names = "ppi"; - interrupts = <0 202 0>; - regulator-names = "gdscr", "refgen"; - gdscr-supply = <&titan_top_gdsc>; - clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, - <&clock_camcc CAM_CC_PPI0_CLK>, - <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, - <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>; - clock-names = "cphy_rx_clk_src", "ppi0_clk" - clock-rates = <400000000 0 300000000 0>; - clock-cntl-level = "turbo"; - status = "ok"; -}; diff --git a/Documentation/devicetree/bindings/mhi/msm_mhi_dev.txt b/Documentation/devicetree/bindings/mhi/msm_mhi_dev.txt index ece30e43d308..30174680a91d 100644 --- a/Documentation/devicetree/bindings/mhi/msm_mhi_dev.txt +++ b/Documentation/devicetree/bindings/mhi/msm_mhi_dev.txt @@ -31,18 +31,6 @@ Optional property: MHI driver on the host. This property is required if iatu property qcom,mhi-config-iatu is present. -MSM MHI DEV NET - -MSM MHI DEV enables communication with the host over a PCIe link using the -Network Interface. - -Required properties: - - compatible: should be "qcom,msm-mhi-dev-net" for MHI net device driver. - -Optional property: - - qcom,mhi-ethernet-interface;: If property is present use ethernet packet - parsing support. - Example: mhi: qcom,msm-mhi-dev { @@ -56,8 +44,3 @@ Example: qcom,mhi-ep-msi = <1>; qcom,mhi-version = <0x1000000>; }; - - qcom,mhi_net_dev { - compatible = "qcom,msm-mhi-dev-net"; - qcom,mhi-ethernet-interface; - }; diff --git a/Documentation/devicetree/bindings/pci/msm_pcie.txt b/Documentation/devicetree/bindings/pci/msm_pcie.txt index 8c12600f65a9..909913441ed7 100644 --- a/Documentation/devicetree/bindings/pci/msm_pcie.txt +++ b/Documentation/devicetree/bindings/pci/msm_pcie.txt @@ -78,8 +78,6 @@ Optional Properties: - qcom,phy-sequence: The initialization sequence to bring up the PCIe PHY. Should be specified in groups (offset, value, delay). Should be specified in groups (offset, value, delay). - - qcom,bw-scale: Table of CX voltage and rate change clock frequency pair - for PCIe bandwidth scaling. - qcom,use-19p2mhz-aux-clk: The frequency of PCIe AUX clock is 19.2MHz. - qcom,boot-option: Bits that alter PCIe bus driver boot sequence. Below details what happens when each bit is set diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6150-pinctrl b/Documentation/devicetree/bindings/pinctrl/qcom,sm6150-pinctrl index ff7848aeee2d..30fe7bdc947e 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm6150-pinctrl +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6150-pinctrl @@ -46,12 +46,6 @@ SM6150 platform. Value type: Definition: must be 2. Specifying the pin number and flags, as defined in -- dirconn-list: - Usage: optional - Value type: - Definition: a 3-tuple list which contains mapping of GPIO pin to - hardware IRQ, and a boolean for enabling the TLMM direct - connect interrupt for the pin. Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for a general description of GPIO and interrupt bindings. diff --git a/Documentation/devicetree/bindings/power/supply/qcom/oneplus_fastchg.txt b/Documentation/devicetree/bindings/power/supply/qcom/oneplus_fastchg.txt new file mode 100644 index 000000000000..95a17d1dddad --- /dev/null +++ b/Documentation/devicetree/bindings/power/supply/qcom/oneplus_fastchg.txt @@ -0,0 +1,42 @@ +* Fast charge control + +Required properties: + - compatible : "microchip,oneplus_fastchg" + - reg : Device address + - interrupts : IRQ specifier + + +Optional properties: + - microchip,mcu-en-gpio : enable or reset the mcu + - microchip,usb-sw-1-gpio : fast charge switch 1 control + - microchip,usb-sw-2-gpio : fast charge switch 2 control + - microchip,ap-clk : gpio work for clk + - microchip,ap-data : gpio work for data + +Example: + +&qupv3_se16_i2c { + oneplus_fastchg@26{ + status = "ok"; + compatible = "microchip,oneplus_fastchg"; + reg = <0x26>; + microchip,mcu-en-gpio = <&tlmm 10 0x00>; + microchip,usb-sw-1-gpio = <&tlmm 50 0x00>; + microchip,usb-sw-2-gpio = <&tlmm 82 0x00>; + microchip,ap-clk = <&tlmm 8 0x00>; + microchip,ap-data = <&tlmm 9 0x00>; + + pinctrl-names = "mux_fastchg_active", + "mux_fastchg_suspend", + "mcu_data_active", + "mcu_data_suspend"; + pinctrl-0 = <&fastchg_active + &usb_sw_active + &ap_clk_active>; + pinctrl-1 = <&usb_sw_suspend + &fastchg_suspend + &ap_clk_suspend>; + pinctrl-2 =<&ap_data_active>; + pinctrl-3 =<&ap_data_suspend>; + } +} \ No newline at end of file diff --git a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-qg.txt b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-qg.txt index 3daca154bb52..b00d7c7534d2 100644 --- a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-qg.txt +++ b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-qg.txt @@ -389,21 +389,6 @@ First Level Node - QGAUGE device 'qcom,qg-sleep-config' is enabled. the default value if not specified is 200ms. -- qcom,qg-fast-chg-config - Usage: optional - Value type: bool - Definition: Enables fast-charge configurtion for QG. This - allows configuring the FIFO length during - fast charge. - -- qcom,fast-chg-s2-fifo-length - Usage: optional - Value type: - Definition: The FIFO length to be applied when system enters - fast-chargging. Takes effect only if - 'qcom,qg-fast-chg-config' is enabled. The - default value if not specified is 1. - ========================================================== Second Level Nodes - Peripherals managed by QGAUGE driver ========================================================== diff --git a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-smb5.txt b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-smb5.txt index f8f71c901761..23803b2992e0 100644 --- a/Documentation/devicetree/bindings/power/supply/qcom/qpnp-smb5.txt +++ b/Documentation/devicetree/bindings/power/supply/qcom/qpnp-smb5.txt @@ -306,12 +306,6 @@ Charger specific properties: Definition: Boolean flag which when present enables h/w based skin temperature mitigation. -- qcom,en-skin-therm-mitigation - Usage: optional - Value type: bool - Definition: Boolean flag which when present enables skin - thermal mitigation. - - qcom,connector-internal-pull-kohm Usage: optional Value type: @@ -319,13 +313,6 @@ Charger specific properties: connector THERM, only valid values are (0/30/100/400). If not specified 100K is used as default pull-up. -- qcom,smb-internal-pull-kohm - Usage: optional - Value type: - Definition: Specifies internal pull-up configuration to be applied to - smb THERM, only valid values are (0/30/100/400). - If not specified 100K is used as default pull-up. - - qcom,wd-snarl-time-config Usage: optional Value type: diff --git a/Documentation/devicetree/bindings/sound/qcom,hsi2s.txt b/Documentation/devicetree/bindings/sound/qcom,hsi2s.txt index f3331cb6e376..debeef5780d6 100644 --- a/Documentation/devicetree/bindings/sound/qcom,hsi2s.txt +++ b/Documentation/devicetree/bindings/sound/qcom,hsi2s.txt @@ -4,10 +4,7 @@ Qualcomm Technologies, Inc. High Speed I2S Interface Required properties: - - compatible : Should include "qcom,hsi2s" - Should include target specific compatible field - "qcom,sa6155-hsi2s" for SA6155 - "qcom,sa8155-hsi2s" for SA8155 + - compatible : Should be "qcom,hsi2s" - number-of-interfaces : Denotes the number of HS-I2S interfaces - reg : Specifies the base physical address and the size of the HS-I2S register space @@ -15,8 +12,6 @@ Required properties: - interrupts : Interrupt number used by this interface - clocks : Core clocks used by this interface - clock-names : Clock names for each core clock - - bit-clock-hz : Default bit clock frequency in hertz - - interrupt-interval-ms : Default interrupt interval in milliseconds * HS-I2S interface nodes @@ -26,7 +21,6 @@ Required properties: - minor-number : Minor number of the character device interface Should be 0 for HS0 interface Should be 1 for HS1 interface - Should be 2 for HS2 interface - clocks : Interface clock used by this interface - clock-names : Clock name for the interface clock - pinctrl-names : Pinctrl state names for each pin group configuration @@ -41,7 +35,7 @@ Optional properties: Example: hsi2s: qcom,hsi2s { - compatible = "qcom,sa6155-hsi2s", "qcom,hsi2s"; + compatible = "qcom,hsi2s"; number-of-interfaces = <2>; reg = <0x1B40000 0x28000>; reg-names = "lpa_if"; diff --git a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt index 934a777e0614..e5f44ae56a8b 100644 --- a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt +++ b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt @@ -220,13 +220,6 @@ Required properties: inCall Music Delivery port ID is 32773. incall Music 2 Delivery port ID is 32770. -Optional properties: - - - qcom,msm-dai-q6-slim-dev-id : The Slimbus HW device (instance) ID associated - with Slimbus ports. - 0 - Slimbus HW device ID 0 (first instance) - 1 - Slimbus HW device ID 1 (second instance) - * msm_dai_cdc_dma [First Level Nodes] @@ -560,7 +553,6 @@ Example: qcom,msm-dai-q6-sb-0-rx { compatible = "qcom,msm-dai-q6-dev"; qcom,msm-dai-q6-dev-id = <16384>; - qcom,msm-dai-q6-slim-dev-id = <0>; }; qcom,msm-dai-q6-sb-0-tx { @@ -1078,7 +1070,6 @@ Example: Required properties: - compatible : "qcom,sm8150-asoc-snd-stub" for SM8150 target. -- compatible : "qcom,kona-asoc-snd-stub" for Kona target. - qcom,model : The user-visible name of this sound card. - qcom,tasha-mclk-clk-freq : MCLK frequency value for tasha codec - asoc-platform: This is phandle list containing the references to platform device @@ -1868,231 +1859,6 @@ Example: "msm-dai-q6-auxpcm.2"; }; -* SDX ASoC Auto Machine driver - -Required properties: -- compatible : "qcom,sdx-asoc-snd-auto" -- qcom,model : The user-visible name of this sound card. -- qcom,prim_mi2s_aux_master : Handle to prim_master pinctrl configurations -- qcom,prim_mi2s_aux_slave : Handle to prim_slave pinctrl configurations -- qcom,sec_mi2s_aux_master : Handle to sec_master pinctrl configurations -- qcom,sec_mi2s_aux_slave : Handle to sec_slave pinctrl configurations -- asoc-platform: This is phandle list containing the references to platform device - nodes that are used as part of the sound card dai-links. -- asoc-platform-names: This property contains list of platform names. The order of - the platform names should match to that of the phandle order - given in "asoc-platform". -- asoc-cpu: This is phandle list containing the references to cpu dai device nodes - that are used as part of the sound card dai-links. -- asoc-cpu-names: This property contains list of cpu dai names. The order of the - cpu dai names should match to that of the phandle order give - in "asoc-cpu". The cpu names are in the form of "%s.%d" form, - where the id (%d) field represents the back-end AFE port id that - this CPU dai is associated with. -- asoc-codec: This is phandle list containing the references to codec dai device - nodes that are used as part of the sound card dai-links. -- asoc-codec-names: This property contains list of codec dai names. The order of the - codec dai names should match to that of the phandle order given - in "asoc-codec". - -Example: - - sound-auto { - compatible = "qcom,sdx-asoc-snd-auto"; - qcom,model = "sdx-auto-i2s-snd-card"; - qcom,prim_mi2s_aux_master = <&prim_master>; - qcom,prim_mi2s_aux_slave = <&prim_slave>; - qcom,sec_mi2s_aux_master = <&sec_master>; - qcom,sec_mi2s_aux_slave = <&sec_slave>; - - asoc-platform = <&pcm0>, <&pcm1>, <&voip>, <&voice>, - <&loopback>, <&hostless>, <&afe>, <&routing>, - <&pcm_dtmf>, <&host_pcm>, <&compress>; - asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", - "msm-voip-dsp", "msm-pcm-voice", - "msm-pcm-loopback", "msm-pcm-hostless", - "msm-pcm-afe", "msm-pcm-routing", - "msm-pcm-dtmf", "msm-voice-host-pcm", - "msm-compress-dsp"; - asoc-cpu = <&dai_pri_auxpcm>, <&mi2s_prim>, <&mi2s_sec>, - <&dtmf_tx>, - <&rx_capture_tx>, <&rx_playback_rx>, - <&tx_capture_tx>, <&tx_playback_rx>, - <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, - <&afe_proxy_tx>, <&incall_record_rx>, - <&incall_record_tx>, <&incall_music_rx>, - <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, - <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, - <&dai_sec_auxpcm>; - asoc-cpu-names = "msm-dai-q6-auxpcm.1", - "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", - "msm-dai-stub-dev.4", "msm-dai-stub-dev.5", - "msm-dai-stub-dev.6", "msm-dai-stub-dev.7", - "msm-dai-stub-dev.8", "msm-dai-q6-dev.224", - "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", - "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", - "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", - "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", - "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", - "msm-dai-q6-auxpcm.2"; - asoc-codec = <&tlv320aic3x_codec>, <&stub_codec>; - asoc-codec-names = "tlv320aic3x-codec", "msm-stub-codec.1"; - }; - -* KONA ASoC Machine driver - -Required properties: -- compatible : "qcom,kona-asoc-snd". -- qcom,model : The user-visible name of this sound card. -- qcom,audio-routing : A list of the connections between audio components. -- asoc-platform: This is phandle list containing the references to platform device - nodes that are used as part of the sound card dai-links. -- asoc-platform-names: This property contains list of platform names. The order of - the platform names should match to that of the phandle order - given in "asoc-platform". -- asoc-cpu: This is phandle list containing the references to cpu dai device nodes - that are used as part of the sound card dai-links. -- asoc-cpu-names: This property contains list of cpu dai names. The order of the - cpu dai names should match to that of the phandle order given - in "asoc-cpu". The cpu names are in the form of "%s.%d" form, - where the id (%d) field represents the back-end AFE port id that - this CPU dai is associated with. -- asoc-codec: This is phandle list containing the references to codec dai device - nodes that are used as part of the sound card dai-links. -- asoc-codec-names: This property contains list of codec dai names. The order of the - codec dai names should match to that of the phandle order given - in "asoc-codec". -- qcom,codec-aux-devs: This is phandle list containing the references to Auxilary - codec devices. - -Optional properties: -- qcom,msm-mi2s-master: This property is used to inform machine driver - if MSM is the clock master of mi2s. 1 means master and 0 means slave. The - first entry is primary mi2s; the second entry is secondary mi2s, and so on. -- qcom,msm-mbhc-hphl-swh: This property is used to distinguish headset HPHL - switch type on target typically the switch type will be normally open or - normally close, value for this property 0 for normally close and 1 for - normally open. -- qcom,msm-mbhc-gnd-swh: This property is used to distinguish headset GND - switch type on target typically the switch type will be normally open or - normally close, value for this property 0 for normally close and 1 for - normally open. -- qcom,wsa-max-devs : Maximum number of WSA881x devices present in the target -- qcom,wsa-devs : List of phandles for all possible WSA881x devices supported for the target -- qcom,wsa-aux-dev-prefix : Name prefix with Left/Right configuration for WSA881x device -- qcom,ext-disp-audio-rx: Property to specify if Audio over Display port is supported for the target -- qcom,wcn-btfm : Property to specify if WCN BT/FM chip is used for the target -- qcom,mi2s-audio-intf: Property to specify if MI2S interface is used for the target -- qcom,auxpcm-audio-intf: Property to specify if Aux PCM interface is used for the target -- qcom,cdc-dmic-gpios : phandle for Digital mic clk and data gpios. -- qcom,msm_audio_ssr_devs: List the snd event framework clients -- qcom,afe-rxtx-lb: AFE RX to TX loopback. - -Example: - kona_snd: sound { - status = "okay"; - compatible = "qcom,kona-asoc-snd"; - qcom,ext-disp-audio-rx = <1>; - qcom,wcn-btfm = <1>; - qcom,mi2s-audio-intf = <1>; - qcom,auxpcm-audio-intf = <1>; - qcom,afe-rxtx-lb = <1>; - - asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, - <&loopback>, <&compress>, <&hostless>, - <&afe>, <&lsm>, <&routing>, <&compr>, - <&pcm_noirq>; - asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", - "msm-pcm-dsp.2", "msm-voip-dsp", - "msm-pcm-voice", "msm-pcm-loopback", - "msm-compress-dsp", "msm-pcm-hostless", - "msm-pcm-afe", "msm-lsm-client", - "msm-pcm-routing", "msm-compr-dsp", - "msm-pcm-dsp-noirq"; - asoc-cpu = <&dai_dp>, - <&dai_mi2s0>, <&dai_mi2s1>, - <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_pri_auxpcm>, - <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, - <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, - <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, - <&afe_proxy_tx>, <&incall_record_rx>, - <&incall_record_tx>, <&incall_music_rx>, - <&incall_music_2_rx>, - <&usb_audio_rx>, <&usb_audio_tx>, - <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, - <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, - <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, - <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, - <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>, - <&wsa_cdc_dma_0_rx>, <&wsa_cdc_dma_0_tx>, - <&wsa_cdc_dma_1_rx>, <&wsa_cdc_dma_1_tx>, - <&wsa_cdc_dma_2_tx>, - <&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>, - <&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>, - <&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>, - <&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>, - <&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>, - <&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>, - <&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>, - <&tx_cdc_dma_6_tx>, <&tx_cdc_dma_7_tx>; - asoc-cpu-names = "msm-dai-q6-dp.24608", - "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", - "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", - "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", - "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", - "msm-dai-q6-dev.224", - "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", - "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", - "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", - "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16398", - "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", - "msm-dai-q6-dev.16400", - "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", - "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", - "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", - "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", - "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", - "msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36929", - "msm-dai-cdc-dma-dev.45056", - "msm-dai-cdc-dma-dev.45057", - "msm-dai-cdc-dma-dev.45058", - "msm-dai-cdc-dma-dev.45059", - "msm-dai-cdc-dma-dev.45061", - "msm-dai-cdc-dma-dev.45089", - "msm-dai-cdc-dma-dev.45091", - "msm-dai-cdc-dma-dev.45120", - "msm-dai-cdc-dma-dev.45121", - "msm-dai-cdc-dma-dev.45122", - "msm-dai-cdc-dma-dev.45123", - "msm-dai-cdc-dma-dev.45124", - "msm-dai-cdc-dma-dev.45125", - "msm-dai-cdc-dma-dev.45126", - "msm-dai-cdc-dma-dev.45127", - "msm-dai-cdc-dma-dev.45128", - "msm-dai-cdc-dma-dev.45129", - "msm-dai-cdc-dma-dev.45130", - "msm-dai-cdc-dma-dev.45131", - "msm-dai-cdc-dma-dev.45133", - "msm-dai-cdc-dma-dev.45135"; - qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; - qcom,msm-mbhc-hphl-swh = <1>; - qcom,msm-mbhc-gnd-swh = <1>; - qcom,cdc-dmic-gpios = <&cdc_dmic12_gpios>, <&cdc_dmic34_gpios>; - asoc-codec = <&stub_codec>, <&bolero>, - <&ext_disp_audio_codec>; - asoc-codec-names = "msm-stub-codec.1", "bolero-codec", - "msm-ext-disp-audio-codec-rx"; - qcom,wsa-max-devs = <2>; - qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>, - <&wsa881x_0213>, <&wsa881x_0214>; - qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", - "SpkrLeft", "SpkrRight"; - qcom,codec-aux-devs = <&wcd937x_codec>; - qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>; - }; - * voice-mhi-audio Required properties: diff --git a/Documentation/devicetree/bindings/sound/tfa98xx.txt b/Documentation/devicetree/bindings/sound/tfa98xx.txt new file mode 100644 index 000000000000..cf43fd717d5b --- /dev/null +++ b/Documentation/devicetree/bindings/sound/tfa98xx.txt @@ -0,0 +1,23 @@ +Tfa98xx device + +Required Properties +- compatible Must be "compatible = "nxp,tfa98xx". + +Example: + + + &qupv3_se4_i2c { + tfa98xx_right: tfa98xx_right@34 { + compatible = "nxp,tfa98xx"; + reg = <0x34>; + reset-gpio = <&tlmm 37 0>; + status = "ok"; + }; + + tfa98xx_left: tfa98xx_left@35 { + compatible = "nxp,tfa98xx"; + reg = <0x35>; + reset-gpio = <&tlmm 37 0>; + status = "ok"; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt b/Documentation/devicetree/bindings/sound/tlv320aic3x.txt index 41fec22d6480..ba5b45c483f5 100644 --- a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt +++ b/Documentation/devicetree/bindings/sound/tlv320aic3x.txt @@ -17,8 +17,7 @@ Required properties: Optional properties: -- gpio-reset - gpio pin number used for codec reset, default active low -- reset-inverted - set the reset gpio mode as active high +- gpio-reset - gpio pin number used for codec reset - ai3x-gpio-func - - AIC3X_GPIO1 & AIC3X_GPIO2 Functionality - Not supported on tlv320aic3104 - ai3x-micbias-vg - MicBias Voltage required. diff --git a/Documentation/devicetree/bindings/sound/wcd_codec.txt b/Documentation/devicetree/bindings/sound/wcd_codec.txt index 6d51456a9b5c..7f3183e8a97f 100644 --- a/Documentation/devicetree/bindings/sound/wcd_codec.txt +++ b/Documentation/devicetree/bindings/sound/wcd_codec.txt @@ -455,7 +455,6 @@ Required properties: soundwire core registers. - clock-names : clock names defined for WSA macro - clocks : clock handles defined for WSA macro - - qcom,default-clk-id: Default clk ID used for WSA macro - qcom,wsa-swr-gpios: phandle for SWR data and clock GPIOs of WSA macro - qcom,wsa-bcl-pmic-params: u8 array of PMIC ID, SID and PPID in same order required to be configured to receive interrupts @@ -472,15 +471,6 @@ Example: <&clock_audio_wsa_2 0>; qcom,wsa-swr-gpios = &wsa_swr_gpios; qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>; - qcom,default-clk-id = ; - swr_0: wsa_swr_master { - compatible = "qcom,swr-mstr"; - wsa881x_1: wsa881x@20170212 { - compatible = "qcom,wsa881x"; - reg = <0x00 0x20170212>; - qcom,spkr-sd-n-gpio = <&tlmm 80 0>; - }; - }; }; }; @@ -490,18 +480,8 @@ Required properties: - compatible = "qcom,va-macro"; - reg: Specifies the VA macro base address for Bolero soundwire core registers. - - clock-names : clock names defined for VA macro - - clocks : clock handles defined for VA macro - - qcom,default-clk-id: Default clk ID used for VA macro - - va-vdd-micb-supply: phandle of mic bias supply's regulator device tree node - - qcom,va-vdd-micb-voltage: mic bias supply's voltage level min and max in mV - - qcom,va-vdd-micb-current: mic bias supply's max current in mA - - qcom,va-dmic-sample-rate: Sample rate defined for DMIC connected to VA macro - -Optional properties: - - qcom,va-clk-mux-select: VA macro MCLK MUX selection - - qcom,va-island-mode-muxsel: VA macro island mode MUX selection - This property is required if qcom,va-clk-mux-select is provided + - clock-names : clock names defined for WSA macro + - clocks : clock handles defined for WSA macro Example: @@ -511,13 +491,6 @@ Example: reg = <0x0C490000 0x0>; clock-names = "va_core_clk"; clocks = <&clock_audio_va 0>; - qcom,default-clk-id = ; - va-vdd-micb-supply = <&S4A>; - qcom,va-vdd-micb-voltage = <1800000 1800000>; - qcom,va-vdd-micb-current = <11200>; - qcom,va-dmic-sample-rate = <4800000>; - qcom,va-clk-mux-select = <1>; - qcom,va-island-mode-muxsel = <0x033A0000>; }; }; @@ -529,7 +502,6 @@ Required properties: soundwire core registers. - clock-names : clock names defined for RX macro - clocks : clock handles defined for RX macro - - qcom,default-clk-id: Default clk ID used for RX macro - qcom,rx-swr-gpios: phandle for SWR data and clock GPIOs of RX macro - qcom,rx_mclk_mode_muxsel: register address for RX macro MCLK mode mux select - qcom,rx-bcl-pmic-params: u8 array of PMIC ID, SID and PPID in same order @@ -548,15 +520,11 @@ Example: qcom,rx-swr-gpios = <&rx_swr_gpios>; qcom,rx_mclk_mode_muxsel = <0x62C25020>; qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>; - qcom,default-clk-id = ; swr_1: rx_swr_master { compatible = "qcom,swr-mstr"; wcd937x_rx_slave: wcd937x-rx-slave { compatible = "qcom,wcd937x-slave"; }; - wcd938x_rx_slave: wcd938x-rx-slave { - compatible = "qcom,wcd938x-slave"; - }; }; }; }; @@ -592,8 +560,6 @@ Example: wcd937x_tx_slave: wcd937x-tx-slave { compatible = "qcom,wcd937x-slave"; }; - wcd938x_tx_slave: wcd938x-tx-slave { - compatible = "qcom,wcd938x-slave"; }; }; }; @@ -682,120 +648,3 @@ wcd937x_codec: wcd937x-codec { qcom,cdc-on-demand-supplies = "cdc-vdd-buck", "cdc-vdd-mic-bias"; }; - -Traverso Codec - -Required properties: - - compatible: "qcom,wcd938x-codec"; - - qcom,rx_swr_ch_map: mapping of swr rx slave port configuration to port_type and also - corresponding master port type it need to attach. - format: - same port_id configurations have to be grouped, and in ascending order. - - qcom,tx_swr_ch_map: mapping of swr tx slave port configuration to port_type and also - corresponding master port type it need to attach. - format: - same port_id configurations have to be grouped, and in ascending order. - - qcom,wcd-rst-gpio-node: Phandle reference to the DT node having codec reset gpio - configuration. If this property is not defined, it is - expected to atleast define "qcom,cdc-reset-gpio" property. - - qcom,rx-slave: phandle reference of Soundwire Rx slave device. - - qcom,tx-slave: phandle reference of Soundwire Tx slave device. - -Optional properties: - - - cdc-vdd-rxtx-supply: phandle of rxtx supply's regulator device tree node. - - qcom,cdc-vdd-rxtx-voltage: rxtx supply's voltage level min and max in mV. - - qcom,cdc-vdd-rxtx-current: rxtx supply's max current in mA. - - - cdc-vddio-supply: phandle of io supply's regulator device tree node. - - qcom,cdc-vddio-voltage: io supply's voltage level min and max in mV. - - qcom,cdc-vddio-current: io supply's max current in mA. - - - cdc-vdd-buck-supply: phandle of buck supply's regulator device tree node. - - qcom,cdc-vdd-buck-voltage: buck supply's voltage level min and max in mV. - - qcom,cdc-vdd-buck-current: buck supply's max current in mA. - - - cdc-vdd-mic-bias-supply: phandle of mic bias supply's regulator device tree node. - - qcom,cdc-vdd-mic-bias-voltage: mic bias supply's voltage level min and max in mV. - - qcom,cdc-vdd-mic-bias-current: mic bias supply's max current in mA. - - - qcom,cdc-static-supplies: List of supplies to be enabled prior to codec - hardware probe. Supplies in this list will be - stay enabled. - - - qcom,cdc-on-demand-supplies: List of supplies which can be enabled - dynamically. - Supplies in this list are off by default. - -Example: -wcd938x_codec: wcd938x-codec { - compatible = "qcom,wcd938x-codec"; - qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>, - <0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x3 0 CLSH>, - <2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>, - <3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>, - <4 DSD_R 0x2 0 DSD_R>; - qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>, - <1 ADC2 0x1 0 ADC3>, <1 ADC3 0x2 0 ADC4>, - <2 DMIC0 0x1 0 DMIC0>, <2 DMIC1 0x2 0 DMIC1>, - <2 MBHC 0x4 0 DMIC2>, <3 DMIC2 0x1 0 DMIC4>, - <3 DMIC3 0x2 0 DMIC5>, <3 DMIC4 0x4 0 DMIC6>, - <3 DMIC5 0x8 0 DMIC7>; - - qcom,wcd-rst-gpio-node = <&wcd938x_rst_gpio>; - qcom,rx-slave = <&wcd938x_rx_slave>; - qcom,tx-slave = <&wcd938x_tx_slave>; - - cdc-vdd-buck-supply = <&S4A>; - qcom,cdc-vdd-buck-voltage = <1800000 1800000>; - qcom,cdc-vdd-buck-current = <650000>; - - cdc-vdd-rxtx-supply = <&S4A>; - qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>; - qcom,cdc-vdd-rxtx-current = <30000>; - - cdc-vddio-supply = <&S4A>; - qcom,cdc-vddio-voltage = <1800000 1800000>; - qcom,cdc-vddio-current = <30000>; - - cdc-vdd-mic-bias-supply = <&BOB>; - qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>; - qcom,cdc-vdd-mic-bias-current = <30000>; - - qcom,cdc-static-supplies = "cdc-vdd-rxtx", - "cdc-vddio"; - qcom,cdc-on-demand-supplies = "cdc-vdd-buck", - "cdc-vdd-mic-bias"; -}; - -Bolero Clock Resource Manager - -Required Properties: - - compatible = "qcom,bolero-clk-rsc-mngr"; - - qcom,fs-gen-sequence: Register sequence for fs clock generation - - clock-names : clock names defined for WSA macro - - clocks : clock handles defined for WSA macro - -Optional Properties: - - qcom,rx_mclk_mode_muxsel: register address for RX macro MCLK mode mux select - - qcom,wsa_mclk_mode_muxsel: register address for WSA macro MCLK mux select - - qcom,va_mclk_mode_muxsel: register address for VA macro MCLK mode mux select - -Example: -&bolero { - bolero-clock-rsc-manager { - compatible = "qcom,bolero-clk-rsc-mngr"; - qcom,fs-gen-sequence = <0x3000 0x1>, - <0x3004 0x1>, <0x3080 0x2>; - qcom,rx_mclk_mode_muxsel = <0x033240D8>; - qcom,wsa_mclk_mode_muxsel = <0x033220D8>; - qcom,va_mclk_mode_muxsel = <0x033A0000>; - clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", - "rx_npl_clk", "wsa_core_clk", "wsa_npl_clk", - "va_core_clk", "va_npl_clk"; - clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>, - <&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>, - <&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>, - <&clock_audio_va_1 0>, <&clock_audio_va_2 0>; - }; -}; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/spmi/qcom,viospmi-pmic-arb.txt b/Documentation/devicetree/bindings/spmi/qcom,viospmi-pmic-arb.txt deleted file mode 100644 index 2221ecea91cd..000000000000 --- a/Documentation/devicetree/bindings/spmi/qcom,viospmi-pmic-arb.txt +++ /dev/null @@ -1,38 +0,0 @@ -QTI Virtio SPMI controller (Virtio PMIC Arbiter) - -The Virtio SPMI PMIC Arbiter is a frontend proxy based on backend virtio device. - -Required properties: -- compatible : should be "qcom,viospmi-pmic-arb". -- #address-cells : must be set to 2 -- #size-cells : must be set to 0 -- interrupt-controller : boolean indicator that the PMIC arbiter is an interrupt controller -- #interrupt-cells : must be set to 4. Interrupts are specified as a 4-tuple: - cell 1: slave ID for the requested interrupt (0-15) - cell 2: peripheral ID for requested interrupt (0-255) - cell 3: the requested peripheral interrupt (0-7) - cell 4: interrupt flags indicating level-sense information, as defined in - dt-bindings/interrupt-controller/irq.h - -Example Virtio PMIC-Arbiter: - - spmi_bus: qcom,spmi { - compatible = "qcom,viospmi-pmic-arb"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - viospmi: virtio-spmi@c440000 { - compatible = "virtio,mmio"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xc440000 0x1100>; - interrupts = ; - status = "okay"; - }; diff --git a/Documentation/devicetree/bindings/thermal/qcom-bcl-pmic5.txt b/Documentation/devicetree/bindings/thermal/qcom-bcl-pmic5.txt index 8e5ba1b7e914..82da01868532 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-bcl-pmic5.txt +++ b/Documentation/devicetree/bindings/thermal/qcom-bcl-pmic5.txt @@ -26,9 +26,11 @@ Required Parameters: interrupt names will be used by the drivers to identify the interrupts, instead of specifying the ID's. bcl driver will accept these standard interrupts. - "bcl-lvl0", - "bcl-lvl1", - "bcl-lvl2", + "bcl-ibat-lvl0", + "bcl-ibat-lvl1", + "bcl-vbat-lvl0", + "bcl-vbat-lvl1", + "bcl-vbat-lvl2", Optional Parameters: - qcom,ibat-use-qg-adc-5a: This optional property is used to divide Ibat @@ -42,7 +44,7 @@ Example: reg = <0x4200 0x100>; interrupts = <0x2 0x42 0x0 IRQ_TYPE_NONE>, <0x2 0x42 0x1 IRQ_TYPE_NONE>; - interrupt-names = "bcl-lvl0", - "bcl-lvl1"; + interrupt-names = "bcl-ibat-lvl0", + "bcl-vbat-lvl0"; qcom,ibat-use-qg-adc-5a; }; diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt index 0c451273a926..2beaa9b8dc3e 100644 --- a/Documentation/devicetree/bindings/usb/msm-ssusb.txt +++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt @@ -75,8 +75,6 @@ Optional properties : - qcom,gsi-reg-offset: USB GSI wrapper registers offset. It is must to provide this if qcom,num-gsi-evt-buffs property is specified. Check dwc3-msm driver for order and name of register offset need to provide. -- qcom,gsi-disable-io-coherency: IO-coherency is enabled by default in usb gsi driver. - This property disables io-coherency in usb gsi driver. - qcom,pm-qos-latency: This represents max tolerable CPU latency in microsecs, which is used as a vote by driver to get max performance in perf mode. - qcom,smmu-s1-bypass: If present, configure SMMU to bypass stage 1 translation. diff --git a/Documentation/devicetree/bindings/usb/qcom,msm-phy.txt b/Documentation/devicetree/bindings/usb/qcom,msm-phy.txt index a29332c48f90..d62ccc012913 100644 --- a/Documentation/devicetree/bindings/usb/qcom,msm-phy.txt +++ b/Documentation/devicetree/bindings/usb/qcom,msm-phy.txt @@ -202,10 +202,8 @@ Optional properties: - qcom,emu-init-seq : emulation initialization sequence with value,reg pair. - qcom,phy-pll-reset-seq : emulation PLL reset sequence with value,reg pair. - qcom,emu-dcm-reset-seq : emulation DCM reset sequence with value,reg pair. - - qcom,tune2-efuse-bit-pos: TUNE2 parameter related start bit position with EFUSE register for "qcom,qusb2phy". - - qcom,tune2-efuse-num-bits: Number of bits based value to use for TUNE2 high nibble for "qcom,qusb2phy". - - qcom,efuse-bit-pos: start bit position within EFUSE register for "qcom,qusb2phy-v2". - - qcom,efuse-num-bits: Number of bits to read from EFUSE register for "qcom,qusb2phy-v2". + - qcom,efuse-bit-pos: start bit position within EFUSE register + - qcom,efuse-num-bits: Number of bits to read from EFUSE register - qcom,emulation: Indicates that we are running on emulation platform. - qcom,hold-reset: Indicates that hold QUSB PHY into reset state. - qcom,phy-clk-scheme: Should be one of "cml" or "cmos" if ref_clk_addr is provided. diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 921637fd8d71..61114fefeed5 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -390,3 +390,6 @@ zidoo Shenzhen Zidoo Technology Co., Ltd. zii Zodiac Inflight Innovations zte ZTE Corp. zyxel ZyXEL Communications Corp. +oneplus ONEPLUS Corp. +oneplus,fpdetect oneplus Fingerprint +goodix,fingerprint goodix Fingerprint diff --git a/Documentation/filesystems/cifs/winucase_convert.pl b/Documentation/filesystems/cifs/winucase_convert.pl old mode 100755 new mode 100644 diff --git a/Documentation/s390/config3270.sh b/Documentation/s390/config3270.sh old mode 100644 new mode 100755 diff --git a/Documentation/sphinx/kernel_include.py b/Documentation/sphinx/kernel_include.py old mode 100755 new mode 100644 diff --git a/Documentation/sphinx/parse-headers.pl b/Documentation/sphinx/parse-headers.pl old mode 100755 new mode 100644 diff --git a/Documentation/sphinx/rstFlatTable.py b/Documentation/sphinx/rstFlatTable.py old mode 100755 new mode 100644 diff --git a/Documentation/target/target-export-device b/Documentation/target/target-export-device old mode 100755 new mode 100644 diff --git a/Documentation/target/tcm_mod_builder.py b/Documentation/target/tcm_mod_builder.py old mode 100755 new mode 100644 diff --git a/Makefile b/Makefile index 582c1acd42ae..8b0ec4425a3e 100644 --- a/Makefile +++ b/Makefile @@ -531,6 +531,7 @@ config: scripts_basic outputmakefile FORCE $(Q)$(MAKE) $(build)=scripts/kconfig $@ %config: scripts_basic outputmakefile FORCE + $(shell cp -rf $(KBUILD_SRC)/../oneplus/ $(KBUILD_SRC)/../) $(Q)$(MAKE) $(build)=scripts/kconfig $@ else @@ -587,7 +588,7 @@ scripts: scripts_basic include/config/auto.conf include/config/tristate.conf \ # Objects we will link into vmlinux / subdirs we need to visit init-y := init/ -drivers-y := drivers/ sound/ firmware/ +drivers-y := drivers/ sound/ firmware/ coretech/ net-y := net/ libs-y := lib/ core-y := usr/ diff --git a/arch/arm/boot/dts/qcom b/arch/arm/boot/dts/qcom deleted file mode 120000 index 5bfdaf7a4c4b..000000000000 --- a/arch/arm/boot/dts/qcom +++ /dev/null @@ -1 +0,0 @@ -../../../arm64/boot/dts/qcom \ No newline at end of file diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile new file mode 100644 index 000000000000..7480090de710 --- /dev/null +++ b/arch/arm/boot/dts/qcom/Makefile @@ -0,0 +1,344 @@ +# SPDX-License-Identifier: GPL-2.0 +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY_QCOM),y) +dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb +dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb +ifeq ($(CONFIG_ARM64),y) +dtb-$(CONFIG_ARCH_QCS405) += qcs405-rumi.dtb \ + qcs405-iot-sku1.dtb \ + qcs405-iot-sku2.dtb \ + qcs405-iot-sku3.dtb \ + qcs405-iot-sku4.dtb \ + qcs405-iot-sku5.dtb \ + qcs405-iot-sku6.dtb \ + qcs405-iot-sku7.dtb \ + qcs405-iot-sku8.dtb \ + qcs405-iot-sku9.dtb \ + qcs405-iot-sku10.dtb \ + qcs405-iot-sku11.dtb \ + qcs405-iot-sku12.dtb \ + qcs401-iot-sku1.dtb +else +dtb-$(CONFIG_ARCH_QCS405) += qcs403-iot-sku1.dtb \ + qcs403-iot-sku2.dtb \ + qcs403-iot-sku3.dtb \ + qcs403-iot-sku4.dtb +endif + +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) + dtbo-$(CONFIG_ARCH_SM8150) += \ + sm8150-cdp-overlay.dtbo \ + sm8150-mtp-overlay.dtbo \ + sm8150-rumi-overlay.dtbo \ + sm8150-qrd-overlay.dtbo \ + sm8150-qrd-dvt-overlay.dtbo \ + sa8155-adp-star-overlay.dtbo \ + sa8155p-adp-star-overlay.dtbo \ + sa8155-v2-adp-air-overlay.dtbo \ + sa8155p-v2-adp-air-overlay.dtbo \ + sa8155-adp-alcor-overlay.dtbo \ + sa8155p-adp-alcor-overlay.dtbo \ + sm8150-sdx50m-cdp-overlay.dtbo \ + sm8150-sdx50m-mtp-overlay.dtbo \ + sm8150-sdx50m-mtp-2.5k-panel-overlay.dtbo \ + sm8150-sdx50m-qrd-overlay.dtbo \ + sm8150-sdxprairie-cdp-overlay.dtbo \ + sm8150-sdxprairie-mtp-overlay.dtbo \ + sm8150-sdxprairie-v2-cdp-overlay.dtbo \ + sm8150-sdxprairie-v2-mtp-overlay.dtbo \ + sm8150-hdk-overlay.dtbo + +sm8150-cdp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +sm8150-mtp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +sm8150-rumi-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +sm8150-qrd-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +sm8150-hdk-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +sm8150-qrd-dvt-overlay.dtbo-base := sm8150-v2.dtb sm8150p-v2.dtb +sa8155-adp-star-overlay.dtbo-base := sa8155.dtb sa8155-v2.dtb +sa8155p-adp-star-overlay.dtbo-base := sa8155p.dtb sa8155p-v2.dtb +sa8155-v2-adp-air-overlay.dtbo-base := sa8155.dtb sa8155-v2.dtb +sa8155p-v2-adp-air-overlay.dtbo-base := sa8155p.dtb sa8155p-v2.dtb +sa8155-adp-alcor-overlay.dtbo-base := sa8155.dtb sa8155-v2.dtb +sa8155p-adp-alcor-overlay.dtbo-base := sa8155p.dtb sa8155p-v2.dtb +sm8150-sdx50m-cdp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +sm8150-sdx50m-mtp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +sm8150-sdx50m-mtp-2.5k-panel-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +sm8150-sdx50m-qrd-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +sm8150-sdxprairie-cdp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +sm8150-sdxprairie-mtp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +endif +endif + +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) + dtbo-$(CONFIG_ARCH_SM8150) += \ + sm8150-mtp-overlay.dtbo \ + sm8150-sdxprairie-mtp-overlay.dtbo \ + guacamole-overlay-t0.dtbo \ + guacamole-overlay-evt1.dtbo \ + guacamole-overlay-evt2.dtbo \ + guacamole-overlay-evt2-second.dtbo \ + guacamole-overlay-evt3.dtbo \ + guacamole-overlay-dvt.dtbo \ + guacamole-overlay-pvt.dtbo \ + guacamoleb-overlay-t0.dtbo \ + guacamoleb-overlay-evt.dtbo \ + guacamoleb-overlay-dvt.dtbo \ + guacamoleb-overlay-pvt.dtbo \ + sm8150-sdx50m-mtp-overlay.dtbo \ + guacamole-sdx50m-overlay-t0.dtbo \ + guacamole-sdx50m-overlay-evt1.dtbo \ + guacamole-sdx50m-overlay-evt2.dtbo \ + guacamole-sdx50m-overlay-dvt.dtbo \ + guacamole-sdx50m-overlay-pvt.dtbo \ + guacamoles-sdx50m-overlay-t0.dtbo \ + guacamoles-sdx50m-overlay-evt.dtbo \ + guacamoles-sdx50m-overlay-dvt.dtbo \ + guacamoles-sdx50m-overlay-pvt.dtbo + +sm8150-mtp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +sm8150-sdxprairie-mtp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-t0.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-evt1.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-evt2.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-evt2-second.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-evt3.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-dvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-pvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoleb-overlay-t0.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoleb-overlay-evt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoleb-overlay-dvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoleb-overlay-pvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +sm8150-sdx50m-mtp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-sdx50m-overlay-t0.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-sdx50m-overlay-evt1.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-sdx50m-overlay-evt2.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-sdx50m-overlay-dvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-sdx50m-overlay-pvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoles-sdx50m-overlay-t0.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoles-sdx50m-overlay-evt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoles-sdx50m-overlay-dvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoles-sdx50m-overlay-pvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +sm8150-sdxprairie-v2-cdp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +sm8150-sdxprairie-v2-mtp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +else +dtb-$(CONFIG_ARCH_SM8150) += sm8150-rumi.dtb \ + sm8150-mtp.dtb \ + sm8150-cdp.dtb \ + sm8150-qrd.dtb \ + sa8155-adp-star.dtb \ + sa8155p-adp-star.dtb \ + sa8155-v2-adp-star.dtb \ + sa8155p-v2-adp-star.dtb \ + sa8155-v2-adp-air.dtb \ + sa8155p-v2-adp-air.dtb \ + sa8155-adp-alcor.dtb \ + sa8155p-adp-alcor.dtb \ + sm8150-v2-rumi.dtb \ + sm8150-v2-mtp.dtb \ + sm8150-v2-cdp.dtb \ + sm8150-v2-qrd.dtb \ + sm8150-v2-qrd-dvt.dtb \ + sm8150p-mtp.dtb \ + sm8150p-cdp.dtb \ + sm8150p-qrd.dtb \ + sm8150p-v2-mtp.dtb \ + sm8150p-v2-cdp.dtb \ + sm8150p-v2-qrd.dtb \ + sm8150-hdk.dtb \ + sm8150p-hdk.dtb +endif + +dtb-$(CONFIG_QTI_GVM) += sa8155-vm.dtb \ + sa8155-vm-lv.dtb \ + sa8155-vm-lv-mt.dtb \ + sa8155-vm-la-mt.dtb \ + sa6155p-vm.dtb \ + sa8195-vm.dtb + +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) + dtbo-$(CONFIG_ARCH_SDMSHRIKE) += \ + sdmshrike-cdp-overlay.dtbo \ + sdmshrike-mtp-overlay.dtbo \ + sa8195p-adp-star-overlay.dtbo + +sdmshrike-cdp-overlay.dtbo-base := sdmshrike.dtb sdmshrike-v2.dtb +sdmshrike-mtp-overlay.dtbo-base := sdmshrike.dtb sdmshrike-v2.dtb +sa8195p-adp-star-overlay.dtbo-base := sa8195p.dtb +else +dtb-$(CONFIG_ARCH_SDMSHRIKE) += sdmshrike-rumi.dtb \ + sdmshrike-mtp.dtb \ + sdmshrike-cdp.dtb \ + sdmshrike-v2-mtp.dtb \ + sa8195p-adp-star.dtb +endif + +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) + dtbo-$(CONFIG_ARCH_SM6150) += \ + sm6150-rumi-overlay.dtbo \ + sm6150-qrd-overlay.dtbo \ + sm6150-idp-overlay.dtbo \ + sm6150p-qrd-overlay.dtbo \ + sm6150p-idp-overlay.dtbo \ + sm6150-external-codec-idp-overlay.dtbo \ + sm6150-usbc-idp-overlay.dtbo \ + sm6150-usbc-minidp-idp-overlay.dtbo \ + sm6150-cmd-mode-display-idp-overlay.dtbo \ + sa6155-adp-star-overlay.dtbo \ + sa6155p-adp-star-overlay.dtbo \ + sa6155-adp-air-overlay.dtbo \ + sa6155p-adp-air-overlay.dtbo \ + sa6155p-v2-adp-star-overlay.dtbo \ + sa6155p-v2-adp-air-overlay.dtbo \ + qcs610-iot-overlay.dtbo \ + qcs410-iot-overlay.dtbo + +sm6150-rumi-overlay.dtbo-base := sm6150.dtb +sm6150-qrd-overlay.dtbo-base := sm6150.dtb +sm6150-idp-overlay.dtbo-base := sm6150.dtb +sm6150p-qrd-overlay.dtbo-base := sm6150p.dtb +sm6150p-idp-overlay.dtbo-base := sm6150p.dtb +sm6150-external-codec-idp-overlay.dtbo-base := sm6150.dtb +sm6150-usbc-idp-overlay.dtbo-base := sm6150.dtb +sm6150-usbc-minidp-idp-overlay.dtbo-base := sm6150.dtb +sm6150-cmd-mode-display-idp-overlay.dtbo-base := sm6150.dtb +sa6155-adp-star-overlay.dtbo-base := sa6155.dtb +sa6155p-adp-star-overlay.dtbo-base := sa6155p.dtb +sa6155p-v2-adp-star-overlay.dtbo-base := sa6155p.dtb +sa6155-adp-air-overlay.dtbo-base := sa6155.dtb +sa6155p-adp-air-overlay.dtbo-base := sa6155p.dtb +sa6155p-v2-adp-air-overlay.dtbo-base := sa6155p.dtb +qcs610-iot-overlay.dtbo-base := sm6150.dtb +qcs410-iot-overlay.dtbo-base := sm6150.dtb +else +dtb-$(CONFIG_ARCH_SM6150) += sm6150-rumi.dtb \ + sm6150-qrd.dtb \ + sm6150-idp.dtb \ + sm6150p-qrd.dtb \ + sm6150p-idp.dtb \ + sm6150-external-codec-idp.dtb \ + sm6150-usbc-idp.dtb \ + sm6150-usbc-minidp-idp.dtb \ + sm6150-cmd-mode-display-idp.dtb \ + sa6155-adp-star.dtb \ + sa6155p-adp-star.dtb \ + sa6155-adp-air.dtb \ + sa6155p-adp-air.dtb \ + sa6155p-v2-adp-star.dtb \ + sa6155p-v2-adp-air.dtb \ + qcs610-iot.dtb \ + qcs410-iot.dtb + +endif + +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) + dtbo-$(CONFIG_ARCH_SDMMAGPIE) += \ + sdmmagpie-idp-overlay.dtbo \ + sdmmagpie-atp-overlay.dtbo \ + sdmmagpie-rumi-overlay.dtbo \ + sdmmagpie-qrd-overlay.dtbo \ + sdmmagpiep-idp-overlay.dtbo \ + sdmmagpiep-atp-overlay.dtbo \ + sdmmagpiep-qrd-overlay.dtbo \ + sdmmagpie-external-codec-idp-overlay.dtbo \ + sdmmagpie-usbc-idp-overlay.dtbo \ + sdmmagpie-dual-display-idp-overlay.dtbo + +sdmmagpie-idp-overlay.dtbo-base := sdmmagpie.dtb +sdmmagpie-atp-overlay.dtbo-base := sdmmagpie.dtb +sdmmagpie-rumi-overlay.dtbo-base := sdmmagpie.dtb +sdmmagpie-qrd-overlay.dtbo-base := sdmmagpie.dtb +sdmmagpiep-idp-overlay.dtbo-base := sdmmagpiep.dtb +sdmmagpiep-atp-overlay.dtbo-base := sdmmagpiep.dtb +sdmmagpiep-qrd-overlay.dtbo-base := sdmmagpiep.dtb +sdmmagpie-external-codec-idp-overlay.dtbo-base := sdmmagpie.dtb +sdmmagpie-usbc-idp-overlay.dtbo-base := sdmmagpie.dtb +sdmmagpie-dual-display-idp-overlay.dtbo-base := sdmmagpie.dtb +else +dtb-$(CONFIG_ARCH_SDMMAGPIE) += sdmmagpie-rumi.dtb \ + sdmmagpie-idp.dtb \ + sdmmagpie-atp.dtb \ + sdmmagpie-qrd.dtb \ + sdmmagpiep-idp.dtb \ + sdmmagpiep-atp.dtb \ + sdmmagpiep-qrd.dtb \ + sdmmagpie-external-codec-idp.dtb \ + sdmmagpie-usbc-idp.dtb \ + sdmmagpie-dual-display-idp.dtb +endif + +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) + dtbo-$(CONFIG_ARCH_TRINKET) += \ + trinket-rumi-overlay.dtbo \ + trinket-idp-overlay.dtbo \ + trinket-qrd-overlay.dtbo \ + trinket-external-codec-idp-overlay.dtbo \ + trinket-usbc-external-codec-idp-overlay.dtbo \ + trinket-usbc-idp-overlay.dtbo \ + trinket-dp-idp-overlay.dtbo + +trinket-rumi-overlay.dtbo-base := trinket.dtb +trinket-idp-overlay.dtbo-base := trinket.dtb +trinket-qrd-overlay.dtbo-base := trinket.dtb +trinket-external-codec-idp-overlay.dtbo-base := trinket.dtb +trinket-usbc-external-codec-idp-overlay.dtbo-base := trinket.dtb +trinket-usbc-idp-overlay.dtbo-base := trinket.dtb +trinket-dp-idp-overlay.dtbo-base := trinket.dtb +else +dtb-$(CONFIG_ARCH_TRINKET) += trinket-rumi.dtb \ + trinket-idp.dtb \ + trinket-qrd.dtb \ + trinket-external-codec-idp.dtb \ + trinket-usbc-external-codec-idp.dtb \ + trinket-usbc-idp.dtb \ + trinket-dp-idp.dtb +endif + +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) + dtbo-$(CONFIG_ARCH_ATOLL) += \ + atoll-idp-overlay.dtbo\ + atoll-qrd-overlay.dtbo\ + atoll-rumi-overlay.dtbo + +atoll-idp-overlay.dtbo-base := atoll.dtb +atoll-qrd-overlay.dtbo-base := atoll.dtb +atoll-rumi-overlay.dtbo-base := atoll.dtb +else +dtb-$(CONFIG_ARCH_ATOLL) += atoll-idp.dtb\ + atoll-qrd.dtb\ + atoll-rumi.dtb +endif + +dtb-$(CONFIG_ARCH_SDXPRAIRIE) += sdxprairie-rumi.dtb \ + sdxprairie-cdp.dtb \ + sdxprairie-dsda-cdp.dtb \ + sdxprairie-mtp.dtb \ + sdxprairie-pcie-ep-mtp.dtb \ + sdxprairie-mtp-cpe.dtb \ + sdxprairie-cdp-cpe.dtb \ + sdxprairie-cdp-256.dtb \ + sdxprairie-mtp-256.dtb \ + sdxprairie-mtp-aqc.dtb \ + sdxprairie-dsda-mtp.dtb \ + sdxprairie-v2-cdp.dtb \ + sdxprairie-v2-mtp.dtb \ + sa515m-ccard.dtb \ + sa515m-ccard-pcie-ep.dtb \ + sa515m-ccard-usb-ep.dtb + +ifeq ($(CONFIG_ARM64),y) +always := $(dtb-y) +subdir-y := $(dts-dirs) +else +targets += dtbs +targets += $(addprefix ../, $(dtb-y)) + +$(obj)/../%.dtb: $(src)/%.dts FORCE + $(call if_changed_dep,dtc) + +dtbs: $(addprefix $(obj)/../,$(dtb-y)) +endif +clean-files := *.dtb *.dtbo diff --git a/arch/arm/boot/dts/qcom/OP-fg-batterydata-3700mah.dtsi b/arch/arm/boot/dts/qcom/OP-fg-batterydata-3700mah.dtsi new file mode 100644 index 000000000000..131fb2dc9e0d --- /dev/null +++ b/arch/arm/boot/dts/qcom/OP-fg-batterydata-3700mah.dtsi @@ -0,0 +1,144 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,OP_3700mAh { + qcom,max-voltage-uv = <4370000>; + qcom,fastchg-current-ma = <3000>; + qcom,jeita-fcc-ranges = <0 100 2500000 + 110 400 5400000 + 410 450 2500000>; + qcom,jeita-fv-ranges = <0 100 4250000 + 110 400 4350000 + 410 450 4250000>; + qcom,step-chg-ranges = <3600000 3800000 5400000 + 3801000 4300000 3600000 + 4301000 4350000 2500000>; + qcom,ocv-based-step-chg; + qcom,batt-id-kohm = <200>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,fg-cc-cv-threshold-mv = <4340>; + qcom,battery-type = "OP_3700mAh"; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0xdf 0x02 0x77 0x1a>; + qcom,rslow-low-coeffs = <0x51 0x04 0xd0 0x13>; + qcom,checksum = <0x1538>; + qcom,gui-version = "PM855GUI - 1.0.0.10"; + qcom,fg-profile-data = [ + 09 00 C7 EA + C4 DC 8E E2 + 3A DD 00 00 + 15 BC A5 8A + 02 80 D1 92 + AB 9D 47 80 + 10 00 DF 02 + 77 1A 85 EC + E1 FD CE 07 + 32 00 75 EB + AA ED F3 CD + 0C 0A 7A E4 + ED C5 40 1B + D0 02 1F CA + FF 00 52 00 + 4D 00 4A 00 + 3C 00 35 00 + 38 00 39 00 + 48 00 43 00 + 3F 00 FF 00 + 38 00 40 00 + 46 00 50 00 + 45 00 5C 00 + 7E 64 60 00 + 50 08 50 10 + FF 00 6A 00 + 5F 00 63 00 + 6E 00 60 00 + 7D 20 96 40 + 75 50 6B 13 + 63 00 D8 00 + 14 22 7E 0D + 21 02 AA 04 + ED 1C D4 09 + 64 0C D3 23 + A4 18 D3 42 + B5 55 91 02 + 90 12 2A 1F + 02 06 1F 0A + A3 06 AE 1C + 8D 02 96 04 + D2 03 D1 17 + 51 23 3F 45 + 28 53 69 14 + 93 20 8E EC + 18 CB C8 C5 + DB 1C 7B C9 + 7C 05 E6 C2 + B9 17 2C 93 + 87 85 A2 92 + 91 A8 09 80 + 92 F2 1A 0D + F4 FC 5E EB + 00 F8 FB ED + 15 E2 F6 0F + 75 02 72 05 + 49 01 10 00 + FA E5 E2 03 + 8D 05 85 02 + CE 07 32 00 + 23 03 46 02 + 9C 04 03 02 + 48 07 0A 00 + BA 03 97 02 + 65 05 50 00 + 3A 00 41 00 + 43 64 45 00 + 45 10 45 18 + 46 08 44 00 + 47 00 3A 08 + 4B 08 37 00 + 47 20 4E 40 + 54 58 60 10 + 57 00 5F 00 + 57 08 55 00 + 4B 00 50 00 + 3E 08 52 08 + 52 00 5C 20 + 6F 40 7D 58 + 67 10 63 00 + 69 08 4F 10 + D8 00 8C 2A + DB 04 28 02 + AD 04 0B 1D + 50 22 A7 45 + 0D 52 A2 18 + 74 03 AD 04 + 35 02 AE 13 + 3F 0A 5A 20 + DD 04 F1 02 + D8 05 C7 1C + DD 02 3D 04 + EB 03 97 18 + 52 03 D5 04 + 19 02 72 00 + 14 22 7E 05 + 21 02 AA 04 + ED 1C D4 01 + 64 04 D3 03 + A4 18 D3 02 + B5 05 91 02 + 90 00 7C 01 + C0 00 FA 00 + 04 0E 00 00 + ]; +}; diff --git a/arch/arm/boot/dts/qcom/OP-fg-batterydata-3800mah.dtsi b/arch/arm/boot/dts/qcom/OP-fg-batterydata-3800mah.dtsi new file mode 100644 index 000000000000..f24c758591f2 --- /dev/null +++ b/arch/arm/boot/dts/qcom/OP-fg-batterydata-3800mah.dtsi @@ -0,0 +1,144 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,OP_3800mAh { + qcom,max-voltage-uv = <4370000>; + qcom,fastchg-current-ma = <3000>; + qcom,jeita-fcc-ranges = <0 100 2500000 + 110 400 5400000 + 410 450 2500000>; + qcom,jeita-fv-ranges = <0 100 4250000 + 110 400 4350000 + 410 450 4250000>; + qcom,step-chg-ranges = <3600000 3800000 5400000 + 3801000 4300000 3600000 + 4301000 4350000 2500000>; + qcom,ocv-based-step-chg; + qcom,batt-id-kohm = <200>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,fg-cc-cv-threshold-mv = <4340>; + qcom,battery-type = "OP_3800mAh"; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0xdf 0x02 0x77 0x1a>; + qcom,rslow-low-coeffs = <0x51 0x04 0xd0 0x13>; + qcom,checksum = <0x1538>; + qcom,gui-version = "PM855GUI - 1.0.0.10"; + qcom,fg-profile-data = [ + 09 00 C7 EA + C4 DC 8E E2 + 3A DD 00 00 + 15 BC A5 8A + 02 80 D1 92 + AB 9D 47 80 + 10 00 DF 02 + 77 1A 85 EC + E1 FD CE 07 + 32 00 75 EB + AA ED F3 CD + 0C 0A 7A E4 + ED C5 40 1B + D0 02 1F CA + FF 00 52 00 + 4D 00 4A 00 + 3C 00 35 00 + 38 00 39 00 + 48 00 43 00 + 3F 00 FF 00 + 38 00 40 00 + 46 00 50 00 + 45 00 5C 00 + 7E 64 60 00 + 50 08 50 10 + FF 00 6A 00 + 5F 00 63 00 + 6E 00 60 00 + 7D 20 96 40 + 75 50 6B 13 + 63 00 D8 00 + 14 22 7E 0D + 21 02 AA 04 + ED 1C D4 09 + 64 0C D3 23 + A4 18 D3 42 + B5 55 91 02 + 90 12 2A 1F + 02 06 1F 0A + A3 06 AE 1C + 8D 02 96 04 + D2 03 D1 17 + 51 23 3F 45 + 28 53 69 14 + 93 20 8E EC + 18 CB C8 C5 + DB 1C 7B C9 + 7C 05 E6 C2 + B9 17 2C 93 + 87 85 A2 92 + 91 A8 09 80 + 92 F2 1A 0D + F4 FC 5E EB + 00 F8 FB ED + 15 E2 F6 0F + 75 02 72 05 + 49 01 10 00 + FA E5 E2 03 + 8D 05 85 02 + CE 07 32 00 + 23 03 46 02 + 9C 04 03 02 + 48 07 0A 00 + BA 03 97 02 + 65 05 50 00 + 3A 00 41 00 + 43 64 45 00 + 45 10 45 18 + 46 08 44 00 + 47 00 3A 08 + 4B 08 37 00 + 47 20 4E 40 + 54 58 60 10 + 57 00 5F 00 + 57 08 55 00 + 4B 00 50 00 + 3E 08 52 08 + 52 00 5C 20 + 6F 40 7D 58 + 67 10 63 00 + 69 08 4F 10 + D8 00 8C 2A + DB 04 28 02 + AD 04 0B 1D + 50 22 A7 45 + 0D 52 A2 18 + 74 03 AD 04 + 35 02 AE 13 + 3F 0A 5A 20 + DD 04 F1 02 + D8 05 C7 1C + DD 02 3D 04 + EB 03 97 18 + 52 03 D5 04 + 19 02 72 00 + 14 22 7E 05 + 21 02 AA 04 + ED 1C D4 01 + 64 04 D3 03 + A4 18 D3 02 + B5 05 91 02 + 90 00 7C 01 + C0 00 FA 00 + 04 0E 00 00 + ]; +}; diff --git a/arch/arm/boot/dts/qcom/OP-fg-batterydata-4000mah.dtsi b/arch/arm/boot/dts/qcom/OP-fg-batterydata-4000mah.dtsi new file mode 100644 index 000000000000..3f0116c033ba --- /dev/null +++ b/arch/arm/boot/dts/qcom/OP-fg-batterydata-4000mah.dtsi @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,OP_4000mAh { + qcom,max-voltage-uv = <4370000>; + qcom,fastchg-current-ma = <3000>; + qcom,jeita-fcc-ranges = <0 100 2500000 + 110 400 5400000 + 410 450 2500000>; + qcom,jeita-fv-ranges = <0 100 4250000 + 110 400 4350000 + 410 450 4250000>; + qcom,step-chg-ranges = <3600000 3800000 5400000 + 3801000 4300000 3600000 + 4301000 4350000 2500000>; + qcom,ocv-based-step-chg; + qcom,batt-id-kohm = <200>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,fg-cc-cv-threshold-mv = <4340>; + qcom,battery-type = "OP_4000mAh "; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0xdf 0x02 0x77 0x1a>; + qcom,rslow-low-coeffs = <0x51 0x04 0xd0 0x13>; + qcom,checksum = <0x1538>; + qcom,gui-version = "PM855GUI - 1.0.0.10"; + qcom,fg-profile-data = [ + 09 00 C7 EA + C4 DC 8E E2 + 3A DD 00 00 + 15 BC A5 8A + 02 80 D1 92 + AB 9D 47 80 + 10 00 DF 02 + 77 1A 85 EC + E1 FD CE 07 + 32 00 75 EB + AA ED F3 CD + 0C 0A 7A E4 + ED C5 40 1B + D0 02 1F CA + FF 00 52 00 + 4D 00 4A 00 + 3C 00 35 00 + 38 00 39 00 + 48 00 43 00 + 3F 00 FF 00 + 38 00 40 00 + 46 00 50 00 + 45 00 5C 00 + 7E 64 60 00 + 50 08 50 10 + FF 00 6A 00 + 5F 00 63 00 + 6E 00 60 00 + 7D 20 96 40 + 75 50 6B 13 + 63 00 D8 00 + 14 22 7E 0D + 21 02 AA 04 + ED 1C D4 09 + 64 0C D3 23 + A4 18 D3 42 + B5 55 91 02 + 90 12 2A 1F + 02 06 1F 0A + A3 06 AE 1C + 8D 02 96 04 + D2 03 D1 17 + 51 23 3F 45 + 28 53 69 14 + 93 20 8E EC + 18 CB C8 C5 + DB 1C 7B C9 + 7C 05 E6 C2 + B9 17 2C 93 + 87 85 A2 92 + 91 A8 09 80 + 92 F2 1A 0D + F4 FC 5E EB + 00 F8 FB ED + 15 E2 F6 0F + 75 02 72 05 + 49 01 10 00 + FA E5 E2 03 + 8D 05 85 02 + CE 07 32 00 + 23 03 46 02 + 9C 04 03 02 + 48 07 0A 00 + BA 03 97 02 + 65 05 50 00 + 3A 00 41 00 + 43 64 45 00 + 45 10 45 18 + 46 08 44 00 + 47 00 3A 08 + 4B 08 37 00 + 47 20 4E 40 + 54 58 60 10 + 57 00 5F 00 + 57 08 55 00 + 4B 00 50 00 + 3E 08 52 08 + 52 00 5C 20 + 6F 40 7D 58 + 67 10 63 00 + 69 08 4F 10 + D8 00 8C 2A + DB 04 28 02 + AD 04 0B 1D + 50 22 A7 45 + 0D 52 A2 18 + 74 03 AD 04 + 35 02 AE 13 + 3F 0A 5A 20 + DD 04 F1 02 + D8 05 C7 1C + DD 02 3D 04 + EB 03 97 18 + 52 03 D5 04 + 19 02 72 00 + 14 22 7E 05 + 21 02 AA 04 + ED 1C D4 01 + 64 04 D3 03 + A4 18 D3 02 + B5 05 91 02 + 90 00 7C 01 + C0 00 FA 00 + 04 0E 00 00 + ]; +}; diff --git a/arch/arm/boot/dts/qcom/OP-fg-batterydata-4085mah.dtsi b/arch/arm/boot/dts/qcom/OP-fg-batterydata-4085mah.dtsi new file mode 100644 index 000000000000..c6c284df1b9b --- /dev/null +++ b/arch/arm/boot/dts/qcom/OP-fg-batterydata-4085mah.dtsi @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,OP_4085mAh { + qcom,max-voltage-uv = <4370000>; + qcom,fastchg-current-ma = <3000>; + qcom,jeita-fcc-ranges = <0 100 2500000 + 110 400 5400000 + 410 450 2500000>; + qcom,jeita-fv-ranges = <0 100 4250000 + 110 400 4350000 + 410 450 4250000>; + qcom,step-chg-ranges = <3600000 3800000 5400000 + 3801000 4300000 3600000 + 4301000 4350000 2500000>; + qcom,ocv-based-step-chg; + qcom,batt-id-kohm = <200>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,fg-cc-cv-threshold-mv = <4340>; + qcom,battery-type = "OP_4085mAh "; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0xdf 0x02 0x77 0x1a>; + qcom,rslow-low-coeffs = <0x51 0x04 0xd0 0x13>; + qcom,checksum = <0x1538>; + qcom,gui-version = "PM855GUI - 1.0.0.10"; + qcom,fg-profile-data = [ + 09 00 C7 EA + C4 DC 8E E2 + 3A DD 00 00 + 15 BC A5 8A + 02 80 D1 92 + AB 9D 47 80 + 10 00 DF 02 + 77 1A 85 EC + E1 FD CE 07 + 32 00 75 EB + AA ED F3 CD + 0C 0A 7A E4 + ED C5 40 1B + D0 02 1F CA + FF 00 52 00 + 4D 00 4A 00 + 3C 00 35 00 + 38 00 39 00 + 48 00 43 00 + 3F 00 FF 00 + 38 00 40 00 + 46 00 50 00 + 45 00 5C 00 + 7E 64 60 00 + 50 08 50 10 + FF 00 6A 00 + 5F 00 63 00 + 6E 00 60 00 + 7D 20 96 40 + 75 50 6B 13 + 63 00 D8 00 + 14 22 7E 0D + 21 02 AA 04 + ED 1C D4 09 + 64 0C D3 23 + A4 18 D3 42 + B5 55 91 02 + 90 12 2A 1F + 02 06 1F 0A + A3 06 AE 1C + 8D 02 96 04 + D2 03 D1 17 + 51 23 3F 45 + 28 53 69 14 + 93 20 8E EC + 18 CB C8 C5 + DB 1C 7B C9 + 7C 05 E6 C2 + B9 17 2C 93 + 87 85 A2 92 + 91 A8 09 80 + 92 F2 1A 0D + F4 FC 5E EB + 00 F8 FB ED + 15 E2 F6 0F + 75 02 72 05 + 49 01 10 00 + FA E5 E2 03 + 8D 05 85 02 + CE 07 32 00 + 23 03 46 02 + 9C 04 03 02 + 48 07 0A 00 + BA 03 97 02 + 65 05 50 00 + 3A 00 41 00 + 43 64 45 00 + 45 10 45 18 + 46 08 44 00 + 47 00 3A 08 + 4B 08 37 00 + 47 20 4E 40 + 54 58 60 10 + 57 00 5F 00 + 57 08 55 00 + 4B 00 50 00 + 3E 08 52 08 + 52 00 5C 20 + 6F 40 7D 58 + 67 10 63 00 + 69 08 4F 10 + D8 00 8C 2A + DB 04 28 02 + AD 04 0B 1D + 50 22 A7 45 + 0D 52 A2 18 + 74 03 AD 04 + 35 02 AE 13 + 3F 0A 5A 20 + DD 04 F1 02 + D8 05 C7 1C + DD 02 3D 04 + EB 03 97 18 + 52 03 D5 04 + 19 02 72 00 + 14 22 7E 05 + 21 02 AA 04 + ED 1C D4 01 + 64 04 D3 03 + A4 18 D3 02 + B5 05 91 02 + 90 00 7C 01 + C0 00 FA 00 + 04 0E 00 00 + ]; +}; diff --git a/arch/arm/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi b/arch/arm/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi new file mode 100644 index 000000000000..ec2f0de67993 --- /dev/null +++ b/arch/arm/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include + +&pm8916_gpios { + + usb_hub_reset_pm: usb_hub_reset_pm { + pinconf { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + }; + }; + + usb_sw_sel_pm: usb_sw_sel_pm { + pinconf { + pins = "gpio4"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = ; + input-disable; + output-high; + }; + }; + + pm8916_gpios_leds: pm8916_gpios_leds { + pinconf { + pins = "gpio1", "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + }; + }; +}; + +&pm8916_mpps { + + pinctrl-names = "default"; + pinctrl-0 = <&ls_exp_gpio_f>; + + ls_exp_gpio_f: pm8916_mpp4 { + pinconf { + pins = "mpp4"; + function = "digital"; + output-low; + power-source = ; // 1.8V + }; + }; + + pm8916_mpps_leds: pm8916_mpps_leds { + pinconf { + pins = "mpp2", "mpp3"; + function = "digital"; + output-low; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi b/arch/arm/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi new file mode 100644 index 000000000000..21d0822f1ca6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +&msmgpio { + + msmgpio_leds: msmgpio_leds { + pinconf { + pins = "gpio21", "gpio120"; + function = "gpio"; + output-low; + }; + }; + + usb_id_default: usb-id-default { + pinmux { + function = "gpio"; + pins = "gpio121"; + }; + + pinconf { + pins = "gpio121"; + drive-strength = <8>; + input-enable; + bias-pull-up; + }; + }; + + adv7533_int_active: adv533_int_active { + pinmux { + function = "gpio"; + pins = "gpio31"; + }; + pinconf { + pins = "gpio31"; + drive-strength = <16>; + bias-disable; + }; + }; + + adv7533_int_suspend: adv7533_int_suspend { + pinmux { + function = "gpio"; + pins = "gpio31"; + }; + pinconf { + pins = "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; + + adv7533_switch_active: adv7533_switch_active { + pinmux { + function = "gpio"; + pins = "gpio32"; + }; + pinconf { + pins = "gpio32"; + drive-strength = <16>; + bias-disable; + }; + }; + + adv7533_switch_suspend: adv7533_switch_suspend { + pinmux { + function = "gpio"; + pins = "gpio32"; + }; + pinconf { + pins = "gpio32"; + drive-strength = <2>; + bias-disable; + }; + }; + + msm_key_volp_n_default: msm_key_volp_n_default { + pinmux { + function = "gpio"; + pins = "gpio107"; + }; + pinconf { + pins = "gpio107"; + drive-strength = <8>; + input-enable; + bias-pull-up; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/apq8016-sbc.dts b/arch/arm/boot/dts/qcom/apq8016-sbc.dts new file mode 100644 index 000000000000..825f489a2af7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/apq8016-sbc.dts @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "apq8016-sbc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. APQ 8016 SBC"; + compatible = "qcom,apq8016-sbc", "qcom,apq8016", "qcom,sbc"; +}; diff --git a/arch/arm/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm/boot/dts/qcom/apq8016-sbc.dtsi new file mode 100644 index 000000000000..b6b44fdf7fac --- /dev/null +++ b/arch/arm/boot/dts/qcom/apq8016-sbc.dtsi @@ -0,0 +1,502 @@ +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msm8916.dtsi" +#include "pm8916.dtsi" +#include "apq8016-sbc-soc-pins.dtsi" +#include "apq8016-sbc-pmic-pins.dtsi" +#include +#include +#include + +/ { + aliases { + serial0 = &blsp1_uart2; + serial1 = &blsp1_uart1; + usid0 = &pm8916_0; + i2c0 = &blsp_i2c2; + i2c1 = &blsp_i2c6; + i2c3 = &blsp_i2c4; + spi0 = &blsp_spi5; + spi1 = &blsp_spi3; + }; + + chosen { + stdout-path = "serial0"; + }; + + reserved-memory { + ramoops@bff00000{ + compatible = "ramoops"; + reg = <0x0 0xbff00000 0x0 0x100000>; + + record-size = <0x20000>; + console-size = <0x20000>; + ftrace-size = <0x20000>; + }; + }; + + soc { + dma@7884000 { + status = "okay"; + }; + + serial@78af000 { + label = "LS-UART0"; + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart1_default>; + pinctrl-1 = <&blsp1_uart1_sleep>; + }; + + serial@78b0000 { + label = "LS-UART1"; + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; + }; + + i2c@78b6000 { + /* On Low speed expansion */ + label = "LS-I2C0"; + status = "okay"; + }; + + i2c@78b8000 { + /* On High speed expansion */ + label = "HS-I2C2"; + status = "okay"; + + adv_bridge: bridge@39 { + status = "okay"; + + compatible = "adi,adv7533"; + reg = <0x39>; + + interrupt-parent = <&msmgpio>; + interrupts = <31 2>; + + adi,dsi-lanes = <4>; + clocks = <&rpmcc RPM_SMD_BB_CLK2>; + clock-names = "cec"; + + pd-gpios = <&msmgpio 32 0>; + + avdd-supply = <&pm8916_l6>; + v1p2-supply = <&pm8916_l6>; + v3p3-supply = <&pm8916_l17>; + + pinctrl-names = "default","sleep"; + pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>; + pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>; + #sound-dai-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7533_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7533_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + }; + + i2c@78ba000 { + /* On Low speed expansion */ + label = "LS-I2C1"; + status = "okay"; + }; + + spi@78b7000 { + /* On High speed expansion */ + label = "HS-SPI1"; + status = "okay"; + }; + + spi@78b9000 { + /* On Low speed expansion */ + label = "LS-SPI0"; + status = "okay"; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&msmgpio_leds>, + <&pm8916_gpios_leds>, + <&pm8916_mpps_leds>; + + compatible = "gpio-leds"; + + led@1 { + label = "apq8016-sbc:green:user1"; + gpios = <&msmgpio 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led@2 { + label = "apq8016-sbc:green:user2"; + gpios = <&msmgpio 120 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led@3 { + label = "apq8016-sbc:green:user3"; + gpios = <&pm8916_gpios 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led@4 { + label = "apq8016-sbc:green:user4"; + gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + }; + + led@5 { + label = "apq8016-sbc:yellow:wlan"; + gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + led@6 { + label = "apq8016-sbc:blue:bt"; + gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + }; + + sdhci@07824000 { + vmmc-supply = <&pm8916_l8>; + vqmmc-supply = <&pm8916_l5>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; + status = "okay"; + }; + + sdhci@07864000 { + vmmc-supply = <&pm8916_l11>; + vqmmc-supply = <&pm8916_l12>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&msmgpio 38 0x1>; + status = "okay"; + }; + + usb@78d9000 { + extcon = <&usb_id>; + status = "okay"; + adp-disable; + hnp-disable; + srp-disable; + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&usb_sw_sel_pm>; + ulpi { + phy { + v1p8-supply = <&pm8916_l7>; + v3p3-supply = <&pm8916_l13>; + extcon = <&usb_id>; + }; + }; + }; + + lpass@07708000 { + status = "okay"; + }; + + mdss@1a00000 { + status = "okay"; + + mdp@1a01000 { + status = "okay"; + }; + + dsi@1a98000 { + status = "okay"; + + vdda-supply = <&pm8916_l2>; + vddio-supply = <&pm8916_l6>; + + ports { + port@1 { + endpoint { + remote-endpoint = <&adv7533_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; + }; + + dsi-phy@1a98300 { + status = "okay"; + + vddio-supply = <&pm8916_l6>; + }; + }; + + lpass_codec: codec{ + status = "okay"; + }; + + /* + Internal Codec + playback - Primary MI2S + capture - Ter MI2S + + External Primary: + playback - secondary MI2S + capture - Quat MI2S + + External Secondary: + playback - Quat MI2S + capture - Quat MI2S + + */ + + sound: sound { + compatible = "qcom,apq8016-sbc-sndcard"; + reg = <0x07702000 0x4>, <0x07702004 0x4>; + reg-names = "mic-iomux", "spkr-iomux"; + + status = "okay"; + pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>; + pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>; + pinctrl-names = "default", "sleep"; + qcom,model = "DB410c"; + qcom,audio-routing = + "AMIC2", "MIC BIAS Internal2", + "AMIC3", "MIC BIAS External1"; + external-dai-link@0 { + link-name = "ADV7533"; + cpu { /* QUAT */ + sound-dai = <&lpass MI2S_QUATERNARY>; + }; + codec { + sound-dai = <&adv_bridge 0>; + }; + }; + + internal-codec-playback-dai-link@0 { /* I2S - Internal codec */ + link-name = "WCD"; + cpu { /* PRIMARY */ + sound-dai = <&lpass MI2S_PRIMARY>; + }; + codec { + sound-dai = <&lpass_codec 0>, <&wcd_codec 0>; + }; + }; + + internal-codec-capture-dai-link@0 { /* I2S - Internal codec */ + link-name = "WCD-Capture"; + cpu { /* PRIMARY */ + sound-dai = <&lpass MI2S_TERTIARY>; + }; + codec { + sound-dai = <&lpass_codec 1>, <&wcd_codec 1>; + }; + }; + }; + + wcnss@a21b000 { + status = "okay"; + }; + }; + + usb2513 { + compatible = "smsc,usb3503"; + reset-gpios = <&pm8916_gpios 3 GPIO_ACTIVE_LOW>; + initial-mode = <1>; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + vbus-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_id_default>; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7533_out>; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&msm_key_volp_n_default>; + + button@0 { + label = "Volume Up"; + linux,code = ; + gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&wcd_codec { + status = "okay"; + clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; + clock-names = "mclk"; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l5-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + s1 { + regulator-min-microvolt = <375000>; + regulator-max-microvolt = <1562000>; + }; + + s3 { + regulator-min-microvolt = <375000>; + regulator-max-microvolt = <1562000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + }; + + l1 { + regulator-min-microvolt = <375000>; + regulator-max-microvolt = <1525000>; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l3 { + regulator-min-microvolt = <375000>; + regulator-max-microvolt = <1525000>; + }; + + l4 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3337000>; + }; + + l5 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3337000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l7 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3337000>; + }; + + l8 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3337000>; + }; + + l9 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3337000>; + }; + + l10 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3337000>; + }; + + l11 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3337000>; + }; + + l12 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3337000>; + }; + + l13 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3337000>; + }; + + l14 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3337000>; + }; + + /** + * 1.8v required on LS expansion + * for mezzanine boards + */ + l15 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3337000>; + regulator-always-on; + }; + + l16 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3337000>; + }; + + l17 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l18 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <3337000>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/apq8096-db820c-pins.dtsi b/arch/arm/boot/dts/qcom/apq8096-db820c-pins.dtsi new file mode 100644 index 000000000000..24552f19b3fa --- /dev/null +++ b/arch/arm/boot/dts/qcom/apq8096-db820c-pins.dtsi @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&msmgpio { + sdc2_cd_on: sdc2_cd_on { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + bias-pull-up; /* pull up */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_cd_off: sdc2_cd_off { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi b/arch/arm/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi new file mode 100644 index 000000000000..59b29ddfb6e9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +&pm8994_gpios { + + pinctrl-names = "default"; + pinctrl-0 = <&ls_exp_gpio_f>; + + ls_exp_gpio_f: pm8994_gpio5 { + pinconf { + pins = "gpio5"; + output-low; + power-source = <2>; // PM8994_GPIO_S4, 1.8V + }; + }; + + volume_up_gpio: pm8996_gpio2 { + pinconf { + pins = "gpio2"; + function = "normal"; + input-enable; + drive-push-pull; + bias-pull-up; + qcom,drive-strength = ; + power-source = ; // 1.8V + }; + }; + + usb3_vbus_det_gpio: pm8996_gpio22 { + pinconf { + pins = "gpio22"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-down; + qcom,drive-strength = ; + power-source = ; // 1.8V + }; + }; +}; + +&pmi8994_gpios { + usb2_vbus_det_gpio: pmi8996_gpio6 { + pinconf { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-down; + qcom,drive-strength = ; + power-source = ; // 1.8V + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/apq8096-db820c.dts b/arch/arm/boot/dts/qcom/apq8096-db820c.dts new file mode 100644 index 000000000000..230e9c8484ac --- /dev/null +++ b/arch/arm/boot/dts/qcom/apq8096-db820c.dts @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "apq8096-db820c.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. DB820c"; + compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc"; +}; diff --git a/arch/arm/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm/boot/dts/qcom/apq8096-db820c.dtsi new file mode 100644 index 000000000000..789f3e87321e --- /dev/null +++ b/arch/arm/boot/dts/qcom/apq8096-db820c.dtsi @@ -0,0 +1,307 @@ +/* + * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msm8996.dtsi" +#include "pm8994.dtsi" +#include "pmi8994.dtsi" +#include "apq8096-db820c-pins.dtsi" +#include "apq8096-db820c-pmic-pins.dtsi" +#include +#include + +/ { + aliases { + serial0 = &blsp2_uart1; + serial1 = &blsp2_uart2; + i2c0 = &blsp1_i2c2; + i2c1 = &blsp2_i2c1; + i2c2 = &blsp2_i2c0; + spi0 = &blsp1_spi0; + spi1 = &blsp2_spi5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + soc { + serial@75b0000 { + label = "LS-UART1"; + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_uart1_2pins_default>; + pinctrl-1 = <&blsp2_uart1_2pins_sleep>; + }; + + serial@75b1000 { + label = "LS-UART0"; + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_uart2_4pins_default>; + pinctrl-1 = <&blsp2_uart2_4pins_sleep>; + }; + + i2c@07577000 { + /* On Low speed expansion */ + label = "LS-I2C0"; + status = "okay"; + }; + + i2c@075b6000 { + /* On Low speed expansion */ + label = "LS-I2C1"; + status = "okay"; + }; + + spi@07575000 { + /* On Low speed expansion */ + label = "LS-SPI0"; + status = "okay"; + }; + + i2c@075b5000 { + /* On High speed expansion */ + label = "HS-I2C2"; + status = "okay"; + }; + + spi@075ba000{ + /* On High speed expansion */ + label = "HS-SPI1"; + status = "okay"; + }; + + sdhci@74a4900 { + /* External SD card */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + cd-gpios = <&msmgpio 38 0x1>; + status = "okay"; + }; + + phy@34000 { + status = "okay"; + }; + + phy@7410000 { + status = "okay"; + }; + + phy@7411000 { + status = "okay"; + }; + + phy@7412000 { + status = "okay"; + }; + + usb@6a00000 { + status = "okay"; + + dwc3@6a00000 { + extcon = <&usb3_id>; + dr_mode = "otg"; + }; + }; + + usb3_id: usb3-id { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_vbus_det_gpio>; + }; + + usb@7600000 { + status = "okay"; + + dwc3@7600000 { + extcon = <&usb2_id>; + dr_mode = "otg"; + maximum-speed = "high-speed"; + }; + }; + + usb2_id: usb2-id { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb2_vbus_det_gpio>; + }; + }; + + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&volume_up_gpio>; + + button@0 { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; + }; + }; + + rpm-glink { + rpm_requests { + pm8994-regulators { + vdd_l1-supply = <&pm8994_s3>; + vdd_l2_l26_l28-supply = <&pm8994_s3>; + vdd_l3_l11-supply = <&pm8994_s3>; + vdd_l4_l27_l31-supply = <&pm8994_s3>; + vdd_l5_l7-supply = <&pm8994_s5>; + vdd_l14_l15-supply = <&pm8994_s5>; + vdd_l20_l21-supply = <&pm8994_s5>; + vdd_l25-supply = <&pm8994_s3>; + + s3 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + s5 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + }; + s7 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + l2 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + }; + l3 { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + }; + l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + l6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + l11 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + l17 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + }; + l19 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + l22 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + l23 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + l25 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-allow-set-load; + }; + l27 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + l28 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-allow-set-load; + }; + l29 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + l30 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + l32 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/atoll-coresight.dtsi b/arch/arm/boot/dts/qcom/atoll-coresight.dtsi new file mode 100644 index 000000000000..1cd3070a7918 --- /dev/null +++ b/arch/arm/boot/dts/qcom/atoll-coresight.dtsi @@ -0,0 +1,2979 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + csr: csr@6001000 { + compatible = "qcom,coresight-csr"; + reg = <0x6001000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-csr"; + + qcom,usb-bam-support; + qcom,hwctrl-set-support; + qcom,set-byte-cntr-support; + qcom,blk-size = <1>; + }; + + audio_etm0: audio_etm0 { + compatible = "qcom,coresight-remote-etm"; + coresight-name = "coresight-audio-etm0"; + + qcom,inst-id = <5>; + + port { + audio_etm0_out_funnel_swao: endpoint { + remote-endpoint = + <&funnel_swao_in_audio_etm0>; + }; + }; + }; + + tpdm_lpass_lpi: tpdm@6b26000 { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-tpdm-lpass-lpi"; + qcom,dummy-source; + + port { + tpdm_lpss_lpi_out_funnel_swao: endpoint { + remote-endpoint = <&funnel_swao_in_tpdm_lpass_lpi>; + }; + }; + }; + + tpdm_swao_0: tpdm@6b09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6b09000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_swao_0_out_tpda_swao0: endpoint { + remote-endpoint = + <&tpda_swao0_in_tpdm_swao_0>; + }; + }; + }; + + tpdm_swao_1: tpdm@6b0a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6b0a000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_swao_1_out_tpda_swao1: endpoint { + remote-endpoint = + <&tpda_swao1_in_tpdm_swao_1>; + }; + }; + }; + + tpdm_vsense: tpdm@6834000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6834000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-vsense"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_vsense_out_tpda21: endpoint { + remote-endpoint = + <&tpda21_in_tpdm_vsense>; + }; + }; + }; + + tpdm_dcc: tpdm@6870000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6870000 0x1000>; + reg-names = "tpdm-base"; + + qcom,hw-enable-check; + coresight-name = "coresight-tpdm-dcc"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_dcc_out_tpda22: endpoint { + remote-endpoint = + <&tpda22_in_tpdm_dcc>; + }; + }; + }; + + tpdm_prng: tpdm@684c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x684c000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-prng"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_prng_out_tpda23: endpoint { + remote-endpoint = + <&tpda23_in_tpdm_prng>; + }; + }; + }; + + tpdm_qm: tpdm@69d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x69d0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-qm"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_qm_out_tpda24: endpoint { + remote-endpoint = + <&tpda24_in_tpdm_qm>; + }; + }; + }; + + tpdm_lpass: tpdm@6844000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6844000 0x1000>; + reg-names = "tpdm-base"; + + qcom,msr-fix-req; + coresight-name = "coresight-tpdm-lpass"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_lpass_out_funnel_lpass: endpoint { + remote-endpoint = + <&funnel_lpass_in_tpdm_lpass>; + }; + }; + }; + + tpdm_npu: tpdm@6c47000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6c47000 0x1000>; + reg-names = "tpdm-base"; + status = "disabled"; + + coresight-name = "coresight-tpdm-npu"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_npu_out_funnel_npu: endpoint { + remote-endpoint = + <&funnel_npu_in_tpdm_npu>; + }; + }; + }; + + tpdm_npu_llm: tpdm@6c40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6c40000 0x1000>; + reg-names = "tpdm-base"; + + status = "disabled"; + coresight-name = "coresight-tpdm-npu-llm"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_npu_llm_out_funnel_npu: endpoint { + remote-endpoint = + <&funnel_npu_in_tpdm_npu_llm>; + }; + }; + }; + + tpdm_npu_dpm: tpdm@6c41000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6c41000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-npu-dpm"; + + status = "disabled"; + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_npu_dpm_out_funnel_npu: endpoint { + remote-endpoint = + <&funnel_npu_in_tpdm_npu_dpm>; + }; + }; + }; + + npu_etm0: npu_etm0 { + compatible = "qcom,coresight-remote-etm"; + coresight-name = "coresight-npu-etm0"; + + qcom,inst-id = <2>; + + port { + npu_etm0_out_funnel_npu: endpoint { + remote-endpoint = + <&funnel_npu_in_npu_etm0>; + }; + }; + }; + + tpdm_mdss: tpdm@6c60000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6c60000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-mdss"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_mdss_out_funnel_dlnt: endpoint { + remote-endpoint = + <&funnel_dlnt_in_tpdm_mdss>; + }; + }; + }; + + tpdm_dl_north: tpdm@6ac0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6ac0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dl-north"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_dl_north_out_funnel_dlnt: endpoint { + remote-endpoint = + <&funnel_dlnt_in_tpdm_dl_north>; + }; + }; + }; + + tpdm_nav: tpdm@6842000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6842000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-nav"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_nav_out_tpda_nav0: endpoint { + remote-endpoint = + <&tpda_nav0_in_tpdm_nav>; + }; + }; + }; + + modem_etm0: modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + coresight-name = "coresight-modem-etm0"; + + qcom,inst-id = <11>; + + port { + modem_etm0_out_funnel_dlnt: endpoint { + remote-endpoint = + <&funnel_dlnt_in_modem_etm0>; + }; + }; + }; + + tpdm_modem_0: tpdm@6800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6800000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-modem-0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_modem_0_out_tpda_modem0: endpoint { + remote-endpoint = + <&tpda_modem0_in_tpdm_modem_0>; + }; + }; + }; + + tpdm_modem_1: tpdm@6804000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6804000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-modem-1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_modem_1_out_tpda_modem1: endpoint { + remote-endpoint = + <&tpda_modem1_in_tpdm_modem_1>; + }; + }; + }; + + tpdm_dlct: tpdm@6c28000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6c28000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dlct"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_dlct_out_funnel_dlct0: endpoint { + remote-endpoint = + <&funnel_dlct0_in_tpdm_dlct>; + }; + }; + }; + + tpdm_pimem: tpdm@6850000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6850000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-pimem"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_pimem_out_tpda_dl_center16: endpoint { + remote-endpoint = + <&tpda_dl_center16_in_tpdm_pimem>; + }; + }; + }; + + tpdm_gpu: tpdm@6940000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6940000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-gpu"; + status = "disabled"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_gpu_out_funnel_gpu: endpoint { + remote-endpoint = + <&funnel_gpu_in_tpdm_gpu>; + }; + }; + }; + + tpdm_ddr: tpdm@6f80000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6f80000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr"; + qcom,msr-fix-req; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_ddr_out_funnel_ddr0: endpoint { + remote-endpoint = + <&funnel_ddr0_in_tpdm_ddr>; + }; + }; + }; + + tpdm_turing: tpdm@6980000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6980000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-turing"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_turing_out_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_in_tpdm_turing>; + }; + }; + }; + + tpdm_turing_llm: tpdm@6981000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6981000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-turing-llm"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_turing_llm_out_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_in_tpdm_turing_llm>; + }; + }; + }; + + turing_etm0: turing_etm0 { + compatible = "qcom,coresight-remote-etm"; + coresight-name = "coresight-turing-etm0"; + + qcom,inst-id = <13>; + + port { + turing_etm0_out_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_in_turing_etm0>; + }; + }; + }; + + tpdm_wcss: tpdm@69a4000 { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-tpdm-wcss"; + qcom,dummy-source; + + port { + tpdm_wcss_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_tpdm_wcss>; + }; + }; + }; + + etm0: tpdm@7040000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x7040000 0x1000>; + cpu = <&CPU0>; + + coresight-name = "coresight-etm0"; + + qcom,tupwr-disable; + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + etm0_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_etm0>; + }; + }; + }; + + etm1: tpdm@7140000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x7140000 0x1000>; + cpu = <&CPU1>; + + coresight-name = "coresight-etm1"; + + qcom,tupwr-disable; + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + etm1_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_etm1>; + }; + }; + }; + + etm2: tpdm@7240000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x7240000 0x1000>; + cpu = <&CPU2>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + etm2_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_etm2>; + }; + }; + }; + + etm3: tpdm@7340000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x7340000 0x1000>; + cpu = <&CPU3>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm3"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + etm3_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_etm3>; + }; + }; + }; + + etm4: tpdm@7440000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x7440000 0x1000>; + cpu = <&CPU4>; + + coresight-name = "coresight-etm4"; + + qcom,tupwr-disable; + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + etm4_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_etm4>; + }; + }; + }; + + etm5: tpdm@7540000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x7540000 0x1000>; + cpu = <&CPU5>; + + coresight-name = "coresight-etm5"; + + qcom,tupwr-disable; + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + etm5_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_etm5>; + }; + }; + }; + + etm6: tpdm@7640000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x7640000 0x1000>; + cpu = <&CPU6>; + + coresight-name = "coresight-etm6"; + + qcom,tupwr-disable; + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + etm6_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_etm6>; + }; + }; + }; + + etm7: tpdm@7740000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + reg = <0x7740000 0x1000>; + cpu = <&CPU7>; + + coresight-name = "coresight-etm7"; + + qcom,tupwr-disable; + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + etm7_out_funnel_apss: endpoint { + remote-endpoint = + <&funnel_apss_in_etm7>; + }; + }; + }; + + tpdm_olc: tpdm@7830000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x7830000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-olc"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_olc_out_tpda_olc0: endpoint { + remote-endpoint = + <&tpda_olc0_in_tpdm_olc>; + }; + }; + }; + + tpdm_llm_silver: tpdm@78a0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x78a0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-llm-silver"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_llm_silver_out_tpda_llm_silver0: endpoint { + remote-endpoint = + <&tpda_llm_silver0_in_tpdm_llm_silver>; + }; + }; + }; + + tpdm_llm_gold: tpdm@78b0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x78b0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-llm-gold"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_llm_gold_out_tpda_llm_gold0: endpoint { + remote-endpoint = + <&tpda_llm_gold0_in_tpdm_llm_gold>; + }; + }; + }; + + tpdm_apss: tpdm@7860000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x7860000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-apss"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + port { + tpdm_apss_out_tpda_apss0: endpoint { + remote-endpoint = + <&tpda_apss0_in_tpdm_apss>; + }; + }; + }; + + funnel_lpass: funnel@6846000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + reg = <0x6846000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-lpass"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_lpass_out_funnel_dlct0: endpoint { + remote-endpoint = + <&funnel_dlct0_in_funnel_lpass>; + }; + }; + + port@1 { + reg = <0>; + funnel_lpass_in_tpdm_lpass: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_lpass_out_funnel_lpass>; + }; + }; + + }; + }; + + funnel_npu: funnel@6c44000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + reg = <0x6c44000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-npu"; + + status = "disabled"; + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_npu_out_funnel_dlct0: endpoint { + remote-endpoint = + <&funnel_dlct0_in_funnel_npu>; + }; + }; + + port@1 { + reg = <0>; + funnel_npu_in_tpdm_npu: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_npu_out_funnel_npu>; + }; + }; + + port@2 { + reg = <1>; + funnel_npu_in_tpdm_npu_llm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_npu_llm_out_funnel_npu>; + }; + }; + + port@3 { + reg = <2>; + funnel_npu_in_tpdm_npu_dpm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_npu_dpm_out_funnel_npu>; + }; + }; + + port@4 { + reg = <3>; + funnel_npu_in_npu_etm0: endpoint { + slave-mode; + remote-endpoint = + <&npu_etm0_out_funnel_npu>; + }; + }; + + }; + }; + + tpda_nav: tpda@6843000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6843000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-nav"; + qcom,tpda-atid = <68>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_nav_out_funnel_dlnt: endpoint { + remote-endpoint = + <&funnel_dlnt_in_tpda_nav>; + }; + }; + + port@1 { + reg = <0>; + tpda_nav0_in_tpdm_nav: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_nav_out_tpda_nav0>; + }; + }; + + }; + }; + + tpda_modem0: tpda@6801000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6801000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-modem0"; + qcom,tpda-atid = <67>; + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_modem0_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_tpda_modem0>; + }; + }; + + port@1 { + reg = <0>; + tpda_modem0_in_tpdm_modem_0: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_modem_0_out_tpda_modem0>; + }; + }; + + }; + }; + + tpda_modem1: tpda@6803000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6803000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-modem1"; + qcom,tpda-atid = <98>; + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_modem1_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_tpda_modem1>; + }; + }; + + port@1 { + reg = <0>; + tpda_modem1_in_tpdm_modem_1: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_modem_1_out_tpda_modem1>; + }; + }; + + }; + }; + + funnel_modem: funnel@6802000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + reg = <0x6802000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-modem"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_modem_out_funnel_dlnt: endpoint { + remote-endpoint = + <&funnel_dlnt_in_funnel_modem>; + }; + }; + + port@1 { + reg = <0>; + funnel_modem_in_tpda_modem0: endpoint { + slave-mode; + remote-endpoint = + <&tpda_modem0_out_funnel_modem>; + }; + }; + + port@2 { + reg = <1>; + funnel_modem_in_tpda_modem1: endpoint { + slave-mode; + remote-endpoint = + <&tpda_modem1_out_funnel_modem>; + }; + }; + + }; + }; + + funnel_dlnt: funnel@6ac5000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + reg = <0x6ac5000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dlnt"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_dlnt_out_funnel_dlct0: endpoint { + remote-endpoint = + <&funnel_dlct0_in_funnel_dlnt>; + }; + }; + + port@1 { + reg = <0>; + funnel_dlnt_in_tpdm_mdss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_mdss_out_funnel_dlnt>; + }; + }; + + port@2 { + reg = <1>; + funnel_dlnt_in_tpdm_dl_north: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dl_north_out_funnel_dlnt>; + }; + }; + + port@3 { + reg = <2>; + funnel_dlnt_in_tpda_nav: endpoint { + slave-mode; + remote-endpoint = + <&tpda_nav_out_funnel_dlnt>; + }; + }; + + port@4 { + reg = <5>; + funnel_dlnt_in_modem_etm0: endpoint { + slave-mode; + remote-endpoint = + <&modem_etm0_out_funnel_dlnt>; + }; + }; + + port@5 { + reg = <6>; + funnel_dlnt_in_funnel_modem: endpoint { + slave-mode; + remote-endpoint = + <&funnel_modem_out_funnel_dlnt>; + }; + }; + + }; + }; + + funnel_dlct0: funnel@6c2d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + reg = <0x6c2d000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dlct0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_dlct0_out_tpda2: endpoint { + remote-endpoint = + <&tpda2_in_funnel_dlct0>; + source = <&tpdm_lpass>; + }; + }; + + port@1 { + reg = <0>; + funnel_dlct0_out_tpda11: endpoint { + remote-endpoint = + <&tpda11_in_funnel_dlct0>; + source = <&tpdm_npu>; + }; + }; + + port@2 { + reg = <0>; + funnel_dlct0_out_tpda12: endpoint { + remote-endpoint = + <&tpda12_in_funnel_dlct0>; + source = <&tpdm_npu_llm>; + }; + }; + + port@3 { + reg = <0>; + funnel_dlct0_out_tpda13: endpoint { + remote-endpoint = + <&tpda13_in_funnel_dlct0>; + source = <&tpdm_npu_dpm>; + }; + }; + + port@4 { + reg = <0>; + funnel_dlct0_out_tpda14: endpoint { + remote-endpoint = + <&tpda14_in_funnel_dlct0>; + source = <&tpdm_mdss>; + }; + }; + + port@5 { + reg = <0>; + funnel_dlct0_out_tpda15: endpoint { + remote-endpoint = + <&tpda15_in_funnel_dlct0>; + source = <&tpdm_dl_north>; + }; + }; + + port@6 { + reg = <0>; + funnel_dlct0_out_tpda19: endpoint { + remote-endpoint = + <&tpda19_in_funnel_dlct0>; + source = <&tpdm_dlct>; + }; + }; + + port@7 { + reg = <0>; + funnel_dlct0_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_funnel_dlct0>; + }; + }; + + port@8 { + reg = <0>; + funnel_dlct0_in_funnel_lpass: endpoint { + slave-mode; + remote-endpoint = + <&funnel_lpass_out_funnel_dlct0>; + }; + }; + + port@9 { + reg = <4>; + funnel_dlct0_in_funnel_npu: endpoint { + slave-mode; + remote-endpoint = + <&funnel_npu_out_funnel_dlct0>; + }; + }; + + port@10 { + reg = <5>; + funnel_dlct0_in_funnel_dlnt: endpoint { + slave-mode; + remote-endpoint = + <&funnel_dlnt_out_funnel_dlct0>; + }; + }; + + port@11 { + reg = <6>; + funnel_dlct0_in_tpdm_dlct: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dlct_out_funnel_dlct0>; + }; + }; + + }; + }; + + funnel_gpu: funnel@6944000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + reg = <0x6944000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-gpu"; + status = "disabled"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_gpu_out_tpda_dl_center: endpoint { + remote-endpoint = + <&tpda_dl_center_in_funnel_gpu>; + }; + }; + + port@1 { + reg = <0>; + funnel_gpu_in_tpdm_gpu: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_gpu_out_funnel_gpu>; + }; + }; + + }; + }; + + funnel_ddr0: funnel@6f85000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + reg = <0x6f85000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-ddr0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_ddr0_out_tpda_dl_center: endpoint { + remote-endpoint = + <&tpda_dl_center_in_funnel_ddr0>; + }; + }; + + port@1 { + reg = <0>; + funnel_ddr0_in_tpdm_ddr: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_ddr_out_funnel_ddr0>; + }; + }; + + }; + }; + + funnel_turing: funnel@6983000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + reg = <0x6983000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-turing"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_turing_out_tpda_dl_center5: endpoint { + remote-endpoint = + <&tpda_dl_center5_in_funnel_turing>; + source = <&tpdm_turing>; + }; + }; + + port@1 { + reg = <0>; + funnel_turing_out_tpda_dl_center6: endpoint { + remote-endpoint = + <&tpda_dl_center6_in_funnel_turing>; + source = <&tpdm_turing_llm>; + }; + }; + + port@2 { + reg = <0>; + funnel_turing_out_funnel_dlct1: endpoint { + remote-endpoint = + <&funnel_dlct1_in_funnel_turing>; + }; + }; + + port@3 { + reg = <0>; + funnel_turing_in_tpdm_turing: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_turing_out_funnel_turing>; + }; + }; + + port@4 { + reg = <1>; + funnel_turing_in_tpdm_turing_llm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_turing_llm_out_funnel_turing>; + }; + }; + + port@5 { + reg = <2>; + funnel_turing_in_turing_etm0: endpoint { + slave-mode; + remote-endpoint = + <&turing_etm0_out_funnel_turing>; + }; + }; + + }; + }; + + tpda_dl_center: tpda@6c38000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6c38000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-dl-center"; + qcom,tpda-atid = <78>; + qcom,dsb-elem-size = <0 32>, + <3 32>, + <5 32>, + <16 32>; + qcom,cmb-elem-size = <3 32>, + <6 32>, + <16 64>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_dl_center_out_funnel_dlct1: endpoint { + remote-endpoint = + <&funnel_dlct1_in_tpda_dl_center>; + }; + }; + + port@1 { + reg = <16>; + tpda_dl_center16_in_tpdm_pimem: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_pimem_out_tpda_dl_center16>; + }; + }; + + port@2 { + reg = <0>; + tpda_dl_center_in_funnel_gpu: endpoint { + slave-mode; + remote-endpoint = + <&funnel_gpu_out_tpda_dl_center>; + }; + }; + + port@3 { + reg = <3>; + tpda_dl_center_in_funnel_ddr0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_ddr0_out_tpda_dl_center>; + }; + }; + + port@4 { + reg = <5>; + tpda_dl_center5_in_funnel_turing: endpoint { + slave-mode; + remote-endpoint = + <&funnel_turing_out_tpda_dl_center5>; + }; + }; + + port@5 { + reg = <6>; + tpda_dl_center6_in_funnel_turing: endpoint { + slave-mode; + remote-endpoint = + <&funnel_turing_out_tpda_dl_center6>; + }; + }; + + }; + }; + + funnel_dlct1: funnel@6c39000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + reg = <0x6c39000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dlct1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_dlct1_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_dlct1>; + }; + }; + + port@1 { + reg = <0>; + funnel_dlct1_in_tpda_dl_center: endpoint { + slave-mode; + remote-endpoint = + <&tpda_dl_center_out_funnel_dlct1>; + }; + }; + + port@2 { + reg = <4>; + funnel_dlct1_in_funnel_turing: endpoint { + slave-mode; + remote-endpoint = + <&funnel_turing_out_funnel_dlct1>; + }; + }; + + }; + }; + + funnel_apss: funnel@7800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + reg = <0x7800000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_apss_out_funnel_apss_merge: endpoint { + remote-endpoint = + <&funnel_apss_merge_in_funnel_apss>; + }; + }; + + port@1 { + reg = <0>; + funnel_apss_in_etm0: endpoint { + slave-mode; + remote-endpoint = + <&etm0_out_funnel_apss>; + }; + }; + + port@2 { + reg = <1>; + funnel_apss_in_etm1: endpoint { + slave-mode; + remote-endpoint = + <&etm1_out_funnel_apss>; + }; + }; + + port@3 { + reg = <2>; + funnel_apss_in_etm2: endpoint { + slave-mode; + remote-endpoint = + <&etm2_out_funnel_apss>; + }; + }; + + port@4 { + reg = <3>; + funnel_apss_in_etm3: endpoint { + slave-mode; + remote-endpoint = + <&etm3_out_funnel_apss>; + }; + }; + + port@5 { + reg = <4>; + funnel_apss_in_etm4: endpoint { + slave-mode; + remote-endpoint = + <&etm4_out_funnel_apss>; + }; + }; + + port@6 { + reg = <5>; + funnel_apss_in_etm5: endpoint { + slave-mode; + remote-endpoint = + <&etm5_out_funnel_apss>; + }; + }; + + port@7 { + reg = <6>; + funnel_apss_in_etm6: endpoint { + slave-mode; + remote-endpoint = + <&etm6_out_funnel_apss>; + }; + }; + + port@8 { + reg = <7>; + funnel_apss_in_etm7: endpoint { + slave-mode; + remote-endpoint = + <&etm7_out_funnel_apss>; + }; + }; + + }; + }; + + tpda_olc: tpda@7832000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x7832000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-olc"; + qcom,tpda-atid = <69>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_olc_out_funnel_apss_merge: endpoint { + remote-endpoint = + <&funnel_apss_merge_in_tpda_olc>; + }; + }; + + port@1 { + reg = <0>; + tpda_olc0_in_tpdm_olc: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_olc_out_tpda_olc0>; + }; + }; + + }; + }; + + tpda_llm_silver: tpda@78c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x78c0000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-llm-silver"; + qcom,tpda-atid = <72>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_silver_out_funnel_apss_merge: endpoint { + remote-endpoint = + <&funnel_apss_merge_in_tpda_llm_silver>; + }; + }; + + port@1 { + reg = <0>; + tpda_llm_silver0_in_tpdm_llm_silver: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_llm_silver_out_tpda_llm_silver0>; + }; + }; + + }; + }; + + tpda_llm_gold: tpda@78d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x78d0000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-llm-gold"; + qcom,tpda-atid = <73>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_llm_gold_out_funnel_apss_merge: endpoint { + remote-endpoint = + <&funnel_apss_merge_in_tpda_llm_gold>; + }; + }; + + port@1 { + reg = <0>; + tpda_llm_gold0_in_tpdm_llm_gold: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_llm_gold_out_tpda_llm_gold0>; + }; + }; + + }; + }; + + tpda_apss: tpda@7862000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x7862000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-apss"; + qcom,tpda-atid = <66>; + qcom,dsb-elem-size = <0 32>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_apss_out_funnel_apss_merge: endpoint { + remote-endpoint = + <&funnel_apss_merge_in_tpda_apss>; + }; + }; + + port@1 { + reg = <0>; + tpda_apss0_in_tpdm_apss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_apss_out_tpda_apss0>; + }; + }; + + }; + }; + + funnel_apss_merge: funnel@7810000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + reg = <0x7810000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss-merge"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_apss_merge_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_apss_merge>; + }; + }; + + port@1 { + reg = <0>; + funnel_apss_merge_in_funnel_apss: endpoint { + slave-mode; + remote-endpoint = + <&funnel_apss_out_funnel_apss_merge>; + }; + }; + + port@2 { + reg = <2>; + funnel_apss_merge_in_tpda_olc: endpoint { + slave-mode; + remote-endpoint = + <&tpda_olc_out_funnel_apss_merge>; + }; + }; + + port@3 { + reg = <3>; + funnel_apss_merge_in_tpda_llm_silver: endpoint { + slave-mode; + remote-endpoint = + <&tpda_silver_out_funnel_apss_merge>; + }; + }; + + port@4 { + reg = <4>; + funnel_apss_merge_in_tpda_llm_gold: endpoint { + slave-mode; + remote-endpoint = + <&tpda_llm_gold_out_funnel_apss_merge>; + }; + }; + + port@5 { + reg = <5>; + funnel_apss_merge_in_tpda_apss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_apss_out_funnel_apss_merge>; + }; + }; + + }; + }; + + tpda: tpda@6004000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6004000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda"; + qcom,tpda-atid = <65>; + qcom,bc-elem-size = <16 32>, + <24 32>, + <25 32>; + qcom,tc-elem-size = <16 32>, + <25 32>; + qcom,dsb-elem-size = <2 32>, + <11 32>, + <14 32>, + <15 32>, + <19 32>, + <24 32>; + qcom,cmb-elem-size = <11 32>, + <12 32>, + <13 64>, + <14 32>, + <21 32>, + <22 32>, + <23 32>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_tpda>; + }; + }; + + port@1 { + reg = <21>; + tpda21_in_tpdm_vsense: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_vsense_out_tpda21>; + }; + }; + + port@2 { + reg = <22>; + tpda22_in_tpdm_dcc: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dcc_out_tpda22>; + }; + }; + + port@3 { + reg = <23>; + tpda23_in_tpdm_prng: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_prng_out_tpda23>; + }; + }; + + port@4 { + reg = <24>; + tpda24_in_tpdm_qm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_qm_out_tpda24>; + }; + }; + + port@5 { + reg = <2>; + tpda2_in_funnel_dlct0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_dlct0_out_tpda2>; + }; + }; + + port@6 { + reg = <11>; + tpda11_in_funnel_dlct0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_dlct0_out_tpda11>; + }; + }; + + port@7 { + reg = <12>; + tpda12_in_funnel_dlct0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_dlct0_out_tpda12>; + }; + }; + + port@8 { + reg = <13>; + tpda13_in_funnel_dlct0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_dlct0_out_tpda13>; + }; + }; + + port@9 { + reg = <14>; + tpda14_in_funnel_dlct0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_dlct0_out_tpda14>; + }; + }; + + port@10 { + reg = <15>; + tpda15_in_funnel_dlct0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_dlct0_out_tpda15>; + }; + }; + + port@11 { + reg = <19>; + tpda19_in_funnel_dlct0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_dlct0_out_tpda19>; + }; + }; + + }; + }; + + funnel_qatb: funnel@6005000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + reg = <0x6005000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-qatb"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_qatb_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_qatb>; + }; + }; + + port@1 { + reg = <0>; + funnel_qatb_in_tpda: endpoint { + slave-mode; + remote-endpoint = + <&tpda_out_funnel_qatb>; + }; + }; + + port@2 { + reg = <3>; + funnel_qatb_in_funnel_dlct0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_dlct0_out_funnel_qatb>; + }; + }; + + }; + }; + + funnel_in0: funnel@6041000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + reg = <0x6041000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_in0_out_funnel_merge: endpoint { + remote-endpoint = + <&funnel_merge_in_funnel_in0>; + }; + }; + + port@1 { + reg = <6>; + funnel_in0_in_funnel_qatb: endpoint { + slave-mode; + remote-endpoint = + <&funnel_qatb_out_funnel_in0>; + }; + }; + + port@2 { + reg = <7>; + funnel_in0_in_stm: endpoint { + slave-mode; + remote-endpoint = + <&stm_out_funnel_in0>; + }; + }; + + }; + }; + + funnel_in1: funnel@6042000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + reg = <0x6042000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_in1_out_funnel_merge: endpoint { + remote-endpoint = + <&funnel_merge_in_funnel_in1>; + }; + }; + + port@1 { + reg = <1>; + funnel_in1_in_funnel_dlct1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_dlct1_out_funnel_in1>; + }; + }; + + port@2 { + reg = <2>; + funnel_in1_in_tpdm_wcss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_wcss_out_funnel_in1>; + }; + }; + + port@3 { + reg = <4>; + funnel_in1_in_funnel_apss_merge: endpoint { + slave-mode; + remote-endpoint = + <&funnel_apss_merge_out_funnel_in1>; + }; + }; + + }; + }; + + funnel_merge: funnel@6045000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + reg = <0x6045000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-merge"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_merge_out_funnel_swao: endpoint { + remote-endpoint = + <&funnel_swao_in_funnel_merge>; + }; + }; + + port@1 { + reg = <0>; + funnel_merge_in_funnel_in0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in0_out_funnel_merge>; + }; + }; + + port@2 { + reg = <1>; + funnel_merge_in_funnel_in1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in1_out_funnel_merge>; + }; + }; + + }; + }; + + tpda_swao: tpda@6b08000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6b08000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-swao"; + qcom,tpda-atid = <71>; + qcom,dsb-elem-size = <1 32>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_swao_out_funnel_swao: endpoint { + remote-endpoint = + <&funnel_swao_in_tpda_swao>; + }; + }; + + port@1 { + reg = <0>; + tpda_swao0_in_tpdm_swao_0: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_swao_0_out_tpda_swao0>; + }; + }; + + port@2 { + reg = <1>; + tpda_swao1_in_tpdm_swao_1: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_swao_1_out_tpda_swao1>; + }; + }; + + }; + }; + + funnel_swao: funnel@6b04000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + reg = <0x6b04000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-swao"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_swao_out_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_in_funnel_swao>; + }; + }; + + port@1 { + reg = <5>; + funnel_swao_in_audio_etm0: endpoint { + slave-mode; + remote-endpoint = + <&audio_etm0_out_funnel_swao>; + }; + }; + + port@2 { + reg = <5>; + funnel_swao_in_tpdm_lpass_lpi: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_lpss_lpi_out_funnel_swao>; + }; + }; + + port@3 { + reg = <6>; + funnel_swao_in_tpda_swao: endpoint { + slave-mode; + remote-endpoint = + <&tpda_swao_out_funnel_swao>; + }; + }; + + port@4 { + reg = <7>; + funnel_swao_in_funnel_merge: endpoint { + slave-mode; + remote-endpoint = + <&funnel_merge_out_funnel_swao>; + }; + }; + + }; + }; + + tmc_etf: tmc@6b05000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + reg = <0x6b05000 0x1000>; + reg-names = "tmc-base"; + + coresight-csr = <&csr>; + coresight-name = "coresight-tmc-etf"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tmc_etf_out_replicator_swao: endpoint { + remote-endpoint = + <&replicator_swao_in_tmc_etf>; + }; + }; + + port@1 { + reg = <0>; + tmc_etf_in_funnel_swao: endpoint { + slave-mode; + remote-endpoint = + <&funnel_swao_out_tmc_etf>; + }; + }; + + }; + }; + + replicator_swao: replicator@6b06000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b909>; + reg = <0x6b06000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-swao"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + replicator_swao_out_replicator_qdss: endpoint { + remote-endpoint = + <&replicator_qdss_in_replicator_swao>; + }; + }; + + port@1 { + reg = <1>; + replicator_swao_out_eud: endpoint { + remote-endpoint = + <&eud_in_replicator_swao>; + }; + }; + + port@2 { + reg = <0>; + replicator_swao_in_tmc_etf: endpoint { + slave-mode; + remote-endpoint = + <&tmc_etf_out_replicator_swao>; + }; + }; + + }; + }; + + replicator_qdss: replicator@6046000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b909>; + reg = <0x6046000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-qdss"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + replicator_qdss_out_tmc_etr: endpoint { + remote-endpoint = + <&tmc_etr_in_replicator_qdss>; + }; + }; + + port@1 { + reg = <0>; + replicator_qdss_in_replicator_swao: endpoint { + slave-mode; + remote-endpoint = + <&replicator_swao_out_replicator_qdss>; + }; + }; + + }; + }; + + tmc_etr: tmc@6048000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + reg = <0x6048000 0x1000>, + <0x6064000 0x15000>; + reg-names = "tmc-base", "bam-base"; + + iommus = <&apps_smmu 0x04a0 0x20>, + <&apps_smmu 0x0480 0x20>; + + coresight-ctis = <&cti0 &cti0>; + coresight-csr = <&csr>; + coresight-name = "coresight-tmc-etr"; + arm,buffer-size = <0x400000>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + port { + tmc_etr_in_replicator_qdss: endpoint { + slave-mode; + remote-endpoint = + <&replicator_qdss_out_tmc_etr>; + }; + }; + }; + + cti_apss_cti0: cti@78e0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x78e0000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss_cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_apss_cti1: cti@78f0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x78f0000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss_cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_apss_cti2: cti@7900000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7900000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss_cti2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0: cti@6010000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6010000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1: cti@6011000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6011000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti10: cti@601a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti10"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti11: cti@601b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti11"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti12: cti@601c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti12"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti13: cti@601d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601d000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti13"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti14: cti@601e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601e000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti14"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti15: cti@601f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601f000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti15"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti2: cti@6012000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6012000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,cti-gpio-trigout = <4>; + pinctrl-names = "cti-trigout-pctrl"; + pinctrl-0 = <&trigout_a>; + }; + + cti3: cti@6013000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6013000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti3"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti4: cti@6014000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6014000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti4"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti5: cti@6015000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6015000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti5"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti6: cti@6016000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6016000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti6"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti7: cti@6017000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6017000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti7"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti8: cti@6018000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6018000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti8"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti9: cti@6019000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6019000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti9"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_mss: cti@680b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x680b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-mss_q6"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_venus: cti@6830000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6830000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-arm9"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_lpass_dl_cti: cti@6845000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6845000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-lpass_dl_cti"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_gpu_isdb_cti: cti@6941000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6941000 0x1000>; + reg-names = "cti-base"; + + status = "disabled"; + coresight-name = "coresight-cti-gpu_isdb_cti"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_gpu_cortex_m3: cti@6942000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6942000 0x1000>; + reg-names = "cti-base"; + + status = "disabled"; + coresight-name = "coresight-cti-gpu_cortex_m3"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_turing_dl_cti: cti@6982000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6982000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-turing_dl_cti"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_turing_q6_cti: cti@698b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x698b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-turing_q6_cti"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_dl_north_cti0: cti@6ac1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6ac1000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlnt_cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_dl_north_cti1: cti@6ac2000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6ac2000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlnt_cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_dl_north_cti2: cti@6ac3000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6ac3000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlnt_cti2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_dl_north_cti3: cti@6ac4000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6ac4000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlnt_cti3"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_swao_cti0: cti@6b00000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b00000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_swao_cti1: cti@6b01000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b01000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_swao_cti2: cti@6b02000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b02000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_swao_cti3: cti@6b03000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b03000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti3"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_aop_m3: cti@6b0e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b0e000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cortex_m3"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_lpass_lpi_cti: cti@6b21000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b21000 0x1000>; + reg-names = "cti-base"; + + status = "disabled"; + + coresight-name = "coresight-cti-lpass_lpi_cti"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_lpass_q6_cti: cti@6b2B000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b2B000 0x1000>; + reg-names = "cti-base"; + + status = "disabled"; + coresight-name = "coresight-cti-lpass_q6_cti"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_dlct_cti0: cti@6c2a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6c2a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct0_cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_dlct_cti1: cti@6C2b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6C2b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct0_cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_dlct_cti2: cti@6c2c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6c2c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct0_cti2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_npu_dl_cti_0: cti@6c42000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6c42000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-npu_dl_cti_0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_npu_dl_cti_1: cti@6C43000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6C43000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-npu_dl_cti_1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_npu_q6_cti: cti@6C4b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6C4b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-npu_q6_cti"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_sierra_a6_cti: cti@6c13000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6c13000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-sierra_a6_cti"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_mdss_dl_cti: cti@6c61000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6c61000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-mdss_dl_cti"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_ddr_dl_0_cti_0: cti@6f82000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6f82000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_0_cti_0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_ddr_dl_0_cti_1: cti@6f83000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6f83000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_0_cti_1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_ddr_dl_0_cti_2: cti@6f84000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6f84000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_0_cti_2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_ddr_dl_1_cti_0: cti@6f90000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6f90000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_1_cti_0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_ddr_dl_1_cti_1: cti@6f91000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6f91000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_1_cti_1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_ddr_dl_1_cti_2: cti@6f92000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6f92000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_1_cti_2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_olc: cti@7831000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7831000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-olc"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_dl_apss: cti@7861000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7861000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dl-apss"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + stm: stm@6002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b962>; + + reg = <0x6002000 0x1000>, + <0x16280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + coresight-name = "coresight-stm"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + stm_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_stm>; + }; + }; + + }; + + swao_csr: csr@6b0c000 { + compatible = "qcom,coresight-csr"; + reg = <0x6b0c000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-swao-csr"; + qcom,timestamp-support; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,blk-size = <1>; + }; + + hwevent { + compatible = "qcom,coresight-hwevent"; + + coresight-name = "coresight-hwevent"; + coresight-csr = <&csr>; + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + dummy_eud: dummy_sink { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-eud"; + + qcom,dummy-sink; + port { + eud_in_replicator_swao: endpoint { + slave-mode; + remote-endpoint = + <&replicator_swao_out_eud>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/atoll-gdsc.dtsi b/arch/arm/boot/dts/qcom/atoll-gdsc.dtsi new file mode 100644 index 000000000000..723bdb0495c8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/atoll-gdsc.dtsi @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + /* GDSCs in Global CC */ + ufs_phy_gdsc: qcom,gdsc@177004 { + compatible = "regulator-fixed"; + regulator-name = "ufs_phy_gdsc"; + reg = <0x177004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + usb30_prim_gdsc: qcom,gdsc@10f004 { + compatible = "regulator-fixed"; + regulator-name = "usb30_prim_gdsc"; + reg = <0x10f004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d040 { + compatible = "regulator-fixed"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; + reg = <0x17d040 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@17d044 { + compatible = "regulator-fixed"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc"; + reg = <0x17d044 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + /* GDSCs in Camera CC */ + bps_gdsc: qcom,gdsc@ad06004 { + compatible = "regulator-fixed"; + regulator-name = "bps_gdsc"; + reg = <0xad06004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + ipe_0_gdsc: qcom,gdsc@ad07004 { + compatible = "regulator-fixed"; + regulator-name = "ipe_0_gdsc"; + reg = <0xad07004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + ife_0_gdsc: qcom,gdsc@ad09004 { + compatible = "regulator-fixed"; + regulator-name = "ife_0_gdsc"; + reg = <0xad09004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + ife_1_gdsc: qcom,gdsc@ad0a004 { + compatible = "regulator-fixed"; + regulator-name = "ife_1_gdsc"; + reg = <0xad0a004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + titan_top_gdsc: qcom,gdsc@ad0b134 { + compatible = "regulator-fixed"; + regulator-name = "titan_top_gdsc"; + reg = <0xad0b134 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + /* GDSCs in Display CC */ + mdss_core_gdsc: qcom,gdsc@af03000 { + compatible = "regulator-fixed"; + regulator-name = "mdss_core_gdsc"; + reg = <0xaf03000 0x4>; + qcom,poll-cfg-gdscr; + qcom,support-hw-trigger; + status = "disabled"; + proxy-supply = <&mdss_core_gdsc>; + qcom,proxy-consumer-enable; + }; + + /* GDSCs in Graphics CC */ + gpu_cx_hw_ctrl: syscon@5091540 { + compatible = "syscon"; + reg = <0x5091540 0x4>; + }; + + gpu_gx_domain_addr: syscon@5091508 { + compatible = "syscon"; + reg = <0x5091508 0x4>; + }; + + gpu_gx_sw_reset: syscon@5091008 { + compatible = "syscon"; + reg = <0x5091008 0x4>; + }; + + gpu_cx_gdsc: qcom,gdsc@509106c { + compatible = "regulator-fixed"; + regulator-name = "gpu_cx_gdsc"; + reg = <0x509106c 0x4>; + hw-ctrl-addr = <&gpu_cx_hw_ctrl>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + qcom,clk-dis-wait-val = <8>; + status = "disabled"; + }; + + gpu_gx_gdsc: qcom,gdsc@509100c { + compatible = "regulator-fixed"; + regulator-name = "gpu_gx_gdsc"; + reg = <0x509100c 0x4>; + qcom,poll-cfg-gdscr; + domain-addr = <&gpu_gx_domain_addr>; + sw-reset = <&gpu_gx_sw_reset>; + status = "disabled"; + }; + + /* GDSCs in Video CC */ + vcodec0_gdsc: qcom,gdsc@ab00874 { + compatible = "regulator-fixed"; + regulator-name = "vcodec0_gdsc"; + reg = <0xab00874 0x4>; + status = "disabled"; + }; + + venus_gdsc: qcom,gdsc@ab00814 { + compatible = "regulator-fixed"; + regulator-name = "venus_gdsc"; + reg = <0xab00814 0x4>; + status = "disabled"; + }; + + /* GDSCs in NPU CC */ + npu_core_gdsc: qcom,gdsc@9981004 { + compatible = "regulator-fixed"; + regulator-name = "npu_core_gdsc"; + reg = <0x9981004 0x4>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll-usbc-idp-overlay.dts b/arch/arm/boot/dts/qcom/atoll-idp-overlay.dts similarity index 93% rename from arch/arm64/boot/dts/qcom/atoll-usbc-idp-overlay.dts rename to arch/arm/boot/dts/qcom/atoll-idp-overlay.dts index c84414e72a51..46b35d146ce3 100644 --- a/arch/arm64/boot/dts/qcom/atoll-usbc-idp-overlay.dts +++ b/arch/arm/boot/dts/qcom/atoll-idp-overlay.dts @@ -18,8 +18,8 @@ #include "atoll-idp.dtsi" / { - model = "USBC Audio IDP"; + model = "IDP"; compatible = "qcom,atoll-idp", "qcom,atoll", "qcom,idp"; qcom,msm-id = <407 0x0>; - qcom,board-id = <34 2>; + qcom,board-id = <34 0>; }; diff --git a/arch/arm64/boot/dts/qcom/atoll-usbc-idp.dts b/arch/arm/boot/dts/qcom/atoll-idp.dts similarity index 87% rename from arch/arm64/boot/dts/qcom/atoll-usbc-idp.dts rename to arch/arm/boot/dts/qcom/atoll-idp.dts index 7d7e38278a5a..ff2b4c4266c9 100644 --- a/arch/arm64/boot/dts/qcom/atoll-usbc-idp.dts +++ b/arch/arm/boot/dts/qcom/atoll-idp.dts @@ -16,7 +16,7 @@ #include "atoll-idp.dtsi" / { - model = "Qualcomm Technologies, Inc. ATOLL PM6150 USBC Audio IDP"; + model = "Qualcomm Technologies, Inc. ATOLL PM6150 IDP"; compatible = "qcom,atoll-idp", "qcom,atoll", "qcom,idp"; - qcom,board-id = <34 2>; + qcom,board-id = <34 0>; }; diff --git a/arch/arm64/boot/dts/qcom/atoll-atp.dtsi b/arch/arm/boot/dts/qcom/atoll-idp.dtsi similarity index 95% rename from arch/arm64/boot/dts/qcom/atoll-atp.dtsi rename to arch/arm/boot/dts/qcom/atoll-idp.dtsi index a2bfa96448c0..a9c5ba4e4177 100644 --- a/arch/arm64/boot/dts/qcom/atoll-atp.dtsi +++ b/arch/arm/boot/dts/qcom/atoll-idp.dtsi @@ -57,14 +57,6 @@ }; }; -&usb0 { - extcon = <&pm6150_pdphy>, <&pm6150_charger>; -}; - -&usb_qmp_dp_phy { - extcon = <&pm6150_pdphy>; -}; - &spmi_bus { qcom,pm6150l@4 { pm6150l_adc_tm_iio: adc_tm@3400 { diff --git a/arch/arm/boot/dts/qcom/atoll-ion.dtsi b/arch/arm/boot/dts/qcom/atoll-ion.dtsi new file mode 100644 index 000000000000..fa7262d64552 --- /dev/null +++ b/arch/arm/boot/dts/qcom/atoll-ion.dtsi @@ -0,0 +1,41 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = <25>; + qcom,ion-heap-type = "SYSTEM"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = <27>; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@9 { + reg = <9>; + qcom,ion-heap-type = "SYSTEM_SECURE"; + }; + + qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ + reg = <10>; + memory-region = <&secure_display_memory>; + qcom,ion-heap-type = "HYP_CMA"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/atoll-pinctrl.dtsi b/arch/arm/boot/dts/qcom/atoll-pinctrl.dtsi new file mode 100644 index 000000000000..328f975d136b --- /dev/null +++ b/arch/arm/boot/dts/qcom/atoll-pinctrl.dtsi @@ -0,0 +1,250 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tlmm: pinctrl@3400000 { + compatible = "qcom,atoll-pinctrl"; + reg = <0x03400000 0x989000>, <0x17c000f0 0x60>; + reg-names = "pinctrl", "spi_cfg"; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + ufs_dev_reset_assert: ufs_dev_reset_assert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * UFS_RESET driver strengths are having + * different values/steps compared to typical + * GPIO drive strengths. + * + * Following table clarifies: + * + * HDRV value | UFS_RESET | Typical GPIO + * (dec) | (mA) | (mA) + * 0 | 0.8 | 2 + * 1 | 1.55 | 4 + * 2 | 2.35 | 6 + * 3 | 3.1 | 8 + * 4 | 3.9 | 10 + * 5 | 4.65 | 12 + * 6 | 5.4 | 14 + * 7 | 6.15 | 16 + * + * POR value for UFS_RESET HDRV is 3 which means + * 3.1mA and we want to use that. Hence just + * specify 8mA to "drive-strength" binding and + * that should result into writing 3 to HDRV + * field. + */ + drive-strength = <8>; /* default: 3.1 mA */ + output-low; /* active low reset */ + }; + }; + + ufs_dev_reset_deassert: ufs_dev_reset_deassert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * default: 3.1 mA + * check comments under ufs_dev_reset_assert + */ + drive-strength = <8>; + output-high; /* active low reset */ + }; + }; + + /* SDC pin type */ + sdc1_clk_on: sdc1_clk_on { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc1_clk_off: sdc1_clk_off { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_cmd_on: sdc1_cmd_on { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_cmd_off: sdc1_cmd_off { + config { + pins = "sdc1_cmd"; + num-grp-pins = <1>; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_data_on: sdc1_data_on { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_data_off: sdc1_data_off { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_rclk_on: sdc1_rclk_on { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc1_rclk_off: sdc1_rclk_off { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_on: cd_on { + mux { + pins = "gpio69"; + function = "gpio"; + }; + + config { + pins = "gpio69"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_cd_off: cd_off { + mux { + pins = "gpio69"; + function = "gpio"; + }; + + config { + pins = "gpio69"; + drive-strength = <2>; + bias-disable; + }; + }; + + trigout_a: trigout_a { + mux { + pins = "gpio72"; + function = "qdss_cti"; + }; + + config { + pins = "gpio72"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se8_2uart_pins: qupv3_se8_2uart_pins { + qupv3_se8_2uart_active: qupv3_se8_2uart_active { + mux { + pins = "gpio44", "gpio45"; + function = "qup12"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se8_2uart_sleep: qupv3_se8_2uart_sleep { + mux { + pins = "gpio44", "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + }; +}; diff --git a/arch/arm/boot/dts/qcom/atoll-pm.dtsi b/arch/arm/boot/dts/qcom/atoll-pm.dtsi new file mode 100644 index 000000000000..b482446cfe8b --- /dev/null +++ b/arch/arm/boot/dts/qcom/atoll-pm.dtsi @@ -0,0 +1,170 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm-cluster@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + label = "L3"; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xfff>; + qcom,clstr-tmr-add = <1000>; + + qcom,pm-cluster-level@0 { /* D1 */ + reg = <0>; + label = "l3-wfi"; + qcom,psci-mode = <0x1>; + qcom,entry-latency-us = <660>; + qcom,exit-latency-us = <600>; + qcom,min-residency-us = <1260>; + }; + + qcom,pm-cluster-level@1 { /* D4 */ + reg = <1>; + label = "l3-pc"; + qcom,psci-mode = <0x4>; + qcom,entry-latency-us = <2752>; + qcom,exit-latency-us = <3048>; + qcom,min-residency-us = <6118>; + qcom,min-child-idx = <2>; + qcom,is-reset; + }; + + qcom,pm-cluster-level@2 { /* Cx Ret */ + reg = <2>; + label = "cx-ret"; + qcom,psci-mode = <0x124>; + qcom,entry-latency-us = <3638>; + qcom,exit-latency-us = <4562>; + qcom,min-residency-us = <8467>; + qcom,min-child-idx = <2>; + qcom,is-reset; + qcom,notify-rpm; + }; + + qcom,pm-cluster-level@3 { /* LLCC off, AOSS sleep */ + reg = <3>; + label = "llcc-off"; + qcom,psci-mode = <0xB24>; + qcom,entry-latency-us = <3263>; + qcom,exit-latency-us = <6562>; + qcom,min-residency-us = <9826>; + qcom,min-child-idx = <2>; + qcom,is-reset; + qcom,notify-rpm; + }; + + qcom,pm-cpu@0 { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,ref-stddev = <500>; + qcom,tmr-add = <1000>; + qcom,ref-premature-cnt = <1>; + qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 + &CPU5>; + + qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + label = "wfi"; + qcom,psci-cpu-mode = <0x1>; + qcom,entry-latency-us = <61>; + qcom,exit-latency-us = <60>; + qcom,min-residency-us = <121>; + }; + + qcom,pm-cpu-level@1 { /* C3 */ + reg = <1>; + label = "pc"; + qcom,psci-cpu-mode = <0x3>; + qcom,entry-latency-us = <549>; + qcom,exit-latency-us = <901>; + qcom,min-residency-us = <1774>; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + + qcom,pm-cpu-level@2 { /* C4 */ + reg = <2>; + label = "rail-pc"; + qcom,psci-cpu-mode = <0x4>; + qcom,entry-latency-us = <702>; + qcom,exit-latency-us = <915>; + qcom,min-residency-us = <4001>; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + + qcom,pm-cpu@1 { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,ref-stddev = <100>; + qcom,tmr-add = <100>; + qcom,ref-premature-cnt = <3>; + qcom,cpu = <&CPU6 &CPU7>; + + qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + label = "wfi"; + qcom,psci-cpu-mode = <0x1>; + qcom,entry-latency-us = <55>; + qcom,exit-latency-us = <66>; + qcom,min-residency-us = <121>; + }; + + qcom,pm-cpu-level@1 { /* C3 */ + reg = <1>; + label = "pc"; + qcom,psci-cpu-mode = <0x3>; + qcom,entry-latency-us = <523>; + qcom,exit-latency-us = <1244>; + qcom,min-residency-us = <2207>; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + + qcom,pm-cpu-level@2 { /* C4 */ + reg = <2>; + label = "rail-pc"; + qcom,psci-cpu-mode = <0x4>; + qcom,entry-latency-us = <526>; + qcom,exit-latency-us = <1854>; + qcom,min-residency-us = <5555>; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + }; + }; + + qcom,rpm-stats@c300000 { + compatible = "qcom,rpm-stats"; + reg = <0xc300000 0x1000>, <0xc3f0004 0x4>; + reg-names = "phys_addr_base", "offset_addr"; + qcom,num-records = <3>; + }; + + qcom,rpmh-master-stats@b221200 { + compatible = "qcom,rpmh-master-stats-v1"; + reg = <0xb221200 0x60>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/atoll-qrd-overlay.dts b/arch/arm/boot/dts/qcom/atoll-qrd-overlay.dts new file mode 100644 index 000000000000..a041d8a82236 --- /dev/null +++ b/arch/arm/boot/dts/qcom/atoll-qrd-overlay.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include "atoll-qrd.dtsi" + +/ { + model = "QRD"; + compatible = "qcom,atoll-qrd", "qcom,atoll", "qcom,qrd"; + qcom,msm-id = <407 0x0>; + qcom,board-id = <0x1000B 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll-atp.dts b/arch/arm/boot/dts/qcom/atoll-qrd.dts similarity index 76% rename from arch/arm64/boot/dts/qcom/atoll-atp.dts rename to arch/arm/boot/dts/qcom/atoll-qrd.dts index 2e7bb88a2c4e..9a61533fdfec 100644 --- a/arch/arm64/boot/dts/qcom/atoll-atp.dts +++ b/arch/arm/boot/dts/qcom/atoll-qrd.dts @@ -13,10 +13,10 @@ /dts-v1/; #include "atoll.dtsi" -#include "atoll-atp.dtsi" +#include "atoll-qrd.dtsi" / { - model = "Qualcomm Technologies, Inc. ATOLL PM6150 ATP"; - compatible = "qcom,atoll-idp", "qcom,atoll", "qcom,idp", "qcom,atp"; - qcom,board-id = <33 0>; + model = "Qualcomm Technologies, Inc. ATOLL PM6150 QRD"; + compatible = "qcom,atoll-qrd", "qcom,atoll", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; }; diff --git a/arch/arm/boot/dts/qcom/atoll-qrd.dtsi b/arch/arm/boot/dts/qcom/atoll-qrd.dtsi new file mode 100644 index 000000000000..9132ac26e635 --- /dev/null +++ b/arch/arm/boot/dts/qcom/atoll-qrd.dtsi @@ -0,0 +1,14 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { +}; diff --git a/arch/arm/boot/dts/qcom/atoll-qupv3.dtsi b/arch/arm/boot/dts/qcom/atoll-qupv3.dtsi new file mode 100644 index 000000000000..a79cdac7c492 --- /dev/null +++ b/arch/arm/boot/dts/qcom/atoll-qupv3.dtsi @@ -0,0 +1,62 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + + /* QUPv3 North instances */ + qupv3_0: qcom,qupv3_0_geni_se@0x8c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x8c0000 0x2000>; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; + qcom,iommu-s1-bypass; + + iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0x043 0x0>; + }; + }; + + /* QUPv3 South Instances */ + qupv3_1: qcom,qupv3_1_geni_se@0xac0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0xac0000 0x2000>; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; + qcom,iommu-s1-bypass; + + iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0x4c3 0x0>; + }; + }; + + /* Debug UART Instance for CDP/MTP/RUMI platform: QUPV3_1_SE2 */ + qupv3_se8_2uart: qcom,qup_uart@0xa88000 { + compatible = "qcom,msm-geni-console"; + reg = <0xa88000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_2uart_active>; + pinctrl-1 = <&qupv3_se8_2uart_sleep>; + interrupts = ; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; +}; + diff --git a/arch/arm64/boot/dts/qcom/atoll-atp-overlay.dts b/arch/arm/boot/dts/qcom/atoll-rumi-overlay.dts similarity index 82% rename from arch/arm64/boot/dts/qcom/atoll-atp-overlay.dts rename to arch/arm/boot/dts/qcom/atoll-rumi-overlay.dts index 28d6d79ddfbd..cac08cb5989f 100644 --- a/arch/arm64/boot/dts/qcom/atoll-atp-overlay.dts +++ b/arch/arm/boot/dts/qcom/atoll-rumi-overlay.dts @@ -15,11 +15,11 @@ #include -#include "atoll-atp.dtsi" +#include "atoll-rumi.dtsi" / { - model = "ATP"; - compatible = "qcom,atoll-idp", "qcom,atoll", "qcom,idp", "qcom,atp"; + model = "RUMI"; + compatible = "qcom,atoll-rumi", "qcom,atoll", "qcom,rumi"; qcom,msm-id = <407 0x0>; - qcom,board-id = <33 0>; + qcom,board-id = <15 0>; }; diff --git a/arch/arm/boot/dts/qcom/atoll-rumi.dts b/arch/arm/boot/dts/qcom/atoll-rumi.dts new file mode 100644 index 000000000000..211ad5995532 --- /dev/null +++ b/arch/arm/boot/dts/qcom/atoll-rumi.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "atoll.dtsi" +#include "atoll-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. ATOLL PM6150 RUMI"; + compatible = "qcom,atoll-rumi", "qcom,atoll", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/arch/arm/boot/dts/qcom/atoll-rumi.dtsi b/arch/arm/boot/dts/qcom/atoll-rumi.dtsi new file mode 100644 index 000000000000..1d0c58235836 --- /dev/null +++ b/arch/arm/boot/dts/qcom/atoll-rumi.dtsi @@ -0,0 +1,144 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + timer { + clock-frequency = <1000000>; + }; + + timer@17c20000 { + clock-frequency = <1000000>; + }; + + usb_emu_phy: usb_emu_phy@a720000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x0a720000 0x9500>, + <0x0a6f8800 0x100>; + reg-names = "base", "qcratch_base"; + + qcom,emu-init-seq = <0xfff0 0x4 + 0xfff3 0x4 + 0x40 0x4 + 0xfff3 0x4 + 0xfff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x1a0 0x20 + 0x100000 0x3c + 0x0 0x3c + 0x10060 0x3c + 0x0 0x4>; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + wdog: qcom,wdt@17c10000{ + status = "disabled"; + }; + + disp_rsc: mailbox@af20000 { + status = "disabled"; + }; +}; + +#include "atoll-stub-regulator.dtsi" + +&sdhc_1 { + vdd-supply = <&pm6150_l19>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&pm6150_l12>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on + &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off + &sdc1_rclk_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000>; + qcom,bus-speed-mode = "DDR_1p8v"; + + /delete-property/qcom,devfreq,freq-table; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm6150l_l9>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&pm6150l_l6>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50"; + + /delete-property/qcom,devfreq,freq-table; + + status = "ok"; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qrbtc-sdm845"; + + vdda-phy-supply = <&pm6150_l4>; /* 0.88v */ + vdda-pll-supply = <&pm6150l_l3>; /* 1.2v */ + vdda-phy-max-microamp = <62900>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + limit-tx-hs-gear = <1>; + limit-rx-hs-gear = <1>; + scsi-cmd-timeout = <300000>; + + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm6150_l19>; + vccq2-supply = <&pm6150_l12>; + vcc-max-microamp = <600000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm6150l_l3>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vddp-ref-clk-min-uV = <1200000>; + qcom,vddp-ref-clk-max-uV = <1200000>; + + + qcom,disable-lpm; + rpm-level = <0>; + spm-level = <0>; + status = "ok"; +}; + +&usb0 { + dwc3@a600000 { + usb-phy = <&usb_emu_phy>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/atoll-stub-regulator.dtsi b/arch/arm/boot/dts/qcom/atoll-stub-regulator.dtsi new file mode 100644 index 000000000000..889b00937b97 --- /dev/null +++ b/arch/arm/boot/dts/qcom/atoll-stub-regulator.dtsi @@ -0,0 +1,405 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +/* Stub regulators */ + +/ { + /* pm6150l S1 - VDD_CX supply */ + VDD_CX_LEVEL: + S1C_LEVEL: pm6150l_s1_level: regulator-pm6150l-s1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_s1_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + VDD_CX_LEVEL_AO: + S1C_LEVEL_AO: pm6150l_s1_level_ao: regulator-pm6150l-s1-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_s1_level_ao"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + /* pm6150 S2 - VDD_GFX supply */ + VDD_GFX_LEVEL: + S2A_LEVEL: pm6150_s2_level: regulator-pm6150-s2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_s2_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + VDD_GFX_LEVEL_AO: + S2A_LEVEL_AO: pm6150_s2_level_ao: regulator-pm6150-s2-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_s2_level_ao"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + /* pm6150 S3 - VDD_MX supply */ + VDD_MX_LEVEL: + S3A_LEVEL: pm6150_s3_level: regulator-pm6150-s3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_s3_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + VDD_MX_LEVEL_AO: + S3A_LEVEL_AO: pm6150_s3_level_ao: regulator-pm6150-s3-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_s3_level_ao"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + S1A: pm6150_s1: regulator-pm6150-s1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_s1"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + /* pm6150l S7 - VDD_MSS supply */ + VDD_MSS_LEVEL: + S7C_LEVEL: pm6150l_s7_level: regulator-pm6150l-s7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_s7_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + S8C: pm6150l_s8: regulator-pm6150l-s8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_s8"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + }; + + L1A: pm6150_l1: regulator-pm6150-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1178000>; + regulator-max-microvolt = <1252000>; + }; + + L2A: pm6150_l2: regulator-pm6150-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1050000>; + }; + + L3A: pm6150_l3: regulator-pm6150-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <970000>; + regulator-max-microvolt = <1060000>; + }; + + L4A: pm6150_l4: regulator-pm6150-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + }; + + L5A: pm6150_l5: regulator-pm6150-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2800000>; + }; + + L6A: pm6150_l6: regulator-pm6150-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <650000>; + }; + + /* pm6150 L7 - LPI_MX supply */ + L7A_LEVEL: pm6150_l7_level: regulator-pm6150-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l7_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + /* pm6150 L8 - LPI_CX supply */ + L8A_LEVEL: pm6150_l8_level: regulator-pm6150-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l8_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + L9A: pm6150_l9: regulator-pm6150-l9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <630000>; + regulator-max-microvolt = <760000>; + }; + + L10A: pm6150_l10: regulator-pm6150-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l10"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1721000>; + regulator-max-microvolt = <1829000>; + }; + + L11A: pm6150_l11: regulator-pm6150-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l11"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + L12A: pm6150_l12: regulator-pm6150-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l12"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1950000>; + }; + + L13A: pm6150_l13: regulator-pm6150-l13 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l13"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + + L14A: pm6150_l14: regulator-pm6150-l14 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l14"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1721000>; + regulator-max-microvolt = <1850000>; + }; + + L15A: pm6150_l15: regulator-pm6150-l15 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l15"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + + L16A: pm6150_l16: regulator-pm6150-l16 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l16"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2430000>; + regulator-max-microvolt = <2970000>; + }; + + L17A: pm6150_l17: regulator-pm6150-l17 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l17"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3230000>; + }; + + L18A: pm6150_l18: regulator-pm6150-l18 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l18"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <4400000>; + }; + + L19A: pm6150_l19: regulator-pm6150-l19 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l19"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3300000>; + }; + + L1C: pm6150l_l1: regulator-pm6150l-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + L2C: pm6150l_l2: regulator-pm6150l-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + }; + + L3C: pm6150l_l3: regulator-pm6150l-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + }; + + L4C: pm6150l_l4: regulator-pm6150l-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3300000>; + }; + + L5C: pm6150l_l5: regulator-pm6150l-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3300000>; + }; + + L6C: pm6150l_l6: regulator-pm6150l-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l6"; + qcom,hpm-min-load = <5000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3600000>; + }; + + L7C: pm6150l_l7: regulator-pm6150l-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + }; + + L8C: pm6150l_l8: regulator-pm6150l-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + + L9C: pm6150l_l9: regulator-pm6150l-l9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3300000>; + }; + + L10C: pm6150l_l10: regulator-pm6150l-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l10"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3400000>; + }; + + L11C: pm6150l_l11: regulator-pm6150l-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l11"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + }; + + BOB: pm6150l_bob: regulator-pm6150l-bob { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_bob"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <4200000>; + }; + + BOB_AO: pm6150l_bob_ao: regulator-pm6150l-bob-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_bob_ao"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <4200000>; + }; + + L1P: qcom,pm8008-l1@4000 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8008_l1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1600000>; + }; + + L2P: qcom,pm8008-l2@4100 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8008_l2"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + L3P: qcom,pm8008-l3@4200 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8008_l3"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + }; + + L4P: qcom,pm8008-l4@4300 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8008_l4"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + }; + + L5P: qcom,pm8008-l5@4400 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8008_l5"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3400000>; + }; + + L6P: qcom,pm8008-l6@4500 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8008_l6"; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3000000>; + }; + + L7P: qcom,pm8008-l7@4600 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8008_l7"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/atoll-thermal.dtsi b/arch/arm/boot/dts/qcom/atoll-thermal.dtsi new file mode 100644 index 000000000000..3397ad51b4b2 --- /dev/null +++ b/arch/arm/boot/dts/qcom/atoll-thermal.dtsi @@ -0,0 +1,621 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&thermal_zones { + aoss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 0>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 1>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 3>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-4-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-5-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 0>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cwlan-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 1>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + audio-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 2>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + ddr-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + q6-hvx-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 5>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-core-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 6>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-dsp-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 7>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + npu-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + video-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 9>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + xo-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6150_adc_tm ADC_XO_THERM_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + chg-skin-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6150_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + nvm-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6150_adc_tm ADC_GPIO1_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdm-skin-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6150_adc_tm ADC_GPIO2_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6150l_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-therm0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6150l_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + camera-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6150l_adc_tm ADC_GPIO1_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/atoll-usb.dtsi b/arch/arm/boot/dts/qcom/atoll-usb.dtsi new file mode 100644 index 000000000000..90b79a03bf55 --- /dev/null +++ b/arch/arm/boot/dts/qcom/atoll-usb.dtsi @@ -0,0 +1,372 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&soc { + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a600000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x540 0x0>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <0 489 0>, <0 130 0>, <0 486 0>, <0 488 0>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + USB3_GDSC-supply = <&usb30_prim_gdsc>; + dpdm-supply = <&qusb_phy0>; + qcom,use-pdc-interrupts; + + clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>, + <&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&clock_gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <133333333>; + qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + qcom,pm-qos-latency = <62>; + + qcom,msm-bus,name = "usb0"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <3>; + qcom,msm-bus,vectors-KBps = + /* suspend vote */ + , + , + , + + /* nominal vote */ + , + , + , + + /* svs vote */ + , + , + , + + /* min vote */ + , + , + ; + + qcom,default-bus-vote = <2>; /* use svs bus voting */ + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0x0a600000 0xcd00>; + interrupts = <0 133 0>; + usb-phy = <&qusb_phy0>, <&usb_qmp_dp_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + usb-core-id = <0>; + tx-fifo-resize; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + + qcom,usbbam@a704000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa704000 0x17000>; + interrupts = <0 132 0>; + + qcom,usb-bam-fifo-baseaddr = <0x146a6000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + /* Primary USB port related QUSB2 PHY */ + qusb_phy0: qusb@88e2000 { + compatible = "qcom,qusb2phy-v2"; + reg = <0x088e2000 0x400>, + <0x00780200 0x4>, + <0x088e7014 0x4>; + reg-names = "qusb_phy_base", "efuse_addr", + "refgen_north_bg_reg_addr"; + + qcom,efuse-bit-pos = <25>; + qcom,efuse-num-bits = <3>; + vdd-supply = <&pm6150_l4>; + vdda18-supply = <&pm6150_l11>; + vdda33-supply = <&pm6150_l17>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,qusb-phy-reg-offset = + <0x240 /* QUSB2PHY_PORT_TUNE1 */ + 0x1a0 /* QUSB2PHY_PLL_COMMON_STATUS_ONE */ + 0x210 /* QUSB2PHY_PWR_CTRL1 */ + 0x230 /* QUSB2PHY_INTR_CTRL */ + 0x0a8 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE */ + 0x254 /* QUSB2PHY_TEST1 */ + 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x27c /* QUSB2PHY_DEBUG_CTRL1 */ + 0x280 /* QUSB2PHY_DEBUG_CTRL2 */ + 0x2a0>; /* QUSB2PHY_STAT5 */ + + qcom,qusb-phy-init-seq = + /* */ + <0x23 0x210 /* PWR_CTRL1 */ + 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */ + 0x7c 0x18c /* PLL_CLOCK_INVERTERS */ + 0x80 0x2c /* PLL_CMODE */ + 0x0a 0x184 /* PLL_LOCK_DELAY */ + 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ + 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ + 0x22 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x21 0x214 /* PWR_CTRL2 */ + 0x08 0x220 /* IMP_CTRL1 */ + 0x58 0x224 /* IMP_CTRL2 */ + 0x45 0x240 /* TUNE1 */ + 0x29 0x244 /* TUNE2 */ + 0xca 0x248 /* TUNE3 */ + 0x04 0x24c /* TUNE4 */ + 0x03 0x250 /* TUNE5 */ + 0x30 0x23c /* CHG_CTRL2 */ + 0x22 0x210>; /* PWR_CTRL1 */ + + qcom,qusb-phy-host-init-seq = + /* */ + <0x23 0x210 /* PWR_CTRL1 */ + 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */ + 0x7c 0x18c /* PLL_CLOCK_INVERTERS */ + 0x80 0x2c /* PLL_CMODE */ + 0x0a 0x184 /* PLL_LOCK_DELAY */ + 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ + 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ + 0x22 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x21 0x214 /* PWR_CTRL2 */ + 0x08 0x220 /* IMP_CTRL1 */ + 0x58 0x224 /* IMP_CTRL2 */ + 0x45 0x240 /* TUNE1 */ + 0x29 0x244 /* TUNE2 */ + 0xca 0x248 /* TUNE3 */ + 0x04 0x24c /* TUNE4 */ + 0x03 0x250 /* TUNE5 */ + 0x30 0x23c /* CHG_CTRL2 */ + 0x22 0x210>; /* PWR_CTRL1 */ + + phy_type= "utmi"; + clocks = <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; + clock-names = "ref_clk_src", "cfg_ahb_clk"; + + resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + /* Primary USB port related QMP USB DP Combo PHY */ + usb_qmp_dp_phy: ssphy@88e8000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88e8000 0x3000>; + reg-names = "qmp_phy_base"; + vdd-supply = <&pm6150_l4>; + qcom,vdd-voltage-level = <0 880000 880000>; + core-supply = <&pm6150l_l3>; + qcom,vbus-valid-override; + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + + clocks = <&clock_gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk", "cfg_ahb_clk"; + + resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&clock_gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x1b2f 0x0>; + qcom,usb-audio-stream-id = <0xf>; + qcom,usb-audio-intr-num = <2>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/atoll-vidc.dtsi b/arch/arm/boot/dts/qcom/atoll-vidc.dtsi new file mode 100644 index 000000000000..24e21d0080ca --- /dev/null +++ b/arch/arm/boot/dts/qcom/atoll-vidc.dtsi @@ -0,0 +1,106 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&soc { + msm_vidc: qcom,vidc@aa00000 { + compatible = "qcom,msm-vidc", "qcom,atoll"; + status = "ok"; + reg = <0xaa00000 0x200000>; + interrupts = ; + + /* Supply */ + venus-supply = <&venus_gdsc>; + venus-core0-supply = <&vcodec0_gdsc>; + + /* Clocks */ + clock-names = "core_clk", "iface_clk", "bus_clk", + "core0_clk", "core0_bus_clk"; + clocks = <&clock_videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, + <&clock_videocc VIDEO_CC_VENUS_AHB_CLK>, + <&clock_videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, + <&clock_videocc VIDEO_CC_VCODEC0_CORE_CLK>, + <&clock_videocc VIDEO_CC_VCODEC0_AXI_CLK>; + qcom,proxy-clock-names = "core_clk", "iface_clk", + "bus_clk", "core0_clk", "core0_bus_clk"; + qcom,clock-configs = <0x1 0x0 0x0 0x1 0x0>; + qcom,allowed-clock-rates = <150000000 270000000 340000000 + 434000000>; + + /* Buses */ + bus_cnoc { + compatible = "qcom,msm-vidc,bus"; + label = "cnoc"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 1000>; + }; + + venus_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-ddr"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "vidc-ar50-ddr"; + qcom,bus-range-kbps = <1000 2128000>; + }; + arm9_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-arm9-ddr"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 1000>; + }; + + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_ns"; + iommus = <&apps_smmu 0xC00 0x60>; + buffer-types = <0xfff>; + virtual-addr-pool = <0x70800000 0x6f800000>; + }; + + secure_bitstream_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_bitstream"; + iommus = <&apps_smmu 0xC21 0x4>; + buffer-types = <0x241>; + virtual-addr-pool = <0x4b000000 0x25800000>; + qcom,secure-context-bank; + }; + + secure_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_pixel"; + iommus = <&apps_smmu 0xC23 0x0>; + buffer-types = <0x106>; + virtual-addr-pool = <0x25800000 0x25800000>; + qcom,secure-context-bank; + }; + + secure_non_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_non_pixel"; + iommus = <&apps_smmu 0xC04 0x60>; + buffer-types = <0x480>; + virtual-addr-pool = <0x1000000 0x24800000>; + qcom,secure-context-bank; + }; + }; +}; + diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_ir_led/cam_ir_led_soc.h b/arch/arm/boot/dts/qcom/atoll.dts similarity index 71% rename from drivers/media/platform/msm/camera/cam_sensor_module/cam_ir_led/cam_ir_led_soc.h rename to arch/arm/boot/dts/qcom/atoll.dts index 3a9139ae2cc1..22d9bd7c3b11 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_ir_led/cam_ir_led_soc.h +++ b/arch/arm/boot/dts/qcom/atoll.dts @@ -10,12 +10,13 @@ * GNU General Public License for more details. */ -#ifndef _CAM_IR_LED_SOC_H_ -#define _CAM_IR_LED_SOC_H_ +/dts-v1/; -#include "cam_ir_led_dev.h" +#include "atoll.dtsi" -int cam_ir_led_get_dt_data(struct cam_ir_led_ctrl *fctrl, - struct cam_hw_soc_info *soc_info); - -#endif /*_CAM_IR_LED_SOC_H_*/ +/ { + model = "Qualcomm Technologies, Inc. ATOLL SoC"; + compatible = "qcom,atoll"; + qcom,pmic-name = "PM6150"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm/boot/dts/qcom/atoll.dtsi b/arch/arm/boot/dts/qcom/atoll.dtsi new file mode 100644 index 000000000000..ef8f9ebafa09 --- /dev/null +++ b/arch/arm/boot/dts/qcom/atoll.dtsi @@ -0,0 +1,2486 @@ +/* Copyright (c) 2019, The Linux Foundation.All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "skeleton64.dtsi" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. ATOLL"; + compatible = "qcom,atoll"; + qcom,msm-name = "ATOLL"; + qcom,msm-id = <407 0x0>; + interrupt-parent = <&pdc>; + + aliases { + serial0 = &qupv3_se8_2uart; + sdhc1 = &sdhc_1; /* eMMC */ + sdhc2 = &sdhc_2; /* SD Card */ + ufshc1 = &ufshc_mem; /* Embedded UFS slot */ + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-size = <0x100000>; + cache-level = <3>; + }; + }; + + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_0: l2-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + next-level-cache = <&L2_100>; + L2_100: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_100: l2-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + next-level-cache = <&L2_200>; + L2_200: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_200: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_200: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_200: l2-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + next-level-cache = <&L2_300>; + L2_300: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_300: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_300: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_300: l2-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + next-level-cache = <&L2_400>; + L2_400: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_400: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_400: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_400: l2-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + next-level-cache = <&L2_500>; + L2_500: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_500: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_500: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_500: l2-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; + d-cache-size = <0x10000>; + i-cache-size = <0x10000>; + next-level-cache = <&L2_600>; + L2_600: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + qcom,dump-size = <0x48000>; + }; + + L1_I_600: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x11000>; + }; + + L1_D_600: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + + L1_ITLB_600: l1-itlb { + qcom,dump-size = <0x300>; + }; + + L1_DTLB_600: l1-dtlb { + qcom,dump-size = <0x480>; + }; + + L2_TLB_600: l2-tlb { + qcom,dump-size = <0x7800>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; + d-cache-size = <0x10000>; + i-cache-size = <0x10000>; + next-level-cache = <&L2_700>; + L2_700: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + qcom,dump-size = <0x48000>; + }; + + L1_I_700: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x11000>; + }; + + L1_D_700: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + + L1_ITLB_700: l1-itlb { + qcom,dump-size = <0x300>; + }; + + L1_DTLB_700: l1-dtlb { + qcom,dump-size = <0x480>; + }; + + L2_TLB_700: l2-tlb { + qcom,dump-size = <0x7800>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + }; + + cluster1 { + core0 { + cpu = <&CPU6>; + }; + + core1 { + cpu = <&CPU7>; + }; + }; + }; + }; + + energy_costs: energy-costs { + compatible = "sched-energy"; + + CPU_COST_0: core-cost0 { + busy-cost-data = < + 300000 10 + 576000 18 + 768000 23 + 1017600 36 + 1248000 52 + 1324800 67 + 1516800 76 + 1612800 92 + 1708800 113 + 1804800 119 + >; + idle-cost-data = < + 16 12 8 6 + >; + }; + + CPU_COST_1: core-cost1 { + busy-cost-data = < + 652800 242 + 825600 293 + 979200 424 + 1113600 470 + 1209600 621 + 1267200 676 + 1555200 973 + 1708800 1060 + 1843200 1298 + 1900800 1362 + 2112000 1801 + 2208000 2000 + 2304000 2326 + 2400000 2568 + >; + idle-cost-data = < + 100 80 60 40 + >; + }; + + CLUSTER_COST_0: cluster-cost0 { + busy-cost-data = < + 300000 5 + 576000 5 + 768000 5 + 1017600 7 + 1248000 8 + 1324800 10 + 1516800 10 + 1612800 12 + 1708800 14 + 1804800 14 + >; + idle-cost-data = < + 5 4 3 2 1 + >; + }; + + CLUSTER_COST_1: cluster-cost1 { + busy-cost-data = < + 652800 21 + 825600 21 + 979200 25 + 1113600 26 + 1209600 32 + 1267200 33 + 1555200 41 + 1708800 43 + 1843200 49 + 1900800 50 + 2112000 60 + 2208000 61 + 2304000 62 + 2400000 63 + >; + idle-cost-data = < + 5 4 3 2 1 + >; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + firmware: firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; + }; + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/7c4000.sdhci/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_region: hyp_region@80000000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x80000000 0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_mem@80700000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x80700000 0x0 0x140000>; + }; + + sec_apps_mem: sec_apps_region@808ff000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x808ff000 0x0 0x1000>; + }; + + smem_region: smem@80900000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x80900000 0x0 0x200000>; + }; + + removed_region: removed_region@80b00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x80b00000 0 0x3900000>; + }; + + pil_camera_mem: camera_region@8e000000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x8e000000 0 0x500000>; + }; + + pil_modem_mem: modem_region@86000000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x86000000 0 0x8000000>; + }; + + pil_video_mem: pil_video_region@8ea00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x8ea00000 0 0x500000>; + }; + + pil_cdsp_mem: cdsp_regions@8ef00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x8ef00000 0 0x1e00000>; + }; + + pil_adsp_mem: pil_adsp_region@90d00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x90d00000 0 0x2800000>; + }; + + wlan_fw_mem: wlan_fw_region@93500000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x93500000 0 0x200000>; + }; + + npu_mem: npu_region@8e500000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x8e500000 0 0x500000>; + }; + + pil_ipa_fw_mem: ipa_fw_region@93700000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x93700000 0 0x10000>; + }; + + pil_ipa_gsi_mem: ipa_gsi_region@93710000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x93710000 0 0x5000>; + }; + + pil_gpu_mem: gpu_region@93715000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x93715000 0 0x2000>; + }; + + qseecom_mem: qseecom_region@9e000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x9e000000 0 0x1400000>; + }; + + cdsp_sec_mem: cdsp_sec_regions@0x9f400000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x9f400000 0 0xc00000>; + }; + + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x8c00000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x2400000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x2000000>; + linux,cma-default; + }; + }; + + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + }; + + soc: soc { }; + +}; + +&soc { + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17a60000 0x100000>; /* GICR * 8 */ + interrupts = ; + interrupt-parent = <&intc>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,pdc-atoll"; + reg = <0xb220000 0x400>; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + timer@17c20000{ + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17c20000 0x1000>; + clock-frequency = <19200000>; + + frame@17c21000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = ; + reg = <0x17c23000 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = ; + reg = <0x17c25000 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = ; + reg = <0x17c27000 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = ; + reg = <0x17c29000 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = ; + reg = <0x17c2b000 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = ; + reg = <0x17c2d000 0x1000>; + status = "disabled"; + }; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = ; + }; + + jtag_mm0: jtagmm@7040000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7040000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU0>; + }; + + jtag_mm1: jtagmm@7140000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7140000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU1>; + }; + + jtag_mm2: jtagmm@7240000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7240000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU2>; + }; + + jtag_mm3: jtagmm@7340000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7340000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU3>; + }; + + jtag_mm4: jtagmm@7440000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7440000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU4>; + }; + + jtag_mm5: jtagmm@7540000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7540000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU5>; + }; + + jtag_mm6: jtagmm@7640000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7640000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU6>; + }; + + jtag_mm7: jtagmm@7740000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7740000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU7>; + }; + + qcom,msm-imem@146aa000 { + compatible = "qcom,msm-imem"; + reg = <0x146aa000 0x1000>; + ranges = <0x0 0x146aa000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 32>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 12>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 200>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 200>; + }; + }; + + dcc: dcc_v2@10a2000 { + compatible = "qcom,dcc-v2"; + reg = <0x10a2000 0x1000>, + <0x10ae000 0x2000>; + reg-names = "dcc-base", "dcc-ram-base"; + dcc-ram-offset = <0x6000>; + }; + + restart@c264000 { + compatible = "qcom,pshold"; + reg = <0xc264000 0x4>, + <0x1fd3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + aop-msg-client { + compatible = "qcom,debugfs-qmp-client"; + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + wdog: qcom,wdt@17c10000{ + compatible = "qcom,msm-watchdog"; + reg = <0x17c10000 0x1000>; + reg-names = "wdt-base"; + interrupts = , + ; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + qcom,scandump-sizes = <0x10100 0x10100 0x10100 0x10100 + 0x10100 0x10100 0x25900 0x25900>; + }; + + qcom,chd_sliver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x18000058 0x18010058 + 0x18020058 0x18030058 + 0x18040058 0x18050058>; + qcom,config-arr = <0x18000060 0x18010060 + 0x18020060 0x18030060 + 0x18040060 0x18050060>; + }; + + qcom,chd_gold { + compatible = "qcom,core-hang-detect"; + label = "gold"; + qcom,threshold-arr = <0x18060058 0x18070058>; + qcom,config-arr = <0x18060060 0x18070060>; + }; + + qcom,ghd { + compatible = "qcom,gladiator-hang-detect-v3"; + qcom,threshold-arr = <0x17e0041C>; + qcom,config-reg = <0x17e00434>; + }; + + kryo-erp { + compatible = "arm,arm64-kryo-cpu-erp"; + interrupts = , + ; + + interrupt-names = "l1-l2-faultirq", + "l3-scu-faultirq"; + }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x200000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + qcom,guard-memory; + }; + + pil_modem: qcom,mss@4080000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x4080000 0x100>; + + qcom,firmware-name = "modem"; + memory-region = <&pil_modem_mem>; + qcom,proxy-timeout-ms = <10000>; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x12>; + qcom,pas-id = <4>; + qcom,smem-id = <421>; + qcom,signal-aop; + qcom,minidump-id = <3>; + qcom,complete-ramdump; + + /* Inputs from mss */ + interrupts-extended = <&pdc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_NONE>, + <&modem_smp2p_in 1 IRQ_TYPE_NONE>, + <&modem_smp2p_in 2 IRQ_TYPE_NONE>, + <&modem_smp2p_in 3 IRQ_TYPE_NONE>, + <&modem_smp2p_in 7 IRQ_TYPE_NONE>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,err-ready", + "qcom,proxy-unvote", + "qcom,stop-ack", + "qcom,shutdown-ack"; + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "mss-pil"; + }; + + qcom,turing@8300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x8300000 0x100000>; + + qcom,pas-id = <18>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <601>; + qcom,sysmon-id = <7>; + qcom,ssctl-instance-id = <0x17>; + qcom,firmware-name = "cdsp"; + memory-region = <&pil_cdsp_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + + /* Inputs from turing */ + interrupts-extended = <&pdc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,err-ready", + "qcom,proxy-unvote", + "qcom,stop-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "cdsp-pil"; + }; + + qcom,msm-cdsp-loader { + compatible = "qcom,cdsp-loader"; + qcom,proc-img-to-load = "cdsp"; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + restrict-access; + }; + + qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,rpc-latency-us = <611>; + qcom,adsp-remoteheap-vmid = <22 37>; + qcom,fastrpc-adsp-audio-pdr; + qcom,fastrpc-adsp-sensors-pdr; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1401 0x20>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1402 0x20>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1403 0x20>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1404 0x20>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1405 0x20>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1406 0x20>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb7 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1407 0x20>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb8 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1408 0x20>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb9 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x1409 0x20>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb10 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1003 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb11 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1004 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb12 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1005 0x0>; + shared-cb = <5>; + dma-coherent; + }; + }; + + qcom,lpass@62400000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x62400000 0x00100>; + + qcom,pas-id = <1>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,sysmon-id = <1>; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + + /* Inputs from lpass */ + interrupts-extended = <&pdc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,err-ready", + "qcom,proxy-unvote", + "qcom,stop-ack"; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "adsp-pil"; + }; + + qcom,llcc@9200000 { + compatible = "qcom,llcc-core", "syscon", "simple-mfd"; + reg = <0x9200000 0x450000>; + reg-names = "llcc_base"; + qcom,llcc-banks-off = <0x0>; + qcom,llcc-broadcast-off = <0x400000>; + + llcc: qcom,atoll-llcc { + compatible = "qcom,atoll-llcc"; + #cache-cells = <1>; + max-slices = <32>; + cap-based-alloc-and-pwr-collapse; + }; + + qcom,llcc-erp { + compatible = "qcom,llcc-erp"; + }; + + qcom,llcc-amon { + compatible = "qcom,llcc-amon"; + }; + + LLCC_1: llcc_1_dcache { + qcom,dump-size = <0x6c000>; + }; + }; + + cpuss_dump { + compatible = "qcom,cpuss-dump"; + + qcom,l1_i_cache0 { + qcom,dump-node = <&L1_I_0>; + qcom,dump-id = <0x60>; + }; + + qcom,l1_i_cache100 { + qcom,dump-node = <&L1_I_100>; + qcom,dump-id = <0x61>; + }; + + qcom,l1_i_cache200 { + qcom,dump-node = <&L1_I_200>; + qcom,dump-id = <0x62>; + }; + + qcom,l1_i_cache300 { + qcom,dump-node = <&L1_I_300>; + qcom,dump-id = <0x63>; + }; + + qcom,l1_i_cache400 { + qcom,dump-node = <&L1_I_400>; + qcom,dump-id = <0x64>; + }; + + qcom,l1_i_cache500 { + qcom,dump-node = <&L1_I_500>; + qcom,dump-id = <0x65>; + }; + + qcom,l1_i_cache600 { + qcom,dump-node = <&L1_I_600>; + qcom,dump-id = <0x66>; + }; + + qcom,l1_i_cache700 { + qcom,dump-node = <&L1_I_700>; + qcom,dump-id = <0x67>; + }; + + qcom,l1_d_cache0 { + qcom,dump-node = <&L1_D_0>; + qcom,dump-id = <0x80>; + }; + + qcom,l1_d_cache100 { + qcom,dump-node = <&L1_D_100>; + qcom,dump-id = <0x81>; + }; + + qcom,l1_d_cache200 { + qcom,dump-node = <&L1_D_200>; + qcom,dump-id = <0x82>; + }; + + qcom,l1_d_cache300 { + qcom,dump-node = <&L1_D_300>; + qcom,dump-id = <0x83>; + }; + + qcom,l1_d_cache400 { + qcom,dump-node = <&L1_D_400>; + qcom,dump-id = <0x84>; + }; + + qcom,l1_d_cache500 { + qcom,dump-node = <&L1_D_500>; + qcom,dump-id = <0x85>; + }; + + qcom,l1_d_cache600 { + qcom,dump-node = <&L1_D_600>; + qcom,dump-id = <0x86>; + }; + + qcom,l1_d_cache700 { + qcom,dump-node = <&L1_D_700>; + qcom,dump-id = <0x87>; + }; + + qcom,l1_i_tlb_dump600 { + qcom,dump-node = <&L1_ITLB_600>; + qcom,dump-id = <0x26>; + }; + + qcom,l1_i_tlb_dump700 { + qcom,dump-node = <&L1_ITLB_700>; + qcom,dump-id = <0x27>; + }; + + qcom,l1_d_tlb_dump600 { + qcom,dump-node = <&L1_DTLB_600>; + qcom,dump-id = <0x46>; + }; + + qcom,l1_d_tlb_dump700 { + qcom,dump-node = <&L1_DTLB_700>; + qcom,dump-id = <0x47>; + }; + + qcom,l2_cache_dump600 { + qcom,dump-node = <&L2_600>; + qcom,dump-id = <0xc6>; + }; + + qcom,l2_cache_dump700 { + qcom,dump-node = <&L2_700>; + qcom,dump-id = <0xc7>; + }; + + qcom,l2_tlb_dump0 { + qcom,dump-node = <&L2_TLB_0>; + qcom,dump-id = <0x120>; + }; + + qcom,l2_tlb_dump100 { + qcom,dump-node = <&L2_TLB_100>; + qcom,dump-id = <0x121>; + }; + + qcom,l2_tlb_dump200 { + qcom,dump-node = <&L2_TLB_200>; + qcom,dump-id = <0x122>; + }; + + qcom,l2_tlb_dump300 { + qcom,dump-node = <&L2_TLB_300>; + qcom,dump-id = <0x123>; + }; + + qcom,l2_tlb_dump400 { + qcom,dump-node = <&L2_TLB_400>; + qcom,dump-id = <0x124>; + }; + + qcom,l2_tlb_dump500 { + qcom,dump-node = <&L2_TLB_500>; + qcom,dump-id = <0x125>; + }; + + qcom,l2_tlb_dump600 { + qcom,dump-node = <&L2_TLB_600>; + qcom,dump-id = <0x126>; + }; + + qcom,l2_tlb_dump700 { + qcom,dump-node = <&L2_TLB_700>; + qcom,dump-id = <0x127>; + }; + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + rpmh { + qcom,dump-size = <0x2000000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + etf_swao { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + etf_lpass { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf4>; + }; + + etflpass_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x104>; + }; + }; + + clock_rpmh: qcom,rpmh { + compatible = "qcom,dummycc"; + clock-output-names = "rpm_clocks"; + #clock-cells = <1>; + }; + + clock_aop: qcom,aopclk { + compatible = "qcom,dummycc"; + clock-output-names = "aop_clocks"; + #clock-cells = <1>; + }; + + clock_gcc: qcom,gcc { + compatible = "qcom,dummycc"; + clock-output-names = "gcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_camcc: qcom,camcc { + compatible = "qcom,dummycc"; + clock-output-names = "camcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_dispcc: qcom,dispcc { + compatible = "qcom,dummycc"; + clock-output-names = "dispcc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_gpucc: qcom,gpucc { + compatible = "qcom,dummycc"; + clock-output-names = "gpucc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_npucc: qcom,npucc { + compatible = "qcom,dummycc"; + clock-output-names = "npucc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_videocc: qcom,videocc { + compatible = "qcom,dummycc"; + clock-output-names = "videocc_clocks"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + tcsr_mutex_block: syscon@01F40000 { + compatible = "syscon"; + reg = <0x01F40000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 3>; + }; + + apcs_glb: mailbox@17C00000 { + compatible = "qcom,atoll-apcs-hmss-global"; + reg = <0x17C00000 0x10000>; + + #mbox-cells = <1>; + }; + + apcs_glb2: mailbox@17C00010 { + compatible = "qcom,atoll-apcs-hmss-ipc2"; + reg = <0x17C00010 0x4>; + + #mbox-cells = <1>; + }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_modem: modem { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&apcs_glb 12>; + mbox-names = "mpss_smem"; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 2>; + }; + + qcom,modem_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>, + <&glink_cdsp>; + }; + }; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&apcs_glb 8>; + mbox-names = "adsp_smem"; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,apr_tal_rpmsg { + qcom,glink-channels = "apr_audio_svc"; + qcom,intents = <0x200 20>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,adsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_cdsp>; + }; + }; + + glink_cdsp: cdsp { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&apcs_glb 4>; + mbox-names = "cdsp_smem"; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12>; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-latency-us = <44>; + qcom,qos-maxhold-ms = <20>; + #cooling-cells = <2>; + }; + + msm_hvx_rm: qcom,msm_hvx_rm { + compatible = "qcom,msm-hvx-rm"; + #cooling-cells = <2>; + }; + }; + + qcom,cdsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_npu>, + <&glink_adsp>; + }; + }; + + glink_npu: npu { + transport = "smem"; + qcom,remote-pid = <10>; + mboxes = <&apcs_glb2 4>; + mbox-names = "npu_smem"; + interrupts = ; + + label = "npu"; + qcom,glink-label = "npu"; + + qcom,npu_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,npu_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_cdsp>; + }; + }; + + glink_spi_xprt_wdsp: wdsp { + transport = "spi"; + tx-descriptors = <0x12000 0x12004>; + rx-descriptors = <0x1200c 0x12010>; + + label = "wdsp"; + qcom,glink-label = "wdsp"; + + qcom,wdsp_ctrl { + qcom,glink-channels = "g_glink_ctrl"; + qcom,intents = <0x400 1>; + }; + + qcom,wdsp_ild { + qcom,glink-channels = + "g_glink_persistent_data_ild"; + }; + + qcom,wdsp_nild { + qcom,glink-channels = + "g_glink_persistent_data_nild"; + }; + + qcom,wdsp_data { + qcom,glink-channels = "g_glink_audio_data"; + qcom,intents = <0x1000 2>; + }; + + qcom,diag_data { + qcom,glink-channels = "DIAG_DATA"; + qcom,intents = <0x4000 2>; + }; + + qcom,diag_ctrl { + qcom,glink-channels = "DIAG_CTRL"; + qcom,intents = <0x4000 1>; + }; + + qcom,diag_cmd { + qcom,glink-channels = "DIAG_CMD"; + qcom,intents = <0x4000 1 >; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + interrupt-parent = <&sleepstate_smp2p_in>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + mboxes = <&apcs_glb 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = ; + mboxes = <&apcs_glb 10>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts = ; + mboxes = <&apcs_glb 6>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-npu { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupts = ; + mboxes = <&apcs_glb2 6>; + qcom,local-pid = <0>; + qcom,remote-pid = <10>; + + npu_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + npu_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qmp_aop: qcom,qmp-aop@c300000 { + compatible = "qcom,qmp-mbox"; + reg = <0xc300000 0x1000>, <0x17c0000C 0x4>; + reg-names = "msgram", "irq-reg-base"; + qcom,irq-mask = <0x1>; + interrupts = ; + + label = "aop"; + qcom,early-boot; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; + + spmi_bus: qcom,spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0x1100>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>, + <0xe700000 0xa0000>, + <0xc40a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + qcom,ipa-platform-type-msm; + qcom,ipa-advertise-sg-support; + qcom,ipa-napi-enable; + }; + + ipa_hw: qcom,ipa@1e00000 { + compatible = "qcom,ipa"; + reg = <0x1e00000 0x34000>, + <0x1e04000 0x2c000>; + reg-names = "ipa-base", "gsi-base"; + interrupts = <0 311 0>, <0 432 0>; + interrupt-names = "ipa-irq", "gsi-irq"; + qcom,ipa-hw-ver = <16>; /* IPA core version = IPAv4.2 */ + qcom,ipa-hw-mode = <0>; + qcom,ee = <0>; + qcom,use-ipa-tethering-bridge; + qcom,modem-cfg-emb-pipe-flt; + qcom,ipa-wdi2; + qcom,ipa-wdi2_over_gsi; + qcom,ipa-fltrt-not-hashable; + qcom,ipa-endp-delay-wa; + qcom,use-64-bit-dma-mask; + qcom,arm-smmu; + qcom,smmu-fast-map; + qcom,use-ipa-pm; + qcom,bandwidth-vote-for-ipa; + qcom,msm-bus,name = "ipa"; + qcom,msm-bus,num-cases = <5>; + qcom,msm-bus,num-paths = <4>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + , + , + , + , + /* SVS2 */ + , + , + , + , + /* SVS */ + , + , + , + , + /* NOMINAL */ + , + , + , + , + /* TURBO */ + , + , + , + ; + qcom,bus-vector-names = + "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; + qcom,throughput-threshold = <310 600 1000>; + qcom,scaling-exceptions = <>; + + /* smp2p information */ + qcom,smp2p_map_ipa_1_out { + compatible = "qcom,smp2p-map-ipa-1-out"; + qcom,smem-states = <&smp2p_ipa_1_out 0>; + qcom,smem-state-names = "ipa-smp2p-out"; + }; + + qcom,smp2p_map_ipa_1_in { + compatible = "qcom,smp2p-map-ipa-1-in"; + interrupts-extended = <&smp2p_ipa_1_in 0 0>; + interrupt-names = "ipa-smp2p-in"; + }; + }; + + ipa_smmu_ap: ipa_smmu_ap { + compatible = "qcom,ipa-smmu-ap-cb"; + qcom,smmu-s1-bypass; + iommus = <&apps_smmu 0x0440 0x0>; + qcom,iova-mapping = <0x20000000 0x40000000>; + /* modem tables in IMEM */ + qcom,additional-mapping = <0x146A8000 0x146A8000 0x2000>; + }; + + ipa_smmu_wlan: ipa_smmu_wlan { + compatible = "qcom,ipa-smmu-wlan-cb"; + qcom,smmu-s1-bypass; + iommus = <&apps_smmu 0x0441 0x0>; + /* ipa-uc ram */ + qcom,additional-mapping = <0x1e60000 0x1e60000 0x80000>; + }; + + ipa_smmu_uc: ipa_smmu_uc { + compatible = "qcom,ipa-smmu-uc-cb"; + qcom,smmu-s1-bypass; + iommus = <&apps_smmu 0x0442 0x0>; + qcom,iova-mapping = <0x40400000 0x1fc00000>; + }; + + qcom,ipa_fws { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0xf>; + qcom,firmware-name = "ipa_fws"; + qcom,pil-force-shutdown; + memory-region = <&pil_ipa_fw_mem>; + }; + + apps_rsc: mailbox@18220000 { + compatible = "qcom,tcs-drv"; + label = "apps_rsc"; + reg = <0x18220000 0x100>, <0x18220d00 0x3000>; + interrupts = <0 5 0>; + #mbox-cells = <1>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + }; + + sdhc_1: sdhci@7c4000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>; + reg-names = "hc_mem", "cmdq_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <8>; + qcom,large-address-bus; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 + 192000000 384000000>; + qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; + + qcom,devfreq,freq-table = <50000000 200000000>; + + clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, + <&clock_gcc GCC_SDCC1_APPS_CLK>, + <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface_clk", "core_clk", "ice_core_clk"; + + qcom,ice-clk-rates = <300000000 100000000>; + + qcom,scaling-lower-bus-speed-mode = "DDR52"; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x000F642C 0x0 0x0 0x00010800 0x80040868>; + + qcom,nonremovable; + status = "disabled"; + }; + + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x8804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <4>; + qcom,large-address-bus; + + qcom,clk-rates = <400000 20000000 25000000 + 50000000 100000000 202000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", + "SDR104"; + + qcom,devfreq,freq-table = <50000000 202000000>; + + clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>, + <&clock_gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface_clk", "core_clk"; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642C 0x0 0x0 0x00010800 0x80040868>; + + status = "disabled"; + }; + + ufsphy_mem: ufsphy_mem@1d87000 { + reg = <0x1d87000 0xddc>; /* PHY regs */ + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <1>; + + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>, + <&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x3000>; + interrupts = <0 265 0>; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + + lanes-per-direction = <1>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + spm-level = <5>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks = + <&clock_gcc GCC_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_UFS_PHY_AHB_CLK>, + <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + + qcom,msm-bus,name = "ufshc_mem"; + qcom,msm-bus,num-cases = <12>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <123 512 0 0>, <1 757 0 0>, /* No vote */ + <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */ + <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */ + <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */ + <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */ + <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */ + <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */ + <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */ + <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */ + <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */ + <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */ + <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", + "MAX"; + + /* PM QoS */ + qcom,pm-qos-cpu-groups = <0x3f 0xC0>; + qcom,pm-qos-cpu-group-latency-us = <67 67>; + qcom,pm-qos-default-cpu = <0>; + + pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; + pinctrl-0 = <&ufs_dev_reset_assert>; + pinctrl-1 = <&ufs_dev_reset_deassert>; + + resets = <&clock_gcc GCC_UFS_PHY_BCR>; + reset-names = "core_reset"; + non-removable; + + status = "disabled"; + }; + + disp_rsc: mailbox@af20000 { + compatible = "qcom,tcs-drv"; + label = "display_rsc"; + reg = <0xaf20000 0x100>, <0xaf21c00 0x3000>; + interrupts = <0 129 0>; + #mbox-cells = <1>; + qcom,drv-id = <0>; + qcom,tcs-config = , + , + , + ; + }; + + system_pm { + compatible = "qcom,system-pm"; + mboxes = <&apps_rsc 0>; + }; + + cmd_db: qcom,cmd-db@c3f000c { + compatible = "qcom,cmd-db"; + reg = <0xc3f000c 8>; + }; + + thermal_zones: thermal-zones {}; + + tsens0: tsens@c222000 { + compatible = "qcom,tsens24xx"; + reg = <0xc222000 0x8>, + <0xc263000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts = <0 506 0>, <0 508 0>; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: tsens@c223000 { + compatible = "qcom,tsens24xx"; + reg = <0xc223000 0x8>, + <0xc265000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts = <0 507 0>, <0 509 0>; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + #thermal-sensor-cells = <1>; + }; + + qcom,venus@aae0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xaae0000 0x4000>; + + vdd-supply = <&venus_gdsc>; + qcom,proxy-reg-names = "vdd"; + + clocks = <&clock_videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, + <&clock_videocc VIDEO_CC_VENUS_AHB_CLK>, + <&clock_videocc VIDEO_CC_VENUS_CTL_AXI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_clk"; + qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk"; + + qcom,pas-id = <9>; + qcom,msm-bus,name = "pil-venus"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <63 512 0 0>, + <63 512 0 304000>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&pil_video_mem>; + }; +}; + +#include "atoll-gdsc.dtsi" +#include "atoll-ion.dtsi" +#include "msm-arm-smmu-atoll.dtsi" +#include "atoll-qupv3.dtsi" +#include "sdmmagpie-gpu.dtsi" + +&msm_gpu { + /delete-property/qcom,gpu-speed-bin; +}; + +&ufs_phy_gdsc { + status = "ok"; +}; + +&usb30_prim_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc { + status = "ok"; +}; + +&bps_gdsc { + status = "ok"; +}; + +&ipe_0_gdsc { + status = "ok"; +}; + +&ife_0_gdsc { + status = "ok"; +}; + +&ife_1_gdsc { + status = "ok"; +}; + +&titan_top_gdsc { + status = "ok"; +}; + +&mdss_core_gdsc { + status = "ok"; +}; + +&gpu_cx_gdsc { + status = "ok"; +}; + +&gpu_gx_gdsc { + status = "ok"; +}; + +&vcodec0_gdsc { + status = "ok"; +}; + +&venus_gdsc { + status = "ok"; +}; + +&npu_core_gdsc { + status = "ok"; +}; + +&qupv3_se8_2uart { + status = "ok"; +}; + +#include "pm6150.dtsi" +#include "pm6150l.dtsi" +#include "atoll-pinctrl.dtsi" +#include "atoll-pm.dtsi" +#include "atoll-coresight.dtsi" +#include "atoll-stub-regulator.dtsi" +#include "atoll-usb.dtsi" +#include "atoll-vidc.dtsi" + +&usb0 { + extcon = <&pm6150_pdphy>, <&pm6150_charger>; +}; + +&usb_qmp_dp_phy { + extcon = <&pm6150_pdphy>; +}; + +&pm6150_vadc { + pinctrl-names = "default"; + pinctrl-0 = <&nvm_therm_default &sdm_skin_therm_default>; + + chg_skin_therm { + reg = ; + label = "chg_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + nvm_therm { + reg = ; + label = "nvm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + sdm_skin_therm { + reg = ; + label = "sdm_skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm6150_gpios { + nvm_therm { + nvm_therm_default: nvm_therm_default { + pins = "gpio1"; + bias-high-impedance; + }; + }; + + sdm_skin_therm { + sdm_skin_therm_default: sdm_skin_therm_default { + pins = "gpio8"; + bias-high-impedance; + }; + }; +}; + +&pm6150_adc_tm { + io-channels = <&pm6150_vadc ADC_XO_THERM_PU2>, + <&pm6150_vadc ADC_AMUX_THM1_PU2>, + <&pm6150_vadc ADC_GPIO1_PU2>, + <&pm6150_vadc ADC_GPIO2_PU2>; + + /* Channel nodes */ + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + chg_skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + nvm_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + sdm_skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm6150l_vadc { + pinctrl-names = "default"; + pinctrl-0 = <&camera_flash_therm_default>; + + quiet_therm { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm0 { + reg = ; + label = "pa_therm0"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + camera_flash_therm { + reg = ; + label = "camera_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm6150l_gpios { + camera_flash_therm { + camera_flash_therm_default: camera_flash_therm_default { + pins = "gpio5"; + bias-high-impedance; + }; + }; +}; + +&pm6150l_adc_tm { + io-channels = <&pm6150l_vadc ADC_AMUX_THM1_PU2>, + <&pm6150l_vadc ADC_AMUX_THM2_PU2>, + <&pm6150l_vadc ADC_GPIO1_PU2>; + + /* Channel nodes */ + quiet_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm0 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + camera_flash_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +#include "atoll-thermal.dtsi" diff --git a/arch/arm/boot/dts/qcom/dm-verity-boot.dtsi b/arch/arm/boot/dts/qcom/dm-verity-boot.dtsi new file mode 100644 index 000000000000..3aee6a4295f9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dm-verity-boot.dtsi @@ -0,0 +1,28 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +dm_verity { + dmname="disabled"; + version="1"; + data_device="/dev/sda6"; + hash_device="/dev/sda6"; + data_block_size="4096"; + hash_block_size="4096"; + number_of_data_blocks="262144"; + hash_start_block="262145"; + algorithm="sha256"; + // root hash: 64 bytes long + digest= + "b0fe12d7da6e23a1e19b5a69252c7aaf7b249191eb13bba3f566d630b3f2828a"; + salt="a2df040e00f02c3b2a19e90e5aa76fe1a303f4e08584aaf40e87f088a32b7709"; + // restart_on_corruption ignore_corruption ignore_zero_blocks + opt="restart_on_corruption"; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-ext-bridge-1080p.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-ext-bridge-1080p.dtsi new file mode 100644 index 000000000000..9347de7ecc7a --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-ext-bridge-1080p.dtsi @@ -0,0 +1,52 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_ext_bridge_1080p: qcom,mdss_dsi_ext_bridge_1080p { + qcom,mdss-dsi-panel-name = "ext video mode dsi bridge"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-t-clk-post = <0x03>; + qcom,mdss-dsi-t-clk-pre = <0x24>; + qcom,mdss-dsi-force-clock-lane-hs; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1920>; + qcom,mdss-dsi-panel-height = <1080>; + qcom,mdss-dsi-h-front-porch = <88>; + qcom,mdss-dsi-h-back-porch = <148>; + qcom,mdss-dsi-h-pulse-width = <44>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <36>; + qcom,mdss-dsi-v-front-porch = <4>; + qcom,mdss-dsi-v-pulse-width = <5>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-ext-bridge-hdmi-1080p.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-ext-bridge-hdmi-1080p.dtsi new file mode 100644 index 000000000000..ed9398f1cae6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-ext-bridge-hdmi-1080p.dtsi @@ -0,0 +1,52 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_ext_bridge_hdmi_1080p: qcom,mdss_dsi_ext_bridge_hdmi_1080p { + qcom,mdss-dsi-panel-name = "ext bridge video mode hdmi 1080p"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-t-clk-post = <0x18>; + qcom,mdss-dsi-t-clk-pre = <0x1b>; + qcom,mdss-dsi-force-clock-lane-hs; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1920>; + qcom,mdss-dsi-panel-height = <1080>; + qcom,mdss-dsi-h-front-porch = <88>; + qcom,mdss-dsi-h-back-porch = <148>; + qcom,mdss-dsi-h-pulse-width = <44>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <36>; + qcom,mdss-dsi-v-front-porch = <4>; + qcom,mdss-dsi-v-pulse-width = <5>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi new file mode 100644 index 000000000000..817b26fe1da2 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi @@ -0,0 +1,159 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_hx83112a_truly_video: qcom,mdss_dsi_hx83112a_truly_video { + qcom,mdss-dsi-panel-name = + "hx83112a video mode dsi truly panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <65>; + qcom,mdss-pan-physical-height-dimension = <129>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2160>; + qcom,mdss-dsi-h-front-porch = <42>; + qcom,mdss-dsi-h-back-porch = <42>; + qcom,mdss-dsi-h-pulse-width = <10>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <15>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <3>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 04 B9 83 11 2A + 39 01 00 00 00 00 09 B1 08 29 29 00 00 4F 54 + 33 + 39 01 00 00 00 00 11 B2 00 02 00 80 70 00 08 + 26 FC 01 00 03 15 A3 87 09 + 39 01 00 00 00 00 02 BD 02 + 39 01 00 00 00 00 02 BD 00 + 39 01 00 00 00 00 03 D2 2C 2C + 39 01 00 00 00 00 1C B4 01 CE 01 CE 01 CE 0A + CE 0A CE 0A CE 00 FF 00 FF 00 00 22 23 00 + 28 0A 13 14 00 8A + 39 01 00 00 00 00 02 BD 02 + 39 01 00 00 00 00 0A B4 00 92 12 22 88 12 12 + 00 53 + 39 01 00 00 00 00 02 BD 00 + 39 01 00 00 00 00 04 B6 82 82 E3 + 39 01 00 00 00 00 02 CC 08 + 39 01 00 00 00 00 2B D3 40 00 00 00 00 01 01 + 0A 0A 07 07 00 08 09 09 09 09 32 10 09 00 + 09 32 21 0A 00 0A 32 10 08 00 00 00 00 00 + 00 00 00 00 0B 08 82 + 39 01 00 00 00 00 02 BD 01 + 39 01 00 00 00 00 09 D3 00 00 19 00 00 0A 00 + 81 + 39 01 00 00 00 00 02 BD 00 + 39 01 00 00 00 00 31 D5 18 18 18 18 18 18 18 + 18 31 31 30 30 2F 2F 31 31 30 30 2F 2F C0 + 18 40 40 01 00 07 06 05 04 03 02 21 20 18 + 18 19 19 18 18 03 03 18 18 18 18 18 18 + 39 01 00 00 00 00 31 D6 18 18 18 18 18 18 18 + 18 31 31 30 30 2F 2F 31 31 30 30 2F 2F C0 + 18 40 40 02 03 04 05 06 07 00 01 20 21 18 + 18 18 18 19 19 20 20 18 18 18 18 18 18 + 39 01 00 00 00 00 19 D8 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 + 39 01 00 00 00 00 02 BD 01 + 39 01 00 00 00 00 19 D8 AA AA AA AA AA AA AA + AA AA AA AA AA AA AA AA AA AA AA AA AA AA + AA AA AA + 39 01 00 00 00 00 02 BD 02 + 39 01 00 00 00 00 0D D8 AF FF FA AA BA AA AA + FF FA AA BA AA + 39 01 00 00 00 00 02 BD 03 + 39 01 00 00 00 00 19 D8 AA AA AA AA AA AA AA + AA AA AA AA AA AA AA AA AA AA AA AA AA AA + AA AA AA + 39 01 00 00 00 00 02 BD 00 + 39 01 00 00 00 00 18 E7 0E 0E 1E 6A 1D 6A 00 + 32 02 02 00 00 02 02 02 05 14 14 32 B9 23 + B9 08 + 39 01 00 00 00 00 02 BD 01 + 39 01 00 00 00 00 0A E7 02 00 98 01 9A 0D A8 + 0E 01 + 39 01 00 00 00 00 02 BD 02 + 39 01 00 00 00 00 1E E7 00 00 08 00 01 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 04 00 00 00 00 02 00 + 39 01 00 00 00 00 02 BD 00 + 39 01 00 00 00 00 02 C1 01 + 39 01 00 00 00 00 02 BD 01 + 39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4 + C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74 + 6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22 + 1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54 + C6 B8 9C 37 43 3D E5 00 + 39 01 00 00 00 00 02 BD 02 + 39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4 + C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74 + 6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22 + 1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54 + C6 B8 9C 37 43 3D E5 00 + 39 01 00 00 00 00 02 BD 03 + 39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4 + C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74 + 6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22 + 1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54 + C6 B8 9C 37 43 3D E5 00 + 39 01 00 00 00 00 02 BD 00 + 39 01 00 00 00 00 02 E9 C3 + 39 01 00 00 00 00 03 CB 92 01 + 39 01 00 00 00 00 02 E9 3F + 39 01 00 00 00 00 07 C7 70 00 04 E0 33 00 + 39 01 00 00 00 00 03 51 0F FF + 39 01 00 00 00 00 02 53 24 + 39 01 00 00 00 00 02 55 00 + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 96 00 02 11 00 + 05 01 00 00 32 00 02 29 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 32 00 02 28 00 + 05 01 00 00 96 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-hx8394d-720p-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-hx8394d-720p-video.dtsi new file mode 100644 index 000000000000..094ac1035ac3 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-hx8394d-720p-video.dtsi @@ -0,0 +1,99 @@ +/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_hx8394d_720_vid: qcom,mdss_dsi_hx8394d_720p_video { + qcom,mdss-dsi-panel-name = "hx8394d 720p video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <52>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <24>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 04 b9 ff 83 94 + 39 01 00 00 00 00 03 ba 33 83 + 39 01 00 00 00 00 10 b1 6c 12 12 + 37 04 11 f1 80 ec 94 23 80 c0 + d2 18 + 39 01 00 00 00 00 0c b2 00 64 0e + 0d 32 23 08 08 1c 4d 00 + 39 01 00 00 00 00 0d b4 00 ff 03 + 50 03 50 03 50 01 6a 01 6a + 39 01 00 00 00 00 02 bc 07 + 39 01 00 00 00 00 04 bf 41 0e 01 + 39 01 00 00 00 00 1f d3 00 07 00 + 00 00 10 00 32 10 05 00 00 32 + 10 00 00 00 32 10 00 00 00 36 + 03 09 09 37 00 00 37 + 39 01 00 00 00 00 2d d5 02 03 00 + 01 06 07 04 05 20 21 22 23 18 + 18 18 18 18 18 18 18 18 18 18 + 18 18 18 18 18 18 18 18 18 18 + 18 18 18 18 18 24 25 18 18 19 + 19 + 39 01 00 00 00 00 2d d6 05 04 07 + 06 01 00 03 02 23 22 21 20 18 + 18 18 18 18 18 58 58 18 18 18 + 18 18 18 18 18 18 18 18 18 18 + 18 18 18 18 18 25 24 19 19 18 + 18 + 39 01 00 00 00 00 02 cc 09 + 39 01 00 00 00 00 03 c0 30 14 + 39 01 00 00 00 00 05 c7 00 c0 40 c0 + 39 01 00 00 00 00 03 b6 43 43 + 05 01 00 00 c8 00 02 11 00 + 05 01 00 00 0a 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <1>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-panel-timings = [ + 79 1a 12 00 3e 42 + 16 1e 15 03 04 00 + ]; + qcom,mdss-dsi-t-clk-post = <0x04>; + qcom,mdss-dsi-t-clk-pre = <0x1b>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>; + qcom,mdss-pan-physical-width-dimension = <59>; + qcom,mdss-pan-physical-height-dimension = <104>; + + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi new file mode 100644 index 000000000000..0ca117567478 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi @@ -0,0 +1,247 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_nt35597_truly_dsc_cmd: qcom,mdss_dsi_nt35597_dsc_cmd_truly { + qcom,mdss-dsi-panel-name = + "nt35597 cmd mode dsi truly panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-pan-physical-width-dimension = <74>; + qcom,mdss-pan-physical-height-dimension = <131>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x1 0x1>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1e + 15 01 00 00 00 00 02 0b 73 + 15 01 00 00 00 00 02 0c 73 + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f ae + 15 01 00 00 00 00 02 11 b8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5a 00 + 15 01 00 00 00 00 02 5b 01 + 15 01 00 00 00 00 02 5c 80 + 15 01 00 00 00 00 02 5d 81 + 15 01 00 00 00 00 02 5e 00 + 15 01 00 00 00 00 02 5f 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1c + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0f + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8a + 15 01 00 00 00 00 02 0a 13 + 15 01 00 00 00 00 02 0b 13 + 15 01 00 00 00 00 02 0c 15 + 15 01 00 00 00 00 02 0d 15 + 15 01 00 00 00 00 02 0e 17 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 1c + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0f + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8a + 15 01 00 00 00 00 02 1a 13 + 15 01 00 00 00 00 02 1b 13 + 15 01 00 00 00 00 02 1c 15 + 15 01 00 00 00 00 02 1d 15 + 15 01 00 00 00 00 02 1e 17 + 15 01 00 00 00 00 02 1f 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 e0 00 + 15 01 00 00 00 00 02 dc 21 + 15 01 00 00 00 00 02 dd 22 + 15 01 00 00 00 00 02 de 07 + 15 01 00 00 00 00 02 df 07 + 15 01 00 00 00 00 02 e3 6D + 15 01 00 00 00 00 02 e1 07 + 15 01 00 00 00 00 02 e2 07 + /* UD */ + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + /* CLK */ + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c D8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 7f 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 b3 C0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0a + 15 01 00 00 00 00 02 94 0a + /* Inversion Type */ + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b ff + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9d b0 + 15 01 00 00 00 00 02 9f 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 ec 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VESA DSC PPS settings + * (1440x2560 slide 16H) + */ + 39 01 00 00 00 00 11 c1 09 + 20 00 10 02 00 02 68 01 bb + 00 0a 06 67 04 c5 + + 39 01 00 00 00 00 03 c2 10 f0 + /* C0h = 0x0(2 Port SDC) + * 0x01(1 PortA FBC) + * 0x02(MTK) 0x03(1 PortA VESA) + */ + 15 01 00 00 00 00 02 c0 03 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3b 03 0a 0a + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 e5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 bb 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 fb 01 + /* SlpOut + DispOn */ + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi new file mode 100644 index 000000000000..50adcde6e596 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi @@ -0,0 +1,233 @@ +/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_nt35597_truly_dsc_video: qcom,mdss_dsi_nt35597_dsc_video_truly { + qcom,mdss-dsi-panel-name = + "nt35597 video mode dsi truly panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <74>; + qcom,mdss-pan-physical-height-dimension = <131>; + qcom,mdss-dsi-dma-schedule-line = <5>; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1e + 15 01 00 00 00 00 02 0b 73 + 15 01 00 00 00 00 02 0c 73 + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f aE + 15 01 00 00 00 00 02 11 b8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5a 00 + 15 01 00 00 00 00 02 5b 01 + 15 01 00 00 00 00 02 5c 80 + 15 01 00 00 00 00 02 5d 81 + 15 01 00 00 00 00 02 5e 00 + 15 01 00 00 00 00 02 5f 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1c + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0f + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8a + 15 01 00 00 00 00 02 0a 13 + 15 01 00 00 00 00 02 0b 13 + 15 01 00 00 00 00 02 0c 15 + 15 01 00 00 00 00 02 0d 15 + 15 01 00 00 00 00 02 0e 17 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 1c + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0f + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8a + 15 01 00 00 00 00 02 1a 13 + 15 01 00 00 00 00 02 1b 13 + 15 01 00 00 00 00 02 1c 15 + 15 01 00 00 00 00 02 1d 15 + 15 01 00 00 00 00 02 1e 17 + 15 01 00 00 00 00 02 1f 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 e0 00 + 15 01 00 00 00 00 02 dc 21 + 15 01 00 00 00 00 02 dd 22 + 15 01 00 00 00 00 02 de 07 + 15 01 00 00 00 00 02 df 07 + 15 01 00 00 00 00 02 e3 6d + 15 01 00 00 00 00 02 e1 07 + 15 01 00 00 00 00 02 e2 07 + /* UD */ + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + /* CLK */ + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 7f 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0a + 15 01 00 00 00 00 02 94 0a + /* Inversion Type */ + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b ff + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9d b0 + 15 01 00 00 00 00 02 9f 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 ec 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VESA DSC PPS settings + * (1440x2560 slide 16H) + */ + 39 01 00 00 00 00 11 c1 09 + 20 00 10 02 00 02 68 01 bb + 00 0a 06 67 04 c5 + + 39 01 00 00 00 00 03 c2 10 f0 + /* C0h = 0x00(2 Port SDC); + * 0x01(1 PortA FBC); + * 0x02(MTK); 0x03(1 PortA VESA) + */ + 15 01 00 00 00 00 02 c0 03 + /* VBP+VSA=,VFP = 10H */ + 39 01 00 00 00 00 04 3b 03 0a 0a + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 e5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 bb 03 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 fb 01 + /* SlpOut + DispOn */ + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi new file mode 100644 index 000000000000..87cabae99e91 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi @@ -0,0 +1,226 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_dual_nt35597_truly_cmd: qcom,mdss_dsi_nt35597_truly_wqxga_cmd{ + qcom,mdss-dsi-panel-name = + "Dual nt35597 cmd mode dsi truly panel without DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <74>; + qcom,mdss-pan-physical-height-dimension = <131>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-jitter = <0x1 0x1>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 FF 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1E + 15 01 00 00 00 00 02 0B 73 + 15 01 00 00 00 00 02 0C 73 + 15 01 00 00 00 00 02 0E B0 + 15 01 00 00 00 00 02 0F AE + 15 01 00 00 00 00 02 11 B8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5A 00 + 15 01 00 00 00 00 02 5B 01 + 15 01 00 00 00 00 02 5C 80 + 15 01 00 00 00 00 02 5D 81 + 15 01 00 00 00 00 02 5E 00 + 15 01 00 00 00 00 02 5F 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1C + 15 01 00 00 00 00 02 01 0B + 15 01 00 00 00 00 02 02 0C + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0F + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8A + 15 01 00 00 00 00 02 0A 13 + 15 01 00 00 00 00 02 0B 13 + 15 01 00 00 00 00 02 0C 15 + 15 01 00 00 00 00 02 0D 15 + 15 01 00 00 00 00 02 0E 17 + 15 01 00 00 00 00 02 0F 17 + 15 01 00 00 00 00 02 10 1C + 15 01 00 00 00 00 02 11 0B + 15 01 00 00 00 00 02 12 0C + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0F + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8A + 15 01 00 00 00 00 02 1A 13 + 15 01 00 00 00 00 02 1B 13 + 15 01 00 00 00 00 02 1C 15 + 15 01 00 00 00 00 02 1D 15 + 15 01 00 00 00 00 02 1E 17 + 15 01 00 00 00 00 02 1F 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6D + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 E0 00 + 15 01 00 00 00 00 02 DC 21 + 15 01 00 00 00 00 02 DD 22 + 15 01 00 00 00 00 02 DE 07 + 15 01 00 00 00 00 02 DF 07 + 15 01 00 00 00 00 02 E3 6D + 15 01 00 00 00 00 02 E1 07 + 15 01 00 00 00 00 02 E2 07 + /* UD */ + 15 01 00 00 00 00 02 29 D8 + 15 01 00 00 00 00 02 2A 2A + /* CLK */ + 15 01 00 00 00 00 02 4B 03 + 15 01 00 00 00 00 02 4C 11 + 15 01 00 00 00 00 02 4D 10 + 15 01 00 00 00 00 02 4E 01 + 15 01 00 00 00 00 02 4F 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5B 43 + 15 01 00 00 00 00 02 5C 00 + 15 01 00 00 00 00 02 5F 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7A 80 + 15 01 00 00 00 00 02 7B 91 + 15 01 00 00 00 00 02 7C D8 + 15 01 00 00 00 00 02 7D 60 + 15 01 00 00 00 00 02 7F 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 B3 C0 + 15 01 00 00 00 00 02 B4 00 + 15 01 00 00 00 00 02 B5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0A + 15 01 00 00 00 00 02 94 0A + /* Inversion Type */ + 15 01 00 00 00 00 02 8A 00 + 15 01 00 00 00 00 02 9B FF + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9D B0 + 15 01 00 00 00 00 02 9F 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 EC 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3B 03 0A 0A + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 E5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 BB 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 FB 01 + /* SlpOut + DispOn */ + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi new file mode 100644 index 000000000000..c83fd8735604 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi @@ -0,0 +1,213 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_dual_nt35597_truly_video: qcom,mdss_dsi_nt35597_wqxga_video_truly { + qcom,mdss-dsi-panel-name = + "Dual nt35597 video mode dsi truly panel without DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 50>; + qcom,mdss-pan-physical-width-dimension = <74>; + qcom,mdss-pan-physical-height-dimension = <131>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-underflow-color = <0x3ff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-bpp = <24>; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 FF 20 + 15 01 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1E + 15 01 00 00 00 00 02 0B 73 + 15 01 00 00 00 00 02 0C 73 + 15 01 00 00 00 00 02 0E B0 + 15 01 00 00 00 00 02 0F AE + 15 01 00 00 00 00 02 11 B8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5A 00 + 15 01 00 00 00 00 02 5B 01 + 15 01 00 00 00 00 02 5C 80 + 15 01 00 00 00 00 02 5D 81 + 15 01 00 00 00 00 02 5E 00 + 15 01 00 00 00 00 02 5F 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 FF 24 + 15 01 00 00 00 00 02 FB 01 + 15 01 00 00 00 00 02 00 1C + 15 01 00 00 00 00 02 01 0B + 15 01 00 00 00 00 02 02 0C + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0F + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8A + 15 01 00 00 00 00 02 0A 13 + 15 01 00 00 00 00 02 0B 13 + 15 01 00 00 00 00 02 0C 15 + 15 01 00 00 00 00 02 0D 15 + 15 01 00 00 00 00 02 0E 17 + 15 01 00 00 00 00 02 0F 17 + 15 01 00 00 00 00 02 10 1C + 15 01 00 00 00 00 02 11 0B + 15 01 00 00 00 00 02 12 0C + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0F + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8A + 15 01 00 00 00 00 02 1A 13 + 15 01 00 00 00 00 02 1B 13 + 15 01 00 00 00 00 02 1C 15 + 15 01 00 00 00 00 02 1D 15 + 15 01 00 00 00 00 02 1E 17 + 15 01 00 00 00 00 02 1F 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6D + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 E0 00 + 15 01 00 00 00 00 02 DC 21 + 15 01 00 00 00 00 02 DD 22 + 15 01 00 00 00 00 02 DE 07 + 15 01 00 00 00 00 02 DF 07 + 15 01 00 00 00 00 02 E3 6D + 15 01 00 00 00 00 02 E1 07 + 15 01 00 00 00 00 02 E2 07 + /* UD */ + 15 01 00 00 00 00 02 29 D8 + 15 01 00 00 00 00 02 2A 2A + /* CLK */ + 15 01 00 00 00 00 02 4B 03 + 15 01 00 00 00 00 02 4C 11 + 15 01 00 00 00 00 02 4D 10 + 15 01 00 00 00 00 02 4E 01 + 15 01 00 00 00 00 02 4F 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5B 43 + 15 01 00 00 00 00 02 5C 00 + 15 01 00 00 00 00 02 5F 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7A 80 + 15 01 00 00 00 00 02 7B 91 + 15 01 00 00 00 00 02 7C D8 + 15 01 00 00 00 00 02 7D 60 + 15 01 00 00 00 00 02 7F 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 B3 C0 + 15 01 00 00 00 00 02 B4 00 + 15 01 00 00 00 00 02 B5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0A + 15 01 00 00 00 00 02 94 0A + /* Inversion Type */ + 15 01 00 00 00 00 02 8A 00 + 15 01 00 00 00 00 02 9B FF + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9D B0 + 15 01 00 00 00 00 02 9F 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 EC 00 + /* CMD1 */ + 15 01 00 00 00 00 02 FF 10 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3B 03 0A 0A + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 E5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 BB 03 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 FB 01 + /* SlpOut + DispOn */ + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-nt35695b-truly-fhd-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-nt35695b-truly-fhd-cmd.dtsi new file mode 100644 index 000000000000..3ad438337dff --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-nt35695b-truly-fhd-cmd.dtsi @@ -0,0 +1,188 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_nt35695b_truly_fhd_cmd: qcom,mdss_dsi_nt35695b_truly_fhd_cmd { + qcom,mdss-dsi-panel-name = + "nt35695b truly fhd command mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-post-init-delay = <1>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <60>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <2>; + qcom,mdss-dsi-v-front-porch = <12>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = + [15 01 00 00 10 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 03 55 + 15 01 00 00 00 00 02 05 50 + 15 01 00 00 00 00 02 06 a8 + 15 01 00 00 00 00 02 07 ad + 15 01 00 00 00 00 02 08 0c + 15 01 00 00 00 00 02 0b aa + 15 01 00 00 00 00 02 0c aa + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f b3 + 15 01 00 00 00 00 02 11 28 + 15 01 00 00 00 00 02 12 10 + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 4a + 15 01 00 00 00 00 02 15 12 + 15 01 00 00 00 00 02 16 12 + 15 01 00 00 00 00 02 30 01 + 15 01 00 00 00 00 02 72 11 + 15 01 00 00 00 00 02 58 82 + 15 01 00 00 00 00 02 59 00 + 15 01 00 00 00 00 02 5a 02 + 15 01 00 00 00 00 02 5b 00 + 15 01 00 00 00 00 02 5c 82 + 15 01 00 00 00 00 02 5d 80 + 15 01 00 00 00 00 02 5e 02 + 15 01 00 00 00 00 02 5f 00 + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 89 + 15 01 00 00 00 00 02 04 8a + 15 01 00 00 00 00 02 05 0f + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 1c + 15 01 00 00 00 00 02 09 00 + 15 01 00 00 00 00 02 0a 00 + 15 01 00 00 00 00 02 0b 00 + 15 01 00 00 00 00 02 0c 00 + 15 01 00 00 00 00 02 0d 13 + 15 01 00 00 00 00 02 0e 15 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 01 + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 89 + 15 01 00 00 00 00 02 14 8a + 15 01 00 00 00 00 02 15 0f + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 1c + 15 01 00 00 00 00 02 19 00 + 15 01 00 00 00 00 02 1a 00 + 15 01 00 00 00 00 02 1b 00 + 15 01 00 00 00 00 02 1c 00 + 15 01 00 00 00 00 02 1d 13 + 15 01 00 00 00 00 02 1e 15 + 15 01 00 00 00 00 02 1f 17 + 15 01 00 00 00 00 02 20 00 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 55 25 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 93 06 + 15 01 00 00 00 00 02 94 06 + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b 0f + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + 15 01 00 00 00 00 02 b6 21 + 15 01 00 00 00 00 02 b7 22 + 15 01 00 00 00 00 02 b8 07 + 15 01 00 00 00 00 02 b9 07 + 15 01 00 00 00 00 02 ba 22 + 15 01 00 00 00 00 02 bd 20 + 15 01 00 00 00 00 02 be 07 + 15 01 00 00 00 00 02 bf 07 + 15 01 00 00 00 00 02 c1 6d + 15 01 00 00 00 00 02 c4 24 + 15 01 00 00 00 00 02 e3 00 + 15 01 00 00 00 00 02 ec 00 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 14 + 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-nt35695b-truly-fhd-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-nt35695b-truly-fhd-video.dtsi new file mode 100644 index 000000000000..aaf96b412e96 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-nt35695b-truly-fhd-video.dtsi @@ -0,0 +1,184 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_nt35695b_truly_fhd_video: qcom,mdss_dsi_nt35695b_truly_fhd_video { + qcom,mdss-dsi-panel-name = + "nt35695b truly fhd video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-post-init-delay = <1>; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <60>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-v-back-porch = <2>; + qcom,mdss-dsi-v-front-porch = <12>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = + [15 01 00 00 10 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 03 55 + 15 01 00 00 00 00 02 05 50 + 15 01 00 00 00 00 02 06 a8 + 15 01 00 00 00 00 02 07 ad + 15 01 00 00 00 00 02 08 0c + 15 01 00 00 00 00 02 0b aa + 15 01 00 00 00 00 02 0c aa + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f b3 + 15 01 00 00 00 00 02 11 28 + 15 01 00 00 00 00 02 12 10 + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 4a + 15 01 00 00 00 00 02 15 12 + 15 01 00 00 00 00 02 16 12 + 15 01 00 00 00 00 02 30 01 + 15 01 00 00 00 00 02 72 11 + 15 01 00 00 00 00 02 58 82 + 15 01 00 00 00 00 02 59 00 + 15 01 00 00 00 00 02 5a 02 + 15 01 00 00 00 00 02 5b 00 + 15 01 00 00 00 00 02 5c 82 + 15 01 00 00 00 00 02 5d 80 + 15 01 00 00 00 00 02 5e 02 + 15 01 00 00 00 00 02 5f 00 + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 89 + 15 01 00 00 00 00 02 04 8a + 15 01 00 00 00 00 02 05 0f + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 1c + 15 01 00 00 00 00 02 09 00 + 15 01 00 00 00 00 02 0a 00 + 15 01 00 00 00 00 02 0b 00 + 15 01 00 00 00 00 02 0c 00 + 15 01 00 00 00 00 02 0d 13 + 15 01 00 00 00 00 02 0e 15 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 01 + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 89 + 15 01 00 00 00 00 02 14 8a + 15 01 00 00 00 00 02 15 0f + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 1c + 15 01 00 00 00 00 02 19 00 + 15 01 00 00 00 00 02 1a 00 + 15 01 00 00 00 00 02 1b 00 + 15 01 00 00 00 00 02 1c 00 + 15 01 00 00 00 00 02 1d 13 + 15 01 00 00 00 00 02 1e 15 + 15 01 00 00 00 00 02 1f 17 + 15 01 00 00 00 00 02 20 00 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 55 25 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 93 06 + 15 01 00 00 00 00 02 94 06 + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b 0f + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + 15 01 00 00 00 00 02 b6 21 + 15 01 00 00 00 00 02 b7 22 + 15 01 00 00 00 00 02 b8 07 + 15 01 00 00 00 00 02 b9 07 + 15 01 00 00 00 00 02 ba 22 + 15 01 00 00 00 00 02 bd 20 + 15 01 00 00 00 00 02 be 07 + 15 01 00 00 00 00 02 bf 07 + 15 01 00 00 00 00 02 c1 6d + 15 01 00 00 00 00 02 c4 24 + 15 01 00 00 00 00 02 e3 00 + 15 01 00 00 00 00 02 ec 00 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 bb 03 + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 + 14 00 02 28 00 05 01 00 00 78 00 + 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-nt36672-truly-fhd-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-nt36672-truly-fhd-video.dtsi new file mode 100644 index 000000000000..c34131bf8f79 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-nt36672-truly-fhd-video.dtsi @@ -0,0 +1,282 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_nt36672_truly_video: qcom,mdss_dsi_nt36672_truly_video { + qcom,mdss-dsi-panel-name = + "nt36672 truly fhd video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-post-init-delay = <1>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2520>; + qcom,mdss-dsi-h-front-porch = <28>; + qcom,mdss-dsi-h-back-porch = <176>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <10>; + qcom,mdss-dsi-v-front-porch = <12>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 29 01 00 00 00 00 02 FF 10 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 FF 20 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 0E B0 + 29 01 00 00 00 00 02 0F AE + 29 01 00 00 00 00 02 62 93 + 29 01 00 00 00 00 02 6D 44 + 29 01 00 00 00 00 02 78 01 + 29 01 00 00 00 00 02 95 B9 + 29 01 00 00 00 00 02 96 B9 + 29 01 00 00 00 00 02 97 B9 + 29 01 00 00 00 00 02 98 B9 + 29 01 00 00 00 00 02 FF 24 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 00 1C + 29 01 00 00 00 00 02 01 1C + 29 01 00 00 00 00 02 02 1C + 29 01 00 00 00 00 02 03 1C + 29 01 00 00 00 00 02 04 20 + 29 01 00 00 00 00 02 05 00 + 29 01 00 00 00 00 02 06 09 + 29 01 00 00 00 00 02 07 0A + 29 01 00 00 00 00 02 08 1E + 29 01 00 00 00 00 02 09 0D + 29 01 00 00 00 00 02 0A 0D + 29 01 00 00 00 00 02 0B 25 + 29 01 00 00 00 00 02 0C 24 + 29 01 00 00 00 00 02 0D 01 + 29 01 00 00 00 00 02 0E 04 + 29 01 00 00 00 00 02 0F 04 + 29 01 00 00 00 00 02 10 03 + 29 01 00 00 00 00 02 11 03 + 29 01 00 00 00 00 02 12 14 + 29 01 00 00 00 00 02 13 14 + 29 01 00 00 00 00 02 14 12 + 29 01 00 00 00 00 02 15 12 + 29 01 00 00 00 00 02 16 10 + 29 01 00 00 00 00 02 17 1C + 29 01 00 00 00 00 02 18 1C + 29 01 00 00 00 00 02 19 1C + 29 01 00 00 00 00 02 1A 1C + 29 01 00 00 00 00 02 1B 20 + 29 01 00 00 00 00 02 1C 0D + 29 01 00 00 00 00 02 1D 09 + 29 01 00 00 00 00 02 1E 0A + 29 01 00 00 00 00 02 1F 1E + 29 01 00 00 00 00 02 20 0D + 29 01 00 00 00 00 02 21 0D + 29 01 00 00 00 00 02 22 25 + 29 01 00 00 00 00 02 23 24 + 29 01 00 00 00 00 02 24 01 + 29 01 00 00 00 00 02 25 04 + 29 01 00 00 00 00 02 26 04 + 29 01 00 00 00 00 02 27 03 + 29 01 00 00 00 00 02 28 03 + 29 01 00 00 00 00 02 29 14 + 29 01 00 00 00 00 02 2A 14 + 29 01 00 00 00 00 02 2B 12 + 29 01 00 00 00 00 02 2D 12 + 29 01 00 00 00 00 02 2F 10 + 29 01 00 00 00 00 02 31 02 + 29 01 00 00 00 00 02 32 03 + 29 01 00 00 00 00 02 33 04 + 29 01 00 00 00 00 02 34 02 + 29 01 00 00 00 00 02 37 09 + 29 01 00 00 00 00 02 38 6A + 29 01 00 00 00 00 02 39 6A + 29 01 00 00 00 00 02 3F 6A + 29 01 00 00 00 00 02 41 02 + 29 01 00 00 00 00 02 42 03 + 29 01 00 00 00 00 02 4C 10 + 29 01 00 00 00 00 02 4D 10 + 29 01 00 00 00 00 02 60 90 + 29 01 00 00 00 00 02 61 D8 + 29 01 00 00 00 00 02 72 00 + 29 01 00 00 00 00 02 73 00 + 29 01 00 00 00 00 02 74 00 + 29 01 00 00 00 00 02 75 00 + 29 01 00 00 00 00 02 79 23 + 29 01 00 00 00 00 02 7A 0D + 29 01 00 00 00 00 02 7B 98 + 29 01 00 00 00 00 02 7C 80 + 29 01 00 00 00 00 02 7D 09 + 29 01 00 00 00 00 02 80 42 + 29 01 00 00 00 00 02 82 11 + 29 01 00 00 00 00 02 83 22 + 29 01 00 00 00 00 02 84 33 + 29 01 00 00 00 00 02 85 00 + 29 01 00 00 00 00 02 86 00 + 29 01 00 00 00 00 02 87 00 + 29 01 00 00 00 00 02 88 11 + 29 01 00 00 00 00 02 89 22 + 29 01 00 00 00 00 02 8A 33 + 29 01 00 00 00 00 02 8B 00 + 29 01 00 00 00 00 02 8C 00 + 29 01 00 00 00 00 02 8D 00 + 29 01 00 00 00 00 02 92 6D + 29 01 00 00 00 00 02 9D B6 + 29 01 00 00 00 00 02 B3 02 + 29 01 00 00 00 00 02 B4 00 + 29 01 00 00 00 00 02 DC 44 + 29 01 00 00 00 00 02 DD 03 + 29 01 00 00 00 00 02 DF 3E + 29 01 00 00 00 00 02 E0 3E + 29 01 00 00 00 00 02 E1 22 + 29 01 00 00 00 00 02 E2 24 + 29 01 00 00 00 00 02 E3 09 + 29 01 00 00 00 00 02 E4 09 + 29 01 00 00 00 00 02 EB 0F + 29 01 00 00 00 00 02 FF 25 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 21 18 + 29 01 00 00 00 00 02 22 18 + 29 01 00 00 00 00 02 24 6D + 29 01 00 00 00 00 02 25 6D + 29 01 00 00 00 00 02 2F 10 + 29 01 00 00 00 00 02 30 2D + 29 01 00 00 00 00 02 38 2D + 29 01 00 00 00 00 02 3F 21 + 29 01 00 00 00 00 02 40 65 + 29 01 00 00 00 00 02 4B 21 + 29 01 00 00 00 00 02 4C 65 + 29 01 00 00 00 00 02 58 22 + 29 01 00 00 00 00 02 59 04 + 29 01 00 00 00 00 02 5A 09 + 29 01 00 00 00 00 02 5B 09 + 29 01 00 00 00 00 02 5C 25 + 29 01 00 00 00 00 02 5E FF + 29 01 00 00 00 00 02 5F 28 + 29 01 00 00 00 00 02 66 D8 + 29 01 00 00 00 00 02 67 2B + 29 01 00 00 00 00 02 68 58 + 29 01 00 00 00 00 02 6B 00 + 29 01 00 00 00 00 02 6C 6D + 29 01 00 00 00 00 02 77 72 + 29 01 00 00 00 00 02 BF 00 + 29 01 00 00 00 00 02 C3 01 + 29 01 00 00 00 00 02 FF 26 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 06 FF + 29 01 00 00 00 00 02 0C 11 + 29 01 00 00 00 00 02 0F 09 + 29 01 00 00 00 00 02 10 0A + 29 01 00 00 00 00 02 12 8C + 29 01 00 00 00 00 02 1A 28 + 29 01 00 00 00 00 02 1C AF + 29 01 00 00 00 00 02 1E AB + 29 01 00 00 00 00 02 98 F1 + 29 01 00 00 00 00 02 A9 12 + 29 01 00 00 00 00 02 AA 10 + 29 01 00 00 00 00 02 AE 6A + 29 01 00 00 00 00 02 FF 27 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 13 00 + 29 01 00 00 00 00 02 1E 24 + 29 01 00 00 00 00 02 FF F0 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 02 A2 00 + 29 01 00 00 00 00 02 FF 20 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 11 B0 00 00 00 3D 00 + 74 00 9A 00 B9 00 D1 00 E6 00 F8 + 29 01 00 00 00 00 11 B1 01 08 01 3B 01 + 5E 01 95 01 BB 01 F8 02 23 02 25 + 29 01 00 00 00 00 11 B2 02 51 02 84 02 + AB 02 E1 02 FB 03 30 03 3E 03 4D + 29 01 00 00 00 00 0D B3 03 5F 03 72 03 + 8A 03 A9 03 C9 03 FF + 29 01 00 00 00 00 11 B4 00 00 00 3D 00 + 74 00 9A 00 B9 00 D1 00 E6 00 F8 + 29 01 00 00 00 00 11 B5 01 08 01 3B 01 + 5E 01 95 01 BB 01 F8 02 23 02 25 + 29 01 00 00 00 00 11 B6 02 51 02 84 02 + AB 02 E1 02 FB 03 30 03 3E 03 4D + 29 01 00 00 00 00 0D B7 03 5F 03 72 03 + 8A 03 A9 03 C9 03 FF + 29 01 00 00 00 00 11 B8 00 00 00 3D 00 + 74 00 9A 00 B9 00 D1 00 E6 00 F8 + 29 01 00 00 00 00 11 B9 01 08 01 3B 01 + 5E 01 95 01 BB 01 F8 02 23 02 25 + 29 01 00 00 00 00 11 BA 02 51 02 84 02 + AB 02 E1 02 FB 03 30 03 3E 03 4D + 29 01 00 00 00 00 0D BB 03 5F 03 72 03 + 8A 03 A9 03 C9 03 FF + 29 01 00 00 00 00 02 FF 21 + 29 01 00 00 00 00 02 FB 01 + 29 01 00 00 00 00 11 B0 00 00 00 3D 00 + 74 00 9A 00 B9 00 D1 00 E6 00 F8 + 29 01 00 00 00 00 11 B1 01 08 01 3B 01 + 5E 01 95 01 BB 01 F8 02 23 02 25 + 29 01 00 00 00 00 11 B2 02 51 02 84 02 + AB 02 E1 02 FB 03 30 03 3E 03 4D + 29 01 00 00 00 00 0D B3 03 5F 03 72 03 + 8A 03 A9 03 C9 03 FF + 29 01 00 00 00 00 11 B4 00 00 00 3D 00 + 74 00 9A 00 B9 00 D1 00 E6 00 F8 + 29 01 00 00 00 00 11 B5 01 08 01 3B 01 + 5E 01 95 01 BB 01 F8 02 23 02 25 + 29 01 00 00 00 00 11 B6 02 51 02 84 02 + AB 02 E1 02 FB 03 30 03 3E 03 4D + 29 01 00 00 00 00 0D B7 03 5F 03 72 03 + 8A 03 A9 03 C9 03 FF + 29 01 00 00 00 00 11 B8 00 00 00 3D 00 + 74 00 9A 00 B9 00 D1 00 E6 00 F8 + 29 01 00 00 00 00 11 B9 01 08 01 3B 01 + 5E 01 95 01 BB 01 F8 02 23 02 25 + 29 01 00 00 00 00 11 BA 02 51 02 84 02 + AB 02 E1 02 FB 03 30 03 3E 03 4D + 29 01 00 00 00 00 0D BB 03 5F 03 72 03 + 8A 03 A9 03 C9 03 FF + 29 01 00 00 00 00 02 FF 10 + 29 01 00 00 00 00 02 FB 01 + 39 01 00 00 00 00 02 51 FF + 39 01 00 00 00 00 02 53 2C + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 32 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 14 + 00 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi new file mode 100644 index 000000000000..ca28261a82a7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi @@ -0,0 +1,87 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_dual_nt36850_truly_cmd: qcom,mdss_dsi_nt36850_truly_wqhd_cmd { + qcom,mdss-dsi-panel-name = + "Dual nt36850 cmd mode dsi truly panel without DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 50>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <140>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 36 00 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 44 03 e8 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 2c + 15 01 00 00 00 00 02 55 01 + 05 01 00 00 0a 00 02 20 00 + 15 01 00 00 00 00 02 bb 10 + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-rm69298-truly-amoled-fhd-plus-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-rm69298-truly-amoled-fhd-plus-cmd.dtsi new file mode 100644 index 000000000000..506a0c4dfad3 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-rm69298-truly-amoled-fhd-plus-cmd.dtsi @@ -0,0 +1,330 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_rm69298_truly_amoled_cmd: qcom,mdss_dsi_rm69298_truly_amoled_cmd { + qcom,mdss-dsi-panel-name = + "rm69298 amoled fhd+ cmd mode dsi truly panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2160>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <10>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <16>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 FE 40 + 15 01 00 00 00 00 02 0A 15 + 15 01 00 00 00 00 02 0B CC + 15 01 00 00 00 00 02 0C 15 + 15 01 00 00 00 00 02 0D 80 + 15 01 00 00 00 00 02 0F 87 + 15 01 00 00 00 00 02 05 08 + 15 01 00 00 00 00 02 06 08 + 15 01 00 00 00 00 02 08 08 + 15 01 00 00 00 00 02 09 08 + 15 01 00 00 00 00 02 16 15 + 15 01 00 00 00 00 02 20 8D + 15 01 00 00 00 00 02 21 8D + 15 01 00 00 00 00 02 24 55 + 15 01 00 00 00 00 02 26 55 + 15 01 00 00 00 00 02 28 55 + 15 01 00 00 00 00 02 2A 55 + 15 01 00 00 00 00 02 2D 28 + 15 01 00 00 00 00 02 2F 28 + 15 01 00 00 00 00 02 30 1E + 15 01 00 00 00 00 02 31 1E + 15 01 00 00 00 00 02 37 80 + 15 01 00 00 00 00 02 38 40 + 15 01 00 00 00 00 02 39 90 + 15 01 00 00 00 00 02 46 43 + 15 01 00 00 00 00 02 47 43 + 15 01 00 00 00 00 02 64 02 + 15 01 00 00 00 00 02 6F 02 + 15 01 00 00 00 00 02 74 2F + 15 01 00 00 00 00 02 80 16 + 15 01 00 00 00 00 02 4E 01 + 15 01 00 00 00 00 02 FE A0 + 15 01 00 00 00 00 02 2B 22 + 15 01 00 00 00 00 02 16 00 + 15 01 00 00 00 00 02 2F 35 + 15 01 00 00 00 00 02 FE 60 + 15 01 00 00 00 00 02 00 AC + 15 01 00 00 00 00 02 01 0F + 15 01 00 00 00 00 02 02 FF + 15 01 00 00 00 00 02 03 05 + 15 01 00 00 00 00 02 04 00 + 15 01 00 00 00 00 02 05 06 + 15 01 00 00 00 00 02 06 00 + 15 01 00 00 00 00 02 07 00 + 15 01 00 00 00 00 02 09 C0 + 15 01 00 00 00 00 02 0A 00 + 15 01 00 00 00 00 02 0B 02 + 15 01 00 00 00 00 02 0C 00 + 15 01 00 00 00 00 02 0E 00 + 15 01 00 00 00 00 02 0E 04 + 15 01 00 00 00 00 02 0F 0E + 15 01 00 00 00 00 02 10 A2 + 15 01 00 00 00 00 02 12 C0 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 14 02 + 15 01 00 00 00 00 02 15 00 + 15 01 00 00 00 00 02 16 00 + 15 01 00 00 00 00 02 17 05 + 15 01 00 00 00 00 02 18 0E + 15 01 00 00 00 00 02 19 A2 + 15 01 00 00 00 00 02 1b C0 + 15 01 00 00 00 00 02 1c 00 + 15 01 00 00 00 00 02 1d 04 + 15 01 00 00 00 00 02 1E 01 + 15 01 00 00 00 00 02 1F 00 + 15 01 00 00 00 00 02 20 04 + 15 01 00 00 00 00 02 21 24 + 15 01 00 00 00 00 02 22 99 + 15 01 00 00 00 00 02 24 C0 + 15 01 00 00 00 00 02 25 00 + 15 01 00 00 00 00 02 26 04 + 15 01 00 00 00 00 02 27 01 + 15 01 00 00 00 00 02 28 00 + 15 01 00 00 00 00 02 29 06 + 15 01 00 00 00 00 02 2a 24 + 15 01 00 00 00 00 02 2b 99 + 15 01 00 00 00 00 02 83 CA + 15 01 00 00 00 00 02 84 0F + 15 01 00 00 00 00 02 85 FF + 15 01 00 00 00 00 02 86 0A + 15 01 00 00 00 00 02 87 00 + 15 01 00 00 00 00 02 88 08 + 15 01 00 00 00 00 02 89 00 + 15 01 00 00 00 00 02 8A 00 + 15 01 00 00 00 00 02 8B 80 + 15 01 00 00 00 00 02 C7 1F + 15 01 00 00 00 00 02 C8 00 + 15 01 00 00 00 00 02 C9 01 + 15 01 00 00 00 00 02 CA 1F + 15 01 00 00 00 00 02 CB 02 + 15 01 00 00 00 00 02 CC 1F + 15 01 00 00 00 00 02 CD 1F + 15 01 00 00 00 00 02 CE 1F + 15 01 00 00 00 00 02 CF 1F + 15 01 00 00 00 00 02 D0 1F + 15 01 00 00 00 00 02 D1 1F + 15 01 00 00 00 00 02 D2 1F + 15 01 00 00 00 00 02 D3 1F + 15 01 00 00 00 00 02 D4 1F + 15 01 00 00 00 00 02 D5 1F + 15 01 00 00 00 00 02 D6 1F + 15 01 00 00 00 00 02 D7 1F + 15 01 00 00 00 00 02 D8 1F + 15 01 00 00 00 00 02 D9 1F + 15 01 00 00 00 00 02 DA 1F + 15 01 00 00 00 00 02 DB 1F + 15 01 00 00 00 00 02 DC 00 + 15 01 00 00 00 00 02 DD 0E + 15 01 00 00 00 00 02 DE 1F + 15 01 00 00 00 00 02 DF 03 + 15 01 00 00 00 00 02 E0 04 + 15 01 00 00 00 00 02 E1 1F + 15 01 00 00 00 00 02 E2 01 + 15 01 00 00 00 00 02 E3 02 + 15 01 00 00 00 00 02 E4 1F + 15 01 00 00 00 00 02 E5 1F + 15 01 00 00 00 00 02 E6 1F + 15 01 00 00 00 00 02 E7 1F + 15 01 00 00 00 00 02 E8 1F + 15 01 00 00 00 00 02 E9 1F + 15 01 00 00 00 00 02 EA 1F + 15 01 00 00 00 00 02 EB 1F + 15 01 00 00 00 00 02 EC 1F + 15 01 00 00 00 00 02 ED 1F + 15 01 00 00 00 00 02 EE 1F + 15 01 00 00 00 00 02 EF 03 + 15 01 00 00 00 00 02 FE E0 + 15 01 00 00 00 00 02 C6 15 + 15 01 00 00 00 00 02 C9 9E + 15 01 00 00 00 00 02 CB 3F + 15 01 00 00 00 00 02 D1 0F + 15 01 00 00 00 00 02 D3 15 + 15 01 00 00 00 00 02 D4 15 + 15 01 00 00 00 00 02 D5 00 + 15 01 00 00 00 00 02 FE 90 + 15 01 00 00 00 00 02 C8 00 + 15 01 00 00 00 00 02 FE E0 + 15 01 00 00 00 00 02 09 00 + 15 01 00 00 00 00 02 FE 70 + 15 01 00 00 00 00 02 A9 40 + 15 01 00 00 00 00 02 CB 05 + 15 01 00 00 00 00 02 FE 70 + 15 01 00 00 00 00 02 5A FF + 15 01 00 00 00 00 02 5C FF + 15 01 00 00 00 00 02 5D 0A + 15 01 00 00 00 00 02 7D 31 + 15 01 00 00 00 00 02 7E 4A + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 49 05 + 15 01 00 00 00 00 02 4A 2E + 15 01 00 00 00 00 02 4B 58 + 15 01 00 00 00 00 02 4C 77 + 15 01 00 00 00 00 02 4D A1 + 15 01 00 00 00 00 02 4E DE + 15 01 00 00 00 00 02 4F 2C + 15 01 00 00 00 00 02 50 97 + 15 01 00 00 00 00 02 51 2A + 15 01 00 00 00 00 02 AD EC + 15 01 00 00 00 00 02 AE 80 + 15 01 00 00 00 00 02 AF 00 + 15 01 00 00 00 00 02 B0 50 + 15 01 00 00 00 00 02 B1 3A + 15 01 00 00 00 00 02 FE 90 + 15 01 00 00 00 00 02 56 91 + 15 01 00 00 00 00 02 58 04 + 15 01 00 00 00 00 02 59 24 + 15 01 00 00 00 00 02 5A 05 + 15 01 00 00 00 00 02 5B C6 + 15 01 00 00 00 00 02 5C 05 + 15 01 00 00 00 00 02 5D 66 + 15 01 00 00 00 00 02 5E 06 + 15 01 00 00 00 00 02 5F 17 + 15 01 00 00 00 00 02 60 07 + 15 01 00 00 00 00 02 61 CF + 15 01 00 00 00 00 02 62 07 + 15 01 00 00 00 00 02 63 98 + 15 01 00 00 00 00 02 64 08 + 15 01 00 00 00 00 02 65 65 + 15 01 00 00 00 00 02 66 09 + 15 01 00 00 00 00 02 67 37 + 15 01 00 00 00 00 02 68 0A + 15 01 00 00 00 00 02 6B 02 + 15 01 00 00 00 00 02 6C 0C + 15 01 00 00 00 00 02 71 02 + 15 01 00 00 00 00 02 72 0F + 15 01 00 00 00 00 02 73 93 + 15 01 00 00 00 00 02 74 0F + 15 01 00 00 00 00 02 FE 20 + 15 01 00 00 00 00 02 98 CF + 15 01 00 00 00 00 02 FE 20 + 15 01 00 00 00 00 02 72 11 + 15 01 00 00 00 00 02 B4 31 + 15 01 00 00 00 00 02 B7 42 + 15 01 00 00 00 00 02 AA 03 + 15 01 00 00 00 00 02 09 13 + 15 01 00 00 00 00 02 FE 20 + 15 01 00 00 00 00 02 01 41 + 15 01 00 00 00 00 02 02 00 + 15 01 00 00 00 00 02 03 00 + 15 01 00 00 00 00 02 04 FF + 15 01 00 00 00 00 02 05 00 + 15 01 00 00 00 00 02 06 C0 + 15 01 00 00 00 00 02 07 40 + 15 01 00 00 00 00 02 08 20 + 15 01 00 00 00 00 02 19 E0 + 15 01 00 00 00 00 02 1A 40 + 15 01 00 00 00 00 02 1B 00 + 15 01 00 00 00 00 02 1C 80 + 15 01 00 00 00 00 02 60 40 + 15 01 00 00 00 00 02 61 40 + 15 01 00 00 00 00 02 62 40 + 15 01 00 00 00 00 02 63 40 + 15 01 00 00 00 00 02 64 40 + 15 01 00 00 00 00 02 65 40 + 15 01 00 00 00 00 02 72 11 + 15 01 00 00 00 00 02 73 00 + 15 01 00 00 00 00 02 74 02 + 15 01 00 00 00 00 02 75 10 + 15 01 00 00 00 00 02 76 14 + 15 01 00 00 00 00 02 77 1C + 15 01 00 00 00 00 02 78 20 + 15 01 00 00 00 00 02 79 0A + 15 01 00 00 00 00 02 7A 00 + 15 01 00 00 00 00 02 7B 00 + 15 01 00 00 00 00 02 7C 00 + 15 01 00 00 00 00 02 7D 00 + 15 01 00 00 00 00 02 7E 00 + 15 01 00 00 00 00 02 7F 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 81 00 + 15 01 00 00 00 00 02 82 00 + 15 01 00 00 00 00 02 83 00 + 15 01 00 00 00 00 02 84 00 + 15 01 00 00 00 00 02 85 00 + 15 01 00 00 00 00 02 86 20 + 15 01 00 00 00 00 02 87 0A + 15 01 00 00 00 00 02 88 02 + 15 01 00 00 00 00 02 89 2B + 15 01 00 00 00 00 02 8A 14 + 15 01 00 00 00 00 02 8B 01 + 15 01 00 00 00 00 02 8C 00 + 15 01 00 00 00 00 02 8D 00 + 15 01 00 00 00 00 02 8E 00 + 15 01 00 00 00 00 02 8F 00 + 15 01 00 00 00 00 02 90 00 + 15 01 00 00 00 00 02 91 00 + 15 01 00 00 00 00 02 92 00 + 15 01 00 00 00 00 02 93 00 + 15 01 00 00 00 00 02 94 00 + 15 01 00 00 00 00 02 95 00 + 15 01 00 00 00 00 02 96 00 + 15 01 00 00 00 00 02 B2 40 + 15 01 00 00 00 00 02 B7 42 + 15 01 00 00 00 00 02 B8 D0 + 15 01 00 00 00 00 02 B9 06 + 15 01 00 00 00 00 02 BA 00 + 15 01 00 00 00 00 02 FE 00 + 39 01 00 00 00 00 05 51 00 00 FF FF + 15 01 00 00 00 00 02 C2 08 + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 96 00 01 11 + 05 01 00 00 32 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 32 00 02 28 00 + 05 01 00 00 96 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-rm69298-truly-amoled-fhd-plus-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-rm69298-truly-amoled-fhd-plus-video.dtsi new file mode 100644 index 000000000000..a42d873f1139 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-rm69298-truly-amoled-fhd-plus-video.dtsi @@ -0,0 +1,330 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_rm69298_truly_amoled_video: + qcom,mdss_dsi_rm69298_truly_amoled_video { + qcom,mdss-dsi-panel-name = + "rm69298 amoled fhd+ video mode dsi truly panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2160>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <10>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <16>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 FE 40 + 15 01 00 00 00 00 02 0A 15 + 15 01 00 00 00 00 02 0B CC + 15 01 00 00 00 00 02 0C 15 + 15 01 00 00 00 00 02 0D 80 + 15 01 00 00 00 00 02 0F 87 + 15 01 00 00 00 00 02 05 08 + 15 01 00 00 00 00 02 06 08 + 15 01 00 00 00 00 02 08 08 + 15 01 00 00 00 00 02 09 08 + 15 01 00 00 00 00 02 16 15 + 15 01 00 00 00 00 02 20 8D + 15 01 00 00 00 00 02 21 8D + 15 01 00 00 00 00 02 24 55 + 15 01 00 00 00 00 02 26 55 + 15 01 00 00 00 00 02 28 55 + 15 01 00 00 00 00 02 2A 55 + 15 01 00 00 00 00 02 2D 28 + 15 01 00 00 00 00 02 2F 28 + 15 01 00 00 00 00 02 30 1E + 15 01 00 00 00 00 02 31 1E + 15 01 00 00 00 00 02 37 80 + 15 01 00 00 00 00 02 38 40 + 15 01 00 00 00 00 02 39 90 + 15 01 00 00 00 00 02 46 43 + 15 01 00 00 00 00 02 47 43 + 15 01 00 00 00 00 02 64 02 + 15 01 00 00 00 00 02 6F 02 + 15 01 00 00 00 00 02 74 2F + 15 01 00 00 00 00 02 80 16 + 15 01 00 00 00 00 02 4E 01 + 15 01 00 00 00 00 02 FE A0 + 15 01 00 00 00 00 02 2B 22 + 15 01 00 00 00 00 02 16 00 + 15 01 00 00 00 00 02 2F 35 + 15 01 00 00 00 00 02 FE 60 + 15 01 00 00 00 00 02 00 AC + 15 01 00 00 00 00 02 01 0F + 15 01 00 00 00 00 02 02 FF + 15 01 00 00 00 00 02 03 05 + 15 01 00 00 00 00 02 04 00 + 15 01 00 00 00 00 02 05 06 + 15 01 00 00 00 00 02 06 00 + 15 01 00 00 00 00 02 07 00 + 15 01 00 00 00 00 02 09 C0 + 15 01 00 00 00 00 02 0A 00 + 15 01 00 00 00 00 02 0B 02 + 15 01 00 00 00 00 02 0C 00 + 15 01 00 00 00 00 02 0E 00 + 15 01 00 00 00 00 02 0E 04 + 15 01 00 00 00 00 02 0F 0E + 15 01 00 00 00 00 02 10 A2 + 15 01 00 00 00 00 02 12 C0 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 14 02 + 15 01 00 00 00 00 02 15 00 + 15 01 00 00 00 00 02 16 00 + 15 01 00 00 00 00 02 17 05 + 15 01 00 00 00 00 02 18 0E + 15 01 00 00 00 00 02 19 A2 + 15 01 00 00 00 00 02 1b C0 + 15 01 00 00 00 00 02 1c 00 + 15 01 00 00 00 00 02 1d 04 + 15 01 00 00 00 00 02 1E 01 + 15 01 00 00 00 00 02 1F 00 + 15 01 00 00 00 00 02 20 04 + 15 01 00 00 00 00 02 21 24 + 15 01 00 00 00 00 02 22 99 + 15 01 00 00 00 00 02 24 C0 + 15 01 00 00 00 00 02 25 00 + 15 01 00 00 00 00 02 26 04 + 15 01 00 00 00 00 02 27 01 + 15 01 00 00 00 00 02 28 00 + 15 01 00 00 00 00 02 29 06 + 15 01 00 00 00 00 02 2a 24 + 15 01 00 00 00 00 02 2b 99 + 15 01 00 00 00 00 02 83 CA + 15 01 00 00 00 00 02 84 0F + 15 01 00 00 00 00 02 85 FF + 15 01 00 00 00 00 02 86 0A + 15 01 00 00 00 00 02 87 00 + 15 01 00 00 00 00 02 88 08 + 15 01 00 00 00 00 02 89 00 + 15 01 00 00 00 00 02 8A 00 + 15 01 00 00 00 00 02 8B 80 + 15 01 00 00 00 00 02 C7 1F + 15 01 00 00 00 00 02 C8 00 + 15 01 00 00 00 00 02 C9 01 + 15 01 00 00 00 00 02 CA 1F + 15 01 00 00 00 00 02 CB 02 + 15 01 00 00 00 00 02 CC 1F + 15 01 00 00 00 00 02 CD 1F + 15 01 00 00 00 00 02 CE 1F + 15 01 00 00 00 00 02 CF 1F + 15 01 00 00 00 00 02 D0 1F + 15 01 00 00 00 00 02 D1 1F + 15 01 00 00 00 00 02 D2 1F + 15 01 00 00 00 00 02 D3 1F + 15 01 00 00 00 00 02 D4 1F + 15 01 00 00 00 00 02 D5 1F + 15 01 00 00 00 00 02 D6 1F + 15 01 00 00 00 00 02 D7 1F + 15 01 00 00 00 00 02 D8 1F + 15 01 00 00 00 00 02 D9 1F + 15 01 00 00 00 00 02 DA 1F + 15 01 00 00 00 00 02 DB 1F + 15 01 00 00 00 00 02 DC 00 + 15 01 00 00 00 00 02 DD 0E + 15 01 00 00 00 00 02 DE 1F + 15 01 00 00 00 00 02 DF 03 + 15 01 00 00 00 00 02 E0 04 + 15 01 00 00 00 00 02 E1 1F + 15 01 00 00 00 00 02 E2 01 + 15 01 00 00 00 00 02 E3 02 + 15 01 00 00 00 00 02 E4 1F + 15 01 00 00 00 00 02 E5 1F + 15 01 00 00 00 00 02 E6 1F + 15 01 00 00 00 00 02 E7 1F + 15 01 00 00 00 00 02 E8 1F + 15 01 00 00 00 00 02 E9 1F + 15 01 00 00 00 00 02 EA 1F + 15 01 00 00 00 00 02 EB 1F + 15 01 00 00 00 00 02 EC 1F + 15 01 00 00 00 00 02 ED 1F + 15 01 00 00 00 00 02 EE 1F + 15 01 00 00 00 00 02 EF 03 + 15 01 00 00 00 00 02 FE E0 + 15 01 00 00 00 00 02 C6 15 + 15 01 00 00 00 00 02 C9 9E + 15 01 00 00 00 00 02 CB 3F + 15 01 00 00 00 00 02 D1 0F + 15 01 00 00 00 00 02 D3 15 + 15 01 00 00 00 00 02 D4 15 + 15 01 00 00 00 00 02 D5 00 + 15 01 00 00 00 00 02 FE 90 + 15 01 00 00 00 00 02 C8 00 + 15 01 00 00 00 00 02 FE E0 + 15 01 00 00 00 00 02 09 00 + 15 01 00 00 00 00 02 FE 70 + 15 01 00 00 00 00 02 A9 40 + 15 01 00 00 00 00 02 CB 05 + 15 01 00 00 00 00 02 FE 70 + 15 01 00 00 00 00 02 5A FF + 15 01 00 00 00 00 02 5C FF + 15 01 00 00 00 00 02 5D 0A + 15 01 00 00 00 00 02 7D 31 + 15 01 00 00 00 00 02 7E 4A + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 49 05 + 15 01 00 00 00 00 02 4A 2E + 15 01 00 00 00 00 02 4B 58 + 15 01 00 00 00 00 02 4C 77 + 15 01 00 00 00 00 02 4D A1 + 15 01 00 00 00 00 02 4E DE + 15 01 00 00 00 00 02 4F 2C + 15 01 00 00 00 00 02 50 97 + 15 01 00 00 00 00 02 51 2A + 15 01 00 00 00 00 02 AD EC + 15 01 00 00 00 00 02 AE 80 + 15 01 00 00 00 00 02 AF 00 + 15 01 00 00 00 00 02 B0 50 + 15 01 00 00 00 00 02 B1 3A + 15 01 00 00 00 00 02 FE 90 + 15 01 00 00 00 00 02 56 91 + 15 01 00 00 00 00 02 58 04 + 15 01 00 00 00 00 02 59 24 + 15 01 00 00 00 00 02 5A 05 + 15 01 00 00 00 00 02 5B C6 + 15 01 00 00 00 00 02 5C 05 + 15 01 00 00 00 00 02 5D 66 + 15 01 00 00 00 00 02 5E 06 + 15 01 00 00 00 00 02 5F 17 + 15 01 00 00 00 00 02 60 07 + 15 01 00 00 00 00 02 61 CF + 15 01 00 00 00 00 02 62 07 + 15 01 00 00 00 00 02 63 98 + 15 01 00 00 00 00 02 64 08 + 15 01 00 00 00 00 02 65 65 + 15 01 00 00 00 00 02 66 09 + 15 01 00 00 00 00 02 67 37 + 15 01 00 00 00 00 02 68 0A + 15 01 00 00 00 00 02 6B 02 + 15 01 00 00 00 00 02 6C 0C + 15 01 00 00 00 00 02 71 02 + 15 01 00 00 00 00 02 72 0F + 15 01 00 00 00 00 02 73 93 + 15 01 00 00 00 00 02 74 0F + 15 01 00 00 00 00 02 FE 20 + 15 01 00 00 00 00 02 98 CF + 15 01 00 00 00 00 02 FE 20 + 15 01 00 00 00 00 02 72 11 + 15 01 00 00 00 00 02 B4 31 + 15 01 00 00 00 00 02 B7 42 + 15 01 00 00 00 00 02 AA 03 + 15 01 00 00 00 00 02 09 13 + 15 01 00 00 00 00 02 FE 20 + 15 01 00 00 00 00 02 01 41 + 15 01 00 00 00 00 02 02 00 + 15 01 00 00 00 00 02 03 00 + 15 01 00 00 00 00 02 04 FF + 15 01 00 00 00 00 02 05 00 + 15 01 00 00 00 00 02 06 C0 + 15 01 00 00 00 00 02 07 40 + 15 01 00 00 00 00 02 08 20 + 15 01 00 00 00 00 02 19 E0 + 15 01 00 00 00 00 02 1A 40 + 15 01 00 00 00 00 02 1B 00 + 15 01 00 00 00 00 02 1C 80 + 15 01 00 00 00 00 02 60 40 + 15 01 00 00 00 00 02 61 40 + 15 01 00 00 00 00 02 62 40 + 15 01 00 00 00 00 02 63 40 + 15 01 00 00 00 00 02 64 40 + 15 01 00 00 00 00 02 65 40 + 15 01 00 00 00 00 02 72 11 + 15 01 00 00 00 00 02 73 00 + 15 01 00 00 00 00 02 74 02 + 15 01 00 00 00 00 02 75 10 + 15 01 00 00 00 00 02 76 14 + 15 01 00 00 00 00 02 77 1C + 15 01 00 00 00 00 02 78 20 + 15 01 00 00 00 00 02 79 0A + 15 01 00 00 00 00 02 7A 00 + 15 01 00 00 00 00 02 7B 00 + 15 01 00 00 00 00 02 7C 00 + 15 01 00 00 00 00 02 7D 00 + 15 01 00 00 00 00 02 7E 00 + 15 01 00 00 00 00 02 7F 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 81 00 + 15 01 00 00 00 00 02 82 00 + 15 01 00 00 00 00 02 83 00 + 15 01 00 00 00 00 02 84 00 + 15 01 00 00 00 00 02 85 00 + 15 01 00 00 00 00 02 86 20 + 15 01 00 00 00 00 02 87 0A + 15 01 00 00 00 00 02 88 02 + 15 01 00 00 00 00 02 89 2B + 15 01 00 00 00 00 02 8A 14 + 15 01 00 00 00 00 02 8B 01 + 15 01 00 00 00 00 02 8C 00 + 15 01 00 00 00 00 02 8D 00 + 15 01 00 00 00 00 02 8E 00 + 15 01 00 00 00 00 02 8F 00 + 15 01 00 00 00 00 02 90 00 + 15 01 00 00 00 00 02 91 00 + 15 01 00 00 00 00 02 92 00 + 15 01 00 00 00 00 02 93 00 + 15 01 00 00 00 00 02 94 00 + 15 01 00 00 00 00 02 95 00 + 15 01 00 00 00 00 02 96 00 + 15 01 00 00 00 00 02 B2 40 + 15 01 00 00 00 00 02 B7 42 + 15 01 00 00 00 00 02 B8 D0 + 15 01 00 00 00 00 02 B9 06 + 15 01 00 00 00 00 02 BA 00 + 15 01 00 00 00 00 02 FE 00 + 39 01 00 00 00 00 05 51 00 00 FF FF + 15 01 00 00 00 00 02 C2 09 + 05 01 00 00 96 00 01 11 + 05 01 00 00 32 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 32 00 02 28 00 + 05 01 00 00 96 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-rm69299-visionox-amoled-fhd-plus-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-rm69299-visionox-amoled-fhd-plus-video.dtsi new file mode 100644 index 000000000000..0939b5a4c76f --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-rm69299-visionox-amoled-fhd-plus-video.dtsi @@ -0,0 +1,75 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_rm69299_visionox_amoled_video: + qcom,mdss_dsi_rm69299_visionox_amoled_video { + qcom,mdss-dsi-panel-name = + "rm69299 amoled fhd+ video mode dsi visionox panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2248>; + qcom,mdss-dsi-h-front-porch = <26>; + qcom,mdss-dsi-h-back-porch = <36>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <56>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 FE 00 + 39 01 00 00 00 00 02 C2 08 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 51 FF + 05 01 00 00 96 00 02 11 00 + 05 01 00 00 32 00 02 29 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 32 00 02 28 00 + 05 01 00 00 96 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi new file mode 100644 index 000000000000..834a08fd4625 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi @@ -0,0 +1,141 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_dual_s6e3ha3_amoled_cmd: qcom,mdss_dsi_s6e3ha3_amoled_wqhd_cmd{ + qcom,mdss-dsi-panel-name = + "Dual s6e3ha3 amoled cmd mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <31>; + qcom,mdss-dsi-v-front-porch = <30>; + qcom,mdss-dsi-v-pulse-width = <8>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-on-command = [05 01 00 00 05 00 02 11 00 + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 09 ff + 39 01 00 00 00 00 03 f0 5a 5a + 39 01 00 00 00 00 02 b0 10 + 39 01 00 00 00 00 02 b5 a0 + 39 01 00 00 00 00 02 c4 03 + 39 01 00 00 00 00 0a + f6 42 57 37 00 aa cc d0 00 00 + 39 01 00 00 00 00 02 f9 03 + 39 01 00 00 00 00 14 + c2 00 00 d8 d8 00 80 2b 05 08 + 0e 07 0b 05 0d 0a 15 13 20 1e + 39 01 00 00 78 00 03 f0 a5 a5 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 02 51 60 + 05 01 00 00 05 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 3c 00 02 28 00 + 05 01 00 00 b4 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-lp-mode-on = [39 00 00 00 05 00 03 f0 5a 5a + 39 00 00 00 05 00 03 f1 5a 5a + 39 00 00 00 05 00 03 fc 5a 5a + 39 00 00 00 05 00 02 b0 17 + 39 00 00 00 05 00 02 cb 10 + 39 00 00 00 05 00 02 b0 2d + 39 00 00 00 05 00 02 cb cd + 39 00 00 00 05 00 02 b0 0e + 39 00 00 00 05 00 02 cb 02 + 39 00 00 00 05 00 02 b0 0f + 39 00 00 00 05 00 02 cb 09 + 39 00 00 00 05 00 02 b0 02 + 39 00 00 00 05 00 02 f2 c9 + 39 00 00 00 05 00 02 b0 03 + 39 00 00 00 05 00 02 f2 c0 + 39 00 00 00 05 00 02 b0 03 + 39 00 00 00 05 00 02 f4 aa + 39 00 00 00 05 00 02 b0 08 + 39 00 00 00 05 00 02 b1 30 + 39 00 00 00 05 00 02 b0 09 + 39 00 00 00 05 00 02 b1 0a + 39 00 00 00 05 00 02 b0 0d + 39 00 00 00 05 00 02 b1 10 + 39 00 00 00 05 00 02 b0 00 + 39 00 00 00 05 00 02 f7 03 + 39 00 00 00 05 00 02 fe 30 + 39 01 00 00 05 00 02 fe b0]; + qcom,mdss-dsi-lp-mode-off = [39 00 00 00 05 00 03 f0 5a 5a + 39 00 00 00 05 00 03 f1 5a 5a + 39 00 00 00 05 00 03 fc 5a 5a + 39 00 00 00 05 00 02 b0 2d + 39 00 00 00 05 00 02 cb 4d + 39 00 00 00 05 00 02 b0 17 + 39 00 00 00 05 00 02 cb 04 + 39 00 00 00 05 00 02 b0 0e + 39 00 00 00 05 00 02 cb 06 + 39 00 00 00 05 00 02 b0 0f + 39 00 00 00 05 00 02 cb 05 + 39 00 00 00 05 00 02 b0 02 + 39 00 00 00 05 00 02 f2 b8 + 39 00 00 00 05 00 02 b0 03 + 39 00 00 00 05 00 02 f2 80 + 39 00 00 00 05 00 02 b0 03 + 39 00 00 00 05 00 02 f4 8a + 39 00 00 00 05 00 02 b0 08 + 39 00 00 00 05 00 02 b1 10 + 39 00 00 00 05 00 02 b0 09 + 39 00 00 00 05 00 02 b1 0a + 39 00 00 00 05 00 02 b0 0d + 39 00 00 00 05 00 02 b1 80 + 39 00 00 00 05 00 02 b0 00 + 39 00 00 00 05 00 02 f7 03 + 39 00 00 00 05 00 02 fe 30 + 39 01 00 00 05 00 02 fe b0]; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,dcs-cmd-by-left; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <122>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-samsung_oneplus_dsc.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-samsung_oneplus_dsc.dtsi new file mode 100644 index 000000000000..d52ead622a0e --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-samsung_oneplus_dsc.dtsi @@ -0,0 +1,2665 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_samsung_oneplus_dsc_cmd: qcom,mdss_dsi_samsung_oneplus_dsc_cmd { + qcom,mdss-dsi-panel-name = "samsung dsc cmd mode oneplus dsi panel"; + qcom,mdss-dsi-panel-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-version = "DSC"; + qcom,mdss-dsi-backlight-version = "SAMSUNG"; + qcom,mdss-dsi-backlight-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-reset-sequence = <1 8>, <0 1>, <1 5>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-default-val = <200>; + qcom,mdss-brightness-max-level = <1023>; + qcom,mdss-pan-physical-width-dimension = <71>; + qcom,mdss-pan-physical-height-dimension = <154>; + qcom,mdss-dsi-init-delay-us = <1000>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-high-brightness-panel; + qcom,mdss-dsi-acl-cmd-index = <0>; + qcom,mdss-dsi-acl-mode-index = <1>; + qcom,mdss-bl-high2bit; + qcom,mdss-loading-effect; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,dynamic-mode-switch-enabled; + qcom,dynamic-mode-switch-type = "dynamic-resolution-switch-immediate"; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + /* HDR Setting */ + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15635 16450 34000 16000 13250 34500 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <5400000>; + qcom,mdss-dsi-panel-average-brightness = <2000000>; + qcom,mdss-dsi-panel-blackness-level = <2000>; + qcom,mdss-dsi-panel-seria-num-year-index = <12>; + qcom,mdss-dsi-panel-seria-num-mon-index = <12>; + qcom,mdss-dsi-panel-seria-num-day-index = <13>; + qcom,mdss-dsi-panel-seria-num-hour-index = <14>; + qcom,mdss-dsi-panel-seria-num-min-index = <15>; + qcom,mdss-dsi-panel-seria-num-sec-index = <16>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 00]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-id1-command = [06 01 00 00 00 00 02 0A 00]; + qcom,mdss-dsi-panel-id2-command = [06 01 00 00 00 00 02 0E 00]; + qcom,mdss-dsi-panel-id3-command = [06 01 00 00 00 00 02 0F 00]; + qcom,mdss-dsi-panel-id4-command = [06 01 00 00 00 00 02 C4 00]; + qcom,mdss-dsi-panel-id5-command = [06 01 00 00 00 00 02 E7 00]; + qcom,mdss-dsi-panel-id6-command = [06 01 00 00 00 00 02 EA 00]; + qcom,mdss-dsi-panel-id7-command = [06 01 00 00 00 00 02 FB 00]; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-read-esd-registed-longread-command = [ + 37 01 00 00 05 00 02 22 00 + ]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-esd-registed-longread-command-state = "dsi_lp_mode"; + + /* + * ************************************************************************************************************************ + * DMS (Dynamic Mode Switch) + * ************************************************************************************************************************ + */ + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,mdss-mdp-transfer-time-us = <8000>; //for 60fps + qcom,mdss-dsi-timing-default; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3120>; + qcom,mdss-dsi-h-front-porch = <16>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <1156>; + qcom,mdss-dsi-v-front-porch = <400>; + qcom,mdss-dsi-v-pulse-width = <28>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 00]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-id1-command = [06 01 00 00 00 00 02 0A 00]; + qcom,mdss-dsi-panel-id2-command = [06 01 00 00 00 00 02 0E 00]; + qcom,mdss-dsi-panel-id3-command = [06 01 00 00 00 00 02 0F 00]; + qcom,mdss-dsi-panel-id4-command = [06 01 00 00 00 00 02 C4 00]; + qcom,mdss-dsi-panel-id5-command = [06 01 00 00 00 00 02 E7 00]; + qcom,mdss-dsi-panel-id6-command = [06 01 00 00 00 00 02 EA 00]; + qcom,mdss-dsi-panel-id7-command = [06 01 00 00 00 00 02 FB 00]; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-read-esd-registed-longread-command = [ + 37 01 00 00 05 00 02 22 00 + ]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-esd-registed-longread-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-timing-switch-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + //29 01 00 00 00 00 03 9F A5 A5 + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 29 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + //29 01 00 00 00 00 03 9F 5A 5A + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-on-command = [ + /* DSC Setting */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 39 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 39 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 09 10 B4 24 FB /* FFC Setting; 0x09 : Enable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame*/ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-113mhz-osc-dsi-on-command = [ + /* DSC Setting */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 39 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 39 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 08 10 B4 24 FB /* FFC Setting; 0x08 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame*/ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-113mhz-osc-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-off-command=[ + 05 01 00 00 0A 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-panel-hbm-brightness-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 53 /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM Mode ON */ + 15 01 00 00 11 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-brightness-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 53 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 11 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-hbm-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-3 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-4 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 14 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 29 01 00 00 0D 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 11 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + ]; + qcom,mdss-dsi-panel-serial-num-pre-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 37 01 00 00 05 00 02 10 00 + ]; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 00 + ]; + qcom,mdss-dsi-panel-code-info-command = [ + 06 01 00 00 00 00 01 DA 00 + ]; + qcom,mdss-dsi-panel-stage-info-command = [ + 06 01 00 00 00 00 01 DB 00 + ]; + qcom,mdss-dsi-panel-production-info-command = [ + 06 01 00 00 00 00 01 DC 00 + ]; + qcom,mdss-dsi-panel-serial-num-post-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-aod-off-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 29 01 00 00 00 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command = [ + /*Level2 key Enable*/ + 29 01 00 00 00 00 03 F0 5A 5A + //07 01 00 00 00 00 01 01 + //29 00 00 00 00 00 05 2A 00 00 05 9F + //29 00 00 00 00 00 05 2B 00 00 0C 2F + /*OTP key Enable*/ + 29 01 00 00 00 00 03 F1 F1 A2 + 29 01 00 00 00 00 0D C1 00 00 00 06 00 00 00 00 00 00 00 05 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0C C1 00 00 00 01 40 02 00 00 00 00 10 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0E C1 00 00 00 6B 00 00 00 0A 00 00 00 05 01 + 15 01 00 00 00 00 02 B0 07 + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command = [ + 15 01 00 00 00 00 02 C0 03 + 15 01 00 00 00 00 02 B0 08 + ]; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command = [ + /*13th Parameter : 1byte Read value*/ + 06 01 00 00 00 00 02 FB 00 + ]; + qcom,mdss-dsi-panel-level2-key-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command = [ + 37 01 00 00 05 00 02 87 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command = [ + 06 01 00 00 00 00 02 C8 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command = [ + 37 01 00 00 00 00 02 B4 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command = [ + 06 01 00 00 00 00 02 C9 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command = [ + 37 01 00 00 00 00 02 2F 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command = [ + 06 01 00 00 00 00 02 B3 00 + ]; + qcom,mdss-dsi-panel-level2-key-disable-command = [ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-night-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 39 01 00 0A 00 00 16 67 BB 0E 04 3E D8 12 09 05 EA 41 E2 D0 E5 09 F6 D0 D0 11 F8 FE DC + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-p3-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 E0 03 00 11 E2 01 0D 08 E5 1A FA FC E5 09 F6 EA F3 01 FE FF F7 + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 03 67 00 01 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 81 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 FF 6D + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-disable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 A1 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 28 28 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-srgb-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command = [ + 15 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 0A 00 02 B0 02 + 29 01 00 00 0A 00 16 67 FF 05 00 0B EB 00 07 00 FF 14 F8 EA F0 03 F5 DE F5 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-seed-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 D3 03 00 11 E4 01 0B 06 F0 1A FA FC E5 09 F6 EA F3 01 FC FF EA + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-seed-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-customer-p3-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-customer-srgb-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-loading-effect-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-loading-effect-disable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-p3-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-night-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-dci-p3-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-aod-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-pre-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-code-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-state-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-production-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-post-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-brightness-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-brightness-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-3-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-4-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-disable-command-state = "dsi_lp_mode"; + qcom,panel-roi-alignment=<720 65 720 65 720 65>; + qcom,compression-mode = "dsc"; + qcom,lm-split = <720 720>; + qcom,mdss-dsc-encoders = <2>; + qcom,mdss-dsc-slice-height = <65>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1{ + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,mdss-mdp-transfer-time-us = <8000>; //for 90fps + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <16>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <4>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 00]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-id1-command = [06 01 00 00 00 00 02 0A 00]; + qcom,mdss-dsi-panel-id2-command = [06 01 00 00 00 00 02 0E 00]; + qcom,mdss-dsi-panel-id3-command = [06 01 00 00 00 00 02 0F 00]; + qcom,mdss-dsi-panel-id4-command = [06 01 00 00 00 00 02 C4 00]; + qcom,mdss-dsi-panel-id5-command = [06 01 00 00 00 00 02 E7 00]; + qcom,mdss-dsi-panel-id6-command = [06 01 00 00 00 00 02 EA 00]; + qcom,mdss-dsi-panel-id7-command = [06 01 00 00 00 00 02 FB 00]; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 F0 5A 5A]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-panel-read-esd-registed-longread-command = [ + 37 01 00 00 05 00 02 22 00 + ]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-esd-registed-longread-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-timing-switch-command = [ + 29 01 00 00 00 00 03 F0 5A 5A /* Level2 key Access Enable */ + //29 01 00 00 00 00 03 9F A5 A5 /* Level1 key Access Enable */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 23 /* PASET */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2340) */ + 11 00 00 89 30 80 09 24 + 04 38 00 1E 02 1C 02 1C + 02 00 02 0E 00 20 02 E3 + 00 07 00 0C 03 50 03 64 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + //29 01 00 00 00 00 03 9F 5A 5A + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-on-command = [ + /* DSC Setting */ + 29 01 00 00 00 00 03 F0 5A 5A + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2340) */ + 11 00 00 89 30 80 09 24 + 04 38 00 1E 02 1C 02 1C + 02 00 02 0E 00 20 02 E3 + 00 07 00 0C 03 50 03 64 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 29 01 00 00 00 00 03 F0 A5 A5 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 23 /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 09 10 B4 24 FB /* FFC Setting; 0x09 : Enable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame */ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-113mhz-osc-dsi-on-command = [ + /* DSC Setting */ + 29 01 00 00 00 00 03 F0 5A 5A + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2340) */ + 11 00 00 89 30 80 09 24 + 04 38 00 1E 02 1C 02 1C + 02 00 02 0E 00 20 02 E3 + 00 07 00 0C 03 50 03 64 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 29 01 00 00 00 00 03 F0 A5 A5 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 23 /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 08 10 B4 24 FB /* FFC Setting; 0x08 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame */ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-113mhz-osc-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-off-command=[ + 05 01 00 00 0A 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-panel-hbm-brightness-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 53 /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM Mode ON */ + 15 01 00 00 0C 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-brightness-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 53 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 0C 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-hbm-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-3 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-4 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 10 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 29 01 00 00 0C 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-serial-num-pre-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 37 01 00 00 05 00 02 10 00 + ]; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 00 + ]; + qcom,mdss-dsi-panel-code-info-command = [ + 06 01 00 00 00 00 01 DA 00 + ]; + qcom,mdss-dsi-panel-stage-info-command = [ + 06 01 00 00 00 00 01 DB 00 + ]; + qcom,mdss-dsi-panel-production-info-command = [ + 06 01 00 00 00 00 01 DC 00 + ]; + qcom,mdss-dsi-panel-serial-num-post-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-aod-off-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 29 01 00 00 00 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command = [ + /*Level2 key Enable*/ + 29 01 00 00 00 00 03 F0 5A 5A + //07 01 00 00 00 00 01 01 + //29 00 00 00 00 00 05 2A 00 00 05 9F + //29 00 00 00 00 00 05 2B 00 00 0C 2F + /*OTP key Enable*/ + 29 01 00 00 00 00 03 F1 F1 A2 + 29 01 00 00 00 00 0D C1 00 00 00 06 00 00 00 00 00 00 00 05 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0C C1 00 00 00 01 40 02 00 00 00 00 10 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0E C1 00 00 00 6B 00 00 00 0A 00 00 00 05 01 + 15 01 00 00 00 00 02 B0 07 + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command = [ + 15 01 00 00 00 00 02 C0 03 + 15 01 00 00 00 00 02 B0 08 + ]; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command = [ + /*13th Parameter : 1byte Read value*/ + 06 01 00 00 00 00 02 FB 00 + ]; + qcom,mdss-dsi-panel-level2-key-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command = [ + 37 01 00 00 00 00 02 87 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command = [ + 06 01 00 00 00 00 02 C8 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command = [ + 37 01 00 00 00 00 02 B4 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command = [ + 06 01 00 00 00 00 02 C9 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command = [ + 37 01 00 00 00 00 02 2F 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command = [ + 06 01 00 00 00 00 02 B3 00 + ]; + qcom,mdss-dsi-panel-level2-key-disable-command = [ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-night-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 39 01 00 0A 00 00 16 67 BB 0E 04 3E D8 12 09 05 EA 41 E2 D0 E5 09 F6 D0 D0 11 F8 FE DC + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-p3-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 E0 03 00 11 E2 01 0D 08 E5 1A FA FC E5 09 F6 EA F3 01 FE FF F7 + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 03 67 00 01 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 81 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 FF 6D + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-disable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 A1 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 28 28 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-srgb-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command = [ + 15 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 0A 00 02 B0 02 + 29 01 00 00 0A 00 16 67 FF 05 00 0B EB 00 07 00 FF 14 F8 EA F0 03 F5 DE F5 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-seed-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 D3 03 00 11 E4 01 0B 06 F0 1A FA FC E5 09 F6 EA F3 01 FC FF EA + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-seed-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-customer-p3-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-customer-srgb-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-loading-effect-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-loading-effect-disable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-p3-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-night-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-dci-p3-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-aod-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-pre-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-code-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-state-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-production-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-post-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-brightness-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-brightness-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-3-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-4-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-disable-command-state = "dsi_lp_mode"; + qcom,panel-roi-alignment=<540 60 540 60 540 60>; + qcom,compression-mode = "dsc"; + qcom,lm-split = <540 540>; + qcom,mdss-dsc-encoders = <2>; + qcom,mdss-dsc-slice-height = <60>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2{ + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,mdss-mdp-transfer-time-us = <8000>; //for 60fps + qcom,mdss-dsi-timing-default; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <16>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <1156>; + qcom,mdss-dsi-v-front-porch = <400>; + qcom,mdss-dsi-v-pulse-width = <28>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 00]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-id1-command = [06 01 00 00 00 00 02 0A 00]; + qcom,mdss-dsi-panel-id2-command = [06 01 00 00 00 00 02 0E 00]; + qcom,mdss-dsi-panel-id3-command = [06 01 00 00 00 00 02 0F 00]; + qcom,mdss-dsi-panel-id4-command = [06 01 00 00 00 00 02 C4 00]; + qcom,mdss-dsi-panel-id5-command = [06 01 00 00 00 00 02 E7 00]; + qcom,mdss-dsi-panel-id6-command = [06 01 00 00 00 00 02 EA 00]; + qcom,mdss-dsi-panel-id7-command = [06 01 00 00 00 00 02 FB 00]; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-read-esd-registed-longread-command = [ + 37 01 00 00 05 00 02 22 00 + ]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-esd-registed-longread-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-timing-switch-command = [ + 29 01 00 00 00 00 03 F0 5A 5A /* Level2 key Access Enable */ + //29 01 00 00 00 00 03 9F A5 A5 /* Level1 key Access Enable */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 23 /* PASET */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2340) */ + 11 00 00 89 30 80 09 24 + 04 38 00 1E 02 1C 02 1C + 02 00 02 0E 00 20 02 E3 + 00 07 00 0C 03 50 03 64 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + //29 01 00 00 00 00 03 9F 5A 5A + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-on-command = [ + /* DSC Setting */ + 29 01 00 00 00 00 03 F0 5A 5A + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2340) */ + 11 00 00 89 30 80 09 24 + 04 38 00 1E 02 1C 02 1C + 02 00 02 0E 00 20 02 E3 + 00 07 00 0C 03 50 03 64 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 29 01 00 00 00 00 03 F0 A5 A5 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 23 /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 09 10 B4 24 FB /* FFC Setting; 0x09 : Enable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame */ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-113mhz-osc-dsi-on-command = [ + /* DSC Setting */ + 29 01 00 00 00 00 03 F0 5A 5A + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2340) */ + 11 00 00 89 30 80 09 24 + 04 38 00 1E 02 1C 02 1C + 02 00 02 0E 00 20 02 E3 + 00 07 00 0C 03 50 03 64 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 29 01 00 00 00 00 03 F0 A5 A5 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 23 /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 08 10 B4 24 FB /* FFC Setting; 0x08 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame */ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-113mhz-osc-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-off-command=[ + 05 01 00 00 0A 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-panel-hbm-brightness-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 53 /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM Mode ON */ + 15 01 00 00 11 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-brightness-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 53 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 11 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-hbm-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-3 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-4 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 14 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 29 01 00 00 0D 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 11 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + ]; + qcom,mdss-dsi-panel-serial-num-pre-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 37 01 00 00 05 00 02 10 00 + ]; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 00 + ]; + qcom,mdss-dsi-panel-code-info-command = [ + 06 01 00 00 00 00 01 DA 00 + ]; + qcom,mdss-dsi-panel-stage-info-command = [ + 06 01 00 00 00 00 01 DB 00 + ]; + qcom,mdss-dsi-panel-production-info-command = [ + 06 01 00 00 00 00 01 DC 00 + ]; + qcom,mdss-dsi-panel-serial-num-post-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-aod-off-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 29 01 00 00 00 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command = [ + /*Level2 key Enable*/ + 29 01 00 00 00 00 03 F0 5A 5A + //07 01 00 00 00 00 01 01 + //29 00 00 00 00 00 05 2A 00 00 05 9F + //29 00 00 00 00 00 05 2B 00 00 0C 2F + /*OTP key Enable*/ + 29 01 00 00 00 00 03 F1 F1 A2 + 29 01 00 00 00 00 0D C1 00 00 00 06 00 00 00 00 00 00 00 05 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0C C1 00 00 00 01 40 02 00 00 00 00 10 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0E C1 00 00 00 6B 00 00 00 0A 00 00 00 05 01 + 15 01 00 00 00 00 02 B0 07 + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command = [ + 15 01 00 00 00 00 02 C0 03 + 15 01 00 00 00 00 02 B0 08 + ]; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command = [ + /*13th Parameter : 1byte Read value*/ + 06 01 00 00 00 00 02 FB 00 + ]; + qcom,mdss-dsi-panel-level2-key-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command = [ + 37 01 00 00 05 00 02 87 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command = [ + 06 01 00 00 00 00 02 C8 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command = [ + 37 01 00 00 00 00 02 B4 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command = [ + 06 01 00 00 00 00 02 C9 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command = [ + 37 01 00 00 00 00 02 2F 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command = [ + 06 01 00 00 00 00 02 B3 00 + ]; + qcom,mdss-dsi-panel-level2-key-disable-command = [ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-night-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 39 01 00 0A 00 00 16 67 BB 0E 04 3E D8 12 09 05 EA 41 E2 D0 E5 09 F6 D0 D0 11 F8 FE DC + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-p3-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 E0 03 00 11 E2 01 0D 08 E5 1A FA FC E5 09 F6 EA F3 01 FE FF F7 + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 03 67 00 01 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 81 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 FF 6D + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-disable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 A1 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 28 28 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-srgb-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command = [ + 15 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 0A 00 02 B0 02 + 29 01 00 00 0A 00 16 67 FF 05 00 0B EB 00 07 00 FF 14 F8 EA F0 03 F5 DE F5 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-seed-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 D3 03 00 11 E4 01 0B 06 F0 1A FA FC E5 09 F6 EA F3 01 FC FF EA + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-seed-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-customer-p3-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-customer-srgb-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-loading-effect-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-loading-effect-disable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-p3-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-night-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-dci-p3-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-aod-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-pre-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-code-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-state-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-production-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-post-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-brightness-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-brightness-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-3-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-4-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-disable-command-state = "dsi_lp_mode"; + qcom,panel-roi-alignment=<540 60 540 60 540 60>; + qcom,compression-mode = "dsc"; + qcom,lm-split = <540 540>; + qcom,mdss-dsc-encoders = <2>; + qcom,mdss-dsc-slice-height = <60>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@3{ + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,mdss-mdp-transfer-time-us = <8000>; //for 90fps + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3120>; + qcom,mdss-dsi-h-front-porch = <16>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <4>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 00]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-id1-command = [06 01 00 00 00 00 02 0A 00]; + qcom,mdss-dsi-panel-id2-command = [06 01 00 00 00 00 02 0E 00]; + qcom,mdss-dsi-panel-id3-command = [06 01 00 00 00 00 02 0F 00]; + qcom,mdss-dsi-panel-id4-command = [06 01 00 00 00 00 02 C4 00]; + qcom,mdss-dsi-panel-id5-command = [06 01 00 00 00 00 02 E7 00]; + qcom,mdss-dsi-panel-id6-command = [06 01 00 00 00 00 02 EA 00]; + qcom,mdss-dsi-panel-id7-command = [06 01 00 00 00 00 02 FB 00]; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 F0 5A 5A]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-panel-read-esd-registed-longread-command = [ + 37 01 00 00 05 00 02 22 00 + ]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-esd-registed-longread-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-timing-switch-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + //29 01 00 00 00 00 03 9F A5 A5 + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 29 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + //29 01 00 00 00 00 03 9F 5A 5A + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-on-command = [ + /* DSC Setting */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 39 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 39 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 09 10 B4 24 FB /* FFC Setting; 0x09 : Enable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame*/ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-113mhz-osc-dsi-on-command = [ + /* DSC Setting */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 39 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 39 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 08 10 B4 24 FB /* FFC Setting; 0x08 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame*/ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-113mhz-osc-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-off-command=[ + 05 01 00 00 0A 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-panel-hbm-brightness-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 53 /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM Mode ON */ + 15 01 00 00 0C 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-brightness-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 53 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 0C 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-hbm-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-3 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-4 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 10 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 29 01 00 00 0C 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-serial-num-pre-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 37 01 00 00 05 00 02 10 00 + ]; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 00 + ]; + qcom,mdss-dsi-panel-code-info-command = [ + 06 01 00 00 00 00 01 DA 00 + ]; + qcom,mdss-dsi-panel-stage-info-command = [ + 06 01 00 00 00 00 01 DB 00 + ]; + qcom,mdss-dsi-panel-production-info-command = [ + 06 01 00 00 00 00 01 DC 00 + ]; + qcom,mdss-dsi-panel-serial-num-post-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-aod-off-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 29 01 00 00 00 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command = [ + /*Level2 key Enable*/ + 29 01 00 00 00 00 03 F0 5A 5A + //07 01 00 00 00 00 01 01 + //29 00 00 00 00 00 05 2A 00 00 05 9F + //29 00 00 00 00 00 05 2B 00 00 0C 2F + /*OTP key Enable*/ + 29 01 00 00 00 00 03 F1 F1 A2 + 29 01 00 00 00 00 0D C1 00 00 00 06 00 00 00 00 00 00 00 05 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0C C1 00 00 00 01 40 02 00 00 00 00 10 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0E C1 00 00 00 6B 00 00 00 0A 00 00 00 05 01 + 15 01 00 00 00 00 02 B0 07 + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command = [ + 15 01 00 00 00 00 02 C0 03 + 15 01 00 00 00 00 02 B0 08 + ]; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command = [ + /*13th Parameter : 1byte Read value*/ + 06 01 00 00 00 00 02 FB 00 + ]; + qcom,mdss-dsi-panel-level2-key-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command = [ + 37 01 00 00 00 00 02 87 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command = [ + 06 01 00 00 00 00 02 C8 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command = [ + 37 01 00 00 00 00 02 B4 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command = [ + 06 01 00 00 00 00 02 C9 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command = [ + 37 01 00 00 00 00 02 2F 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command = [ + 06 01 00 00 00 00 02 B3 00 + ]; + qcom,mdss-dsi-panel-level2-key-disable-command = [ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-night-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 39 01 00 0A 00 00 16 67 BB 0E 04 3E D8 12 09 05 EA 41 E2 D0 E5 09 F6 D0 D0 11 F8 FE DC + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-p3-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 E0 03 00 11 E2 01 0D 08 E5 1A FA FC E5 09 F6 EA F3 01 FE FF F7 + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 03 67 00 01 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 81 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 FF 6D + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-disable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 A1 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 28 28 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-srgb-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command = [ + 15 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 0A 00 02 B0 02 + 29 01 00 00 0A 00 16 67 FF 05 00 0B EB 00 07 00 FF 14 F8 EA F0 03 F5 DE F5 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-seed-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 D3 03 00 11 E4 01 0B 06 F0 1A FA FC E5 09 F6 EA F3 01 FC FF EA + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-seed-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-customer-p3-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-customer-srgb-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-loading-effect-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-loading-effect-disable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-p3-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-night-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-dci-p3-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-aod-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-pre-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-code-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-state-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-production-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-post-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-brightness-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-brightness-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-3-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-4-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-disable-command-state = "dsi_lp_mode"; + qcom,panel-roi-alignment=<720 65 720 65 720 65>; + qcom,compression-mode = "dsc"; + qcom,lm-split = <720 720>; + qcom,mdss-dsc-encoders = <2>; + qcom,mdss-dsc-slice-height = <65>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + }; + }; +}; + +&dsi_samsung_oneplus_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; + qcom,platform-reset-gpio-tmo = <&tlmm 78 0>; + qcom,platform-poc-gpio = <&tlmm 130 0>; + qcom,tp1v8-gpio = <&tlmm 119 0>; +}; + +&soc { + dsi_samsung_oneplus_dsc_cmd_display { + qcom,dsi-display-active; + }; +}; + +&dsi_samsung_oneplus_dsc_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { /* wqhd 60hz */ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment=<720 65 720 65 720 65>; + }; + timing@1 { /* fhd 90hz */ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment=<540 60 540 60 540 60>; + }; + timing@2 { /* fhd 60hz */ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment=<540 60 540 60 540 60>; + }; + timing@3 { /* wqhd 90hz */ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment=<720 65 720 65 720 65>; + }; + }; +}; + + diff --git a/arch/arm/boot/dts/qcom/dsi-panel-samsung_s6e3fc2x01.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-samsung_s6e3fc2x01.dtsi new file mode 100644 index 000000000000..bd7245490744 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-samsung_s6e3fc2x01.dtsi @@ -0,0 +1,435 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_samsung_s6e3fc2x01_cmd: qcom,mdss_dsi_samsung_s6e3fc2x01_cmd { + qcom,mdss-dsi-panel-name = "samsung s6e3fc2x01 cmd mode dsi panel"; + qcom,mdss-dsi-panel-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-version = "S6E3FC2X01"; + qcom,mdss-dsi-backlight-version = "SAMSUNG"; + qcom,mdss-dsi-backlight-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-reset-sequence = <1 7>, <0 1>, <1 5>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <145>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + //qcom,mdss-dsi-te-check-enable; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 08]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-high-brightness-panel; + qcom,mdss-dsi-acl-cmd-index = <0>; + qcom,mdss-dsi-acl-mode-index = <1>; + qcom,mdss-bl-high2bit; + //qcom,mdss-dsi-panel-status-check-mode = "te_signal_check"; + qcom,mdss-dsi-panel-seria-num-year-index = <12>; + qcom,mdss-dsi-panel-seria-num-mon-index = <12>; + qcom,mdss-dsi-panel-seria-num-day-index = <13>; + qcom,mdss-dsi-panel-seria-num-hour-index = <14>; + qcom,mdss-dsi-panel-seria-num-min-index = <15>; + qcom,mdss-dsi-panel-seria-num-sec-index = <16>; + qcom,ulps-enabled; + qcom,mdss-brightness-max-level = <1023>; + /* HDR Setting */ + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15635 16450 34000 16000 13250 34500 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <8000000>; + qcom,mdss-dsi-panel-average-brightness = <2000000>; + qcom,mdss-dsi-panel-blackness-level = <5>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <72>; + qcom,mdss-dsi-h-back-porch = <36>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <32>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <1037000000>;// 518.5MHZ + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 05 00 02 11 00 + 39 01 00 00 00 00 03 9F 5A 5A + /*FD setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 01 + 15 01 00 00 00 00 02 CD 01 + 39 01 00 00 0F 00 03 F0 A5 A5 + /*TE ON*/ + 39 01 00 00 00 00 03 9F A5 A5 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 9F 5A 5A + /*MIC Setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 08 EB 17 41 92 0E 10 82 5A + 39 01 00 00 00 00 03 F0 A5 A5 + /*CASET/PASET*/ + 39 01 00 00 00 00 05 2A 00 00 04 37 + 39 01 00 00 00 00 05 2B 00 00 09 23 + /*TSP H_sync Setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 09 + 39 01 00 00 00 00 03 E8 10 30 + 39 01 00 00 00 00 03 F0 A5 A5 + /*Dimming Setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B7 01 + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 00 00 02 B7 12 + 39 01 00 00 00 00 03 F0 A5 A5 + /*ESD improvement Setting*/ + 39 01 00 00 00 00 03 FC 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 02 E3 88 + 39 01 00 00 00 00 02 B0 07 + 39 01 00 00 00 00 02 ED 67 + 39 01 00 00 00 00 03 FC A5 A5 + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 F0 A5 A5 + /*ACL off*/ + 39 01 00 00 01 00 02 55 00 + /*SEED OFF*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 B1 00 01 + 39 01 00 00 00 00 03 F0 A5 A5 + /*SEED TCS OFF*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 B3 00 C1 + 39 01 00 00 00 00 03 F0 A5 A5 + /*Display on*/ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 00 00 02 29 00 + 39 01 00 00 00 00 03 9F 5A 5A + ]; + qcom,mdss-dsi-off-command = [ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 0A 00 01 28 + 05 01 00 00 00 00 01 10 + 39 01 00 00 00 00 03 9F 5A 5A + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 F4 01 + 39 01 00 00 96 00 03 F0 A5 A5 + ]; + //qcom,mdss-dsi-post-on-backlight=[ + // 39 01 00 00 00 00 03 9F A5 A5 + // 05 01 00 00 00 00 01 29 + // 39 01 00 00 00 00 03 9F 5A 5A + //]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + /**************************************************************/ + qcom,mdss-dsi-panel-hbm-brightness-on-command = [ + /*HBM ON */ + 39 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 53 E0 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-brightness-off-command = [ + /* DLY ON */ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 04 B7 00 01 5B + 39 00 00 00 00 00 03 F0 A5 A5 + + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /*ELVSS OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 08 + 15 00 00 00 00 00 02 B7 12 + 39 01 00 00 10 00 03 F0 A5 A5 + /*DLY OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 04 B7 00 01 5B + 39 00 00 00 00 00 03 F0 A5 A5 + /*HBM ON */ + 15 00 00 00 00 00 02 53 E0 + 39 01 00 00 0E 00 03 51 03 FF + /*HBM 670nit*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 BD 00 00 + 39 00 00 00 00 00 03 F0 A5 A5 + /*DLY OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 04 B7 00 01 53 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /*HBM 670nit off*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 BD 00 02 + 39 00 00 00 00 00 03 F0 A5 A5 + /*HBM off */ + 15 01 00 00 00 00 02 53 20 + ]; + qcom,mdss-dsi-panel-hbm-max-brightness-command-on = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B7 7F + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 80 00 02 B7 92 + 39 01 00 00 40 00 02 53 E8 + 39 01 00 00 80 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 51 03 FF + ]; + qcom,mdss-dsi-panel-hbm-max-brightness-command-off = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 40 00 02 B7 7F + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 40 00 02 B7 92 + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 10 00 02 53 28 + ]; + qcom,mdss-dsi-panel-hbm-brightness-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-brightness-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-max-brightness-command-on-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-max-brightness-command-off-state = "dsi_lp_mode"; + qcom,mdss-dsi-hbm-off-command-state = "dsi_hs_mode"; + + qcom,mdss-dsi-panel-aod-on-command-1 = [ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 0A 00 01 28 + 05 01 00 00 78 00 01 10 + 05 01 00 00 05 00 01 11 + 39 01 00 00 00 00 03 9F 5A 5A + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 01 + 15 01 00 00 64 00 02 CD 02 + 15 01 00 00 00 00 02 53 23 + 15 01 00 00 00 00 02 B0 A5 + 15 01 00 00 00 00 02 C7 00 + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 00 00 01 29 + 39 01 00 00 00 00 03 9F 5A 5A + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + + ]; + + qcom,mdss-dsi-panel-aod-off-command = [ + /*ELVSS OFF*/ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 08 + /*DLY OFF*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 04 B7 00 01 5B + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 01 + 15 01 00 00 00 00 02 CD 01 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 F0 A5 A5 + /*DLY ON*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 04 B7 00 01 53 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + + ]; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + /*ELVSS OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 08 + 15 00 00 00 00 00 02 B7 12 + 39 00 00 00 00 00 03 F0 A5 A5 + /*DL0 OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 04 B7 00 01 5B + 39 00 00 00 00 00 03 F0 A5 A5 + /*HB0 ON */ + 15 00 00 00 00 00 02 53 E0 + 39 01 00 00 00 00 03 51 03 FF + /*HB0 670nit*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 BD 00 00 + 39 01 00 00 00 00 03 F0 A5 A5 + /*DL0 OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 04 B7 00 01 53 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + /*HBM 670nit off*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 BD 00 02 + 39 00 00 00 00 00 03 F0 A5 A5 + /*HBM off */ + 15 01 00 00 00 00 02 53 20 + ]; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command = [ + + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 CE 01 02 1D E3 00 07 0D E9 28 FD F0 D3 0A E2 EA EA 01 FF FF F2 + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + + ]; + qcom,mdss-dsi-panel-display-p3-mode-on-command = [ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 CE 01 02 1D E3 00 07 0D E9 28 FD F0 D3 0A E2 EA EA 01 FF FF F2 + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command = [ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + + ]; + qcom,mdss-dsi-customer-srgb-enable-command = [ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 CE 01 02 1D E3 00 07 0D E9 28 FD F0 D3 0A E2 EA EA 01 FF FF F2 + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command = [ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF F2 + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-customer-srgb-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-p3-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-aod-mode-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 + ]; + + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0E 08]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id-command = [06 01 00 01 05 00 02 DC 08]; + qcom,mdss-dsi-panel-id-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id1-command = [06 01 00 01 05 00 02 0A 08]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command = [06 01 00 01 05 00 02 0E 08]; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command = [06 01 00 01 05 00 02 E0 08]; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command = [06 01 00 01 05 00 02 0F 08]; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command = [06 01 00 01 05 00 02 E3 08]; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command = [06 01 00 01 05 00 02 E5 08]; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command = [06 01 00 01 05 00 02 FB 08]; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-level1-command = [15 01 00 00 00 00 02 B0 08]; + qcom,mdss-dsi-panel-hbm-level1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-read-command = [06 01 00 01 05 00 02 B7 08]; + qcom,mdss-dsi-panel-hbm-read-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 FC 5A 5A]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 FC A5 A5]; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + }; + }; + }; +}; + +&dsi_samsung_s6e3fc2x01_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; + qcom,platform-poc-gpio = <&tlmm 130 0>; + qcom,tp1v8-gpio = <&tlmm 119 0>; +}; + +&soc { + dsi_samsung_s6e3fc2x01_cmd_display { + qcom,dsi-display-active; + }; +}; + +&dsi_samsung_s6e3fc2x01_cmd { + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 25 23 + 09 09 06 03 04 00 1C 19]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + + diff --git a/arch/arm/boot/dts/qcom/dsi-panel-samsung_sofef00_m_video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-samsung_sofef00_m_video.dtsi new file mode 100644 index 000000000000..15a81d8158d4 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-samsung_sofef00_m_video.dtsi @@ -0,0 +1,103 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_samsung_sofef00_m_video: qcom,mdss_dsi_samsung_sofef00_m_video { + qcom,mdss-dsi-panel-name = + "samsung sofef00_m video mode dsi panel"; + qcom,mdss-dsi-panel-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-version = "SOFEF00_M"; + qcom,mdss-dsi-backlight-version = "SAMSUNG"; + qcom,mdss-dsi-backlight-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-reset-sequence = <1 5>, <0 2>, <1 12>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <145>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-high-brightness-panel; + qcom,mdss-bl-high2bit; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2280>; + qcom,mdss-dsi-h-front-porch = <112>; + qcom,mdss-dsi-h-back-porch = <36>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <12>; + qcom,mdss-dsi-v-front-porch = <36>; + qcom,mdss-dsi-v-pulse-width = <8>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + 05 01 00 00 0A 00 02 11 00 + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 F0 A5 A5 + 15 01 00 00 00 00 02 53 20 + 15 01 00 00 00 00 02 55 00 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 28 00 02 28 00 + 05 01 00 00 A0 00 02 10 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; + +&dsi_samsung_sofef00_m_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; + qcom,platform-reset-gpio-tmo = <&tlmm 78 0>; +}; + +&soc { + dsi_samsung_sofef00_m_video_display { + qcom,dsi-display-active; + }; +}; + +&dsi_samsung_sofef00_m_video { + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 20 07 07 0c 12 06 + 08 06 03 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-sharp-1080p-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-sharp-1080p-cmd.dtsi new file mode 100644 index 000000000000..aebc8b924182 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-sharp-1080p-cmd.dtsi @@ -0,0 +1,86 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_sharp_1080_cmd: qcom,mdss_dsi_sharp_1080p_cmd { + qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel"; + qcom,mdss-dsi-panel-controller = <&mdss_dsi0>; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-destination = "display_1"; + qcom,mdss-dsi-panel-clockrate = <850000000>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <64>; + qcom,mdss-pan-physical-height-dimension = <117>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 28 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-sharp-dsc-4k-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-sharp-dsc-4k-cmd.dtsi new file mode 100644 index 000000000000..92897aee929e --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-sharp-dsc-4k-cmd.dtsi @@ -0,0 +1,103 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_sharp_4k_dsc_cmd: qcom,mdss_dsi_sharp_4k_dsc_cmd { + qcom,mdss-dsi-panel-name = "Sharp 4k cmd mode dsc dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 100>, <0 100>, <1 100>; + qcom,mdss-pan-physical-width-dimension = <71>; + qcom,mdss-pan-physical-height-dimension = <129>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,dcs-cmd-by-left; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-jitter = <0x8 0xa>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <1080>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-sharp-dsc-4k-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-sharp-dsc-4k-video.dtsi new file mode 100644 index 000000000000..9995fb3e79bc --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-sharp-dsc-4k-video.dtsi @@ -0,0 +1,96 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_sharp_4k_dsc_video: qcom,mdss_dsi_sharp_4k_dsc_video { + qcom,mdss-dsi-panel-name = "Sharp 4k video mode dsc dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 100>, <0 100>, <1 100>; + qcom,mdss-pan-physical-width-dimension = <71>; + qcom,mdss-pan-physical-height-dimension = <129>; + qcom,mdss-dsi-tx-eot-append; + + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 10 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <1080>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi new file mode 100644 index 000000000000..6af3e36acbd2 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi @@ -0,0 +1,93 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_dual_sharp_wqhd_cmd: qcom,mdss_dsi_sharp_wqhd_cmd { + qcom,mdss-dsi-panel-name = + "Dual Sharp WQHD cmd mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 20>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,dcs-cmd-by-left; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <121>; + + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 + 20 00 20 02 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 15 01 00 00 00 00 02 90 01 + 15 01 00 00 00 00 02 03 00 + 15 01 00 00 00 00 02 58 01 + 15 01 00 00 00 00 02 c9 00 + 15 01 00 00 00 00 02 c0 15 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-sharp-dualdsi-wqhd-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-sharp-dualdsi-wqhd-video.dtsi new file mode 100644 index 000000000000..2f8fdb57f6e0 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-sharp-dualdsi-wqhd-video.dtsi @@ -0,0 +1,89 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_dual_sharp_wqhd_video: qcom,mdss_dsi_sharp_wqhd_video { + qcom,mdss-dsi-panel-name = + "Dual Sharp wqhd video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 20>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <121>; + + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 + 20 00 20 02 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 10 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 15 01 00 00 00 00 02 90 01 + 15 01 00 00 00 00 02 03 00 + 15 01 00 00 00 00 02 58 01 + 15 01 00 00 00 00 02 c9 00 + 15 01 00 00 00 00 02 c0 15 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + }; + }; + }; +}; + diff --git a/arch/arm/boot/dts/qcom/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi new file mode 100644 index 000000000000..6dc621ed8922 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi @@ -0,0 +1,633 @@ +/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_dual_sharp_1080_120hz_cmd: qcom,mdss_dual_sharp_1080p_120hz_cmd { + qcom,mdss-dsi-panel-name = + "sharp 1080p 120hz dual dsi cmd mode panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 10>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,cmd-sync-wait-broadcast; + qcom,cmd-sync-wait-trigger; + qcom,mdss-tear-check-frame-rate = <12000>; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <28>; + qcom,mdss-dsi-h-back-porch = <4>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <12>; + qcom,mdss-dsi-v-front-porch = <12>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-on-command = + [15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 ba 07 + 15 01 00 00 00 00 02 c0 00 + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 d9 00 + 15 01 00 00 00 00 02 ef 70 + 15 01 00 00 00 00 02 f7 80 + 39 01 00 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00 02 c9 02 + 15 01 00 00 00 00 02 ca 0d + 15 01 00 00 00 00 02 cb 02 + 15 01 00 00 00 00 02 cc 4a + 15 01 00 00 00 00 02 cd 02 + 15 01 00 00 00 00 02 ce 4c + 15 01 00 00 00 00 02 cf 02 + 15 01 00 00 00 00 02 d0 85 + 15 01 00 00 00 00 02 d1 02 + 15 01 00 00 00 00 02 d2 c3 + 15 01 00 00 00 00 02 d3 02 + 15 01 00 00 00 00 02 d4 e9 + 15 01 00 00 00 00 02 d5 03 + 15 01 00 00 00 00 02 d6 16 + 15 01 00 00 00 00 02 d7 03 + 15 01 00 00 00 00 02 d8 34 + 15 01 00 00 00 00 02 d9 03 + 15 01 00 00 00 00 02 da 56 + 15 01 00 00 00 00 02 db 03 + 15 01 00 00 00 00 02 dc 62 + 15 01 00 00 00 00 02 dd 03 + 15 01 00 00 00 00 02 de 6c + 15 01 00 00 00 00 02 df 03 + 15 01 00 00 00 00 02 e0 74 + 15 01 00 00 00 00 02 e1 03 + 15 01 00 00 00 00 02 e2 80 + 15 01 00 00 00 00 02 e3 03 + 15 01 00 00 00 00 02 e4 89 + 15 01 00 00 00 00 02 e5 03 + 15 01 00 00 00 00 02 e6 8b + 15 01 00 00 00 00 02 e7 03 + 15 01 00 00 00 00 02 e8 8d + 15 01 00 00 00 00 02 e9 03 + 15 01 00 00 00 00 02 ea 8e + 15 01 00 00 00 00 02 FF 10 + 05 01 00 00 00 00 01 29]; + qcom,mdss-dsi-off-command = + [15 01 00 00 00 00 02 ff 10 + 05 01 00 00 10 00 01 28 + 15 01 00 00 00 00 02 b0 00 + 05 01 00 00 40 00 01 10 + 15 01 00 00 00 00 02 4f 01]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-sharp-split-link-wuxga-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-sharp-split-link-wuxga-video.dtsi new file mode 100644 index 000000000000..b778066a0950 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-sharp-split-link-wuxga-video.dtsi @@ -0,0 +1,74 @@ +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_sharp_split_link_wuxga_video: + qcom,mdss_dsi_sharp_split_link_wuxga_video { + qcom,mdss-dsi-panel-name = + "sharp split link video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-reset-sequence = <1 2>, <0 5>, <1 120>; + qcom,mdss-pan-physical-width-dimension = <83>; + qcom,mdss-pan-physical-height-dimension = <133>; + qcom,split-link-enabled; + qcom,sublinks-count = <2>; + qcom,lanes-per-sublink = <2>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <600>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <54>; + qcom,mdss-dsi-h-back-porch = <4>; + qcom,mdss-dsi-h-pulse-width = <6>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <6>; + qcom,mdss-dsi-v-front-porch = <12>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = + [05 01 00 00 a0 00 02 11 00]; + qcom,mdss-dsi-post-panel-on-command = + [05 01 00 00 a0 00 02 29 00]; + qcom,mdss-dsi-off-command = + [05 01 00 00 02 00 02 28 00 + 05 01 00 00 a0 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-timings = + [00 24 07 08 0e 14 07 09 07 03 04 00]; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-sim-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-sim-cmd.dtsi new file mode 100644 index 000000000000..c49583e0d92a --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-sim-cmd.dtsi @@ -0,0 +1,220 @@ +/* Copyright (c) 2014-2015, 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_sim_cmd: qcom,mdss_dsi_sim_cmd{ + qcom,mdss-dsi-panel-name = "Simulator cmd mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-t-clk-post = <0x03>; + qcom,mdss-dsi-t-clk-pre = <0x27>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,panel-ack-disabled; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <100>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-timings = + [00 21 09 09 24 23 08 08 08 03 04 00]; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1{ + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <460>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <740>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-timings = + [00 21 09 09 24 23 08 08 08 03 04 00]; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2{ + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <840>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <1380>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-timings = + [00 21 09 09 24 23 08 08 08 03 04 00]; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-sim-dsc375-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-sim-dsc375-cmd.dtsi new file mode 100644 index 000000000000..ceb68568fa9f --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-sim-dsc375-cmd.dtsi @@ -0,0 +1,286 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_sim_dsc_375_cmd: qcom,mdss_dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-panel-name = + "Simulator cmd mode DSC 3.75:1 dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-ack-disabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1e + 15 01 00 00 00 00 02 0b 73 + 15 01 00 00 00 00 02 0c 73 + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f aE + 15 01 00 00 00 00 02 11 b8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5a 00 + 15 01 00 00 00 00 02 5b 01 + 15 01 00 00 00 00 02 5c 80 + 15 01 00 00 00 00 02 5d 81 + 15 01 00 00 00 00 02 5e 00 + 15 01 00 00 00 00 02 5f 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1c + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0f + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8a + 15 01 00 00 00 00 02 0a 13 + 15 01 00 00 00 00 02 0b 13 + 15 01 00 00 00 00 02 0c 15 + 15 01 00 00 00 00 02 0d 15 + 15 01 00 00 00 00 02 0e 17 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 1c + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0f + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8a + 15 01 00 00 00 00 02 1a 13 + 15 01 00 00 00 00 02 1b 13 + 15 01 00 00 00 00 02 1c 15 + 15 01 00 00 00 00 02 1d 15 + 15 01 00 00 00 00 02 1e 17 + 15 01 00 00 00 00 02 1f 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 e0 00 + 15 01 00 00 00 00 02 dc 21 + 15 01 00 00 00 00 02 dd 22 + 15 01 00 00 00 00 02 de 07 + 15 01 00 00 00 00 02 df 07 + 15 01 00 00 00 00 02 e3 6d + 15 01 00 00 00 00 02 e1 07 + 15 01 00 00 00 00 02 e2 07 + /* UD */ + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + /* CLK */ + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 7f 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0a + 15 01 00 00 00 00 02 94 0a + /* Inversion Type */ + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b ff + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9d b0 + 15 01 00 00 00 00 02 9f 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 ec 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VESA DSC PPS settings + * (1440x2560 slide 16H) + */ + 39 01 00 00 00 00 11 c1 09 + 20 00 10 02 00 02 68 01 bb + 00 0a 06 67 04 c5 + + 39 01 00 00 00 00 03 c2 10 f0 + /* C0h = 0x0(2 Port SDC) + * 0x01(1 PortA FBC) + * 0x02(MTK) 0x03(1 PortA VESA) + */ + 15 01 00 00 00 00 02 c0 03 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3b 03 0a 0a + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 e5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 bb 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 fb 01 + /* SlpOut + DispOn */ + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + timing@1 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 28 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-sim-dualmipi-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-sim-dualmipi-cmd.dtsi new file mode 100644 index 000000000000..0b0b087994a0 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-sim-dualmipi-cmd.dtsi @@ -0,0 +1,146 @@ +/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_dual_sim_cmd: qcom,mdss_dsi_dual_sim_cmd { + qcom,mdss-dsi-panel-name = "Sim dual cmd mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,cmd-sync-wait-broadcast; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-hor-line-idle = <0 40 256>, + <40 120 128>, + <120 240 64>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-ack-disabled; + qcom,mdss-dsi-qsync-min-refresh-rate = <45>; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <28>; + qcom,mdss-dsi-h-back-porch = <4>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <12>; + qcom,mdss-dsi-v-front-porch = <12>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-on-command = + [/* exit sleep mode, wait 0ms */ + 05 01 00 00 00 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + }; + timing@1{ + qcom,mdss-dsi-panel-width = <1280>; + qcom,mdss-dsi-panel-height = <1440>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <44>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = + [/* exit sleep mode, wait 0ms */ + 05 01 00 00 00 00 01 29]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + }; + timing@2{ + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <40>; + qcom,mdss-dsi-on-command = + [/* exit sleep mode, wait 0ms */ + 05 01 00 00 00 00 01 29]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi new file mode 100644 index 000000000000..5d977e7cb675 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi @@ -0,0 +1,281 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_dual_sim_dsc_375_cmd: qcom,mdss_dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-panel-name = + "Sim dual cmd mode DSC 3.75:1 dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,cmd-sync-wait-broadcast; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-hor-line-idle = <0 40 256>, + <40 120 128>, + <120 240 64>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-ack-disabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <1080>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + timing@1 { + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 FF 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1E + 15 01 00 00 00 00 02 0B 73 + 15 01 00 00 00 00 02 0C 73 + 15 01 00 00 00 00 02 0E B0 + 15 01 00 00 00 00 02 0F AE + 15 01 00 00 00 00 02 11 B8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5A 00 + 15 01 00 00 00 00 02 5B 01 + 15 01 00 00 00 00 02 5C 80 + 15 01 00 00 00 00 02 5D 81 + 15 01 00 00 00 00 02 5E 00 + 15 01 00 00 00 00 02 5F 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1C + 15 01 00 00 00 00 02 01 0B + 15 01 00 00 00 00 02 02 0C + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0F + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8A + 15 01 00 00 00 00 02 0A 13 + 15 01 00 00 00 00 02 0B 13 + 15 01 00 00 00 00 02 0C 15 + 15 01 00 00 00 00 02 0D 15 + 15 01 00 00 00 00 02 0E 17 + 15 01 00 00 00 00 02 0F 17 + 15 01 00 00 00 00 02 10 1C + 15 01 00 00 00 00 02 11 0B + 15 01 00 00 00 00 02 12 0C + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0F + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8A + 15 01 00 00 00 00 02 1A 13 + 15 01 00 00 00 00 02 1B 13 + 15 01 00 00 00 00 02 1C 15 + 15 01 00 00 00 00 02 1D 15 + 15 01 00 00 00 00 02 1E 17 + 15 01 00 00 00 00 02 1F 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6D + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 E0 00 + 15 01 00 00 00 00 02 DC 21 + 15 01 00 00 00 00 02 DD 22 + 15 01 00 00 00 00 02 DE 07 + 15 01 00 00 00 00 02 DF 07 + 15 01 00 00 00 00 02 E3 6D + 15 01 00 00 00 00 02 E1 07 + 15 01 00 00 00 00 02 E2 07 + /* UD */ + 15 01 00 00 00 00 02 29 D8 + 15 01 00 00 00 00 02 2A 2A + /* CLK */ + 15 01 00 00 00 00 02 4B 03 + 15 01 00 00 00 00 02 4C 11 + 15 01 00 00 00 00 02 4D 10 + 15 01 00 00 00 00 02 4E 01 + 15 01 00 00 00 00 02 4F 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5B 43 + 15 01 00 00 00 00 02 5C 00 + 15 01 00 00 00 00 02 5F 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7A 80 + 15 01 00 00 00 00 02 7B 91 + 15 01 00 00 00 00 02 7C D8 + 15 01 00 00 00 00 02 7D 60 + 15 01 00 00 00 00 02 7F 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 B3 C0 + 15 01 00 00 00 00 02 B4 00 + 15 01 00 00 00 00 02 B5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0A + 15 01 00 00 00 00 02 94 0A + /* Inversion Type */ + 15 01 00 00 00 00 02 8A 00 + 15 01 00 00 00 00 02 9B FF + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9D B0 + 15 01 00 00 00 00 02 9F 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 EC 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3B 03 0A 0A + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 E5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 BB 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 FB 01 + /* SlpOut + DispOn */ + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-sim-dualmipi-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-sim-dualmipi-video.dtsi new file mode 100644 index 000000000000..f06e26b30e09 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-sim-dualmipi-video.dtsi @@ -0,0 +1,70 @@ +/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_dual_sim_vid: qcom,mdss_dsi_dual_sim_video { + qcom,mdss-dsi-panel-name = "Sim dual video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-panel-broadcast-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 200>, <1 20>; + qcom,panel-ack-disabled; + qcom,mdss-dsi-qsync-min-refresh-rate = <45>; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1280>; + qcom,mdss-dsi-panel-height = <1440>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <44>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-sim-sec-hd-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-sim-sec-hd-cmd.dtsi new file mode 100644 index 000000000000..a697c2098bb5 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-sim-sec-hd-cmd.dtsi @@ -0,0 +1,75 @@ +/* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_sim_sec_hd_cmd: qcom,mdss_dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-panel-name = + "sim hd command mode secondary dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,panel-ack-disabled; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-post-init-delay = <1>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <60>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <2>; + qcom,mdss-dsi-v-front-porch = <12>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + + qcom,mdss-dsi-on-command = [ + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-sim-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-sim-video.dtsi new file mode 100644 index 000000000000..40bedd0e462c --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-sim-video.dtsi @@ -0,0 +1,69 @@ +/* Copyright (c) 2012-2015, 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_sim_vid: qcom,mdss_dsi_sim_video { + qcom,mdss-dsi-panel-name = "Simulator video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-t-clk-post = <0x04>; + qcom,mdss-dsi-t-clk-pre = <0x1b>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 0>, <0 0>, <1 0>; + qcom,panel-ack-disabled; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <640>; + qcom,mdss-dsi-panel-height = <480>; + qcom,mdss-dsi-h-front-porch = <8>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <6>; + qcom,mdss-dsi-v-front-porch = <6>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-timings = + [00 00 00 00 00 00 00 00 00 00 00 00]; + qcom,mdss-dsi-on-command = + [32 01 00 00 00 00 02 00 00]; + qcom,mdss-dsi-off-command = + [22 01 00 00 00 00 02 00 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi new file mode 100644 index 000000000000..ae15eddd7f48 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi @@ -0,0 +1,111 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_sw43404_amoled_fhd_plus_cmd: qcom,mdss_dsi_sw43404_fhd_plus_cmd { + qcom,mdss-dsi-panel-name = + "sw43404 amoled boe fhd+ panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <138>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2160>; + qcom,mdss-dsi-h-front-porch = <160>; + qcom,mdss-dsi-h-back-porch = <72>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x3 0x1>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 03 b0 a5 00 + 07 01 00 00 00 00 02 01 00 + 0a 01 00 00 00 00 80 11 00 00 89 30 80 + 08 70 04 38 02 1c 02 1c 02 1c 02 00 + 02 0e 00 20 34 29 00 07 00 0C 00 2e + 00 31 18 00 10 F0 03 0C 20 00 06 0B + 0B 33 0E 1C 2A 38 46 54 62 69 70 77 + 79 7B 7D 7E 01 02 01 00 09 40 09 BE + 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6 + 2A F6 2B 34 2B 74 3B 74 6B F4 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 + 39 01 00 00 00 00 03 b0 a5 00 + 15 01 00 00 00 00 02 5e 10 + 39 01 00 00 00 00 06 b9 bf 11 40 00 30 + 39 01 00 00 00 00 09 F8 00 08 10 08 2D + 00 00 2D + 15 01 00 00 00 00 02 55 08 + 05 01 00 00 1e 00 02 11 00 + 15 01 00 00 78 00 02 3d 01 + 39 01 00 00 00 00 03 b0 a5 00 + 05 01 00 00 78 00 02 35 00 + 05 01 00 00 3c 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <270>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi new file mode 100644 index 000000000000..ade94b284b03 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi @@ -0,0 +1,130 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_sw43404_amoled_cmd: qcom,mdss_dsi_sw43404_amoled_wqhd_cmd { + qcom,mdss-dsi-panel-name = + "sw43404 amoled cmd mode dsi boe panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-qsync-min-refresh-rate = <55>; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2880>; + qcom,mdss-dsi-h-front-porch = <60>; + qcom,mdss-dsi-h-back-porch = <30>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x7 0x1>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 03 b0 a5 00 + 39 01 00 00 00 00 03 5c 42 00 + 07 01 00 00 00 00 02 01 00 + 0a 01 00 00 00 00 80 11 00 00 89 30 80 + 0B 40 05 A0 05 A0 02 D0 02 D0 02 00 + 02 68 00 20 9A DB 00 0A 00 0C 00 12 + 00 0E 18 00 10 F0 03 0C 20 00 06 0B + 0B 33 0E 1C 2A 38 46 54 62 69 70 77 + 79 7B 7D 7E 01 02 01 00 09 40 09 BE + 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6 + 2A F6 2B 34 2B 74 3B 74 6B F4 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 + 39 01 00 00 00 00 03 b0 a5 00 + 39 01 00 00 00 00 09 F8 00 08 10 08 2D + 00 00 2D + 15 01 00 00 00 00 02 55 08 + 05 01 00 00 1e 00 02 11 00 + 39 01 00 00 00 00 03 b0 a5 00 + 15 01 00 00 00 00 02 e0 18 + 39 01 00 00 00 00 0c c0 00 53 6f 51 50 + 51 34 4f 5a 33 19 + 05 01 00 00 78 00 02 35 00 + 05 01 00 00 3c 00 02 29 00 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 5a 01]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_lp_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 5a 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_lp_mode"; + qcom,mdss-dsi-lp1-command = [ + 05 01 00 00 00 00 02 39 00 + ]; + qcom,mdss-dsi-lp1-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-nolp-command = [ + 05 01 00 00 00 00 02 38 00 + ]; + qcom,mdss-dsi-nolp-command-state = + "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <180>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi new file mode 100644 index 000000000000..88abe5006db8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi @@ -0,0 +1,95 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_sw43404_amoled_video: qcom,mdss_dsi_sw43404_amoled_wqhd_video { + qcom,mdss-dsi-panel-name = + "sw43404 amoled video mode dsi boe panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2880>; + qcom,mdss-dsi-h-front-porch = <10>; + qcom,mdss-dsi-h-back-porch = <10>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <10>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 03 b0 a5 00 + 07 01 00 00 00 00 02 01 00 + 39 01 00 00 00 00 06 b2 00 5d 04 80 49 + 15 01 00 00 00 00 02 3d 10 + 15 01 00 00 00 00 02 36 00 + 15 01 00 00 00 00 02 55 08 + 39 01 00 00 00 00 09 f8 00 08 10 08 2d + 00 00 2d + 39 01 00 00 3c 00 03 51 00 00 + 05 01 00 00 50 00 02 11 00 + 39 01 00 00 00 00 03 b0 34 04 + 39 01 00 00 00 00 05 c1 00 00 00 46 + 39 01 00 00 00 00 03 b0 a5 00 + 0a 01 00 00 00 00 80 11 00 00 89 30 80 + 0B 40 05 A0 02 d0 02 D0 02 D0 02 00 + 02 68 00 20 4e a8 00 0A 00 0C 00 23 + 00 1c 18 00 10 F0 03 0C 20 00 06 0B + 0B 33 0E 1C 2A 38 46 54 62 69 70 77 + 79 7B 7D 7E 01 02 01 00 09 40 09 BE + 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6 + 2A F6 2B 34 2B 74 3B 74 6B F4 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 + 05 01 00 00 78 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <720>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-td4328-1080p-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-td4328-1080p-cmd.dtsi new file mode 100644 index 000000000000..0c84ca1acca1 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-td4328-1080p-cmd.dtsi @@ -0,0 +1,177 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_td4328_truly_cmd: qcom,mdss_dsi_td4328_truly_cmd { + qcom,mdss-dsi-panel-name = + "td4328 cmd mode dsi truly panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2160>; + qcom,mdss-dsi-h-front-porch = <70>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <10>; + qcom,mdss-dsi-v-front-porch = <5>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-on-command = [ + 29 01 00 00 00 00 02 B0 00 + 29 01 00 00 00 00 04 B3 00 00 06 + 29 01 00 00 00 00 02 B4 00 + 29 01 00 00 00 00 06 B6 33 DB 80 12 00 + 29 01 00 00 00 00 08 B8 57 3D 19 1E 0A + 50 50 + 29 01 00 00 00 00 08 B9 6F 3D 28 3C 14 + C8 C8 + 29 01 00 00 00 00 08 BA B5 33 41 64 23 + A0 A0 + 29 01 00 00 00 00 03 BB 14 14 + 29 01 00 00 00 00 03 BC 37 32 + 29 01 00 00 00 00 03 BD 64 32 + 29 01 00 00 00 00 02 BE 04 + 29 01 00 00 00 00 02 C0 00 + 29 01 00 00 00 00 2E C1 04 48 00 00 26 + 15 19 0B 63 D2 D9 9A 73 EF BD E7 5C + 6B 93 4D 22 18 8B 2A 41 00 00 00 00 + 00 00 00 00 00 40 02 22 1B 06 03 00 + 07 FF 00 01 + 29 01 00 00 00 00 18 C2 01 F8 70 08 68 + 08 0C 10 00 08 30 00 00 00 00 00 00 + 20 02 43 00 00 00 + 29 01 00 00 00 00 3F C3 87 D8 7D 87 D0 + 00 00 00 00 00 00 04 3A 00 00 00 04 + 44 00 00 01 01 03 28 00 01 00 01 00 + 00 19 00 0C 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 32 00 19 00 5A + 02 32 00 19 00 5A 02 40 00 + 29 01 00 00 00 00 15 C4 70 00 00 00 11 + 11 00 00 00 02 02 31 01 00 00 00 02 + 01 01 01 + 29 01 00 00 00 00 08 C5 08 00 00 00 00 + 70 00 + 29 01 00 00 00 00 40 C6 5B 2D 2D 07 54 + 07 54 01 02 01 02 07 07 00 00 07 07 + 0F 11 07 5B 00 5B 5B C2 C2 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 29 01 00 00 00 00 27 C7 01 1D 2E 41 4F + 5A 71 80 8B 95 45 4F 5C 71 7B 88 98 + A6 BE 01 1D 2E 41 4F 5A 71 80 8B 95 + 45 4F 5C 71 7B 88 98 A6 BE + 29 01 00 00 00 00 38 C8 00 00 00 00 00 + FC 00 00 00 00 00 FC 00 00 00 00 00 + FC 00 00 00 00 00 FC 00 00 00 00 00 + FC 00 00 00 00 00 FC 00 00 00 00 00 + FC 00 00 00 00 00 FC 00 00 00 00 00 + FC 00 + 29 01 00 00 00 00 14 C9 00 00 00 00 00 + FC 00 00 00 00 00 FC 00 00 00 00 00 + FC 00 + 29 01 00 00 00 00 2C CA 1C FC FC FC 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 + 29 01 00 00 00 00 1C CB FF FF FF FF 0F + 00 08 00 01 00 31 F0 40 08 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 29 01 00 00 00 00 02 CC 02 + 29 01 00 00 00 00 27 CD 10 80 37 C0 1A + 00 5C 02 19 90 11 88 D8 6C D8 6C 01 + 00 00 00 32 00 32 00 5D 02 32 32 01 + 33 00 33 00 5E 02 32 32 AF + 29 01 00 00 00 00 1A CE 5D 40 49 53 59 + 5E 63 68 6E 74 7E 8A 98 A8 BB D0 FF + 04 00 04 04 42 00 69 5A + 29 01 00 00 00 00 03 CF 4A 1D + 29 01 00 00 00 00 12 D0 33 57 D4 31 01 + 10 10 10 19 19 00 00 00 00 00 00 00 + 29 01 00 00 00 00 02 D1 00 + 29 01 00 00 00 00 20 D2 10 00 00 10 75 + 0F 03 25 20 00 00 00 00 00 00 00 00 + 04 00 00 00 00 00 00 00 00 00 00 00 + 00 00 + 29 01 00 00 00 00 17 D3 1B 3B BB 77 77 + 77 BB B3 33 00 00 6D 6E C7 C7 33 BB + F2 FD C6 0B 07 + 29 01 00 00 00 00 08 D4 00 00 00 00 00 + 00 00 + 29 01 00 00 00 00 08 D5 03 00 00 02 2B + 02 2B + 29 01 00 00 00 00 02 D6 01 + 29 01 00 00 00 00 22 D7 F6 FF 03 05 41 + 24 80 1F C7 1F 1B 00 0C 07 20 00 00 + 00 00 00 0C 00 1F 00 FC 00 00 AA 67 + 7E 5D 06 00 + 29 01 00 00 00 00 03 D9 20 14 + 29 01 00 00 00 00 05 DD 30 06 23 65 + 29 01 00 00 00 00 05 DE 00 3F FF 50 + 29 01 00 00 00 00 06 E7 00 00 00 46 61 + 29 01 00 00 00 00 02 EA 1F + 29 01 00 00 00 00 04 EE 41 51 00 + 29 01 00 00 00 00 03 F1 00 00 + 39 01 00 00 00 00 05 2A 00 00 04 37 + 39 01 00 00 00 00 05 2B 00 00 08 6F + 39 01 00 00 00 00 01 2C + 29 01 00 00 00 00 02 B0 00 + 39 01 00 00 00 00 02 51 FF + 39 01 00 00 00 00 02 53 0C + 39 01 00 00 00 00 02 55 00 + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 96 00 01 11 + 05 01 00 00 32 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 32 00 02 28 00 + 05 01 00 00 96 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-td4328-1080p-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-td4328-1080p-video.dtsi new file mode 100644 index 000000000000..12827c80a583 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-td4328-1080p-video.dtsi @@ -0,0 +1,172 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_td4328_truly_video: qcom,mdss_dsi_td4328_truly_video { + qcom,mdss-dsi-panel-name = + "td4328 video mode dsi truly panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2160>; + qcom,mdss-dsi-h-front-porch = <70>; + qcom,mdss-dsi-h-back-porch = <40>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <10>; + qcom,mdss-dsi-v-front-porch = <5>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 29 01 00 00 00 00 02 B0 00 + 29 01 00 00 00 00 04 B3 31 00 06 + 29 01 00 00 00 00 02 B4 00 + 29 01 00 00 00 00 06 B6 33 DB 80 12 00 + 29 01 00 00 00 00 08 B8 57 3D 19 1E 0A + 50 50 + 29 01 00 00 00 00 08 B9 6F 3D 28 3C 14 + C8 C8 + 29 01 00 00 00 00 08 BA B5 33 41 64 23 + A0 A0 + 29 01 00 00 00 00 03 BB 14 14 + 29 01 00 00 00 00 03 BC 37 32 + 29 01 00 00 00 00 03 BD 64 32 + 29 01 00 00 00 00 02 BE 04 + 29 01 00 00 00 00 02 C0 00 + 29 01 00 00 00 00 2E C1 04 48 00 00 26 + 15 19 0B 63 D2 D9 9A 73 EF BD E7 5C + 6B 93 4D 22 18 8B 2A 41 00 00 00 00 + 00 00 00 00 00 40 02 22 1B 06 03 00 + 07 FF 00 01 + 29 01 00 00 00 00 18 C2 01 F8 70 08 68 + 08 0C 10 00 08 30 00 00 00 00 00 00 + 20 02 43 00 00 00 + 29 01 00 00 00 00 3F C3 87 D8 7D 87 D0 + 00 00 00 00 00 00 04 3A 00 00 00 04 + 44 00 00 01 01 03 28 00 01 00 01 00 + 00 19 00 0C 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 32 00 19 00 5A + 02 32 00 19 00 5A 02 40 00 + 29 01 00 00 00 00 15 C4 70 00 00 00 11 + 11 00 00 00 02 02 31 01 00 00 00 02 + 01 01 01 + 29 01 00 00 00 00 08 C5 08 00 00 00 00 + 70 00 + 29 01 00 00 00 00 40 C6 5B 2D 2D 07 54 + 07 54 01 02 01 02 07 07 00 00 07 07 + 0F 11 07 5B 00 5B 5B C2 C2 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 29 01 00 00 00 00 27 C7 01 1D 2E 41 4F + 5A 71 80 8B 95 45 4F 5C 71 7B 88 98 + A6 BE 01 1D 2E 41 4F 5A 71 80 8B 95 + 45 4F 5C 71 7B 88 98 A6 BE + 29 01 00 00 00 00 38 C8 00 00 00 00 00 + FC 00 00 00 00 00 FC 00 00 00 00 00 + FC 00 00 00 00 00 FC 00 00 00 00 00 + FC 00 00 00 00 00 FC 00 00 00 00 00 + FC 00 00 00 00 00 FC 00 00 00 00 00 + FC 00 + 29 01 00 00 00 00 14 C9 00 00 00 00 00 + FC 00 00 00 00 00 FC 00 00 00 00 00 + FC 00 + 29 01 00 00 00 00 2C CA 1C FC FC FC 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 + 29 01 00 00 00 00 1C CB FF FF FF FF 0F + 00 08 00 01 00 31 F0 40 08 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 29 01 00 00 00 00 02 CC 02 + 29 01 00 00 00 00 27 CD 10 80 37 C0 1A + 00 5C 02 19 90 11 88 D8 6C D8 6C 01 + 00 00 00 32 00 32 00 5D 02 32 32 01 + 33 00 33 00 5E 02 32 32 AF + 29 01 00 00 00 00 1A CE 5D 40 49 53 59 + 5E 63 68 6E 74 7E 8A 98 A8 BB D0 FF + 04 00 04 04 42 00 69 5A + 29 01 00 00 00 00 03 CF 4A 1D + 29 01 00 00 00 00 12 D0 33 57 D4 31 01 + 10 10 10 19 19 00 00 00 00 00 00 00 + 29 01 00 00 00 00 02 D1 00 + 29 01 00 00 00 00 20 D2 10 00 00 10 75 + 0F 03 25 20 00 00 00 00 00 00 00 00 + 04 00 00 00 00 00 00 00 00 00 00 00 + 00 00 + 29 01 00 00 00 00 17 D3 1B 3B BB 77 77 + 77 BB B3 33 00 00 6D 6E DB DB 33 BB + F2 FD C6 0B 07 + 29 01 00 00 00 00 08 D4 00 00 00 00 00 + 00 00 + 29 01 00 00 00 00 08 D5 03 00 00 02 40 + 02 40 + 29 01 00 00 00 00 02 D6 01 + 29 01 00 00 00 00 22 D7 F6 FF 03 05 41 + 24 80 1F C7 1F 1B 00 0C 07 20 00 00 + 00 00 00 0C 00 1F 00 FC 00 00 AA 67 + 7E 5D 06 00 + 29 01 00 00 00 00 03 D9 20 14 + 29 01 00 00 00 00 05 DD 30 06 23 65 + 29 01 00 00 00 00 05 DE 00 3F FF 90 + 29 01 00 00 00 00 06 E7 00 00 00 46 61 + 29 01 00 00 00 00 02 EA 1F + 29 01 00 00 00 00 04 EE 41 51 00 + 29 01 00 00 00 00 03 F1 00 00 + 39 01 00 00 00 00 05 2A 00 00 04 37 + 39 01 00 00 00 00 05 2B 00 00 08 6F + 39 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 51 FF + 39 01 00 00 00 00 02 53 0C + 39 01 00 00 00 00 02 55 00 + 05 01 00 00 96 00 01 11 + 05 01 00 00 32 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 32 00 02 28 00 + 05 01 00 00 96 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-td4330-truly-singlemipi-fhd-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-td4330-truly-singlemipi-fhd-cmd.dtsi new file mode 100644 index 000000000000..782a5c0346d7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-td4330-truly-singlemipi-fhd-cmd.dtsi @@ -0,0 +1,316 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_td4330_truly_cmd: qcom,mdss_dsi_td4330_truly_cmd { + qcom,mdss-dsi-panel-name = + "td4330 cmd mode dsi truly panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2280>; + qcom,mdss-dsi-h-front-porch = <80>; + qcom,mdss-dsi-h-back-porch = <80>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <13>; + qcom,mdss-dsi-v-front-porch = <16>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 B0 04 + 15 01 00 00 00 00 02 B0 00 + 39 01 00 00 00 00 0D B6 30 6B + 00 06 03 0A 13 1A 6C 18 + 19 02 + 39 01 00 00 00 00 05 B7 00 00 00 + 00 + 39 01 00 00 00 00 08 B8 57 3D 19 + BE 1E 0A 0A + 39 01 00 00 00 00 08 B9 6F 3D 28 + BE 3C 14 0A + 39 01 00 00 00 00 08 BA B5 33 41 + BE 64 23 0A + 39 01 00 00 00 00 0C BB 44 26 C3 + 1F 19 06 03 C0 00 00 10 + 39 01 00 00 00 00 0C BC 32 4C C3 + 52 32 1F 03 F2 00 00 13 + 39 01 00 00 00 00 0C BD 24 68 C3 + AA 3F 32 03 FF 00 00 25 + 39 01 00 00 00 00 0D BE 00 00 00 + 00 00 00 00 00 00 00 00 + 00 + 39 01 00 00 00 00 0D C0 00 D9 01 + 2C 06 08 E8 00 06 00 00 + 08 + 39 01 00 00 00 00 24 C1 30 00 00 + 11 11 00 00 00 22 00 05 + 20 FA 00 08 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 79 C2 06 C0 6D + 01 03 00 02 02 01 20 12 + 01 03 08 F0 01 00 00 00 + 00 00 00 00 00 01 20 D9 + 04 04 01 01 01 00 28 F1 + 00 00 01 08 00 00 11 00 + 28 F1 04 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 11 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 11 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 11 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 + 39 01 00 00 00 00 6D C3 01 20 12 + 01 8F 00 01 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 AA AA AA 00 00 + 00 00 00 00 09 00 09 00 + 00 00 00 00 80 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 + 39 01 00 00 00 00 43 C4 00 00 00 + 00 4F 00 3E 3F 4F 00 00 + 44 06 02 10 10 0E 0E 61 + 61 5F 5F 5D 5D 00 00 00 + 00 4F 00 3E 3F 4F 00 00 + 44 06 02 11 11 0F 0F 61 + 61 5F 5F 5D 5D F0 FF FF + F0 FF FF E0 FF FF E0 FF + FF 10 00 00 10 00 00 + 39 01 00 00 00 00 06 C5 08 00 00 + 00 00 + 39 01 00 00 00 00 3A C6 02 0A 08 + FC FF FF FF 00 00 13 01 + FF 0F 22 01 3A 3A 3A 00 + 00 00 01 05 09 28 28 22 + 01 3A 3A 3A 00 00 00 01 + 21 00 00 00 1C 01 00 00 + 00 00 00 00 00 00 00 00 + 00 00 20 20 00 00 + 39 01 00 00 00 00 4D C7 00 00 01 + 11 02 15 02 AA 02 2E 02 + B3 03 1A 02 5F 02 78 02 + 97 02 E2 02 2E 02 6B 02 + CF 02 39 02 D0 03 41 03 + 96 03 A0 00 00 01 11 02 + 15 02 AA 02 2E 02 B3 03 + 1A 02 5F 02 78 02 97 02 + E2 02 2E 02 6B 02 CF 02 + 39 02 D0 03 41 03 96 03 + A0 + 39 01 00 00 00 00 42 C8 40 00 00 + 00 00 FF 00 00 00 00 00 + FF 00 00 00 00 00 FF 00 + 00 00 00 00 FF 00 00 00 + 00 00 FF 00 00 00 00 FF + 00 00 00 00 FF 00 00 00 + 00 FF 00 00 00 00 FF 00 + 00 00 00 FF 00 00 00 00 + FF 00 00 00 00 FF + 39 01 00 00 00 00 19 C9 00 00 00 + 00 FF 00 00 00 00 00 FF + 00 00 00 00 00 FF 00 00 + 00 00 00 FF 00 + 39 01 00 00 00 00 42 CA 1C FC FC + FC 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 + 39 01 00 00 00 00 0C CB A0 00 F0 + 00 20 81 00 00 00 00 FF + 39 01 00 00 00 00 0B CC 00 00 4D + 8B 55 4D 8B AA 4D 8B + 39 01 00 00 00 00 24 CE 5D 40 49 + 53 59 5E 63 68 6E 74 7E + 8A 98 A8 BB D0 E7 FF 04 + 00 04 04 42 00 69 5A 40 + 11 F4 00 00 04 FA 00 00 + 39 01 00 00 00 00 12 D0 F3 96 11 + B1 55 C9 00 F3 D4 11 F0 + 01 12 C8 02 20 11 + 39 01 00 00 00 00 23 D1 E3 E3 33 + 33 07 03 3B 33 77 37 77 + 37 35 77 07 77 F7 33 73 + 07 33 33 03 33 1B 03 32 + 3D 0A 30 13 13 30 00 + 39 01 00 00 00 00 05 D2 00 00 07 + 00 + 39 01 00 00 00 00 9A D3 00 00 00 + 00 00 00 00 00 00 FF F7 + FF FF F7 FF FF F7 FF FF + F7 FF FF F7 FF FF F7 FF + FF F7 FF FF F7 FF FF F7 + FF FF F7 FF FF F7 FF FF + F7 FF FF F7 FF FF F7 FF + FF F7 FF FF F7 FF FF F7 + FF FF F7 FF FF F7 FF FF + F7 FF FF F7 FF FF F7 FF + FF F7 FF FF F7 FF FF F7 + FF FF F7 FF FF F7 FF FF + F7 FF FF F7 FF FF F7 FF + FF F7 FF FF F7 FF FF F7 + FF FF F7 FF FF F7 FF FF + F7 FF FF F7 FF FF F7 FF + FF F7 FF FF F7 FF FF F7 + FF FF F7 FF FF F7 FF FF + F7 FF FF F7 FF FF F7 FF + FF F7 FF FF F7 FF + 15 01 00 00 00 00 02 E5 0F + 39 01 00 00 00 00 09 D5 02 31 02 + 31 02 31 02 31 + 15 01 00 00 00 00 02 D6 00 + 39 01 00 00 00 00 05 DD 30 06 23 + 65 + 39 01 00 00 00 00 0D DE 00 00 00 + 0F FF 00 00 00 00 00 00 + 10 + 39 01 00 00 00 00 99 DF 80 80 80 + FF FF FF FF FF FF FF 00 + 08 0F 08 08 D3 D3 D3 D3 + D3 60 60 60 60 60 F5 F5 + 75 75 75 20 20 34 20 20 + 80 01 41 00 32 00 00 96 + 20 40 00 00 FF FF FF 0E + 22 D0 04 0F 00 23 0D 18 + 14 C1 4D F1 10 FF 44 FF + 4F 05 00 11 11 11 FF 08 + 13 00 80 05 0E 02 14 08 + 0E 00 00 00 00 FC 72 7C + 72 7C 7C 61 40 50 40 90 + 90 20 A0 08 B1 00 00 00 + 22 22 22 17 63 06 4F 26 + 46 06 80 98 20 04 44 63 + F8 FC 03 75 44 6B 6B 6B + 26 40 C8 48 05 40 14 7F + 14 7F 15 01 4B 10 00 24 + 01 00 00 00 00 + 15 01 00 00 00 00 02 E3 FF + 39 01 00 00 00 00 05 E5 03 7F 00 + 00 + 39 01 00 00 00 00 07 E6 00 00 00 + 00 00 00 + 39 01 00 00 00 00 0B E7 50 00 00 + 00 00 00 00 00 00 00 + 39 01 00 00 00 00 1E EA 01 02 47 + 40 47 40 00 00 05 00 14 + C8 00 00 00 00 00 00 00 + 00 04 C2 00 11 00 30 0D + 90 86 + 39 01 00 00 00 00 08 EB 00 00 00 + 00 01 00 11 + 39 01 00 00 00 00 04 EC 00 00 00 + 39 01 00 00 00 00 21 ED 01 01 02 + 02 02 02 00 00 00 00 00 + 00 0A 00 00 00 00 10 00 + 18 00 00 00 B0 00 00 00 + 00 00 D0 10 00 + 39 01 00 00 00 00 61 EE 03 3F F0 + 03 00 F0 03 00 00 00 00 + 02 3F FC 00 00 00 00 00 + 00 00 00 00 00 3F 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 3F 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 48 8F 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 + 39 01 00 00 00 00 8C EF 02 30 5D + 09 70 00 00 00 00 2A 2A + 2A 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 02 30 5D 09 70 00 00 00 + 00 2A 2A 2A 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 10 03 10 02 00 10 00 10 + 00 0A 0A 00 00 00 00 00 + 0F 00 03 40 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 03 00 02 + 15 01 00 00 00 00 02 35 00 + 15 01 00 00 00 00 02 B0 04 + 29 01 00 00 00 00 02 D6 00 + 15 01 00 00 00 00 02 B0 03 + 39 01 00 00 00 00 03 51 FF F0 + 15 01 00 00 00 00 02 53 0C + 15 01 00 00 00 00 02 55 00 + 39 01 00 00 00 00 05 2A 00 00 04 37 + 39 01 00 00 00 00 05 2B 00 00 08 E7 + 39 01 00 00 00 00 05 30 00 00 02 A7 + 15 01 00 00 00 00 02 B0 03 + 05 01 00 00 64 00 02 29 00 + 05 01 00 00 C8 00 02 11 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 32 00 02 28 00 + 05 01 00 00 96 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-td4330-truly-singlemipi-fhd-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-td4330-truly-singlemipi-fhd-video.dtsi new file mode 100644 index 000000000000..e25f149bd8b9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-td4330-truly-singlemipi-fhd-video.dtsi @@ -0,0 +1,315 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_td4330_truly_video: qcom,mdss_dsi_td4330_truly_video { + qcom,mdss-dsi-panel-name = + "td4330 video mode dsi truly panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <65>; + qcom,mdss-pan-physical-height-dimension = <129>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2280>; + qcom,mdss-dsi-h-front-porch = <75>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <1>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <90>; + qcom,mdss-dsi-v-front-porch = <5>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 B0 04 + 15 01 00 00 00 00 02 B0 00 + 29 01 00 00 00 00 0D B6 30 + 6B 00 06 03 0A 13 + 1A 6C 18 19 02 + 29 01 00 00 00 00 05 B7 11 00 00 + 00 + 29 01 00 00 00 00 08 B8 57 3D 19 + BE 1E 0A 0A + 29 01 00 00 00 00 08 B9 6F 3D 28 + BE 3C 14 0A + 29 01 00 00 00 00 08 BA B5 33 41 + BE 64 23 0A + 29 01 00 00 00 00 0C BB 44 26 C3 + 1F 19 06 03 C0 00 00 10 + 29 01 00 00 00 00 0C BC 32 4C C3 + 52 32 1F 03 F2 00 00 13 + 29 01 00 00 00 00 0C BD 24 68 C3 + AA 3F 32 03 FF 00 00 25 + 29 01 00 00 00 00 0D BE 00 00 00 + 00 00 00 00 00 00 00 00 + 00 + 29 01 00 00 00 00 0D C0 00 D9 01 + 2C 06 08 E8 00 06 00 00 + 08 + 29 01 00 00 00 00 24 C1 30 00 00 + 11 11 00 00 00 22 00 05 + 20 FA 00 08 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 29 01 00 00 00 00 79 C2 06 C0 6D + 01 03 00 02 02 01 20 12 + 01 03 08 F0 01 00 00 00 + 00 00 00 00 00 01 20 D9 + 04 04 01 01 01 00 28 F1 + 00 00 01 08 00 00 11 00 + 28 F1 04 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 11 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 11 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 11 00 + 00 00 00 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00 04 FA 00 00 + 29 01 00 00 00 00 12 D0 F3 96 11 + B1 55 C9 00 F3 D4 11 F0 + 01 12 C8 02 20 11 + 29 01 00 00 00 00 23 D1 E3 E3 33 + 33 07 03 3B 33 77 37 77 + 37 35 77 07 77 F7 33 73 + 07 33 33 03 33 1B 03 32 + 3D 0A 30 13 13 30 00 + 29 01 00 00 00 00 05 D2 00 00 07 + 00 + 29 01 00 00 00 00 9A D3 00 00 00 + 00 00 00 00 00 00 FF F7 + FF FF F7 FF FF F7 FF FF + F7 FF FF F7 FF FF F7 FF + FF F7 FF FF F7 FF FF F7 + FF FF F7 FF FF F7 FF FF + F7 FF FF F7 FF FF F7 FF + FF F7 FF FF F7 FF FF F7 + FF FF F7 FF FF F7 FF FF + F7 FF FF F7 FF FF F7 FF + FF F7 FF FF F7 FF FF F7 + FF FF F7 FF FF F7 FF FF + F7 FF FF F7 FF FF F7 FF + FF F7 FF FF F7 FF FF F7 + FF FF F7 FF FF F7 FF FF + F7 FF FF F7 FF FF F7 FF + FF F7 FF FF F7 FF FF F7 + FF FF F7 FF FF F7 FF FF + F7 FF FF F7 FF FF F7 FF + FF F7 FF FF F7 FF + 15 01 00 00 00 00 02 E5 0F + 29 01 00 00 00 00 09 D5 02 31 02 + 31 02 31 02 31 + 15 01 00 00 00 00 02 D6 00 + 29 01 00 00 00 00 05 DD 30 06 23 + 65 + 29 01 00 00 00 00 0D DE 00 00 00 + 0F FF 00 00 00 00 00 00 + 10 + 29 01 00 00 00 00 99 DF 80 80 80 + FF FF FF FF FF FF FF 00 + 08 0F 08 08 D3 D3 D3 D3 + D3 60 60 60 60 60 F5 F5 + 75 75 75 20 20 34 20 20 + 80 01 41 00 32 00 00 96 + 20 40 00 00 FF FF FF 0E + 22 D0 04 0F 00 23 0D 18 + 14 C1 4D F1 10 FF 44 FF + 4F 05 00 11 11 11 FF 08 + 13 00 80 05 0E 02 14 08 + 0E 00 00 00 00 FC 72 7C + 72 7C 7C 61 40 50 40 90 + 90 20 A0 08 B1 00 00 00 + 22 22 22 17 63 06 4F 26 + 46 06 80 98 20 04 44 63 + F8 FC 03 75 44 6B 6B 6B + 26 40 C8 48 05 40 14 7F + 14 7F 15 01 4B 10 00 24 + 01 00 00 00 00 + 15 01 00 00 00 00 02 E3 FF + 29 01 00 00 00 00 05 E5 03 7F 00 + 00 + 29 01 00 00 00 00 07 E6 00 00 00 + 00 00 00 + 29 01 00 00 00 00 0B E7 50 00 00 + 00 00 00 00 00 00 00 + 29 01 00 00 00 00 1E EA 01 02 47 + 40 47 40 00 00 05 00 12 + 86 00 00 00 00 00 00 00 + 00 04 C2 00 11 00 30 0D + 90 86 + 29 01 00 00 00 00 08 EB 00 00 00 + 00 01 00 11 + 29 01 00 00 00 00 04 EC 01 E0 00 + 29 01 00 00 00 00 21 ED 01 01 02 + 02 02 02 00 00 00 00 00 + 00 0A 00 00 00 00 10 00 + 18 00 00 00 B0 00 00 00 + 00 00 D0 10 00 + 29 01 00 00 00 00 61 EE 03 3F F0 + 03 00 F0 03 00 00 00 00 + 02 3F FC 00 00 00 00 00 + 00 00 00 00 00 3F 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 3F 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 48 8F 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 + 29 01 00 00 00 00 8C EF 02 30 5D + 09 70 00 00 00 00 2A 2A + 2A 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 02 30 5D 09 70 00 00 00 + 00 2A 2A 2A 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 10 03 10 02 00 10 00 10 + 00 0A 0A 00 00 00 00 00 + 0F 00 03 40 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 03 00 02 + 15 01 00 00 00 00 02 35 00 + 15 01 00 00 00 00 02 B0 04 + 15 01 00 00 00 00 02 D6 00 + 29 01 00 00 00 00 02 B0 03 + 39 01 00 00 00 00 03 51 FF F0 + 15 01 00 00 00 00 02 53 0C + 15 01 00 00 00 00 02 55 00 + 39 01 00 00 00 00 05 2A 00 00 04 37 + 39 01 00 00 00 00 05 2B 00 00 08 E7 + 39 01 00 00 00 00 05 30 00 00 02 A7 + 15 01 00 00 00 00 02 B0 04 + 05 01 00 00 64 00 02 29 00 + 05 01 00 00 C8 00 02 11 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 32 00 02 28 00 + 05 01 00 00 96 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/fg-gen4-batterydata-alium-3600mah.dtsi b/arch/arm/boot/dts/qcom/fg-gen4-batterydata-alium-3600mah.dtsi new file mode 100644 index 000000000000..e8a8417c5c8b --- /dev/null +++ b/arch/arm/boot/dts/qcom/fg-gen4-batterydata-alium-3600mah.dtsi @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,alium_860_89032_0000_3600mah_averaged_masterslave_sep24th2018 { + /* #Alium_860_89032_0000_3600mAh_averaged_MasterSlave_Sept24th2018*/ + qcom,max-voltage-uv = <4350000>; + qcom,fastchg-current-ma = <5400>; + qcom,jeita-fcc-ranges = <0 100 2500000 + 110 400 3600000 + 410 450 2500000>; + qcom,jeita-fv-ranges = <0 100 4250000 + 110 400 4350000 + 410 450 4250000>; + qcom,step-chg-ranges = <3600000 3800000 5400000 + 3801000 4300000 3600000 + 4301000 4350000 2500000>; + /* COLD = 0 DegC, HOT = 45 DegC */ + qcom,jeita-hard-thresholds = <0x58cd 0x20b8>; + /* COOL = 10 DegC, WARM = 40 DegC */ + qcom,jeita-soft-thresholds = <0x4ccc 0x25e3>; + /* COLD hys = 13 DegC, WARM hys = 37 DegC */ + qcom,jeita-soft-hys-thresholds = <0x48d4 0x2943>; + qcom,jeita-soft-fcc-ua = <2500000 2500000>; + qcom,jeita-soft-fv-uv = <4250000 4250000>; + qcom,ocv-based-step-chg; + qcom,batt-id-kohm = <107>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,fg-cc-cv-threshold-mv = <4340>; + qcom,battery-type = "alium_860_89032_0000_3600mah_sept24th2018"; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0xdf 0x02 0x77 0x1a>; + qcom,rslow-low-coeffs = <0x51 0x04 0xd0 0x13>; + qcom,checksum = <0x1538>; + qcom,gui-version = "PM855GUI - 1.0.0.10"; + qcom,fg-profile-data = [ + 09 00 C7 EA + C4 DC 8E E2 + 3A DD 00 00 + 15 BC A5 8A + 02 80 D1 92 + AB 9D 47 80 + 10 00 DF 02 + 77 1A 85 EC + E1 FD CE 07 + 32 00 75 EB + AA ED F3 CD + 0C 0A 7A E4 + ED C5 40 1B + D0 02 1F CA + FF 00 52 00 + 4D 00 4A 00 + 3C 00 35 00 + 38 00 39 00 + 48 00 43 00 + 3F 00 FF 00 + 38 00 40 00 + 46 00 50 00 + 45 00 5C 00 + 7E 64 60 00 + 50 08 50 10 + FF 00 6A 00 + 5F 00 63 00 + 6E 00 60 00 + 7D 20 96 40 + 75 50 6B 13 + 63 00 D8 00 + 14 22 7E 0D + 21 02 AA 04 + ED 1C D4 09 + 64 0C D3 23 + A4 18 D3 42 + B5 55 91 02 + 90 12 2A 1F + 02 06 1F 0A + A3 06 AE 1C + 8D 02 96 04 + D2 03 D1 17 + 51 23 3F 45 + 28 53 69 14 + 93 20 8E EC + 18 CB C8 C5 + DB 1C 7B C9 + 7C 05 E6 C2 + B9 17 2C 93 + 87 85 A2 92 + 91 A8 09 80 + 92 F2 1A 0D + F4 FC 5E EB + 00 F8 FB ED + 15 E2 F6 0F + 75 02 72 05 + 49 01 10 00 + FA E5 E2 03 + 8D 05 85 02 + CE 07 32 00 + 23 03 46 02 + 9C 04 03 02 + 48 07 0A 00 + BA 03 97 02 + 65 05 50 00 + 3A 00 41 00 + 43 64 45 00 + 45 10 45 18 + 46 08 44 00 + 47 00 3A 08 + 4B 08 37 00 + 47 20 4E 40 + 54 58 60 10 + 57 00 5F 00 + 57 08 55 00 + 4B 00 50 00 + 3E 08 52 08 + 52 00 5C 20 + 6F 40 7D 58 + 67 10 63 00 + 69 08 4F 10 + D8 00 8C 2A + DB 04 28 02 + AD 04 0B 1D + 50 22 A7 45 + 0D 52 A2 18 + 74 03 AD 04 + 35 02 AE 13 + 3F 0A 5A 20 + DD 04 F1 02 + D8 05 C7 1C + DD 02 3D 04 + EB 03 97 18 + 52 03 D5 04 + 19 02 72 00 + 14 22 7E 05 + 21 02 AA 04 + ED 1C D4 01 + 64 04 D3 03 + A4 18 D3 02 + B5 05 91 02 + 90 00 7C 01 + C0 00 FA 00 + 04 0E 00 00 + ]; +}; diff --git a/arch/arm/boot/dts/qcom/fg-gen4-batterydata-mlp466076-3250mah.dtsi b/arch/arm/boot/dts/qcom/fg-gen4-batterydata-mlp466076-3250mah.dtsi new file mode 100644 index 000000000000..2664336da9c8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/fg-gen4-batterydata-mlp466076-3250mah.dtsi @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,mlp466076_3250mah_averaged_masterslave_sept24th2018 { + /* #mlp466076_3250mAh_averaged_MasterSlave_sept24th2018 */ + qcom,max-voltage-uv = <4400000>; + qcom,fastchg-current-ma = <6000>; + /* COLD = 0 DegC, HOT = 55 DegC */ + qcom,jeita-hard-thresholds = <0x5840 0x1810>; + /* COOL = 15 DegC, WARM = 45 DegC */ + qcom,jeita-soft-thresholds = <0x45f3 0x20c4>; + /* COOL hys = 18 DegC, WARM hys = 42 DegC */ + qcom,jeita-soft-hys-thresholds = <0x4206 0x23c0>; + qcom,jeita-fcc-ranges = <0 150 650000 + 151 450 4875000 + 451 550 1625000>; + qcom,jeita-fv-ranges = <0 150 4150000 + 151 450 4400000 + 451 550 4150000>; + qcom,jeita-soft-fcc-ua = <650000 1625000>; + qcom,jeita-soft-fv-uv = <4150000 4150000>; + qcom,batt-id-kohm = <133>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,fg-cc-cv-threshold-mv = <4390>; + qcom,battery-type = "qrd855_mlp466076_3200mah_sept24th2018"; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,rslow-normal-coeffs = <0x43 0xfc 0xc9 0x12>; + qcom,rslow-low-coeffs = <0x07 0x15 0x8d 0xf5>; + qcom,checksum = <0x7F72>; + qcom,gui-version = "PM8150GUI - 1.0.0.10"; + qcom,fg-profile-data = [ + 09 00 53 00 + 77 DD 12 E2 + E4 DD 00 00 + 49 BC 7B 8B + F9 87 5A 9A + A8 86 C3 87 + 29 00 43 FC + C9 12 DC 04 + 75 FB CE 07 + 32 00 43 EB + 7A ED B9 B5 + EF 0A C4 E2 + 2B BC EF 0B + 40 02 5C DB + 60 00 46 00 + 49 00 48 00 + 3B 00 30 00 + 30 00 37 00 + 41 00 43 00 + 45 00 60 00 + 40 00 3A 00 + 36 00 36 00 + 33 00 5B 00 + 4F 64 4A 00 + 4F 08 4F 08 + 60 F8 4D 00 + 4A 00 5A 08 + 59 08 4E 00 + 93 20 6A 40 + 59 58 52 10 + 59 00 D8 08 + 6A 21 E7 0D + 42 03 1F FC + 5B 1C 1C 03 + 3A 04 8B 23 + FB 17 7A 3B + B1 4C 31 02 + 85 15 3A 21 + DB 0D E5 0B + F7 04 E0 1C + 4D FB F6 04 + 8B 03 7E 18 + 9C 22 29 3C + E3 4B 8C 16 + F6 20 FE ED + C5 D3 01 D5 + D5 1C 03 CB + AF 05 DD BA + 60 18 87 92 + 73 84 70 9B + 8F 98 09 80 + 67 FA 62 05 + 58 03 C9 04 + 00 00 1A E4 + C1 02 E9 0F + E0 EB 80 A2 + 6C 1F 1C 10 + 93 04 29 02 + 8D 04 6F 02 + CE 07 32 00 + C3 01 CA 02 + 6F 07 4A 03 + 03 05 EC 04 + 3E 04 71 04 + CD 02 4A 00 + 3D 00 40 00 + 42 64 44 00 + 43 00 47 08 + 44 00 4B 00 + 50 00 4F 10 + 46 10 3C 00 + 45 20 48 40 + 48 58 4D 0E + 48 00 40 00 + 46 08 5E 00 + 61 00 48 00 + 43 08 59 08 + 5B 00 5F 20 + 74 40 5F 50 + 53 10 5B 00 + 70 00 E6 08 + D8 00 DD 20 + 9A 04 2B 0B + 97 0D C7 1C + 55 23 E3 45 + 1B 52 89 18 + B9 03 18 04 + DB 02 74 12 + 3F 0A D4 20 + 4A 04 8A 03 + 32 05 C8 1C + DF 02 66 04 + C4 03 A7 18 + 2F 03 10 05 + C6 03 76 00 + D0 20 31 04 + AA 03 0E 05 + D3 1C 33 02 + A2 05 91 02 + AB 18 D6 02 + A7 05 B2 02 + 7F 00 7F 01 + C0 00 FA 00 + F2 0C 00 00 + ]; +}; diff --git a/arch/arm/boot/dts/qcom/guacamole-overlay-dvt.dts b/arch/arm/boot/dts/qcom/guacamole-overlay-dvt.dts new file mode 100644 index 000000000000..e273cc611f3f --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamole-overlay-dvt.dts @@ -0,0 +1,43 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +#include "guacamole_evt3.dtsi" +#include "guacamole_dvt.dtsi" + +/ { + model = "MTP 18821 18831 15"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0 >; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <15>; +}; + diff --git a/arch/arm/boot/dts/qcom/guacamole-overlay-evt1.dts b/arch/arm/boot/dts/qcom/guacamole-overlay-evt1.dts new file mode 100644 index 000000000000..68749dd8d795 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamole-overlay-evt1.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +/ { + model = "MTP 18821 18831 12"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <12>; +}; + diff --git a/arch/arm/boot/dts/qcom/guacamole-overlay-evt2-second.dts b/arch/arm/boot/dts/qcom/guacamole-overlay-evt2-second.dts new file mode 100644 index 000000000000..64fc4a52eb25 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamole-overlay-evt2-second.dts @@ -0,0 +1,40 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +/ { + model = "MTP 18821 18831 second 55"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <55>; +}; + diff --git a/arch/arm/boot/dts/qcom/guacamole-overlay-evt2.dts b/arch/arm/boot/dts/qcom/guacamole-overlay-evt2.dts new file mode 100644 index 000000000000..d75754eb4b0f --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamole-overlay-evt2.dts @@ -0,0 +1,40 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +/ { + model = "MTP 18821 18831 13 54 evt2"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <13 54>; +}; + diff --git a/arch/arm/boot/dts/qcom/guacamole-overlay-evt3.dts b/arch/arm/boot/dts/qcom/guacamole-overlay-evt3.dts new file mode 100644 index 000000000000..070ed1c5453c --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamole-overlay-evt3.dts @@ -0,0 +1,41 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +#include "guacamole_evt3.dtsi" +/ { + model = "MTP 18821 18831 14 52 53"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <14 52 53>; +}; + diff --git a/arch/arm/boot/dts/qcom/guacamole-overlay-pvt.dts b/arch/arm/boot/dts/qcom/guacamole-overlay-pvt.dts new file mode 100644 index 000000000000..1a3299e5dfed --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamole-overlay-pvt.dts @@ -0,0 +1,44 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +#include "guacamole_evt3.dtsi" +#include "guacamole_dvt.dtsi" +#include "guacamole_pvt.dtsi" + +/ { + model = "MTP 18821 18831 21 22"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0 >; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <21 22>; +}; + diff --git a/arch/arm/boot/dts/qcom/guacamole-overlay-t0.dts b/arch/arm/boot/dts/qcom/guacamole-overlay-t0.dts new file mode 100644 index 000000000000..ef389e47a275 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamole-overlay-t0.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" + +/ { + model = "MTP 18821 18831 T0 11"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <11>; +}; + diff --git a/arch/arm/boot/dts/qcom/guacamole-sdx50m-overlay-dvt.dts b/arch/arm/boot/dts/qcom/guacamole-sdx50m-overlay-dvt.dts new file mode 100644 index 000000000000..1f8a448555d7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamole-sdx50m-overlay-dvt.dts @@ -0,0 +1,46 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sdx50m.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +#include "guacamole_dvt.dtsi" + + +/ { + model = "SDX50M MTP 18827 15"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18827>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <15>; + +}; diff --git a/arch/arm/boot/dts/qcom/guacamole-sdx50m-overlay-evt1.dts b/arch/arm/boot/dts/qcom/guacamole-sdx50m-overlay-evt1.dts new file mode 100644 index 000000000000..5826102194b8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamole-sdx50m-overlay-evt1.dts @@ -0,0 +1,44 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sdx50m.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" + + +/ { + model = "SDX50M MTP 18827 12 13"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18827>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <12 13>; + +}; diff --git a/arch/arm/boot/dts/qcom/guacamole-sdx50m-overlay-evt2.dts b/arch/arm/boot/dts/qcom/guacamole-sdx50m-overlay-evt2.dts new file mode 100644 index 000000000000..df0d83680882 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamole-sdx50m-overlay-evt2.dts @@ -0,0 +1,45 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sdx50m.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" + + +/ { + model = "SDX50M MTP 18827 14"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18827>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <14>; + +}; diff --git a/arch/arm/boot/dts/qcom/guacamole-sdx50m-overlay-pvt.dts b/arch/arm/boot/dts/qcom/guacamole-sdx50m-overlay-pvt.dts new file mode 100644 index 000000000000..440fa057b30e --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamole-sdx50m-overlay-pvt.dts @@ -0,0 +1,47 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sdx50m.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +#include "guacamole_dvt.dtsi" +#include "guacamole_pvt.dtsi" + + +/ { + model = "SDX50M MTP 18827 21 22"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18827>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <21 22>; + +}; diff --git a/arch/arm/boot/dts/qcom/guacamole-sdx50m-overlay-t0.dts b/arch/arm/boot/dts/qcom/guacamole-sdx50m-overlay-t0.dts new file mode 100644 index 000000000000..31c592f7d9a4 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamole-sdx50m-overlay-t0.dts @@ -0,0 +1,43 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sdx50m.dtsi" +#include "guacamole_t0.dtsi" + + +/ { + model = "SDX50M MTP 18827 11"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18827>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <11>; + +}; diff --git a/arch/arm/boot/dts/qcom/guacamole.dtsi b/arch/arm/boot/dts/qcom/guacamole.dtsi new file mode 100644 index 000000000000..18151a2d7ffb --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamole.dtsi @@ -0,0 +1,166 @@ +/*this is for different project dtsi*/ +/* OnePlus add thermistor, by rio.zhao*/ + +&thermal_zones { + skin-therm { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + trips { + freq_config1: freq_config1 { + temperature = <52000>; + hysteresis = <2000>; + type = "passive"; + }; + freq_config2: freq_config2 { + temperature = <54000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + cooling-maps { + freq_dev0 { + trip = <&freq_config1>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>;/*345*/ + }; + freq_dev1 { + trip = <&freq_config1>; + cooling-device = + <&CPU0 9 9>;/*1036*/ + }; + freq_dev2 { + trip = <&freq_config1>; + cooling-device = + <&CPU4 13 13>;/*1056*/ + }; + freq_dev3 { + trip = <&freq_config1>; + cooling-device = + <&CPU7 16 16>;/*1171*/ + }; + freq_dev4 { + trip = <&freq_config2>; + cooling-device = + <&CPU0 11 11>;/*844*/ + }; + freq_dev5 { + trip = <&freq_config2>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev6 { + trip = <&freq_config2>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev7 { + trip = <&freq_config2>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev8 { + trip = <&freq_config2>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pa-therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-msm-therm { + trips { + freq_config3: freq_config3 { + temperature = <62000>; + hysteresis = <2000>; + type = "passive"; + }; + freq_config4: freq_config4 { + temperature = <64000>; + hysteresis = <2000>; + type = "passive"; + }; + freq_config5: freq_config5 { + temperature = <66000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + cooling-maps { + freq_dev0 { + trip = <&freq_config3>; + cooling-device = + <&CPU0 2 2>;/*1632 18*/ + }; + freq_dev1 { + trip = <&freq_config3>; + cooling-device = + <&CPU4 8 8>;/*1612 17*/ + }; + freq_dev2 { + trip = <&freq_config3>; + cooling-device = + <&CPU7 9 9>;/*1920 20*/ + }; + freq_dev3 { + trip = <&freq_config4>; + cooling-device = + <&CPU0 4 4>;/*1478*/ + }; + freq_dev4 { + trip = <&freq_config4>; + cooling-device = + <&CPU4 11 11>;/*1286*/ + }; + freq_dev5 { + trip = <&freq_config4>; + cooling-device = + <&CPU7 13 13>;/*1497*/ + }; + freq_dev6 { + trip = <&freq_config4>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-3)>;/*499*/ + }; + freq_dev7 { + trip = <&freq_config5>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-2)>;/*427*/ + }; + }; + }; +}; +&pm8150b_charger { + /* for verify test adjust 530->500 */ + hot-bat-decidegc = <500>; + op,dis_ctrl_current; +}; + +&mtp_batterydata { + #include "OP-fg-batterydata-4000mah.dtsi" +}; + +&wdog{ + qcom,bark-time = <15000>; +}; diff --git a/arch/arm/boot/dts/qcom/guacamole_dvt.dtsi b/arch/arm/boot/dts/qcom/guacamole_dvt.dtsi new file mode 100644 index 000000000000..18b79ae52aba --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamole_dvt.dtsi @@ -0,0 +1 @@ +/*this is for one project different hw version */ \ No newline at end of file diff --git a/arch/arm/boot/dts/qcom/guacamole_evt1.dtsi b/arch/arm/boot/dts/qcom/guacamole_evt1.dtsi new file mode 100644 index 000000000000..8f699bb7f922 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamole_evt1.dtsi @@ -0,0 +1,2 @@ +/*this is for one project different hw version */ + diff --git a/arch/arm/boot/dts/qcom/guacamole_evt2.dtsi b/arch/arm/boot/dts/qcom/guacamole_evt2.dtsi new file mode 100644 index 000000000000..8f699bb7f922 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamole_evt2.dtsi @@ -0,0 +1,2 @@ +/*this is for one project different hw version */ + diff --git a/arch/arm/boot/dts/qcom/guacamole_evt3.dtsi b/arch/arm/boot/dts/qcom/guacamole_evt3.dtsi new file mode 100644 index 000000000000..8f699bb7f922 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamole_evt3.dtsi @@ -0,0 +1,2 @@ +/*this is for one project different hw version */ + diff --git a/arch/arm/boot/dts/qcom/guacamole_pvt.dtsi b/arch/arm/boot/dts/qcom/guacamole_pvt.dtsi new file mode 100644 index 000000000000..18b79ae52aba --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamole_pvt.dtsi @@ -0,0 +1 @@ +/*this is for one project different hw version */ \ No newline at end of file diff --git a/arch/arm/boot/dts/qcom/guacamole_sdx50m.dtsi b/arch/arm/boot/dts/qcom/guacamole_sdx50m.dtsi new file mode 100644 index 000000000000..78884d9ed161 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamole_sdx50m.dtsi @@ -0,0 +1,17 @@ +/*this is for sdx50m project */ +&ois_rear_0 { +ois_gyro,id = <2>;//18827 +}; +&ois_rear_1 { +ois_gyro,id = <2>;//18827 +}; + +&soc { + qcom,msm-imem@146bf000 { + download_mode@0{ + compatible = "qcom,msm-imem-download_mode"; + reg = <0x658 4>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/qcom/guacamole_sm8150.dtsi b/arch/arm/boot/dts/qcom/guacamole_sm8150.dtsi new file mode 100644 index 000000000000..a9e5ae4e8b22 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamole_sm8150.dtsi @@ -0,0 +1,8 @@ +/*this is for sm8150 version */ + +&ois_rear_0 { + ois_gyro,id = <1>;//18821 +}; +&ois_rear_1 { + ois_gyro,id = <1>;//18821 +}; diff --git a/arch/arm/boot/dts/qcom/guacamole_t0.dtsi b/arch/arm/boot/dts/qcom/guacamole_t0.dtsi new file mode 100644 index 000000000000..cba91f689146 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamole_t0.dtsi @@ -0,0 +1,99 @@ +/*this is for one project different hw version */ + +/*tp 1.8v power change to gpio119 for T0 hw*/ +&qupv3_se17_i2c { + sec-s6sy761@48 { + //enable1v8_gpio = <&tlmm 119 0x00>; + pinctrl-0 = <&tp_irq_active &tp_rst_active &tp_1v8_t0_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_t0_suspend>; + }; +}; + +&qupv3_se17_i2c { + st_fts@49 { + //enable1v8_gpio = <&tlmm 119 0x00>; + pinctrl-0 = <&tp_irq_active &tp_rst_active &tp_1v8_t0_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_t0_suspend>; + }; +}; + +&tlmm { + + + tp_1v8_t0_active: tp_1v8_t0_active { + mux { + pins = "gpio119"; + function = "gpio"; + }; + config { + pins = "gpio119"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + tp_1v8_t0_suspend: tp_1v8_t0_suspend { + mux { + pins = "gpio119"; + function = "gpio"; + }; + config { + pins = "gpio119"; + drive-strength = <8>; + bias-pull-down; + }; + }; +}; + +/* for Battery & Charging STRAT */ +&qupv3_se8_i2c { + oneplus_fastchg@26{ + microchip,mcu-en-gpio = <&tlmm 10 0x00>; + microchip,usb-sw-2-gpio = <&tlmm 59 0x00>; + op,mcl_verion; + }; + +}; + +&pm8150b_charger { + /* for external ship mode suppot */ + op,stm-ctrl-gpio = <&tlmm 21 0x00>; + op,vbus-ctrl-gpio = <&pm8150_gpios 9 GPIO_ACTIVE_LOW>; +}; + +/* for Battery & Charging END */ + +/* @bsp, usb config START*/ +&usb2_phy0 { + qcom,param-override-seq = + <0x67 0x6c/*Disconnection voltage +21.56%*/ + 0x06 0x70/*Pre-emphasis:4x DC voltage level:+6.50%*/ + 0x28 0x74>; +}; + +&extcon_usb1 { + status = "disabled"; +}; + +&usb1 { + status = "disabled"; +}; + +/* @bsp, As QRD-DVT have this config, keep the same config + * for ldo18 power suspend + */ +&usb_qmp_dp_phy { + vdd-supply = <&pm8150_l18>; + qcom,vdd-voltage-level = <0 912000 912000>; +}; + +&sde_dp { + vdda-0p9-supply = <&pm8150_l18>; + qcom,phy-supply-entries { + qcom,phy-supply-entry@0 { + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <912000>; + }; + }; +}; +/* @bsp, usb config END*/ diff --git a/arch/arm/boot/dts/qcom/guacamoleb-overlay-dvt.dts b/arch/arm/boot/dts/qcom/guacamoleb-overlay-dvt.dts new file mode 100644 index 000000000000..8db1e3b3e020 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamoleb-overlay-dvt.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-guacamoleb.dtsi" +#include "guacamoleb_sm8150.dtsi" +#include "guacamoleb.dtsi" +#include "guacamoleb_dvt.dtsi" + +/ { + model = "MTP 18857 13"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0 >; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18857 >; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <13>; +}; + diff --git a/arch/arm/boot/dts/qcom/guacamoleb-overlay-evt.dts b/arch/arm/boot/dts/qcom/guacamoleb-overlay-evt.dts new file mode 100644 index 000000000000..cbc81cc94b9b --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamoleb-overlay-evt.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-guacamoleb.dtsi" +#include "guacamoleb_sm8150.dtsi" +#include "guacamoleb.dtsi" +#include "guacamoleb_evt.dtsi" + +/ { + model = "MTP 18857 12 "; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18857>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <12>; +}; + diff --git a/arch/arm/boot/dts/qcom/guacamoleb-overlay-pvt.dts b/arch/arm/boot/dts/qcom/guacamoleb-overlay-pvt.dts new file mode 100644 index 000000000000..0914cf131d2f --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamoleb-overlay-pvt.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-guacamoleb.dtsi" +#include "guacamoleb_sm8150.dtsi" +#include "guacamoleb.dtsi" +#include "guacamoleb_pvt.dtsi" + +/ { + model = "MTP 18857 14 15"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0 >; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18857>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <14 15>; +}; + diff --git a/arch/arm/boot/dts/qcom/guacamoleb-overlay-t0.dts b/arch/arm/boot/dts/qcom/guacamoleb-overlay-t0.dts new file mode 100644 index 000000000000..694df9a2a39b --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamoleb-overlay-t0.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-guacamoleb.dtsi" +#include "guacamoleb_sm8150.dtsi" +#include "guacamoleb.dtsi" +#include "guacamoleb_t0.dtsi" + +/ { + model = "MTP 18857 T0 11"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18857>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <11>; +}; + diff --git a/arch/arm/boot/dts/qcom/guacamoleb.dtsi b/arch/arm/boot/dts/qcom/guacamoleb.dtsi new file mode 100644 index 000000000000..2685b9ccd4a4 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamoleb.dtsi @@ -0,0 +1,490 @@ +/*this is for different project dtsi*/ +/* OnePlus add thermistor, by rio.zhao*/ +&pm8150_adc_tm { + skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + skin-therm { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + trips { + freq_config1: freq_config1 { + temperature = <52000>; + hysteresis = <2000>; + type = "passive"; + }; + freq_config2: freq_config2 { + temperature = <54000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + cooling-maps { + freq_dev0 { + trip = <&freq_config1>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>;/*345*/ + }; + freq_dev1 { + trip = <&freq_config1>; + cooling-device = + <&CPU0 9 9>;/*1036*/ + }; + freq_dev2 { + trip = <&freq_config1>; + cooling-device = + <&CPU4 13 13>;/*1056*/ + }; + freq_dev3 { + trip = <&freq_config1>; + cooling-device = + <&CPU7 16 16>;/*1171*/ + }; + freq_dev4 { + trip = <&freq_config2>; + cooling-device = + <&CPU0 11 11>;/*844*/ + }; + freq_dev5 { + trip = <&freq_config2>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev6 { + trip = <&freq_config2>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev7 { + trip = <&freq_config2>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev8 { + trip = <&freq_config2>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pa-therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-msm-therm { + trips { + freq_config3: freq_config3 { + temperature = <63000>; + hysteresis = <2000>; + type = "passive"; + }; + freq_config4: freq_config4 { + temperature = <65000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + cooling-maps { + freq_dev0 { + trip = <&freq_config3>; + cooling-device = + <&CPU0 2 2>;/*1632 18*/ + }; + freq_dev1 { + trip = <&freq_config3>; + cooling-device = + <&CPU4 8 8>;/*1612 17*/ + }; + freq_dev2 { + trip = <&freq_config3>; + cooling-device = + <&CPU7 9 9>;/*1920 20*/ + }; + freq_dev3 { + trip = <&freq_config4>; + cooling-device = + <&CPU0 4 4>;/*1478*/ + }; + freq_dev4 { + trip = <&freq_config4>; + cooling-device = + <&CPU4 11 11>;/*1286*/ + }; + freq_dev5 { + trip = <&freq_config4>; + cooling-device = + <&CPU7 13 13>;/*1497*/ + }; + freq_dev6 { + trip = <&freq_config3>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-3)>;/*499*/ + }; + freq_dev7 { + trip = <&freq_config4>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-2)>;/*427*/ + }; + }; + }; +}; + +/*tp 1.8v power change to gpio119 for T0 hw*/ +&qupv3_se17_i2c { + sec-s6sy761@48 { + status = "disable"; + // enable1v8_gpio = <&tlmm 119 0x00>; + pinctrl-0 = <&tp_irq_active &tp_rst_active &tp_1v8_t0_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_t0_suspend>; + }; +}; +&qupv3_se17_i2c { + st_fts@49{ + status = "disable"; + }; +}; +&qupv3_se17_i2c { + synaptics-s3706@20 { + //enable1v8_gpio = <&tlmm 119 0x00>; + project-name = "18857"; + reset-gpio = <&tlmm 54 0x00>; + touchpanel,display-coords = <1079 2339>; + touchpanel,panel-coords = <1079 2339>; + touchpanel,tx-rx-num = <16 33>; + pinctrl-0 = <&tp_irq_active &tp_1v8_t0_active &tp_rst_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_t0_suspend>; + }; + /delete-node/ sec-s6sy761@48; + /delete-node/ st_fts@49; +}; + +&tp_rst_active{ + mux { + pins = "gpio54"; + function = "gpio"; + }; + config { + pins = "gpio54"; + drive-strength = <8>; + bias-pull-up; + }; + +}; +&tlmm { + tp_1v8_t0_active: tp_1v8_t0_active { + mux { + pins = "gpio119"; + function = "gpio"; + }; + config { + pins = "gpio119"; + drive-strength = <8>; + bias-pull-up; + }; + }; + tp_1v8_t0_suspend: tp_1v8_t0_suspend { + mux { + pins = "gpio119"; + function = "gpio"; + }; + config { + pins = "gpio119"; + drive-strength = <8>; + bias-pull-down; + }; + }; +}; + +/* add for hall tri_state_key */ + +&tri_state_key { + compatible = "oneplus,hall_tri_state_key"; + status = "ok"; + interrupt-parent = <&tlmm>; +}; + +&qupv3_se9_i2c { + //qcom,clk-freq-out = <300000>; + status = "ok"; + magnachip@0D { + compatible = "tri_key_magnachip,tk_mxm1120,up"; + reg = <0x0D>; + vdd-supply = <&pm8150l_l7>; + magnachip,init-interval = <200>; + interrupt-parent = <&tlmm>; + interrupts = <26 0x02>; + dhall,irq-gpio = <&tlmm 26 0x2008>; + mxm,id = <1>; + pinctrl-names = "uphall_tri_state_key_active"; + pinctrl-0 = <&uphall_tri_state_key_active>; + }; + magnachip@0C { + compatible = "tri_key_magnachip,tk_mxm1120,down"; + reg = <0x0C>; + vdd-supply = <&pm8150l_l7>; + magnachip,init-interval = <200>; + interrupt-parent = <&tlmm>; + interrupts = <27 0x02>; + dhall,irq-gpio = <&tlmm 27 0x2008>; + mxm,id = <2>; + pinctrl-names = "downhall_tri_state_key_active"; + pinctrl-0 = <&downhall_tri_state_key_active>; + }; +}; + +&tlmm { + uphall_tri_state_key_active: uphall_tri_state_key_active { + mux { + pins = "gpio26"; + function = "gpio"; + }; + config { + pins = "gpio26"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + downhall_tri_state_key_active: downhall_tri_state_key_active { + mux { + pins = "gpio27"; + function = "gpio"; + }; + config { + pins = "gpio27"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +/* for Battery & Charging STRAT */ +&qupv3_se8_i2c { + oneplus_fastchg@26{ + microchip,mcu-en-gpio = <&tlmm 10 0x00>; + microchip,usb-sw-2-gpio = <&tlmm 59 0x00>; + }; +}; + +&pm8150b_charger { + /* for external ship mode support */ + op,stm-ctrl-gpio = <&tlmm 21 0x00>; + op,vbus-ctrl-gpio = <&pm8150_gpios 9 GPIO_ACTIVE_LOW>; + /* ibatmax setting for different temp regions */ + op,dis_ctrl_current; + ibatmax-little-cold-ma = <320>; + ibatmax-little-cool-thr-ma = <1750>; + ibatmax-cool-thr-ma = <1000>; + ibatmax-cool-ma = <1450>; + ibatmax-warm-ma = <1050>; + op,little_cold_term_current = <250>; + vph-sel-disable; +}; + +&mtp_batterydata { + #include "OP-fg-batterydata-3700mah.dtsi" +}; +/* for Battery & Charging END */ + +/* @bsp, USB oem config START*/ +&usb2_phy0 { + qcom,param-override-seq = + <0x67 0x6c/*Disconnection voltage +21.56%*/ + 0x09 0x70/*Pre-emphasis:4x DC voltage level:+13.30%*/ + 0x28 0x74>; +}; + +&extcon_usb1 { + status = "disabled"; +}; + +&usb1 { + status = "disabled"; +}; +/* @bsp, USB oem config END*/ + +&qupv3_se1_i2c { + magnachip@0C { + status = "disabled"; + }; + + magnachip@0D { + status = "disabled"; + }; +}; + +&vendor { + step_motor { + status = "disabled"; + }; +}; + +&motor_pl { + status = "disabled"; +}; + +&infrared_pl { + interrupt-parent = <&tlmm>; + interrupts = <163 0x2>; + infrared,irq-gpio = <&tlmm 163 0x2008>; + pinctrl-names = "infrared_input"; + pinctrl-0 = <&free_fall_input>; +}; + +&tlmm { + infrared_input: infrared_input { + mux { + pins = "gpio163"; + function = "gpio"; + }; + config { + pins = "gpio163"; + drive-strength = <2>; + input-enable; + bias-disable; //No Pull + }; + }; + +}; + + + + +&oem_rf_cable { + rf,cable-gpio-1 = <&pm8150_gpios 4 0>; + pinctrl-0 = <&rf_cable_ant0_active &rf_pm8150_cable_ant1>; +}; + +&oem_aboard_check { + /delete-property/ oem,aboard-gpio-1; + pinctrl-0 = <&ab_id1_default>; +}; + +&pm8150_gpios { + rf_pm8150_cable_ant1: rf_pm8150_cable_ant1 { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; +&pm8150b_gpios { + haptics_boost { + haptics_boost_default: haptics_boost_default { + pins = "gpio5"; + function = "normal"; + output-enable; + input-disable; + bias-disable; + qcom,drive-strength = <3>; /* high */ + power-source = <0>; /* VPH_PWR */ + }; + }; +}; +/* OnePlus add haptic, by yangfb*/ +&aw8697_haptic { + status = "disabled"; +}; + +&vendor { + step_motor { + status = "disabled"; + }; +}; + +&pm8150b_gpios { + haptics_boost { + haptics_boost_default: haptics_boost_default { + pins = "gpio5"; + function = "normal"; + output-enable; + input-disable; + bias-disable; + qcom,drive-strength = <3>; /* high */ + power-source = <0>; /* VPH_PWR */ + }; + }; +}; + +&vendor { + haptics_boost_vreg: haptics_boost_vreg { + compatible = "regulator-fixed"; + regulator-name = "haptics_boost"; + gpio = <&pm8150b_gpios 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-enable-ramp-delay = <300>; + pinctrl-names = "default"; + pinctrl-0 = <&haptics_boost_default>; + status = "ok"; + }; +}; +&pm8150b_haptics { + status = "ok"; + vdd-supply = <&haptics_boost_vreg>; + wf_5 { + qcom,wf-brake-pattern = [03 03 03 03]; + }; + wf_6 { + /* WEAK */ + qcom,effect-id = <6>; + qcom,wf-vmax-mv = <2500>; + qcom,wf-pattern = [7e 7e 7e fe fe]; + qcom,wf-play-rate-us = <6667>; + qcom,wf-brake-pattern = [00 00 00 00]; + qcom,lra-auto-resonance-disable; + }; + wf_7 { + /* MIDDLE */ + qcom,effect-id = <7>; + qcom,wf-vmax-mv = <2500>; + qcom,wf-pattern = [7e 7e 7e 7e fe fe fe]; + qcom,wf-play-rate-us = <6667>; + qcom,wf-brake-pattern = [00 00 00 00]; + qcom,lra-auto-resonance-disable; + }; + wf_8 { + /* STRONG */ + qcom,effect-id = <8>; + qcom,wf-vmax-mv = <2500>; + qcom,wf-pattern = [7e 7e 7e 7e 7e fe fe fe]; + qcom,wf-play-rate-us = <6667>; + qcom,wf-brake-pattern = [00 00 00 00]; + qcom,lra-auto-resonance-disable; + }; +}; + +&wdog{ + qcom,bark-time = <15000>; +}; diff --git a/arch/arm/boot/dts/qcom/guacamoleb_dvt.dtsi b/arch/arm/boot/dts/qcom/guacamoleb_dvt.dtsi new file mode 100644 index 000000000000..18b79ae52aba --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamoleb_dvt.dtsi @@ -0,0 +1 @@ +/*this is for one project different hw version */ \ No newline at end of file diff --git a/arch/arm/boot/dts/qcom/guacamoleb_evt.dtsi b/arch/arm/boot/dts/qcom/guacamoleb_evt.dtsi new file mode 100644 index 000000000000..18b79ae52aba --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamoleb_evt.dtsi @@ -0,0 +1 @@ +/*this is for one project different hw version */ \ No newline at end of file diff --git a/arch/arm/boot/dts/qcom/guacamoleb_pvt.dtsi b/arch/arm/boot/dts/qcom/guacamoleb_pvt.dtsi new file mode 100644 index 000000000000..18b79ae52aba --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamoleb_pvt.dtsi @@ -0,0 +1 @@ +/*this is for one project different hw version */ \ No newline at end of file diff --git a/arch/arm/boot/dts/qcom/guacamoleb_sm8150.dtsi b/arch/arm/boot/dts/qcom/guacamoleb_sm8150.dtsi new file mode 100644 index 000000000000..8ec64a5dc408 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamoleb_sm8150.dtsi @@ -0,0 +1,7 @@ +/*this is for sm8150 version */ +&ois_rear_0 { +ois_gyro,id = <3>;//18821 +}; +&ois_rear_1 { +ois_gyro,id = <3>;//18821 +}; diff --git a/arch/arm/boot/dts/qcom/guacamoleb_t0.dtsi b/arch/arm/boot/dts/qcom/guacamoleb_t0.dtsi new file mode 100644 index 000000000000..479382ca9ad9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamoleb_t0.dtsi @@ -0,0 +1,4 @@ +/*this is for one project different hw version */ + + + diff --git a/arch/arm/boot/dts/qcom/guacamoles-sdx50m-overlay-dvt.dts b/arch/arm/boot/dts/qcom/guacamoles-sdx50m-overlay-dvt.dts new file mode 100644 index 000000000000..5d9f553032f1 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamoles-sdx50m-overlay-dvt.dts @@ -0,0 +1,45 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamoles_sdx50m.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_dvt.dtsi" + +#include "guacamoles_sdx50m_dvt.dtsi" + +/ { + model = "SDX50M MTP 18825 15"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18825>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <15>; + +}; diff --git a/arch/arm/boot/dts/qcom/guacamoles-sdx50m-overlay-evt.dts b/arch/arm/boot/dts/qcom/guacamoles-sdx50m-overlay-evt.dts new file mode 100644 index 000000000000..2b3166bb0959 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamoles-sdx50m-overlay-evt.dts @@ -0,0 +1,45 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamoles_sdx50m.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" + +#include "guacamoles_sdx50m_evt.dtsi" + +/ { + model = "SDX50M MTP 18825 24"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18825>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <24>; + +}; diff --git a/arch/arm/boot/dts/qcom/guacamoles-sdx50m-overlay-pvt.dts b/arch/arm/boot/dts/qcom/guacamoles-sdx50m-overlay-pvt.dts new file mode 100644 index 000000000000..5e6f508497cc --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamoles-sdx50m-overlay-pvt.dts @@ -0,0 +1,45 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamoles_sdx50m.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_pvt.dtsi" + +#include "guacamoles_sdx50m_pvt.dtsi" + +/ { + model = "SDX50M MTP 18825 21"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18825>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <21>; + +}; diff --git a/arch/arm/boot/dts/qcom/guacamoles-sdx50m-overlay-t0.dts b/arch/arm/boot/dts/qcom/guacamoles-sdx50m-overlay-t0.dts new file mode 100644 index 000000000000..a2b12f352416 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamoles-sdx50m-overlay-t0.dts @@ -0,0 +1,44 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamoles_sdx50m.dtsi" +#include "guacamole_t0.dtsi" + +#include "guacamoles_sdx50m_t0.dtsi" + +/ { + model = "SDX50M MTP 18825 11"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18825>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <11>; + +}; diff --git a/arch/arm/boot/dts/qcom/guacamoles_sdx50m.dtsi b/arch/arm/boot/dts/qcom/guacamoles_sdx50m.dtsi new file mode 100644 index 000000000000..74a3457efd7b --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamoles_sdx50m.dtsi @@ -0,0 +1,11 @@ +/*this is for sdx50m project */ +&ois_rear_0 { +ois_gyro,id = <2>;//18827 +}; +&ois_rear_1 { +ois_gyro,id = <2>;//18827 +}; + +&pm8150b_charger { + op,dis_ctrl_current; +}; diff --git a/arch/arm/boot/dts/qcom/guacamoles_sdx50m_dvt.dtsi b/arch/arm/boot/dts/qcom/guacamoles_sdx50m_dvt.dtsi new file mode 100644 index 000000000000..50cb0f3e0436 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamoles_sdx50m_dvt.dtsi @@ -0,0 +1,2 @@ +/*this is for sdx50m project */ + diff --git a/arch/arm/boot/dts/qcom/guacamoles_sdx50m_evt.dtsi b/arch/arm/boot/dts/qcom/guacamoles_sdx50m_evt.dtsi new file mode 100644 index 000000000000..25e705a507d3 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamoles_sdx50m_evt.dtsi @@ -0,0 +1 @@ +/*this is for sdx50m project */ diff --git a/arch/arm/boot/dts/qcom/guacamoles_sdx50m_pvt.dtsi b/arch/arm/boot/dts/qcom/guacamoles_sdx50m_pvt.dtsi new file mode 100644 index 000000000000..25e705a507d3 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamoles_sdx50m_pvt.dtsi @@ -0,0 +1 @@ +/*this is for sdx50m project */ diff --git a/arch/arm/boot/dts/qcom/guacamoles_sdx50m_t0.dtsi b/arch/arm/boot/dts/qcom/guacamoles_sdx50m_t0.dtsi new file mode 100644 index 000000000000..25e705a507d3 --- /dev/null +++ b/arch/arm/boot/dts/qcom/guacamoles_sdx50m_t0.dtsi @@ -0,0 +1 @@ +/*this is for sdx50m project */ diff --git a/arch/arm/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm/boot/dts/qcom/ipq8074-hk01.dts new file mode 100644 index 000000000000..6a838b5d321e --- /dev/null +++ b/arch/arm/boot/dts/qcom/ipq8074-hk01.dts @@ -0,0 +1,52 @@ +/dts-v1/; +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "ipq8074.dtsi" + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + model = "Qualcomm Technologies, Inc. IPQ8074-HK01"; + compatible = "qcom,ipq8074-hk01", "qcom,ipq8074"; + interrupt-parent = <&intc>; + + aliases { + serial0 = &blsp1_uart5; + }; + + chosen { + stdout-path = "serial0"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x40000000 0x0 0x20000000>; + }; + + soc { + pinctrl@1000000 { + serial_4_pins: serial4_pinmux { + mux { + pins = "gpio23", "gpio24"; + function = "blsp4_uart1"; + bias-disable; + }; + }; + }; + + serial@78b3000 { + pinctrl-0 = <&serial_4_pins>; + pinctrl-names = "default"; + status = "ok"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/ipq8074.dtsi b/arch/arm/boot/dts/qcom/ipq8074.dtsi new file mode 100644 index 000000000000..2bc5dec5614d --- /dev/null +++ b/arch/arm/boot/dts/qcom/ipq8074.dtsi @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. IPQ8074"; + compatible = "qcom,ipq8074"; + + soc: soc { + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + pinctrl@1000000 { + compatible = "qcom,ipq8074-pinctrl"; + reg = <0x1000000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <0x2>; + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <0x3>; + reg = <0xb000000 0x1000>, <0xb002000 0x1000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + timer@b120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xb120000 0x1000>; + clock-frequency = <19200000>; + + frame@b120000 { + frame-number = <0>; + interrupts = , + ; + reg = <0xb121000 0x1000>, + <0xb122000 0x1000>; + }; + + frame@b123000 { + frame-number = <1>; + interrupts = ; + reg = <0xb123000 0x1000>; + status = "disabled"; + }; + + frame@b124000 { + frame-number = <2>; + interrupts = ; + reg = <0xb124000 0x1000>; + status = "disabled"; + }; + + frame@b125000 { + frame-number = <3>; + interrupts = ; + reg = <0xb125000 0x1000>; + status = "disabled"; + }; + + frame@b126000 { + frame-number = <4>; + interrupts = ; + reg = <0xb126000 0x1000>; + status = "disabled"; + }; + + frame@b127000 { + frame-number = <5>; + interrupts = ; + reg = <0xb127000 0x1000>; + status = "disabled"; + }; + + frame@b128000 { + frame-number = <6>; + interrupts = ; + reg = <0xb128000 0x1000>; + status = "disabled"; + }; + }; + + gcc: gcc@1800000 { + compatible = "qcom,gcc-ipq8074"; + reg = <0x1800000 0x80000>; + #clock-cells = <0x1>; + #reset-cells = <0x1>; + }; + + blsp1_uart5: serial@78b3000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78b3000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + }; + + cpus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x1>; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x2>; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + reg = <0x3>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <0x2>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + clocks { + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + xo: xo { + compatible = "fixed-clock"; + clock-frequency = <19200000>; + #clock-cells = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-atoll.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-atoll.dtsi new file mode 100644 index 000000000000..d96746cce5cd --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-atoll.dtsi @@ -0,0 +1,204 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include + +&soc { + kgsl_smmu: arm,smmu-kgsl@5040000 { + status = "ok"; + compatible = "qcom,smmu-v2"; + reg = <0x5040000 0x10000>; + #iommu-cells = <1>; + qcom,dynamic; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <2>; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cx_gdsc>; + qcom,deferred-regulator-disable-delay = <80>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clock-names = "gcc_gpu_memnoc_gfx_clk"; + clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>; + }; + + apps_smmu: apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x15182000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + anoc_1_tbu: anoc_1_tbu@0x15185000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15185000 0x1000>, + <0x15182200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + }; + + anoc_2_tbu: anoc_2_tbu@0x15189000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15189000 0x1000>, + <0x15182208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + }; + + mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x1518d000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x1518d000 0x1000>, + <0x15182210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>; + }; + + mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x15191000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15191000 0x1000>, + <0x15182218 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xc00 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>; + }; + + lpass_noc_tbu: lpass_noc_tbu@0x15195000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15195000 0x1000>, + <0x15182220 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1000 0x400>; + }; + + compute_dsp_0_tbu: compute_dsp_0_tbu@0x15199000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15199000 0x1000>, + <0x15182228 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1400 0x400>; + /* No GDSC */ + }; + }; + + kgsl_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x7>; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x1 0>; + }; + + apps_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x3 0>; + dma-coherent; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-qcs405.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-qcs405.dtsi new file mode 100644 index 000000000000..2338738e7c55 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-qcs405.dtsi @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + gfx_iommu: qcom,iommu@1f00000 { + status = "okay"; + compatible = "qcom,qsmmu-v500"; + reg = <0x1f00000 0x10000>, + <0x1ee2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,tz-device-id = "GPU"; + qcom,skip-init; + qcom,disable-atos; + qcom,dynamic; + qcom,use-3-lvl-tables; + #global-interrupts = <0>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + ; + clocks = <&clock_gcc GCC_SMMU_CFG_CLK>, + <&clock_gcc GCC_GFX_TCU_CLK>; + clock-names = "iface_clk", "core_clk"; + }; + + apps_smmu: qcom,iommu@1e00000 { + status = "okay"; + compatible = "qcom,qsmmu-v500"; + reg = <0x1e00000 0x40000>, + <0x1ee2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,tz-device-id = "APPS"; + qcom,skip-init; + qcom,disable-atos; + qcom,enable-static-cb; + qcom,use-3-lvl-tables; + #global-interrupts = <0>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&clock_gcc GCC_SMMU_CFG_CLK>, + <&clock_gcc GCC_APSS_TCU_CLK>; + clock-names = "iface_clk", "core_clk"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-sdmmagpie.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-sdmmagpie.dtsi new file mode 100644 index 000000000000..75decfcc9f8a --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-sdmmagpie.dtsi @@ -0,0 +1,358 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&soc { + kgsl_smmu: arm,smmu-kgsl@5040000 { + status = "ok"; + compatible = "qcom,smmu-v2"; + reg = <0x5040000 0x10000>; + #iommu-cells = <1>; + qcom,dynamic; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <2>; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cx_gdsc>; + qcom,deferred-regulator-disable-delay = <80>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clock-names = "gcc_gpu_memnoc_gfx_clk"; + clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>; + attach-impl-defs = + <0x6000 0x2378>, + <0x6060 0x1055>, + <0x678c 0x8>, + <0x6794 0x28>, + <0x6800 0x6>, + <0x6900 0x3ff>, + <0x6924 0x204>, + <0x6928 0x11000>, + <0x6930 0x800>, + <0x6960 0xffffffff>, + <0x6b64 0x1a5551>, + <0x6b68 0x9a82a382>; + }; + + apps_smmu: apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x15182000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + + anoc_1_tbu: anoc_1_tbu@0x15185000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15185000 0x1000>, + <0x15182200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + anoc_2_tbu: anoc_2_tbu@0x15189000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15189000 0x1000>, + <0x15182208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x1518d000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x1518d000 0x1000>, + <0x15182210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>; + qcom,msm-bus,name = "mnoc_hf_0_tbu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + mnoc_hf_1_tbu: mnoc_hf_1_tbu@0x15191000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15191000 0x1000>, + <0x15182218 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xc00 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>; + qcom,msm-bus,name = "mnoc_hf_1_tbu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x15195000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15195000 0x1000>, + <0x15182220 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1000 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>; + qcom,msm-bus,name = "mnoc_sf_0_tbu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + compute_dsp_0_tbu: compute_dsp_0_tbu@0x15199000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15199000 0x1000>, + <0x15182228 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1400 0x400>; + /* No GDSC */ + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + adsp_tbu: adsp_tbu@0x1519d000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x1519d000 0x1000>, + <0x15182230 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + anoc_1_pcie_tbu: anoc_1_pcie_tbu@0x151a1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151a1000 0x1000>, + <0x15182238 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1c00 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc>; + clock-names = "gcc_aggre_noc_pcie_tbu_clk"; + clocks = <&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + }; + + kgsl_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x7>; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x21 0>; + }; + + apps_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x23 0>; + dma-coherent; + }; +}; + +&apps_smmu { + qcom,actlr = + /* HF0 and HF1 TBUs: +3 deep PF */ + <0x800 0x7ff 0x103>, + + /* SF TBU: +3 deep PF */ + <0x1000 0x3ff 0x103>, + + /* NPU SIDs: +15 deep PF */ + <0x1460 0x1f 0x303>; +}; diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-sdmshrike.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-sdmshrike.dtsi new file mode 100644 index 000000000000..540cd72c26e5 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-sdmshrike.dtsi @@ -0,0 +1,444 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&soc { + kgsl_smmu: kgsl-smmu@0x02CA0000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x02CA0000 0x10000>, + <0x2CC2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,dynamic; + qcom,use-3-lvl-tables; + #global-interrupts = <2>; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cx_gdsc>; + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk"; + clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&clock_gpucc GPU_CC_AHB_CLK>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + ; + + gfx_0_tbu: gfx_0_tbu@0x2CC5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x2CC5000 0x1000>, + <0x2CC2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + }; + + gfx_1_tbu: gfx_1_tbu@0x2CC9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x2CC9000 0x1000>, + <0x2CC2208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + }; + + gfx_2_tbu: gfx_2_tbu@0x2CCD000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x2CCD000 0x1000>, + <0x2CC2210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + }; + + gfx_3_tbu: gfx_3_tbu@0x2CD1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x2CD1000 0x1000>, + <0x2CC2218 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xC00 0x400>; + }; + }; + + apps_smmu: apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x15182000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + + anoc_1_tbu: anoc_1_tbu@0x15185000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15185000 0x1000>, + <0x15182200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + anoc_2_tbu: anoc_2_tbu@0x15189000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15189000 0x1000>, + <0x15182208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x1518D000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x1518D000 0x1000>, + <0x15182210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>; + qcom,msm-bus,name = "mnoc_hf_0_tbu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + mnoc_hf_1_tbu: mnoc_hf_1_tbu@0x15191000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15191000 0x1000>, + <0x15182218 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xc00 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>; + qcom,msm-bus,name = "mnoc_hf_1_tbu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + compute_dsp_1_tbu: compute_dsp_1_tbu@0x15195000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15195000 0x1000>, + <0x15182220 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1000 0x400>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + compute_dsp_0_tbu: compute_dsp_0_tbu@0x15199000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15199000 0x1000>, + <0x15182228 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1400 0x400>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + adsp_tbu: adsp_tbu@0x1519D000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x1519D000 0x1000>, + <0x15182230 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + anoc_pcie: anoc_pcie@151A1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151A1000 0x1000>, + <0x15182238 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1c00 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc>; + clock-names = "gcc_aggre_noc_pcie_tbu_clk"; + clocks = <&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x151A5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151A5000 0x1000>, + <0x15182240 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x2000 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>; + qcom,msm-bus,name = "mnoc_sf_0_tbu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + }; + + kgsl_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x7 0>; + }; + + kgsl_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x9 0>; + dma-coherent; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x21 0>; + }; + + apps_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x23 0>; + dma-coherent; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-sdxprairie.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-sdxprairie.dtsi new file mode 100644 index 000000000000..7185473263bd --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-sdxprairie.dtsi @@ -0,0 +1,102 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&soc { + apps_smmu: apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x20000>, + <0x15022000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + + periph_tbu: periph_tbu@0x15025000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15025000 0x1000>, + <0x15022200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + ipa_tbu: ipa_tbu@0x15029000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15029000 0x1000>, + <0x15022208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x100 0x0>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-sm6150.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-sm6150.dtsi new file mode 100644 index 000000000000..5acf174d40c6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-sm6150.dtsi @@ -0,0 +1,317 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&soc { + kgsl_smmu: kgsl-smmu@0x50a0000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x50a0000 0x10000>, + <0x50c2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,dynamic; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <1>; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cx_gdsc>; + clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&clock_gpucc GPU_CC_AHB_CLK>, + <&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk"; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + ; + + gfx_0_tbu: gfx_0_tbu@0x50c5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x50c5000 0x1000>, + <0x50c2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + }; + + gfx_1_tbu: gfx_1_tbu@0x50c9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x50c9000 0x1000>, + <0x50c2208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + }; + }; + + apps_smmu: apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x80000>, + <0x150c2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + + anoc_1_tbu: anoc_1_tbu@0x150c5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150c5000 0x1000>, + <0x150c2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + anoc_2_tbu: anoc_2_tbu@0x150c9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150c9000 0x1000>, + <0x150c2208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x150cd000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150cd000 0x1000>, + <0x150c2210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>; + qcom,msm-bus,name = "mnoc_hf_0_tbu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x150d1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150d1000 0x1000>, + <0x150c2218 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xc00 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>; + qcom,msm-bus,name = "mnoc_sf_0_tbu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + compute_dsp_tbu: compute_dsp_tbu@0x150d5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150d5000 0x1000>, + <0x150c2220 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1000 0x400>; + /* No GDSC */ + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + adsp_tbu: adsp_tbu@0x150d9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x150d9000 0x1000>, + <0x150c2228 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1400 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + }; + + kgsl_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x7 0>; + }; + + kgsl_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x9 0>; + dma-coherent; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x21 0>; + }; + + apps_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x23 0>; + dma-coherent; + }; +}; + +&kgsl_smmu { + qcom,actlr = + /* All CBs of GFX: +15 deep PF */ + <0x0 0x7ff 0x303>; +}; + +&apps_smmu { + qcom,actlr = + /* HF and SF TBUs: +3 deep PF */ + <0x800 0x7ff 0x103>; +}; diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-sm8150-v2.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-sm8150-v2.dtsi new file mode 100644 index 000000000000..372566374c4e --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-sm8150-v2.dtsi @@ -0,0 +1,406 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&soc { + kgsl_smmu: kgsl-smmu@0x02ca0000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x02ca0000 0x10000>, + <0x2cc2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,dynamic; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <1>; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cx_gdsc>; + clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&clock_gpucc GPU_CC_AHB_CLK>; + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk"; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + ; + + gfx_0_tbu: gfx_0_tbu@0x2cc5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x2cc5000 0x1000>, + <0x2cc2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + }; + + gfx_1_tbu: gfx_1_tbu@0x2cc9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x2cc9000 0x1000>, + <0x2cc2208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + }; + }; + + apps_smmu: apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x15182000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + + anoc_1_tbu: anoc_1_tbu@0x15185000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15185000 0x1000>, + <0x15182200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + anoc_2_tbu: anoc_2_tbu@0x15189000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15189000 0x1000>, + <0x15182208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x1518d000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x1518d000 0x1000>, + <0x15182210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>; + qcom,msm-bus,name = "mnoc_hf_0_tbu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + mnoc_hf_1_tbu: mnoc_hf_1_tbu@0x15191000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15191000 0x1000>, + <0x15182218 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xc00 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>; + qcom,msm-bus,name = "mnoc_hf_1_tbu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + compute_dsp_1_tbu: compute_dsp_1_tbu@0x15195000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15195000 0x1000>, + <0x15182220 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1000 0x400>; + /* No GDSC */ + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + compute_dsp_0_tbu: compute_dsp_0_tbu@0x15199000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15199000 0x1000>, + <0x15182228 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1400 0x400>; + /* No GDSC */ + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + adsp_tbu: adsp_tbu@0x1519d000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x1519d000 0x1000>, + <0x15182230 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + anoc_1_pcie_tbu: anoc_1_pcie_tbu@0x151a1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151a1000 0x1000>, + <0x15182238 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1c00 0x400>; + qcom,opt-out-tbu-halting; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc>; + clock-names = "gcc_aggre_noc_pcie_tbu_clk"; + clocks = <&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x151a5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151a5000 0x1000>, + <0x15182240 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x2000 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>; + qcom,msm-bus,name = "mnoc_sf_0_tbu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + }; + + kgsl_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x7 0>; + }; + + kgsl_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x9 0>; + dma-coherent; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x21 0>; + }; + + apps_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x23 0>; + dma-coherent; + }; +}; + +&kgsl_smmu { + qcom,actlr = + /* All CBs of GFX: +15 deep PF */ + <0x0 0x407 0x303>; +}; + +&apps_smmu { + qcom,actlr = + /* HF0 and HF1 TBUs: +3 deep PF */ + <0x800 0x7ff 0x103>, + + /* SF TBU: +3 deep PF */ + <0x2000 0x3ff 0x103>, + + /* NPU SIDs: +15 deep PF */ + <0x1480 0x3 0x303>, + <0x1484 0x1 0x303>, + <0x1080 0x3 0x303>, + <0x1084 0x1 0x303>; +}; + diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-sm8150.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-sm8150.dtsi new file mode 100644 index 000000000000..7e59f3c78f18 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-sm8150.dtsi @@ -0,0 +1,420 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&soc { + kgsl_smmu: kgsl-smmu@0x02CA0000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x02CA0000 0x10000>, + <0x2CC2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,dynamic; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + qcom,min-iova-align; + #global-interrupts = <1>; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cx_gdsc>; + clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&clock_gpucc GPU_CC_AHB_CLK>; + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk"; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + ; + + gfx_0_tbu: gfx_0_tbu@0x2CC5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x2CC5000 0x1000>, + <0x2CC2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + }; + + gfx_1_tbu: gfx_1_tbu@0x2CC9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x2CC9000 0x1000>, + <0x2CC2208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + }; + }; + + apps_smmu: apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x15182000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + qcom,min-iova-align; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + + anoc_1_tbu: anoc_1_tbu@0x15185000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15185000 0x1000>, + <0x15182200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + anoc_2_tbu: anoc_2_tbu@0x15189000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15189000 0x1000>, + <0x15182208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x1518D000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x1518D000 0x1000>, + <0x15182210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>; + qcom,msm-bus,name = "mnoc_hf_0_tbu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + mnoc_hf_1_tbu: mnoc_hf_1_tbu@0x15191000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15191000 0x1000>, + <0x15182218 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xc00 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>; + qcom,msm-bus,name = "mnoc_hf_1_tbu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x15195000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15195000 0x1000>, + <0x15182220 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1000 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>; + qcom,msm-bus,name = "mnoc_sf_0_tbu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + compute_dsp_0_tbu: compute_dsp_0_tbu@0x15199000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x15199000 0x1000>, + <0x15182228 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1400 0x400>; + /* No GDSC */ + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + adsp_tbu: adsp_tbu@0x1519D000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x1519D000 0x1000>, + <0x15182230 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + anoc_1_pcie_tbu: anoc_1_pcie_tbu@0x151A1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151A1000 0x1000>, + <0x15182238 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1c00 0x400>; + qcom,opt-out-tbu-halting; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc>; + clock-names = "gcc_aggre_noc_pcie_tbu_clk"; + clocks = <&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + + compute_dsp_1_tbu: compute_dsp_1_tbu@0x151A5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151A5000 0x1000>, + <0x15182240 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x2000 0x400>; + /* No GDSC */ + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + }; + }; + + kgsl_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x7 0>; + }; + + kgsl_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x9 0>; + dma-coherent; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x21 0>; + }; + + apps_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x23 0>; + dma-coherent; + }; +}; + +&kgsl_smmu { + qcom,actlr = + /* All CBs of GFX: +15 deep PF */ + <0x0 0x407 0x303>; +}; + +&apps_smmu { + qcom,actlr = + /* SIDs 0x1460 - 0x1463 of NPU: +3 deep PF */ + <0x1460 0x3 0x103>, + + /* SIDs 0x1464 - 0x1465 of NPU: +3 deep PF */ + <0x1464 0x1 0x103>, + + /* SIDs 0x2060 - 0x2063 of NPU: +3 deep PF */ + <0x2060 0x3 0x103>, + + /* SIDs 0x2064 - 0x2065 of NPU: +3 deep PF */ + <0x2064 0x1 0x103>, + + /* Display SIDs: +3 deep PF */ + <0x0800 0x0420 0x103>, + <0x0801 0x0420 0x103>, + <0x1040 0x0001 0x103>, + + /* Video SIDs: +3 deep PF */ + <0x1300 0x0060 0x103>, + <0x1301 0x0004 0x103>, + <0x1303 0x0020 0x103>, + <0x1304 0x0060 0x103>, + <0x1342 0x0000 0x103>; +}; + diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-trinket.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-trinket.dtsi new file mode 100644 index 000000000000..6fab5f53ea61 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-trinket.dtsi @@ -0,0 +1,280 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&soc { + kgsl_smmu: kgsl-smmu@0x59a0000 { + status = "okay"; + compatible = "qcom,qsmmu-v500"; + reg = <0x59a0000 0x10000>, + <0x59c2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,dynamic; + qcom,skip-init; + qcom,no-dynamic-asid; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cx_gdsc>; + qcom,deferred-regulator-disable-delay = <80>; + clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&clock_gpucc GPU_CC_AHB_CLK>, + <&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk"; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + ; + + gfx_0_tbu: gfx_0_tbu@0x59c5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x59c5000 0x1000>, + <0x59c2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + }; + }; + + apps_smmu: apps-smmu@0xc600000 { + status = "okay"; + compatible = "qcom,qsmmu-v500"; + reg = <0xc600000 0x80000>, + <0xc782000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>; + anoc_1_tbu: anoc_1_tbu@0xc785000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0xc785000 0x1000>, + <0xc782200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>, + , + , + <0 0>, + , + , + <0 1000>; + }; + + mm_rt_tbu: mm_rt_tbu@0xc789000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0xc789000 0x1000>, + <0xc782208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>, + , + , + <0 0>, + , + , + <0 1000>; + }; + + mm_nrt_tbu: mm_nrt_tbu@0xc78d000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0xc78d000 0x1000>, + <0xc782210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>, + , + , + <0 0>, + , + , + <0 1000>; + }; + + cdsp_tbu: cdsp_tbu@0xc791000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0xc791000 0x1000>, + <0xc782218 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xc00 0x400>; + qcom,regulator-names = "vdd"; + vdd-supply = <&hlos1_vote_turing_mmu_tbu0_gdsc>; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + , + , + <0 0>, + , + , + <0 1000>, + , + , + <0 0>, + , + , + <0 1000>; + }; + }; + + kgsl_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x7 0>; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x21 0>; + }; +}; + +&kgsl_smmu { + qcom,actlr = + /* All CBs of GFX: +15 deep PF */ + <0x0 0x3ff 0x303>; +}; + +&apps_smmu { + qcom,actlr = + /* MMRT and MMNRT TBUs: +3 deep PF */ + <0x400 0x3ff 0x103>, + <0x800 0x3ff 0x103>; +}; diff --git a/arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi b/arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi new file mode 100644 index 000000000000..34a342a42561 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi @@ -0,0 +1,738 @@ +/* + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + pcm0: qcom,msm-pcm { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <0>; + }; + + routing: qcom,msm-pcm-routing { + compatible = "qcom,msm-pcm-routing"; + }; + + compr: qcom,msm-compr-dsp { + compatible = "qcom,msm-compr-dsp"; + }; + + pcm1: qcom,msm-pcm-low-latency { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <1>; + qcom,msm-pcm-low-latency; + qcom,latency-level = "regular"; + }; + + pcm2: qcom,msm-ultra-low-latency { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <2>; + qcom,msm-pcm-low-latency; + qcom,latency-level = "ultra"; + }; + + pcm_noirq: qcom,msm-pcm-dsp-noirq { + compatible = "qcom,msm-pcm-dsp-noirq"; + qcom,msm-pcm-low-latency; + qcom,latency-level = "ultra"; + }; + + trans_loopback: qcom,msm-transcode-loopback { + compatible = "qcom,msm-transcode-loopback"; + }; + + compress: qcom,msm-compress-dsp { + compatible = "qcom,msm-compress-dsp"; + }; + + voip: qcom,msm-voip-dsp { + compatible = "qcom,msm-voip-dsp"; + }; + + voice: qcom,msm-pcm-voice { + compatible = "qcom,msm-pcm-voice"; + qcom,destroy-cvd; + }; + + stub_codec: qcom,msm-stub-codec { + compatible = "qcom,msm-stub-codec"; + }; + + qcom,msm-dai-fe { + compatible = "qcom,msm-dai-fe"; + }; + + afe: qcom,msm-pcm-afe { + compatible = "qcom,msm-pcm-afe"; + }; + + dai_hdmi: qcom,msm-dai-q6-hdmi { + compatible = "qcom,msm-dai-q6-hdmi"; + qcom,msm-dai-q6-dev-id = <8>; + }; + + dai_dp: qcom,msm-dai-q6-dp { + compatible = "qcom,msm-dai-q6-hdmi"; + qcom,msm-dai-q6-dev-id = <24608>; + }; + + loopback: qcom,msm-pcm-loopback { + compatible = "qcom,msm-pcm-loopback"; + }; + + loopback1: qcom,msm-pcm-loopback-low-latency { + compatible = "qcom,msm-pcm-loopback"; + qcom,msm-pcm-loopback-low-latency; + }; + + pcm_dtmf: qcom,msm-pcm-dtmf { + compatible = "qcom,msm-pcm-dtmf"; + }; + + msm_dai_mi2s: qcom,msm-dai-mi2s { + compatible = "qcom,msm-dai-mi2s"; + dai_mi2s0: qcom,msm-dai-q6-mi2s-prim { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <0>; + qcom,msm-mi2s-rx-lines = <3>; + qcom,msm-mi2s-tx-lines = <0>; + }; + + dai_mi2s1: qcom,msm-dai-q6-mi2s-sec { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <1>; + qcom,msm-mi2s-rx-lines = <1>; + qcom,msm-mi2s-tx-lines = <0>; + }; + + dai_mi2s2: qcom,msm-dai-q6-mi2s-tert { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <2>; + qcom,msm-mi2s-rx-lines = <0>; + qcom,msm-mi2s-tx-lines = <3>; + }; + + dai_mi2s3: qcom,msm-dai-q6-mi2s-quat { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <3>; + qcom,msm-mi2s-rx-lines = <1>; + qcom,msm-mi2s-tx-lines = <2>; + }; + + dai_mi2s4: qcom,msm-dai-q6-mi2s-quin { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <4>; + qcom,msm-mi2s-rx-lines = <1>; + qcom,msm-mi2s-tx-lines = <2>; + }; + + dai_mi2s5: qcom,msm-dai-q6-mi2s-senary { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <6>; + qcom,msm-mi2s-rx-lines = <0>; + qcom,msm-mi2s-tx-lines = <3>; + }; + }; + + msm_dai_cdc_dma: qcom,msm-dai-cdc-dma { + compatible = "qcom,msm-dai-cdc-dma"; + wsa_cdc_dma_0_rx: qcom,msm-dai-wsa-cdc-dma-0-rx { + compatible = "qcom,msm-dai-cdc-dma-dev"; + qcom,msm-dai-cdc-dma-dev-id = <45056>; + }; + + wsa_cdc_dma_0_tx: qcom,msm-dai-wsa-cdc-dma-0-tx { + compatible = "qcom,msm-dai-cdc-dma-dev"; + qcom,msm-dai-cdc-dma-dev-id = <45057>; + }; + + wsa_cdc_dma_1_rx: qcom,msm-dai-wsa-cdc-dma-1-rx { + compatible = "qcom,msm-dai-cdc-dma-dev"; + qcom,msm-dai-cdc-dma-dev-id = <45058>; + }; + + wsa_cdc_dma_1_tx: qcom,msm-dai-wsa-cdc-dma-1-tx { + compatible = "qcom,msm-dai-cdc-dma-dev"; + qcom,msm-dai-cdc-dma-dev-id = <45059>; + }; + + wsa_cdc_dma_2_tx: qcom,msm-dai-wsa-cdc-dma-2-tx { + compatible = "qcom,msm-dai-cdc-dma-dev"; + qcom,msm-dai-cdc-dma-dev-id = <45061>; + }; + + va_cdc_dma_0_tx: qcom,msm-dai-va-cdc-dma-0-tx { + compatible = "qcom,msm-dai-cdc-dma-dev"; + qcom,msm-dai-cdc-dma-dev-id = <45089>; + }; + + va_cdc_dma_1_tx: qcom,msm-dai-va-cdc-dma-1-tx { + compatible = "qcom,msm-dai-cdc-dma-dev"; + qcom,msm-dai-cdc-dma-dev-id = <45091>; + }; + + rx_cdc_dma_0_rx: qcom,msm-dai-rx-cdc-dma-0-rx { + compatible = "qcom,msm-dai-cdc-dma-dev"; + qcom,msm-dai-cdc-dma-dev-id = <45104>; + }; + + rx_cdc_dma_1_rx: qcom,msm-dai-rx-cdc-dma-1-rx { + compatible = "qcom,msm-dai-cdc-dma-dev"; + qcom,msm-dai-cdc-dma-dev-id = <45106>; + }; + + rx_cdc_dma_2_rx: qcom,msm-dai-rx-cdc-dma-2-rx { + compatible = "qcom,msm-dai-cdc-dma-dev"; + qcom,msm-dai-cdc-dma-dev-id = <45108>; + }; + + rx_cdc_dma_3_rx: qcom,msm-dai-rx-cdc-dma-3-rx { + compatible = "qcom,msm-dai-cdc-dma-dev"; + qcom,msm-dai-cdc-dma-dev-id = <45110>; + }; + + rx_cdc_dma_4_rx: qcom,msm-dai-rx-cdc-dma-4-rx { + compatible = "qcom,msm-dai-cdc-dma-dev"; + qcom,msm-dai-cdc-dma-dev-id = <45112>; + }; + + rx_cdc_dma_5_rx: qcom,msm-dai-rx-cdc-dma-5-rx { + compatible = "qcom,msm-dai-cdc-dma-dev"; + qcom,msm-dai-cdc-dma-dev-id = <45114>; + }; + + rx_cdc_dma_6_rx: qcom,msm-dai-rx-cdc-dma-6-rx { + compatible = "qcom,msm-dai-cdc-dma-dev"; + qcom,msm-dai-cdc-dma-dev-id = <45116>; + }; + + rx_cdc_dma_7_rx: qcom,msm-dai-rx-cdc-dma-7-rx { + compatible = "qcom,msm-dai-cdc-dma-dev"; + qcom,msm-dai-cdc-dma-dev-id = <45118>; + }; + + tx_cdc_dma_0_tx: qcom,msm-dai-tx-cdc-dma-0-tx { + compatible = "qcom,msm-dai-cdc-dma-dev"; + qcom,msm-dai-cdc-dma-dev-id = <45105>; + }; + + tx_cdc_dma_1_tx: qcom,msm-dai-tx-cdc-dma-1-tx { + compatible = "qcom,msm-dai-cdc-dma-dev"; + qcom,msm-dai-cdc-dma-dev-id = <45107>; + }; + + tx_cdc_dma_2_tx: qcom,msm-dai-tx-cdc-dma-2-tx { + compatible = "qcom,msm-dai-cdc-dma-dev"; + qcom,msm-dai-cdc-dma-dev-id = <45109>; + }; + + tx_cdc_dma_3_tx: qcom,msm-dai-tx-cdc-dma-3-tx { + compatible = "qcom,msm-dai-cdc-dma-dev"; + qcom,msm-dai-cdc-dma-dev-id = <45111>; + }; + + tx_cdc_dma_4_tx: qcom,msm-dai-tx-cdc-dma-4-tx { + compatible = "qcom,msm-dai-cdc-dma-dev"; + qcom,msm-dai-cdc-dma-dev-id = <45113>; + }; + + tx_cdc_dma_5_tx: qcom,msm-dai-tx-cdc-dma-5-tx { + compatible = "qcom,msm-dai-cdc-dma-dev"; + qcom,msm-dai-cdc-dma-dev-id = <45115>; + }; + + }; + + lsm: qcom,msm-lsm-client { + compatible = "qcom,msm-lsm-client"; + }; + + qcom,msm-dai-q6 { + compatible = "qcom,msm-dai-q6"; + sb_0_rx: qcom,msm-dai-q6-sb-0-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16384>; + }; + + sb_0_tx: qcom,msm-dai-q6-sb-0-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16385>; + }; + + sb_1_rx: qcom,msm-dai-q6-sb-1-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16386>; + }; + + sb_1_tx: qcom,msm-dai-q6-sb-1-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16387>; + }; + + sb_2_rx: qcom,msm-dai-q6-sb-2-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16388>; + }; + + sb_2_tx: qcom,msm-dai-q6-sb-2-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16389>; + }; + + + sb_3_rx: qcom,msm-dai-q6-sb-3-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16390>; + }; + + sb_3_tx: qcom,msm-dai-q6-sb-3-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16391>; + }; + + sb_4_rx: qcom,msm-dai-q6-sb-4-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16392>; + }; + + sb_4_tx: qcom,msm-dai-q6-sb-4-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16393>; + }; + + sb_5_tx: qcom,msm-dai-q6-sb-5-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16395>; + }; + + sb_5_rx: qcom,msm-dai-q6-sb-5-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16394>; + }; + + sb_6_rx: qcom,msm-dai-q6-sb-6-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16396>; + }; + + sb_7_rx: qcom,msm-dai-q6-sb-7-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16398>; + }; + + sb_7_tx: qcom,msm-dai-q6-sb-7-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16399>; + }; + + sb_8_rx: qcom,msm-dai-q6-sb-8-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16400>; + }; + + sb_8_tx: qcom,msm-dai-q6-sb-8-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16401>; + }; + + sb_9_rx: qcom,msm-dai-q6-sb-9-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16402>; + }; + + sb_9_tx: qcom,msm-dai-q6-sb-9-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <16403>; + }; + + bt_sco_rx: qcom,msm-dai-q6-bt-sco-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12288>; + }; + + bt_sco_tx: qcom,msm-dai-q6-bt-sco-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12289>; + }; + + int_fm_rx: qcom,msm-dai-q6-int-fm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12292>; + }; + + int_fm_tx: qcom,msm-dai-q6-int-fm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <12293>; + }; + + afe_pcm_rx: qcom,msm-dai-q6-be-afe-pcm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <224>; + }; + + afe_pcm_tx: qcom,msm-dai-q6-be-afe-pcm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <225>; + }; + + afe_proxy_rx: qcom,msm-dai-q6-afe-proxy-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <241>; + }; + + afe_proxy_tx: qcom,msm-dai-q6-afe-proxy-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <240>; + }; + + incall_record_rx: qcom,msm-dai-q6-incall-record-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32771>; + }; + + incall_record_tx: qcom,msm-dai-q6-incall-record-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32772>; + }; + + incall_music_rx: qcom,msm-dai-q6-incall-music-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32773>; + }; + + incall_music_2_rx: qcom,msm-dai-q6-incall-music-2-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32770>; + }; + + usb_audio_rx: qcom,msm-dai-q6-usb-audio-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <28672>; + }; + + usb_audio_tx: qcom,msm-dai-q6-usb-audio-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <28673>; + }; + }; + + hostless: qcom,msm-pcm-hostless { + compatible = "qcom,msm-pcm-hostless"; + }; + + audio_apr: qcom,msm-audio-apr { + compatible = "qcom,msm-audio-apr"; + qcom,subsys-name = "apr_adsp"; + + msm_audio_ion: qcom,msm-audio-ion { + compatible = "qcom,msm-audio-ion"; + qcom,smmu-version = <2>; + qcom,smmu-enabled; + iommus = <&apps_smmu 0x1b21 0x0>; + }; + }; + + dai_pri_auxpcm: qcom,msm-pri-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "primary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + dai_sec_auxpcm: qcom,msm-sec-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "secondary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + dai_tert_auxpcm: qcom,msm-tert-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "tertiary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + dai_quat_auxpcm: qcom,msm-quat-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "quaternary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + dai_quin_auxpcm: qcom,msm-quin-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "quinary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + hdmi_dba: qcom,msm-hdmi-dba-codec-rx { + compatible = "qcom,msm-hdmi-dba-codec-rx"; + qcom,dba-bridge-chip = "adv7533"; + }; + + qcom,msm-adsp-loader { + status = "ok"; + compatible = "qcom,adsp-loader"; + qcom,adsp-state = <0>; + }; + + tdm_pri_rx: qcom,msm-dai-tdm-pri-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37120>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36864>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_pri_tdm_rx_0: qcom,msm-dai-q6-tdm-pri-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36864>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_pri_tx: qcom,msm-dai-tdm-pri-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37121>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36865>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_pri_tdm_tx_0: qcom,msm-dai-q6-tdm-pri-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36865>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sec_rx: qcom,msm-dai-tdm-sec-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37136>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36880>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_sec_tdm_rx_0: qcom,msm-dai-q6-tdm-sec-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36880>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sec_tx: qcom,msm-dai-tdm-sec-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37137>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36881>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_sec_tdm_tx_0: qcom,msm-dai-q6-tdm-sec-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36881>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_tert_rx: qcom,msm-dai-tdm-tert-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37152>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36896>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_tert_tdm_rx_0: qcom,msm-dai-q6-tdm-tert-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36896>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_tert_tx: qcom,msm-dai-tdm-tert-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37153>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36897 >; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_tert_tdm_tx_0: qcom,msm-dai-q6-tdm-tert-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36897 >; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quat_rx: qcom,msm-dai-tdm-quat-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37168>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36912>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_quat_tdm_rx_0: qcom,msm-dai-q6-tdm-quat-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36912>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quat_tx: qcom,msm-dai-tdm-quat-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37169>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36913 >; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_quat_tdm_tx_0: qcom,msm-dai-q6-tdm-quat-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36913 >; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quin_rx: qcom,msm-dai-tdm-quin-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37184>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36928>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_quin_tdm_rx_0: qcom,msm-dai-q6-tdm-quin-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36928>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quin_tx: qcom,msm-dai-tdm-quin-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37185>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36929>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + dai_quin_tdm_tx_0: qcom,msm-dai-q6-tdm-quin-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36929>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + dai_pri_spdif_rx: qcom,msm-dai-q6-spdif-pri-rx { + compatible = "qcom,msm-dai-q6-spdif"; + qcom,msm-dai-q6-dev-id = <20480>; + }; + + dai_pri_spdif_tx: qcom,msm-dai-q6-spdif-pri-tx { + compatible = "qcom,msm-dai-q6-spdif"; + qcom,msm-dai-q6-dev-id = <20481>; + }; + + dai_sec_spdif_rx: qcom,msm-dai-q6-spdif-sec-rx { + compatible = "qcom,msm-dai-q6-spdif"; + qcom,msm-dai-q6-dev-id = <20482>; + }; + + dai_sec_spdif_tx: qcom,msm-dai-q6-spdif-sec-tx { + compatible = "qcom,msm-dai-q6-spdif"; + qcom,msm-dai-q6-dev-id = <20483>; + }; + + afe_loopback_tx: qcom,msm-dai-q6-afe-loopback-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <24577>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm-qvr-external.dtsi b/arch/arm/boot/dts/qcom/msm-qvr-external.dtsi new file mode 100644 index 000000000000..3bc08d65cb65 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-qvr-external.dtsi @@ -0,0 +1,21 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + qcom,smp2p_interrupt_qvrexternal_5_out { + compatible = "qcom,smp2p-interrupt-qvrexternal-5-out"; + qcom,smem-states = <&smp2p_qvrexternal5_out 0>; + qcom,smem-state-names = "qvrexternal-smp2p-out"; + }; + +}; diff --git a/arch/arm/boot/dts/qcom/msm-rdbg.dtsi b/arch/arm/boot/dts/qcom/msm-rdbg.dtsi new file mode 100644 index 000000000000..426e105b0b87 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-rdbg.dtsi @@ -0,0 +1,35 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + /* smp2p information */ + qcom,smp2p_interrupt_rdbg_2_out { + compatible = "qcom,smp2p-interrupt-rdbg-2-out"; + qcom,smem-states = <&smp2p_rdbg2_out 0>; + qcom,smem-state-names = "rdbg-smp2p-out"; + }; + qcom,smp2p_interrupt_rdbg_2_in { + compatible = "qcom,smp2p-interrupt-rdbg-2-in"; + interrupts-extended = <&smp2p_rdbg2_in 0 0>; + interrupt-names = "rdbg-smp2p-in"; + }; + qcom,smp2p_interrupt_rdbg_5_out { + compatible = "qcom,smp2p-interrupt-rdbg-5-out"; + qcom,smem-states = <&smp2p_rdbg5_out 0>; + qcom,smem-state-names = "rdbg-smp2p-out"; + }; + qcom,smp2p_interrupt_rdbg_5_in { + compatible = "qcom,smp2p-interrupt-rdbg-5-in"; + interrupts-extended = <&smp2p_rdbg5_in 0 0>; + interrupt-names = "rdbg-smp2p-in"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm-wsa881x.dtsi b/arch/arm/boot/dts/qcom/msm-wsa881x.dtsi new file mode 100644 index 000000000000..59adb6c6d8fd --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-wsa881x.dtsi @@ -0,0 +1,77 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&slim_aud { + pahu_codec { + swr_master { + compatible = "qcom,swr-wcd"; + #address-cells = <2>; + #size-cells = <0>; + + wsa881x_0211: wsa881x@20170211 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170211>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>; + }; + + wsa881x_0212: wsa881x@20170212 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170212>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>; + }; + + wsa881x_0213: wsa881x@21170213 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170213>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>; + }; + + wsa881x_0214: wsa881x@21170214 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170214>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>; + }; + }; + }; + + tavil_codec { + swr_master { + compatible = "qcom,swr-wcd"; + #address-cells = <2>; + #size-cells = <0>; + + wsa881x_70211: wsa881x@20170211 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170211>; + qcom,spkr-sd-n-node = <&wsa_spk_wcd_sd1>; + }; + + wsa881x_70212: wsa881x@20170212 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170212>; + qcom,spkr-sd-n-node = <&wsa_spk_wcd_sd2>; + }; + + wsa881x_70213: wsa881x@21170213 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170213>; + qcom,spkr-sd-n-node = <&wsa_spk_wcd_sd1>; + }; + + wsa881x_70214: wsa881x@21170214 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170214>; + qcom,spkr-sd-n-node = <&wsa_spk_wcd_sd2>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm8916-mtp.dts b/arch/arm/boot/dts/qcom/msm8916-mtp.dts new file mode 100644 index 000000000000..b0a064d3806b --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8916-mtp.dts @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "msm8916-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM 8916 MTP"; + compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp/1", + "qcom,msm8916", "qcom,mtp"; +}; diff --git a/arch/arm/boot/dts/qcom/msm8916-mtp.dtsi b/arch/arm/boot/dts/qcom/msm8916-mtp.dtsi new file mode 100644 index 000000000000..ceeb8a6feed6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8916-mtp.dtsi @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msm8916.dtsi" +#include "pm8916.dtsi" + +/ { + aliases { + serial0 = &blsp1_uart2; + usid0 = &pm8916_0; + }; + + chosen { + stdout-path = "serial0"; + }; + + soc { + serial@78b0000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm/boot/dts/qcom/msm8916-pins.dtsi new file mode 100644 index 000000000000..4cb0b5834143 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8916-pins.dtsi @@ -0,0 +1,736 @@ +/* + * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&msmgpio { + + blsp1_uart1_default: blsp1_uart1_default { + pinmux { + function = "blsp_uart1"; + // TX, RX, CTS_N, RTS_N + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + }; + pinconf { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp1_uart1_sleep: blsp1_uart1_sleep { + pinmux { + function = "gpio"; + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + }; + pinconf { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart2_default: blsp1_uart2_default { + pinmux { + function = "blsp_uart2"; + pins = "gpio4", "gpio5"; + }; + pinconf { + pins = "gpio4", "gpio5"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp1_uart2_sleep: blsp1_uart2_sleep { + pinmux { + function = "gpio"; + pins = "gpio4", "gpio5"; + }; + pinconf { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + spi1_default: spi1_default { + pinmux { + function = "blsp_spi1"; + pins = "gpio0", "gpio1", "gpio3"; + }; + pinmux_cs { + function = "gpio"; + pins = "gpio2"; + }; + pinconf { + pins = "gpio0", "gpio1", "gpio3"; + drive-strength = <12>; + bias-disable; + }; + pinconf_cs { + pins = "gpio2"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + spi1_sleep: spi1_sleep { + pinmux { + function = "gpio"; + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + }; + pinconf { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + spi2_default: spi2_default { + pinmux { + function = "blsp_spi2"; + pins = "gpio4", "gpio5", "gpio7"; + }; + pinmux_cs { + function = "gpio"; + pins = "gpio6"; + }; + pinconf { + pins = "gpio4", "gpio5", "gpio7"; + drive-strength = <12>; + bias-disable; + }; + pinconf_cs { + pins = "gpio6"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + spi2_sleep: spi2_sleep { + pinmux { + function = "gpio"; + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + }; + pinconf { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + spi3_default: spi3_default { + pinmux { + function = "blsp_spi3"; + pins = "gpio8", "gpio9", "gpio11"; + }; + pinmux_cs { + function = "gpio"; + pins = "gpio10"; + }; + pinconf { + pins = "gpio8", "gpio9", "gpio11"; + drive-strength = <12>; + bias-disable; + }; + pinconf_cs { + pins = "gpio10"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + spi3_sleep: spi3_sleep { + pinmux { + function = "gpio"; + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + }; + pinconf { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + spi4_default: spi4_default { + pinmux { + function = "blsp_spi4"; + pins = "gpio12", "gpio13", "gpio15"; + }; + pinmux_cs { + function = "gpio"; + pins = "gpio14"; + }; + pinconf { + pins = "gpio12", "gpio13", "gpio15"; + drive-strength = <12>; + bias-disable; + }; + pinconf_cs { + pins = "gpio14"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + spi4_sleep: spi4_sleep { + pinmux { + function = "gpio"; + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + }; + pinconf { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + spi5_default: spi5_default { + pinmux { + function = "blsp_spi5"; + pins = "gpio16", "gpio17", "gpio19"; + }; + pinmux_cs { + function = "gpio"; + pins = "gpio18"; + }; + pinconf { + pins = "gpio16", "gpio17", "gpio19"; + drive-strength = <12>; + bias-disable; + }; + pinconf_cs { + pins = "gpio18"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + spi5_sleep: spi5_sleep { + pinmux { + function = "gpio"; + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + }; + pinconf { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + spi6_default: spi6_default { + pinmux { + function = "blsp_spi6"; + pins = "gpio20", "gpio21", "gpio23"; + }; + pinmux_cs { + function = "gpio"; + pins = "gpio22"; + }; + pinconf { + pins = "gpio20", "gpio21", "gpio23"; + drive-strength = <12>; + bias-disable; + }; + pinconf_cs { + pins = "gpio22"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + spi6_sleep: spi6_sleep { + pinmux { + function = "gpio"; + pins = "gpio20", "gpio21", "gpio22", "gpio23"; + }; + pinconf { + pins = "gpio20", "gpio21", "gpio22", "gpio23"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + i2c2_default: i2c2_default { + pinmux { + function = "blsp_i2c2"; + pins = "gpio6", "gpio7"; + }; + pinconf { + pins = "gpio6", "gpio7"; + drive-strength = <16>; + bias-disable = <0>; + }; + }; + + i2c2_sleep: i2c2_sleep { + pinmux { + function = "gpio"; + pins = "gpio6", "gpio7"; + }; + pinconf { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable = <0>; + }; + }; + + i2c4_default: i2c4_default { + pinmux { + function = "blsp_i2c4"; + pins = "gpio14", "gpio15"; + }; + pinconf { + pins = "gpio14", "gpio15"; + drive-strength = <16>; + bias-disable = <0>; + }; + }; + + i2c4_sleep: i2c4_sleep { + pinmux { + function = "gpio"; + pins = "gpio14", "gpio15"; + }; + pinconf { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable = <0>; + }; + }; + + i2c6_default: i2c6_default { + pinmux { + function = "blsp_i2c6"; + pins = "gpio22", "gpio23"; + }; + pinconf { + pins = "gpio22", "gpio23"; + drive-strength = <16>; + bias-disable = <0>; + }; + }; + + i2c6_sleep: i2c6_sleep { + pinmux { + function = "gpio"; + pins = "gpio22", "gpio23"; + }; + pinconf { + pins = "gpio22", "gpio23"; + drive-strength = <2>; + bias-disable = <0>; + }; + }; + + sdhc2_cd_pin { + sdc2_cd_on: cd_on { + pinmux { + function = "gpio"; + pins = "gpio38"; + }; + pinconf { + pins = "gpio38"; + drive-strength = <2>; + bias-pull-up; + }; + }; + sdc2_cd_off: cd_off { + pinmux { + function = "gpio"; + pins = "gpio38"; + }; + pinconf { + pins = "gpio38"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + pmx_sdc1_clk { + sdc1_clk_on: clk_on { + pinmux { + pins = "sdc1_clk"; + }; + pinconf { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + }; + sdc1_clk_off: clk_off { + pinmux { + pins = "sdc1_clk"; + }; + pinconf { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + }; + }; + + pmx_sdc1_cmd { + sdc1_cmd_on: cmd_on { + pinmux { + pins = "sdc1_cmd"; + }; + pinconf { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + }; + sdc1_cmd_off: cmd_off { + pinmux { + pins = "sdc1_cmd"; + }; + pinconf { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + }; + }; + + pmx_sdc1_data { + sdc1_data_on: data_on { + pinmux { + pins = "sdc1_data"; + }; + pinconf { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + sdc1_data_off: data_off { + pinmux { + pins = "sdc1_data"; + }; + pinconf { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + }; + + pmx_sdc2_clk { + sdc2_clk_on: clk_on { + pinmux { + pins = "sdc2_clk"; + }; + pinconf { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + }; + sdc2_clk_off: clk_off { + pinmux { + pins = "sdc2_clk"; + }; + pinconf { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + }; + }; + + pmx_sdc2_cmd { + sdc2_cmd_on: cmd_on { + pinmux { + pins = "sdc2_cmd"; + }; + pinconf { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + }; + sdc2_cmd_off: cmd_off { + pinmux { + pins = "sdc2_cmd"; + }; + pinconf { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + }; + }; + + pmx_sdc2_data { + sdc2_data_on: data_on { + pinmux { + pins = "sdc2_data"; + }; + pinconf { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + sdc2_data_off: data_off { + pinmux { + pins = "sdc2_data"; + }; + pinconf { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + }; + + ext-codec-lines { + ext_codec_lines_act: lines_on { + pinmux { + function = "gpio"; + pins = "gpio67"; + }; + pinconf { + pins = "gpio67"; + drive-strength = <8>; + bias-disable; + output-high; + }; + }; + ext_codec_lines_sus: lines_off { + pinmux { + function = "gpio"; + pins = "gpio67"; + }; + pinconf { + pins = "gpio67"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + cdc-pdm-lines { + cdc_pdm_lines_act: pdm_lines_on { + pinmux { + function = "cdc_pdm0"; + pins = "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68"; + }; + pinconf { + pins = "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68"; + drive-strength = <8>; + bias-pull-none; + }; + }; + cdc_pdm_lines_sus: pdm_lines_off { + pinmux { + function = "cdc_pdm0"; + pins = "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68"; + }; + pinconf { + pins = "gpio63", "gpio64", "gpio65", "gpio66", + "gpio67", "gpio68"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + ext-pri-tlmm-lines { + ext_pri_tlmm_lines_act: ext_pa_on { + pinmux { + function = "pri_mi2s"; + pins = "gpio113", "gpio114", "gpio115", + "gpio116"; + }; + pinconf { + pins = "gpio113", "gpio114", "gpio115", + "gpio116"; + drive-strength = <8>; + bias-pull-none; + }; + }; + + ext_pri_tlmm_lines_sus: ext_pa_off { + pinmux { + function = "pri_mi2s"; + pins = "gpio113", "gpio114", "gpio115", + "gpio116"; + }; + pinconf { + pins = "gpio113", "gpio114", "gpio115", + "gpio116"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + ext-pri-ws-line { + ext_pri_ws_act: ext_pa_on { + pinmux { + function = "pri_mi2s_ws"; + pins = "gpio110"; + }; + pinconf { + pins = "gpio110"; + drive-strength = <8>; + bias-pull-none; + }; + }; + + ext_pri_ws_sus: ext_pa_off { + pinmux { + function = "pri_mi2s_ws"; + pins = "gpio110"; + }; + pinconf { + pins = "gpio110"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + ext-mclk-tlmm-lines { + ext_mclk_tlmm_lines_act: mclk_lines_on { + pinmux { + function = "pri_mi2s"; + pins = "gpio116"; + }; + pinconf { + pins = "gpio116"; + drive-strength = <8>; + bias-pull-none; + }; + }; + ext_mclk_tlmm_lines_sus: mclk_lines_off { + pinmux { + function = "pri_mi2s"; + pins = "gpio116"; + }; + pinconf { + pins = "gpio116"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + /* secondary Mi2S */ + ext-sec-tlmm-lines { + ext_sec_tlmm_lines_act: tlmm_lines_on { + pinmux { + function = "sec_mi2s"; + pins = "gpio112", "gpio117", "gpio118", + "gpio119"; + }; + pinconf { + pins = "gpio112", "gpio117", "gpio118", + "gpio119"; + drive-strength = <8>; + bias-pull-none; + }; + }; + ext_sec_tlmm_lines_sus: tlmm_lines_off { + pinmux { + function = "sec_mi2s"; + pins = "gpio112", "gpio117", "gpio118", + "gpio119"; + }; + pinconf { + pins = "gpio112", "gpio117", "gpio118", + "gpio119"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + cdc-dmic-lines { + cdc_dmic_lines_act: dmic_lines_on { + pinmux_dmic0_clk { + function = "dmic0_clk"; + pins = "gpio0"; + }; + pinmux_dmic0_data { + function = "dmic0_data"; + pins = "gpio1"; + }; + pinconf { + pins = "gpio0", "gpio1"; + drive-strength = <8>; + }; + }; + cdc_dmic_lines_sus: dmic_lines_off { + pinconf { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + cross-conn-det { + cross_conn_det_act: lines_on { + pinmux { + function = "gpio"; + pins = "gpio120"; + }; + pinconf { + pins = "gpio120"; + drive-strength = <8>; + output-low; + bias-pull-down; + }; + }; + cross_conn_det_sus: lines_off { + pinmux { + function = "gpio"; + pins = "gpio120"; + }; + pinconf { + pins = "gpio120"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + wcnss_pin_a: wcnss-active { + pinmux { + pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; + function = "wcss_wlan"; + }; + + pinconf { + pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; + drive-strength = <6>; + bias-pull-up; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm8916.dtsi b/arch/arm/boot/dts/qcom/msm8916.dtsi new file mode 100644 index 000000000000..3cc449425a03 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8916.dtsi @@ -0,0 +1,1461 @@ +/* + * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. MSM8916"; + compatible = "qcom,msm8916"; + + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + }; + + chosen { }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tz-apps@86000000 { + reg = <0x0 0x86000000 0x0 0x300000>; + no-map; + }; + + smem_mem: smem_region@86300000 { + reg = <0x0 0x86300000 0x0 0x100000>; + no-map; + }; + + hypervisor@86400000 { + reg = <0x0 0x86400000 0x0 0x100000>; + no-map; + }; + + tz@86500000 { + reg = <0x0 0x86500000 0x0 0x180000>; + no-map; + }; + + reserved@8668000 { + reg = <0x0 0x86680000 0x0 0x80000>; + no-map; + }; + + rmtfs@86700000 { + reg = <0x0 0x86700000 0x0 0xe0000>; + no-map; + }; + + rfsa@867e00000 { + reg = <0x0 0x867e0000 0x0 0x20000>; + no-map; + }; + + mpss_mem: mpss@86800000 { + reg = <0x0 0x86800000 0x0 0x2b00000>; + no-map; + }; + + wcnss_mem: wcnss@89300000 { + reg = <0x0 0x89300000 0x0 0x600000>; + no-map; + }; + + venus_mem: venus@89900000 { + reg = <0x0 0x89900000 0x0 0x600000>; + no-map; + }; + + mba_mem: mba@8ea00000 { + no-map; + reg = <0 0x8ea00000 0 0x100000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SPC>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SPC>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SPC>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SPC>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + + idle-states { + CPU_SPC: spc { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000002>; + entry-latency-us = <130>; + exit-latency-us = <150>; + min-residency-us = <2000>; + local-timer-stop; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 4>; + + trips { + cpu_alert0: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 3>; + + trips { + cpu_alert1: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + }; + + gpu_opp_table: opp_table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + smem { + compatible = "qcom,smem"; + + memory-region = <&smem_mem>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + + hwlocks = <&tcsr_mutex 3>; + }; + + firmware { + scm: scm { + compatible = "qcom,scm"; + clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "core", "bus", "iface"; + #reset-cells = <1>; + }; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x4ab000 0x4>; + }; + + msmgpio: pinctrl@1000000 { + compatible = "qcom,msm8916-pinctrl"; + reg = <0x1000000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-msm8916"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x1800000 0x80000>; + }; + + tcsr_mutex_regs: syscon@1905000 { + compatible = "syscon"; + reg = <0x1905000 0x20000>; + }; + + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-msm8916", "syscon"; + reg = <0x1937000 0x30000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x1000>; + #hwlock-cells = <1>; + }; + + rpm_msg_ram: memory@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x60000 0x8000>; + }; + + blsp1_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78af000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 1>, <&blsp_dma 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + apcs: syscon@b011000 { + compatible = "syscon"; + reg = <0x0b011000 0x1000>; + }; + + blsp1_uart2: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78b0000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 3>, <&blsp_dma 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + blsp_dma: dma@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x23000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + blsp_spi1: spi@78b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b5000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 5>, <&blsp_dma 4>; + dma-names = "rx", "tx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_default>; + pinctrl-1 = <&spi1_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi2: spi@78b6000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b6000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 7>, <&blsp_dma 6>; + dma-names = "rx", "tx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi2_default>; + pinctrl-1 = <&spi2_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi3: spi@78b7000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b7000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 9>, <&blsp_dma 8>; + dma-names = "rx", "tx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi3_default>; + pinctrl-1 = <&spi3_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi4: spi@78b8000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b8000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 11>, <&blsp_dma 10>; + dma-names = "rx", "tx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi4_default>; + pinctrl-1 = <&spi4_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi5: spi@78b9000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b9000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 13>, <&blsp_dma 12>; + dma-names = "rx", "tx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi5_default>; + pinctrl-1 = <&spi5_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_spi6: spi@78ba000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078ba000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 15>, <&blsp_dma 14>; + dma-names = "rx", "tx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi6_default>; + pinctrl-1 = <&spi6_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c2: i2c@78b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x78b6000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_default>; + pinctrl-1 = <&i2c2_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c4: i2c@78b8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x78b8000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_default>; + pinctrl-1 = <&i2c4_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c6: i2c@78ba000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x78ba000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c6_default>; + pinctrl-1 = <&i2c6_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + lpass: lpass@07708000 { + status = "disabled"; + compatible = "qcom,lpass-cpu-apq8016"; + clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, + <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, + <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>; + + clock-names = "ahbix-clk", + "pcnoc-mport-clk", + "pcnoc-sway-clk", + "mi2s-bit-clk0", + "mi2s-bit-clk1", + "mi2s-bit-clk2", + "mi2s-bit-clk3"; + #sound-dai-cells = <1>; + + interrupts = <0 160 0>; + interrupt-names = "lpass-irq-lpaif"; + reg = <0x07708000 0x10000>; + reg-names = "lpass-lpaif"; + }; + + lpass_codec: codec{ + compatible = "qcom,msm8916-wcd-digital-codec"; + reg = <0x0771c000 0x400>; + clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, + <&gcc GCC_CODEC_DIGCODEC_CLK>; + clock-names = "ahbix-clk", "mclk"; + #sound-dai-cells = <1>; + }; + + sdhc_1: sdhci@07824000 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x07824900 0x11c>, <0x07824000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <0 123 0>, <0 138 0>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + mmc-ddr-1_8v; + bus-width = <8>; + non-removable; + status = "disabled"; + }; + + sdhc_2: sdhci@07864000 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0x07864900 0x11c>, <0x07864000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <0 125 0>, <0 221 0>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + bus-width = <4>; + status = "disabled"; + }; + + otg: usb@78d9000 { + compatible = "qcom,ci-hdrc"; + reg = <0x78d9000 0x200>, + <0x78d9200 0x200>; + interrupts = , + ; + clocks = <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names = "iface", "core"; + assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <80000000>; + resets = <&gcc GCC_USB_HS_BCR>; + reset-names = "core"; + phy_type = "ulpi"; + dr_mode = "otg"; + ahb-burst-config = <0>; + phy-names = "usb-phy"; + phys = <&usb_hs_phy>; + status = "disabled"; + #reset-cells = <1>; + + ulpi { + usb_hs_phy: phy { + compatible = "qcom,usb-hs-phy-msm8916", + "qcom,usb-hs-phy"; + #phy-cells = <0>; + clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "sleep"; + resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>; + reset-names = "phy", "por"; + qcom,init-seq = /bits/ 8 <0x0 0x44 + 0x1 0x6b 0x2 0x24 0x3 0x13>; + }; + }; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; + }; + + timer@b020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xb020000 0x1000>; + clock-frequency = <19200000>; + + frame@b021000 { + frame-number = <0>; + interrupts = , + ; + reg = <0xb021000 0x1000>, + <0xb022000 0x1000>; + }; + + frame@b023000 { + frame-number = <1>; + interrupts = ; + reg = <0xb023000 0x1000>; + status = "disabled"; + }; + + frame@b024000 { + frame-number = <2>; + interrupts = ; + reg = <0xb024000 0x1000>; + status = "disabled"; + }; + + frame@b025000 { + frame-number = <3>; + interrupts = ; + reg = <0xb025000 0x1000>; + status = "disabled"; + }; + + frame@b026000 { + frame-number = <4>; + interrupts = ; + reg = <0xb026000 0x1000>; + status = "disabled"; + }; + + frame@b027000 { + frame-number = <5>; + interrupts = ; + reg = <0xb027000 0x1000>; + status = "disabled"; + }; + + frame@b028000 { + frame-number = <6>; + interrupts = ; + reg = <0xb028000 0x1000>; + status = "disabled"; + }; + }; + + spmi_bus: spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x200f000 0x001000>, + <0x2400000 0x400000>, + <0x2c00000 0x400000>, + <0x3800000 0x200000>, + <0x200a000 0x002100>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + rng@22000 { + compatible = "qcom,prng"; + reg = <0x00022000 0x200>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + qfprom: qfprom@5c000 { + compatible = "qcom,qfprom"; + reg = <0x5c000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + tsens_caldata: caldata@d0 { + reg = <0xd0 0x8>; + }; + tsens_calsel: calsel@ec { + reg = <0xec 0x4>; + }; + }; + + tsens: thermal-sensor@4a8000 { + compatible = "qcom,msm8916-tsens"; + reg = <0x4a8000 0x2000>; + nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; + nvmem-cell-names = "calib", "calib_sel"; + #thermal-sensor-cells = <1>; + }; + + apps_iommu: iommu@1ef0000 { + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + ranges = <0 0x1e20000 0x40000>; + reg = <0x1ef0000 0x3000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface", "bus"; + qcom,iommu-secure-id = <17>; + + // mdp_0: + iommu-ctx@4000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x4000 0x1000>; + interrupts = ; + }; + + // venus_ns: + iommu-ctx@5000 { + compatible = "qcom,msm-iommu-v1-sec"; + reg = <0x5000 0x1000>; + interrupts = ; + }; + }; + + gpu_iommu: iommu@1f08000 { + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + ranges = <0 0x1f08000 0x10000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX_TCU_CLK>; + clock-names = "iface", "bus"; + qcom,iommu-secure-id = <18>; + + // gfx3d_user: + iommu-ctx@1000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + // gfx3d_priv: + iommu-ctx@2000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + }; + + gpu@1c00000 { + compatible = "qcom,adreno-306.0", "qcom,adreno"; + reg = <0x01c00000 0x20000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = ; + interrupt-names = "kgsl_3d0_irq"; + clock-names = + "core", + "iface", + "mem", + "mem_iface", + "alt_mem_iface", + "gfx3d"; + clocks = + <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_OXILI_GMEM_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc GFX3D_CLK_SRC>; + power-domains = <&gcc OXILI_GDSC>; + operating-points-v2 = <&gpu_opp_table>; + iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; + }; + + mdss: mdss@1a00000 { + compatible = "qcom,mdss"; + reg = <0x1a00000 0x1000>, + <0x1ac8000 0x3000>; + reg-names = "mdss_phys", "vbif_phys"; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface_clk", + "bus_clk", + "vsync_clk"; + + interrupts = <0 72 0>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mdp: mdp@1a01000 { + compatible = "qcom,mdp5"; + reg = <0x1a01000 0x90000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0 0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>; + clock-names = "iface_clk", + "bus_clk", + "core_clk", + "vsync_clk"; + + iommus = <&apps_iommu 4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdp5_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + + dsi0: dsi@1a98000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0x1a98000 0x25c>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4 0>; + + assigned-clocks = <&gcc BYTE0_CLK_SRC>, + <&gcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi_phy0 0>, + <&dsi_phy0 1>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names = "mdp_core_clk", + "iface_clk", + "bus_clk", + "byte_clk", + "pixel_clk", + "core_clk"; + phys = <&dsi_phy0>; + phy-names = "dsi-phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&mdp5_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi_phy0: dsi-phy@1a98300 { + compatible = "qcom,dsi-phy-28nm-lp"; + reg = <0x1a98300 0xd4>, + <0x1a98500 0x280>, + <0x1a98780 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + }; + }; + + + hexagon@4080000 { + compatible = "qcom,q6v5-pil"; + reg = <0x04080000 0x100>, + <0x04020000 0x040>; + + reg-names = "qdsp6", "rmb"; + + interrupts-extended = <&intc 0 24 1>, + <&hexagon_smp2p_in 0 0>, + <&hexagon_smp2p_in 1 0>, + <&hexagon_smp2p_in 2 0>, + <&hexagon_smp2p_in 3 0>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&xo_board>; + clock-names = "iface", "bus", "mem", "xo"; + + qcom,smem-states = <&hexagon_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + resets = <&scm 0>; + reset-names = "mss_restart"; + + cx-supply = <&pm8916_s1>; + mx-supply = <&pm8916_l3>; + pll-supply = <&pm8916_l7>; + + qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; + + status = "disabled"; + + mba { + memory-region = <&mba_mem>; + }; + + mpss { + memory-region = <&mpss_mem>; + }; + + smd-edge { + interrupts = <0 25 IRQ_TYPE_EDGE_RISING>; + + qcom,smd-edge = <0>; + qcom,ipc = <&apcs 8 12>; + qcom,remote-pid = <1>; + + label = "hexagon"; + }; + }; + + pronto: wcnss@a21b000 { + compatible = "qcom,pronto-v2-pil", "qcom,pronto"; + reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; + reg-names = "ccu", "dxe", "pmu"; + + memory-region = <&wcnss_mem>; + + interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + vddmx-supply = <&pm8916_l3>; + vddpx-supply = <&pm8916_l7>; + + qcom,state = <&wcnss_smp2p_out 0>; + qcom,state-names = "stop"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcnss_pin_a>; + + status = "disabled"; + + iris { + compatible = "qcom,wcn3620"; + + clocks = <&rpmcc RPM_SMD_RF_CLK2>; + clock-names = "xo"; + + vddxo-supply = <&pm8916_l7>; + vddrfa-supply = <&pm8916_s3>; + vddpa-supply = <&pm8916_l9>; + vdddig-supply = <&pm8916_l5>; + }; + + smd-edge { + interrupts = <0 142 1>; + + qcom,ipc = <&apcs 8 17>; + qcom,smd-edge = <6>; + qcom,remote-pid = <4>; + + label = "pronto"; + + wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; + + qcom,mmio = <&pronto>; + + bt { + compatible = "qcom,wcnss-bt"; + }; + + wifi { + compatible = "qcom,wcnss-wlan"; + + interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>, + <0 146 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + + qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", "tx-rings-empty"; + }; + }; + }; + }; + + tpiu@820000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x820000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + port { + tpiu_in: endpoint { + slave-mode; + remote-endpoint = <&replicator_out1>; + }; + }; + }; + + funnel@821000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x821000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * Not described input ports: + * 0 - connected to Resource and Power Manger CPU ETM + * 1 - not-connected + * 2 - connected to Modem CPU ETM + * 3 - not-connected + * 5 - not-connected + * 6 - connected trought funnel to Wireless CPU ETM + * 7 - connected to STM component + */ + + port@4 { + reg = <4>; + funnel0_in4: endpoint { + slave-mode; + remote-endpoint = <&funnel1_out>; + }; + }; + port@8 { + reg = <0>; + funnel0_out: endpoint { + remote-endpoint = <&etf_in>; + }; + }; + }; + }; + + replicator@824000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x824000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out0: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + port@1 { + reg = <1>; + replicator_out1: endpoint { + remote-endpoint = <&tpiu_in>; + }; + }; + port@2 { + reg = <0>; + replicator_in: endpoint { + slave-mode; + remote-endpoint = <&etf_out>; + }; + }; + }; + }; + + etf@825000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x825000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + etf_in: endpoint { + slave-mode; + remote-endpoint = <&funnel0_out>; + }; + }; + port@1 { + reg = <0>; + etf_out: endpoint { + remote-endpoint = <&replicator_in>; + }; + }; + }; + }; + + etr@826000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x826000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + port { + etr_in: endpoint { + slave-mode; + remote-endpoint = <&replicator_out0>; + }; + }; + }; + + funnel@841000 { /* APSS funnel only 4 inputs are used */ + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x841000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel1_in0: endpoint { + slave-mode; + remote-endpoint = <&etm0_out>; + }; + }; + port@1 { + reg = <1>; + funnel1_in1: endpoint { + slave-mode; + remote-endpoint = <&etm1_out>; + }; + }; + port@2 { + reg = <2>; + funnel1_in2: endpoint { + slave-mode; + remote-endpoint = <&etm2_out>; + }; + }; + port@3 { + reg = <3>; + funnel1_in3: endpoint { + slave-mode; + remote-endpoint = <&etm3_out>; + }; + }; + port@4 { + reg = <0>; + funnel1_out: endpoint { + remote-endpoint = <&funnel0_in4>; + }; + }; + }; + }; + + debug@850000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0x850000 0x1000>; + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + cpu = <&CPU0>; + }; + + debug@852000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0x852000 0x1000>; + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + cpu = <&CPU1>; + }; + + debug@854000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0x854000 0x1000>; + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + cpu = <&CPU2>; + }; + + debug@856000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0x856000 0x1000>; + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + cpu = <&CPU3>; + }; + + etm@85c000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x85c000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU0>; + + port { + etm0_out: endpoint { + remote-endpoint = <&funnel1_in0>; + }; + }; + }; + + etm@85d000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x85d000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU1>; + + port { + etm1_out: endpoint { + remote-endpoint = <&funnel1_in1>; + }; + }; + }; + + etm@85e000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x85e000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU2>; + + port { + etm2_out: endpoint { + remote-endpoint = <&funnel1_in2>; + }; + }; + }; + + etm@85f000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x85f000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU3>; + + port { + etm3_out: endpoint { + remote-endpoint = <&funnel1_in3>; + }; + }; + }; + + venus: video-codec@1d00000 { + compatible = "qcom,msm8916-venus"; + reg = <0x01d00000 0xff000>; + interrupts = ; + power-domains = <&gcc VENUS_GDSC>; + clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, + <&gcc GCC_VENUS0_AHB_CLK>, + <&gcc GCC_VENUS0_AXI_CLK>; + clock-names = "core", "iface", "bus"; + iommus = <&apps_iommu 5>; + memory-region = <&venus_mem>; + status = "okay"; + + video-decoder { + compatible = "venus-decoder"; + }; + + video-encoder { + compatible = "venus-encoder"; + }; + }; + }; + + smd { + compatible = "qcom,smd"; + + rpm { + interrupts = ; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests { + compatible = "qcom,rpm-msm8916"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: qcom,rpmcc { + compatible = "qcom,rpmcc-msm8916"; + #clock-cells = <1>; + }; + + smd_rpm_regulators: pm8916-regulators { + compatible = "qcom,rpm-pm8916-regulators"; + + pm8916_s1: s1 {}; + pm8916_s3: s3 {}; + pm8916_s4: s4 {}; + + pm8916_l1: l1 {}; + pm8916_l2: l2 {}; + pm8916_l3: l3 {}; + pm8916_l4: l4 {}; + pm8916_l5: l5 {}; + pm8916_l6: l6 {}; + pm8916_l7: l7 {}; + pm8916_l8: l8 {}; + pm8916_l9: l9 {}; + pm8916_l10: l10 {}; + pm8916_l11: l11 {}; + pm8916_l12: l12 {}; + pm8916_l13: l13 {}; + pm8916_l14: l14 {}; + pm8916_l15: l15 {}; + pm8916_l16: l16 {}; + pm8916_l17: l17 {}; + pm8916_l18: l18 {}; + }; + }; + }; + }; + + hexagon-smp2p { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts = <0 27 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + hexagon_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + hexagon_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + wcnss-smp2p { + compatible = "qcom,smp2p"; + qcom,smem = <451>, <431>; + + interrupts = <0 143 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 18>; + + qcom,local-pid = <0>; + qcom,remote-pid = <4>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smsm { + compatible = "qcom,smsm"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,ipc-1 = <&apcs 8 13>; + qcom,ipc-3 = <&apcs 8 19>; + + apps_smsm: apps@0 { + reg = <0>; + + #qcom,smem-state-cells = <1>; + }; + + hexagon_smsm: hexagon@1 { + reg = <1>; + interrupts = <0 26 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + wcnss_smsm: wcnss@6 { + reg = <6>; + interrupts = <0 144 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +#include "msm8916-pins.dtsi" diff --git a/arch/arm/boot/dts/qcom/msm8992-bullhead-rev-101.dts b/arch/arm/boot/dts/qcom/msm8992-bullhead-rev-101.dts new file mode 100644 index 000000000000..454213391671 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8992-bullhead-rev-101.dts @@ -0,0 +1,41 @@ +/* Copyright (c) 2015, LGE Inc. All rights reserved. + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "msm8992.dtsi" + +/ { + model = "LG Nexus 5X"; + compatible = "lg,bullhead", "qcom,msm8992"; + /* required for bootloader to select correct board */ + qcom,board-id = <0xb64 0>; + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + soc { + serial@f991e000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm8992-pins.dtsi b/arch/arm/boot/dts/qcom/msm8992-pins.dtsi new file mode 100644 index 000000000000..d2a26f0f8d73 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8992-pins.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&msmgpio { + blsp1_uart2_default: blsp1_uart2_default { + pinmux { + function = "blsp_uart2"; + pins = "gpio4", "gpio5"; + }; + pinconf { + pins = "gpio4", "gpio5"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp1_uart2_sleep: blsp1_uart2_sleep { + pinmux { + function = "gpio"; + pins = "gpio4", "gpio5"; + }; + pinconf { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-pull-down; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm8992.dtsi b/arch/arm/boot/dts/qcom/msm8992.dtsi new file mode 100644 index 000000000000..171578747ed0 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8992.dtsi @@ -0,0 +1,237 @@ +/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. MSM 8992"; + compatible = "qcom,msm8992"; + // msm-id needed by bootloader for selecting correct blob + qcom,msm-id = <251 0>, <252 0>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + }; + }; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + xo_board: xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + vreg_vph_pwr: vreg-vph-pwr { + compatible = "regulator-fixed"; + status = "okay"; + regulator-name = "vph-pwr"; + + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + regulator-always-on; + }; + + sfpb_mutex: hwmutex { + compatible = "qcom,sfpb-mutex"; + syscon = <&sfpb_mutex_regs 0x0 0x100>; + #hwlock-cells = <1>; + }; + + smem { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + hwlocks = <&sfpb_mutex 3>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf9000000 0x1000>, + <0xf9002000 0x1000>; + }; + + apcs: syscon@f900d000 { + compatible = "syscon"; + reg = <0xf900d000 0x2000>; + }; + + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = , + ; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = ; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = ; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = ; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = ; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = ; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = ; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + + restart@fc4ab000 { + compatible = "qcom,pshold"; + reg = <0xfc4ab000 0x4>; + }; + + msmgpio: pinctrl@fd510000 { + compatible = "qcom,msm8994-pinctrl"; + reg = <0xfd510000 0x4000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + blsp1_uart2: serial@f991e000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf991e000 0x1000>; + interrupts = ; + status = "disabled"; + clock-names = "core", "iface"; + clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, + <&clock_gcc GCC_BLSP1_AHB_CLK>; + }; + + clock_gcc: clock-controller@fc400000 { + compatible = "qcom,gcc-msm8994"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0xfc400000 0x2000>; + }; + + rpm_msg_ram: memory@fc428000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0xfc428000 0x4000>; + }; + + sfpb_mutex_regs: syscon@fd484000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "syscon"; + reg = <0xfd484000 0x400>; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0 0 0>; // bootloader will update + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + smem_region: smem@6a00000 { + reg = <0x0 0x6a00000 0x0 0x200000>; + no-map; + }; + }; + +}; + + +#include "msm8992-pins.dtsi" diff --git a/arch/arm/boot/dts/qcom/msm8994-angler-rev-101.dts b/arch/arm/boot/dts/qcom/msm8994-angler-rev-101.dts new file mode 100644 index 000000000000..dfa08f513dc4 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8994-angler-rev-101.dts @@ -0,0 +1,40 @@ +/* Copyright (c) 2015, Huawei Inc. All rights reserved. + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "msm8994.dtsi" + +/ { + model = "Huawei Nexus 6P"; + compatible = "huawei,angler", "qcom,msm8994"; + /* required for bootloader to select correct board */ + qcom,board-id = <8026 0>; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + soc { + serial@f991e000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm8994-pins.dtsi b/arch/arm/boot/dts/qcom/msm8994-pins.dtsi new file mode 100644 index 000000000000..0e4eea0df25d --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8994-pins.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&msmgpio { + blsp1_uart2_default: blsp1_uart2_default { + pinmux { + function = "blsp_uart2"; + pins = "gpio4", "gpio5"; + }; + pinconf { + pins = "gpio4", "gpio5"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp1_uart2_sleep: blsp1_uart2_sleep { + pinmux { + function = "gpio"; + pins = "gpio4", "gpio5"; + }; + pinconf { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-pull-down; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm8994.dtsi b/arch/arm/boot/dts/qcom/msm8994.dtsi new file mode 100644 index 000000000000..f33c41d01c86 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8994.dtsi @@ -0,0 +1,216 @@ +/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. MSM 8994"; + compatible = "qcom,msm8994"; + // msm-id and pmic-id are required by bootloader for + // proper selection of dt blob + qcom,msm-id = <207 0x20000>; + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + }; + }; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 2 0xff08>, + <1 3 0xff08>, + <1 4 0xff08>, + <1 1 0xff08>; + }; + + soc: soc { + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf9000000 0x1000>, + <0xf9002000 0x1000>; + }; + + timer@f9020000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + + frame@f9021000 { + frame-number = <0>; + interrupts = , + ; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = ; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = ; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = ; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = ; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = ; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = ; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + + restart@fc4ab000 { + compatible = "qcom,pshold"; + reg = <0xfc4ab000 0x4>; + }; + + msmgpio: pinctrl@fd510000 { + compatible = "qcom,msm8994-pinctrl"; + reg = <0xfd510000 0x4000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + blsp1_uart2: serial@f991e000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf991e000 0x1000>; + interrupts = ; + status = "disabled"; + clock-names = "core", "iface"; + clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, + <&clock_gcc GCC_BLSP1_AHB_CLK>; + }; + + tcsr_mutex_regs: syscon@fd484000 { + compatible = "syscon"; + reg = <0xfd484000 0x2000>; + }; + + clock_gcc: clock-controller@fc400000 { + compatible = "qcom,gcc-msm8994"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0xfc400000 0x2000>; + }; + }; + + memory { + device_type = "memory"; + // We expect the bootloader to fill in the reg + reg = <0 0 0 0>; + }; + + xo_board: xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + smem_mem: smem_region@6a00000 { + reg = <0x0 0x6a00000 0x0 0x200000>; + no-map; + }; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x80>; + #hwlock-cells = <1>; + }; + + qcom,smem@6a00000 { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; +}; + + +#include "msm8994-pins.dtsi" diff --git a/arch/arm/boot/dts/qcom/msm8996-mtp.dts b/arch/arm/boot/dts/qcom/msm8996-mtp.dts new file mode 100644 index 000000000000..619af44a595d --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8996-mtp.dts @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "msm8996-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM 8996 MTP"; + compatible = "qcom,msm8996-mtp"; +}; diff --git a/arch/arm/boot/dts/qcom/msm8996-mtp.dtsi b/arch/arm/boot/dts/qcom/msm8996-mtp.dtsi new file mode 100644 index 000000000000..9bab5c011c07 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8996-mtp.dtsi @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msm8996.dtsi" + +/ { + aliases { + serial0 = &blsp2_uart1; + }; + + chosen { + stdout-path = "serial0"; + }; + + soc { + serial@75b0000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm/boot/dts/qcom/msm8996-pins.dtsi new file mode 100644 index 000000000000..659940434842 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8996-pins.dtsi @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&msmgpio { + + blsp1_spi0_default: blsp1_spi0_default { + pinmux { + function = "blsp_spi1"; + pins = "gpio0", "gpio1", "gpio3"; + }; + pinmux_cs { + function = "gpio"; + pins = "gpio2"; + }; + pinconf { + pins = "gpio0", "gpio1", "gpio3"; + drive-strength = <12>; + bias-disable; + }; + pinconf_cs { + pins = "gpio2"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp1_spi0_sleep: blsp1_spi0_sleep { + pinmux { + function = "gpio"; + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + }; + pinconf { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_i2c2_default: blsp1_i2c2_default { + pinmux { + function = "blsp_i2c3"; + pins = "gpio47", "gpio48"; + }; + pinconf { + pins = "gpio47", "gpio48"; + drive-strength = <16>; + bias-disable = <0>; + }; + }; + + blsp1_i2c2_sleep: blsp1_i2c2_sleep { + pinmux { + function = "gpio"; + pins = "gpio47", "gpio48"; + }; + pinconf { + pins = "gpio47", "gpio48"; + drive-strength = <2>; + bias-disable = <0>; + }; + }; + + blsp2_i2c0_default: blsp2_i2c0 { + pinmux { + function = "blsp_i2c7"; + pins = "gpio55", "gpio56"; + }; + pinconf { + pins = "gpio55", "gpio56"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp2_i2c0_sleep: blsp2_i2c0_sleep { + pinmux { + function = "gpio"; + pins = "gpio55", "gpio56"; + }; + pinconf { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart1_2pins_default: blsp2_uart1_2pins { + pinmux { + function = "blsp_uart8"; + pins = "gpio4", "gpio5"; + }; + pinconf { + pins = "gpio4", "gpio5"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp2_uart1_2pins_sleep: blsp2_uart1_2pins_sleep { + pinmux { + function = "gpio"; + pins = "gpio4", "gpio5"; + }; + pinconf { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart1_4pins_default: blsp2_uart1_4pins { + pinmux { + function = "blsp_uart8"; + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + }; + + pinconf { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp2_uart1_4pins_sleep: blsp2_uart1_4pins_sleep { + pinmux { + function = "gpio"; + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + }; + + pinconf { + pins = "gpio4", "gpiio5", "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_i2c1_default: blsp2_i2c1 { + pinmux { + function = "blsp_i2c8"; + pins = "gpio6", "gpio7"; + }; + pinconf { + pins = "gpio6", "gpio7"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp2_i2c1_sleep: blsp2_i2c1_sleep { + pinmux { + function = "gpio"; + pins = "gpio6", "gpio7"; + }; + pinconf { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart2_2pins_default: blsp2_uart2_2pins { + pinmux { + function = "blsp_uart9"; + pins = "gpio49", "gpio50"; + }; + pinconf { + pins = "gpio49", "gpio50"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp2_uart2_2pins_sleep: blsp2_uart2_2pins_sleep { + pinmux { + function = "gpio"; + pins = "gpio49", "gpio50"; + }; + pinconf { + pins = "gpio49", "gpio50"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart2_4pins_default: blsp2_uart2_4pins { + pinmux { + function = "blsp_uart9"; + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + }; + + pinconf { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp2_uart2_4pins_sleep: blsp2_uart2_4pins_sleep { + pinmux { + function = "gpio"; + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + }; + + pinconf { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_spi5_default: blsp2_spi5_default { + pinmux { + function = "blsp_spi12"; + pins = "gpio85", "gpio86", "gpio88"; + }; + pinmux_cs { + function = "gpio"; + pins = "gpio87"; + }; + pinconf { + pins = "gpio85", "gpio86", "gpio88"; + drive-strength = <12>; + bias-disable; + }; + pinconf_cs { + pins = "gpio87"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp2_spi5_sleep: blsp2_spi5_sleep { + pinmux { + function = "gpio"; + pins = "gpio85", "gpio86", "gpio87", "gpio88"; + }; + pinconf { + pins = "gpio85", "gpio86", "gpio87", "gpio88"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm8996.dtsi b/arch/arm/boot/dts/qcom/msm8996.dtsi new file mode 100644 index 000000000000..6f372ec055dd --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8996.dtsi @@ -0,0 +1,925 @@ +/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. MSM8996"; + + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mba_region: mba@91500000 { + reg = <0x0 0x91500000 0x0 0x200000>; + no-map; + }; + + slpi_region: slpi@90b00000 { + reg = <0x0 0x90b00000 0x0 0xa00000>; + no-map; + }; + + venus_region: venus@90400000 { + reg = <0x0 0x90400000 0x0 0x700000>; + no-map; + }; + + adsp_region: adsp@8ea00000 { + reg = <0x0 0x8ea00000 0x0 0x1a00000>; + no-map; + }; + + mpss_region: mpss@88800000 { + reg = <0x0 0x88800000 0x0 0x6200000>; + no-map; + }; + + smem_mem: smem-mem@86000000 { + reg = <0x0 0x86000000 0x0 0x200000>; + no-map; + }; + + memory@85800000 { + reg = <0x0 0x85800000 0x0 0x800000>; + no-map; + }; + + memory@86200000 { + reg = <0x0 0x86200000 0x0 0x2600000>; + no-map; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU3: cpu@101 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x101>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU2>; + }; + + core1 { + cpu = <&CPU3>; + }; + }; + }; + }; + + thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 3>; + + trips { + cpu_alert0: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 5>; + + trips { + cpu_alert1: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit1: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 8>; + + trips { + cpu_alert2: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit2: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 10>; + + trips { + cpu_alert3: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit3: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32764>; + clock-output-names = "sleep_clk"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + firmware { + scm { + compatible = "qcom,scm-msm8996"; + }; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + + interrupts = ; + + qcom,rpm-msg-ram = <&rpm_msg_ram>; + + mboxes = <&apcs_glb 0>; + + rpm_requests { + compatible = "qcom,rpm-msm8996"; + qcom,glink-channels = "rpm_requests"; + + pm8994-regulators { + compatible = "qcom,rpm-pm8994-regulators"; + + pm8994_s1: s1 {}; + pm8994_s2: s2 {}; + pm8994_s3: s3 {}; + pm8994_s4: s4 {}; + pm8994_s5: s5 {}; + pm8994_s6: s6 {}; + pm8994_s7: s7 {}; + pm8994_s8: s8 {}; + pm8994_s9: s9 {}; + pm8994_s10: s10 {}; + pm8994_s11: s11 {}; + pm8994_s12: s12 {}; + + pm8994_l1: l1 {}; + pm8994_l2: l2 {}; + pm8994_l3: l3 {}; + pm8994_l4: l4 {}; + pm8994_l5: l5 {}; + pm8994_l6: l6 {}; + pm8994_l7: l7 {}; + pm8994_l8: l8 {}; + pm8994_l9: l9 {}; + pm8994_l10: l10 {}; + pm8994_l11: l11 {}; + pm8994_l12: l12 {}; + pm8994_l13: l13 {}; + pm8994_l14: l14 {}; + pm8994_l15: l15 {}; + pm8994_l16: l16 {}; + pm8994_l17: l17 {}; + pm8994_l18: l18 {}; + pm8994_l19: l19 {}; + pm8994_l20: l20 {}; + pm8994_l21: l21 {}; + pm8994_l22: l22 {}; + pm8994_l23: l23 {}; + pm8994_l24: l24 {}; + pm8994_l25: l25 {}; + pm8994_l26: l26 {}; + pm8994_l27: l27 {}; + pm8994_l28: l28 {}; + pm8994_l29: l29 {}; + pm8994_l30: l30 {}; + pm8994_l31: l31 {}; + pm8994_l32: l32 {}; + }; + + }; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + rpm_msg_ram: memory@68000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x68000 0x6000>; + }; + + tcsr_mutex_regs: syscon@740000 { + compatible = "syscon"; + reg = <0x740000 0x20000>; + }; + + intc: interrupt-controller@9bc0000 { + compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + reg = <0x09bc0000 0x10000>, + <0x09c00000 0x100000>; + interrupts = ; + }; + + apcs: syscon@9820000 { + compatible = "syscon"; + reg = <0x9820000 0x1000>; + }; + + apcs_glb: mailbox@9820000 { + compatible = "qcom,msm8996-apcs-hmss-global"; + reg = <0x9820000 0x1000>; + + #mbox-cells = <1>; + }; + + gcc: clock-controller@300000 { + compatible = "qcom,gcc-msm8996"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x300000 0x90000>; + }; + + kryocc: clock-controller@6400000 { + compatible = "qcom,apcc-msm8996"; + reg = <0x6400000 0x90000>; + #clock-cells = <1>; + }; + + blsp1_spi0: spi@07575000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x07575000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_spi0_default>; + pinctrl-1 = <&blsp1_spi0_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_i2c0: i2c@075b5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x075b5000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c0_default>; + pinctrl-1 = <&blsp2_i2c0_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + tsens0: thermal-sensor@4a8000 { + compatible = "qcom,msm8996-tsens"; + reg = <0x4a8000 0x2000>; + #thermal-sensor-cells = <1>; + }; + + blsp2_uart1: serial@75b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x75b0000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp2_i2c1: i2c@075b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x075b6000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c1_default>; + pinctrl-1 = <&blsp2_i2c1_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_uart2: serial@75b1000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x075b1000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + blsp1_i2c2: i2c@07577000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x07577000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_i2c2_default>; + pinctrl-1 = <&blsp1_i2c2_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp2_spi5: spi@075ba000{ + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x075ba000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_spi5_default>; + pinctrl-1 = <&blsp2_spi5_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sdhc2: sdhci@74a4900 { + status = "disabled"; + compatible = "qcom,sdhci-msm-v4"; + reg = <0x74a4900 0x314>, <0x74a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <0 125 0>, <0 221 0>; + interrupt-names = "hc_irq", "pwr_irq"; + + clock-names = "iface", "core", "xo"; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; + bus-width = <4>; + }; + + msmgpio: pinctrl@1010000 { + compatible = "qcom,msm8996-pinctrl"; + reg = <0x01010000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + timer@09840000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x09840000 0x1000>; + clock-frequency = <19200000>; + + frame@9850000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x09850000 0x1000>, + <0x09860000 0x1000>; + }; + + frame@9870000 { + frame-number = <1>; + interrupts = ; + reg = <0x09870000 0x1000>; + status = "disabled"; + }; + + frame@9880000 { + frame-number = <2>; + interrupts = ; + reg = <0x09880000 0x1000>; + status = "disabled"; + }; + + frame@9890000 { + frame-number = <3>; + interrupts = ; + reg = <0x09890000 0x1000>; + status = "disabled"; + }; + + frame@98a0000 { + frame-number = <4>; + interrupts = ; + reg = <0x098a0000 0x1000>; + status = "disabled"; + }; + + frame@98b0000 { + frame-number = <5>; + interrupts = ; + reg = <0x098b0000 0x1000>; + status = "disabled"; + }; + + frame@98c0000 { + frame-number = <6>; + interrupts = ; + reg = <0x098c0000 0x1000>; + status = "disabled"; + }; + }; + + spmi_bus: qcom,spmi@400f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x400f000 0x1000>, + <0x4400000 0x800000>, + <0x4c00000 0x800000>, + <0x5800000 0x200000>, + <0x400a000 0x002100>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + mmcc: clock-controller@8c0000 { + compatible = "qcom,mmcc-msm8996"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x8c0000 0x40000>; + assigned-clocks = <&mmcc MMPLL9_PLL>, + <&mmcc MMPLL1_PLL>, + <&mmcc MMPLL3_PLL>, + <&mmcc MMPLL4_PLL>, + <&mmcc MMPLL5_PLL>; + assigned-clock-rates = <624000000>, + <810000000>, + <980000000>, + <960000000>, + <825000000>; + }; + + qfprom@74000 { + compatible = "qcom,qfprom"; + reg = <0x74000 0x8ff>; + #address-cells = <1>; + #size-cells = <1>; + + qusb2p_hstx_trim: hstx_trim@24e { + reg = <0x24e 0x2>; + bits = <5 4>; + }; + + qusb2s_hstx_trim: hstx_trim@24f { + reg = <0x24f 0x1>; + bits = <1 4>; + }; + }; + + phy@34000 { + compatible = "qcom,msm8996-qmp-pcie-phy"; + reg = <0x34000 0x488>; + #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_CLK>; + clock-names = "aux", "cfg_ahb", "ref"; + + vdda-phy-supply = <&pm8994_l28>; + vdda-pll-supply = <&pm8994_l12>; + + resets = <&gcc GCC_PCIE_PHY_BCR>, + <&gcc GCC_PCIE_PHY_COM_BCR>, + <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; + reset-names = "phy", "common", "cfg"; + status = "disabled"; + + pciephy_0: lane@35000 { + reg = <0x035000 0x130>, + <0x035200 0x200>, + <0x035400 0x1dc>; + #phy-cells = <0>; + + clock-output-names = "pcie_0_pipe_clk_src"; + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "pipe0"; + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "lane0"; + }; + + pciephy_1: lane@36000 { + reg = <0x036000 0x130>, + <0x036200 0x200>, + <0x036400 0x1dc>; + #phy-cells = <0>; + + clock-output-names = "pcie_1_pipe_clk_src"; + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "pipe1"; + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "lane1"; + }; + + pciephy_2: lane@37000 { + reg = <0x037000 0x130>, + <0x037200 0x200>, + <0x037400 0x1dc>; + #phy-cells = <0>; + + clock-output-names = "pcie_2_pipe_clk_src"; + clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; + clock-names = "pipe2"; + resets = <&gcc GCC_PCIE_2_PHY_BCR>; + reset-names = "lane2"; + }; + }; + + phy@7410000 { + compatible = "qcom,msm8996-qmp-usb3-phy"; + reg = <0x7410000 0x1c4>; + #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_CLKREF_CLK>; + clock-names = "aux", "cfg_ahb", "ref"; + + vdda-phy-supply = <&pm8994_l28>; + vdda-pll-supply = <&pm8994_l12>; + + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "phy", "common"; + status = "disabled"; + + ssusb_phy_0: lane@7410200 { + reg = <0x7410200 0x200>, + <0x7410400 0x130>, + <0x7410600 0x1a8>; + #phy-cells = <0>; + + clock-output-names = "usb3_phy_pipe_clk_src"; + clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "pipe0"; + }; + }; + + hsusb_phy1: phy@7411000 { + compatible = "qcom,msm8996-qusb2-phy"; + reg = <0x7411000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_RX1_USB2_CLKREF_CLK>; + clock-names = "cfg_ahb", "ref"; + + vdda-pll-supply = <&pm8994_l12>; + vdda-phy-dpdm-supply = <&pm8994_l24>; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + nvmem-cells = <&qusb2p_hstx_trim>; + status = "disabled"; + }; + + hsusb_phy2: phy@7412000 { + compatible = "qcom,msm8996-qusb2-phy"; + reg = <0x7412000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_RX2_USB2_CLKREF_CLK>; + clock-names = "cfg_ahb", "ref"; + + vdda-pll-supply = <&pm8994_l12>; + vdda-phy-dpdm-supply = <&pm8994_l24>; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + nvmem-cells = <&qusb2s_hstx_trim>; + status = "disabled"; + }; + + usb2: usb@7600000 { + compatible = "qcom,dwc3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; + + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates = <19200000>, <60000000>; + + power-domains = <&gcc USB30_GDSC>; + status = "disabled"; + + dwc3@7600000 { + compatible = "snps,dwc3"; + reg = <0x7600000 0xcc00>; + interrupts = <0 138 0>; + phys = <&hsusb_phy2>; + phy-names = "usb2-phy"; + }; + }; + + usb3: usb@6a00000 { + compatible = "qcom,dwc3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_AGGRE2_USB3_AXI_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <120000000>; + + power-domains = <&gcc USB30_GDSC>; + status = "disabled"; + + dwc3@6a00000 { + compatible = "snps,dwc3"; + reg = <0x6a00000 0xcc00>; + interrupts = <0 131 0>; + phys = <&hsusb_phy1>, <&ssusb_phy_0>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + }; + + adsp-pil { + compatible = "qcom,msm8996-adsp-pil"; + + interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&xo_board>; + clock-names = "xo"; + + memory-region = <&adsp_region>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + smd-edge { + interrupts = ; + + label = "lpass"; + qcom,ipc = <&apcs 16 8>; + qcom,smd-edge = <1>; + qcom,remote-pid = <2>; + }; + }; + + adsp-smp2p { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + + interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 16 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + modem-smp2p { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts = ; + + qcom,ipc = <&apcs 16 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-slpi { + compatible = "qcom,smp2p"; + qcom,smem = <481>, <430>; + + interrupts = ; + + qcom,ipc = <&apcs 16 26>; + + qcom,local-pid = <0>; + qcom,remote-pid = <3>; + + slpi_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + slpi_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + }; + +}; +#include "msm8996-pins.dtsi" diff --git a/arch/arm/boot/dts/qcom/pm6125-rpm-regulator.dtsi b/arch/arm/boot/dts/qcom/pm6125-rpm-regulator.dtsi new file mode 100644 index 000000000000..849b7aedbdcd --- /dev/null +++ b/arch/arm/boot/dts/qcom/pm6125-rpm-regulator.dtsi @@ -0,0 +1,505 @@ +/* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&rpm_bus { + /* VDD_APC supply */ + rpm-regulator-smpa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwmx"; + qcom,resource-id = <0>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + /* VDD_CX */ + rpm-regulator-smpa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwcx"; + qcom,resource-id = <0>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + /* VDD_MX */ + rpm-regulator-smpa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwmx"; + qcom,resource-id = <0>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <6>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <8>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + /* VDD_WCSS_CX */ + rpm-regulator-ldoa8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa9 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa11 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <11>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l11 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l11"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l12 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l12"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa13 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <13>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l13 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l13"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa14 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <14>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l14 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l14"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa15 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <15>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l15 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l15"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa16 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <16>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l16 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l16"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa17 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <17>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l17 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l17"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa18 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <18>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l18 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l18"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa19 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <19>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l19 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l19"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa20 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <20>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l20 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l20"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa21 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <21>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l21 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l21"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa22 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <22>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l22 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l22"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa23 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <23>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l23 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l23"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa24 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <24>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l24 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_l24"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/pm6125.dtsi b/arch/arm/boot/dts/qcom/pm6125.dtsi new file mode 100644 index 000000000000..308adcbb2468 --- /dev/null +++ b/arch/arm/boot/dts/qcom/pm6125.dtsi @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +&spmi_bus { + qcom,pm6125@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + + pm6125_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr", "resin"; + qcom,pon-dbc-delay = <15625>; + qcom,kpdpwr-sw-debounce; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = ; + qcom,pull-up = <1>; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + qcom,pull-up = <1>; + linux,code = ; + }; + }; + + pm6125_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-vdd-reference = <1875>; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel nodes */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + }; + + pm6125_adc_tm: adc_tm@3500 { + compatible = "qcom,adc-tm5"; + reg = <0x3500 0x100>; + interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "thr-int-en"; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + }; + + pm6125_misc: qcom,misc@900 { + compatible = "qcom,qpnp-misc"; + reg = <0x900 0x100>; + }; + + pm6125_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + pm6125_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00 0x100>; + #clock-cells = <1>; + qcom,num-clkdivs = <1>; + clock-output-names = "pm6125_div_clk1"; + clocks = <&clock_rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + assigned-clocks = <&pm6125_clkdiv 1>; + assigned-clock-rates = <9600000>; + }; + + pm6125_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0x900>; + interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>, + <0x0 0xc1 0 IRQ_TYPE_NONE>, + <0x0 0xc2 0 IRQ_TYPE_NONE>, + <0x0 0xc3 0 IRQ_TYPE_NONE>, + <0x0 0xc4 0 IRQ_TYPE_NONE>, + <0x0 0xc5 0 IRQ_TYPE_NONE>, + <0x0 0xc6 0 IRQ_TYPE_NONE>, + <0x0 0xc7 0 IRQ_TYPE_NONE>, + <0x0 0xc8 0 IRQ_TYPE_NONE>; + interrupt-names = "pm6125_gpio1", "pm6125_gpio2", + "pm6125_gpio3", "pm6125_gpio4", + "pm6125_gpio5", "pm6125_gpio6", + "pm6125_gpio7", "pm6125_gpio8", + "pm6125_gpio9"; + gpio-controller; + #gpio-cells = <2>; + }; + + pm6125_rtc: qcom,pm6125_rtc { + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pm6125_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + + qcom,pm6125_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + }; + }; + + qcom,pm6125@1 { + compatible ="qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + + pm6125_pwm: qcom,pwms@b300 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xb300 0x100>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <1>; + #pwm-cells = <2>; + }; + }; +}; + +&thermal_zones { + pm6125_temp_alarm: pm6125-tz { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6125_tz>; + wake-capable-sensor; + + trips { + pm6125_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + pm6125_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/pm6150.dtsi b/arch/arm/boot/dts/qcom/pm6150.dtsi new file mode 100644 index 000000000000..087aa21910ce --- /dev/null +++ b/arch/arm/boot/dts/qcom/pm6150.dtsi @@ -0,0 +1,665 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +&spmi_bus { + qcom,pm6150@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + + pm6150_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr", "resin"; + qcom,pon-dbc-delay = <15625>; + qcom,kpdpwr-sw-debounce; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = ; + qcom,pull-up; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + qcom,pull-up; + linux,code = ; + }; + }; + + pm6150_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100 0x100>, <0x3700 0x100>; + reg-names = "adc5-usr-base", "adc5-cal-base"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-vdd-reference = <1875>; + #io-channel-cells = <1>; + io-channel-ranges; + qcom,pmic-revid = <&pm6150_revid>; + + /* Channel nodes */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vbat_sns { + reg = ; + label = "vbat_sns"; + qcom,pre-scaling = <1 3>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + usb_in_i_uv { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + usb_in_v_div_16 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; + + chg_temp { + reg = ; + label = "chg_temp"; + qcom,pre-scaling = <1 1>; + }; + + bat_therm { + reg = ; + label = "bat_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_therm_30k { + reg = ; + label = "bat_therm_30k"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_therm_400k { + reg = ; + label = "bat_therm_400k"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_id { + reg = ; + label = "bat_id"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + chg_sbux { + reg = ; + label = "chg_sbux"; + qcom,pre-scaling = <1 3>; + }; + + mid_chg_div6 { + reg = ; + label = "chg_mid"; + qcom,pre-scaling = <1 6>; + }; + + v_i_int_ext { + reg = ; + label = "v_i_int_vbat_vdata"; + qcom,pre-scaling = <1 1>; + }; + + v_i_parallel { + reg = ; + label = "v_i_parallel_vbat_vdata"; + qcom,pre-scaling = <1 1>; + }; + + }; + + pm6150_adc_tm: adc_tm@3500 { + compatible = "qcom,adc-tm5"; + reg = <0x3500 0x100>; + interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "thr-int-en"; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + }; + + pm6150_misc: qcom,misc@900 { + compatible = "qcom,qpnp-misc"; + reg = <0x900 0x100>; + }; + + pm6150_charger: qcom,qpnp-smb5 { + compatible = "qcom,qpnp-smb5"; + #address-cells = <1>; + #size-cells = <1>; + #cooling-cells = <2>; + + qcom,pmic-revid = <&pm6150_revid>; + + qcom,chgr@1000 { + reg = <0x1000 0x100>; + interrupts = + <0x0 0x10 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x3 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "chgr-error", + "chg-state-change", + "step-chg-state-change", + "step-chg-soc-update-fail", + "step-chg-soc-update-req", + "fg-fvcal-qualified", + "vph-alarm", + "vph-drop-prechg"; + }; + + qcom,dcdc@1100 { + reg = <0x1100 0x100>; + interrupts = + <0x0 0x11 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x11 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x11 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x11 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x11 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x11 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x11 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0x11 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "otg-fail", + "otg-oc-disable-sw", + "otg-oc-hiccup", + "bsm-active", + "high-duty-cycle", + "input-current-limiting", + "concurrent-mode-disable", + "switcher-power-ok"; + }; + + qcom,batif@1200 { + reg = <0x1200 0x100>; + interrupts = + <0x0 0x12 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x12 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x6 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "bat-temp", + "bat-ov", + "bat-low", + "bat-therm-or-id-missing", + "bat-terminal-missing", + "buck-oc", + "vph-ov"; + }; + + qcom,usb@1300 { + reg = <0x1300 0x100>; + interrupts = + <0x0 0x13 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0x13 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0x13 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "usbin-collapse", + "usbin-vashdn", + "usbin-uv", + "usbin-ov", + "usbin-plugin", + "usbin-revi-change", + "usbin-src-change", + "usbin-icl-change"; + }; + + qcom,dc@1400 { + reg = <0x1400 0x100>; + interrupts = + <0x0 0x14 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x14 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x14 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x14 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x14 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0x14 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0x14 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "dcin-vashdn", + "dcin-uv", + "dcin-ov", + "dcin-plugin", + "dcin-revi", + "dcin-pon", + "dcin-en"; + }; + + qcom,typec@1500 { + reg = <0x1500 0x100>; + interrupts = + <0x0 0x15 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x3 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "typec-or-rid-detect-change", + "typec-vpd-detect", + "typec-cc-state-change", + "typec-vconn-oc", + "typec-vbus-change", + "typec-attach-detach", + "typec-legacy-cable-detect", + "typec-try-snk-src-detect"; + }; + + qcom,misc@1600 { + reg = <0x1600 0x100>; + interrupts = + <0x0 0x16 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x3 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x16 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "wdog-snarl", + "wdog-bark", + "aicl-fail", + "aicl-done", + "smb-en", + "imp-trigger", + "temp-change", + "temp-change-smb"; + }; + + qcom,sdam@b100 { + reg = <0xb100 0x100>; + interrupts = + <0x0 0xb1 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "sdam-sts"; + }; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; + }; + + pm6150_pdphy: qcom,usb-pdphy@1700 { + compatible = "qcom,qpnp-pdphy"; + reg = <0x1700 0x100>; + vdd-pdphy-supply = <&pm6150_l17>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + interrupts = <0x0 0x17 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x3 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "sig-tx", + "sig-rx", + "msg-tx", + "msg-rx", + "msg-tx-failed", + "msg-tx-discarded", + "msg-rx-discarded", + "fr-swap"; + + qcom,default-sink-caps = <5000 3000>, /* 5V @ 3A */ + <9000 3000>, /* 9V @ 3A */ + <12000 2250>; /* 12V @ 2.25A */ + }; + + pm6150_qg: qpnp,qg { + compatible = "qcom,qpnp-qg"; + #address-cells = <1>; + #size-cells = <1>; + + qcom,vbatt-cutoff-mv = <3200>; + qcom,vbatt-low-mv = <3300>; + qcom,vbatt-low-cold-mv = <3700>; + qcom,vbatt-empty-mv = <3000>; + qcom,vbatt-empty-cold-mv = <3000>; + qcom,s3-entry-fifo-length = <2>; + + qcom,pmic-revid = <&pm6150_revid>; + io-channels = <&pm6150_vadc ADC_BAT_THERM_PU2>, + <&pm6150_vadc ADC_BAT_ID_PU2>; + io-channel-names = "batt-therm", + "batt-id"; + + qcom,qgauge@4800 { + status = "okay"; + reg = <0x4800 0x100>; + interrupts = + <0x0 0x48 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x48 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x48 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x48 0x3 IRQ_TYPE_EDGE_RISING>, + <0x0 0x48 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "qg-batt-missing", + "qg-vbat-low", + "qg-vbat-empty", + "qg-fifo-done", + "qg-good-ocv"; + }; + + qcom,qg-sdam@b600 { + status = "okay"; + reg = <0xb600 0x100>; + }; + }; + + pm6150_bcl: bcl@1d00 { + compatible = "qcom,bcl-v5"; + reg = <0x1d00 0x100>; + interrupts = <0x0 0x1d 0x0 IRQ_TYPE_NONE>, + <0x0 0x1d 0x1 IRQ_TYPE_NONE>, + <0x0 0x1d 0x0 IRQ_TYPE_NONE>, + <0x0 0x1d 0x1 IRQ_TYPE_NONE>, + <0x0 0x1d 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-ibat-lvl0", + "bcl-ibat-lvl1", + "bcl-vbat-lvl0", + "bcl-vbat-lvl1", + "bcl-vbat-lvl2"; + #thermal-sensor-cells = <1>; + }; + + bcl_soc:bcl-soc { + compatible = "qcom,msm-bcl-soc"; + #thermal-sensor-cells = <0>; + }; + + pm6150_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + pm6150_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00 0x100>; + #clock-cells = <1>; + qcom,num-clkdivs = <1>; + clock-output-names = "pm6150_div_clk1"; + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + assigned-clocks = <&pm6150_clkdiv 1>; + assigned-clock-rates = <19200000>; + }; + + pm6150_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0xa00>; + interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>, + <0x0 0xc1 0 IRQ_TYPE_NONE>, + <0x0 0xc2 0 IRQ_TYPE_NONE>, + <0x0 0xc3 0 IRQ_TYPE_NONE>, + <0x0 0xc6 0 IRQ_TYPE_NONE>, + <0x0 0xc7 0 IRQ_TYPE_NONE>; + interrupt-names = "pm6150_gpio1", "pm6150_gpio2", + "pm6150_gpio3", "pm6150_gpio4", + "pm6150_gpio7", "pm6150_gpio8"; + gpio-controller; + #gpio-cells = <2>; + qcom,gpios-disallowed = <5 6 9 10>; + }; + + pm6150_rtc: qcom,pm6150_rtc { + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pm6150_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + + qcom,pm6150_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + }; + }; + + qcom,pm6150@1 { + compatible ="qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + + pm6150_vib: qcom,vibrator@5300 { + compatible = "qcom,qpnp-vibrator-ldo"; + reg = <0x5300 0x100>; + qcom,vib-ldo-volt-uv = <3000000>; + qcom,disable-overdrive; + }; + }; +}; + +&thermal_zones { + pm6150_temp_alarm: pm6150-tz { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6150_tz>; + wake-capable-sensor; + + trips { + pm6150_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + pm6150_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + pm6150-ibat-lvl0 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6150_bcl 0>; + wake-capable-sensor; + + trips { + ibat_lvl0:ibat-lvl0 { + temperature = <5500>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm6150-ibat-lvl1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6150_bcl 1>; + wake-capable-sensor; + + trips { + ibat_lvl1:ibat-lvl1 { + temperature = <6000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm6150-vbat-lvl0 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&pm6150_bcl 2>; + wake-capable-sensor; + tracks-low; + + trips { + vbat_lvl0: vbat-lvl0 { + temperature = <3000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm6150-vbat-lvl1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&pm6150_bcl 3>; + wake-capable-sensor; + tracks-low; + + trips { + vbat_lvl1:vbat-lvl1 { + temperature = <2800>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm6150-vbat-lvl2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&pm6150_bcl 4>; + wake-capable-sensor; + tracks-low; + + trips { + vbat_lvl2:vbat-lvl2 { + temperature = <2600>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + soc { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&bcl_soc>; + wake-capable-sensor; + tracks-low; + + trips { + soc_trip:soc-trip { + temperature = <10>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/pm6150l.dtsi b/arch/arm/boot/dts/qcom/pm6150l.dtsi new file mode 100644 index 000000000000..64672673a4f9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/pm6150l.dtsi @@ -0,0 +1,514 @@ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&spmi_bus { + qcom,pm6150l@4 { + compatible = "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + + pm6150l_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + }; + + pm6150l_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + pm6150l_bcl: bcl@3d00 { + compatible = "qcom,bcl-v5"; + reg = <0x3d00 0x100>; + interrupts = <0x4 0x3d 0x0 IRQ_TYPE_NONE>, + <0x4 0x3d 0x1 IRQ_TYPE_NONE>, + <0x4 0x3d 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-vbat-lvl0", + "bcl-vbat-lvl1", + "bcl-vbat-lvl2"; + #thermal-sensor-cells = <1>; + }; + + pm6150l_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-vdd-reference = <1875>; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel node */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + }; + + pm6150l_adc_tm: adc_tm@3500 { + compatible = "qcom,adc-tm5"; + reg = <0x3500 0x100>; + interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "thr-int-en"; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + }; + + pm6150l_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00 0x100>; + #clock-cells = <1>; + qcom,num-clkdivs = <1>; + clock-output-names = "pm6150l_div_clk1"; + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + assigned-clocks = <&pm6150l_clkdiv 1>; + assigned-clock-rates = <9600000>; + }; + + pm6150l_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0xc00>; + interrupts = <0x4 0xc0 0 IRQ_TYPE_NONE>, + <0x4 0xc1 0 IRQ_TYPE_NONE>, + <0x4 0xc2 0 IRQ_TYPE_NONE>, + <0x4 0xc3 0 IRQ_TYPE_NONE>, + <0x4 0xc4 0 IRQ_TYPE_NONE>, + <0x4 0xc5 0 IRQ_TYPE_NONE>, + <0x4 0xc7 0 IRQ_TYPE_NONE>, + <0x4 0xc8 0 IRQ_TYPE_NONE>, + <0x4 0xc9 0 IRQ_TYPE_NONE>, + <0x4 0xca 0 IRQ_TYPE_NONE>, + <0x4 0xcb 0 IRQ_TYPE_NONE>; + interrupt-names = "pm6150l_gpio1", "pm6150l_gpio2", + "pm6150l_gpio3", "pm6150l_gpio4", + "pm6150l_gpio5", "pm6150l_gpio6", + "pm6150l_gpio8", "pm6150l_gpio9", + "pm6150l_gpio10", "pm6150l_gpio11", + "pm6150l_gpio12"; + gpio-controller; + #gpio-cells = <2>; + qcom,gpios-disallowed = <7>; + }; + }; + + qcom,pm6150l@5 { + compatible ="qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + + pm6150l_pwm_1: qcom,pwms@bc00 { + status = "disabled"; + compatible = "qcom,pwm-lpg"; + reg = <0xbc00 0x100>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <1>; + #pwm-cells = <2>; + }; + + pm6150l_lcdb: qcom,lcdb@ec00 { + compatible = "qcom,qpnp-lcdb-regulator"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xec00 0x100>; + interrupts = <0x5 0xec 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "sc-irq"; + qcom,pmic-revid = <&pm6150l_revid>; + qcom,voltage-step-ramp; + status = "disabled"; + + lcdb_ldo_vreg: ldo { + label = "ldo"; + regulator-name = "lcdb_ldo"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + }; + + lcdb_ncp_vreg: ncp { + label = "ncp"; + regulator-name = "lcdb_ncp"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + }; + + lcdb_bst_vreg: bst { + label = "bst"; + regulator-name = "lcdb_bst"; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <6275000>; + }; + }; + + flash_led: qcom,leds@d300 { + compatible = "qcom,qpnp-flash-led-v2"; + status = "okay"; + reg = <0xd300 0x100>; + label = "flash"; + interrupts = <0x5 0xd3 0x0 IRQ_TYPE_EDGE_RISING>, + <0x5 0xd3 0x3 IRQ_TYPE_EDGE_RISING>, + <0x5 0xd3 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "led-fault-irq", + "all-ramp-down-done-irq", + "all-ramp-up-done-irq"; + qcom,hdrm-auto-mode; + qcom,short-circuit-det; + qcom,open-circuit-det; + qcom,vph-droop-det; + qcom,thermal-derate-en; + qcom,thermal-derate-current = <200 500 1000>; + qcom,isc-delay = <192>; + qcom,pmic-revid = <&pm6150l_revid>; + + pm6150l_flash0: qcom,flash_0 { + label = "flash"; + qcom,led-name = "led:flash_0"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash0_trigger"; + qcom,id = <0>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm6150l_flash1: qcom,flash_1 { + label = "flash"; + qcom,led-name = "led:flash_1"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash1_trigger"; + qcom,id = <1>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm6150l_flash2: qcom,flash_2 { + label = "flash"; + qcom,led-name = "led:flash_2"; + qcom,max-current = <750>; + qcom,default-led-trigger = "flash2_trigger"; + qcom,id = <2>; + qcom,current-ma = <500>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + status = "disabled"; + }; + + pm6150l_torch0: qcom,torch_0 { + label = "torch"; + qcom,led-name = "led:torch_0"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch0_trigger"; + qcom,id = <0>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm6150l_torch1: qcom,torch_1 { + label = "torch"; + qcom,led-name = "led:torch_1"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch1_trigger"; + qcom,id = <1>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm6150l_torch2: qcom,torch_2 { + label = "torch"; + qcom,led-name = "led:torch_2"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch2_trigger"; + qcom,id = <2>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + status = "disabled"; + }; + + pm6150l_switch0: qcom,led_switch_0 { + label = "switch"; + qcom,led-name = "led:switch_0"; + qcom,led-mask = <1>; + qcom,default-led-trigger = "switch0_trigger"; + }; + + pm6150l_switch1: qcom,led_switch_1 { + label = "switch"; + qcom,led-name = "led:switch_1"; + qcom,led-mask = <2>; + qcom,default-led-trigger = "switch1_trigger"; + }; + + pm6150l_switch2: qcom,led_switch_2 { + label = "switch"; + qcom,led-name = "led:switch_2"; + qcom,led-mask = <3>; + qcom,default-led-trigger = "switch2_trigger"; + }; + }; + + pm6150l_wled: qcom,wled@d800 { + compatible = "qcom,pm6150l-spmi-wled"; + reg = <0xd800 0x100>, <0xd900 0x100>; + reg-names = "wled-ctrl-base", "wled-sink-base"; + label = "backlight"; + interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, + <0x5 0xd8 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x5 0xd8 0x5 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "ovp-irq", "pre-flash-irq", + "flash-irq"; + qcom,pmic-revid = <&pm6150l_revid>; + qcom,auto-calibration; + status = "disabled"; + + wled_flash: qcom,wled-flash { + label = "flash"; + qcom,default-led-trigger = "wled_flash"; + }; + + wled_torch: qcom,wled-torch { + label = "torch"; + qcom,default-led-trigger = "wled_torch"; + qcom,wled-torch-timer = <1200>; + }; + + wled_switch: qcom,wled-switch { + label = "switch"; + qcom,default-led-trigger = "wled_switch"; + }; + }; + + pm6150l_lpg: qcom,pwms@b100 { + compatible = "qcom,pwm-lpg"; + reg = <0xb100 0x300>, <0xb000 0x100>; + reg-names = "lpg-base", "lut-base"; + #pwm-cells = <2>; + qcom,num-lpg-channels = <3>; + qcom,lut-patterns = <0 10 20 30 40 50 60 70 80 90 100 + 90 80 70 60 50 40 30 20 10 0>; + lpg1 { + qcom,lpg-chan-id = <1>; + qcom,ramp-step-ms = <100>; + qcom,ramp-pause-hi-count = <2>; + qcom,ramp-pause-lo-count = <2>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <20>; + qcom,ramp-from-low-to-high; + qcom,ramp-pattern-repeat; + }; + + lpg2 { + qcom,lpg-chan-id = <2>; + qcom,ramp-step-ms = <100>; + qcom,ramp-pause-hi-count = <2>; + qcom,ramp-pause-lo-count = <2>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <20>; + qcom,ramp-from-low-to-high; + qcom,ramp-pattern-repeat; + }; + + lpg3 { + qcom,lpg-chan-id = <3>; + qcom,ramp-step-ms = <100>; + qcom,ramp-pause-hi-count = <2>; + qcom,ramp-pause-lo-count = <2>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <20>; + qcom,ramp-from-low-to-high; + qcom,ramp-pattern-repeat; + }; + }; + + pm6150l_rgb_led: qcom,leds@d000 { + compatible = "qcom,tri-led"; + reg = <0xd000 0x100>; + red { + label = "red"; + pwms = <&pm6150l_lpg 0 1000000>; + led-sources = <0>; + linux,default-trigger = "timer"; + }; + green { + label = "green"; + pwms = <&pm6150l_lpg 1 1000000>; + led-sources = <1>; + linux,default-trigger = "timer"; + }; + blue { + label = "blue"; + pwms = <&pm6150l_lpg 2 1000000>; + led-sources = <2>; + linux,default-trigger = "timer"; + }; + }; + + pm6150a_amoled: qcom,amoled { + compatible = "qcom,qpnp-amoled-regulator"; + status = "disabled"; + + oledb_vreg: oledb@e000 { + reg = <0xe000 0x100>; + reg-names = "oledb_base"; + regulator-name = "oledb"; + regulator-min-microvolt = <4925000>; + regulator-max-microvolt = <8100000>; + qcom,swire-control; + }; + + ab_vreg: ab@de00 { + reg = <0xde00 0x100>; + reg-names = "ab_base"; + regulator-name = "ab"; + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <6100000>; + qcom,swire-control; + }; + + ibb_vreg: ibb@dc00 { + reg = <0xdc00 0x100>; + reg-names = "ibb_base"; + regulator-name = "ibb"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <5400000>; + qcom,swire-control; + }; + }; + }; +}; + +&thermal_zones { + pm6150l_temp_alarm: pm6150l-tz { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6150l_tz>; + wake-capable-sensor; + + trips { + pm6150l_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + pm6150l_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + pm6150l-vph-lvl0 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&pm6150l_bcl 2>; + wake-capable-sensor; + tracks-low; + + trips { + vph_lvl0: vph-lvl0 { + temperature = <3000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm6150l-vph-lvl1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&pm6150l_bcl 3>; + wake-capable-sensor; + tracks-low; + + trips { + vph_lvl1:vph-lvl1 { + temperature = <2750>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm6150l-vph-lvl2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&pm6150l_bcl 4>; + wake-capable-sensor; + tracks-low; + + trips { + vph_lvl2:vph-lvl2 { + temperature = <2500>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/pm6155.dtsi b/arch/arm/boot/dts/qcom/pm6155.dtsi new file mode 100644 index 000000000000..e96b5638ff3d --- /dev/null +++ b/arch/arm/boot/dts/qcom/pm6155.dtsi @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +&spmi_bus { + qcom,pm6155@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm6155_1_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr", "resin"; + qcom,pon-dbc-delay = <15625>; + qcom,kpdpwr-sw-debounce; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = ; + qcom,pull-up = <1>; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + qcom,pull-up; + linux,code = ; + }; + }; + + pm6155_1_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00 0x200>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm6155_1_div_clk1", + "pm6155_1_div_clk2"; + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm6155_1_rtc: qcom,pm6155_1_rtc { + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pm6155_1_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + qcom,pm6155_1_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + }; + + pm6155_1_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0xa00>; + interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>, + <0x0 0xc1 0 IRQ_TYPE_NONE>, + <0x0 0xc2 0 IRQ_TYPE_NONE>, + <0x0 0xc3 0 IRQ_TYPE_NONE>, + <0x0 0xc4 0 IRQ_TYPE_NONE>, + <0x0 0xc5 0 IRQ_TYPE_NONE>, + <0x0 0xc6 0 IRQ_TYPE_NONE>, + <0x0 0xc7 0 IRQ_TYPE_NONE>, + <0x0 0xc8 0 IRQ_TYPE_NONE>, + <0x0 0xc9 0 IRQ_TYPE_NONE>; + interrupt-names = "pm6155_1_gpio1", "pm6155_1_gpio2", + "pm6155_1_gpio3", "pm6155_1_gpio4", + "pm6155_1_gpio5", "pm6155_1_gpio6", + "pm6155_1_gpio7", "pm6155_1_gpio8", + "pm6155_1_gpio9", "pm6155_1_gpio10"; + gpio-controller; + #gpio-cells = <2>; + }; + + pm6155_1_sdam_2: sdam@b100 { + compatible = "qcom,spmi-sdam"; + reg = <0xb100 0x100>; + }; + + }; + + qcom,pm6155@1 { + compatible ="qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + }; + + /* below definitions are for the second instance of pm6155 */ + qcom,pm6155@4 { + compatible = "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + }; + + pm6155_2_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00 0x200>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm6155_2_div_clk1", + "pm6155_2_div_clk2"; + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm6155_2_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0xa00>; + interrupts = <0x4 0xc0 0 IRQ_TYPE_NONE>, + <0x4 0xc1 0 IRQ_TYPE_NONE>, + <0x4 0xc2 0 IRQ_TYPE_NONE>, + <0x4 0xc3 0 IRQ_TYPE_NONE>, + <0x4 0xc4 0 IRQ_TYPE_NONE>, + <0x4 0xc5 0 IRQ_TYPE_NONE>, + <0x4 0xc6 0 IRQ_TYPE_NONE>, + <0x4 0xc7 0 IRQ_TYPE_NONE>, + <0x4 0xc8 0 IRQ_TYPE_NONE>, + <0x4 0xc9 0 IRQ_TYPE_NONE>; + interrupt-names = "pm6155_2_gpio1", "pm6155_2_gpio2", + "pm6155_2_gpio3", "pm6155_2_gpio4", + "pm6155_2_gpio5", "pm6155_2_gpio6", + "pm6155_2_gpio7", "pm6155_2_gpio8", + "pm6155_2_gpio9", "pm6155_2_gpio10"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + qcom,pm6155@5 { + compatible ="qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/pm8004.dtsi b/arch/arm/boot/dts/qcom/pm8004.dtsi new file mode 100644 index 000000000000..297b57bfa87a --- /dev/null +++ b/arch/arm/boot/dts/qcom/pm8004.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include + +&spmi_bus { + + pmic@4 { + compatible = "qcom,pm8004", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pmic@5 { + compatible = "qcom,pm8004", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/pm8008.dtsi b/arch/arm/boot/dts/qcom/pm8008.dtsi new file mode 100644 index 000000000000..8e856874a022 --- /dev/null +++ b/arch/arm/boot/dts/qcom/pm8008.dtsi @@ -0,0 +1,117 @@ +/* Copyright (c) 2019 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +pm8008_8: qcom,pm8008@8 { + compatible = "qcom,i2c-pmic"; + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + + pm8008_chip: qcom,pm8008-chip@900 { + compatible = "qcom,pm8008-chip"; + reg = <0x900>; + PM8008_EN: qcom,pm8008-chip-en { + regulator-name = "pm8008-chip-en"; + }; + }; + + qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100>; + }; + + pm8008_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0x200>; + interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>, + <0x0 0xc1 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8008_gpio1", "pm8008_gpio2"; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +pm8008_9: qcom,pm8008@9 { + compatible = "qcom,i2c-pmic"; + reg = <0x9>; + #address-cells = <1>; + #size-cells = <0>; + + pm8008_regulators: qcom,pm8008-regulator { + compatible = "qcom,pm8008-regulator"; + pm8008_en-supply = <&PM8008_EN>; + L1P: qcom,pm8008-l1@4000 { + reg = /bits/ 16 <0x4000>; + regulator-name = "pm8008_l1"; + regulator-min-microvolt = <528000>; + regulator-max-microvolt = <1504000>; + qcom,min-dropout-voltage = <225000>; + qcom,hpm-min-load = <10000>; + }; + + L2P: qcom,pm8008-l2@4100 { + reg = /bits/ 16 <0x4100>; + regulator-name = "pm8008_l2"; + regulator-min-microvolt = <528000>; + regulator-max-microvolt = <1504000>; + qcom,min-dropout-voltage = <225000>; + qcom,hpm-min-load = <10000>; + }; + + L3P: qcom,pm8008-l3@4200 { + reg = /bits/ 16 <0x4200>; + regulator-name = "pm8008_l3"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + qcom,min-dropout-voltage = <200000>; + qcom,hpm-min-load = <10000>; + }; + + L4P: qcom,pm8008-l4@4300 { + reg = /bits/ 16 <0x4300>; + regulator-name = "pm8008_l4"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + qcom,min-dropout-voltage = <200000>; + qcom,hpm-min-load = <10000>; + }; + + L5P: qcom,pm8008-l5@4400 { + reg = /bits/ 16 <0x4400>; + regulator-name = "pm8008_l5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + qcom,min-dropout-voltage = <300000>; + qcom,hpm-min-load = <10000>; + }; + + L6P: qcom,pm8008-l6@4400 { + reg = /bits/ 16 <0x4500>; + regulator-name = "pm8008_l6"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + qcom,min-dropout-voltage = <300000>; + qcom,hpm-min-load = <10000>; + }; + + L7P: qcom,pm8008-l7@4400 { + reg = /bits/ 16 <0x4600>; + regulator-name = "pm8008_l7"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + qcom,min-dropout-voltage = <300000>; + qcom,hpm-min-load = <10000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/pm8009.dtsi b/arch/arm/boot/dts/qcom/pm8009.dtsi new file mode 100644 index 000000000000..dd3e4b0baa4f --- /dev/null +++ b/arch/arm/boot/dts/qcom/pm8009.dtsi @@ -0,0 +1,47 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&spmi_bus { + qcom,pm8009@a { + compatible ="qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + + qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + pm8009_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0x400>; + interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>, + <0x0 0xc1 0 IRQ_TYPE_NONE>, + <0x0 0xc3 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8009_gpio1", "pm8009_gpio2", + "pm8009_gpio4"; + gpio-controller; + #gpio-cells = <2>; + qcom,gpios-disallowed = <3>; + }; + }; + + qcom,pm8009@b { + compatible = "qcom,spmi-pmic"; + reg = <0xb SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/pm8150.dtsi b/arch/arm/boot/dts/qcom/pm8150.dtsi new file mode 100644 index 000000000000..f1e9dc2f8283 --- /dev/null +++ b/arch/arm/boot/dts/qcom/pm8150.dtsi @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + + qcom,pm8150@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm8150_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8150_vadc ADC_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr", "resin"; + qcom,pon-dbc-delay = <15625>; + qcom,kpdpwr-sw-debounce; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = ; + qcom,pull-up; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + qcom,pull-up; + linux,code = ; + }; + }; + + pm8150_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00 0x200>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8150_div_clk1", + "pm8150_div_clk2"; + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8150_rtc: qcom,pm8150_rtc { + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pm8150_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + qcom,pm8150_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + }; + + pm8150_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0xa00>; + interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>, + <0x0 0xc2 0 IRQ_TYPE_NONE>, + <0x0 0xc3 0 IRQ_TYPE_NONE>, + <0x0 0xc5 0 IRQ_TYPE_NONE>, + <0x0 0xc6 0 IRQ_TYPE_NONE>, + <0x0 0xc8 0 IRQ_TYPE_NONE>, + <0x0 0xc9 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8150_gpio1", "pm8150_gpio3", + "pm8150_gpio4", "pm8150_gpio6", + "pm8150_gpio7","pm8150_gpio9", "pm8150_gpio10"; + gpio-controller; + #gpio-cells = <2>; + qcom,gpios-disallowed = <2 5 8>; + }; + + pm8150_sdam_2: sdam@b100 { + compatible = "qcom,spmi-sdam"; + reg = <0xb100 0x100>; + }; + + pm8150_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-vdd-reference = <1875>; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel node */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + + pm8150_adc_tm: adc_tm@3500 { + compatible = "qcom,adc-tm5"; + reg = <0x3500 0x100>; + interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "thr-int-en"; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + io-channels = <&pm8150_vadc ADC_XO_THERM_PU2>, + <&pm8150_vadc ADC_AMUX_THM1_PU2>, + <&pm8150_vadc ADC_AMUX_THM2_PU2>; + }; + }; + + qcom,pm8150@1 { + compatible ="qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + }; +}; + +&thermal_zones { + pm8150_temp_alarm: pm8150_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8150_tz>; + wake-capable-sensor; + + trips { + pm8150_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + pm8150_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/pm8150b.dtsi b/arch/arm/boot/dts/qcom/pm8150b.dtsi new file mode 100644 index 000000000000..c410e178f2e6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/pm8150b.dtsi @@ -0,0 +1,703 @@ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + + qcom,pm8150b@2 { + compatible = "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm8150b_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + }; + + pm8150b_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8150b_vadc ADC_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + pm8150b_clkdiv: clock-controller@6000 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x6000 0x100>; + #clock-cells = <1>; + qcom,num-clkdivs = <1>; + clock-output-names = "pm8150b_div_clk1"; + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8150b_qnovo: qcom,sdam-qnovo@b000 { + compatible = "qcom,qpnp-qnovo5"; + reg = <0xb000 0x100>; + interrupts = <0x2 0xb0 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ptrain-done"; + }; + + pm8150b_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0xc00>; + interrupts = <0x2 0xc0 0 IRQ_TYPE_NONE>, + <0x2 0xc1 0 IRQ_TYPE_NONE>, + <0x2 0xc4 0 IRQ_TYPE_NONE>, + <0x2 0xc5 0 IRQ_TYPE_NONE>, + <0x2 0xc7 0 IRQ_TYPE_NONE>, + <0x2 0xc8 0 IRQ_TYPE_NONE>, + <0x2 0xc9 0 IRQ_TYPE_NONE>, + <0x2 0xca 0 IRQ_TYPE_NONE>, + <0x2 0xcb 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8150b_gpio1", "pm8150b_gpio2", + "pm8150b_gpio5", "pm8150b_gpio6", + "pm8150b_gpio8", "pm8150b_gpio9", + "pm8150b_gpio10", "pm8150b_gpio11", + "pm8150b_gpio12"; + gpio-controller; + #gpio-cells = <2>; + qcom,gpios-disallowed = <3 4 7>; + }; + + pm8150b_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100 0x100>, <0x3700 0x100>; + reg-names = "adc5-usr-base", "adc5-cal-base"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-vdd-reference = <1875>; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel node */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + + chg_temp { + reg = ; + label = "chg_temp"; + qcom,pre-scaling = <1 1>; + }; + + v_i_int_ext { + reg = ; + label = "v_i_int_vbat_vdata"; + qcom,pre-scaling = <1 1>; + }; + + v_i_ext { + reg = ; + label = "v_i_int_ext_vbat_vdata"; + qcom,pre-scaling = <1 1>; + }; + + v_i_parallel { + reg = ; + label = "v_i_parallel_vbat_vdata"; + qcom,pre-scaling = <1 1>; + }; + + smb1390_therm { + reg = ; + label = "smb1390_therm"; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + smb1355_therm { + reg = ; + label = "smb1355_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + }; + + pm8150b_adc_tm: adc_tm@3500 { + compatible = "qcom,adc-tm5"; + reg = <0x3500 0x100>; + interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "thr-int-en"; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + io-channels = <&pm8150b_vadc ADC_AMUX_THM1_PU2>; + qcom,pmic-revid = <&pm8150b_revid>; + }; + + pm8150b_charger: qcom,qpnp-smb5 { + compatible = "qcom,qpnp-smb5"; + #address-cells = <1>; + #size-cells = <1>; + #cooling-cells = <2>; + + qcom,pmic-revid = <&pm8150b_revid>; + + qcom,thermal-mitigation + = <3000000 1500000 1000000 500000>; + + qcom,chg-term-src = <1>; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + + qcom,chgr@1000 { + reg = <0x1000 0x100>; + interrupts = + <0x2 0x10 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x4 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x6 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x10 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "chgr-error", + "chg-state-change", + "step-chg-state-change", + "step-chg-soc-update-fail", + "step-chg-soc-update-req", + "vph-alarm", + "vph-drop-prechg"; + }; + + qcom,dcdc@1100 { + reg = <0x1100 0x100>; + interrupts = + <0x2 0x11 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x6 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "otg-fail", + "otg-oc-disable-sw", + "otg-oc-hiccup", + "high-duty-cycle", + "input-current-limiting", + "concurrent-mode-disable", + "switcher-power-ok"; + }; + + qcom,batif@1200 { + reg = <0x1200 0x100>; + interrupts = + <0x2 0x12 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x6 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "bat-temp", + "bat-ov", + "bat-low", + "bat-therm-or-id-missing", + "bat-terminal-missing", + "buck-oc", + "vph-ov"; + }; + + qcom,usb@1300 { + reg = <0x1300 0x100>; + interrupts = + <0x2 0x13 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x13 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "usbin-collapse", + "usbin-vashdn", + "usbin-uv", + "usbin-ov", + "usbin-plugin", + "usbin-revi-change", + "usbin-src-change", + "usbin-icl-change"; + }; + + qcom,dc@1400 { + reg = <0x1400 0x100>; + interrupts = + <0x2 0x14 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x6 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x14 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "dcin-vashdn", + "dcin-uv", + "dcin-ov", + "dcin-plugin", + "dcin-revi", + "dcin-pon", + "dcin-en"; + }; + + qcom,typec@1500 { + reg = <0x1500 0x100>; + interrupts = + <0x2 0x15 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x15 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x15 0x4 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x6 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x15 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "typec-or-rid-detect-change", + "typec-vpd-detect", + "typec-cc-state-change", + "typec-vconn-oc", + "typec-vbus-change", + "typec-attach-detach", + "typec-legacy-cable-detect", + "typec-try-snk-src-detect"; + }; + + qcom,misc@1600 { + reg = <0x1600 0x100>; + interrupts = + <0x2 0x16 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x16 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x16 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x16 0x6 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x16 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "wdog-snarl", + "wdog-bark", + "aicl-fail", + "aicl-done", + "smb-en", + "temp-change", + "temp-change-smb"; + }; + }; + + pm8150b_pdphy: qcom,usb-pdphy@1700 { + compatible = "qcom,qpnp-pdphy"; + reg = <0x1700 0x100>; + vdd-pdphy-supply = <&pm8150_l2>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; + interrupts = <0x2 0x17 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x4 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x17 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "sig-tx", + "sig-rx", + "msg-tx", + "msg-rx", + "msg-tx-failed", + "msg-tx-discarded", + "msg-rx-discarded", + "fr-swap"; + + qcom,default-sink-caps = <5000 3000>, /* 5V @ 3A */ + <9000 3000>, /* 9V @ 3A */ + <12000 2250>; /* 12V @ 2.25A */ + }; + + pm8150b_bcl: bcl@1d00 { + compatible = "qcom,bcl-v5"; + reg = <0x1d00 0x100>; + interrupts = <0x2 0x1d 0x0 IRQ_TYPE_NONE>, + <0x2 0x1d 0x1 IRQ_TYPE_NONE>, + <0x2 0x1d 0x0 IRQ_TYPE_NONE>, + <0x2 0x1d 0x1 IRQ_TYPE_NONE>, + <0x2 0x1d 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-ibat-lvl0", + "bcl-ibat-lvl1", + "bcl-vbat-lvl0", + "bcl-vbat-lvl1", + "bcl-vbat-lvl2"; + #thermal-sensor-cells = <1>; + }; + + bcl_soc:bcl-soc { + compatible = "qcom,msm-bcl-soc"; + #thermal-sensor-cells = <0>; + }; + + pm8150b_fg: qpnp,fg { + compatible = "qcom,fg-gen4"; + #address-cells = <1>; + #size-cells = <1>; + qcom,pmic-revid = <&pm8150b_revid>; + status = "okay"; + + qcom,fg-batt-soc@4000 { + status = "okay"; + reg = <0x4000 0x100>; + interrupts = <0x2 0x40 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x40 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x40 0x2 + IRQ_TYPE_EDGE_RISING>, + <0x2 0x40 0x3 + IRQ_TYPE_EDGE_RISING>, + <0x2 0x40 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x40 0x5 + IRQ_TYPE_EDGE_RISING>, + <0x2 0x40 0x6 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x40 0x7 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "soc-update", + "soc-ready", + "bsoc-delta", + "msoc-delta", + "msoc-low", + "msoc-empty", + "msoc-high", + "msoc-full"; + }; + + qcom,fg-batt-info@4100 { + status = "okay"; + reg = <0x4100 0x100>; + interrupts = <0x2 0x41 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x41 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x41 0x3 + IRQ_TYPE_EDGE_RISING>; + interrupt-names = "vbatt-low", + "vbatt-pred-delta", + "esr-delta"; + }; + + qcom,fg-rradc@4200 { + status = "okay"; + reg = <0x4200 0x100>; + interrupts = <0x2 0x42 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x42 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x42 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x42 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x42 0x4 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "batt-missing", + "batt-id", + "batt-temp-delta", + "batt-temp-hot", + "batt-temp-cold"; + }; + + qcom,fg-memif@4300 { + status = "okay"; + reg = <0x4300 0x100>; + interrupts = <0x2 0x43 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x43 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x43 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x43 0x3 + IRQ_TYPE_EDGE_RISING>, + <0x2 0x43 0x4 + IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "ima-rdy", + "ima-xcp", + "dma-xcp", + "dma-grant", + "mem-attn"; + }; + }; + }; + + qcom,pm8150b@3 { + compatible ="qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm8150b_pwm: qcom,pwms@b100 { + compatible = "qcom,pwm-lpg"; + reg = <0xb100 0x200>; + reg-names = "lpg-base"; + #pwm-cells = <2>; + qcom,num-lpg-channels = <2>; + }; + + pm8150b_hr_led: qcom,leds@d000 { + compatible = "qcom,tri-led"; + reg = <0xd000 0x100>; + nvmem-names = "pbs_sdam"; + nvmem = <&pm8150_sdam_2>; + hr_led1 { + label = "hr_led1"; + pwms = <&pm8150b_pwm 0 1000000>; + led-sources = <0>; + }; + hr_led2 { + label = "hr_led2"; + pwms = <&pm8150b_pwm 1 1000000>; + led-sources = <1>; + }; + }; + + pm8150b_haptics: qcom,haptics@c000 { + compatible = "qcom,haptics"; + reg = <0xc000 0x100>; + interrupts = <0x3 0xc0 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x3 0xc0 0x1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hap-sc-irq", "hap-play-irq"; + qcom,actuator-type = "lra"; + qcom,vmax-mv = <3400>; + qcom,play-rate-us = <6667>; + qcom,lra-resonance-sig-shape = "sine"; + qcom,lra-auto-resonance-mode = "qwd"; + qcom,lra-allow-variable-play-rate; + + wf_0 { + /* CLICK */ + qcom,effect-id = <0>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [3e 3e 3e]; + qcom,wf-play-rate-us = <6667>; + qcom,wf-brake-pattern = [01 00 00 00]; + qcom,lra-auto-resonance-disable; + }; + wf_1 { + /* DOUBLE CLICK */ + qcom,effect-id = <1>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [7e 7e 02 02 02 02 02 02]; + qcom,wf-play-rate-us = <7143>; + qcom,wf-repeat-count = <2>; + qcom,wf-s-repeat-count = <1>; + qcom,lra-auto-resonance-disable; + }; + wf_2 { + /* TICK */ + qcom,effect-id = <2>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [7e 7e]; + qcom,wf-play-rate-us = <4000>; + qcom,lra-auto-resonance-disable; + }; + wf_3 { + /* THUD */ + qcom,effect-id = <3>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [7e 7e 7e]; + qcom,wf-play-rate-us = <6667>; + qcom,lra-auto-resonance-disable; + }; + wf_4 { + /* POP */ + qcom,effect-id = <4>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [7e 7e]; + qcom,wf-play-rate-us = <5000>; + qcom,lra-auto-resonance-disable; + }; + wf_5 { + /* HEAVY CLICK */ + qcom,effect-id = <5>; + qcom,wf-vmax-mv = <3600>; + qcom,wf-pattern = [7e 7e 7e]; + qcom,wf-play-rate-us = <6667>; + qcom,wf-brake-pattern = [03 00 00 00]; + qcom,lra-auto-resonance-disable; + }; + }; + }; +}; + +&thermal_zones { + pm8150b-wp-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pm8150b_temp_alarm: pm8150b_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8150b_tz>; + wake-capable-sensor; + + trips { + pm8150b_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + pm8150b_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + pm8150b-ibat-lvl0 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8150b_bcl 0>; + wake-capable-sensor; + + trips { + ibat_lvl0:ibat-lvl0 { + temperature = <4500>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm8150b-ibat-lvl1 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8150b_bcl 1>; + wake-capable-sensor; + + trips { + ibat_lvl1:ibat-lvl1 { + temperature = <5000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm8150b-vbat-lvl0 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&pm8150b_bcl 2>; + wake-capable-sensor; + tracks-low; + + trips { + vbat_lvl0: vbat-lvl0 { + temperature = <3000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm8150b-vbat-lvl1 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&pm8150b_bcl 3>; + wake-capable-sensor; + tracks-low; + + trips { + vbat_lvl1:vbat-lvl1 { + temperature = <2800>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm8150b-vbat-lvl2 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&pm8150b_bcl 4>; + wake-capable-sensor; + tracks-low; + + trips { + vbat_lvl2:vbat-lvl2 { + temperature = <2600>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + soc { + polling-delay-passive = <1000>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&bcl_soc>; + wake-capable-sensor; + tracks-low; + + trips { + soc_trip:soc-trip { + temperature = <5>; + hysteresis = <0>; + type = "passive"; + }; + soc_trip2:soc-trip2 { + temperature = <15>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/pm8150l.dtsi b/arch/arm/boot/dts/qcom/pm8150l.dtsi new file mode 100644 index 000000000000..96e20a8df850 --- /dev/null +++ b/arch/arm/boot/dts/qcom/pm8150l.dtsi @@ -0,0 +1,516 @@ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + + qcom,pm8150l@4 { + compatible = "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm8150l_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + }; + + pm8150l_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8150l_vadc ADC_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + pm8150l_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00 0x100>; + #clock-cells = <1>; + qcom,num-clkdivs = <1>; + clock-output-names = "pm8150l_div_clk1"; + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8150l_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0xc00>; + interrupts = <0x4 0xc0 0 IRQ_TYPE_NONE>, + <0x4 0xc1 0 IRQ_TYPE_NONE>, + <0x4 0xc2 0 IRQ_TYPE_NONE>, + <0x4 0xc3 0 IRQ_TYPE_NONE>, + <0x4 0xc4 0 IRQ_TYPE_NONE>, + <0x4 0xc5 0 IRQ_TYPE_NONE>, + <0x4 0xc7 0 IRQ_TYPE_NONE>, + <0x4 0xc8 0 IRQ_TYPE_NONE>, + <0x4 0xc9 0 IRQ_TYPE_NONE>, + <0x4 0xca 0 IRQ_TYPE_NONE>, + <0x4 0xcb 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8150l_gpio1", "pm8150l_gpio2", + "pm8150l_gpio3", "pm8150l_gpio4", + "pm8150l_gpio5", "pm8150l_gpio6", + "pm8150l_gpio8", "pm8150l_gpio9", + "pm8150l_gpio10", "pm8150l_gpio11", + "pm8150l_gpio12"; + gpio-controller; + #gpio-cells = <2>; + qcom,gpios-disallowed = <7>; + }; + + pm8150l_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-vdd-reference = <1875>; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel node */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + + pm8150l_bcl: bcl@3d00 { + compatible = "qcom,bcl-v5"; + reg = <0x3d00 0x100>; + interrupts = <0x4 0x3d 0x0 IRQ_TYPE_NONE>, + <0x4 0x3d 0x1 IRQ_TYPE_NONE>, + <0x4 0x3d 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-vbat-lvl0", + "bcl-vbat-lvl1", + "bcl-vbat-lvl2"; + #thermal-sensor-cells = <1>; + }; + + pm8150l_adc_tm: adc_tm@3500 { + compatible = "qcom,adc-tm5"; + reg = <0x3500 0x100>; + interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "thr-int-en"; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + io-channels = <&pm8150l_vadc ADC_AMUX_THM1_PU2>, + <&pm8150l_vadc ADC_AMUX_THM2_PU2>, + <&pm8150l_vadc ADC_AMUX_THM3_PU2>; + }; + }; + + qcom,pm8150l@5 { + compatible ="qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm8150l_lcdb: qcom,lcdb@ec00 { + compatible = "qcom,qpnp-lcdb-regulator"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xec00 0x100>; + interrupts = <0x5 0xec 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "sc-irq"; + qcom,pmic-revid = <&pm8150l_revid>; + qcom,voltage-step-ramp; + status = "disabled"; + + lcdb_ldo_vreg: ldo { + label = "ldo"; + regulator-name = "lcdb_ldo"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + }; + + lcdb_ncp_vreg: ncp { + label = "ncp"; + regulator-name = "lcdb_ncp"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + }; + + lcdb_bst_vreg: bst { + label = "bst"; + regulator-name = "lcdb_bst"; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <6275000>; + }; + }; + + flash_led: qcom,leds@d300 { + compatible = "qcom,qpnp-flash-led-v2"; + status = "okay"; + reg = <0xd300 0x100>; + label = "flash"; + interrupts = <0x5 0xd3 0x0 IRQ_TYPE_EDGE_RISING>, + <0x5 0xd3 0x3 IRQ_TYPE_EDGE_RISING>, + <0x5 0xd3 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "led-fault-irq", + "all-ramp-down-done-irq", + "all-ramp-up-done-irq"; + qcom,hdrm-auto-mode; + qcom,short-circuit-det; + qcom,open-circuit-det; + qcom,vph-droop-det; + qcom,thermal-derate-en; + qcom,thermal-derate-current = <200 500 1000>; + qcom,isc-delay = <192>; + qcom,pmic-revid = <&pm8150l_revid>; + + pm8150l_flash0: qcom,flash_0 { + label = "flash"; + qcom,led-name = "led:flash_0"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash0_trigger"; + qcom,id = <0>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm8150l_flash1: qcom,flash_1 { + label = "flash"; + qcom,led-name = "led:flash_1"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash1_trigger"; + qcom,id = <1>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm8150l_flash2: qcom,flash_2 { + label = "flash"; + qcom,led-name = "led:flash_2"; + qcom,max-current = <750>; + qcom,default-led-trigger = "flash2_trigger"; + qcom,id = <2>; + qcom,current-ma = <500>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + status = "disabled"; + }; + + pm8150l_torch0: qcom,torch_0 { + label = "torch"; + qcom,led-name = "led:torch_0"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch0_trigger"; + qcom,id = <0>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm8150l_torch1: qcom,torch_1 { + label = "torch"; + qcom,led-name = "led:torch_1"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch1_trigger"; + qcom,id = <1>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm8150l_torch2: qcom,torch_2 { + label = "torch"; + qcom,led-name = "led:torch_2"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch2_trigger"; + qcom,id = <2>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + status = "disabled"; + }; + + pm8150l_switch0: qcom,led_switch_0 { + label = "switch"; + qcom,led-name = "led:switch_0"; + qcom,led-mask = <1>; + qcom,default-led-trigger = "switch0_trigger"; + }; + + pm8150l_switch1: qcom,led_switch_1 { + label = "switch"; + qcom,led-name = "led:switch_1"; + qcom,led-mask = <2>; + qcom,default-led-trigger = "switch1_trigger"; + }; + + pm8150l_switch2: qcom,led_switch_2 { + label = "switch"; + qcom,led-name = "led:switch_2"; + qcom,led-mask = <3>; + qcom,default-led-trigger = "switch2_trigger"; + }; + }; + + pm8150l_wled: qcom,wled@d800 { + compatible = "qcom,pm8150l-spmi-wled"; + reg = <0xd800 0x100>, <0xd900 0x100>; + reg-names = "wled-ctrl-base", "wled-sink-base"; + label = "backlight"; + interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, + <0x5 0xd8 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x5 0xd8 0x5 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "ovp-irq", "pre-flash-irq", + "flash-irq"; + qcom,pmic-revid = <&pm8150l_revid>; + qcom,auto-calibration; + status = "disabled"; + + wled_flash: qcom,wled-flash { + label = "flash"; + qcom,default-led-trigger = "wled_flash"; + }; + + wled_torch: qcom,wled-torch { + label = "torch"; + qcom,default-led-trigger = "wled_torch"; + qcom,wled-torch-timer = <1200>; + }; + + wled_switch: qcom,wled-switch { + label = "switch"; + qcom,default-led-trigger = "wled_switch"; + }; + }; + + pm8150l_lpg: qcom,pwms@b100 { + compatible = "qcom,pwm-lpg"; + reg = <0xb100 0x300>, <0xb000 0x100>; + reg-names = "lpg-base", "lut-base"; + #pwm-cells = <2>; + qcom,num-lpg-channels = <3>; + qcom,lut-patterns = <0 10 20 30 40 50 60 70 80 90 100 + 90 80 70 60 50 40 30 20 10 0>; + lpg1 { + qcom,lpg-chan-id = <1>; + qcom,ramp-step-ms = <100>; + qcom,ramp-pause-hi-count = <2>; + qcom,ramp-pause-lo-count = <2>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <20>; + qcom,ramp-from-low-to-high; + qcom,ramp-pattern-repeat; + }; + + lpg2 { + qcom,lpg-chan-id = <2>; + qcom,ramp-step-ms = <100>; + qcom,ramp-pause-hi-count = <2>; + qcom,ramp-pause-lo-count = <2>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <20>; + qcom,ramp-from-low-to-high; + qcom,ramp-pattern-repeat; + }; + + lpg3 { + qcom,lpg-chan-id = <3>; + qcom,ramp-step-ms = <100>; + qcom,ramp-pause-hi-count = <2>; + qcom,ramp-pause-lo-count = <2>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <20>; + qcom,ramp-from-low-to-high; + qcom,ramp-pattern-repeat; + }; + }; + + pm8150l_pwm: qcom,pwms@bc00 { + compatible = "qcom,pwm-lpg"; + reg = <0xbc00 0x200>; + reg-names = "lpg-base"; + #pwm-cells = <2>; + qcom,num-lpg-channels = <2>; + }; + + pm8150l_rgb_led: qcom,leds@d000 { + compatible = "qcom,tri-led"; + reg = <0xd000 0x100>; + red { + label = "red"; + pwms = <&pm8150l_lpg 0 1000000>; + led-sources = <0>; + linux,default-trigger = "timer"; + }; + green { + label = "green"; + pwms = <&pm8150l_lpg 1 1000000>; + led-sources = <1>; + linux,default-trigger = "timer"; + }; + blue { + label = "blue"; + pwms = <&pm8150l_lpg 2 1000000>; + led-sources = <2>; + linux,default-trigger = "timer"; + }; + }; + + pm8150a_amoled: qcom,amoled { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "qcom,qpnp-amoled-regulator"; + status = "disabled"; + + oledb_vreg: oledb@e000 { + reg = <0xe000 0x100>; + reg-names = "oledb_base"; + regulator-name = "oledb"; + regulator-min-microvolt = <4925000>; + regulator-max-microvolt = <8100000>; + qcom,swire-control; + }; + + ab_vreg: ab@de00 { + reg = <0xde00 0x100>; + reg-names = "ab_base"; + regulator-name = "ab"; + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <6100000>; + qcom,swire-control; + }; + + ibb_vreg: ibb@dc00 { + reg = <0xdc00 0x100>; + reg-names = "ibb_base"; + regulator-name = "ibb"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <5400000>; + qcom,swire-control; + }; + }; + }; +}; + +&thermal_zones { + pm8150l_temp_alarm: pm8150l_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8150l_tz>; + wake-capable-sensor; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + pm8150l-vph-lvl0 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&pm8150l_bcl 2>; + wake-capable-sensor; + tracks-low; + + trips { + vph_lvl0: vph-lvl0 { + temperature = <3000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm8150l-vph-lvl1 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&pm8150l_bcl 3>; + wake-capable-sensor; + tracks-low; + + trips { + vph_lvl1:vph-lvl1 { + temperature = <2750>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pm8150l-vph-lvl2 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&pm8150l_bcl 4>; + wake-capable-sensor; + tracks-low; + + trips { + vph_lvl2:vph-lvl2 { + temperature = <2500>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/pm8195.dtsi b/arch/arm/boot/dts/qcom/pm8195.dtsi new file mode 100644 index 000000000000..51036638acb1 --- /dev/null +++ b/arch/arm/boot/dts/qcom/pm8195.dtsi @@ -0,0 +1,251 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +&spmi_bus { + qcom,pm8195@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm8195_1_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr", "resin"; + qcom,pon-dbc-delay = <15625>; + qcom,kpdpwr-sw-debounce; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = ; + qcom,pull-up = <1>; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + qcom,pull-up; + linux,code = ; + }; + }; + + pm8195_1_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00 0x200>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8195_1_div_clk1", + "pm8195_1_div_clk2"; + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8195_1_rtc: qcom,pm8195_1_rtc { + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pm8195_1_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + qcom,pm8195_1_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + }; + + pm8195_1_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0xa00>; + interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>, + <0x0 0xc1 0 IRQ_TYPE_NONE>, + <0x0 0xc2 0 IRQ_TYPE_NONE>, + <0x0 0xc3 0 IRQ_TYPE_NONE>, + <0x0 0xc4 0 IRQ_TYPE_NONE>, + <0x0 0xc5 0 IRQ_TYPE_NONE>, + <0x0 0xc6 0 IRQ_TYPE_NONE>, + <0x0 0xc7 0 IRQ_TYPE_NONE>, + <0x0 0xc8 0 IRQ_TYPE_NONE>, + <0x0 0xc9 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8195_1_gpio1", "pm8195_1_gpio2", + "pm8195_1_gpio3", "pm8195_1_gpio4", + "pm8195_1_gpio5", "pm8195_1_gpio6", + "pm8195_1_gpio7", "pm8195_1_gpio8", + "pm8195_1_gpio9", "pm8195_1_gpio10"; + gpio-controller; + #gpio-cells = <2>; + }; + + pm8195_1_sdam_2: sdam@b100 { + compatible = "qcom,spmi-sdam"; + reg = <0xb100 0x100>; + }; + + }; + + qcom,pm8195@1 { + compatible ="qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + }; + + /* below definitions are for the second instance of pm8195 */ + qcom,pm8195@4 { + compatible = "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + }; + + pm8195_2_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00 0x200>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8195_2_div_clk1", + "pm8195_2_div_clk2"; + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8195_2_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0xa00>; + interrupts = <0x4 0xc0 0 IRQ_TYPE_NONE>, + <0x4 0xc1 0 IRQ_TYPE_NONE>, + <0x4 0xc2 0 IRQ_TYPE_NONE>, + <0x4 0xc3 0 IRQ_TYPE_NONE>, + <0x4 0xc4 0 IRQ_TYPE_NONE>, + <0x4 0xc5 0 IRQ_TYPE_NONE>, + <0x4 0xc6 0 IRQ_TYPE_NONE>, + <0x4 0xc7 0 IRQ_TYPE_NONE>, + <0x4 0xc8 0 IRQ_TYPE_NONE>, + <0x4 0xc9 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8195_2_gpio1", "pm8195_2_gpio2", + "pm8195_2_gpio3", "pm8195_2_gpio4", + "pm8195_2_gpio5", "pm8195_2_gpio6", + "pm8195_2_gpio7", "pm8195_2_gpio8", + "pm8195_2_gpio9", "pm8195_2_gpio10"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + qcom,pm8195@5 { + compatible ="qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + }; + + /* below definitions are for the third instance of pm8195 */ + qcom,pm8195@8 { + compatible = "qcom,spmi-pmic"; + reg = <0x8 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + }; + + pm8195_3_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00 0x200>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8195_3_div_clk1", + "pm8195_3_div_clk2"; + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8195_3_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0xa00>; + interrupts = <0x8 0xc0 0 IRQ_TYPE_NONE>, + <0x8 0xc1 0 IRQ_TYPE_NONE>, + <0x8 0xc2 0 IRQ_TYPE_NONE>, + <0x8 0xc3 0 IRQ_TYPE_NONE>, + <0x8 0xc4 0 IRQ_TYPE_NONE>, + <0x8 0xc5 0 IRQ_TYPE_NONE>, + <0x8 0xc6 0 IRQ_TYPE_NONE>, + <0x8 0xc7 0 IRQ_TYPE_NONE>, + <0x8 0xc8 0 IRQ_TYPE_NONE>, + <0x8 0xc9 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8195_3_gpio1", "pm8195_3_gpio2", + "pm8195_3_gpio3", "pm8195_3_gpio4", + "pm8195_3_gpio5", "pm8195_3_gpio6", + "pm8195_3_gpio7", "pm8195_3_gpio8", + "pm8195_3_gpio9", "pm8195_3_gpio10"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + qcom,pm8195@9 { + compatible ="qcom,spmi-pmic"; + reg = <0x9 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +/* PMIC GPIO pin control configurations */ +&pm8195_1_gpios { + storage_sd_detect { + storage_cd_default: storage_cd_default { + pins = "gpio4"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; + + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/pm8916.dtsi b/arch/arm/boot/dts/qcom/pm8916.dtsi new file mode 100644 index 000000000000..0223e60d8b6a --- /dev/null +++ b/arch/arm/boot/dts/qcom/pm8916.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include + +&spmi_bus { + + pm8916_0: pm8916@0 { + compatible = "qcom,pm8916", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pwrkey@800 { + compatible = "qcom,pm8941-pwrkey"; + reg = <0x800>; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + }; + + pm8916_gpios: gpios@c000 { + compatible = "qcom,pm8916-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, + <0 0xc1 0 IRQ_TYPE_NONE>, + <0 0xc2 0 IRQ_TYPE_NONE>, + <0 0xc3 0 IRQ_TYPE_NONE>; + }; + + pm8916_mpps: mpps@a000 { + compatible = "qcom,pm8916-mpp"; + reg = <0xa000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, + <0 0xa1 0 IRQ_TYPE_NONE>, + <0 0xa2 0 IRQ_TYPE_NONE>, + <0 0xa3 0 IRQ_TYPE_NONE>; + }; + + pm8916_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8916_vadc VADC_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm8916_vadc: vadc@3100 { + compatible = "qcom,spmi-vadc"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + usb_in { + reg = ; + qcom,pre-scaling = <1 10>; + }; + vph_pwr { + reg = ; + qcom,pre-scaling = <1 3>; + }; + die_temp { + reg = ; + }; + ref_625mv { + reg = ; + }; + ref_1250v { + reg = ; + }; + ref_gnd { + reg = ; + }; + ref_vdd { + reg = ; + }; + }; + }; + + pm8916_1: pm8916@1 { + compatible = "qcom,pm8916", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + wcd_codec: codec@f000 { + compatible = "qcom,pm8916-wcd-analog-codec"; + reg = <0xf000 0x200>; + reg-names = "pmic-codec-core"; + clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; + clock-names = "mclk"; + interrupt-parent = <&spmi_bus>; + interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>, + <0x1 0xf0 0x1 IRQ_TYPE_NONE>, + <0x1 0xf0 0x2 IRQ_TYPE_NONE>, + <0x1 0xf0 0x3 IRQ_TYPE_NONE>, + <0x1 0xf0 0x4 IRQ_TYPE_NONE>, + <0x1 0xf0 0x5 IRQ_TYPE_NONE>, + <0x1 0xf0 0x6 IRQ_TYPE_NONE>, + <0x1 0xf0 0x7 IRQ_TYPE_NONE>, + <0x1 0xf1 0x0 IRQ_TYPE_NONE>, + <0x1 0xf1 0x1 IRQ_TYPE_NONE>, + <0x1 0xf1 0x2 IRQ_TYPE_NONE>, + <0x1 0xf1 0x3 IRQ_TYPE_NONE>, + <0x1 0xf1 0x4 IRQ_TYPE_NONE>, + <0x1 0xf1 0x5 IRQ_TYPE_NONE>; + interrupt-names = "cdc_spk_cnp_int", + "cdc_spk_clip_int", + "cdc_spk_ocp_int", + "mbhc_ins_rem_det1", + "mbhc_but_rel_det", + "mbhc_but_press_det", + "mbhc_ins_rem_det", + "mbhc_switch_int", + "cdc_ear_ocp_int", + "cdc_hphr_ocp_int", + "cdc_hphl_ocp_det", + "cdc_ear_cnp_int", + "cdc_hphr_cnp_int", + "cdc_hphl_cnp_int"; + vdd-cdc-io-supply = <&pm8916_l5>; + vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>; + vdd-micbias-supply = <&pm8916_l13>; + #sound-dai-cells = <1>; + + }; + + }; +}; diff --git a/arch/arm/boot/dts/qcom/pm8994.dtsi b/arch/arm/boot/dts/qcom/pm8994.dtsi new file mode 100644 index 000000000000..80024c0b1c7c --- /dev/null +++ b/arch/arm/boot/dts/qcom/pm8994.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include + +&spmi_bus { + + pmic@0 { + compatible = "qcom,pm8994", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pm8994_gpios: gpios@c000 { + compatible = "qcom,pm8994-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, + <0 0xc1 0 IRQ_TYPE_NONE>, + <0 0xc2 0 IRQ_TYPE_NONE>, + <0 0xc3 0 IRQ_TYPE_NONE>, + <0 0xc4 0 IRQ_TYPE_NONE>, + <0 0xc5 0 IRQ_TYPE_NONE>, + <0 0xc6 0 IRQ_TYPE_NONE>, + <0 0xc7 0 IRQ_TYPE_NONE>, + <0 0xc8 0 IRQ_TYPE_NONE>, + <0 0xc9 0 IRQ_TYPE_NONE>, + <0 0xca 0 IRQ_TYPE_NONE>, + <0 0xcb 0 IRQ_TYPE_NONE>, + <0 0xcc 0 IRQ_TYPE_NONE>, + <0 0xcd 0 IRQ_TYPE_NONE>, + <0 0xce 0 IRQ_TYPE_NONE>, + <0 0xcf 0 IRQ_TYPE_NONE>, + <0 0xd0 0 IRQ_TYPE_NONE>, + <0 0xd1 0 IRQ_TYPE_NONE>, + <0 0xd2 0 IRQ_TYPE_NONE>, + <0 0xd3 0 IRQ_TYPE_NONE>, + <0 0xd4 0 IRQ_TYPE_NONE>, + <0 0xd5 0 IRQ_TYPE_NONE>; + }; + + pm8994_mpps: mpps@a000 { + compatible = "qcom,pm8994-mpp"; + reg = <0xa000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <0 0xa0 0 IRQ_TYPE_NONE>, + <0 0xa1 0 IRQ_TYPE_NONE>, + <0 0xa2 0 IRQ_TYPE_NONE>, + <0 0xa3 0 IRQ_TYPE_NONE>, + <0 0xa4 0 IRQ_TYPE_NONE>, + <0 0xa5 0 IRQ_TYPE_NONE>, + <0 0xa6 0 IRQ_TYPE_NONE>, + <0 0xa7 0 IRQ_TYPE_NONE>; + }; + }; + + pmic@1 { + compatible = "qcom,pm8994", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/pmi632.dtsi b/arch/arm/boot/dts/qcom/pmi632.dtsi new file mode 100644 index 000000000000..f97fe75e7fe0 --- /dev/null +++ b/arch/arm/boot/dts/qcom/pmi632.dtsi @@ -0,0 +1,737 @@ +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&spmi_bus { + qcom,pmi632@2 { + compatible = "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + + pmi632_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + pmi632_pon: qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + }; + + pmi632_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100 0x100>, <0x3700 0x100>; + reg-names = "adc5-usr-base", "adc5-cal-base"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-vdd-reference = <1875>; + #io-channel-cells = <1>; + io-channel-ranges; + qcom,pmic-revid = <&pmi632_revid>; + + /* Channel nodes */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vbat_sns { + reg = ; + label = "vbat_sns"; + qcom,pre-scaling = <1 3>; + }; + + usb_in_i_uv { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + usb_in_v_div_16 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; + + chg_temp { + reg = ; + label = "chg_temp"; + qcom,pre-scaling = <1 1>; + }; + + bat_therm { + reg = ; + label = "bat_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_therm_30k { + reg = ; + label = "bat_therm_30k"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_therm_400k { + reg = ; + label = "bat_therm_400k"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_id { + reg = ; + label = "bat_id"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + v_i_int_ext { + reg = ; + label = "v_i_int_vbat_vdata"; + qcom,pre-scaling = <1 1>; + }; + + v_i_parallel { + reg = ; + label = "v_i_parallel_vbat_vdata"; + qcom,pre-scaling = <1 1>; + }; + + }; + + pmi632_adc_tm: adc_tm@3500 { + compatible = "qcom,adc-tm5"; + reg = <0x3500 0x100>; + interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "thr-int-en"; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + }; + + pmi632_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + pmi632_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0x800>; + interrupts = <0x2 0xc0 0 IRQ_TYPE_NONE>, + <0x2 0xc1 0 IRQ_TYPE_NONE>, + <0x2 0xc2 0 IRQ_TYPE_NONE>, + <0x2 0xc3 0 IRQ_TYPE_NONE>, + <0x2 0xc4 0 IRQ_TYPE_NONE>, + <0x2 0xc5 0 IRQ_TYPE_NONE>, + <0x2 0xc6 0 IRQ_TYPE_NONE>, + <0x2 0xc7 0 IRQ_TYPE_NONE>; + interrupt-names = "pmi632_gpio1", "pmi632_gpio2", + "pmi632_gpio3", "pmi632_gpio4", + "pmi632_gpio5", "pmi632_gpio6", + "pmi632_gpio7", "pmi632_gpio8"; + gpio-controller; + #gpio-cells = <2>; + }; + + pmi632_charger: qcom,qpnp-smb5 { + compatible = "qcom,qpnp-smb5"; + #address-cells = <1>; + #size-cells = <1>; + #cooling-cells = <2>; + + qcom,pmic-revid = <&pmi632_revid>; + io-channels = <&pmi632_vadc ADC_USB_IN_V_16>, + <&pmi632_vadc ADC_USB_IN_I>, + <&pmi632_vadc ADC_CHG_TEMP>, + <&pmi632_vadc ADC_DIE_TEMP>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp"; + + qcom,chgr@1000 { + reg = <0x1000 0x100>; + interrupts = + <0x2 0x10 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x4 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x10 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "chgr-error", + "chg-state-change", + "step-chg-state-change", + "step-chg-soc-update-fail", + "step-chg-soc-update-req", + "fg-fvcal-qualified", + "vph-alarm", + "vph-drop-prechg"; + }; + + qcom,dcdc@1100 { + reg = <0x1100 0x100>; + interrupts = + <0x2 0x11 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x11 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x11 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x11 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x11 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x11 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "otg-fail", + "otg-oc-disable-sw", + "otg-oc-hiccup", + "bsm-active", + "high-duty-cycle", + "input-current-limiting", + "concurrent-mode-disable", + "switcher-power-ok"; + }; + + qcom,batif@1200 { + reg = <0x1200 0x100>; + interrupts = + <0x2 0x12 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x12 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x6 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x12 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "bat-temp", + "all-chnl-conv-done", + "bat-ov", + "bat-low", + "bat-therm-or-id-missing", + "bat-terminal-missing", + "buck-oc", + "vph-ov"; + }; + + qcom,usb@1300 { + reg = <0x1300 0x100>; + interrupts = + <0x2 0x13 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x13 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x13 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "usbin-collapse", + "usbin-vashdn", + "usbin-uv", + "usbin-ov", + "usbin-plugin", + "usbin-revi-change", + "usbin-src-change", + "usbin-icl-change"; + }; + + qcom,typec@1500 { + reg = <0x1500 0x100>; + interrupts = + <0x2 0x15 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x15 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x15 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x15 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x15 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "typec-or-rid-detect-change", + "typec-vpd-detect", + "typec-cc-state-change", + "typec-vconn-oc", + "typec-vbus-change", + "typec-attach-detach", + "typec-legacy-cable-detect", + "typec-try-snk-src-detect"; + }; + + qcom,misc@1600 { + reg = <0x1600 0x100>; + interrupts = + <0x2 0x16 0x0 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x16 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0x16 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "wdog-snarl", + "wdog-bark", + "aicl-fail", + "aicl-done", + "smb-en", + "imp-trigger", + "temp-change", + "temp-change-smb"; + }; + + qcom,schgm-flash@a600 { + reg = <0xa600 0x100>; + interrupts = + <0x2 0xa6 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0xa6 0x5 IRQ_TYPE_EDGE_RISING>, + <0x2 0xa6 0x6 IRQ_TYPE_EDGE_RISING>, + <0x2 0xa6 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "flash-state-change", + "ilim1-s1", + "ilim2-s2", + "vreg-ok"; + }; + }; + + pmi632_qg: qpnp,qg { + compatible = "qcom,qpnp-qg"; + #address-cells = <1>; + #size-cells = <1>; + + qcom,pmic-revid = <&pmi632_revid>; + io-channels = <&pmi632_vadc ADC_BAT_THERM_PU2>, + <&pmi632_vadc ADC_BAT_ID_PU2>; + io-channel-names = "batt-therm", + "batt-id"; + + qcom,qgauge@4800 { + status = "okay"; + reg = <0x4800 0x100>; + interrupts = + <0x2 0x48 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x48 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x48 0x2 IRQ_TYPE_EDGE_RISING>, + <0x2 0x48 0x3 IRQ_TYPE_EDGE_RISING>, + <0x2 0x48 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "qg-batt-missing", + "qg-vbat-low", + "qg-vbat-empty", + "qg-fifo-done", + "qg-good-ocv"; + }; + + qcom,qg-sdam@b100 { + status = "okay"; + reg = <0xb100 0x100>; + }; + }; + + pmi632_pbs_client3: qcom,pbs@7400 { + compatible = "qcom,qpnp-pbs"; + reg = <0x7400 0x100>; + }; + + pmi632_sdam7: qcom,sdam@b600 { + compatible = "qcom,spmi-sdam"; + reg = <0xb600 0x100>; + }; + + bcl_sensor: bcl@3d00 { + compatible = "qcom,bcl-v5"; + reg = <0x3d00 0x100>; + interrupts = <0x2 0x3d 0x0 IRQ_TYPE_NONE>, + <0x2 0x3d 0x1 IRQ_TYPE_NONE>, + <0x2 0x3d 0x0 IRQ_TYPE_NONE>, + <0x2 0x3d 0x1 IRQ_TYPE_NONE>, + <0x2 0x3d 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-ibat-lvl0", + "bcl-ibat-lvl1", + "bcl-vbat-lvl0", + "bcl-vbat-lvl1", + "bcl-vbat-lvl2"; + qcom,ibat-use-qg-adc-5a; + #thermal-sensor-cells = <1>; + }; + + bcl_soc: bcl-soc { + compatible = "qcom,msm-bcl-soc"; + #thermal-sensor-cells = <0>; + }; + }; + + pmi632_3: qcom,pmi632@3 { + compatible ="qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + + pmi632_vib: qcom,vibrator@5700 { + compatible = "qcom,qpnp-vibrator-ldo"; + reg = <0x5700 0x100>; + qcom,vib-ldo-volt-uv = <3000000>; + qcom,disable-overdrive; + }; + + pmi632_pwm: qcom,pwms@b300 { + compatible = "qcom,pwm-lpg"; + reg = <0xb300 0x500>; + reg-names = "lpg-base"; + #pwm-cells = <2>; + qcom,num-lpg-channels = <5>; + nvmem-names = "ppg_sdam"; + nvmem = <&pmi632_sdam7>; + qcom,pbs-client = <&pmi632_pbs_client3>; + qcom,lut-sdam-base = <0x80>; + qcom,lut-patterns = <0 0 0 14 28 42 56 70 84 100 + 100 84 70 56 42 28 14 0 0 0>; + lpg@1 { + qcom,lpg-chan-id = <1>; + qcom,ramp-step-ms = <200>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <19>; + qcom,ramp-pattern-repeat; + qcom,lpg-sdam-base = <0x48>; + }; + lpg@2 { + qcom,lpg-chan-id = <2>; + qcom,ramp-step-ms = <200>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <19>; + qcom,ramp-pattern-repeat; + qcom,lpg-sdam-base = <0x56>; + }; + lpg@3 { + qcom,lpg-chan-id = <3>; + qcom,ramp-step-ms = <200>; + qcom,ramp-low-index = <0>; + qcom,ramp-high-index = <19>; + qcom,ramp-pattern-repeat; + qcom,lpg-sdam-base = <0x64>; + }; + }; + + pmi632_rgb: qcom,leds@d000 { + compatible = "qcom,tri-led"; + reg = <0xd000 0x100>; + red { + label = "red"; + pwms = <&pmi632_pwm 0 1000000>; + led-sources = <0>; + linux,default-trigger = "timer"; + }; + green { + label = "green"; + pwms = <&pmi632_pwm 1 1000000>; + led-sources = <1>; + linux,default-trigger = "timer"; + }; + blue { + label = "blue"; + pwms = <&pmi632_pwm 2 1000000>; + led-sources = <2>; + linux,default-trigger = "timer"; + }; + }; + + pmi632_lcdb: qpnp-lcdb@ec00 { + compatible = "qcom,qpnp-lcdb-regulator"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xec00 0x100>; + interrupts = <0x3 0xec 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "sc-irq"; + + qcom,pmic-revid = <&pmi632_revid>; + qcom,voltage-step-ramp; + + lcdb_ldo_vreg: ldo { + label = "ldo"; + regulator-name = "lcdb_ldo"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + }; + + lcdb_ncp_vreg: ncp { + label = "ncp"; + regulator-name = "lcdb_ncp"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + }; + + lcdb_bst_vreg: bst { + label = "bst"; + regulator-name = "lcdb_bst"; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <6275000>; + }; + }; + + flash_led: qcom,leds@d300 { + compatible = "qcom,qpnp-flash-led-v2"; + status = "okay"; + reg = <0xd300 0x100>; + label = "flash"; + interrupts = <0x3 0xd3 0x0 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd3 0x3 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd3 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "led-fault-irq", + "all-ramp-down-done-irq", + "all-ramp-up-done-irq"; + qcom,short-circuit-det; + qcom,open-circuit-det; + qcom,vph-droop-det; + qcom,thermal-derate-en; + qcom,thermal-derate-current = <200 500 1000>; + qcom,isc-delay = <192>; + qcom,pmic-revid = <&pmi632_revid>; + + pmi632_flash0: qcom,flash_0 { + label = "flash"; + qcom,led-name = "led:flash_0"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash0_trigger"; + qcom,id = <0>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <400>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi632_flash1: qcom,flash_1 { + label = "flash"; + qcom,led-name = "led:flash_1"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash1_trigger"; + qcom,id = <1>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <400>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi632_torch0: qcom,torch_0 { + label = "torch"; + qcom,led-name = "led:torch_0"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch0_trigger"; + qcom,id = <0>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <400>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi632_torch1: qcom,torch_1 { + label = "torch"; + qcom,led-name = "led:torch_1"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch1_trigger"; + qcom,id = <1>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <400>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmi632_switch0: qcom,led_switch_0 { + label = "switch"; + qcom,led-name = "led:switch_0"; + qcom,led-mask = <3>; + qcom,default-led-trigger = "switch0_trigger"; + }; + + pmi632_switch1: qcom,led_switch_1 { + label = "switch"; + qcom,led-name = "led:switch_1"; + qcom,led-mask = <2>; + qcom,default-led-trigger = "switch1_trigger"; + }; + + }; + + }; +}; + +&thermal_zones { + pmi632_temp_alarm: pmi632-tz { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pmi632_tz>; + wake-capable-sensor; + + trips { + pmi632_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + pmi632_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + pmi632-ibat-lvl0 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&bcl_sensor 0>; + wake-capable-sensor; + + trips { + pmi632_ibat_lvl0: ibat-lvl0 { + temperature = <4000>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pmi632-ibat-lvl1 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&bcl_sensor 1>; + wake-capable-sensor; + + trips { + pmi632_ibat_lvl1: ibat-lvl1 { + temperature = <4200>; + hysteresis = <200>; + type = "passive"; + }; + }; + }; + + pmi632-vbat-lvl0 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&bcl_sensor 2>; + wake-capable-sensor; + tracks-low; + + trips { + pmi632_vbat_lvl0: vbat-lvl0 { + temperature = <3000>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + + pmi632-vbat-lvl1 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&bcl_sensor 3>; + wake-capable-sensor; + tracks-low; + + trips { + pmi632_vbat_lvl1: vbat-lvl1 { + temperature = <2800>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + + pmi632-vbat-lvl2 { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&bcl_sensor 4>; + wake-capable-sensor; + tracks-low; + + trips { + pmi632_vbat_lvl2: vbat-lvl1 { + temperature = <2600>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + + soc { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&bcl_soc>; + wake-capable-sensor; + tracks-low; + + trips { + pmi632_low_soc: low-soc { + temperature = <10>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/pmi8994.dtsi b/arch/arm/boot/dts/qcom/pmi8994.dtsi new file mode 100644 index 000000000000..dae1cdc23f54 --- /dev/null +++ b/arch/arm/boot/dts/qcom/pmi8994.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include + +&spmi_bus { + + pmic@2 { + compatible = "qcom,pmi8994", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmi8994_gpios: gpios@c000 { + compatible = "qcom,pmi8994-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <2 0xc0 0 IRQ_TYPE_NONE>, + <2 0xc1 0 IRQ_TYPE_NONE>, + <2 0xc2 0 IRQ_TYPE_NONE>, + <2 0xc3 0 IRQ_TYPE_NONE>, + <2 0xc4 0 IRQ_TYPE_NONE>, + <2 0xc5 0 IRQ_TYPE_NONE>, + <2 0xc6 0 IRQ_TYPE_NONE>, + <2 0xc7 0 IRQ_TYPE_NONE>, + <2 0xc8 0 IRQ_TYPE_NONE>, + <2 0xc9 0 IRQ_TYPE_NONE>; + }; + }; + + pmic@3 { + compatible = "qcom,pmi8994", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/pms405-rpm-regulator.dtsi b/arch/arm/boot/dts/qcom/pms405-rpm-regulator.dtsi new file mode 100644 index 000000000000..d3227fd03347 --- /dev/null +++ b/arch/arm/boot/dts/qcom/pms405-rpm-regulator.dtsi @@ -0,0 +1,317 @@ +/* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&rpm_bus { + /* VDD_MX/CX supply */ + rpm-regulator-smpa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwmx"; + qcom,resource-id = <0>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_s1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + /* VDD_LPI_CX supply */ + rpm-regulator-smpa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwlc"; + qcom,resource-id = <0>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_s2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_s3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_s4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <5>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_s5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + /* VDD_LPI_MX supply */ + rpm-regulator-ldoa9 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwlm"; + qcom,resource-id = <0>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa11 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <11>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l11 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l11"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l12 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l12"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa13 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <13>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic4-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l13 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l13"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/pms405.dtsi b/arch/arm/boot/dts/qcom/pms405.dtsi new file mode 100644 index 000000000000..09d1b699f689 --- /dev/null +++ b/arch/arm/boot/dts/qcom/pms405.dtsi @@ -0,0 +1,207 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&spmi_bus { + qcom,pms405@0 { + compatible ="qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + + qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + pms405_vadc: vadc@3100 { + compatible = "qcom,spmi-adc-rev2"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-vdd-reference = <1875>; + #io-channel-cells = <1>; + io-channel-ranges; + + ref_gnd { + label = "ref_gnd"; + reg = ; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + label = "vref_1p25"; + reg = ; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + label = "die_temp"; + reg = ; + qcom,pre-scaling = <1 1>; + }; + + vph_pwr { + label = "vph_pwr"; + reg = ; + qcom,pre-scaling = <1 3>; + }; + + xo_therm { + label = "xo_therm"; + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm1 { + label = "pa_therm1"; + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm3 { + label = "pa_therm3"; + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + }; + + pms405_adc_tm_iio: adc_tm@3500 { + compatible = "qcom,adc-tm5-iio"; + reg = <0x3500 0x100>; + #thermal-sensor-cells = <1>; + io-channels = <&pms405_vadc ADC_XO_THERM_PU2>, + <&pms405_vadc ADC_AMUX_THM1_PU2>, + <&pms405_vadc ADC_AMUX_THM3_PU2>; + + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm3 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + }; + + pms405_pon: qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr"; + qcom,pon-dbc-delay = <15625>; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = <0>; + qcom,pull-up; + linux,code = ; + }; + }; + + pms405_misc: qcom,misc@900 { + compatible = "qcom,qpnp-misc"; + reg = <0x900 0x100>; + }; + + pms405_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00 0x100>; + #clock-cells = <1>; + qcom,num-clkdivs = <1>; + clock-output-names = "pms405_div_clk1"; + clocks = <&clock_rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + assigned-clocks = <&pms405_clkdiv 1>; + assigned-clock-rates = <9600000>; + }; + + /* QCS405 + PMS405 GPIO configuration */ + pms405_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0xc00>; + interrupts = <0x0 0xc1 0 IRQ_TYPE_NONE>, + <0x0 0xc2 0 IRQ_TYPE_NONE>, + <0x0 0xc3 0 IRQ_TYPE_NONE>, + <0x0 0xc4 0 IRQ_TYPE_NONE>, + <0x0 0xc5 0 IRQ_TYPE_NONE>, + <0x0 0xc6 0 IRQ_TYPE_NONE>, + <0x0 0xc7 0 IRQ_TYPE_NONE>, + <0x0 0xca 0 IRQ_TYPE_NONE>, + <0x0 0xcb 0 IRQ_TYPE_NONE>; + interrupt-names = "pms405_gpio2", "pms405_gpio3", + "pms405_gpio4", "pms405_gpio5", + "pms405_gpio6", "pms405_gpio7", + "pms405_gpio8", "pms405_gpio11", + "pms405_gpio12"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + qcom,gpios-disallowed = <1 9 10>; + }; + + qcom,pms405_rtc { + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pms405_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + + qcom,pms405_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + }; + }; + + qcom,pms405@1 { + compatible = "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + + pms405_pwm: qcom,pwms@bc00 { + compatible = "qcom,pwm-lpg"; + reg = <0xbc00 0x200>; + reg-names = "lpg-base"; + #pwm-cells = <2>; + qcom,num-lpg-channels = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/pmxprairie.dtsi b/arch/arm/boot/dts/qcom/pmxprairie.dtsi new file mode 100644 index 000000000000..06a3e3256bd4 --- /dev/null +++ b/arch/arm/boot/dts/qcom/pmxprairie.dtsi @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pmxprairie@8 { + compatible = "qcom,spmi-pmic"; + reg = <0x8 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x8 0x8 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x8 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "kpdpwr", "resin"; + qcom,pon-dbc-delay = <15625>; + qcom,kpdpwr-sw-debounce; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = ; + linux,code = ; + qcom,pull-up; + }; + + qcom,pon_2 { + qcom,pon-type = ; + linux,code = ; + qcom,pull-up; + }; + }; + + pmxprairie_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x8 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pmxprairie_vadc ADC_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + pmxprairie_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00 0x100>; + #clock-cells = <1>; + qcom,num-clkdivs = <1>; + clock-output-names = "pmxprairie_div_clk1"; + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pmxprairie_rtc: qcom,rtc@6000 { + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pmxprairie_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + + qcom,pmxprairie_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = + <0x8 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + }; + + pmxprairie_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0xb00>; + interrupts = <0x8 0xc0 0x0 IRQ_TYPE_NONE>, + <0x8 0xc1 0x0 IRQ_TYPE_NONE>, + <0x8 0xc3 0x0 IRQ_TYPE_NONE>, + <0x8 0xc4 0x0 IRQ_TYPE_NONE>, + <0x8 0xc5 0x0 IRQ_TYPE_NONE>, + <0x8 0xc7 0x0 IRQ_TYPE_NONE>, + <0x8 0xc8 0x0 IRQ_TYPE_NONE>, + <0x8 0xc9 0x0 IRQ_TYPE_NONE>; + interrupt-names = "pmxprairie_gpio1", + "pmxprairie_gpio2", + "pmxprairie_gpio4", + "pmxprairie_gpio5", + "pmxprairie_gpio6", + "pmxprairie_gpio8", + "pmxprairie_gpio9", + "pmxprairie_gpio10"; + gpio-controller; + #gpio-cells = <2>; + qcom,gpios-disallowed = <3 7 11>; + }; + + pmxprairie_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x8 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-vdd-reference = <1875>; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel node */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + + pmxprairie_adc_tm_iio: adc_tm@3500 { + compatible = "qcom,adc-tm5-iio"; + reg = <0x3500 0x100>; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + io-channels = <&pmxprairie_vadc ADC_XO_THERM_PU2>, + <&pmxprairie_vadc ADC_AMUX_THM1_PU2>, + <&pmxprairie_vadc ADC_AMUX_THM2_PU2>, + <&pmxprairie_vadc ADC_AMUX_THM3_PU2>, + <&pmxprairie_vadc ADC_GPIO1_PU2>; + }; + }; + + qcom,pmxprairie@9 { + compatible ="qcom,spmi-pmic"; + reg = <0x9 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + }; +}; + +&thermal_zones { + pmxprairie_temp_alarm: pmxprairie_tz { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pmxprairie_tz>; + + trips { + pmxprairie_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pmxprairie_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + pmxprairie_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; +}; + +&soc { + vbus_detect: qcom,pmd-vbus-det { + compatible = "qcom,pmd-vbus-det"; + interrupt-parent = <&spmi_bus>; + interrupts = <0x8 0x0d 0x0 IRQ_TYPE_NONE>; + interrupt-names = "usb_vbus"; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs401-iot-sku1.dts b/arch/arm/boot/dts/qcom/qcs401-iot-sku1.dts new file mode 100644 index 000000000000..4c58e531a81d --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs401-iot-sku1.dts @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "qcs401.dtsi" +#include "qcs405-audio-overlay.dtsi" +#include "qcs405-circular-pca9956.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS401 EVB2 1000 IOT"; + compatible = "qcom,qcs401-iot", "qcom,qcs401", "qcom,iot"; + qcom,board-id = <0x010020 0x2>; + + cpus { + /delete-node/ cpu@102; + /delete-node/ cpu@103; + + cpu-map { + cluster0 { + /delete-node/ core2; + /delete-node/ core3; + }; + }; + }; +}; + +&soc { + cpuss_dump { + /delete-node/ qcom,l1_i_cache102; + /delete-node/ qcom,l1_i_cache103; + /delete-node/ qcom,l1_d_cache102; + /delete-node/ qcom,l1_d_cache103; + }; + + qcom,spm@b012000 { + qcom,cpu-vctl-list = <&CPU0 &CPU1>; + }; + + qcom,lpm-levels { + qcom,pm-cluster@0{ + qcom,pm-cpu { + qcom,cpu = <&CPU0 &CPU1>; + }; + }; + }; + + /delete-node/ cti@61ba000; + /delete-node/ cti@61bb000; + /delete-node/ etm@61be000; + /delete-node/ etm@61bf000; + funnel@61a1000 { + ports { + /delete-node/ port@3; + /delete-node/ port@4; + }; + }; +}; + +&thermal_zones { + cpuss-max-step { + cooling-maps { + /delete-node/ cpu2_cdev; + /delete-node/ cpu3_cdev; + }; + }; + + /delete-node/ cpuss-2-step; + /delete-node/ cpuss-3-step; +}; + diff --git a/arch/arm/boot/dts/qcom/qcs401.dtsi b/arch/arm/boot/dts/qcom/qcs401.dtsi new file mode 100644 index 000000000000..abf0c5893a2b --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs401.dtsi @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "qcs405.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS401"; + qcom,msm-name = "QCS401"; + qcom,msm-id = <372 0x0>; +}; + +&soc { + /delete-node/ qcom,msm-cpufreq; + + msm_cpufreq: qcom,msm-cpufreq { + compatible = "qcom,msm-cpufreq"; + clock-names = "cpu0_clk"; + clocks = <&clock_cpu APCS_MUX_CLK>; + + qcom,cpufreq-table = + < 1094400 >, + < 1248000 >, + < 1401600 >; + }; + + /delete-node/ qcom,cpu0-computemon; + + cpu0_computemon: qcom,cpu0-computemon { + compatible = "qcom,arm-cpu-mon"; + qcom,cpulist = <&CPU0 &CPU1>; + qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1094400 MHZ_TO_MBPS( 297, 8) >, + < 1248000 MHZ_TO_MBPS( 597, 8) >, + < 1401600 MHZ_TO_MBPS( 710, 8) >; + }; +}; + diff --git a/arch/arm/boot/dts/qcom/qcs403-ext-pll-audio.dtsi b/arch/arm/boot/dts/qcom/qcs403-ext-pll-audio.dtsi new file mode 100644 index 000000000000..a8a6a6bea25e --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs403-ext-pll-audio.dtsi @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "qcs405-wsa-audio-overlay.dtsi" + +&soc { + clock_audio_ext_pll: ext_pll_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + #clock-cells = <1>; + }; +}; + +&wcd9335 { + qcom,cdc-ext-clk-rate = <24576000>; + qcom,cdc-mclk-clk-rate = <12288000>; + clock-names = "wcd_clk"; + clocks = <&clock_audio_ext_pll 0>; +}; diff --git a/arch/arm/boot/dts/qcom/qcs403-iot-sku1.dts b/arch/arm/boot/dts/qcom/qcs403-iot-sku1.dts new file mode 100644 index 000000000000..bcf65cf5aa3e --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs403-iot-sku1.dts @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "qcs403.dtsi" +#include "qcs405-audio-overlay.dtsi" +#include "qcs405-circular-pca9956.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS403 EVB2 1000 IOT"; + compatible = "qcom,qcs403-iot", "qcom,qcs403", "qcom,iot"; + qcom,board-id = <0x010020 0x3>; + + cpus { + /delete-node/ cpu@102; + /delete-node/ cpu@103; + + cpu-map { + cluster0 { + /delete-node/ core2; + /delete-node/ core3; + }; + }; + }; +}; + +&soc { + cpuss_dump { + /delete-node/ qcom,l1_i_cache102; + /delete-node/ qcom,l1_i_cache103; + /delete-node/ qcom,l1_d_cache102; + /delete-node/ qcom,l1_d_cache103; + }; + + qcom,spm@b012000 { + qcom,cpu-vctl-list = <&CPU0 &CPU1>; + }; + + qcom,lpm-levels { + qcom,pm-cluster@0{ + qcom,pm-cpu { + qcom,cpu = <&CPU0 &CPU1>; + }; + }; + }; + + /delete-node/ cti@61ba000; + /delete-node/ cti@61bb000; + /delete-node/ etm@61be000; + /delete-node/ etm@61bf000; + funnel@61a1000 { + ports { + /delete-node/ port@3; + /delete-node/ port@4; + }; + }; +}; + +&thermal_zones { + cpuss-max-step { + cooling-maps { + /delete-node/ cpu2_cdev; + /delete-node/ cpu3_cdev; + }; + }; + + /delete-node/ cpuss-2-step; + /delete-node/ cpuss-3-step; +}; + +&qnand_1 { + status = "ok"; +}; + +&qseecom_mem { + size = <0 0x400000>; +}; diff --git a/arch/arm/boot/dts/qcom/qcs403-iot-sku2.dts b/arch/arm/boot/dts/qcom/qcs403-iot-sku2.dts new file mode 100644 index 000000000000..4220f8e48ef5 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs403-iot-sku2.dts @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "qcs403.dtsi" +#include "qcs405-audio-overlay.dtsi" +#include "qcs405-circular-pca9956.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS403 RCM IOT"; + compatible = "qcom,qcs403-iot", "qcom,qcs403", "qcom,iot"; + qcom,board-id = <0x010015 0x0>; + + cpus { + /delete-node/ cpu@102; + /delete-node/ cpu@103; + + cpu-map { + cluster0 { + /delete-node/ core2; + /delete-node/ core3; + }; + }; + }; +}; + +&soc { + cpuss_dump { + /delete-node/ qcom,l1_i_cache102; + /delete-node/ qcom,l1_i_cache103; + /delete-node/ qcom,l1_d_cache102; + /delete-node/ qcom,l1_d_cache103; + }; + + qcom,spm@b012000 { + qcom,cpu-vctl-list = <&CPU0 &CPU1>; + }; + + qcom,lpm-levels { + qcom,pm-cluster@0{ + qcom,pm-cpu { + qcom,cpu = <&CPU0 &CPU1>; + }; + }; + }; + + /delete-node/ cti@61ba000; + /delete-node/ cti@61bb000; + /delete-node/ etm@61be000; + /delete-node/ etm@61bf000; + funnel@61a1000 { + ports { + /delete-node/ port@3; + /delete-node/ port@4; + }; + }; +}; + +&thermal_zones { + cpuss-max-step { + cooling-maps { + /delete-node/ cpu2_cdev; + /delete-node/ cpu3_cdev; + }; + }; + + /delete-node/ cpuss-2-step; + /delete-node/ cpuss-3-step; +}; + +#include "qcs405-mdss-panels.dtsi" + +&mdss_mdp { + qcom,mdss-pref-prim-intf = "dsi"; +}; + +&mdss_dsi { + hw-config = "single_dsi"; +}; + +&mdss_dsi0 { + qcom,dsi-pref-prim-pan = <&dsi_hx8394d_720_vid>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; + pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 41 0>; + qcom,platform-reset-gpio = <&tlmm 39 0>; + qcom,platform-bklight-en-gpio = <&tlmm 48 0>; +}; + +&dsi_hx8394d_720_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_tlmm_gpio"; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&usb3 { + status = "disabled"; +}; + +&usb_ss_phy { + status = "ok"; + qcom,keep-powerdown; +}; + +&usb2_phy1 { + status = "disabled"; +}; + +&qnand_1 { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/qcs403-iot-sku3.dts b/arch/arm/boot/dts/qcom/qcs403-iot-sku3.dts new file mode 100644 index 000000000000..637d94ce2e50 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs403-iot-sku3.dts @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "qcs403.dtsi" +#include "qcs405-wsa-audio-overlay.dtsi" +#include "qcs405-circular-pca9956.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS403 SSRD IOT"; + compatible = "qcom,qcs403-iot", "qcom,qcs403", "qcom,iot"; + qcom,board-id = <0x010020 0x4>; + + cpus { + /delete-node/ cpu@102; + /delete-node/ cpu@103; + + cpu-map { + cluster0 { + /delete-node/ core2; + /delete-node/ core3; + }; + }; + }; +}; + +&soc { + cpuss_dump { + /delete-node/ qcom,l1_i_cache102; + /delete-node/ qcom,l1_i_cache103; + /delete-node/ qcom,l1_d_cache102; + /delete-node/ qcom,l1_d_cache103; + }; + + qcom,spm@b012000 { + qcom,cpu-vctl-list = <&CPU0 &CPU1>; + }; + + qcom,lpm-levels { + qcom,pm-cluster@0{ + qcom,pm-cpu { + qcom,cpu = <&CPU0 &CPU1>; + }; + }; + }; + + /delete-node/ cti@61ba000; + /delete-node/ cti@61bb000; + /delete-node/ etm@61be000; + /delete-node/ etm@61bf000; + funnel@61a1000 { + ports { + /delete-node/ port@3; + /delete-node/ port@4; + }; + }; + + spi@78b5000 { + status = "ok"; + spi@0 { + compatible = "qcom,spi-msm-codec-slave"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; + + gpio_keys { + vol_mute { + gpios = <&tlmm 19 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&thermal_zones { + cpuss-max-step { + cooling-maps { + /delete-node/ cpu2_cdev; + /delete-node/ cpu3_cdev; + }; + }; + + /delete-node/ cpuss-2-step; + /delete-node/ cpuss-3-step; +}; + +&qnand_1 { + status = "ok"; +}; + +&soc { + usb2_extcon: usb2_extcon { + compatible = "linux,extcon-usb-gpio"; + vbus-gpio = <&tlmm 27 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&usb2_ssrd_det_default>; + }; +}; + +&usb2s { + extcon = <&usb2_extcon>; +}; + +&usb3 { + status = "disabled"; +}; + +&usb_ss_phy { + status = "ok"; + qcom,keep-powerdown; +}; + +&usb2_phy1 { + status = "disabled"; +}; + +&tlmm { + evb_tlmm_gpio_key{ + tlmm_gpio_key_active: tlmm_gpio_key_active { + mux { + pins = "gpio19","gpio52","gpio54","gpio115"; + }; + + config { + pins = "gpio19","gpio52","gpio54","gpio115"; + }; + }; + + tlmm_gpio_key_suspend: tlmm_gpio_key_suspend { + mux { + pins = "gpio19","gpio52","gpio54","gpio115"; + }; + + config { + pins = "gpio19","gpio52","gpio54","gpio115"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs403-iot-sku4.dts b/arch/arm/boot/dts/qcom/qcs403-iot-sku4.dts new file mode 100644 index 000000000000..77ac0f29bb32 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs403-iot-sku4.dts @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "qcs403.dtsi" +#include "qcs405-circular-pca9956.dtsi" +#include "qcs403-ext-pll-audio.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS403 SSRD IOT AUDIO PLL"; + compatible = "qcom,qcs403-iot", "qcom,qcs403", "qcom,iot"; + qcom,board-id = <0x010020 0x5>; + + cpus { + /delete-node/ cpu@102; + /delete-node/ cpu@103; + + cpu-map { + cluster0 { + /delete-node/ core2; + /delete-node/ core3; + }; + }; + }; +}; + +&soc { + cpuss_dump { + /delete-node/ qcom,l1_i_cache102; + /delete-node/ qcom,l1_i_cache103; + /delete-node/ qcom,l1_d_cache102; + /delete-node/ qcom,l1_d_cache103; + }; + + qcom,spm@b012000 { + qcom,cpu-vctl-list = <&CPU0 &CPU1>; + }; + + qcom,lpm-levels { + qcom,pm-cluster@0{ + qcom,pm-cpu { + qcom,cpu = <&CPU0 &CPU1>; + }; + }; + }; + + /delete-node/ cti@61ba000; + /delete-node/ cti@61bb000; + /delete-node/ etm@61be000; + /delete-node/ etm@61bf000; + funnel@61a1000 { + ports { + /delete-node/ port@3; + /delete-node/ port@4; + }; + }; + + gpio_keys { + vol_mute { + gpios = <&tlmm 19 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&thermal_zones { + cpuss-max-step { + cooling-maps { + /delete-node/ cpu2_cdev; + /delete-node/ cpu3_cdev; + }; + }; + + /delete-node/ cpuss-2-step; + /delete-node/ cpuss-3-step; +}; + +&qnand_1 { + status = "ok"; +}; + +&usb3 { + status = "disabled"; +}; + +&usb_ss_phy { + status = "disabled"; +}; + +&usb2_phy1 { + status = "disabled"; +}; + +&tlmm { + evb_tlmm_gpio_key{ + tlmm_gpio_key_active: tlmm_gpio_key_active { + mux { + pins = "gpio19","gpio52","gpio54","gpio115"; + }; + + config { + pins = "gpio19","gpio52","gpio54","gpio115"; + }; + }; + + tlmm_gpio_key_suspend: tlmm_gpio_key_suspend { + mux { + pins = "gpio19","gpio52","gpio54","gpio115"; + }; + + config { + pins = "gpio19","gpio52","gpio54","gpio115"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs403.dtsi b/arch/arm/boot/dts/qcom/qcs403.dtsi new file mode 100644 index 000000000000..c5058cbaec53 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs403.dtsi @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "qcs405.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS403"; + qcom,msm-name = "QCS403"; + qcom,msm-id = <373 0x0>; +}; + +&soc { + /delete-node/ qcom,msm-cpufreq; + + msm_cpufreq: qcom,msm-cpufreq { + compatible = "qcom,msm-cpufreq"; + clock-names = "cpu0_clk"; + clocks = <&clock_cpu APCS_MUX_CLK>; + + qcom,cpufreq-table = + < 1094400 >, + < 1248000 >, + < 1401600 >; + }; + + /delete-node/ qcom,cpu0-computemon; + + cpu0_computemon: qcom,cpu0-computemon { + compatible = "qcom,arm-cpu-mon"; + qcom,cpulist = <&CPU0 &CPU1>; + qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1094400 MHZ_TO_MBPS( 297, 8) >, + < 1248000 MHZ_TO_MBPS( 597, 8) >, + < 1401600 MHZ_TO_MBPS( 710, 8) >; + }; +}; + +&adsp_fw_mem { + reg = <0x0 0x87400000 0x0 0x1200000>; +}; + +&reserved_mem { + linux,cma { + size = <0 0x400000>; + }; +}; + +&qcom_seecom { + /delete-property/ qcom,appsbl-qseecom-support; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-amic-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/qcs405-amic-audio-overlay.dtsi new file mode 100644 index 000000000000..9e23790bf6dd --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-amic-audio-overlay.dtsi @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "qcs405-tasha.dtsi" + +&q6core { + bolero: bolero-cdc { + compatible = "qcom,bolero-codec"; + clock-names = "lpass_core_hw_vote"; + clocks = <&lpass_core_hw_vote 0>; + }; +}; + +&qcs405_snd { + qcom,model = "qcs405-amic-snd-card"; + qcom,tasha-codec = <1>; + asoc-codec = <&stub_codec>, <&bolero>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec"; + qcom,audio-routing = + "lineout booster", "LINEOUT1", + "lineout booster", "LINEOUT2", + "LINEOUT1", "rx regulator", + "LINEOUT2", "rx regulator", + "AMIC3", "tx regulator", + "AMIC4", "tx regulator", + "AMIC3", "MIC BIAS3", + "AMIC4", "MIC BIAS4", + "MIC BIAS3", "Analog Mic3", + "MIC BIAS4", "Analog Mic4"; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/qcs405-audio-overlay.dtsi new file mode 100644 index 000000000000..721d31d3213f --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-audio-overlay.dtsi @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&q6core { + cdc_dmic01_gpios: cdc_dmic01_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>; + pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>; + qcom,lpi-gpios; + }; + + cdc_dmic23_gpios: cdc_dmic23_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>; + pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>; + qcom,lpi-gpios; + }; + + cdc_dmic45_gpios: cdc_dmic45_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>; + pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>; + qcom,lpi-gpios; + }; + + cdc_dmic67_gpios: cdc_dmic67_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic67_clk_active &cdc_dmic67_data_active>; + pinctrl-1 = <&cdc_dmic67_clk_sleep &cdc_dmic67_data_sleep>; + qcom,lpi-gpios; + }; +}; + +&q6core { + bolero: bolero-cdc { + compatible = "qcom,bolero-codec"; + clock-names = "lpass_core_hw_vote"; + clocks = <&lpass_core_hw_vote 0>; + qcom,num-macros = <1>; + }; +}; + +&qcs405_snd { + qcom,model = "qcs405-snd-card"; + qcom,va-bolero-codec = <1>; + qcom,tasha-codec = <1>; + asoc-codec = <&stub_codec>, <&bolero>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec"; + qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; + qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; + qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>; + qcom,cdc-dmic67-gpios = <&cdc_dmic67_gpios>; + qcom,audio-routing = + "RX_BIAS", "MCLK", + "lineout booster", "LINEOUT1", + "lineout booster", "LINEOUT2", + "LINEOUT1", "rx regulator", + "LINEOUT2", "rx regulator", + "AMIC3", "tx regulator", + "AMIC4", "tx regulator", + "AMIC3", "MIC BIAS3", + "AMIC4", "MIC BIAS4", + "MIC BIAS3", "Analog Mic3", + "MIC BIAS4", "Analog Mic4", + "VA DMIC0", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic0", + "VA DMIC1", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic1", + "VA DMIC2", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic2", + "VA DMIC3", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic3", + "VA DMIC4", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic4", + "VA DMIC5", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic5", + "VA DMIC6", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic6", + "VA DMIC7", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic7"; + pinctrl-names = "default"; + pinctrl-0 = <&spdifrx_opt_default + &sec_mi2s_sck_active &sec_mi2s_ws_active + &sec_mi2s_sd0_active &sec_mi2s_sd1_active + &sec_mi2s_sd2_active &sec_mi2s_sd3_active>; +}; + +#include "qcs405-tasha.dtsi" +#include "qcs405-va-bolero.dtsi" diff --git a/arch/arm/boot/dts/qcom/qcs405-audio.dtsi b/arch/arm/boot/dts/qcom/qcs405-audio.dtsi new file mode 100644 index 000000000000..7bc66665e401 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-audio.dtsi @@ -0,0 +1,193 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#include "msm-audio-lpass.dtsi" + +&msm_audio_ion { + iommus = <&apps_smmu 0x0801 0x0>; + qcom,smmu-sid-mask = /bits/ 64 <0xf>; + qcom,non-hyp-assign; +}; + +&soc { + qcom,avtimer@C10000C { + compatible = "qcom,avtimer"; + reg = <0x0C10000C 0x4>, + <0x0C100010 0x4>; + reg-names = "avtimer_lsb_addr", "avtimer_msb_addr"; + qcom,clk-div = <192>; + qcom,clk-mult = <10>; + }; + + audio_apr: qcom,msm-audio-apr { + compatible = "qcom,msm-audio-apr"; + q6core: q6core { + compatible = "qcom,q6core-audio"; + }; + }; +}; + +&q6core { + lpass_core_hw_vote: vote_lpass_core_hw { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + #clock-cells = <1>; + }; +}; + +#include "qcs405-lpi.dtsi" + +&i2c_3 { + status = "okay"; + qcom,clk-freq-out = <100000>; + + ep92a6_hdmi_64: ep92a6@64 { + status = "okay"; + compatible = "explore,ep92a6"; + reg = <0x64>; + pinctrl-names = "default"; + pinctrl-0 = <&ep_reset_n_active &ep_mute_active &ep_int_active>; + }; +}; + +&q6core { + qcs405_snd: sound { + compatible = "qcom,qcs405-asoc-snd"; + qcom,model = "qcs405-snd-card"; + qcom,mi2s-audio-intf = <1>; + qcom,auxpcm-audio-intf = <1>; + qcom,spdif-audio-intf = <1>; + qcom,wcn-btfm = <1>; + qcom,afe-rxtx-lb = <1>; + qcom,msm-mi2s-master = <1>, <0>, <1>, <1>, <1>, <1>; + + qcom,ep92-name = "ep92.3-0064"; + qcom,ep92-busnum = <3>; + qcom,ep92-reg = <0x64>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>, <&trans_loopback>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq", "msm-transcode-loopback"; + asoc-cpu = <&dai_dp>, <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, <&dai_mi2s4>, <&dai_mi2s5>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, + <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, + <&dai_quin_auxpcm>, + <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, + <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, + <&sb_4_rx>, <&sb_4_tx>, <&sb_5_rx>, <&sb_5_tx>, + <&sb_6_rx>, <&sb_7_rx>, <&sb_7_tx>, + <&sb_8_rx>, <&sb_8_tx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, + <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, + <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>, + <&wsa_cdc_dma_0_rx>, <&wsa_cdc_dma_0_tx>, + <&wsa_cdc_dma_1_rx>, <&wsa_cdc_dma_1_tx>, + <&wsa_cdc_dma_2_tx>, + <&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>, + <&dai_pri_spdif_rx>, <&dai_pri_spdif_tx>, + <&dai_sec_spdif_rx>, <&dai_sec_spdif_tx>, + <&sb_9_tx>, <&afe_loopback_tx>; + asoc-cpu-names = "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", + "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", + "msm-dai-q6-auxpcm.5", + "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", + "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", + "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", + "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", + "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", + "msm-dai-q6-dev.16394", "msm-dai-q6-dev.16395", + "msm-dai-q6-dev.16396", + "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", + "msm-dai-q6-dev.16400", "msm-dai-q6-dev.16401", + "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", + "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", + "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", + "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", + "msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36929", + "msm-dai-cdc-dma-dev.45056", + "msm-dai-cdc-dma-dev.45057", + "msm-dai-cdc-dma-dev.45058", + "msm-dai-cdc-dma-dev.45059", + "msm-dai-cdc-dma-dev.45061", + "msm-dai-cdc-dma-dev.45089", + "msm-dai-cdc-dma-dev.45091", + "msm-dai-q6-spdif.20480", "msm-dai-q6-spdif.20481", + "msm-dai-q6-spdif.20482", "msm-dai-q6-spdif.20483", + "msm-dai-q6-dev.16403", "msm-dai-q6-dev.24577"; + }; +}; + +&slim_aud { + status = "okay"; + msm_dai_slim { + status = "okay"; + compatible = "qcom,msm-dai-slim"; + elemental-addr = [ff ff ff fe 17 02]; + }; +}; + +&pms405_gpios { + tasha_mclk { + tasha_mclk_default: tasha_mclk_default{ + pins = "gpio8"; + function = "func2"; + qcom,drive-strength = <2>; + power-source = <0>; + bias-disable; + output-low; + }; + }; +}; + +&dai_mi2s1 { + qcom,msm-mi2s-rx-lines = <0>; + qcom,msm-mi2s-tx-lines = <15>; +}; + +&dai_mi2s4 { + qcom,msm-dai-is-island-supported = <1>; +}; + +&dai_quin_auxpcm { + qcom,msm-dai-is-island-supported = <1>; +}; + +&dai_quin_tdm_tx_0 { + qcom,msm-dai-is-island-supported = <1>; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-blsp.dtsi b/arch/arm/boot/dts/qcom/qcs405-blsp.dtsi new file mode 100644 index 000000000000..f58fc527b934 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-blsp.dtsi @@ -0,0 +1,526 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "qcs405-pinctrl.dtsi" + +/ { + aliases { + spi1 = &spi_1; + spi2 = &spi_2; + spi3 = &spi_3; + spi4 = &spi_4; + spi5 = &spi_5; + spi6 = &spi_6; + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + i2c5 = &i2c_5; + i2c6 = &i2c_6; + }; +}; + + +&soc { + + dma_blsp1: qcom,sps-dma@7884000{ /* BLSP1 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0x7884000 0x25000>; + interrupts = <0 238 0>; + qcom,summing-threshold = <0x10>; + }; + + dma_blsp2: qcom,sps-dma@7ac4000{ /* BLSP2 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0x7ac4000 0x17000>; + interrupts = <0 239 0>; + qcom,summing-threshold = <0x10>; + }; + + i2c_1: i2c@78b5000 { /* BLSP1 QUP1 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x78b5000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 95 0>; + dmas = <&dma_blsp1 8 64 0x20000020 0x20>, + <&dma_blsp1 9 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_1_active>; + pinctrl-1 = <&i2c_1_sleep>; + status = "disabled"; + }; + + i2c_2: i2c@78b6000 { /* BLSP1 QUP2 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x78b6000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 96 0>; + dmas = <&dma_blsp1 10 64 0x20000020 0x20>, + <&dma_blsp1 11 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_2_active>; + pinctrl-1 = <&i2c_2_sleep>; + status = "disabled"; + }; + + i2c_3: i2c@78b7000 { /* BLSP1 QUP3 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x78b7000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 97 0>; + dmas = <&dma_blsp1 12 64 0x20000020 0x20>, + <&dma_blsp1 13 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_3_sda_active>, <&i2c_3_scl_active>; + pinctrl-1 = <&i2c_3_sleep>; + status = "disabled"; + }; + + i2c_4: i2c@78b8000 { /* BLSP1 QUP4 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x78b8000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 98 0>; + dmas = <&dma_blsp1 14 64 0x20000020 0x20>, + <&dma_blsp1 15 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_4_active>; + pinctrl-1 = <&i2c_4_sleep>; + status = "disabled"; + }; + + i2c_5: i2c@78b9000 { /* BLSP2 QUP1 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x78b9000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 99 0>; + dmas = <&dma_blsp1 16 64 0x20000020 0x20>, + <&dma_blsp1 17 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_5_active>; + pinctrl-1 = <&i2c_5_sleep>; + status = "disabled"; + }; + + i2c_6: i2c@7af5000 { /* BLSP2 QUP1 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7af5000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 299 0>; + dmas = <&dma_blsp2 2 64 0x20000020 0x20>, + <&dma_blsp2 3 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <84>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, + <&clock_gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_6_active>; + pinctrl-1 = <&i2c_6_sleep>; + status = "disabled"; + }; + + spi_1: spi@78b5000 { /* BLSP1 QUP1 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x78b5000 0x600>, + <0x7884000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 95 0>, <0 238 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <8>; + qcom,bam-producer-pipe-index = <9>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_1_active>; + pinctrl-1 = <&spi_1_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_2: spi@78b6000 { /* BLSP1 QUP2 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x78b6000 0x600>, + <0x7884000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 96 0>, <0 238 0>; + spi-max-frequency = <25000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <10>; + qcom,bam-producer-pipe-index = <11>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_2_active>; + pinctrl-1 = <&spi_2_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_3: spi@78b7000 { /* BLSP1 QUP3 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x78b7000 0x600>, + <0x7884000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 97 0>, <0 238 0>; + spi-max-frequency = <25000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <12>; + qcom,bam-producer-pipe-index = <13>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_3_active>; + pinctrl-1 = <&spi_3_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_4: spi@78b8000 { /* BLSP1 QUP4 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x78b8000 0x600>, + <0x7884000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 98 0>, <0 238 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <14>; + qcom,bam-producer-pipe-index = <15>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_4_active>; + pinctrl-1 = <&spi_4_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_5: spi@78b9000 { /* BLSP1 QUP2 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x78b9000 0x600>, + <0x7884000 0x25000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 99 0>, <0 238 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <16>; + qcom,bam-producer-pipe-index = <17>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_5_active>; + pinctrl-1 = <&spi_5_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_6: spi@7af5000 { /* BLSP2 QUP1 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x7af5000 0x600>, + <0x7ac4000 0x17000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 299 0>, <0 239 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <2>; + qcom,bam-producer-pipe-index = <3>; + qcom,master-id = <84>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_6_active>; + pinctrl-1 = <&spi_6_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, + <&clock_gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>; + status = "disabled"; + }; + + + blsp1_uart1_hs: uart@78af000 { /* BLSP1 UART1 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x78af000 0x200>, + <0x7884000 0x25000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart1_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 107 0 + 1 &intc 0 238 0 + 2 &tlmm 31 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc GCC_BLSP1_UART0_APPS_CLK>, + <&clock_gcc GCC_BLSP1_AHB_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart1_sleep>; + pinctrl-1 = <&blsp1_uart1_active>; + + qcom,msm-bus,name = "buart1"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp1_uart2_hs: uart@78b0000{ /* BLSP1 UART2 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x78b0000 0x200>, + <0x7884000 0x25000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart2_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 108 0 + 1 &intc 0 238 0 + 2 &tlmm 23 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <2>; + qcom,bam-rx-ep-pipe-index = <3>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc GCC_BLSP1_UART1_APPS_CLK>, + <&clock_gcc GCC_BLSP1_AHB_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart2_sleep>; + pinctrl-1 = <&blsp1_uart2_active>; + + qcom,msm-bus,name = "buart2"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp1_uart3_hs: uart@78b1000 { /* BLSP1 UART3 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x78b1000 0x200>, + <0x7884000 0x25000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart3_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 118 0 + 1 &intc 0 238 0 + 2 &tlmm 18 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <4>; + qcom,bam-rx-ep-pipe-index = <5>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, + <&clock_gcc GCC_BLSP1_AHB_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart3_sleep>; + pinctrl-1 = <&blsp1_uart3_active>; + + qcom,msm-bus,name = "buart3"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp1_uart4_hs: uart@78b2000 { /* BLSP1 UART4 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x78b2000 0x200>, + <0x7884000 0x25000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart4_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 119 0 + 1 &intc 0 238 0 + 2 &tlmm 83 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <6>; + qcom,bam-rx-ep-pipe-index = <7>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc GCC_BLSP1_UART3_APPS_CLK>, + <&clock_gcc GCC_BLSP1_AHB_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart4_tx_sleep>, + <&blsp1_uart4_rxcts_sleep>, <&blsp1_uart4_rfr_sleep>; + pinctrl-1 = <&blsp1_uart4_tx_active>, + <&blsp1_uart4_rxcts_active>, <&blsp1_uart4_rfr_active>; + + qcom,msm-bus,name = "buart4"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp2_uart1_hs: uart@7aef000 { /* BLSP1 UART4 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x7aef000 0x200>, + <0x7ac4000 0x17000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp2_uart1_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 297 0 + 1 &intc 0 239 0 + 2 &tlmm 27 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + qcom,master-id = <84>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc GCC_BLSP2_UART0_APPS_CLK>, + <&clock_gcc GCC_BLSP2_AHB_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp2_uart1_sleep>; + pinctrl-1 = <&blsp2_uart1_active>; + + qcom,msm-bus,name = "buart5"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <84 512 0 0>, + <84 512 500 800>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-bus.dtsi b/arch/arm/boot/dts/qcom/qcs405-bus.dtsi new file mode 100644 index 000000000000..dd88ed0ac34e --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-bus.dtsi @@ -0,0 +1,895 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&soc { + ad_hoc_bus: ad-hoc-bus@580000 { + compatible = "qcom,msm-bus-device"; + reg = <0x580000 0x23080>, + <0x400000 0x80000>, + <0x500000 0x15080>; + reg-names = "snoc-base", "bimc-base", "pcnoc-base"; + + /*Buses*/ + fab_bimc: fab-bimc { + cell-id = ; + label = "fab-bimc"; + qcom,fab-dev; + qcom,base-name = "bimc-base"; + qcom,bus-type = <2>; + qcom,util-fact = <153>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_rpmcc BIMC_MSMBUS_CLK>, + <&clock_rpmcc BIMC_MSMBUS_A_CLK>; + }; + + fab_pcnoc: fab-pcnoc { + cell-id = ; + label = "fab-pcnoc"; + qcom,fab-dev; + qcom,base-name = "pcnoc-base"; + qcom,base-offset = <0x7000>; + qcom,qos-off = <0x1000>; + qcom,bus-type = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_rpmcc PNOC_MSMBUS_CLK>, + <&clock_rpmcc PNOC_MSMBUS_A_CLK>; + }; + + fab_snoc: fab-snoc { + cell-id = ; + label = "fab-snoc"; + qcom,fab-dev; + qcom,base-name = "snoc-base"; + qcom,base-offset = <0x11000>; + qcom,qos-off = <0x1000>; + qcom,bus-type = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_rpmcc SNOC_MSMBUS_CLK>, + <&clock_rpmcc SNOC_MSMBUS_A_CLK>; + }; + + /*BIMC Masters*/ + mas_apps_proc: mas-apps-proc { + cell-id = ; + label = "mas-apps-proc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <0>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_ebi &slv_bimc_snoc>; + qcom,prio-lvl = <0>; + qcom,prio-rd = <0>; + qcom,prio-wr = <0>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_oxili: mas-oxili { + cell-id = ; + label = "mas-oxili"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <2>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_ebi &slv_bimc_snoc>; + qcom,prio-lvl = <0>; + qcom,prio-rd = <0>; + qcom,prio-wr = <0>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_mdp: mas-mdp { + cell-id = ; + label = "mas-mdp"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <4>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_ebi &slv_bimc_snoc>; + qcom,prio-lvl = <1>; + qcom,prio-rd = <1>; + qcom,prio-wr = <1>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_snoc_bimc_1: mas-snoc-bimc-1 { + cell-id = ; + label = "mas-snoc-bimc-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <5>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_ebi>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_tcu_0: mas-tcu-0 { + cell-id = ; + label = "mas-tcu-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <6>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_ebi &slv_bimc_snoc>; + qcom,prio-lvl = <2>; + qcom,prio-rd = <2>; + qcom,prio-wr = <2>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + /*PCNOC Masters*/ + mas_spdm: mas-spdm { + cell-id = ; + label = "mas-spdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&pcnoc_int_3>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + }; + + mas_blsp_1: mas-blsp-1 { + cell-id = ; + label = "mas-blsp-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_int_3>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + }; + + mas_blsp_2: mas-blsp-2 { + cell-id = ; + label = "mas-blsp-2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_int_3>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + }; + + mas_xi_usb_hs1: mas-xi-usb-hs1 { + cell-id = ; + label = "mas-xi-usb-hs1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_int_0>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_1 &pcnoc_s_10 + &pcnoc_s_11 &pcnoc_s_2 &pcnoc_s_4 + &pcnoc_s_6 &pcnoc_s_7 &pcnoc_s_8 + &pcnoc_s_9>; + }; + + mas_crypto: mas-crypto { + cell-id = ; + label = "mas-crypto"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <0>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_pcnoc_snoc &pcnoc_int_2>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_1 &pcnoc_s_10 + &pcnoc_s_11 &pcnoc_s_2 &pcnoc_s_4 + &pcnoc_s_6 &pcnoc_s_7 &pcnoc_s_8 + &pcnoc_s_9>; + }; + + mas_sdcc_1: mas-sdcc-1 { + cell-id = ; + label = "mas-sdcc-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_int_0>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_1 &pcnoc_s_10 + &pcnoc_s_11 &pcnoc_s_2 &pcnoc_s_4 + &pcnoc_s_6 &pcnoc_s_7 &pcnoc_s_8 + &pcnoc_s_9>; + }; + + mas_sdcc_2: mas-sdcc-2 { + cell-id = ; + label = "mas-sdcc-2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_int_0>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_1 &pcnoc_s_10 + &pcnoc_s_11 &pcnoc_s_2 &pcnoc_s_4 + &pcnoc_s_6 &pcnoc_s_7 &pcnoc_s_8 + &pcnoc_s_9>; + }; + + mas_snoc_pcnoc: mas-snoc-pcnoc { + cell-id = ; + label = "mas-snoc-pcnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_int_2>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + }; + + mas_qpic: mas-qpic { + cell-id = ; + label = "mas-qpic"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <14>; + qcom,qos-mode = "fixed"; + qcom,connections = <&pcnoc_int_0>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + qcom,blacklist = <&pcnoc_s_0 &pcnoc_s_1 &pcnoc_s_10 + &pcnoc_s_11 &pcnoc_s_2 &pcnoc_s_4 + &pcnoc_s_6 &pcnoc_s_7 &pcnoc_s_8 + &pcnoc_s_9>; + }; + + /*SNOC Masters*/ + mas_qdss_bam: mas-qdss-bam { + cell-id = ; + label = "mas-qdss-bam"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <1>; + qcom,qos-mode = "fixed"; + qcom,connections = <&qdss_int>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_bimc_snoc: mas-bimc-snoc { + cell-id = ; + label = "mas-bimc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_cats_1 &slv_cats_0 + &snoc_int_1 &snoc_int_0>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_pcnoc_snoc: mas-pcnoc-snoc { + cell-id = ; + label = "mas-pcnoc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_snoc_bimc_1 + &snoc_int_2 &snoc_int_0>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_qdss_etr: mas-qdss-etr { + cell-id = ; + label = "mas-qdss-etr"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <0>; + qcom,qos-mode = "fixed"; + qcom,connections = <&qdss_int>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_emac: mas-emac { + cell-id = ; + label = "mas-emac"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <17>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_snoc_bimc_1 &snoc_int_1>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_pcie: mas-pcie { + cell-id = ; + label = "mas-pcie"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <8>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_snoc_bimc_1 &snoc_int_1>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_usb3: mas-usb3 { + cell-id = ; + label = "mas-usb3"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <16>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_snoc_bimc_1 &snoc_int_1>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + qcom,node-qos-clks { + clock-names = "clk-syc-noc-usb3-no-rate"; + clocks = <&clock_gcc GCC_SYS_NOC_USB3_CLK>; + }; + }; + + /*Internal nodes*/ + pcnoc_int_0: pcnoc-int-0 { + cell-id = ; + label = "pcnoc-int-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_pcnoc_snoc &pcnoc_int_2>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + qcom,slv-rpm-id = ; + }; + + pcnoc_int_2: pcnoc-int-2 { + cell-id = ; + label = "pcnoc-int-2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&pcnoc_s_10 &slv_tcu + &pcnoc_s_11 &pcnoc_s_2 + &pcnoc_s_3 &pcnoc_s_0 + &pcnoc_s_1 &pcnoc_s_6 + &pcnoc_s_7 &pcnoc_s_4 + &pcnoc_s_8 &pcnoc_s_9>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + qcom,slv-rpm-id = ; + }; + + pcnoc_int_3: pcnoc-int-3 { + cell-id = ; + label = "pcnoc-int-3"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_pcnoc_snoc>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + qcom,slv-rpm-id = ; + }; + + pcnoc_s_0: pcnoc-s-0 { + cell-id = ; + label = "pcnoc-s-0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_prng &slv_spdm &slv_pdm>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + qcom,slv-rpm-id = ; + }; + + pcnoc_s_1: pcnoc-s-1 { + cell-id = ; + label = "pcnoc-s-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_tcsr>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + qcom,slv-rpm-id = ; + }; + + pcnoc_s_2: pcnoc-s-2 { + cell-id = ; + label = "pcnoc-s-2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_gpu_cfg>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + qcom,slv-rpm-id = ; + }; + + pcnoc_s_3: pcnoc-s-3 { + cell-id = ; + label = "pcnoc-s-3"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_message_ram>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + qcom,slv-rpm-id = ; + }; + + pcnoc_s_4: pcnoc-s-4 { + cell-id = ; + label = "pcnoc-s-4"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_snoc_cfg>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + qcom,slv-rpm-id = ; + }; + + pcnoc_s_6: pcnoc-s-6 { + cell-id = ; + label = "pcnoc-s-6"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_blsp_1 &slv_tlmm_north + &slv_ethernet>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + qcom,slv-rpm-id = ; + }; + + pcnoc_s_7: pcnoc-s-7 { + cell-id = ; + label = "pcnoc-s-7"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_tlmm_south &slv_disp_ss_cfg + &slv_sdcc_1 &slv_pcie &slv_sdcc_2>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + qcom,slv-rpm-id = ; + }; + + pcnoc_s_8: pcnoc-s-8 { + cell-id = ; + label = "pcnoc-s-8"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_crypto_0_cfg>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + qcom,slv-rpm-id = ; + }; + + pcnoc_s_9: pcnoc-s-9 { + cell-id = ; + label = "pcnoc-s-9"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_blsp_2 + &slv_tlmm_east &slv_pmic_arb>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + qcom,slv-rpm-id = ; + }; + + pcnoc_s_10: pcnoc-s-10 { + cell-id = ; + label = "pcnoc-s-10"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_usb_hs>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + qcom,slv-rpm-id = ; + }; + + pcnoc_s_11: pcnoc-s-11 { + cell-id = ; + label = "pcnoc-s-11"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_usb3>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,mas-rpm-id = ; + qcom,slv-rpm-id = ; + }; + + qdss_int: qdss-int { + cell-id = ; + label = "qdss-int"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_snoc_bimc_1 &snoc_int_1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + qcom,slv-rpm-id = ; + }; + + snoc_int_0: snoc-int-0 { + cell-id = ; + label = "snoc-int-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_lpass + &slv_kpss_ahb &slv_wcss>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + qcom,slv-rpm-id = ; + }; + + snoc_int_1: snoc-int-1 { + cell-id = ; + label = "snoc-int-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_snoc_pcnoc &snoc_int_2>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + qcom,slv-rpm-id = ; + }; + + snoc_int_2: snoc-int-2 { + cell-id = ; + label = "snoc-int-2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qdss_stm &slv_imem>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + qcom,slv-rpm-id = ; + }; + + /*Slaves*/ + slv_ebi:slv-ebi { + cell-id = ; + label = "slv-ebi"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_bimc>; + qcom,slv-rpm-id = ; + }; + + slv_bimc_snoc:slv-bimc-snoc { + cell-id = ; + label = "slv-bimc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_bimc>; + qcom,connections = <&mas_bimc_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_spdm:slv-spdm { + cell-id = ; + label = "slv-spdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_pdm:slv-pdm { + cell-id = ; + label = "slv-pdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_prng:slv-prng { + cell-id = ; + label = "slv-prng"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_tcsr:slv-tcsr { + cell-id = ; + label = "slv-tcsr"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_snoc_cfg:slv-snoc-cfg { + cell-id = ; + label = "slv-snoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_message_ram:slv-message-ram { + cell-id = ; + label = "slv-message-ram"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_disp_ss_cfg:slv-disp-ss-cfg { + cell-id = ; + label = "slv-disp-ss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_gpu_cfg:slv-gpu-cfg { + cell-id = ; + label = "slv-gpu-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_blsp_1:slv-blsp-1 { + cell-id = ; + label = "slv-blsp-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_tlmm_north:slv-tlmm-north { + cell-id = ; + label = "slv-tlmm-north"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_pcie:slv-pcie { + cell-id = ; + label = "slv-pcie"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_ethernet:slv-ethernet { + cell-id = ; + label = "slv-ethernet"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_blsp_2:slv-blsp-2 { + cell-id = ; + label = "slv-blsp-2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_tlmm_east:slv-tlmm-east { + cell-id = ; + label = "slv-tlmm-east"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_tcu:slv-tcu { + cell-id = ; + label = "slv-tcu"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_pmic_arb:slv-pmic-arb { + cell-id = ; + label = "slv-pmic-arb"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_sdcc_1:slv-sdcc-1 { + cell-id = ; + label = "slv-sdcc-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_sdcc_2:slv-sdcc-2 { + cell-id = ; + label = "slv-sdcc-2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_tlmm_south:slv-tlmm-south { + cell-id = ; + label = "slv-tlmm-south"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_usb_hs:slv-usb-hs { + cell-id = ; + label = "slv-usb-hs"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_usb3:slv-usb3 { + cell-id = ; + label = "slv-usb3"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_crypto_0_cfg:slv-crypto-0-cfg { + cell-id = ; + label = "slv-crypto-0-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_pcnoc_snoc:slv-pcnoc-snoc { + cell-id = ; + label = "slv-pcnoc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_pcnoc>; + qcom,connections = <&mas_pcnoc_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_kpss_ahb:slv-kpss-ahb { + cell-id = ; + label = "slv-kpss-ahb"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_wcss:slv-wcss { + cell-id = ; + label = "slv-wcss"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_snoc_bimc_1:slv-snoc-bimc-1 { + cell-id = ; + label = "slv-snoc-bimc-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,connections = <&mas_snoc_bimc_1>; + qcom,slv-rpm-id = ; + }; + + slv_imem:slv-imem { + cell-id = ; + label = "slv-imem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_snoc_pcnoc:slv-snoc-pcnoc { + cell-id = ; + label = "slv-snoc-pcnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,connections = <&mas_snoc_pcnoc>; + qcom,slv-rpm-id = ; + }; + + slv_qdss_stm:slv-qdss-stm { + cell-id = ; + label = "slv-qdss-stm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_cats_0:slv-cats-0 { + cell-id = ; + label = "slv-cats-0"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_cats_1:slv-cats-1 { + cell-id = ; + label = "slv-cats-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_lpass:slv-lpass { + cell-id = ; + label = "slv-lpass"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-circular-pca9956.dtsi b/arch/arm/boot/dts/qcom/qcs405-circular-pca9956.dtsi new file mode 100644 index 000000000000..f7da0448d99c --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-circular-pca9956.dtsi @@ -0,0 +1,246 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&i2c_2 { + status = "ok"; + qcom,clk-freq-out = <100000>; + + /* PCA9956B LED Drivers */ + nxp-ledseg-i2c@65 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca9956b"; + reg = <0x65>; + pca9956b,support_initialize = <1>; + pca9956b,mode1 = <0x09>; + pca9956b,mode2 = <0x05>; + + pca9956b,ledout0 = <0xAA>; + pca9956b,ledout1 = <0xAA>; + pca9956b,ledout2 = <0xAA>; + pca9956b,ledout3 = <0xFF>; + pca9956b,ledout4 = <0xFF>; + pca9956b,ledout5 = <0xFF>; + pca9956b,defaultiref = <0x2f>; + out0@0 { + label = "ledsec5_b"; + reg = <0x0>; + }; + out1@1 { + label = "ledsec5_g"; + reg = <0x1>; + }; + out2@2 { + label = "ledsec5_r"; + reg = <0x2>; + }; + out3@3 { + label = "ledsec6_b"; + reg = <0x3>; + }; + out4@4 { + label = "ledsec6_g"; + reg = <0x4>; + }; + out5@5 { + label = "ledsec6_r"; + reg = <0x5>; + }; + out6@6 { + label = "ledsec7_b"; + reg = <0x6>; + }; + out7@7 { + label = "ledsec7_g"; + reg = <0x7>; + }; + out8@8 { + label = "ledsec7_r"; + reg = <0x8>; + }; + out9@9 { + label = "ledsec8_b"; + reg = <0x9>; + }; + out10@10 { + label = "ledsec8_g"; + reg = <0xA>; + }; + out11@11 { + label = "ledsec8_r"; + reg = <0xB>; + }; + out12@12 { + label = "ledsec1_b"; + reg = <0xC>; + }; + out13@13 { + label = "ledsec1_g"; + reg = <0xD>; + }; + out14@14 { + label = "ledsec1_r"; + reg = <0xE>; + }; + out15@15 { + label = "ledsec2_b"; + reg = <0xF>; + }; + out16@16 { + label = "ledsec2_g"; + reg = <0x10>; + }; + out17@17 { + label = "ledsec2_r"; + reg = <0x11>; + }; + out18@18 { + label = "ledsec3_b"; + reg = <0x12>; + }; + out19@19 { + label = "ledsec3_g"; + reg = <0x13>; + }; + out20@20 { + label = "ledsec3_r"; + reg = <0x14>; + }; + out21@21 { + label = "ledsec4_b"; + reg = <0x15>; + }; + out22@22 { + label = "ledsec4_g"; + reg = <0x16>; + }; + out23@23 { + label = "ledsec4_r"; + reg = <0x17>; + }; + }; + + nxp-ledseg-i2c@69 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca9956b"; + reg = <0x69>; + pca9956b,support_initialize = <1>; + pca9956b,mode1 = <0x09>; + pca9956b,mode2 = <0x05>; + + pca9956b,ledout0 = <0xAA>; + pca9956b,ledout1 = <0xAA>; + pca9956b,ledout2 = <0xAA>; + pca9956b,ledout3 = <0xFF>; + pca9956b,ledout4 = <0xFF>; + pca9956b,ledout5 = <0xFF>; + pca9956b,defaultiref = <0x2f>; + out0@0 { + label = "ledsec9_b"; + reg = <0x0>; + }; + out1@1 { + label = "ledsec9_g"; + reg = <0x1>; + }; + out2@2 { + label = "ledsec9_r"; + reg = <0x2>; + }; + out3@3 { + label = "ledsec10_b"; + reg = <0x3>; + }; + out4@4 { + label = "ledsec10_g"; + reg = <0x4>; + }; + out5@5 { + label = "ledsec10_r"; + reg = <0x5>; + }; + out6@6 { + label = "ledsec11_b"; + reg = <0x6>; + }; + out7@7 { + label = "ledsec11_g"; + reg = <0x7>; + }; + out8@8 { + label = "ledsec11_r"; + reg = <0x8>; + }; + out9@9 { + label = "ledsec12_b"; + reg = <0x9>; + }; + out10@10 { + label = "ledsec12_g"; + reg = <0xA>; + }; + out11@11 { + label = "ledsec12_r"; + reg = <0xB>; + }; + out12@12 { + label = "ledsec13_b"; + reg = <0xC>; + }; + out13@13 { + label = "ledsec13_g"; + reg = <0xD>; + }; + out14@14 { + label = "ledsec13_r"; + reg = <0xE>; + }; + out15@15 { + label = "ledsec14_b"; + reg = <0xF>; + }; + out16@16 { + label = "ledsec14_g"; + reg = <0x10>; + }; + out17@17 { + label = "ledsec14_r"; + reg = <0x11>; + }; + out18@18 { + label = "ledsec15_b"; + reg = <0x12>; + }; + out19@19 { + label = "ledsec15_g"; + reg = <0x13>; + }; + out20@20 { + label = "ledsec15_r"; + reg = <0x14>; + }; + out21@21 { + label = "ledsec16_b"; + reg = <0x15>; + }; + out22@22 { + label = "ledsec16_g"; + reg = <0x16>; + }; + out23@23 { + label = "ledsec16_r"; + reg = <0x17>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-coresight.dtsi b/arch/arm/boot/dts/qcom/qcs405-coresight.dtsi new file mode 100644 index 000000000000..1852bfeaa9be --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-coresight.dtsi @@ -0,0 +1,1089 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + csr: csr@0x6001000 { + compatible = "qcom,coresight-csr"; + reg = <0x6001000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-csr"; + qcom,usb-bam-support; + qcom,hwctrl-set-support; + qcom,set-byte-cntr-support; + + qcom,blk-size = <1>; + }; + + replicator_qdss: replicator@6046000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b909>; + + reg = <0x6046000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-qdss"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out_tmc_etr: endpoint { + remote-endpoint= + <&tmc_etr_in_replicator>; + }; + }; + + port@1 { + reg = <0>; + replicator_in_tmc_etf: endpoint { + slave-mode; + remote-endpoint= + <&tmc_etf_out_replicator>; + }; + }; + }; + }; + + tmc_etr: tmc@6048000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + + reg = <0x6048000 0x1000>, + <0x6064000 0x15000>; + reg-names = "tmc-base", "bam-base"; + + arm,buffer-size = <0x400000>; + qcom,force-reg-dump; + arm,sg-enable; + + coresight-name = "coresight-tmc-etr"; + coresight-ctis = <&cti0 &cti0>; + coresight-csr = <&csr>; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + port { + tmc_etr_in_replicator: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_tmc_etr>; + }; + }; + }; + + tmc_etf: tmc@6047000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + + reg = <0x6047000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etf"; + coresight-ctis = <&cti0 &cti0>; + arm,default-sink; + qcom,force-reg-dump; + + coresight-csr = <&csr>; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tmc_etf_out_replicator: endpoint { + remote-endpoint = + <&replicator_in_tmc_etf>; + }; + }; + + port@1 { + reg = <0>; + tmc_etf_in_funnel_merg: endpoint { + slave-mode; + remote-endpoint = + <&funnel_merg_out_tmc_etf>; + }; + }; + }; + + }; + + funnel_merg: funnel@6045000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6045000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-merg"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_merg_out_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_in_funnel_merg>; + }; + }; + + port@1 { + reg = <0>; + funnel_merg_in_funnel_in0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in0_out_funnel_merg>; + }; + }; + + port@2 { + reg = <1>; + funnel_merg_in_funnel_in1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in1_out_funnel_merg>; + }; + }; + + port@3 { + reg = <2>; + funnel_merg_in_funnel_in2: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in2_out_funnel_merg>; + }; + }; + }; + }; + + funnel_in0: funnel@6041000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6041000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in0"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in0_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in0>; + }; + }; + + port@1 { + reg = <0>; + funnel_in0_in_rpm_etm0: endpoint { + slave-mode; + remote-endpoint = + <&rpm_etm0_out_funnel_in0>; + }; + }; + + port@2 { + reg = <6>; + funnel_in0_in_funnel_qatb: endpoint { + slave-mode; + remote-endpoint = + <&funnel_qatb_out_funnel_in0>; + }; + }; + + port@3 { + reg = <7>; + funnel_in0_in_stm: endpoint { + slave-mode; + remote-endpoint = + <&stm_out_funnel_in0>; + }; + }; + }; + }; + + funnel_in1: funnel@6042000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6042000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in1"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in1_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in1>; + }; + }; + port@1 { + reg = <3>; + funnel_in1_in_audio_etm0: endpoint { + slave-mode; + remote-endpoint = + <&audio_etm0_out_funnel_in1>; + }; + }; + }; + }; + + funnel_in2: funnel@6043000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6043000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in2"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in2_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in2>; + }; + }; + + port@1 { + reg = <3>; + funnel_in2_in_turing_etm0: endpoint { + slave-mode; + remote-endpoint = + <&turing_etm0_out_funnel_in2>; + }; + }; + + port@2 { + reg = <4>; + funnel_in2_in_modem_etm0: endpoint { + slave-mode; + remote-endpoint = + <&modem_etm0_out_funnel_in2>; + }; + }; + + port@3 { + reg = <7>; + funnel_in2_in_funnel_apss: endpoint { + slave-mode; + remote-endpoint = + <&funnel_apss_out_funnel_in2>; + }; + }; + }; + }; + + stm: stm@6002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b962>; + + reg = <0x6002000 0x1000>, + <0x09280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + coresight-name = "coresight-stm"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + port { + stm_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_stm>; + }; + }; + }; + + tpda: tpda@6004000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6004000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda"; + + qcom,tpda-atid = <65>; + qcom,bc-elem-size = <10 32>, + <13 32>; + qcom,tc-elem-size = <13 32>; + qcom,dsb-elem-size = <0 32>, + <2 32>, + <3 32>, + <5 32>, + <6 32>, + <10 32>, + <11 32>, + <13 32>; + qcom,cmb-elem-size = <3 64>, + <7 64>, + <13 64>; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_tpda>; + }; + }; + + port@1 { + reg = <0>; + tpda_in_tpdm_wcss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_wcss_out_tpda>; + }; + }; + + port@2 { + reg = <7>; + tpda_in_tpdm_dcc: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dcc_out_tpda>; + }; + }; + + port@3 { + reg = <9>; + tpda_in_tpdm_0_north: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_0_north_out_tpda>; + }; + }; + port@4 { + reg = <10>; + tpda_in_tpdm_1_south: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_1_south_out_tpda>; + }; + }; + + port@5 { + reg = <11>; + tpda_in_tpdm_2_center: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_2_center_out_tpda>; + }; + }; + + + port@6 { + reg = <12>; + tpda_in_tpdm_3_center: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_3_center_out_tpda>; + }; + }; + }; + }; + + tpdm_0_north: tpdm@6114000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6114000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-0-north"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + qcom,msr-fix-req; + + port { + tpdm_0_north_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_0_north>; + }; + }; + }; + + tpdm_1_south: tpdm@6115000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6115000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-1-south"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + qcom,msr-fix-req; + + port { + tpdm_1_south_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_tpdm_1_south>; + }; + }; + }; + + + tpdm_2_center: tpdm@6116000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6116000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-2-center"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + port { + tpdm_2_center_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_2_center>; + }; + }; + }; + + + tpdm_3_center: tpdm@6117000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6117000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-3-center"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + port { + tpdm_3_center_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_3_center>; + }; + }; + }; + + tpdm_dcc: tpdm@6178000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6178000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dcc"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + qcom,hw-enable-check; + qcom,msr-fix-req; + + port { + tpdm_dcc_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_dcc>; + }; + }; + }; + + tpdm_wcss { + compatible = "qcom,coresight-dummy"; + coresight-name = "coresight-tpdm-west-dl"; + + qcom,dummy-source; + port { + tpdm_wcss_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_tpdm_wcss>; + }; + }; + }; + + funnel_qatb: funnel@6005000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6005000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-qatb"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_qatb_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_qatb>; + }; + }; + + port@1 { + reg = <0>; + funnel_qatb_in_tpda: endpoint { + slave-mode; + remote-endpoint = + <&tpda_out_funnel_qatb>; + }; + }; + }; + }; + + cti_cpu0: cti@61b8000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x61b8000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu0"; + cpu = <&CPU0>; + qcom,cti-save; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + }; + + cti_cpu1: cti@61b9000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x61b9000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu1"; + cpu = <&CPU1>; + qcom,cti-save; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + }; + + cti_cpu2: cti@61ba000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x61ba000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu2"; + cpu = <&CPU2>; + qcom,cti-save; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + }; + + cti_cpu3: cti@61bb000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x61bb000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu3"; + cpu = <&CPU3>; + qcom,cti-save; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + }; + + cti0: cti@6010000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6010000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti0"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + }; + + cti1: cti@6011000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6011000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti1"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + }; + + cti2: cti@6012000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6012000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti2"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + }; + + cti3: cti@6013000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6013000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti3"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + }; + + cti4: cti@6014000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6014000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti4"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + }; + + cti5: cti@6015000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6015000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti5"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + }; + + cti6: cti@6016000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6016000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti6"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + }; + + cti7: cti@6017000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6017000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti7"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + }; + + cti8: cti@6018000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6018000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti8"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + }; + + cti9: cti@6019000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6019000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti9"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + }; + + cti10: cti@601a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti10"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + }; + + cti11: cti@601b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti11"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + }; + + cti12: cti@601c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti12"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + }; + + cti13: cti@601d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601d000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti13"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + }; + + cti14: cti@601e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601e000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti14"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + }; + + cti15: cti@601f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601f000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti15"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + }; + + rpm_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-rpm-etm0"; + qcom,inst-id = <4>; + + port{ + rpm_etm0_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_rpm_etm0>; + }; + }; + }; + + turing_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-turing-etm0"; + qcom,inst-id = <13>; + + port{ + turing_etm0_out_funnel_in2: endpoint { + remote-endpoint = + <&funnel_in2_in_turing_etm0>; + }; + }; + }; + + audio_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-audio-etm0"; + qcom,inst-id = <5>; + + port { + audio_etm0_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_audio_etm0>; + }; + }; + }; + + modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem-etm0"; + qcom,inst-id = <2>; + + port{ + modem_etm0_out_funnel_in2: endpoint { + remote-endpoint = + <&funnel_in2_in_modem_etm0>; + }; + }; + }; + + etm0: etm@61bc000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x61bc000 0x1000>; + cpu = <&CPU0>; + + coresight-name = "coresight-etm0"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + port { + etm0_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm0>; + }; + }; + }; + + etm1: etm@61bd000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x61bd000 0x1000>; + cpu = <&CPU1>; + + coresight-name = "coresight-etm1"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + port { + etm1_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm1>; + }; + }; + }; + + etm2: etm@61be000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x61be000 0x1000>; + cpu = <&CPU2>; + + coresight-name = "coresight-etm2"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + port { + etm2_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm2>; + }; + }; + }; + + etm3: etm@61bf000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x61bf000 0x1000>; + cpu = <&CPU3>; + + coresight-name = "coresight-etm3"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + port { + etm3_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm3>; + }; + }; + }; + + funnel_apss: funnel@61a1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x61a1000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss_out_funnel_in2: endpoint { + remote-endpoint = + <&funnel_in2_in_funnel_apss>; + }; + }; + port@1 { + reg = <0>; + funnel_apss_in_etm0: endpoint { + slave-mode; + remote-endpoint = + <&etm0_out_funnel_apss>; + }; + }; + + port@2 { + reg = <1>; + funnel_apss_in_etm1: endpoint { + slave-mode; + remote-endpoint = + <&etm1_out_funnel_apss>; + }; + }; + + port@3 { + reg = <2>; + funnel_apss_in_etm2: endpoint { + slave-mode; + remote-endpoint = + <&etm2_out_funnel_apss>; + }; + }; + + port@4 { + reg = <3>; + funnel_apss_in_etm3: endpoint { + slave-mode; + remote-endpoint = + <&etm3_out_funnel_apss>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-cpu.dtsi b/arch/arm/boot/dts/qcom/qcs405-cpu.dtsi new file mode 100644 index 000000000000..f4f616825cbd --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-cpu.dtsi @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + }; + + CPU0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + /* A53 L2 dump not supported */ + qcom,dump-size = <0x0>; + }; + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + }; + + CPU1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L1_I_101: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + L1_D_101: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + }; + + CPU2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L1_I_102: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + L1_D_102: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + }; + + CPU3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L1_I_103: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + L1_D_103: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + }; + }; + + energy_costs: energy-costs { + compatible = "sched-energy"; + + CPU_COST_0: core-cost0 { + busy-cost-data = < + 960000 159 + 1094400 207 + 1248000 256 + 1401600 327 + >; + idle-cost-data = < + 100 80 60 40 + >; + }; + CLUSTER_COST_0: cluster-cost0 { + busy-cost-data = < + 960000 53 + 1094400 61 + 1248000 71 + 1401600 85 + >; + idle-cost-data = < + 4 3 2 1 + >; + }; + }; +}; + +&soc { + cpuss_dump { + compatible = "qcom,cpuss-dump"; + qcom,l2_dump1 { + /* L2 cache dump for A53 cluster */ + qcom,dump-node = <&L2_1>; + qcom,dump-id = <0xC1>; + }; + qcom,l1_i_cache100 { + qcom,dump-node = <&L1_I_100>; + qcom,dump-id = <0x60>; + }; + qcom,l1_i_cache101 { + qcom,dump-node = <&L1_I_101>; + qcom,dump-id = <0x61>; + }; + qcom,l1_i_cache102 { + qcom,dump-node = <&L1_I_102>; + qcom,dump-id = <0x62>; + }; + qcom,l1_i_cache103 { + qcom,dump-node = <&L1_I_103>; + qcom,dump-id = <0x63>; + }; + qcom,l1_d_cache100 { + qcom,dump-node = <&L1_D_100>; + qcom,dump-id = <0x80>; + }; + qcom,l1_d_cache101 { + qcom,dump-node = <&L1_D_101>; + qcom,dump-id = <0x81>; + }; + qcom,l1_d_cache102 { + qcom,dump-node = <&L1_D_102>; + qcom,dump-id = <0x82>; + }; + qcom,l1_d_cache103 { + qcom,dump-node = <&L1_D_103>; + qcom,dump-id = <0x83>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs404-csra1-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/qcs405-csra1-audio-overlay.dtsi similarity index 97% rename from arch/arm64/boot/dts/qcom/qcs404-csra1-audio-overlay.dtsi rename to arch/arm/boot/dts/qcom/qcs405-csra1-audio-overlay.dtsi index e2fe8dabb057..408285b6c756 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-csra1-audio-overlay.dtsi +++ b/arch/arm/boot/dts/qcom/qcs405-csra1-audio-overlay.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018,2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -129,6 +129,6 @@ #include "qcs405-tasha.dtsi" #include "qcs405-va-bolero.dtsi" -#include "qcs404-csra1.dtsi" +#include "qcs405-csra1.dtsi" diff --git a/arch/arm64/boot/dts/qcom/qcs404-csra1.dtsi b/arch/arm/boot/dts/qcom/qcs405-csra1.dtsi similarity index 91% rename from arch/arm64/boot/dts/qcom/qcs404-csra1.dtsi rename to arch/arm/boot/dts/qcom/qcs405-csra1.dtsi index cefa0706ba5c..b1724376fabd 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-csra1.dtsi +++ b/arch/arm/boot/dts/qcom/qcs405-csra1.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018,2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -11,7 +11,7 @@ * GNU General Public License for more details. */ -&i2c_2 { +&i2c_5 { qcom,clk-freq-out = <100000>; status = "okay"; /* CSRA66X0 cluster GRP_0 */ diff --git a/arch/arm/boot/dts/qcom/qcs405-csra6-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/qcs405-csra6-audio-overlay.dtsi new file mode 100644 index 000000000000..44b10697db35 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-csra6-audio-overlay.dtsi @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&q6core { + cdc_dmic01_gpios: cdc_dmic01_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>; + pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>; + qcom,lpi-gpios; + }; + + cdc_dmic23_gpios: cdc_dmic23_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>; + pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>; + qcom,lpi-gpios; + }; + + cdc_dmic45_gpios: cdc_dmic45_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>; + pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>; + qcom,lpi-gpios; + }; + + cdc_dmic67_gpios: cdc_dmic67_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic67_clk_active &cdc_dmic67_data_active>; + pinctrl-1 = <&cdc_dmic67_clk_sleep &cdc_dmic67_data_sleep>; + qcom,lpi-gpios; + }; + + pri_mi2s_gpios: pri_mi2s_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&pri_mi2s_sck_active &pri_mi2s_ws_active + &pri_mi2s_sd0_active &pri_mi2s_sd1_active + &pri_mi2s_sd2_active &pri_mi2s_sd3_active + &pri_mi2s_sd4_active &pri_mi2s_sd5_active>; + pinctrl-1 = <&pri_mi2s_sck_sleep &pri_mi2s_ws_sleep + &pri_mi2s_sd0_sleep &pri_mi2s_sd1_sleep + &pri_mi2s_sd2_sleep &pri_mi2s_sd3_sleep + &pri_mi2s_sd4_sleep &pri_mi2s_sd5_sleep>; + }; + + sec_mi2s_gpios: sec_mi2s_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&sec_mi2s_sck_active &sec_mi2s_ws_active + &sec_mi2s_sd0_active &sec_mi2s_sd1_active + &sec_mi2s_sd2_active &sec_mi2s_sd3_active>; + pinctrl-1 = <&sec_mi2s_sck_sleep &sec_mi2s_ws_sleep + &sec_mi2s_sd0_sleep &sec_mi2s_sd1_sleep + &sec_mi2s_sd2_sleep &sec_mi2s_sd3_sleep>; + }; +}; + +&q6core { + bolero: bolero-cdc { + compatible = "qcom,bolero-codec"; + clock-names = "lpass_core_hw_vote"; + clocks = <&lpass_core_hw_vote 0>; + qcom,num-macros = <1>; + }; +}; + +&qcs405_snd { + qcom,model = "qcs405-csra6-snd-card"; + qcom,va-bolero-codec = <1>; + qcom,tasha-codec = <1>; + qcom,csra-codec = <1>; + asoc-codec = <&stub_codec>, <&bolero>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec"; + qcom,csra-max-devs = <6>; + qcom,csra-devs = <&csra66x0_ampl_6B>, <&csra66x0_ampl_6A>, + <&csra66x0_ampl_69>, <&csra66x0_ampl_68>, + <&csra66x0_ampl_69_1>, <&csra66x0_ampl_68_1>; + qcom,csra-aux-dev-prefix = "CSRA_78", "CSRA_56", "CSRA_34", + "CSRA_12", "CSRA_BC", "CSRA_9A"; + qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; + qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; + qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>; + qcom,cdc-dmic67-gpios = <&cdc_dmic67_gpios>; + qcom,pri-mi2s-gpios = <&pri_mi2s_gpios>; + qcom,sec-mi2s-gpios = <&sec_mi2s_gpios>; + qcom,audio-routing = + "RX_BIAS", "MCLK", + "lineout booster", "LINEOUT1", + "lineout booster", "LINEOUT2", + "LINEOUT1", "rx regulator", + "LINEOUT2", "rx regulator", + "AMIC3", "tx regulator", + "AMIC4", "tx regulator", + "AMIC3", "MIC BIAS3", + "AMIC4", "MIC BIAS4", + "MIC BIAS3", "Analog Mic3", + "MIC BIAS4", "Analog Mic4", + "VA DMIC0", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic0", + "VA DMIC1", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic1", + "VA DMIC2", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic2", + "VA DMIC3", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic3", + "VA DMIC4", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic4", + "VA DMIC5", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic5", + "VA DMIC6", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic6", + "VA DMIC7", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic7", + "CSRA_12 IN", "PRI_MI2S_RX", + "CSRA_34 IN", "PRI_MI2S_RX", + "CSRA_56 IN", "PRI_MI2S_RX", + "CSRA_78 IN", "PRI_MI2S_RX", + "CSRA_9A IN", "PRI_MI2S_RX", + "CSRA_BC IN", "PRI_MI2S_RX"; + pinctrl-names = "default"; + pinctrl-0 = <&spdifrx_opt_default>; +}; + +&dai_mi2s0 { + qcom,msm-mi2s-rx-lines = <0x3f>; +}; + +#include "qcs405-tasha.dtsi" +#include "qcs405-va-bolero.dtsi" +#include "qcs405-csra6.dtsi" + diff --git a/arch/arm/boot/dts/qcom/qcs405-csra6.dtsi b/arch/arm/boot/dts/qcom/qcs405-csra6.dtsi new file mode 100644 index 000000000000..5e9664fe60cf --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-csra6.dtsi @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&i2c_5 { + qcom,clk-freq-out = <100000>; + status = "okay"; + /* CSRA66X0 cluster GRP_0 */ + csra66x0_ampl_68: csra66x0@68 { + compatible = "qcom,csra66x0"; + reg = <0x68>; + qcom,csra-vreg-en-gpio = <&tlmm 96 0>; + qcom,csra-cluster = <1>; + qcom,csra-cluster-master = <1>; + interrupt-parent = <&tlmm>; + interrupts = <80 IRQ_TYPE_LEVEL_HIGH>; + irq-active-low = <0>; + }; + + csra66x0_ampl_69: csra66x0@69 { + compatible = "qcom,csra66x0"; + reg = <0x69>; + qcom,csra-vreg-en-gpio = <&tlmm 96 0>; + qcom,csra-cluster = <1>; + }; + + csra66x0_ampl_6A: csra66x0@6A { + compatible = "qcom,csra66x0"; + reg = <0x6A>; + qcom,csra-vreg-en-gpio = <&tlmm 96 0>; + qcom,csra-cluster = <1>; + }; + + csra66x0_ampl_6B: csra66x0@6B { + compatible = "qcom,csra66x0"; + reg = <0x6B>; + qcom,csra-vreg-en-gpio = <&tlmm 96 0>; + qcom,csra-cluster = <1>; + }; +}; + +&i2c_2 { + status = "okay"; + /* CSRA66X0 cluster GRP_1 */ + csra66x0_ampl_68_1: csra66x0_1@68 { + compatible = "qcom,csra66x0"; + reg = <0x68>; + qcom,csra-vreg-en-gpio = <&tlmm 96 0>; + qcom,csra-cluster = <1>; + qcom,csra-cluster-master = <1>; + interrupt-parent = <&tlmm>; + interrupts = <81 IRQ_TYPE_LEVEL_HIGH>; + irq-active-low = <0>; + }; + + csra66x0_ampl_69_1: csra66x0_1@69 { + compatible = "qcom,csra66x0"; + reg = <0x69>; + qcom,csra-vreg-en-gpio = <&tlmm 96 0>; + qcom,csra-cluster = <1>; + }; +}; + +&csra66x0_ampl_68 { + status = "okay"; +}; + +&csra66x0_ampl_69 { + status = "okay"; +}; + +&csra66x0_ampl_6A { + status = "okay"; +}; + +&csra66x0_ampl_6B { + status = "okay"; +}; + +&csra66x0_ampl_68_1 { + status = "okay"; +}; + +&csra66x0_ampl_69_1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-csra8-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/qcs405-csra8-audio-overlay.dtsi new file mode 100644 index 000000000000..1138390a012c --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-csra8-audio-overlay.dtsi @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&q6core { + cdc_dmic01_gpios: cdc_dmic01_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>; + pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>; + qcom,lpi-gpios; + }; + + cdc_dmic23_gpios: cdc_dmic23_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>; + pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>; + qcom,lpi-gpios; + }; + + cdc_dmic45_gpios: cdc_dmic45_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>; + pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>; + qcom,lpi-gpios; + }; + + cdc_dmic67_gpios: cdc_dmic67_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic67_clk_active &cdc_dmic67_data_active>; + pinctrl-1 = <&cdc_dmic67_clk_sleep &cdc_dmic67_data_sleep>; + qcom,lpi-gpios; + }; + + pri_mi2s_gpios: pri_mi2s_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&pri_mi2s_sck_active &pri_mi2s_ws_active + &pri_mi2s_sd0_active &pri_mi2s_sd1_active + &pri_mi2s_sd2_active &pri_mi2s_sd3_active + &pri_mi2s_sd4_active &pri_mi2s_sd5_active + &pri_mi2s_sd6_active &pri_mi2s_sd7_active>; + pinctrl-1 = <&pri_mi2s_sck_sleep &pri_mi2s_ws_sleep + &pri_mi2s_sd0_sleep &pri_mi2s_sd1_sleep + &pri_mi2s_sd2_sleep &pri_mi2s_sd3_sleep + &pri_mi2s_sd4_sleep &pri_mi2s_sd5_sleep + &pri_mi2s_sd6_sleep &pri_mi2s_sd7_sleep>; + }; + + sec_mi2s_gpios: sec_mi2s_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&sec_mi2s_sck_active &sec_mi2s_ws_active + &sec_mi2s_sd0_active &sec_mi2s_sd1_active + &sec_mi2s_sd2_active &sec_mi2s_sd3_active>; + pinctrl-1 = <&sec_mi2s_sck_sleep &sec_mi2s_ws_sleep + &sec_mi2s_sd0_sleep &sec_mi2s_sd1_sleep + &sec_mi2s_sd2_sleep &sec_mi2s_sd3_sleep>; + }; +}; + +&q6core { + bolero: bolero-cdc { + compatible = "qcom,bolero-codec"; + clock-names = "lpass_core_hw_vote"; + clocks = <&lpass_core_hw_vote 0>; + qcom,num-macros = <1>; + }; +}; + +&qcs405_snd { + qcom,model = "qcs405-csra8-snd-card"; + qcom,va-bolero-codec = <1>; + qcom,tasha-codec = <1>; + qcom,csra-codec = <1>; + asoc-codec = <&stub_codec>, <&bolero>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec"; + qcom,csra-max-devs = <8>; + qcom,csra-devs = <&csra66x0_ampl_6B>, <&csra66x0_ampl_6A>, + <&csra66x0_ampl_69>, <&csra66x0_ampl_68>, + <&csra66x0_ampl_6B_1>, <&csra66x0_ampl_6A_1>, + <&csra66x0_ampl_69_1>, <&csra66x0_ampl_68_1>; + qcom,csra-aux-dev-prefix = "CSRA_78", "CSRA_56", "CSRA_34", + "CSRA_12", "CSRA_F0", "CSRA_DE", "CSRA_BC", "CSRA_9A"; + qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; + qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; + qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>; + qcom,cdc-dmic67-gpios = <&cdc_dmic67_gpios>; + qcom,pri-mi2s-gpios = <&pri_mi2s_gpios>; + qcom,sec-mi2s-gpios = <&sec_mi2s_gpios>; + qcom,audio-routing = + "RX_BIAS", "MCLK", + "lineout booster", "LINEOUT1", + "lineout booster", "LINEOUT2", + "LINEOUT1", "rx regulator", + "LINEOUT2", "rx regulator", + "AMIC3", "tx regulator", + "AMIC4", "tx regulator", + "AMIC3", "MIC BIAS3", + "AMIC4", "MIC BIAS4", + "MIC BIAS3", "Analog Mic3", + "MIC BIAS4", "Analog Mic4", + "VA DMIC0", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic0", + "VA DMIC1", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic1", + "VA DMIC2", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic2", + "VA DMIC3", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic3", + "VA DMIC4", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic4", + "VA DMIC5", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic5", + "VA DMIC6", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic6", + "VA DMIC7", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic7", + "CSRA_12 IN", "PRI_MI2S_RX", + "CSRA_34 IN", "PRI_MI2S_RX", + "CSRA_56 IN", "PRI_MI2S_RX", + "CSRA_78 IN", "PRI_MI2S_RX", + "CSRA_9A IN", "PRI_MI2S_RX", + "CSRA_BC IN", "PRI_MI2S_RX", + "CSRA_DE IN", "PRI_MI2S_RX", + "CSRA_F0 IN", "PRI_MI2S_RX"; + pinctrl-names = "default"; + pinctrl-0 = <&spdifrx_opt_default>; +}; + +&dai_mi2s0 { + qcom,msm-mi2s-rx-lines = <0xff>; +}; + +#include "qcs405-tasha.dtsi" +#include "qcs405-va-bolero.dtsi" +#include "qcs405-csra8.dtsi" + diff --git a/arch/arm/boot/dts/qcom/qcs405-csra8.dtsi b/arch/arm/boot/dts/qcom/qcs405-csra8.dtsi new file mode 100644 index 000000000000..256c6bf20ddd --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-csra8.dtsi @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&i2c_5 { + qcom,clk-freq-out = <100000>; + status = "okay"; + /* CSRA66X0 cluster GRP_0 */ + csra66x0_ampl_68: csra66x0@68 { + compatible = "qcom,csra66x0"; + reg = <0x68>; + qcom,csra-vreg-en-gpio = <&tlmm 113 0>; + qcom,csra-cluster = <1>; + qcom,csra-cluster-master = <1>; + interrupt-parent = <&tlmm>; + interrupts = <80 IRQ_TYPE_LEVEL_HIGH>; + irq-active-low = <0>; + }; + + csra66x0_ampl_69: csra66x0@69 { + compatible = "qcom,csra66x0"; + reg = <0x69>; + qcom,csra-vreg-en-gpio = <&tlmm 113 0>; + qcom,csra-cluster = <1>; + }; + + csra66x0_ampl_6A: csra66x0@6A { + compatible = "qcom,csra66x0"; + reg = <0x6A>; + qcom,csra-vreg-en-gpio = <&tlmm 113 0>; + qcom,csra-cluster = <1>; + }; + + csra66x0_ampl_6B: csra66x0@6B { + compatible = "qcom,csra66x0"; + reg = <0x6B>; + qcom,csra-vreg-en-gpio = <&tlmm 113 0>; + qcom,csra-cluster = <1>; + }; +}; + +&i2c_2 { + status = "okay"; + /* CSRA66X0 cluster GRP_1 */ + csra66x0_ampl_68_1: csra66x0_1@68 { + compatible = "qcom,csra66x0"; + reg = <0x68>; + qcom,csra-vreg-en-gpio = <&tlmm 114 0>; + qcom,csra-cluster = <1>; + qcom,csra-cluster-master = <1>; + interrupt-parent = <&tlmm>; + interrupts = <81 IRQ_TYPE_LEVEL_HIGH>; + irq-active-low = <0>; + }; + + csra66x0_ampl_69_1: csra66x0_1@69 { + compatible = "qcom,csra66x0"; + reg = <0x69>; + qcom,csra-vreg-en-gpio = <&tlmm 114 0>; + qcom,csra-cluster = <1>; + }; + + csra66x0_ampl_6A_1: csra66x0_1@6A { + compatible = "qcom,csra66x0"; + reg = <0x6A>; + qcom,csra-vreg-en-gpio = <&tlmm 114 0>; + qcom,csra-cluster = <1>; + }; + + csra66x0_ampl_6B_1: csra66x0_1@6B { + compatible = "qcom,csra66x0"; + reg = <0x6B>; + qcom,csra-vreg-en-gpio = <&tlmm 114 0>; + qcom,csra-cluster = <1>; + }; +}; + +&csra66x0_ampl_68 { + status = "okay"; +}; + +&csra66x0_ampl_69 { + status = "okay"; +}; + +&csra66x0_ampl_6A { + status = "okay"; +}; + +&csra66x0_ampl_6B { + status = "okay"; +}; + +&csra66x0_ampl_68_1 { + status = "okay"; +}; + +&csra66x0_ampl_69_1 { + status = "okay"; +}; + +&csra66x0_ampl_6A_1 { + status = "okay"; +}; + +&csra66x0_ampl_6B_1 { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/qcom/qcs405-gdsc.dtsi b/arch/arm/boot/dts/qcom/qcs405-gdsc.dtsi new file mode 100644 index 000000000000..52d3ffb8a78a --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-gdsc.dtsi @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + /* GDSCs in Global CC */ + gdsc_mdss: qcom,gdsc@184d078 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_mdss"; + reg = <0x184d078 0x4>; + status = "disabled"; + }; + + gdsc_oxili_gx: qcom,gdsc@185901c { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_oxili_gx"; + reg = <0x185901c 0x4>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-geni-ir-overlay.dtsi b/arch/arm/boot/dts/qcom/qcs405-geni-ir-overlay.dtsi new file mode 100644 index 000000000000..95bbcd2ee793 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-geni-ir-overlay.dtsi @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "qcs405-pinctrl.dtsi" + +&soc { + qcom,msm-geni-ir@740000 { + compatible = "qcom,msm-geni-ir"; + reg-names = "base"; + reg = <0x740000 0x1000>; + + interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "geni-ir-core-irq"; + + clocks = <&clock_gcc GCC_GENI_IR_H_CLK>, + <&clock_gcc GCC_GENI_IR_S_CLK>; + clock-names = "iface_clk", "serial_clk"; + + pinctrl-names = "default"; + pinctrl-0 = <&ir_in_default>; + + resets = <&clock_gcc GCC_GENI_IR_BCR>; + reset-names = "geni_reset"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-gpu.dtsi b/arch/arm/boot/dts/qcom/qcs405-gpu.dtsi new file mode 100644 index 000000000000..2b58972a222c --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-gpu.dtsi @@ -0,0 +1,187 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + msm_bus: qcom,kgsl-busmon { + label = "kgsl-busmon"; + compatible = "qcom,kgsl-busmon"; + }; + + gpu_bw_tbl: gpu-bw-tbl { + compatible = "operating-points-v2"; + opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */ + opp-100 { opp-hz = /bits/ 64 < 769 >; }; /* 1. DDR:100.80MHz */ + opp-211 { opp-hz = /bits/ 64 < 1611 >; }; /* 2. DDR:211.20MHz */ + opp-297 { opp-hz = /bits/ 64 < 2270 >; }; /* 3. DDR:297.60MHz */ + opp-384 { opp-hz = /bits/ 64 < 2929 >; }; /* 4. DDR:384.00MHz */ + opp-556 { opp-hz = /bits/ 64 < 4248 >; }; /* 5. DDR:556.80MHz */ + opp-595 { opp-hz = /bits/ 64 < 4541 >; }; /* 6. DDR:595.20MHz */ + opp-672 { opp-hz = /bits/ 64 < 5126 >; }; /* 7. DDR:672.00MHz */ + opp-740 { opp-hz = /bits/ 64 < 5639 >; }; /* 8. DDR:739.20MHz */ + }; + + /* Bus governor */ + gpubw: qcom,gpubw { + compatible = "qcom,devbw"; + governor = "bw_vbif"; + qcom,src-dst-ports = <26 512>; + operating-points-v2 = <&gpu_bw_tbl>; + }; + + msm_gpu: qcom,kgsl-3d0@1c00000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; + reg = <0x1c00000 0x10000 + 0x1c10000 0x10000 + 0x00a0000 0x06fff>; + reg-names = "kgsl_3d0_reg_memory", "kgsl_3d0_shader_memory", + "qfprom_memory"; + interrupts = <0 33 0>; + interrupt-names = "kgsl_3d0_irq"; + qcom,id = <0>; + + qcom,chipid = <0x03000620>; + + qcom,initial-pwrlevel = <3>; + + qcom,idle-timeout = <80>; //msecs + qcom,strtstp-sleepwake; + qcom,gpu-bimc-interface-clk-freq = <400000000>; //In Hz + qcom,gpu-disable-fuse = <0x41a0 0x00000001 29>; + + clocks = <&clock_gcc GCC_OXILI_GFX3D_CLK>, + <&clock_gcc GCC_OXILI_AHB_CLK>, + <&clock_gcc GCC_BIMC_GFX_CLK>, + <&clock_gcc GCC_BIMC_GPU_CLK>, + <&clock_gcc GCC_GTCU_AHB_CLK>, + <&clock_gcc GCC_GFX_TCU_CLK>, + <&clock_gcc GCC_GFX_TBU_CLK>, + <&clock_rpmcc RPM_SMD_BIMC_GPU_CLK>; + + clock-names = "core_clk", "iface_clk", "mem_iface_clk", + "alt_mem_iface_clk", "gtcu_iface_clk", + "gtcu_clk", "gtbu_clk", "bimc_gpu_clk"; + + /* Bus Scale Settings */ + qcom,gpubw-dev = <&gpubw>; + qcom,bus-control; + qcom,bus-width = <16>; + qcom,msm-bus,name = "grp3d"; + qcom,msm-bus,num-cases = <9>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, /* off */ + <26 512 0 806400>, /* 1. 100.80 MHz */ + <26 512 0 1689600>, /* 2. 211.20 MHz */ + <26 512 0 2380800>, /* 3. 297.60 MHz */ + <26 512 0 3072000>, /* 4. 384.00 MHz */ + <26 512 0 4454400>, /* 5. 556.80 MHz */ + <26 512 0 4761600>, /* 6. 595.20 MHz */ + <26 512 0 5376000>, /* 7. 672.00 MHz */ + <26 512 0 5913600>; /* 8. 739.20 MHz */ + + /* GDSC regulator names */ + regulator-names = "vdd"; + /* GDSC oxili regulators */ + vdd-supply = <&gdsc_oxili_gx>; + + /* CPU latency parameter */ + qcom,pm-qos-active-latency = <651>; + + /* Enable gpu cooling device */ + #cooling-cells = <2>; + + /* Power levels */ + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + /* TURBO */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <598000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <8>; + }; + + /* NOM+ */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <523200000>; + qcom,bus-freq = <6>; + qcom,bus-min = <5>; + qcom,bus-max = <7>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <484800000>; + qcom,bus-freq = <5>; + qcom,bus-min = <4>; + qcom,bus-max = <6>; + }; + + /* SVS+ */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <400000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <270000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <3>; + }; + + /* XO */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <19200000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; +}; + + kgsl_msm_iommu: qcom,kgsl-iommu@1f00000 { + compatible = "qcom,kgsl-smmu-v2"; + reg = <0x1f00000 0x10000>; + /* + * The gpu can only program a single context bank + * at this fixed offset. + */ + qcom,protect = <0xa000 0x1000>; + clocks = <&clock_gcc GCC_SMMU_CFG_CLK>, + <&clock_gcc GCC_GFX_TCU_CLK>, + <&clock_gcc GCC_GTCU_AHB_CLK>, + <&clock_gcc GCC_GFX_TBU_CLK>; + clock-names = "scfg_clk", "gtcu_clk", "gtcu_iface_clk", + "gtbu_clk"; + qcom,retention; + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&gfx_iommu 0 1>; + qcom,gpu-offset = <0xa000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-ion.dtsi b/arch/arm/boot/dts/qcom/qcs405-ion.dtsi new file mode 100644 index 000000000000..925427c5e6c8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-ion.dtsi @@ -0,0 +1,43 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = <25>; + qcom,ion-heap-type = "SYSTEM"; + }; + + qcom,ion-heap@8 { /* CP_MM HEAP */ + status = "disabled"; + reg = <8>; + memory-region = <&secure_mem>; + qcom,ion-heap-type = "SECURE_DMA"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = <27>; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@19 { /* QSEECOM TA HEAP */ + reg = <19>; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs407-iot-sku1.dts b/arch/arm/boot/dts/qcom/qcs405-iot-sku1.dts similarity index 88% rename from arch/arm64/boot/dts/qcom/qcs407-iot-sku1.dts rename to arch/arm/boot/dts/qcom/qcs405-iot-sku1.dts index 34039bc1f83b..3182b2d90182 100644 --- a/arch/arm64/boot/dts/qcom/qcs407-iot-sku1.dts +++ b/arch/arm/boot/dts/qcom/qcs405-iot-sku1.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -13,13 +13,13 @@ /dts-v1/; -#include "qcs407.dtsi" +#include "qcs405.dtsi" #include "qcs405-wsa-audio-overlay.dtsi" #include "qcs405-circular-pca9956.dtsi" / { - model = "Qualcomm Technologies, Inc. QCS407 EVB1 1000 IOT"; - compatible = "qcom,qcs407-iot", "qcom,qcs407", "qcom,iot"; + model = "Qualcomm Technologies, Inc. QCS405 EVB1 1000 IOT"; + compatible = "qcom,qcs405-iot", "qcom,qcs405", "qcom,iot"; qcom,board-id = <0x010020 0>; }; diff --git a/arch/arm/boot/dts/qcom/qcs405-iot-sku10.dts b/arch/arm/boot/dts/qcom/qcs405-iot-sku10.dts new file mode 100644 index 000000000000..f573c43f70e7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-iot-sku10.dts @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "qcs405.dtsi" +#include "qcs405-tdm-audio-overlay.dtsi" +#include "qcs405-circular-pca9956.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS405 EVB1 4000 TDM Mic"; + compatible = "qcom,qcs405-iot", "qcom,qcs405", "qcom,iot"; + qcom,board-id = <0x070020 0x1>; +}; + +#include "qcs405-mdss-panels.dtsi" + +&mdss_mdp { + qcom,mdss-pref-prim-intf = "dsi"; +}; + +&mdss_dsi { + hw-config = "single_dsi"; +}; + +&mdss_dsi0 { + qcom,dsi-pref-prim-pan = <&dsi_hx8394d_720_vid>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; + pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 41 0>; + qcom,platform-reset-gpio = <&tlmm 39 0>; + qcom,platform-bklight-en-gpio = <&tlmm 48 0>; +}; + +&dsi_hx8394d_720_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_tlmm_gpio"; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&soc { + spi@78b5000 { + status = "ok"; + spi@0 { + compatible = "qcom,spi-msm-codec-slave"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-iot-sku11.dts b/arch/arm/boot/dts/qcom/qcs405-iot-sku11.dts new file mode 100644 index 000000000000..2947489bbb36 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-iot-sku11.dts @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "qcs405.dtsi" + +/ { + model = "sEVB/SLT with DSI display and APC external Buck"; + compatible = "qcom,qcs405-iot", "qcom,qcs405", "qcom,iot"; + qcom,board-id = <0x020020 0x2>; +}; + +&soc { + /delete-node/ qcom,msm-cpufreq; + + msm_cpufreq: qcom,msm-cpufreq { + compatible = "qcom,msm-cpufreq"; + clock-names = "cpu0_clk"; + clocks = <&clock_cpu APCS_MUX_CLK>; + + qcom,cpufreq-table = + < 1094400 >, + < 1248000 >, + < 1401600 >; + }; + + /delete-node/ qcom,cpu0-computemon; + + cpu0_computemon: qcom,cpu0-computemon { + compatible = "qcom,arm-cpu-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1094400 MHZ_TO_MBPS( 297, 8) >, + < 1248000 MHZ_TO_MBPS( 597, 8) >, + < 1401600 MHZ_TO_MBPS( 710, 8) >; + }; +}; + +&pms405_s3 { + status = "disabled"; +}; + +&pms405_gpios { + hl7503_vsel { + hl7503_vsel_default: hl7503_vsel_default { + pins = "gpio6"; + function = "normal"; + }; + }; +}; + +&i2c_2 { + status = "ok"; +}; + +&hl7503_vreg { + status = "ok"; + fcs,vsel-gpio = <&pms405_gpios 6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hl7503_vsel_default>; +}; + +&apc_vreg_corner { + vdd-apc-supply = <&hl7503_vreg>; + qcom,cpr-apc-volt-step = <6250>; + qcom,cpr-voltage-ceiling = <1224000 1288000 1356250 1387500>; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs407-iot-sku12.dts b/arch/arm/boot/dts/qcom/qcs405-iot-sku12.dts similarity index 79% rename from arch/arm64/boot/dts/qcom/qcs407-iot-sku12.dts rename to arch/arm/boot/dts/qcom/qcs405-iot-sku12.dts index dbaf21baa7c1..9546c4300c79 100644 --- a/arch/arm64/boot/dts/qcom/qcs407-iot-sku12.dts +++ b/arch/arm/boot/dts/qcom/qcs405-iot-sku12.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -13,14 +13,14 @@ /dts-v1/; -#include "qcs407.dtsi" +#include "qcs405.dtsi" #include "qcs405-csra8-audio-overlay.dtsi" #include "qcs405-geni-ir-overlay.dtsi" #include "qcs405-linear-pca9956.dtsi" / { - model = "Qualcomm Technologies, Inc. QCS407 EVB1 4K/CSRA8 SPI/LiN"; - compatible = "qcom,qcs407-iot", "qcom,qcs407", "qcom,iot"; + model = "Qualcomm Technologies, Inc. QCS405 EVB1 4K/CSRA8 SPI/LiN"; + compatible = "qcom,qcs405-iot", "qcom,qcs405", "qcom,iot"; qcom,board-id = <0x080020 0x1>; }; diff --git a/arch/arm/boot/dts/qcom/qcs405-iot-sku2.dts b/arch/arm/boot/dts/qcom/qcs405-iot-sku2.dts new file mode 100644 index 000000000000..d7dd2c7e179d --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-iot-sku2.dts @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "qcs405.dtsi" +#include "qcs405-audio-overlay.dtsi" +#include "qcs405-geni-ir-overlay.dtsi" +#include "qcs405-circular-pca9956.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS405 EVB1 4000 SPI IOT"; + compatible = "qcom,qcs405-iot", "qcom,qcs405", "qcom,iot"; + qcom,board-id = <0x010020 0x1>; +}; + +&gdsc_mdss { + status = "disabled"; +}; + +&clock_gcc_mdss { + status = "disabled"; +}; + +&mdss_mdp { + status = "disabled"; + /delete-node/ qcom,mdss_fb_primary; +}; + +&mdss_dsi { + status = "disabled"; +}; + +&mdss_dsi0 { + status = "disabled"; +}; + +&soc { + qcom,mdss_wb_panel { + status = "disabled"; + }; +}; + +&mdss_dsi0_pll { + status = "disabled"; +}; + +&mdss_dsi1_pll { + status = "disabled"; +}; + +&soc { + mdss_spi_display: qcom,mdss_spi_display { + compatible = "qcom,mdss-spi-display"; + label = "mdss spi display"; + + mdss_fb0: qcom,mdss_fb_primary { + cell-index = <0>; + compatible = "qcom,mdss-fb"; + }; + }; +}; + +#include "spi-panel-st7789v2-qvga-cmd.dtsi" + +&soc { + mdss_spi_panel: qcom,mdss_spi_panel { + compatible = "qcom,mdss-spi-panel"; + label = "mdss spi panel"; + qcom,spi-pref-prim-pan = <&spi_st7789v2_qvga_cmd>; + qcom,mdss-spi = <&mdss_spi_display>; + qcom,mdss-fb-map = <&mdss_fb0>; + }; + + spi@78b5000 { + status = "okay"; + + spi@0 { + compatible = "qcom,spi-msm-codec-slave"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; + + spi@7af5000 { /* BLSP1 QUP2 */ + status = "ok"; + mdss_spi_client: qcom,mdss_spi_client { + reg = <0>; + compatible = "qcom,mdss-spi-client"; + label = "MDSS SPI QUP2 CLIENT"; + spi-max-frequency = <50000000>; + }; + }; +}; + +&mdss_te_active { + mux { + pins = "gpio57"; + function = "gpio"; + }; + config { + pins = "gpio57"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down*/ + }; +}; + +&mdss_te_suspend { + mux { + pins = "gpio57"; + function = "gpio"; + }; + config { + pins = "gpio57"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down*/ + }; +}; + +&pmx_mdss{ + mdss_spi_panel_active: mdss_spi_panel_active { + mux { + pins = "gpio39", "gpio42"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-high; + }; + }; + + mdss_spi_panel_suspend: mdss_spi_panel_suspend { + mux { + pins = "gpio39", "gpio42"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; +}; + +&mdss_spi_panel { + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_te_active &mdss_spi_panel_active>; + pinctrl-1 = <&mdss_te_suspend &mdss_spi_panel_suspend>; + + qcom,platform-te-gpio = <&tlmm 57 0>; + qcom,platform-reset-gpio = <&tlmm 42 0>; + qcom,platform-spi-dc-gpio = <&tlmm 39 0>; + + vddio-supply = <&pms405_l6>; + + qcom,panel-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <2800000>; + qcom,supply-max-voltage = <2800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + }; +}; + +&sdhc_2 { + /delete-property/ qcom,nonhotplug; + + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on + &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off + &sdc2_cd_off>; + cd-gpios = <&tlmm 21 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs404-iot-sku5.dts b/arch/arm/boot/dts/qcom/qcs405-iot-sku3.dts similarity index 86% rename from arch/arm64/boot/dts/qcom/qcs404-iot-sku5.dts rename to arch/arm/boot/dts/qcom/qcs405-iot-sku3.dts index c76b41fc2d37..a1814a55bcb3 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-iot-sku5.dts +++ b/arch/arm/boot/dts/qcom/qcs405-iot-sku3.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -13,15 +13,15 @@ /dts-v1/; -#include "qcs404.dtsi" +#include "qcs405.dtsi" #include "qcs405-audio-overlay.dtsi" #include "qcs405-geni-ir-overlay.dtsi" #include "qcs405-pinctrl.dtsi" #include "qcs405-circular-pca9956.dtsi" / { - model = "Qualcomm Technologies, Inc. QCS404 sEVB/SLT IOT"; - compatible = "qcom,qcs404-iot", "qcom,qcs404", "qcom,iot"; + model = "Qualcomm Technologies, Inc. QCS405 sEVB/SLT IOT"; + compatible = "qcom,qcs405-iot", "qcom,qcs405", "qcom,iot"; qcom,board-id = <0x010020 0x2>; }; #include "qcs405-mdss-panels.dtsi" diff --git a/arch/arm64/boot/dts/qcom/qcs407-iot-sku4.dts b/arch/arm/boot/dts/qcom/qcs405-iot-sku4.dts similarity index 91% rename from arch/arm64/boot/dts/qcom/qcs407-iot-sku4.dts rename to arch/arm/boot/dts/qcom/qcs405-iot-sku4.dts index 18c434306d6a..b266d4a64db6 100644 --- a/arch/arm64/boot/dts/qcom/qcs407-iot-sku4.dts +++ b/arch/arm/boot/dts/qcom/qcs405-iot-sku4.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -13,14 +13,14 @@ /dts-v1/; -#include "qcs407.dtsi" +#include "qcs405.dtsi" #include "qcs405-audio-overlay.dtsi" #include "qcs405-geni-ir-overlay.dtsi" #include "qcs405-circular-pca9956.dtsi" / { - model = "Qualcomm Technologies, Inc. QCS407 EVB1 4000 DSI IOT"; - compatible = "qcom,qcs407-iot", "qcom,qcs407", "qcom,iot"; + model = "Qualcomm Technologies, Inc. QCS405 EVB1 4000 DSI IOT"; + compatible = "qcom,qcs405-iot", "qcom,qcs405", "qcom,iot"; qcom,board-id = <0x020020 0x1>; }; diff --git a/arch/arm/boot/dts/qcom/qcs405-iot-sku5.dts b/arch/arm/boot/dts/qcom/qcs405-iot-sku5.dts new file mode 100644 index 000000000000..bd92c176147e --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-iot-sku5.dts @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "qcs405.dtsi" +#include "qcs405-nowcd-audio-overlay.dtsi" +#include "qcs405-geni-ir-overlay.dtsi" +#include "qcs405-circular-pca9956.dtsi" +#include "qcs405-mdss-panels.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS405 EVB1 4000 RGB IOT"; + compatible = "qcom,qcs405-iot", "qcom,qcs405", "qcom,iot"; + qcom,board-id = <0x030020 0x1>; +}; + +&mdss_dsi { + status = "disabled"; +}; + +&mdss_dsi0 { + status = "disabled"; +}; + +&mdss_hdmi_tx { + status = "disabled"; +}; + +&msm_ext_disp { + status = "disabled"; +}; + +&mdss_mdp { + qcom,mdss-pref-prim-intf = "rgb"; +}; + +&mdss_rgb { + qcom,rgb-panel = <&rgb_st7789v>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_rgb_active &mdss_rgb_data0_active + &mdss_rgb_data1_active &mdss_rgb_data2_active + &mdss_rgb_data3_active &mdss_rgb_data4_active + &mdss_rgb_data5_active &mdss_rgb_data_b0_active + &mdss_rgb_data_b1_active &mdss_rgb_data_b2_active + &mdss_rgb_data_b3_active &mdss_rgb_data_b4_active + &mdss_rgb_data_b5_active &mdss_rgb_hsync_active + &mdss_rgb_vsync_active &mdss_rgb_de_active + &mdss_rgb_clk_active>; + pinctrl-1 = <&mdss_rgb_suspend &mdss_rgb_data0_suspend + &mdss_rgb_data1_suspend &mdss_rgb_data2_suspend + &mdss_rgb_data3_suspend &mdss_rgb_data4_suspend + &mdss_rgb_data5_suspend &mdss_rgb_data_b0_suspend + &mdss_rgb_data_b1_suspend &mdss_rgb_data_b2_suspend + &mdss_rgb_data_b3_suspend &mdss_rgb_data_b4_suspend + &mdss_rgb_data_b5_suspend &mdss_rgb_hsync_suspend + &mdss_rgb_vsync_suspend &mdss_rgb_de_suspend + &mdss_rgb_clk_suspend>; + qcom,platform-reset-gpio = <&tlmm 58 0>; +}; + +&rgb_st7789v { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&spi_1 { + status = "ok"; + mdss_rgb_spi: qcom,mdss_rgb_spi@0 { + compatible = "qcom,mdss-rgb-spi"; + reg = <0>; + spi-max-frequency = <5000000>; + }; +}; + +&soc { + gpio_keys { + status = "disabled"; + }; + spi@78b5000 { + status = "ok"; + spi@0 { + compatible = "qcom,spi-msm-codec-slave"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-iot-sku6.dts b/arch/arm/boot/dts/qcom/qcs405-iot-sku6.dts new file mode 100644 index 000000000000..dddd2f01b5d1 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-iot-sku6.dts @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "qcs405.dtsi" +#include "qcs405-csra1-audio-overlay.dtsi" +#include "qcs405-geni-ir-overlay.dtsi" +#include "qcs405-circular-pca9956.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS405 EVB1 4000 CSRA1 IOT"; + compatible = "qcom,qcs405-iot", "qcom,qcs405", "qcom,iot"; + qcom,board-id = <0x040020 0x1>; +}; + +#include "qcs405-mdss-panels.dtsi" + +&mdss_mdp { + qcom,mdss-pref-prim-intf = "dsi"; +}; + +&mdss_dsi { + hw-config = "single_dsi"; +}; + +&mdss_dsi0 { + qcom,dsi-pref-prim-pan = <&dsi_hx8394d_720_vid>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; + pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 41 0>; + qcom,platform-reset-gpio = <&tlmm 39 0>; + qcom,platform-bklight-en-gpio = <&tlmm 48 0>; +}; + +&dsi_hx8394d_720_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_tlmm_gpio"; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&soc { + spi@78b5000 { + status = "ok"; + spi@0 { + compatible = "qcom,spi-msm-codec-slave"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; + + gpio_keys { + /delete-node/ vol_mute; + }; +}; + +&pcie0 { + pinctrl-0 = <&pcie0_perst_default &pcie0_wake_default>; + wake-gpio = <&tlmm 21 0>; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-iot-sku7.dts b/arch/arm/boot/dts/qcom/qcs405-iot-sku7.dts new file mode 100644 index 000000000000..8fa169c5d532 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-iot-sku7.dts @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "qcs405.dtsi" +#include "qcs405-csra6-audio-overlay.dtsi" +#include "qcs405-geni-ir-overlay.dtsi" +#include "qcs405-linear-pca9956.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS405 EVB1 4000 CSRA6 IOT"; + compatible = "qcom,qcs405-iot", "qcom,qcs405", "qcom,iot"; + qcom,board-id = <0x050020 0x1>; +}; + +#include "qcs405-mdss-panels.dtsi" + +&mdss_mdp { + qcom,mdss-pref-prim-intf = "dsi"; +}; + +&mdss_dsi { + hw-config = "single_dsi"; +}; + +&mdss_dsi0 { + qcom,dsi-pref-prim-pan = <&dsi_hx8394d_720_vid>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; + pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 41 0>; + qcom,platform-reset-gpio = <&tlmm 39 0>; + qcom,platform-bklight-en-gpio = <&tlmm 48 0>; +}; + +&dsi_hx8394d_720_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_tlmm_gpio"; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&soc { + spi@78b5000 { + status = "ok"; + spi@0 { + compatible = "qcom,spi-msm-codec-slave"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs407-iot-sku6.dts b/arch/arm/boot/dts/qcom/qcs405-iot-sku8.dts similarity index 82% rename from arch/arm64/boot/dts/qcom/qcs407-iot-sku6.dts rename to arch/arm/boot/dts/qcom/qcs405-iot-sku8.dts index 46d06b57b181..0f99af089c34 100644 --- a/arch/arm64/boot/dts/qcom/qcs407-iot-sku6.dts +++ b/arch/arm/boot/dts/qcom/qcs405-iot-sku8.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -13,15 +13,15 @@ /dts-v1/; -#include "qcs407.dtsi" -#include "qcs405-csra1-audio-overlay.dtsi" +#include "qcs405.dtsi" +#include "qcs405-amic-audio-overlay.dtsi" #include "qcs405-geni-ir-overlay.dtsi" #include "qcs405-circular-pca9956.dtsi" / { - model = "Qualcomm Technologies, Inc. QCS407 EVB1 4000 CSRA1 IOT"; - compatible = "qcom,qcs407-iot", "qcom,qcs407", "qcom,iot"; - qcom,board-id = <0x040020 0x1>; + model = "Qualcomm Technologies, Inc. QCS405 EVB1 4k with AMIC"; + compatible = "qcom,qcs405-iot", "qcom,qcs405", "qcom,iot"; + qcom,board-id = <0x060020 0x1>; }; #include "qcs405-mdss-panels.dtsi" diff --git a/arch/arm64/boot/dts/qcom/qcs407-iot-sku9.dts b/arch/arm/boot/dts/qcom/qcs405-iot-sku9.dts similarity index 91% rename from arch/arm64/boot/dts/qcom/qcs407-iot-sku9.dts rename to arch/arm/boot/dts/qcom/qcs405-iot-sku9.dts index ffb93e7e053c..3fd2b6a569af 100644 --- a/arch/arm64/boot/dts/qcom/qcs407-iot-sku9.dts +++ b/arch/arm/boot/dts/qcom/qcs405-iot-sku9.dts @@ -13,14 +13,14 @@ /dts-v1/; -#include "qcs407.dtsi" +#include "qcs405.dtsi" #include "qcs405-audio-overlay.dtsi" #include "qcs405-circular-pca9956.dtsi" #include "qcs405-pinctrl.dtsi" / { - model = "Qualcomm Technologies, Inc. QCS407 RCM IOT"; - compatible = "qcom,qcs407-iot", "qcom,qcs407", "qcom,iot"; + model = "Qualcomm Technologies, Inc. QCS405 RCM IOT"; + compatible = "qcom,qcs405-iot", "qcom,qcs405", "qcom,iot"; qcom,board-id = <0x010015 0x0>; }; diff --git a/arch/arm/boot/dts/qcom/qcs405-linear-pca9956.dtsi b/arch/arm/boot/dts/qcom/qcs405-linear-pca9956.dtsi new file mode 100644 index 000000000000..aa18e3b0ddd7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-linear-pca9956.dtsi @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&va_macro { + qcom,va-dmic-sample-rate = <2400000>; +}; + +&i2c_2 { + status = "ok"; + qcom,clk-freq-out = <100000>; + + /* PCA9956B LED Drivers */ + nxp-ledseg-i2c@65 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca9956b"; + reg = <0x65>; + pca9956b,support_initialize = <1>; + pca9956b,mode1 = <0x09>; + pca9956b,mode2 = <0x05>; + + pca9956b,ledout0 = <0xAA>; + pca9956b,ledout1 = <0xAA>; + pca9956b,ledout2 = <0xAA>; + pca9956b,ledout3 = <0xFF>; + pca9956b,ledout4 = <0xFF>; + pca9956b,ledout5 = <0xFF>; + pca9956b,defaultiref = <0x2f>; + out0@0 { + label = "ledsec5_b"; + reg = <0x0>; + }; + out1@1 { + label = "ledsec5_g"; + reg = <0x1>; + }; + out2@2 { + label = "ledsec5_r"; + reg = <0x2>; + }; + out3@3 { + label = "ledsec6_b"; + reg = <0x3>; + }; + out4@4 { + label = "ledsec6_g"; + reg = <0x4>; + }; + out5@5 { + label = "ledsec6_r"; + reg = <0x5>; + }; + out6@6 { + label = "ledsec7_b"; + reg = <0x6>; + }; + out7@7 { + label = "ledsec7_g"; + reg = <0x7>; + }; + out8@8 { + label = "ledsec7_r"; + reg = <0x8>; + }; + out9@9 { + label = "ledsec8_b"; + reg = <0x9>; + }; + out10@10 { + label = "ledsec8_g"; + reg = <0xA>; + }; + out11@11 { + label = "ledsec8_r"; + reg = <0xB>; + }; + out12@12 { + label = "ledsec1_b"; + reg = <0xC>; + }; + out13@13 { + label = "ledsec1_g"; + reg = <0xD>; + }; + out14@14 { + label = "ledsec1_r"; + reg = <0xE>; + }; + out15@15 { + label = "ledsec2_b"; + reg = <0xF>; + }; + out16@16 { + label = "ledsec2_g"; + reg = <0x10>; + }; + out17@17 { + label = "ledsec2_r"; + reg = <0x11>; + }; + out18@18 { + label = "ledsec3_b"; + reg = <0x12>; + }; + out19@19 { + label = "ledsec3_g"; + reg = <0x13>; + }; + out20@20 { + label = "ledsec3_r"; + reg = <0x14>; + }; + out21@21 { + label = "ledsec4_b"; + reg = <0x15>; + }; + out22@22 { + label = "ledsec4_g"; + reg = <0x16>; + }; + out23@23 { + label = "ledsec4_r"; + reg = <0x17>; + }; + }; + + nxp-ledseg-i2c@15 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,pca9956b"; + reg = <0x15>; + pca9956b,support_initialize = <1>; + pca9956b,mode1 = <0x09>; + pca9956b,mode2 = <0x05>; + + pca9956b,ledout0 = <0xAA>; + pca9956b,ledout1 = <0xAA>; + pca9956b,ledout2 = <0xAA>; + pca9956b,ledout3 = <0xFF>; + pca9956b,ledout4 = <0xFF>; + pca9956b,ledout5 = <0xFF>; + pca9956b,defaultiref = <0x2f>; + out0@0 { + label = "ledsec13_b"; + reg = <0x0>; + }; + out1@1 { + label = "ledsec13_g"; + reg = <0x1>; + }; + out2@2 { + label = "ledsec13_r"; + reg = <0x2>; + }; + out3@3 { + label = "ledsec14_b"; + reg = <0x3>; + }; + out4@4 { + label = "ledsec14_g"; + reg = <0x4>; + }; + out5@5 { + label = "ledsec14_r"; + reg = <0x5>; + }; + out6@6 { + label = "ledsec15_b"; + reg = <0x6>; + }; + out7@7 { + label = "ledsec15_g"; + reg = <0x7>; + }; + out8@8 { + label = "ledsec15_r"; + reg = <0x8>; + }; + out9@9 { + label = "ledsec16_b"; + reg = <0x9>; + }; + out10@10 { + label = "ledsec16_g"; + reg = <0xA>; + }; + out11@11 { + label = "ledsec16_r"; + reg = <0xB>; + }; + out12@12 { + label = "ledsec9_b"; + reg = <0xC>; + }; + out13@13 { + label = "ledsec9_g"; + reg = <0xD>; + }; + out14@14 { + label = "ledsec9_r"; + reg = <0xE>; + }; + out15@15 { + label = "ledsec10_b"; + reg = <0xF>; + }; + out16@16 { + label = "ledsec10_g"; + reg = <0x10>; + }; + out17@17 { + label = "ledsec10_r"; + reg = <0x11>; + }; + out18@18 { + label = "ledsec11_b"; + reg = <0x12>; + }; + out19@19 { + label = "ledsec11_g"; + reg = <0x13>; + }; + out20@20 { + label = "ledsec11_r"; + reg = <0x14>; + }; + out21@21 { + label = "ledsec12_b"; + reg = <0x15>; + }; + out22@22 { + label = "ledsec12_g"; + reg = <0x16>; + }; + out23@23 { + label = "ledsec12_r"; + reg = <0x17>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-lpi.dtsi b/arch/arm/boot/dts/qcom/qcs405-lpi.dtsi new file mode 100644 index 000000000000..ef7a3c487e9b --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-lpi.dtsi @@ -0,0 +1,484 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&q6core { + lpi_tlmm: lpi_pinctrl@C070000 { + compatible = "qcom,lpi-pinctrl"; + reg = <0x0C070000 0x0>; + qcom,num-gpios = <21>; + gpio-controller; + #gpio-cells = <2>; + qcom,lpi-offset-tbl = <0x00000010>, <0x00000020>, + <0x00000030>, <0x00000040>, + <0x00000050>, <0x00000060>, + <0x00000070>, <0x00000080>, + <0x00000090>, <0x00000100>, + <0x00000110>, <0x00000120>, + <0x00000130>, <0x00000140>, + <0x00000150>, <0x00000160>, + <0x00000170>, <0x00000180>, + <0x00000190>, <0x00000200>, + <0x00000210>; + clock-names = "lpass_core_hw_vote"; + clocks = <&lpass_core_hw_vote 0>; + cdc_dmic01_clk_active: dmic01_clk_active { + mux { + pins = "gpio8"; + function = "func1"; + }; + + config { + pins = "gpio8"; + drive-strength = <8>; + output-high; + }; + }; + + cdc_dmic01_clk_sleep: dmic01_clk_sleep { + mux { + pins = "gpio8"; + function = "func1"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_dmic01_data_active: dmic01_data_active { + mux { + pins = "gpio9"; + function = "func1"; + }; + + config { + pins = "gpio9"; + drive-strength = <8>; + input-enable; + }; + }; + + cdc_dmic01_data_sleep: dmic01_data_sleep { + mux { + pins = "gpio9"; + function = "func1"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; + pull-down; + input-enable; + }; + }; + + cdc_dmic23_clk_active: dmic23_clk_active { + mux { + pins = "gpio10"; + function = "func1"; + }; + + config { + pins = "gpio10"; + drive-strength = <8>; + output-high; + }; + }; + + cdc_dmic23_clk_sleep: dmic23_clk_sleep { + mux { + pins = "gpio10"; + function = "func1"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_dmic23_data_active: dmic23_data_active { + mux { + pins = "gpio11"; + function = "func1"; + }; + + config { + pins = "gpio11"; + drive-strength = <8>; + input-enable; + }; + }; + + cdc_dmic23_data_sleep: dmic23_data_sleep { + mux { + pins = "gpio11"; + function = "func1"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; + pull-down; + input-enable; + }; + }; + + cdc_dmic45_clk_active: dmic45_clk_active { + mux { + pins = "gpio12"; + function = "func1"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; + output-high; + }; + }; + + cdc_dmic45_clk_sleep: dmic45_clk_sleep { + mux { + pins = "gpio12"; + function = "func1"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_dmic45_data_active: dmic45_data_active { + mux { + pins = "gpio13"; + function = "func1"; + }; + + config { + pins = "gpio13"; + drive-strength = <8>; + input-enable; + }; + }; + + cdc_dmic45_data_sleep: dmic45_data_sleep { + mux { + pins = "gpio13"; + function = "func1"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; + pull-down; + input-enable; + }; + }; + + cdc_dmic67_clk_active: dmic67_clk_active { + mux { + pins = "gpio14"; + function = "func1"; + }; + + config { + pins = "gpio14"; + drive-strength = <8>; + output-high; + }; + }; + + cdc_dmic67_clk_sleep: dmic67_clk_sleep { + mux { + pins = "gpio14"; + function = "func1"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_dmic67_data_active: dmic67_data_active { + mux { + pins = "gpio15"; + function = "func1"; + }; + + config { + pins = "gpio15"; + drive-strength = <8>; + input-enable; + }; + }; + + cdc_dmic67_data_sleep: dmic67_data_sleep { + mux { + pins = "gpio15"; + function = "func1"; + }; + + config { + pins = "gpio15"; + drive-strength = <2>; + pull-down; + input-enable; + }; + }; + + quin_mi2s_sck { + quin_mi2s_sck_sleep: quin_mi2s_sck_sleep { + mux { + pins = "gpio8"; + function = "func2"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_mi2s_sck_active: quin_mi2s_sck_active { + mux { + pins = "gpio8"; + function = "func2"; + }; + + config { + pins = "gpio8"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quin_mi2s_ws { + quin_mi2s_ws_sleep: quin_mi2s_ws_sleep { + mux { + pins = "gpio9"; + function = "func2"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_mi2s_ws_active: quin_mi2s_ws_active { + mux { + pins = "gpio9"; + function = "func2"; + }; + + config { + pins = "gpio9"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quin_mi2s_sd0 { + quin_mi2s_sd0_sleep: quin_mi2s_sd0_sleep { + mux { + pins = "gpio10"; + function = "func2"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_mi2s_sd0_active: quin_mi2s_sd0_active { + mux { + pins = "gpio10"; + function = "func2"; + }; + + config { + pins = "gpio10"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quin_mi2s_sd1 { + quin_mi2s_sd1_sleep: quin_mi2s_sd1_sleep { + mux { + pins = "gpio11"; + function = "func2"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_mi2s_sd1_active: quin_mi2s_sd1_active { + mux { + pins = "gpio11"; + function = "func2"; + }; + + config { + pins = "gpio11"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + quin_mi2s_sd2 { + quin_mi2s_sd2_sleep: quin_mi2s_sd2_sleep { + mux { + pins = "gpio12"; + function = "func2"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_mi2s_sd2_active: quin_mi2s_sd2_active { + mux { + pins = "gpio12"; + function = "func2"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quin_mi2s_sd3 { + quin_mi2s_sd3_sleep: quin_mi2s_sd3_sleep { + mux { + pins = "gpio13"; + function = "func2"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_mi2s_sd3_active: quin_mi2s_sd3_active { + mux { + pins = "gpio13"; + function = "func2"; + }; + + config { + pins = "gpio13"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + wsa_swr_clk_pin { + wsa_swr_clk_sleep: wsa_swr_clk_sleep { + mux { + pins = "gpio5"; + function = "func1"; + }; + + config { + pins = "gpio5"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + wsa_swr_clk_active: wsa_swr_clk_active { + mux { + pins = "gpio5"; + function = "func1"; + }; + + config { + pins = "gpio5"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + }; + + wsa_swr_data_pin { + wsa_swr_data_sleep: wsa_swr_data_sleep { + mux { + pins = "gpio20"; + function = "func1"; + }; + + config { + pins = "gpio20"; + drive-strength = <4>; + bias-bus-hold; + }; + }; + + wsa_swr_data_active: wsa_swr_data_active { + mux { + pins = "gpio20"; + function = "func1"; + }; + + config { + pins = "gpio20"; + drive-strength = <4>; + bias-bus-hold; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-mdss-panels.dtsi b/arch/arm/boot/dts/qcom/qcs405-mdss-panels.dtsi new file mode 100644 index 000000000000..71b90990eb4a --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-mdss-panels.dtsi @@ -0,0 +1,31 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "dsi-panel-hx8394d-720p-video.dtsi" +#include "rgb-panel-st7789v.dtsi" + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <1>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1704000>; + qcom,supply-max-voltage = <1896000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-mdss-pll.dtsi b/arch/arm/boot/dts/qcom/qcs405-mdss-pll.dtsi new file mode 100644 index 000000000000..06e7d18e97bd --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-mdss-pll.dtsi @@ -0,0 +1,126 @@ +/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + mdss_dsi0_pll: qcom,mdss_dsi_pll@1a94a00 { + compatible = "qcom,mdss_dsi_pll_28lpm"; + label = "MDSS DSI 0 PLL"; + cell-index = <0>; + #clock-cells = <1>; + + reg = <0x01a94a00 0xd4>, + <0x0184d074 0x8>; + reg-names = "pll_base", "gdsc_base"; + + clocks = <&clock_gcc GCC_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + clock-rate = <0>; + + gdsc-supply = <&gdsc_mdss>; + + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,ssc-frequency-hz = <30000>; + qcom,ssc-ppm = <5000>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1_pll: qcom,mdss_dsi_pll@1a96a00 { + status="disabled"; + compatible = "qcom,mdss_dsi_pll_28lpm"; + label = "MDSS DSI 1 PLL"; + cell-index = <1>; + #clock-cells = <1>; + + reg = <0x01a96a00 0xd4>, + <0x0184d074 0x8>; + reg-names = "pll_base", "gdsc_base"; + + clocks = <&clock_gcc GCC_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + clock-rate = <0>; + + gdsc-supply = <&gdsc_mdss>; + + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,ssc-frequency-hz = <30000>; + qcom,ssc-ppm = <5000>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_hdmi_pll: qcom,mdss_hdmi_pll@0x1aa0600 { + compatible = "qcom,mdss_hdmi_pll_28lpm"; + label = "MDSS HDMI PLL"; + cell-index = <0>; + #clock-cells = <1>; + + reg = <0x1aa0600 0x49c>, + <0x0184d074 0x8>; + reg-names = "pll_base", "gdsc_base"; + + gdsc-supply = <&gdsc_mdss>; + vddx-pll-supply = <&pms405_l5>; + + clocks = <&clock_gcc GCC_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + clock-rate = <0>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + qcom,platform-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vddx-pll"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <14300>; + qcom,supply-disable-load = <1>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-mdss.dtsi b/arch/arm/boot/dts/qcom/qcs405-mdss.dtsi new file mode 100644 index 000000000000..ed939ade0dca --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-mdss.dtsi @@ -0,0 +1,466 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@1a00000 { + compatible = "qcom,mdss_mdp"; + reg = <0x01a00000 0x90000>, + <0x01ab0000 0x1040>; + reg-names = "mdp_phys", "vbif_phys"; + interrupts = <0 72 0>; + vdd-supply = <&gdsc_mdss>; + + /* Bus Scale Settings */ + qcom,msm-bus,name = "mdss_mdp"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 6400000>, + <22 512 0 6400000>; + + /* Fudge factors */ + qcom,mdss-ab-factor = <1 1>; /* 1 time */ + qcom,mdss-ib-factor = <1 1>; /* 1 time */ + qcom,mdss-clk-factor = <105 100>; /* 1.05 times */ + + qcom,max-mixer-width = <2048>; + qcom,max-pipe-width = <2048>; + + /* VBIF QoS remapper settings*/ + qcom,mdss-vbif-qos-rt-setting = <1 2 2 2>; + qcom,mdss-vbif-qos-nrt-setting = <1 1 1 1>; + + qcom,mdss-has-panic-ctrl; + qcom,mdss-per-pipe-panic-luts = <0x000f>, + <0x0>, + <0xfffc>, + <0x0>; + + qcom,mdss-mdp-reg-offset = <0x00001000>; + qcom,max-bandwidth-low-kbps = <1800000>; + qcom,max-bandwidth-high-kbps = <1800000>; + qcom,max-bandwidth-per-pipe-kbps = <1000000>; + + /* Bandwidth limit settings */ + qcom,max-bw-settings = <1 3100000>, /* Default */ + <2 1700000>; /* Camera */ + + qcom,max-clk-rate = <320000000>; + qcom,mdss-default-ot-rd-limit = <32>; + qcom,mdss-default-ot-wr-limit = <16>; + + qcom,mdss-pipe-vig-off = <0x00005000>; + qcom,mdss-pipe-rgb-off = <0x00015000 0x00017000>; + qcom,mdss-pipe-dma-off = <0x00025000>; + qcom,mdss-pipe-cursor-off = <0x00035000>; + + qcom,mdss-pipe-vig-xin-id = <0>; + qcom,mdss-pipe-rgb-xin-id = <1 5>; + qcom,mdss-pipe-dma-xin-id = <2>; + qcom,mdss-pipe-cursor-xin-id = <7>; + + /* Offsets relative to "mdp_phys + mdp-reg-offset" address */ + qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x2AC 0 0>; + qcom,mdss-pipe-rgb-clk-ctrl-offsets = <0x2AC 4 8>, + <0x2B4 4 8>; + qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2AC 8 12>; + qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3A8 16 15>; + + + qcom,mdss-ctl-off = <0x00002000 0x00002200 0x00002400 + 0x00002600 0x00002800>; + qcom,mdss-mixer-intf-off = <0x00045000 0x00046000>; + qcom,mdss-dspp-off = <0x00055000>; + qcom,mdss-wb-off = <0x00066000>; + qcom,mdss-intf-off = <0x00000000 0x0006B800 + 0x00000000 0x0006C800>; + qcom,mdss-pingpong-off = <0x00071000 0x00071800>; + qcom,mdss-wfd-mode = "intf"; + qcom,mdss-has-decimation; + qcom,mdss-has-non-scalar-rgb; + qcom,mdss-has-rotator-downscale; + qcom,mdss-rot-downscale-min = <2>; + qcom,mdss-rot-downscale-max = <16>; + qcom,mdss-idle-power-collapse-enabled; + qcom,mdss-rot-block-size = <64>; + + clocks = <&clock_gcc GCC_MDSS_AHB_CLK>, + <&clock_gcc GCC_MDSS_AXI_CLK>, + <&clock_gcc GCC_MDSS_MDP_CLK>, + <&clock_gcc_mdss MDSS_MDP_VOTE_CLK>, + <&clock_gcc GCC_MDSS_VSYNC_CLK>, + <&clock_gcc GCC_BIMC_MDSS_CLK>; + clock-names = "iface_clk", "bus_clk", "core_clk_src", + "core_clk", "vsync_clk", "bimc_clk"; + + qcom,mdp-settings = <0x0506c 0x00000000>, + <0x1506c 0x00000000>, + <0x1706c 0x00000000>, + <0x2506c 0x00000000>; + + qcom,regs-dump-mdp = <0x01000 0x01454>, + <0x02000 0x02064>, + <0x02200 0x02264>, + <0x02400 0x02464>, + <0x05000 0x05150>, + <0x05200 0x05230>, + <0x15000 0x15150>, + <0x17000 0x17150>, + <0x25000 0x25150>, + <0x35000 0x35150>, + <0x45000 0x452bc>, + <0x46000 0x462bc>, + <0x55000 0x5522c>, + <0x65000 0x652c0>, + <0x66000 0x662c0>, + <0x6b800 0x6ba68>, + <0x6c800 0x6c268>, + <0x71000 0x710d4>, + <0x71800 0x718d4>; + + qcom,regs-dump-names-mdp = "MDP", + "CTL_0", "CTL_1", "CTL_2", + "VIG0_SSPP", "VIG0", + "RGB0_SSPP", "RGB1_SSPP", + "DMA0_SSPP", + "CURSOR0_SSPP", + "LAYER_0", "LAYER_1", + "DSPP_0", + "WB_0", "WB_2", + "INTF_1", "INTF_3", + "PP_0", "PP_1"; + + /* buffer parameters to calculate prefill bandwidth */ + qcom,mdss-prefill-outstanding-buffer-bytes = <0>; + qcom,mdss-prefill-y-buffer-bytes = <0>; + qcom,mdss-prefill-scaler-buffer-lines-bilinear = <2>; + qcom,mdss-prefill-scaler-buffer-lines-caf = <4>; + qcom,mdss-prefill-post-scaler-buffer-pixels = <2048>; + qcom,mdss-prefill-pingpong-buffer-pixels = <4096>; + + qcom,mdss-pp-offsets { + qcom,mdss-sspp-mdss-igc-lut-off = <0x2000>; + qcom,mdss-sspp-vig-pcc-off = <0x1780>; + qcom,mdss-sspp-rgb-pcc-off = <0x380>; + qcom,mdss-sspp-dma-pcc-off = <0x380>; + qcom,mdss-lm-pgc-off = <0x3C0>; + qcom,mdss-dspp-pcc-off = <0x1700>; + qcom,mdss-dspp-pgc-off = <0x17C0>; + }; + + qcom,mdss-reg-bus { + /* Reg Bus Scale Settings */ + qcom,msm-bus,name = "mdss_reg"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,active-only; + qcom,msm-bus,vectors-KBps = + <1 590 0 0>, + <1 590 0 76800>, + <1 590 0 160000>, + <1 590 0 320000>; + }; + + qcom,mdss-hw-rt-bus { + /* Bus Scale Settings */ + qcom,msm-bus,name = "mdss_hw_rt"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 1000>; + }; + + smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb { + compatible = "qcom,smmu_mdp_unsec"; + iommus = <&apps_smmu 0xC00 0>; /* For NS ctx bank */ + }; + + mdss_fb0: qcom,mdss_fb_primary { + cell-index = <0>; + compatible = "qcom,mdss-fb"; + }; + + mdss_fb1: qcom,mdss_fb_hdmi { + cell-index = <1>; + compatible = "qcom,mdss-fb"; + qcom,mdss-intf = <&mdss_hdmi_tx>; + }; + + mdss_fb2: qcom,mdss_fb_wfd { + cell-index = <2>; + compatible = "qcom,mdss-fb"; + }; + }; + + mdss_rgb: qcom,mdss_rgb@0 { + compatible = "qcom,mdss-rgb"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x1a94400 0x1a94400 0x280 + 0x1a94b80 0x1a94b80 0x30 + 0x193e000 0x193e000 0x30>; + + reg = <0x1a94400 0x280>, + <0x1a94b80 0x30>, + <0x193e000 0x30>; + reg-names = "dsi_phy", + "dsi_phy_regulator", "mmss_misc_phys"; + + gdsc-supply = <&gdsc_mdss>; + vdda-1p2-supply = <&pms405_l4>; + vdda-1p8-supply = <&pms405_l5>; + vddio-supply = <&pms405_l6>; + + /* Bus Scale Settings */ + qcom,msm-bus,name = "mdss_rgb"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 1000>; + + clocks = <&clock_gcc_mdss MDSS_MDP_VOTE_CLK>, + <&clock_gcc GCC_MDSS_AHB_CLK>, + <&clock_gcc GCC_MDSS_AXI_CLK>, + <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>, + <&mdss_dsi0_pll PCLK_SRC_0_CLK>, + <&clock_gcc_mdss GCC_MDSS_BYTE0_CLK>, + <&clock_gcc_mdss GCC_MDSS_PCLK0_CLK>, + <&clock_gcc GCC_MDSS_ESC0_CLK>, + <&clock_gcc_mdss BYTE0_CLK_SRC>, + <&clock_gcc_mdss PCLK0_CLK_SRC>; + clock-names = "mdp_core_clk", "iface_clk", "bus_clk", + "ext_byte0_clk", "ext_pixel0_clk", + "byte_clk", "pixel_clk", "core_clk", + "byte_clk_rcg", "pixel_clk_rcg"; + + qcom,mdss-fb-map = <&mdss_fb0>; + qcom,mdss-mdp = <&mdss_mdp>; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p8"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + }; + }; + + mdss_dsi: qcom,mdss_dsi@0 { + compatible = "qcom,mdss-dsi"; + hw-config = "single_dsi"; + #address-cells = <1>; + #size-cells = <1>; + gdsc-supply = <&gdsc_mdss>; + vdda-1p2-supply = <&pms405_l4>; + vdda-1p8-supply = <&pms405_l5>; + + /* Bus Scale Settings */ + qcom,msm-bus,name = "mdss_dsi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 1000>; + + ranges = <0x1a94000 0x1a94000 0x300 + 0x1a94400 0x1a94400 0x280 + 0x1a94b80 0x1a94b80 0x30 + 0x193e000 0x193e000 0x30 + 0x1a96000 0x1a96000 0x300 + 0x1a96400 0x1a96400 0x280 + 0x1a96b80 0x1a96b80 0x30 + 0x193e000 0x193e000 0x30>; + + clocks = <&clock_gcc_mdss MDSS_MDP_VOTE_CLK>, + <&clock_gcc GCC_MDSS_AHB_CLK>, + <&clock_gcc GCC_MDSS_AXI_CLK>, + <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>, + <&mdss_dsi0_pll PCLK_SRC_0_CLK>; + clock-names = "mdp_core_clk", "iface_clk", "bus_clk", + "ext_byte0_clk", "ext_pixel0_clk"; + + qcom,mmss-ulp-clamp-ctrl-offset = <0x20>; + qcom,mmss-phyreset-ctrl-offset = <0x24>; + + qcom,mdss-fb-map-prim = <&mdss_fb0>; + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p8"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@1a94000 { + compatible = "qcom,mdss-dsi-ctrl"; + label = "MDSS DSI CTRL->0"; + cell-index = <0>; + reg = <0x1a94000 0x300>, + <0x1a94400 0x280>, + <0x1a94b80 0x30>, + <0x193e000 0x30>; + reg-names = "dsi_ctrl", "dsi_phy", + "dsi_phy_regulator", "mmss_misc_phys"; + + qcom,timing-db-mode; + qcom,mdss-mdp = <&mdss_mdp>; + vddio-supply = <&pms405_l6>; + + clocks = <&clock_gcc_mdss GCC_MDSS_BYTE0_CLK>, + <&clock_gcc_mdss GCC_MDSS_PCLK0_CLK>, + <&clock_gcc GCC_MDSS_ESC0_CLK>, + <&clock_gcc_mdss BYTE0_CLK_SRC>, + <&clock_gcc_mdss PCLK0_CLK_SRC>; + clock-names = "byte_clk", "pixel_clk", "core_clk", + "byte_clk_rcg", "pixel_clk_rcg"; + + qcom,platform-strength-ctrl = [ff 06]; + qcom,platform-bist-ctrl = [00 00 b1 ff 00 00]; + qcom,platform-regulator-settings = [03 08 07 00 + 20 07 01]; + qcom,platform-lane-config = [01 c0 00 00 00 00 00 01 97 + 01 c0 00 00 05 00 00 01 97 + 01 c0 00 00 0a 00 00 01 97 + 01 c0 00 00 0f 00 00 01 97 + 00 40 00 00 00 00 00 01 ff]; + }; + }; + + msm_ext_disp: qcom,msm_ext_disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + qcom,msm_ext_disp = <&msm_ext_disp>; + }; + }; + + mdss_hdmi_tx: qcom,hdmi_tx@1aa0000 { + cell-index = <0>; + compatible = "qcom,hdmi-tx"; + + reg = <0x1aa0000 0x50c>, + <0xa0000 0x6400>, + <0x1ae0000 0x28>; + reg-names = "core_physical", "qfprom_physical", "hdcp_physical"; + + hpd-gdsc-supply = <&gdsc_mdss>; + + qcom,supply-names = "hpd-gdsc"; + qcom,min-voltage-level = <0>; + qcom,max-voltage-level = <0>; + qcom,enable-load = <0>; + qcom,disable-load = <0>; + + qcom,msm_ext_disp = <&msm_ext_disp>; + + clocks = <&clock_gcc GCC_MDSS_AHB_CLK>, + <&clock_gcc_mdss MDSS_MDP_VOTE_CLK>, + <&clock_gcc GCC_MDSS_HDMI_APP_CLK>, + <&clock_gcc GCC_MDSS_HDMI_PCLK_CLK>, + <&clock_gcc HDMI_PCLK_CLK_SRC>, + <&mdss_hdmi_pll HDMI_PCLK_SRC>; + + clock-names = "hpd_iface_clk", "hpd_mdp_core_clk", + "hpd_core_clk", "core_extp_clk", + "hdmi_pclk_rcg", "ext_hdmi_pixel_clk"; + + qcom,mdss-fb-map = <&mdss_fb1>; + qcom,pluggable; + qcom,max-pclk-frequency-khz = <148500>; + }; + + qcom,mdss_wb_panel { + status = "disabled"; + compatible = "qcom,mdss_wb"; + qcom,mdss_pan_res = <640 640>; + qcom,mdss_pan_bpp = <24>; + qcom,mdss-fb-map = <&mdss_fb2>; + }; + +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-mhi.dtsi b/arch/arm/boot/dts/qcom/qcs405-mhi.dtsi new file mode 100644 index 000000000000..12ba814820f3 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-mhi.dtsi @@ -0,0 +1,716 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&pcie_rc0 { + reg = <0 0 0 0 0>; + + mhi_0: qcom,mhi@0 { + reg = <0 0 0 0 0 >; + + pci-ids = "17cb:0304"; + + /* controller specific configuration */ + qcom,smmu-cfg = <0x0>; + qcom,msm-bus,name = "mhi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 1200000000 650000000>; + + /* mhi bus specific settings */ + mhi,max-channels = <110>; + mhi,timeout = <2000>; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@14 { + reg = <14>; + label = "QMI0"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@15 { + reg = <15>; + label = "QMI0"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@16 { + reg = <16>; + label = "QMI1"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@17 { + reg = <17>; + label = "QMI1"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,auto-queue; + mhi,auto-start; + }; + + mhi_chan@32 { + reg = <32>; + label = "DUN"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@33 { + reg = <33>; + label = "DUN"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@46 { + reg = <46>; + label = "IP_SW_0"; + mhi,num-elements = <512>; + mhi,event-ring = <4>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@47 { + reg = <47>; + label = "IP_SW_0"; + mhi,num-elements = <512>; + mhi,event-ring = <5>; + mhi,chan-dir = <2>; + mhi,data-type = <4>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@100 { + reg = <100>; + label = "IP_HW0"; + mhi,num-elements = <512>; + mhi,event-ring = <6>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <3>; + mhi,ee = <0x4>; + mhi,db-mode-switch; + }; + + mhi_chan@101 { + reg = <101>; + label = "IP_HW0"; + mhi,num-elements = <512>; + mhi,event-ring = <7>; + mhi,chan-dir = <2>; + mhi,data-type = <4>; + mhi,doorbell-mode = <3>; + mhi,ee = <0x4>; + }; + + mhi_chan@105 { + reg = <105>; + label = "IP_HW1"; + mhi,num-elements = <512>; + mhi,event-ring = <8>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@106 { + reg = <106>; + label = "IP_HW1"; + mhi,num-elements = <512>; + mhi,event-ring = <9>; + mhi,chan-dir = <2>; + mhi,data-type = <4>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@2 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <3>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@3 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <4>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@4 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <5>; + mhi,chan = <46>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@5 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <6>; + mhi,chan = <47>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,client-manage; + }; + + mhi_event@6 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <5>; + mhi,chan = <100>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + }; + + mhi_event@7 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <6>; + mhi,chan = <101>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + }; + + mhi_event@8 { + mhi,num-elements = <1024>; + mhi,intmod = <0>; + mhi,msi = <7>; + mhi,chan = <105>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,hw-ev; + }; + + mhi_event@9 { + mhi,num-elements = <1024>; + mhi,intmod = <0>; + mhi,msi = <8>; + mhi,chan = <106>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,hw-ev; + mhi,client-manage; + }; + }; + + mhi_devices { + #address-cells = <1>; + #size-cells = <0>; + mhi_netdev_0: mhi_rmnet@0 { + reg = <0x0>; + mhi,chan = "IP_HW0"; + mhi,interface-name = "rmnet_mhi"; + mhi,mru = <0x8000>; + mhi,disable-chain-skb; + }; + + mhi_netdev_1: mhi_rmnet@1 { + reg = <0x1>; + mhi,chan = "IP_HW1"; + mhi,interface-name = "rmnet_mhi"; + mhi,mru = <0x8000>; + mhi,disable-chain-skb; + }; + + mhi_netdev_2: mhi_rmnet@2 { + reg = <0x2>; + mhi,chan = "IP_SW_0"; + mhi,interface-name = "mhi_swip"; + mhi,mru = <0x4000>; + mhi,ethernet-interface; + mhi,disable-chain-skb; + }; + }; + }; + + mhi_1: qcom,mhi@1 { + reg = <0 0 0 0 0 >; + + pci-ids = "17cb:0306"; + + /* controller specific configuration */ + qcom,smmu-cfg = <0x0>; + qcom,msm-bus,name = "mhi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 1200000000 650000000>; + + /* mhi bus specific settings */ + mhi,max-channels = <110>; + mhi,timeout = <2000>; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@14 { + reg = <14>; + label = "QMI0"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@15 { + reg = <15>; + label = "QMI0"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@16 { + reg = <16>; + label = "QMI1"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@17 { + reg = <17>; + label = "QMI1"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,auto-queue; + mhi,auto-start; + }; + + mhi_chan@32 { + reg = <32>; + label = "DUN"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@33 { + reg = <33>; + label = "DUN"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@46 { + reg = <46>; + label = "IP_SW_0"; + mhi,num-elements = <512>; + mhi,event-ring = <4>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@47 { + reg = <47>; + label = "IP_SW_0"; + mhi,num-elements = <512>; + mhi,event-ring = <5>; + mhi,chan-dir = <2>; + mhi,data-type = <4>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@100 { + reg = <100>; + label = "IP_HW0"; + mhi,num-elements = <512>; + mhi,event-ring = <6>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <3>; + mhi,ee = <0x4>; + mhi,db-mode-switch; + }; + + mhi_chan@101 { + reg = <101>; + label = "IP_HW0"; + mhi,num-elements = <512>; + mhi,event-ring = <7>; + mhi,chan-dir = <2>; + mhi,data-type = <4>; + mhi,doorbell-mode = <3>; + mhi,ee = <0x4>; + }; + + mhi_chan@105 { + reg = <105>; + label = "IP_HW1"; + mhi,num-elements = <512>; + mhi,event-ring = <8>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@106 { + reg = <106>; + label = "IP_HW1"; + mhi,num-elements = <512>; + mhi,event-ring = <9>; + mhi,chan-dir = <2>; + mhi,data-type = <4>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@2 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <3>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@3 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <4>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@4 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <5>; + mhi,chan = <46>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@5 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <6>; + mhi,chan = <47>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,client-manage; + }; + + mhi_event@6 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <5>; + mhi,chan = <100>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + }; + + mhi_event@7 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <6>; + mhi,chan = <101>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + }; + + mhi_event@8 { + mhi,num-elements = <1024>; + mhi,intmod = <0>; + mhi,msi = <7>; + mhi,chan = <105>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,hw-ev; + }; + + mhi_event@9 { + mhi,num-elements = <1024>; + mhi,intmod = <0>; + mhi,msi = <8>; + mhi,chan = <106>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,hw-ev; + mhi,client-manage; + }; + }; + + mhi_devices { + #address-cells = <1>; + #size-cells = <0>; + mhi_netdev_3: mhi_rmnet@0 { + reg = <0x0>; + mhi,chan = "IP_HW0"; + mhi,interface-name = "rmnet_mhi"; + mhi,mru = <0x8000>; + mhi,disable-chain-skb; + }; + + mhi_netdev_4: mhi_rmnet@1 { + reg = <0x1>; + mhi,chan = "IP_HW1"; + mhi,interface-name = "rmnet_mhi"; + mhi,mru = <0x8000>; + mhi,disable-chain-skb; + }; + + mhi_netdev_5: mhi_rmnet@2 { + reg = <0x2>; + mhi,chan = "IP_SW_0"; + mhi,interface-name = "mhi_swip"; + mhi,mru = <0x4000>; + mhi,ethernet-interface; + mhi,disable-chain-skb; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-nowcd-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/qcs405-nowcd-audio-overlay.dtsi new file mode 100644 index 000000000000..3d7f604320c3 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-nowcd-audio-overlay.dtsi @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&q6core { + cdc_dmic01_gpios: cdc_dmic01_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>; + pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>; + qcom,lpi-gpios; + }; + + cdc_dmic23_gpios: cdc_dmic23_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>; + pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>; + qcom,lpi-gpios; + }; + + cdc_dmic45_gpios: cdc_dmic45_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>; + pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>; + qcom,lpi-gpios; + }; + + cdc_dmic67_gpios: cdc_dmic67_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic67_clk_active &cdc_dmic67_data_active>; + pinctrl-1 = <&cdc_dmic67_clk_sleep &cdc_dmic67_data_sleep>; + qcom,lpi-gpios; + }; +}; + +&q6core { + bolero: bolero-cdc { + compatible = "qcom,bolero-codec"; + clock-names = "lpass_core_hw_vote"; + clocks = <&lpass_core_hw_vote 0>; + qcom,num-macros = <1>; + }; +}; + +&qcs405_snd { + qcom,model = "qcs405-nowcd-snd-card"; + qcom,va-bolero-codec = <1>; + asoc-codec = <&stub_codec>, <&bolero>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec"; + qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; + qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; + qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>; + qcom,cdc-dmic67-gpios = <&cdc_dmic67_gpios>; + qcom,audio-routing = + "VA DMIC0", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic0", + "VA DMIC1", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic1", + "VA DMIC2", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic2", + "VA DMIC3", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic3", + "VA DMIC4", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic4", + "VA DMIC5", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic5", + "VA DMIC6", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic6", + "VA DMIC7", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic7"; +}; + +#include "qcs405-va-bolero.dtsi" diff --git a/arch/arm/boot/dts/qcom/qcs405-pcie.dtsi b/arch/arm/boot/dts/qcom/qcs405-pcie.dtsi new file mode 100644 index 000000000000..7ead59ebba67 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-pcie.dtsi @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + pcie0: qcom,pcie@7780000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x7780000 0x2000>, + <0x7786000 0x1000>, + <0x10000000 0xf1d>, + <0x10000f20 0xa8>, + <0x10100000 0x100000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "conf"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x10200000 0x10200000 0x0 0x100000>, + <0x02000000 0x0 0x10300000 0x10300000 0x0 0xd00000>; + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc 0 269 0 + 0 0 0 1 &intc 0 68 0 + 0 0 0 2 &intc 0 224 0 + 0 0 0 3 &intc 0 267 0 + 0 0 0 4 &intc 0 268 0 + 0 0 0 5 &intc 0 270 0 + 0 0 0 6 &intc 0 271 0 + 0 0 0 7 &intc 0 272 0 + 0 0 0 8 &intc 0 273 0 + 0 0 0 9 &intc 0 274 0 + 0 0 0 10 &intc 0 275 0 >; + interrupt-names = "int_pls_pme", "int_a", "int_b", "int_c", + "int_d", "int_pme_legacy", "int_pls_err", + "int_aer_legacy", "int_pls_link_up", + "int_pls_link_down", "int_bridge_flush_n"; + + qcom,phy-sequence = <0x00a0 0x0 0x0 + 0x00a4 0x01 0x3E8 + 0x0044 0x01 0x0 + 0x0088 0x78 0x0 + 0x008c 0x78 0x0 + 0x0074 0x24 0x0 + 0x0078 0x1a 0x0 + 0x007c 0x18 0x0 + 0x0084 0x04 0x0 + 0x0094 0x00 0x0 + 0x0080 0x00 0x0 + 0x0044 0x00 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_perst_default>; + + perst-gpio = <&tlmm 43 0>; + + vreg-1.8-supply = <&pms405_l5>; + vreg-0.9-supply = <&pms405_l3>; + + qcom,vreg-0.9-voltage-level = <1160000 976000 24000>; + + msi-parent = <&pcie0_msi>; + + qcom,ep-latency = <10>; + + qcom,phy-status-offset = <0x3c>; + qcom,phy-status-bit = <0>; + qcom,phy-power-down-offset = <0x98>; + qcom,boot-option = <0x0>; + qcom,keep-powerdown-phy; + + qcom,no-l0s-supported; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; + + linux,pci-domain = <0>; + + qcom,msm-bus,name = "pcie0"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + + clocks = <&clock_gcc GCC_PCIE_0_PIPE_CLK>, + <&clock_cmn_blk_pll CMN_BLK_PLL>, + <&clock_gcc GCC_PCIE_0_AUX_CLK>, + <&clock_gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&clock_gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&clock_gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&clock_rpmcc RPM_SMD_LN_BB_CLK>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo"; + max-clock-frequency-hz = <250000000>, <0>, <1200000>, + <0>, <0>, <0>, <0>; + + clock-output-names = "pcie_0_pipe_clk"; + resets = <&clock_gcc GCC_PCIEPHY_0_PHY_BCR>; + reset-names = "pcie_0_phy_reset"; + + pcie_rc0: pcie_rc0 { + #address-cells = <5>; + #size-cells = <0>; + reg = <0 0 0 0 0>; + pci-ids = "17cb:1000"; + }; + }; + + pcie0_msi: qcom,pcie0_msi@a0000000 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0xa0000000 0x0>; + interrupt-parent = <&intc>; + interrupts = ; + qcom,snps; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-pinctrl.dtsi b/arch/arm/boot/dts/qcom/qcs405-pinctrl.dtsi new file mode 100644 index 000000000000..9f33a1d0a0c9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-pinctrl.dtsi @@ -0,0 +1,2478 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tlmm: pinctrl@1000000 { + compatible = "qcom,qcs405-pinctrl"; + reg = <0x1000000 0x200000>; + reg-names = "pinctrl"; + interrupts-extended = <&wakegic GIC_SPI 208 IRQ_TYPE_NONE>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + interrupt-parent = <&wakegpio>; + #interrupt-cells = <2>; + + blsp1_uart2_console { + blsp_uart_tx_a2_active: blsp_uart_tx_a2_active { + mux { + pins = "gpio17"; + function = "blsp_uart_tx_a2"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp_uart_rx_a2_active: blsp_uart_rx_a2_active { + mux { + pins = "gpio18"; + function = "blsp_uart_rx_a2"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp_uart_tx_rx_a2_sleep: blsp_uart_tx_rx_a2_sleep { + mux { + pins = "gpio17", "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio17", "gpio18"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + blsp1_uart1 { + blsp1_uart1_active: blsp1_uart1_active { + mux { + pins = "gpio30", "gpio31", + "gpio32", "gpio33"; + function = "blsp_uart0"; + }; + + config { + pins = "gpio30", "gpio31", + "gpio32", "gpio33"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1_sleep: blsp1_uart1_sleep { + mux { + pins = "gpio30", "gpio31", + "gpio32", "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio31", + "gpio32", "gpio33"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + blsp1_uart2 { + blsp1_uart2_active: blsp1_uart2_active { + mux { + pins = "gpio22", "gpio23"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2_sleep: blsp1_uart2_sleep { + mux { + pins = "gpio22", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + blsp1_uart3 { + blsp1_uart3_active: blsp1_uart3_active { + mux { + pins = "gpio17", "gpio18", + "gpio19", "gpio20"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio17", "gpio18", + "gpio19", "gpio20"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_sleep: blsp1_uart3_sleep { + mux { + pins = "gpio17", "gpio18", + "gpio19", "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio17", "gpio18", + "gpio19", "gpio20"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + blsp1_uart4: blsp1_uart4 { + blsp1_uart4_tx_active: blsp1_uart4_tx_active { + mux { + pins = "gpio82"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio82"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4_tx_sleep: blsp1_uart4_tx_sleep { + mux { + pins = "gpio82"; + function = "gpio"; + }; + + config { + pins = "gpio82"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart4_rxcts_active: blsp1_uart4_rxcts_active { + mux { + pins = "gpio83", "gpio84"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio83", "gpio84"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4_rxcts_sleep: blsp1_uart4_rxcts_sleep { + mux { + pins = "gpio83", "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio83", "gpio84"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + blsp1_uart4_rfr_active: blsp1_uart4_rfr_active { + mux { + pins = "gpio85"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio85"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4_rfr_sleep: blsp1_uart4_rfr_sleep { + mux { + pins = "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio85"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + blsp2_uart1 { + blsp2_uart1_active: blsp2_uart1_active { + mux { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + function = "blsp_uart5"; + }; + + config { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart1_sleep: blsp2_uart1_sleep { + mux { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + /* SPI CONFIGURATION */ + spi_1 { + spi_1_active: spi_1_active { + mux { + pins = "gpio30", "gpio31", + "gpio32", "gpio33"; + function = "blsp_spi0"; + }; + + config { + pins = "gpio30", "gpio31", + "gpio32", "gpio33"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_1_sleep: spi_1_sleep { + mux { + pins = "gpio30", "gpio31", + "gpio32", "gpio33"; + function = "blsp_spi0"; + }; + + config { + pins = "gpio30", "gpio31", + "gpio32", "gpio33"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_2 { + spi_2_active: spi_2_active { + mux { + pins = "gpio22", "gpio23", + "gpio24", "gpio25"; + function = "blsp_spi1"; + }; + + config { + pins = "gpio22", "gpio23", + "gpio24", "gpio25"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_2_sleep: spi_2_sleep { + mux { + pins = "gpio22", "gpio23", + "gpio24", "gpio25"; + function = "blsp_spi1"; + }; + + config { + pins = "gpio22", "gpio23", + "gpio24", "gpio25"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_3 { + spi_3_active: spi_3_active { + mux { + pins = "gpio17", "gpio18", + "gpio19", "gpio20"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio17", "gpio18", + "gpio19", "gpio20"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_3_sleep: spi_3_sleep { + mux { + pins = "gpio17", "gpio18", + "gpio19", "gpio20"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio17", "gpio18", + "gpio19", "gpio20"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_4 { + spi_4_active: spi_4_active { + mux { + pins = "gpio82", "gpio83", + "gpio84", "gpio85"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio82", "gpio83", + "gpio84", "gpio85"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_4_sleep: spi_4_sleep { + mux { + pins = "gpio82", "gpio83", + "gpio84", "gpio85"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio82", "gpio83", + "gpio84", "gpio85"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_5 { + spi_5_active: spi_5_active { + mux { + pins = "gpio37", "gpio38", + "gpio117", "gpio118"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio37", "gpio38", + "gpio117", "gpio118"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_5_sleep: spi_5_sleep { + mux { + pins = "gpio37", "gpio38", + "gpio117", "gpio118"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio37", "gpio38", + "gpio117", "gpio118"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_6 { + spi_6_active: spi_6_active { + mux { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + function = "blsp_spi5"; + }; + + config { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_6_sleep: spi_6_sleep { + mux { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + function = "blsp_spi5"; + }; + + config { + pins = "gpio26", "gpio27", + "gpio28", "gpio29"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + i2c_1 { + i2c_1_active: i2c_1_active { + /* active state */ + mux { + pins = "gpio32", "gpio33"; + function = "blsp_i2c0"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_1_sleep: i2c_1_sleep { + /* suspended state */ + mux { + pins = "gpio32", "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio32", "gpio33"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_2 { + i2c_2_active: i2c_2_active { + /* active state */ + mux { + pins = "gpio24", "gpio25"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_2_sleep: i2c_2_sleep { + /* suspended state */ + mux { + pins = "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_3 { + i2c_3_sda_active: i2c_3_sda_active { + /* active state */ + mux { + pins = "gpio19"; + function = "blsp_i2c_sda_a2"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_3_scl_active: i2c_3_scl_active { + /* active state */ + mux { + pins = "gpio20"; + function = "blsp_i2c_scl_a2"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_3_sleep: i2c_3_sleep { + /* suspended state */ + mux { + pins = "gpio19", "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio19", "gpio20"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_4 { + i2c_4_active: i2c_4_active { + /* active state */ + mux { + pins = "gpio84", "gpio85"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio84", "gpio85"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_4_sleep: i2c_4_sleep { + /* suspended state */ + mux { + pins = "gpio84", "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio84", "gpio85"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_5 { + i2c_5_active: i2c_5_active { + /* active state */ + mux { + pins = "gpio117", "gpio118"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio117", "gpio118"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_5_sleep: i2c_5_sleep { + /* suspended state */ + mux { + pins = "gpio117", "gpio118"; + function = "gpio"; + }; + + config { + pins = "gpio117", "gpio118"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + pcie0 { + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio43"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + i2c_6 { + i2c_6_active: i2c_6_active { + /* active state */ + mux { + pins = "gpio28", "gpio29"; + function = "blsp_i2c5"; + }; + + config { + pins = "gpio28", "gpio29"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_6_sleep: i2c_6_sleep { + /* suspended state */ + mux { + pins = "gpio28", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio29"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + ntag { + ntag_int_active: ntag_int_active { + /* active state */ + mux { + /* GPIO 53 Field Detect Interrupt */ + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + ntag_int_suspend: ntag_int_suspend { + /* sleep state */ + mux { + /* GPIO 53 Field Detect Interrupt */ + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + }; + + mdss_hdmi_5v_active: mdss_hdmi_5v_active { + mux { + pins = "gpio109"; + function = "gpio"; + }; + + config { + pins = "gpio109"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + mdss_hdmi_5v_suspend: mdss_hdmi_5v_suspend { + mux { + pins = "gpio109"; + function = "gpio"; + }; + + config { + pins = "gpio109"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + mdss_hdmi_hpd_active: mdss_hdmi_hpd_active { + mux { + pins = "gpio106"; + function = "hdmi_hot"; + }; + + config { + pins = "gpio106"; + bias-pull-down; + drive-strength = <16>; + }; + }; + + mdss_hdmi_hpd_suspend: mdss_hdmi_hpd_suspend { + mux { + pins = "gpio106"; + function = "hdmi_hot"; + }; + + config { + pins = "gpio106"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + mdss_hdmi_ddc_active: mdss_hdmi_ddc_active { + mux { + pins = "gpio15", "gpio16"; + function = "hdmi_ddc"; + }; + + config { + pins = "gpio15", "gpio16"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + mdss_hdmi_ddc_suspend: mdss_hdmi_ddc_suspend { + mux { + pins = "gpio15", "gpio16"; + function = "hdmi_ddc"; + }; + + config { + pins = "gpio15", "gpio16"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + mdss_hdmi_cec_active: mdss_hdmi_cec_active { + mux { + pins = "gpio14"; + function = "hdmi_cec"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + mdss_hdmi_cec_suspend: mdss_hdmi_cec_suspend { + mux { + pins = "gpio14"; + function = "hdmi_cec"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + mdss_rgb_data0_active: mdss_rgb_data0_active { + mux { + pins = "gpio26", "gpio41"; + function = "rgb_data0"; + }; + + config { + pins = "gpio26", "gpio41"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data0_suspend: mdss_rgb_data0_suspend { + mux { + pins = "gpio26", "gpio41"; + function = "rgb_data0"; + }; + + config { + pins = "gpio26", "gpio41"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_data1_active: mdss_rgb_data1_active { + mux { + pins = "gpio27", "gpio42"; + function = "rgb_data1"; + }; + + config { + pins = "gpio27", "gpio42"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data1_suspend: mdss_rgb_data1_suspend { + mux { + pins = "gpio27", "gpio42"; + function = "rgb_data1"; + }; + + config { + pins = "gpio27", "gpio42"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_data2_active: mdss_rgb_data2_active { + mux { + pins = "gpio28", "gpio43"; + function = "rgb_data2"; + }; + + config { + pins = "gpio28", "gpio43"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data2_suspend: mdss_rgb_data2_suspend { + mux { + pins = "gpio28", "gpio43"; + function = "rgb_data2"; + }; + + config { + pins = "gpio28", "gpio43"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_data3_active: mdss_rgb_data3_active { + mux { + pins = "gpio29", "gpio44"; + function = "rgb_data3"; + }; + + config { + pins = "gpio29", "gpio44"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data3_suspend: mdss_rgb_data3_suspend { + mux { + pins = "gpio29", "gpio44"; + function = "rgb_data3"; + }; + + config { + pins = "gpio29", "gpio44"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_data4_active: mdss_rgb_data4_active { + mux { + pins = "gpio39", "gpio45"; + function = "rgb_data4"; + }; + + config { + pins = "gpio39", "gpio45"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data4_suspend: mdss_rgb_data4_suspend { + mux { + pins = "gpio39", "gpio45"; + function = "rgb_data4"; + }; + + config { + pins = "gpio39", "gpio45"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_data5_active: mdss_rgb_data5_active { + mux { + pins = "gpio40", "gpio46"; + function = "rgb_data5"; + }; + + config { + pins = "gpio40", "gpio46"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data5_suspend: mdss_rgb_data5_suspend { + mux { + pins = "gpio40", "gpio46"; + function = "rgb_data5"; + }; + + config { + pins = "gpio40", "gpio46"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_data_b0_active: mdss_rgb_data_b0_active { + mux { + pins = "gpio47"; + function = "rgb_data_b0"; + }; + + config { + pins = "gpio47"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data_b0_suspend: mdss_rgb_data_b0_suspend { + mux { + pins = "gpio47"; + function = "rgb_data_b0"; + }; + + config { + pins = "gpio47"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_data_b1_active: mdss_rgb_data_b1_active { + mux { + pins = "gpio48"; + function = "rgb_data_b1"; + }; + + config { + pins = "gpio48"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data_b1_suspend: mdss_rgb_data_b1_suspend { + mux { + pins = "gpio48"; + function = "rgb_data_b1"; + }; + + config { + pins = "gpio48"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_data_b2_active: mdss_rgb_data_b2_active { + mux { + pins = "gpio49"; + function = "rgb_data_b2"; + }; + + config { + pins = "gpio49"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data_b2_suspend: mdss_rgb_data_b2_suspend { + mux { + pins = "gpio49"; + function = "rgb_data_b2"; + }; + + config { + pins = "gpio49"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_data_b3_active: mdss_rgb_data_b3_active { + mux { + pins = "gpio50"; + function = "rgb_data_b3"; + }; + + config { + pins = "gpio50"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data_b3_suspend: mdss_rgb_data_b3_suspend { + mux { + pins = "gpio50"; + function = "rgb_data_b3"; + }; + + config { + pins = "gpio50"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_data_b4_active: mdss_rgb_data_b4_active { + mux { + pins = "gpio51"; + function = "rgb_data_b4"; + }; + + config { + pins = "gpio51"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data_b4_suspend: mdss_rgb_data_b4_suspend { + mux { + pins = "gpio51"; + function = "rgb_data_b4"; + }; + + config { + pins = "gpio51"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_data_b5_active: mdss_rgb_data_b5_active { + mux { + pins = "gpio52"; + function = "rgb_data_b5"; + }; + + config { + pins = "gpio52"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_data_b5_suspend: mdss_rgb_data_b5_suspend { + mux { + pins = "gpio52"; + function = "rgb_data_b5"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_hsync_active: mdss_rgb_hsync_active { + mux { + pins = "gpio53"; + function = "rgb_hsync"; + }; + + config { + pins = "gpio53"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_hsync_suspend: mdss_rgb_hsync_suspend { + mux { + pins = "gpio53"; + function = "rgb_hsync"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_vsync_active: mdss_rgb_vsync_active { + mux { + pins = "gpio54"; + function = "rgb_vsync"; + }; + + config { + pins = "gpio54"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_vsync_suspend: mdss_rgb_vsync_suspend { + mux { + pins = "gpio54"; + function = "rgb_vsync"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_de_active: mdss_rgb_de_active { + mux { + pins = "gpio55"; + function = "rgb_de"; + }; + + config { + pins = "gpio55"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_de_suspend: mdss_rgb_de_suspend { + mux { + pins = "gpio55"; + function = "rgb_de"; + }; + + config { + pins = "gpio55"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_clk_active: mdss_rgb_clk_active { + mux { + pins = "gpio56"; + function = "rgb_clk"; + }; + + config { + pins = "gpio56"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-low; + }; + }; + + mdss_rgb_clk_suspend: mdss_rgb_clk_suspend { + mux { + pins = "gpio56"; + function = "rgb_clk"; + }; + + config { + pins = "gpio56"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + mdss_rgb_active: mdss_rgb_active { + mux { + pins = "gpio58"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-high; + }; + }; + + mdss_rgb_suspend: mdss_rgb_suspend { + mux { + pins = "gpio58"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + + pmx_mdss: pmx_mdss { + mdss_dsi_active: mdss_dsi_active { + mux { + pins = "gpio39", "gpio48"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + output-high; + }; + }; + mdss_dsi_suspend: mdss_dsi_suspend { + mux { + pins = "gpio39", "gpio48"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + pmx_mdss_te { + mdss_te_active: mdss_te_active { + mux { + pins = "gpio40"; + function = "mdp_vsync"; + }; + config { + pins = "gpio40"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down*/ + }; + }; + + mdss_te_suspend: mdss_te_suspend { + mux { + pins = "gpio40"; + function = "mdp_vsync"; + }; + config { + pins = "gpio40"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + }; + + /* SDC pin type */ + sdc1_clk_on: sdc1_clk_on { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc1_clk_off: sdc1_clk_off { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_cmd_on: sdc1_cmd_on { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_cmd_off: sdc1_cmd_off { + config { + pins = "sdc1_cmd"; + num-grp-pins = <1>; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_data_on: sdc1_data_on { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_data_off: sdc1_data_off { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_rclk_on: sdc1_rclk_on { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc1_rclk_off: sdc1_rclk_off { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_on: cd_on { + mux { + pins = "gpio21"; /* sdcard_det */ + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_cd_off: cd_off { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* SMB CONFIGURATION */ + smb_stat: smb_stat { + mux { + pins = "gpio107"; + function = "gpio"; + }; + + config { + pins = "gpio107"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; + + nxp_i2c_intr: nxp_i2c_intr { + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; + + usb3_id_det_default: usb2_id_det_default { + config { + pins = "gpio116"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; + + usb2_ssrd_det_default: usb2_ssrd_det_default { + config { + pins = "gpio27"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + + pri_mi2s_mclk { + pri_mi2s_mclk_sleep: pri_mi2s_mclk_sleep { + mux { + pins = "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio64"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_mclk_active: pri_mi2s_mclk_active { + mux { + pins = "gpio64"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio64"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sck { + pri_mi2s_sck_sleep: pri_mi2s_sck_sleep { + mux { + pins = "gpio87"; + function = "i2s_1"; + }; + + config { + pins = "gpio87"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sck_active: pri_mi2s_sck_active { + mux { + pins = "gpio87"; + function = "i2s_1"; + }; + + config { + pins = "gpio87"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_ws { + pri_mi2s_ws_sleep: pri_mi2s_ws_sleep { + mux { + pins = "gpio88"; + function = "i2s_1"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_ws_active: pri_mi2s_ws_active { + mux { + pins = "gpio88"; + function = "i2s_1"; + }; + + config { + pins = "gpio88"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sd0 { + pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep { + mux { + pins = "gpio89"; + function = "i2s_1"; + }; + + config { + pins = "gpio89"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd0_active: pri_mi2s_sd0_active { + mux { + pins = "gpio89"; + function = "i2s_1"; + }; + + config { + pins = "gpio89"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sd1 { + pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep { + mux { + pins = "gpio90"; + function = "i2s_1"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd1_active: pri_mi2s_sd1_active { + mux { + pins = "gpio90"; + function = "i2s_1"; + }; + + config { + pins = "gpio90"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + pri_mi2s_sd2 { + pri_mi2s_sd2_sleep: pri_mi2s_sd2_sleep { + mux { + pins = "gpio91"; + function = "i2s_1"; + }; + + config { + pins = "gpio91"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd2_active: pri_mi2s_sd2_active { + mux { + pins = "gpio91"; + function = "i2s_1"; + }; + + config { + pins = "gpio91"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sd3 { + pri_mi2s_sd3_sleep: pri_mi2s_sd3_sleep { + mux { + pins = "gpio92"; + function = "i2s_1"; + }; + + config { + pins = "gpio92"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd3_active: pri_mi2s_sd3_active { + mux { + pins = "gpio92"; + function = "i2s_1"; + }; + + config { + pins = "gpio92"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + pri_mi2s_sd4 { + pri_mi2s_sd4_sleep: pri_mi2s_sd4_sleep { + mux { + pins = "gpio93"; + function = "i2s_1"; + }; + + config { + pins = "gpio93"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd4_active: pri_mi2s_sd4_active { + mux { + pins = "gpio93"; + function = "i2s_1"; + }; + + config { + pins = "gpio93"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sd5 { + pri_mi2s_sd5_sleep: pri_mi2s_sd5_sleep { + mux { + pins = "gpio94"; + function = "i2s_1"; + }; + + config { + pins = "gpio94"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd5_active: pri_mi2s_sd5_active { + mux { + pins = "gpio94"; + function = "i2s_1"; + }; + + config { + pins = "gpio94"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sd6 { + pri_mi2s_sd6_sleep: pri_mi2s_sd6_sleep { + mux { + pins = "gpio95"; + function = "i2s_1"; + }; + + config { + pins = "gpio95"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd6_active: pri_mi2s_sd6_active { + mux { + pins = "gpio95"; + function = "i2s_1"; + }; + + config { + pins = "gpio95"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sd7 { + pri_mi2s_sd7_sleep: pri_mi2s_sd7_sleep { + mux { + pins = "gpio96"; + function = "i2s_1"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd7_active: pri_mi2s_sd7_active { + mux { + pins = "gpio96"; + function = "i2s_1"; + }; + + config { + pins = "gpio96"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pca9956b_reset_gpio: pca9956b_reset_gpio { + mux { + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + drive-strength = <2>; + bias-pull-up; + output-high; + }; + }; + + sec_mi2s_sck { + sec_mi2s_sck_sleep: sec_mi2s_sck_sleep { + mux { + pins = "gpio97"; + function = "i2s_2"; + }; + + config { + pins = "gpio97"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sck_active: sec_mi2s_sck_active { + mux { + pins = "gpio97"; + function = "i2s_2"; + }; + + config { + pins = "gpio97"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_ws { + sec_mi2s_ws_sleep: sec_mi2s_ws_sleep { + mux { + pins = "gpio98"; + function = "i2s_2"; + }; + + config { + pins = "gpio98"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_ws_active: sec_mi2s_ws_active { + mux { + pins = "gpio98"; + function = "i2s_2"; + }; + + config { + pins = "gpio98"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_sd0 { + sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep { + mux { + pins = "gpio99"; + function = "i2s_2"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sd0_active: sec_mi2s_sd0_active { + mux { + pins = "gpio99"; + function = "i2s_2"; + }; + + config { + pins = "gpio99"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_sd1 { + sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep { + mux { + pins = "gpio100"; + function = "i2s_2"; + }; + + config { + pins = "gpio100"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sd1_active: sec_mi2s_sd1_active { + mux { + pins = "gpio100"; + function = "i2s_2"; + }; + + config { + pins = "gpio100"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + sec_mi2s_sd2 { + sec_mi2s_sd2_sleep: sec_mi2s_sd2_sleep { + mux { + pins = "gpio101"; + function = "i2s_2"; + }; + + config { + pins = "gpio101"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sd2_active: sec_mi2s_sd2_active { + mux { + pins = "gpio101"; + function = "i2s_2"; + }; + + config { + pins = "gpio101"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_sd3 { + sec_mi2s_sd3_sleep: sec_mi2s_sd3_sleep { + mux { + pins = "gpio102"; + function = "i2s_2"; + }; + + config { + pins = "gpio102"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sd3_active: sec_mi2s_sd3_active { + mux { + pins = "gpio102"; + function = "i2s_2"; + }; + + config { + pins = "gpio102"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + /* SPDIF optical input pin */ + spdifrx_opt { + spdifrx_opt_default: spdifrx_opt_default { + mux { + pins = "gpio119"; + function = "spdifrx_opt"; + }; + + config { + pins = "gpio119"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + /* EP92 HDMI pins */ + ep_reset_n { + ep_reset_n_sleep: ep_reset_n_sleep { + mux { + pins = "gpio108"; + function = "gpio"; + }; + + config { + pins = "gpio108"; + drive-strength = <8>; /* 8 mA */ + bias-disable; + output-high; + }; + }; + + ep_reset_n_active: ep_reset_n_active { + mux { + pins = "gpio108"; + function = "gpio"; + }; + + config { + pins = "gpio108"; + drive-strength = <8>; /* 8 mA */ + bias-disable; + output-high; + }; + }; + }; + + ep_mute { + ep_mute_sleep: ep_mute_sleep { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + ep_mute_active: ep_mute_active { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + drive-strength = <8>; /* 8 mA */ + bias-disable; + }; + }; + }; + + ep_int { + ep_int_sleep: ep_int_sleep { + mux { + pins = "gpio107"; + function = "gpio"; + }; + + config { + pins = "gpio107"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + ep_int_active: ep_int_active { + mux { + pins = "gpio107"; + function = "gpio"; + }; + + config { + pins = "gpio107"; + drive-strength = <8>; /* 8 mA */ + bias-disable; + }; + }; + }; + + ir_in { + ir_in_default: ir_in_default { + mux { + pins = "gpio77"; + function = "ir_in"; + }; + + config { + pins = "gpio77"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* no pull */ + input-enable; + }; + }; + }; + + /* WSA speaker reset pins */ + wsa_en_1_2 { + wsa_en_1_2_sleep: wsa_en_1_2_sleep { + mux { + pins = "gpio77"; + function = "gpio"; + }; + + config { + pins = "gpio77"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + wsa_en_1_2_active: wsa_en_1_2_active { + mux { + pins = "gpio77"; + function = "gpio"; + }; + + config { + pins = "gpio77"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + wcd9xxx_intr { + wcd_intr_default: wcd_intr_default{ + mux { + pins = "gpio105"; + function = "gpio"; + }; + + config { + pins = "gpio105"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + cdc_reset_ctrl { + cdc_reset_sleep: cdc_reset_sleep { + mux { + pins = "gpio46"; + function = "gpio"; + }; + config { + pins = "gpio46"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + + cdc_reset_active:cdc_reset_active { + mux { + pins = "gpio46"; + function = "gpio"; + }; + config { + pins = "gpio46"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + }; + + lineout_booster_ctrl { + lineout_booster_sleep: lineout_booster_sleep { + mux { + pins = "gpio113"; + function = "gpio"; + }; + config { + pins = "gpio113"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + lineout_booster_active:lineout_booster_active { + mux { + pins = "gpio113"; + function = "gpio"; + }; + config { + pins = "gpio113"; + drive-strength = <16>; + bias-pull-down; + output-high; + }; + }; + }; + + emac { + emac_mdc: emac_mdc { + mux { + pins = "gpio76"; + function = "rgmii_mdc"; + }; + + config { + pins = "gpio76"; + bias-pull-up; + }; + }; + emac_mdio: emac_mdio { + mux { + pins = "gpio75"; + function = "rgmii_mdio"; + }; + + config { + pins = "gpio75"; + bias-pull-up; + }; + }; + + emac_rgmii_txd0: emac_rgmii_txd0 { + mux { + pins = "gpio67"; + function = "rgmii_tx"; + }; + + config { + pins = "gpio67"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txd1: emac_rgmii_txd1 { + mux { + pins = "gpio66"; + function = "rgmii_tx"; + }; + + config { + pins = "gpio66"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txd2: emac_rgmii_txd2 { + mux { + pins = "gpio65"; + function = "rgmii_tx"; + }; + + config { + pins = "gpio65"; + bias-pull-up; + drive-strength = <16>; + }; + }; + emac_rgmii_txd3: emac_rgmii_txd3 { + mux { + pins = "gpio64"; + function = "rgmii_tx"; + }; + + config { + pins = "gpio64"; + bias-pull-up; + drive-strength = <16>; + }; + }; + emac_rgmii_txc: emac_rgmii_txc { + mux { + pins = "gpio63"; + function = "rgmii_ck"; + }; + + config { + pins = "gpio63"; + bias-pull-up; + drive-strength = <16>; + }; + }; + emac_rgmii_tx_ctl: emac_rgmii_tx_ctl { + mux { + pins = "gpio68"; + function = "rgmii_ctl"; + }; + + config { + pins = "gpio68"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + + emac_rgmii_rxd0: emac_rgmii_rxd0 { + mux { + pins = "gpio73"; + function = "rgmii_rx"; + }; + + config { + pins = "gpio73"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2MA */ + }; + }; + + emac_rgmii_rxd1: emac_rgmii_rxd1 { + mux { + pins = "gpio72"; + function = "rgmii_rx"; + }; + + config { + pins = "gpio72"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_rgmii_rxd2: emac_rgmii_rxd2 { + mux { + pins = "gpio71"; + function = "rgmii_rx"; + }; + + config { + pins = "gpio71"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + emac_rgmii_rxd3: emac_rgmii_rxd3 { + mux { + pins = "gpio70"; + function = "rgmii_rx"; + }; + + config { + pins = "gpio70"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + emac_rgmii_rxc: emac_rgmii_rxc { + mux { + pins = "gpio69"; + function = "rgmii_ck"; + }; + + config { + pins = "gpio69"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + emac_rgmii_rx_ctl: emac_rgmii_rx_ctl { + mux { + pins = "gpio74"; + function = "rgmii_ctl"; + }; + + config { + pins = "gpio74"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + emac_phy_intr: emac_phy_intr { + mux { + pins = "gpio61"; + function = "rgmii_int"; + }; + + config { + pins = "gpio61"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + }; + + evb_tlmm_gpio_key{ + tlmm_gpio_key_active: tlmm_gpio_key_active { + mux { + pins = "gpio21","gpio52","gpio54", + "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio21","gpio52","gpio54", + "gpio115"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + tlmm_gpio_key_suspend: tlmm_gpio_key_suspend { + mux { + pins = "gpio21","gpio52","gpio54", + "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio21","gpio52","gpio54", + "gpio115"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-pm.dtsi b/arch/arm/boot/dts/qcom/qcs405-pm.dtsi new file mode 100644 index 000000000000..183da184bd53 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-pm.dtsi @@ -0,0 +1,140 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + qcom,spm@b012000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb012000 0x1000>; + qcom,name = "perf-l2"; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x14>; + qcom,saw2-spm-dly= <0x3C11840A>; + qcom,saw2-spm-ctl = <0xe>; + qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,vctl-timeout-us = <500>; + qcom,vctl-port = <0x0>; + qcom,vctl-port-ub = <0x1>; + qcom,pfm-port = <0x02>; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + qcom,use-psci; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm-cluster@0{ + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + label = "perf"; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0{ + reg = <0>; + label = "perf-l2-wfi"; + qcom,psci-mode = <1>; + qcom,entry-latency-us = <125>; + qcom,exit-latency-us = <180>; + qcom,min-residency-us = <305>; + }; + + qcom,pm-cluster-level@1{ + reg = <1>; + label = "perf-l2-gdhs"; + qcom,psci-mode = <4>; + qcom,entry-latency-us = <240>; + qcom,exit-latency-us = <280>; + qcom,min-residency-us = <806>; + qcom,min-child-idx = <1>; + qcom,reset-level = ; + }; + + qcom,pm-cluster-level@2{ + reg = <2>; + label = "perf-l2-retention"; + qcom,psci-mode = <2>; + qcom,entry-latency-us = <700>; + qcom,exit-latency-us = <650>; + qcom,min-residency-us = <1972>; + qcom,min-child-idx = <1>; + qcom,reset-level = ; + }; + + qcom,pm-cluster-level@3{ + reg = <3>; + label = "perf-l2-pc"; + qcom,psci-mode = <5>; + qcom,entry-latency-us = <700>; + qcom,exit-latency-us = <1000>; + qcom,min-residency-us = <6500>; + qcom,min-child-idx = <1>; + qcom,is-reset; + qcom,notify-rpm; + qcom,reset-level = ; + }; + + qcom,pm-cpu { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>; + + qcom,pm-cpu-level@0 { + reg = <0>; + qcom,psci-cpu-mode = <0>; + label = "wfi"; + qcom,entry-latency-us = <13>; + qcom,exit-latency-us = <12>; + qcom,min-residency-us = <25>; + }; + + qcom,pm-cpu-level@1 { + reg = <1>; + qcom,psci-cpu-mode = <3>; + label = "pc"; + qcom,entry-latency-us = <125>; + qcom,exit-latency-us = <180>; + qcom,min-residency-us = <595>; + qcom,use-broadcast-timer; + qcom,is-reset; + qcom,reset-level = ; + }; + }; + }; + }; + + qcom,rpm-stats@200000 { + compatible = "qcom,rpm-stats"; + reg = <0x200000 0x1000>, + <0x290014 0x4>, + <0x29001c 0x4>; + reg-names = "phys_addr_base", "offset_addr", + "heap_phys_addrbase"; + qcom,sleep-stats-version = <2>; + }; + + qcom,rpm-master-stats@60150 { + compatible = "qcom,rpm-master-stats"; + reg = <0x60150 0x5000>; + qcom,masters = "APSS", "MPSS", "LPASS", "CDSP", "TZ"; + qcom,master-stats-version = <2>; + qcom,master-offset = <4096>; + }; +}; + diff --git a/arch/arm/boot/dts/qcom/qcs405-regulator.dtsi b/arch/arm/boot/dts/qcom/qcs405-regulator.dtsi new file mode 100644 index 000000000000..6909490abdb9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-regulator.dtsi @@ -0,0 +1,383 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&rpm_bus { + /* PMS405 S1 - VDD_MX/CX supply */ + rpm-regulator-smpa1 { + status = "okay"; + pms405_s1_level: regulator-s1-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_s1_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + pms405_s1_floor_level: regulator-s1-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_s1_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + pms405_s1_level_ao: regulator-s1-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_s1_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + cx_cdev: cx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&pms405_s1_floor_level>; + regulator-levels = ; + #cooling-cells = <2>; + }; + + mx_cdev: mx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&pms405_s1_level>; + regulator-levels = ; + #cooling-cells = <2>; + }; + }; + + /* PMS405 S2 - VDD_LPI_CX supply */ + rpm-regulator-smpa2 { + status = "okay"; + pms405_s2_level: regulator-s2-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_s2_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + pms405_s2_floor_level: regulator-s2-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_s2_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + }; + + rpm-regulator-smpa4 { + status = "okay"; + pms405_s4: regulator-s4 { + regulator-min-microvolt = <1728000>; + regulator-max-microvolt = <1920000>; + qcom,init-voltage = <1728000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + pms405_l1: regulator-l1 { + regulator-min-microvolt = <1240000>; + regulator-max-microvolt = <1352000>; + qcom,init-voltage = <1240000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + pms405_l2: regulator-l2 { + regulator-min-microvolt = <1048000>; + regulator-max-microvolt = <1280000>; + qcom,init-voltage = <1048000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + pms405_l3: regulator-l3 { + regulator-min-microvolt = <976000>; + regulator-max-microvolt = <1160000>; + qcom,init-voltage = <976000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa4 { + status = "okay"; + pms405_l4: regulator-l4 { + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1256000>; + qcom,init-voltage = <1144000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + pms405_l5: regulator-l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + + pms405_l5_ao: regulator-l5-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l5_ao"; + qcom,set = <1>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + pms405_l6: regulator-l6 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1896000>; + qcom,init-voltage = <1704000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + pms405_l7: regulator-l7 { + regulator-min-microvolt = <1616000>; + regulator-max-microvolt = <3000000>; + qcom,init-voltage = <1616000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa8 { + status = "okay"; + pms405_l8: regulator-l8 { + regulator-min-microvolt = <1136000>; + regulator-max-microvolt = <1352000>; + qcom,init-voltage = <1136000>; + status = "okay"; + }; + }; + + /* PMS405 L9 - VDD_LPI_MX supply */ + rpm-regulator-ldoa9 { + status = "okay"; + pms405_l9_level: regulator-l9-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l9_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + pms405_l9_floor_level: regulator-l9-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pms405_l9_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + pms405_l10: regulator-l10 { + regulator-min-microvolt = <2936000>; + regulator-max-microvolt = <3088000>; + qcom,init-voltage = <2936000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + pms405_l11: regulator-l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3304000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + pms405_l12: regulator-l12 { + regulator-min-microvolt = <2968000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <2968000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + pms405_l13: regulator-l13 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <3000000>; + status = "okay"; + }; + }; +}; + +&spmi_bus { + qcom,pms405@1 { + /* PMS405 S3 = VDD_APC_supply */ + pms405_s3: spm-regulator@1a00 { + compatible = "qcom,spm-regulator"; + reg = <0x1a00 0x100>; + regulator-name = "pms405_s3"; + regulator-min-microvolt = <1048000>; + regulator-max-microvolt = <1384000>; + }; + }; +}; + +&soc { + /* APC CPR and MEM ACC regulators */ + mem_acc_vreg_corner: regulator@1942120 { + compatible = "qcom,mem-acc-regulator"; + regulator-name = "mem_acc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <2>; + + qcom,acc-reg-addr-list = + <0x01942138 0x01942130 0x01942120 0x01942124>; + + qcom,acc-init-reg-config = <1 0xff>, <2 0x5555>; + + qcom,num-acc-corners = <2>; + qcom,boot-acc-corner = <2>; + qcom,corner1-reg-config = + /* INT2 => INT2 */ + <(-1) (-1)>, <(-1) (-1)>, + /* INT2 => NOM */ + < 3 0x0>, < 4 0x0>; + + qcom,corner2-reg-config = + /* NOM => INT2 */ + < 3 0x1041040>, < 4 0x41>, + /* NOM => NOM */ + <(-1) (-1)>, <(-1) (-1)>; + }; + + apc_vreg_corner: regulator@b018000 { + compatible = "qcom,cpr-regulator"; + reg = <0xb018000 0x1000>, <0xb011064 4>, <0xa4000 0x1000>; + reg-names = "rbcpr", "rbcpr_clk", "efuse_addr"; + interrupts = <0 15 0>; + regulator-name = "apc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <3>; + + qcom,cpr-fuse-corners = <3>; + qcom,cpr-voltage-ceiling = <1224000 1288000 1384000>; + qcom,cpr-voltage-floor = <1048000 1048000 1088000>; + vdd-apc-supply = <&pms405_s3>; + + mem-acc-supply = <&mem_acc_vreg_corner>; + + qcom,cpr-ref-clk = <19200>; + qcom,cpr-timer-delay = <5000>; + qcom,cpr-timer-cons-up = <0>; + qcom,cpr-timer-cons-down = <2>; + qcom,cpr-irq-line = <0>; + qcom,cpr-step-quotient = <25>; + qcom,cpr-up-threshold = <1>; + qcom,cpr-down-threshold = <3>; + qcom,cpr-idle-clocks = <15>; + qcom,cpr-gcnt-time = <1>; + qcom,vdd-apc-step-up-limit = <1>; + qcom,vdd-apc-step-down-limit = <1>; + qcom,cpr-apc-volt-step = <8000>; + + qcom,cpr-fuse-row = <69 0>; + qcom,cpr-fuse-target-quot = <30 42 64>; + qcom,cpr-fuse-ro-sel = <0 4 8>; + qcom,cpr-init-voltage-ref = <1224000 1288000 1352000>; + qcom,cpr-fuse-init-voltage = + <69 12 6 0>, + <69 18 6 0>, + <69 24 6 0>; + qcom,cpr-fuse-quot-offset = + <70 12 7 0>, + <70 19 7 0>, + <70 26 7 0>; + qcom,cpr-fuse-quot-offset-scale = <5 5 5>; + qcom,cpr-init-voltage-step = <8000>; + qcom,cpr-corner-map = <1 2 3>; + qcom,mem-acc-corner-map = <1 2 2>; + qcom,cpr-corner-frequency-map = + <1 1094400000>, + <2 1248000000>, + <3 1401600000>; + qcom,speed-bin-fuse-sel = <39 34 3 0>; + qcom,cpr-fuse-revision = <67 3 3 0>; + qcom,cpr-speed-bin-max-corners = + <(-1) (-1) 1 2 3>; + qcom,cpr-quot-adjust-scaling-factor-max = <0 1400 1400>; + qcom,cpr-voltage-scaling-factor-max = <0 2000 2000>; + qcom,cpr-scaled-init-voltage-as-ceiling; + qcom,cpr-quotient-adjustment = + <0 (-20) 0>; + qcom,cpr-enable; + }; +}; + +&i2c_2 { + /* I2C based external buck for APC */ + hl7503_vreg: hl7503-regulator@60 { + status = "disabled"; + compatible = "halo,hl7503"; + reg = <0x60>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1387500>; + regulator-ramp-delay = <500>; + regulator-always-on; + fcs,suspend-voltage-selector = <0>; + fcs,disable-suspend; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-rumi.dts b/arch/arm/boot/dts/qcom/qcs405-rumi.dts new file mode 100644 index 000000000000..c2a2a78b3d70 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-rumi.dts @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "qcs405.dtsi" +#include "qcs405-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS405 RUMI"; + compatible = "qcom,qcs405-rumi", "qcom,qcs405", "qcom,rumi"; + qcom,board-id = <15 0>; +}; + +&qnand_1 { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-rumi.dtsi b/arch/arm/boot/dts/qcom/qcs405-rumi.dtsi new file mode 100644 index 000000000000..179875e2d149 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-rumi.dtsi @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "qcs405.dtsi" + +&soc { + usb_emu_phy: usb_emu_phy@78ccd00 { + compatible = "qcom,usb-emu-phy"; + reg = <0x78ccd00 0x9500>, + <0x79b8800 0x100>; + reg-names = "base", "qcratch_base"; + + qcom,emu-init-seq = <0xfff0 0x4 + 0xfff3 0x4 + 0x40 0x4 + 0xfff3 0x4 + 0xfff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x1a0 0x20 + 0x100000 0x3c + 0x0 0x3c + 0x10060 0x3c + 0x0 0x4>; + }; + + timer { + clock-frequency = <0x100000>; + }; + + timer@0xb020000{ + clock-frequency = <0x100000>; + }; +}; + +&usb3 { + /delete-property/ extcon; + status = "disabled"; +}; + +&usb2s { + /delete-property/ extcon; + dwc3@78c0000 { + usb-phy = <&usb_emu_phy>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; +}; + +&rpm_bus { + /delete-node/ rpm-regulator-smpa1; + /delete-node/ rpm-regulator-smpa2; + /delete-node/ rpm-regulator-smpa4; + /delete-node/ rpm-regulator-ldoa1; + /delete-node/ rpm-regulator-ldoa2; + /delete-node/ rpm-regulator-ldoa3; + /delete-node/ rpm-regulator-ldoa4; + /delete-node/ rpm-regulator-ldoa5; + /delete-node/ rpm-regulator-ldoa6; + /delete-node/ rpm-regulator-ldoa7; + /delete-node/ rpm-regulator-ldoa8; + /delete-node/ rpm-regulator-ldoa9; + /delete-node/ rpm-regulator-ldoa10; + /delete-node/ rpm-regulator-ldoa11; + /delete-node/ rpm-regulator-ldoa12; + /delete-node/ rpm-regulator-ldoa13; +}; + +&soc { + /delete-node/ qcom,spmi@200f000; + /delete-node/ regulator@1942120; + /delete-node/ regulator@b018000; + /delete-node/ usb3_extcon; +}; + +&rpm_bus { + rpm-standalone; +}; + +&thermal_zones { + /delete-node/ aoss-lowf; + /delete-node/ xo-therm-usr; + /delete-node/ pa-therm1-usr; + /delete-node/ pa-therm3-usr; +}; + +#include "qcs405-stub-regulator.dtsi" + +&sdhc_1 { + /* VDD external regulator is enabled/disabled by pms405_l6 */ + vdd-io-supply = <&pms405_l6>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1704000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000>; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + + status = "ok"; +}; + +&sdhc_2 { + /* VDD is an external regulator eLDO5 */ + vdd-io-supply = <&pms405_l11>; + qcom,vdd-io-voltage-level = <2696000 3304000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50"; + + status = "disabled"; +}; + +&smb1351_otg_supply { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-stub-regulator.dtsi b/arch/arm/boot/dts/qcom/qcs405-stub-regulator.dtsi new file mode 100644 index 000000000000..9ef1c13731cf --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-stub-regulator.dtsi @@ -0,0 +1,194 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Stub regulators */ + +/ { + /* PMS405_S1 - VDD_MX/CX supply */ + pms405_s1_level: regulator-pms405-s1-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pms405_s1_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + pms405_s1_floor_level: regulator-pms405-s1-floor-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pms405_s1_floor_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + pms405_s1_level_ao: regulator-pms405-s1-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pms405_s1_level_ao"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + /* PMS405_S2 - VDD_LPI_CX supply */ + pms405_s2_level: regulator-pms405-s2-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pms405_s2_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + pms405_s2_floor_level: regulator-pms405-s2-floor-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pms405_s2_floor_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + pms405_s4: regulator-pms405-s4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pms405_s4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1728000>; + regulator-max-microvolt = <1920000>; + }; + + pms405_l1: regulator-pms405-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pms405_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1240000>; + regulator-max-microvolt = <1352000>; + }; + + pms405_l2: regulator-pms405-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pms405_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1048000>; + regulator-max-microvolt = <1280000>; + }; + + pms405_l3: regulator-pms405-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pms405_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <976000>; + regulator-max-microvolt = <1160000>; + }; + + pms405_l4: regulator-pms405-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pms405_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1256000>; + }; + + pms405_l5: regulator-pms405-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pms405_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pms405_l5_ao: regulator-pms405-l5-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pms405_l5_ao"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pms405_l6: regulator-pms405-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pms405_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1896000>; + }; + + pms405_l7: regulator-pms405-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pms405_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1616000>; + regulator-max-microvolt = <3000000>; + }; + + pms405_l8: regulator-pms405-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pms405_l8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1136000>; + regulator-max-microvolt = <1352000>; + }; + + /* PMS405 L9 - VDD_LPI_MX supply */ + pms405_l9_level: regulator-pms405-l9-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pms405_l9_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + pms405_l9_floor_level: regulator-pms405-l9-floor-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pms405_l9_floor_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + pms405_l10: regulator-pms405-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pms405_l10"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2936000>; + regulator-max-microvolt = <3088000>; + }; + + pms405_l11: regulator-pms405-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pms405_l11"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <3304000>; + }; + + pms405_l12: regulator-pms405-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pms405_l12"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2968000>; + regulator-max-microvolt = <3300000>; + }; + + pms405_l13: regulator-pms405-l13 { + compatible = "qcom,stub-regulator"; + regulator-name = "pms405_l13"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + /* VDD_APC supply */ + apc_vreg_corner: regulator-apc-corner { + compatible = "qcom,stub-regulator"; + regulator-name = "apc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <3>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-tasha.dtsi b/arch/arm/boot/dts/qcom/qcs405-tasha.dtsi new file mode 100644 index 000000000000..26183bc3cb16 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-tasha.dtsi @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + wcd9xxx_intc: wcd9xxx-irq { + compatible = "qcom,wcd9xxx-irq"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&tlmm>; + qcom,gpio-connect = <&tlmm 105 0>; + pinctrl-names = "default"; + pinctrl-0 = <&wcd_intr_default>; + }; + + clock_audio: audio_ext_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = <0>; + qcom,use-pinctrl = <1>; + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&tasha_mclk_default>; + pinctrl-1 = <&tasha_mclk_default>; + clock-names = "osr_clk"; + clocks = <&pms405_clkdiv>; + pmic-clock-names = "pms405_div_clk1"; + #clock-cells = <1>; + }; + + wcd_rst_gpio: msm_cdc_pinctrl@46 { + compatible = "qcom,msm-cdc-pinctrl"; + qcom,cdc-rst-n-gpio = <&tlmm 46 0>; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_reset_active>; + pinctrl-1 = <&cdc_reset_sleep>; + }; + + lineout_booster_gpio: msm_cdc_pinctrl@113 { + compatible = "qcom,msm-cdc-pinctrl"; + qcom,lo-booster-gpio = <&tlmm 113 0>; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&lineout_booster_active>; + pinctrl-1 = <&lineout_booster_sleep>; + }; +}; + +&slim_aud { + wcd9335: tasha_codec { + compatible = "qcom,tasha-slim-pgd"; + elemental-addr = [00 01 a0 01 17 02]; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 + 30>; + + qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; + + clock-names = "wcd_clk"; + clocks = <&clock_audio AUDIO_PMI_CLK>; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; + + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-slim-ifd = "tasha-slim-ifd"; + qcom,cdc-slim-ifd-elemental-addr = [00 00 a0 01 17 02]; + qcom,cdc-dmic-sample-rate = <4800000>; + qcom,cdc-mad-dmic-rate = <600000>; + qcom,vote-dynamic-supply-on-demand = <1>; + + cdc-vdd-buck-supply = <&pms405_s4>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <594000>; + + cdc-buck-sido-supply = <&pms405_s4>; + qcom,cdc-buck-sido-voltage = <1800000 1800000>; + qcom,cdc-buck-sido-current = <200000>; + + cdc-vdd-tx-h-supply = <&pms405_l6>; + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-tx-h-current = <25000>; + + cdc-vdd-rx-h-supply = <&pms405_l6>; + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-rx-h-current = <25000>; + + cdc-vdd-px-supply = <&pms405_l6>; + qcom,cdc-vdd-px-voltage = <1800000 1800000>; + qcom,cdc-vdd-px-current = <9000>; + + qcom,cdc-static-supplies = "cdc-vdd-buck", + "cdc-buck-sido", + "cdc-vdd-px"; + + qcom,cdc-on-demand-supplies = "cdc-vdd-tx-h", + "cdc-vdd-rx-h"; + }; +}; + +&qcs405_snd { + qcom,lineout-booster-gpio = <&lineout_booster_gpio>; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-tdm-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/qcs405-tdm-audio-overlay.dtsi new file mode 100644 index 000000000000..17d31c49c63a --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-tdm-audio-overlay.dtsi @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&q6core { + cdc_quin_mi2s_gpios: msm_cdc_pinctrl_quin { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&quin_mi2s_sck_active &quin_mi2s_ws_active + &quin_mi2s_sd0_active &quin_mi2s_sd1_active + &quin_mi2s_sd2_active &quin_mi2s_sd3_active>; + pinctrl-1 = <&quin_mi2s_sck_sleep &quin_mi2s_ws_sleep + &quin_mi2s_sd0_sleep &quin_mi2s_sd1_sleep + &quin_mi2s_sd2_sleep &quin_mi2s_sd3_sleep>; + qcom,lpi-gpios; + }; +}; + +&q6core { + bolero: bolero-cdc { + compatible = "qcom,bolero-codec"; + clock-names = "lpass_core_hw_vote"; + clocks = <&lpass_core_hw_vote 0>; + qcom,num-macros = <1>; + }; +}; + +&qcs405_snd { + qcom,model = "qcs405-tdm-snd-card"; + qcom,va-bolero-codec = <1>; + qcom,tasha-codec = <1>; + asoc-codec = <&stub_codec>, <&bolero>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec"; + qcom,quin-mi2s-gpios = <&cdc_quin_mi2s_gpios>; + tdm-vdd-micb-supply = <&pms405_l7>; + qcom,tdm-vdd-micb-voltage = <1800000 1800000>; + qcom,tdm-vdd-micb-current = <13000>; + qcom,audio-routing = + "RX_BIAS", "MCLK", + "lineout booster", "LINEOUT1", + "lineout booster", "LINEOUT2", + "LINEOUT1", "rx regulator", + "LINEOUT2", "rx regulator", + "AMIC3", "tx regulator", + "AMIC4", "tx regulator", + "AMIC3", "MIC BIAS3", + "AMIC4", "MIC BIAS4", + "MIC BIAS3", "Analog Mic3", + "MIC BIAS4", "Analog Mic4", + "VA DMIC0", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic0", + "VA DMIC1", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic1", + "VA DMIC2", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic2", + "VA DMIC3", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic3", + "VA DMIC4", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic4", + "VA DMIC5", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic5", + "VA DMIC6", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic6", + "VA DMIC7", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic7"; + pinctrl-names = "default"; + pinctrl-0 = <&spdifrx_opt_default>; +}; + +&tdm_quin_tx { + qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>; + qcom,msm-cpudai-tdm-sync-mode = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; +}; + +#include "qcs405-tasha.dtsi" +#include "qcs405-va-bolero.dtsi" + diff --git a/arch/arm/boot/dts/qcom/qcs405-thermal.dtsi b/arch/arm/boot/dts/qcom/qcs405-thermal.dtsi new file mode 100644 index 000000000000..89ea35cba095 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-thermal.dtsi @@ -0,0 +1,417 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + modem { + qcom,instance-id = <0x0>; + + modem_pa: modem_pa { + qcom,qmi-dev-name = "pa"; + #cooling-cells = <2>; + }; + + modem_proc: modem_proc { + qcom,qmi-dev-name = "modem"; + #cooling-cells = <2>; + }; + + modem_current: modem_current { + qcom,qmi-dev-name = "modem_current"; + #cooling-cells = <2>; + }; + + modem_vdd: modem_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + }; +}; + +&rpm_bus { + rpm_smd_cdev: rpm-smd-cdev { + compatible = "qcom,rpm-smd-cooling-device"; + #cooling-cells = <2>; + }; +}; + +&thermal_zones { + aoss-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 0>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + q6-hvx-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 1>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + lpass-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wlan-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 3>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpuss-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpuss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpuss-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpuss-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + gpu-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpuss-max-step { + polling-delay-passive = <50>; + polling-delay = <100>; + thermal-governor = "step_wise"; + trips { + cpu_trip:cpu-trip { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&cpu_trip>; + cooling-device = + <&CPU0 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + cpu1_cdev { + trip = <&cpu_trip>; + cooling-device = + <&CPU1 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + cpu2_cdev { + trip = <&cpu_trip>; + cooling-device = + <&CPU2 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + cpu3_cdev { + trip = <&cpu_trip>; + cooling-device = + <&CPU3 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + }; + }; + + gpu-step { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + thermal-governor = "step_wise"; + trips { + gpu_step_trip: gpu-step-trip { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + }; + cooling-maps { + gpu_cdev0 { + trip = <&gpu_step_trip>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + cpuss-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + thermal-governor = "step_wise"; + trips { + cpuss_0_step_trip: cpuss-0-step-trip { + temperature = <118000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&cpuss_0_step_trip>; + cooling-device = + <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpuss-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + thermal-governor = "step_wise"; + trips { + cpuss_1_step_trip: cpuss-1-step-trip { + temperature = <118000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu1_cdev { + trip = <&cpuss_1_step_trip>; + cooling-device = + <&CPU1 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpuss-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "step_wise"; + trips { + cpuss_2_step_trip: cpuss-2-step-trip { + temperature = <118000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu2_cdev { + trip = <&cpuss_2_step_trip>; + cooling-device = + <&CPU2 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpuss-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "step_wise"; + trips { + cpuss_3_step_trip: cpuss-3-step-trip { + temperature = <118000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu3_cdev { + trip = <&cpuss_3_step_trip>; + cooling-device = + <&CPU3 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + aoss-lowc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_cap"; + thermal-sensors = <&tsens0 0>; + tracks-low; + trips { + aoss_lowc: aoss-lowc { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + rpm_smd_cdev { + trip = <&aoss_lowc>; + cooling-device = <&rpm_smd_cdev 2 2>; + }; + }; + }; + + aoss-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 0>; + tracks-low; + trips { + aoss_lowf: aoss-lowf { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&aoss_lowf>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; + }; + cx_vdd_cdev { + trip = <&aoss_lowf>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&aoss_lowf>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&aoss_lowf>; + cooling-device = <&modem_vdd 0 0>; + }; + }; + }; + + xo-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pms405_adc_tm_iio ADC_XO_THERM_PU2>; + }; + + pa-therm1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pms405_adc_tm_iio ADC_AMUX_THM1_PU2>; + }; + + pa-therm3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pms405_adc_tm_iio ADC_AMUX_THM3_PU2>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-usb.dtsi b/arch/arm/boot/dts/qcom/qcs405-usb.dtsi new file mode 100644 index 000000000000..b9ca3ff635d2 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-usb.dtsi @@ -0,0 +1,216 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&soc { + /* Secondary USB port related controller */ + usb3: ssusb@7580000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x7580000 0x100000>; + reg-names = "core_base"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <0 25 0>, <0 319 0>; + interrupt-names = "pwr_event_irq", "hs_phy_irq"; + + dpdm-supply = <&usb2_phy0>; + clocks = <&clock_gcc GCC_USB30_MASTER_CLK>, + <&clock_gcc GCC_SYS_NOC_USB3_CLK>, + <&clock_gcc GCC_USB30_SLEEP_CLK>, + <&clock_gcc GCC_USB30_MOCK_UTMI_CLK>, + <&clock_rpmcc CXO_SMD_OTG_CLK>, + <&clock_gcc GCC_PCNOC_USB3_CLK>; + clock-names = "core_clk", "iface_clk", "sleep_clk", + "utmi_clk", "xo", "noc_aggr_clk"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <10000000>; + + qcom,pm-qos-latency = <181>; + qcom,msm-bus,name = "usb3"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + + resets = <&clock_gcc GCC_USB_30_BCR>; + reset-names = "core_reset"; + + dwc3@7580000 { + compatible = "snps,dwc3"; + reg = <0x7580000 0xcd00>; + interrupts = <0 26 0>; + usb-phy = <&usb2_phy1>, <&usb_ss_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3-u1u2-disable; + usb-core-id = <1>; + maximum-speed = "super-speed"; + dr_mode = "host"; + }; + }; + + /* Secondary USB port related High Speed PHY */ + usb2_phy1: hsphy@7a000 { + compatible = "qcom,usb-snps-hsphy"; + reg = <0x7a000 0x200>; + reg-names = "phy_csr"; + + vdd-supply = <&pms405_l4>; + vdda18-supply = <&pms405_l5>; + vdda33-supply = <&pms405_l12>; + qcom,vdd-voltage-level = <0 1144000 1200000>; + + clocks = <&clock_rpmcc RPM_SMD_LN_BB_CLK>, + <&clock_gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&clock_gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref_clk", "phy_csr_clk", "sleep_clk"; + + resets = <&clock_gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, + <&clock_gcc GCC_USB2A_PHY_BCR>; + reset-names = "phy_reset", "phy_por_reset"; + + qcom,snps-hs-phy-init-seq = + <0xc0 0x01 0>, + <0xe8 0x0d 0>, + <0x74 0x12 0>, + <0x98 0x63 0>, + <0x9c 0x03 0>, + <0xa0 0x1d 0>, + <0xa4 0x03 0>, + <0x8c 0x23 0>, + <0x78 0x08 0>, + <0x7c 0xdc 0>, + <0x90 0xe0 20>, + <0x74 0x10 0>, + <0x90 0x60 0>, + <0xffffffff 0xffffffff 0>; + }; + + /* Secondary USB port related Super Speed PHY */ + usb_ss_phy: ssphy@78000 { + compatible = "qcom,usb-ssphy"; + reg = <0x78000 0x400>; + vdd-supply = <&pms405_l3>; + vdda18-supply = <&pms405_l5>; + qcom,vdd-voltage-level = <0 1050000 1050000>; + + clocks = <&clock_cmn_blk_pll CMN_BLK_PLL>, + <&clock_gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&clock_gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "ref_clk", "cfg_ahb_clk", "pipe_clk"; + + resets = <&clock_gcc GCC_USB3_PHY_BCR>, + <&clock_gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "phy_reset", "phy_com_reset"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + /* Primary USB port related controller */ + usb2s: hsusb@78c0000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x78c0000 0x100000>; + reg-names = "core_base"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <0 32 0>, <0 318 0>; + interrupt-names = "pwr_event_irq", "hs_phy_irq"; + + clocks = <&clock_gcc GCC_USB_HS_SYSTEM_CLK>, + <&clock_gcc GCC_PCNOC_USB2_CLK>, + <&clock_gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, + <&clock_gcc GCC_USB20_MOCK_UTMI_CLK>, + <&clock_rpmcc CXO_SMD_OTG_CLK>; + clock-names = "core_clk", "iface_clk", "sleep_clk", + "utmi_clk", "xo"; + + qcom,core-clk-rate = <133333333>; + qcom,msm-bus,name = "usb2s"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + + resets = <&clock_gcc GCC_USB_HS_BCR>; + reset-names = "core_reset"; + + dwc3@78c0000 { + compatible = "snps,dwc3"; + reg = <0x78c0000 0xcd00>; + interrupts = <0 44 0>; + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + usb-core-id = <0>; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + /* Primary USB port related High Speed PHY */ + usb2_phy0: hsphy@7c000 { + compatible = "qcom,usb-snps-hsphy"; + reg = <0x7c000 0x200>; + reg-names = "phy_csr"; + + vdd-supply = <&pms405_l4>; + vdda18-supply = <&pms405_l5>; + vdda33-supply = <&pms405_l12>; + qcom,vdd-voltage-level = <0 1144000 1200000>; + + clocks = <&clock_rpmcc RPM_SMD_LN_BB_CLK>, + <&clock_gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&clock_gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref_clk", "phy_csr_clk", "sleep_clk"; + + resets = <&clock_gcc GCC_QUSB2_PHY_BCR>, + <&clock_gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names = "phy_reset", "phy_por_reset"; + + qcom,snps-hs-phy-init-seq = + <0xc0 0x01 0>, + <0xe8 0x0d 0>, + <0x74 0x12 0>, + <0x98 0x63 0>, + <0x9c 0x03 0>, + <0xa0 0x1d 0>, + <0xa4 0x03 0>, + <0x8c 0x23 0>, + <0x78 0x08 0>, + <0x7c 0xdc 0>, + <0x90 0xe0 20>, + <0x74 0x10 0>, + <0x90 0x60 0>, + <0xffffffff 0xffffffff 0>; + }; + +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-va-bolero.dtsi b/arch/arm/boot/dts/qcom/qcs405-va-bolero.dtsi new file mode 100644 index 000000000000..766714c24e6f --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-va-bolero.dtsi @@ -0,0 +1,38 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&bolero { + va_macro: va_macro { + compatible = "qcom,va-macro"; + reg = <0x0C490000 0x0>; + clock-names = "va_core_clk"; + clocks = <&clock_audio_va 0>; + va-vdd-micb-supply = <&pms405_l7>; + qcom,va-vdd-micb-voltage = <1800000 1800000>; + qcom,va-vdd-micb-current = <9000>; + qcom,va-dmic-sample-rate = <600000>; + }; +}; + +&soc { + clock_audio_va: va_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = <2>; + qcom,codec-lpass-ext-clk-freq = <9600000>; + qcom,codec-lpass-clk-id = <0x30B>; + #clock-cells = <1>; + }; +}; + +&va_cdc_dma_0_tx { + qcom,msm-dai-is-island-supported = <1>; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-wsa-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/qcs405-wsa-audio-overlay.dtsi new file mode 100644 index 000000000000..7508cf714e6c --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-wsa-audio-overlay.dtsi @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&q6core { + wsa_swr_gpios: wsa_swr_clk_data_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wsa_swr_clk_active &wsa_swr_data_active>; + pinctrl-1 = <&wsa_swr_clk_sleep &wsa_swr_data_sleep>; + qcom,lpi-gpios; + }; + + wsa_spkr_en_1_2: wsa_spkr_en_1_2_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wsa_en_1_2_active>; + pinctrl-1 = <&wsa_en_1_2_sleep>; + }; + + cdc_dmic01_gpios: cdc_dmic01_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>; + pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>; + qcom,lpi-gpios; + }; + + cdc_dmic23_gpios: cdc_dmic23_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>; + pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>; + qcom,lpi-gpios; + }; + + cdc_dmic45_gpios: cdc_dmic45_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>; + pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>; + qcom,lpi-gpios; + }; + + cdc_dmic67_gpios: cdc_dmic67_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic67_clk_active &cdc_dmic67_data_active>; + pinctrl-1 = <&cdc_dmic67_clk_sleep &cdc_dmic67_data_sleep>; + qcom,lpi-gpios; + }; + +}; + +&q6core { + bolero: bolero-cdc { + compatible = "qcom,bolero-codec"; + clock-names = "lpass_core_hw_vote"; + clocks = <&lpass_core_hw_vote 0>; + qcom,num-macros = <2>; + }; +}; + +&qcs405_snd { + qcom,model = "qcs405-wsa-snd-card"; + qcom,va-bolero-codec = <1>; + qcom,wsa-bolero-codec = <1>; + qcom,tasha-codec = <1>; + asoc-codec = <&stub_codec>, <&bolero>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec"; + qcom,wsa-max-devs = <2>; + qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>, + <&wsa881x_0213>, <&wsa881x_0214>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", + "SpkrLeft", "SpkrRight"; + qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; + qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; + qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>; + qcom,cdc-dmic67-gpios = <&cdc_dmic67_gpios>; + qcom,audio-routing = + "RX_BIAS", "MCLK", + "lineout booster", "LINEOUT1", + "lineout booster", "LINEOUT2", + "LINEOUT1", "rx regulator", + "LINEOUT2", "rx regulator", + "AMIC3", "tx regulator", + "AMIC4", "tx regulator", + "AMIC3", "MIC BIAS3", + "AMIC4", "MIC BIAS4", + "MIC BIAS3", "Analog Mic3", + "MIC BIAS4", "Analog Mic4", + "VA DMIC0", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic0", + "VA DMIC1", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic1", + "VA DMIC2", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic2", + "VA DMIC3", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic3", + "VA DMIC4", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic4", + "VA DMIC5", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic5", + "VA DMIC6", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic6", + "VA DMIC7", "VA MIC BIAS1", + "VA MIC BIAS1", "Digital Mic7", + "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "WSA_SPK1 OUT", "VA_MCLK", + "WSA_SPK2 OUT", "VA_MCLK"; +}; + +#include "qcs405-tasha.dtsi" +#include "qcs405-va-bolero.dtsi" +#include "qcs405-wsa-bolero.dtsi" +#include "qcs405-wsa881x.dtsi" + diff --git a/arch/arm/boot/dts/qcom/qcs405-wsa-bolero.dtsi b/arch/arm/boot/dts/qcom/qcs405-wsa-bolero.dtsi new file mode 100644 index 000000000000..921b2dd76c61 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-wsa-bolero.dtsi @@ -0,0 +1,40 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&bolero { + wsa_macro: wsa-macro { + compatible = "qcom,wsa-macro"; + reg = <0x0C2C0000 0x0>; + clock-names = "wsa_core_clk", "wsa_npl_clk"; + clocks = <&clock_audio_wsa_1 0>, + <&clock_audio_wsa_2 0>; + qcom,wsa-swr-gpios = <&wsa_swr_gpios>; + }; +}; + +&soc { + clock_audio_wsa_1: wsa_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = <3>; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x309>; + #clock-cells = <1>; + }; + + clock_audio_wsa_2: wsa_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = <4>; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x30A>; + #clock-cells = <1>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405-wsa881x.dtsi b/arch/arm/boot/dts/qcom/qcs405-wsa881x.dtsi new file mode 100644 index 000000000000..cbcfc52bea80 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405-wsa881x.dtsi @@ -0,0 +1,61 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/{ + aliases { + swr0 = &swr_0; + }; +}; + +#include + +&wsa_macro { + swr_0: wsa_swr_master { + compatible = "qcom,swr-mstr"; + #address-cells = <2>; + #size-cells = <0>; + swrm-io-base = <0x0C2D0000 0x0>; + interrupts = <0 294 0>; + interrupt-names = "swr_master_irq"; + qcom,swr-num-ports = <8>; + qcom,swr-port-mapping = <1 SPKR_L 0x1>, + <2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>, + <4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>, + <6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>, + <8 SPKR_R_VI 0x3>; + qcom,swr-num-dev = <2>; + qcom,swr_master_id = <1>; + wsa881x_0211: wsa881x@20170211 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x20170211>; + qcom,spkr-sd-n-node = <&wsa_spkr_en_1_2>; + }; + + wsa881x_0212: wsa881x@20170212 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x20170212>; + qcom,spkr-sd-n-node = <&wsa_spkr_en_1_2>; + }; + + wsa881x_0213: wsa881x@21170213 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x21170213>; + qcom,spkr-sd-n-node = <&wsa_spkr_en_1_2>; + }; + + wsa881x_0214: wsa881x@21170214 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x21170214>; + qcom,spkr-sd-n-node = <&wsa_spkr_en_1_2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs405.dtsi b/arch/arm/boot/dts/qcom/qcs405.dtsi new file mode 100644 index 000000000000..a669dcfc8f58 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs405.dtsi @@ -0,0 +1,1691 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "skeleton64.dtsi" +#include +#include +#include +#include +#include +#include +#include +#include + +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} + +/ { + model = "Qualcomm Technologies, Inc. QCS405"; + compatible = "qcom,qcs405"; + qcom,msm-id = <352 0x0>; + interrupt-parent = <&wakegic>; + + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + }; + + reserved_mem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + removed_region0: removed_region@85900000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x85900000 0x0 0x600000>; + }; + + smem_region: smem@85f00000 { + no-map; + reg = <0x0 0x85f00000 0x0 0x200000>; + }; + + removed_region1: removed_region@86100000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x86100000 0x0 0x300000>; + }; + + wlan_fw_mem: wlan_fw_mem@86400000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x86400000 0x0 0x1000000>; + }; + + adsp_fw_mem: adsp_fw_mem@87500000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x87400000 0x0 0x1400000>; + }; + + cdsp_fw_mem: cdsp_fw_mem@88f00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x88800000 0x0 0x600000>; + }; + + wlan_msa_mem: wlan_msa_region@89500000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x88E00000 0x0 0x100000>; + }; + + secure_mem: secure_region { + status = "disabled"; + compatible = "shared-dma-pool"; + reusable; + alignment = <0 0x400000>; + size = <0 0x7000000>; + }; + + mdf_mem: mdf_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + reusable; + alignment = <0 0x400000>; + size = <0 0x1000000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + reusable; + alignment = <0 0x400000>; + size = <0 0x400000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x400000>; + }; + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x1000000>; + linux,cma-default; + }; + }; + + aliases { + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ + sdhc2 = &sdhc_2; /* SDC2 SD Card slot */ + qpic_nand1 = &qnand_1; + pci-domain0 = &pcie0; /* PCIe0 domain */ + mhi0 = &mhi_0; + mhi_netdev0 = &mhi_netdev_0; + mhi_netdev1 = &mhi_netdev_1; + mhi_netdev2 = &mhi_netdev_2; + mhi_netdev3 = &mhi_netdev_3; + mhi_netdev4 = &mhi_netdev_4; + mhi_netdev5 = &mhi_netdev_5; + }; + + soc: soc { }; + +}; + +#include "qcs405-pinctrl.dtsi" +#include "qcs405-blsp.dtsi" +#include "qcs405-cpu.dtsi" +#include "qcs405-ion.dtsi" +#include "qcs405-pm.dtsi" +#include "msm-arm-smmu-qcs405.dtsi" +#include "qcs405-gpu.dtsi" +#include "qcs405-mdss-pll.dtsi" +#include "qcs405-mdss.dtsi" + +&i2c_5 { /* BLSP (NTAG) */ + nq@55 { + status = "disabled"; + compatible = "qcom,nq-ntag"; + reg = <0x55>; + qcom,nq-ntagfd = <&tlmm 53 GPIO_ACTIVE_LOW>; + interrupt-parent = <&tlmm>; + interrupts = <53 0>; + interrupt-names = "ntag_fd"; + pinctrl-names = "ntag_active", "ntag_suspend"; + pinctrl-0 = <&ntag_int_active>; + pinctrl-1 = <&ntag_int_suspend>; + }; +}; + + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + wakegic: wake-gic { + compatible = "qcom,mpm-gic-qcs405", "qcom,mpm-gic"; + interrupts = ; + reg = <0x601b8 0x1000>, + <0xb011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + qcom,num-mpm-irqs = <96>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <3>; + }; + + wakegpio: wake-gpio { + compatible = "qcom,mpm-gpio-qcs405", "qcom,mpm-gpio"; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 2 0xff08>, + <1 3 0xff08>, + <1 4 0xff08>, + <1 1 0xff08>; + clock-frequency = <19200000>; + }; + + timer@b120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xb120000 0x1000>; + clock-frequency = <19200000>; + + frame@b121000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0xb121000 0x1000>, + <0xb122000 0x1000>; + }; + + frame@b123000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0xb123000 0x1000>; + status = "disabled"; + }; + + frame@b124000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0xb124000 0x1000>; + status = "disabled"; + }; + + frame@b125000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0xb125000 0x1000>; + status = "disabled"; + }; + + frame@b126000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0xb126000 0x1000>; + status = "disabled"; + }; + + frame@b127000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0xb127000 0x1000>; + status = "disabled"; + }; + + frame@b128000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0xb128000 0x1000>; + status = "disabled"; + }; + }; + + clocks { + xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "xo_board"; + }; + }; + + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x4ab000 0x4>, + <0x193d100 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + qcom,mpm2-sleep-counter@4a3000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x4a3000 0x1000>; + clock-frequency = <32768>; + }; + + clock_rpmcc: qcom,rpmcc { + compatible = "qcom,rpmcc-qcs405"; + #clock-cells = <1>; + }; + + clock_gcc: qcom,gcc { + compatible = "qcom,gcc-qcs405", "syscon"; + reg = <0x1800000 0x80000>; + reg-names = "cc_base"; + vdd_cx-supply = <&pms405_s1_level>; + clocks = <&clock_rpmcc RPM_SMD_XO_CLK_SRC>; + qcom,gcc_oxili_gfx3d_clk-opp-handle = <&msm_gpu>; + clock-names = "cxo"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_cmn_blk_pll: qcom,cmn_blk_pll@2f780 { + compatible = "qcom,cmn_blk_pll"; + reg = <0x2f780 0x4>; + reg-names = "cmn_blk"; + clocks = <&clock_gcc GCC_BIAS_PLL_MISC_RESET_CLK>, + <&clock_gcc GCC_BIAS_PLL_AHB_CLK>, + <&clock_gcc GCC_BIAS_PLL_AON_CLK>; + clock-names = "misc_reset_clk", "ahb_clk", "aon_clk"; + resets = <&clock_gcc GCC_BIAS_PLL_BCR>; + reset-names = "cmn_blk_pll_reset"; + #clock-cells = <1>; + }; + + clock_gcc_mdss: qcom,gcc-mdss@1800000 { + compatible = "qcom,gcc-mdss-qcs405"; + reg = <0x1800000 0x80000>; + clocks = <&mdss_dsi0_pll PCLK_SRC_0_CLK>, + <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>; + clock-names = "pclk0_src", "byte0_src"; + #clock-cells = <1>; + }; + + clock_debugcc: qcom,cc-debug { + compatible = "qcom,debugcc-qcs405"; + qcom,gcc = <&clock_gcc>; + qcom,cpucc = <&cpucc_debug>; + clocks = <&clock_rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo_clk_src"; + #clock-cells = <1>; + }; + + cpucc_debug: syscon@0b01101c { + compatible = "syscon"; + reg = <0xb01101c 0x4>; + }; + + clock_cpu: qcom,clock-cpu@0b011050 { + compatible = "qcom,cpu-qcs405"; + clocks = <&clock_rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&clock_gcc GPLL0_AO_OUT_MAIN>; + clock-names = "xo_ao", "gpll0_ao" ; + reg = <0x0b011050 0x8>, + <0xb016000 0x34>; + reg-names = "apcs_cmd" , "apcs_pll"; + cpu-vdd-supply = <&apc_vreg_corner>; + vdd_dig_ao-supply = <&pms405_s1_level_ao>; + vdd_hf_pll-supply = <&pms405_l5_ao>; + qcom,speed0-bin-v0 = + < 0 0>, + < 1094400000 1>, + < 1248000000 2>, + < 1401600000 3>; + #clock-cells = <1>; + }; + + cpu-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <1 7 0xff00>; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + + slim_aud: slim@c1c0000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0xc1c0000 0x2c000>, + <0xc184000 0x2a000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 163 0>, <0 180 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x7c0000>; + qcom,ea-pc = <0x2e0>; + status = "disabled"; + }; + + slim_qca: slim@c240000 { + cell-index = <3>; + compatible = "qcom,slim-ngd"; + reg = <0xc240000 0x2c000>, + <0xc204000 0x20000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 191 0>, <0 63 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + status = "ok"; + + /* Slimbus Slave DT for WCN3990 */ + btfmslim_codec: wcn3990 { + compatible = "qcom,btfmslim_slave"; + elemental-addr = [00 01 20 02 17 02]; + qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; + qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; + }; + }; + + blsp1_uart2_console: serial@78b1000 { + compatible = "qcom,msm-uartdm", "qcom,msm-uartdm-v1.4"; + reg = <0x78b1000 0x200>; + interrupts = <0 118 0>; + clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, + <&clock_gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&blsp_uart_tx_a2_active + &blsp_uart_rx_a2_active>; + pinctrl-1 = <&blsp_uart_tx_rx_a2_sleep>; + status = "okay"; + }; + + dcc: dcc_v2@b2000 { + compatible = "qcom,dcc-v2"; + reg = <0x000b2000 0x1000>, + <0x000bfc00 0x400>; + + reg-names = "dcc-base", "dcc-ram-base"; + dcc-ram-offset = <0x400>; + qcom,curr-link-list = <1>; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + interrupts = ; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + + spmi_bus: qcom,spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x200f000 0x1000>, + <0x2400000 0x800000>, + <0x2c00000 0x800000>, + <0x3800000 0x200000>, + <0x200a000 0x2100>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + qcom,wdt@b017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xb017000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 3 0>, <0 4 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + qcom,ipi-ping; + qcom,wakeup-enable; + status = "okay"; + }; + + qcom,chd { + compatible = "qcom,core-hang-detect"; + label = "gold"; + qcom,threshold-arr = <0xb088094 0xb098094 0xb0a8094 + 0xb0b8094>; + qcom,config-arr = <0xb08809c 0xb09809c 0xb0a809c + 0xb0b809c>; + staus = "disabled"; + }; + + qcom,msm-imem@8600000 { + compatible = "qcom,msm-imem"; + reg = <0x08600000 0x1000>; /* Address and size of IMEM */ + ranges = <0x0 0x08600000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 8>; + }; + + dload_type@18 { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x18 4>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 32>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 200>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 200>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 12>; + }; + }; + + qcom,lpass@c000000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xc000000 0x00100>; + + vdd_cx-supply = <&pms405_s2_level>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + + clocks = <&clock_rpmcc CXO_SMD_PIL_LPASS_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <1>; + qcom,mas-crypto = <&mas_crypto>; + qcom,complete-ramdump; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,sysmon-id = <1>; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + + /* GPIO inputs from lpass */ + interrupts-extended = <&intc 0 293 1>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + /* GPIO output to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + memory-region = <&adsp_fw_mem>; + }; + + qcom,turing@800000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x800000 0x00100>; + + vdd_cx-supply = <&pms405_s1_level>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + + clocks = <&clock_rpmcc CXO_SMD_PIL_CDSP_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <18>; + qcom,mas-crypto = <&mas_crypto>; + qcom,complete-ramdump; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <601>; + qcom,sysmon-id = <7>; + qcom,ssctl-instance-id = <0x17>; + qcom,firmware-name = "cdsp"; + + /* GPIO inputs from turing */ + interrupts-extended = <&intc 0 229 1>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + /* GPIO output to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + memory-region = <&cdsp_fw_mem>; + }; + + qcom,wlan_dsp@7000000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x07000000 0x580000>; + + vdd_cx-supply = <&pms405_s1_level>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + + clocks = <&clock_rpmcc CXO_SMD_PIL_PRONTO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <6>; + qcom,mas-crypto = <&mas_crypto>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <421>; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x12>; + qcom,firmware-name = "wcnss"; + + /* GPIO inputs from wcnss */ + interrupts-extended = <&intc 0 153 1>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* GPIO output to wcnss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + memory-region = <&wlan_fw_mem>; + }; + + tsens0: tsens@4a8000 { + compatible = "qcom,qcs405-tsens"; + reg = <0x4a8000 0x1000>, + <0x4a9000 0x1000>, + <0xa4000 0x1000>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical", + "tsens_eeprom_physical"; + interrupts = <0 184 0>; + interrupt-names = "tsens-upper-lower"; + #thermal-sensor-cells = <1>; + }; + + tcsr_mutex_block: syscon@1905000 { + compatible = "syscon"; + reg = <0x1905000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 3>; + }; + + rpm_msg_ram: memory@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x60000 0x6000>; + }; + + apcs: syscon@b011008 { + compatible = "syscon"; + reg = <0xb011008 0x4>; + }; + + apcs_glb: mailbox@b011000 { + compatible = "qcom,msm8916-apcs-kpss-global"; + reg = <0xb011000 0x1000>; + + #mbox-cells = <1>; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + }; + + qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,rpc-latency-us = <611>; + qcom,fastrpc-adsp-audio-pdr; + qcom,fastrpc-adsp-sensors-pdr; + qcom,fastrpc-legacy-remote-heap; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1001 0x0>; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1002 0x0>; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1003 0x0>; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1004 0x0>; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1005 0x0>; + }; + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x804 0x0>; + }; + + qcom,msm_fastrpc_compute_cb7 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x805 0x0>; + }; + + qcom,msm_fastrpc_compute_cb8 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x806 0x0>; + shared-cb = <5>; + }; + }; + + qcom,msm-mdf-mem { + compatible = "qcom,msm-mdf-mem-region"; + qcom,msm-mdf-mem-data-size = <0x800000>; + memory-region = <&mdf_mem>; + }; + + qcom,msm-mdf { + compatible = "qcom,msm-mdf"; + + qcom,msm_mdf_cb1 { + compatible = "qcom,msm-mdf-cb"; + label = "adsp"; + qcom,smmu-enabled; + iommus = <&apps_smmu 0x0800 0x0>; + qcom,smmu-sid-mask = /bits/ 64 <0xf>; + }; + + qcom,msm_mdf_cb2 { + compatible = "qcom,msm-mdf-cb"; + label = "dsps"; + }; + + qcom,msm_mdf_cb3 { + compatible = "qcom,msm-mdf-cb"; + label = "modem"; + }; + + qcom,msm_mdf_cb4 { + compatible = "qcom,msm-mdf-cb"; + label = "cdsp"; + }; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + qcom,rpm_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>, + <&glink_cdsp>, + <&glink_wcnss>; + }; + + }; + + qcom,msm-cdsp-loader { + compatible = "qcom,cdsp-loader"; + qcom,proc-img-to-load = "cdsp"; + }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_wcnss: wcnss { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&apcs_glb 16>; + mbox-names = "wcnss_smem"; + interrupts = ; + + label = "wcnss"; + qcom,glink-label = "mpss"; + + qcom,wcnss_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,wcnss_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>, + <&glink_cdsp>; + }; + }; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&apcs_glb 8>; + mbox-names = "adsp_smem"; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,apr_tal_rpmsg { + qcom,glink-channels = "apr_audio_svc"; + qcom,intents = <0x200 20>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,adsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_wcnss>, + <&glink_cdsp>; + }; + }; + + glink_cdsp: cdsp { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&apcs_glb 12>; + mbox-names = "cdsp_smem"; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,cdsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_wcnss>, + <&glink_adsp>; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + qcom,ipc = <&apcs 0 18>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = ; + qcom,ipc = <&apcs 0 10>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + }; + + qcom,smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts = ; + qcom,ipc = <&apcs 0 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom_crypto: qcrypto@720000 { + compatible = "qcom,qcrypto"; + reg = <0x720000 0x20000>, + <0x704000 0x20000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 206 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + qcom,clk-mgmt-sus-res; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 393600 393600>; + clock-names = + "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = + <&clock_rpmcc QCRYPTO_CE1_CLK>, + <&clock_rpmcc QCRYPTO_CE1_CLK>, + <&clock_rpmcc QCRYPTO_CE1_CLK>, + <&clock_rpmcc QCRYPTO_CE1_CLK>; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-hmac-algo; + qcom,use-sw-aead-algo; + qcom,smmu-s1-enable; + iommus = <&apps_smmu 0x0064 0x0011>, + <&apps_smmu 0x0074 0x0011>; + }; + + qcom_cedev: qcedev@720000 { + compatible = "qcom,qcedev"; + reg = <0x720000 0x20000>, + <0x704000 0x20000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 206 0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + qcom,clk-mgmt-sus-res; + qcom,bam-pipe-pair = <3>; + qcom,ce-hw-instance = <0>; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 393600 393600>; + clock-names = + "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = + <&clock_rpmcc QCEDEV_CE1_CLK>, + <&clock_rpmcc QCEDEV_CE1_CLK>, + <&clock_rpmcc QCEDEV_CE1_CLK>, + <&clock_rpmcc QCEDEV_CE1_CLK>; + qcom,smmu-s1-enable; + iommus = <&apps_smmu 0x0066 0x0011>, + <&apps_smmu 0x0076 0x0011>; + }; + + qcom_tzlog: tz-log@8600720 { + compatible = "qcom,tz-log"; + reg = <0x08600720 0x2000>; + }; + + thermal_zones: thermal-zones {}; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + rpm_sw_dump { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic_dump { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xe4>; + }; + + misc_data_dump { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + + vsense_dump { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xe9>; + }; + + tmc_etf_dump { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf0>; + }; + + tmc_etr_reg_dump { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + tmc_etf_reg_dump { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x101>; + }; + }; + + qcom_seecom: qseecom@85900000 { + compatible = "qcom,qseecom"; + reg = <0x85900000 0x500000>; + reg-names = "secapp-region"; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,fde-key-size; + qcom,no-clock-support; + qcom,appsbl-qseecom-support; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,ce-opp-freq = <171430000>; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_smcinvoke: smcinvoke@85900000 { + compatible = "qcom,smcinvoke"; + reg = <0x85900000 0x500000>; + reg-names = "secapp-region"; + }; + + qcom_rng: qrng@e3000 { + compatible = "qcom,msm-rng"; + reg = <0xe3000 0x1000>; + qcom,msm-rng-iface-clk; + qcom,no-qrng-config; + qcom,msm-bus,name = "msm-rng-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 618 0 0>, /* No vote */ + <1 618 0 800>; /* 100 MB/s */ + clocks = <&clock_gcc GCC_PRNG_AHB_CLK>; + clock-names = "iface_clk"; + }; + + sdcc1_ice: sdcc1ice@7808000 { + compatible = "qcom,ice"; + reg = <0x7808000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ice_core_clk_src", "ice_core_clk", + "bus_clk", "iface_clk"; + clocks = <&clock_gcc SDCC1_ICE_CORE_CLK_SRC>, + <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>, + <&clock_gcc GCC_SDCC1_AHB_CLK>, + <&clock_gcc GCC_SDCC1_APPS_CLK>; + qcom,op-freq-hz = <266666667>, <0>, <0>, <0>; + qcom,msm-bus,name = "sdcc_ice_noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 757 0 0>, /* No vote */ + <1 757 1000 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "sdcc"; + }; + + sdhc_1: sdhci@7804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x7804000 0x1000>, <0x7805000 0x1000>; + reg-names = "hc_mem", "cmdq_mem"; + + interrupts = <0 123 0>, <0 138 0>; + interrupt-names = "hc_irq", "pwr_irq"; + sdhc-msm-crypto = <&sdcc1_ice>; + + qcom,bus-width = <8>; + qcom,large-address-bus; + + qcom,pm-qos-irq-type = "affine_irq"; + qcom,pm-qos-irq-latency = <13 651>; + + qcom,pm-qos-cpu-groups = <0x0f>; + qcom,pm-qos-cmdq-latency-us = <13 651>; + + qcom,pm-qos-legacy-latency-us = <13 651>; + + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <9>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ + <78 512 1046 3200>, /* 400 KB/s*/ + <78 512 52286 160000>, /* 20 MB/s */ + <78 512 65360 200000>, /* 25 MB/s */ + <78 512 130718 400000>, /* 50 MB/s */ + <78 512 130718 400000>, /* 100 MB/s */ + <78 512 261438 800000>, /* 200 MB/s */ + <78 512 261438 800000>, /* 400 MB/s */ + <78 512 1338562 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 + 50000000 100000000 200000000 400000000 4294967295>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 + 192000000 384000000>; + qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; + + qcom,devfreq,freq-table = <50000000 200000000>; + + clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, + <&clock_gcc GCC_SDCC1_APPS_CLK>, + <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface_clk", "core_clk", "ice_core_clk"; + + qcom,ice-clk-rates = <266666667 160000000>; + + qcom,nonremovable; + + /* VDD external regulator is enabled/disabled by pms405_l6 */ + vdd-io-supply = <&pms405_l6>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on + &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off + &sdc1_rclk_off>; + + status = "ok"; + }; + + sdhc_2: sdhci@7844000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x7844000 0x1000>; + reg-names = "hc_mem"; + + interrupts = <0 125 0>, <0 221 0>; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <4>; + qcom,large-address-bus; + qcom,restore-after-cx-collapse; + + qcom,pm-qos-irq-type = "affine_irq"; + qcom,pm-qos-irq-latency = <13 651>; + + qcom,pm-qos-cpu-groups = <0x0f>; + qcom,pm-qos-legacy-latency-us = <13 651>; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */ + <81 512 1046 3200>, /* 400 KB/s*/ + <81 512 52286 160000>, /* 20 MB/s */ + <81 512 65360 200000>, /* 25 MB/s */ + <81 512 130718 400000>, /* 50 MB/s */ + <81 512 261438 800000>, /* 100 MB/s */ + <81 512 261438 800000>, /* 200 MB/s */ + <81 512 1338562 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100000000 200000000 4294967295>; + + qcom,clk-rates = <400000 20000000 25000000 + 50000000 100000000 200000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", + "SDR104"; + + qcom,devfreq,freq-table = <50000000 200000000>; + + clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>, + <&clock_gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface_clk", "core_clk"; + + qcom,nonhotplug; + + /* VDD is an external regulator eLDO5 */ + vdd-io-supply = <&pms405_l11>; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 24200>; + + qcom,core_3_0v_support; + qcom,nonremovable; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + /delete-property/ qcom,devfreq,freq-table; + /delete-property/ cd-gpios; + + status = "ok"; + }; + + qnand_1: nand@4c0000 { + compatible = "qcom,msm-nand"; + reg = <0x004c0000 0x1000>, + <0x004c4000 0x1a000>; + reg-names = "nand_phys", + "bam_phys"; + qcom,reg-adjustment-offset = <0x4000>; + + interrupts = <0 49 0>; + interrupt-names = "bam_irq"; + + qcom,msm-bus,name = "qpic_nand"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + + qcom,msm-bus,vectors-KBps = + <91 512 0 0>, + /* Voting for max b/w on PNOC bus for now */ + <91 512 400000 400000>; + + clock-names = "core_clk"; + clocks = <&clock_rpmcc RPM_SMD_QPIC_CLK>; + + status = "disabled"; + }; + + msm_cpufreq: qcom,msm-cpufreq { + compatible = "qcom,msm-cpufreq"; + clock-names = "cpu0_clk"; + clocks = <&clock_cpu APCS_MUX_CLK>; + + qcom,cpufreq-table = + < 1094400 >, + < 1248000 >, + < 1401600 >; + }; + + ddr_bw_opp_table: ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 297, 8); /* 2265 MB/s */ + BW_OPP_ENTRY( 595, 8); /* 4539 MB/s */ + BW_OPP_ENTRY( 710, 8); /* 5416 MB/s */ + }; + + cpubw: qcom,cpubw { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = <1 512>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + qcom,cpu-bwmon { + compatible = "qcom,bimc-bwmon2"; + reg = <0x408000 0x300>, <0x401000 0x200>; + reg-names = "base", "global_base"; + interrupts = <0 183 4>; + qcom,mport = <0>; + qcom,target-dev = <&cpubw>; + }; + + cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = <1 512>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_computemon: qcom,cpu0-computemon { + compatible = "qcom,arm-cpu-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1094400 MHZ_TO_MBPS( 297, 8) >, + < 1248000 MHZ_TO_MBPS( 597, 8) >, + < 1401600 MHZ_TO_MBPS( 710, 8) >; + }; + + emac_hw: qcom,emac@07A80000 { + compatible = "qcom,emac-dwc-eqos"; + reg = <0x07A80000 0x10000>, + <0x7A96000 0x100>; + reg-names = "emac-base", "rgmii-base"; + dma-bit-mask = <32>; + emac-core-version = <6>; + interrupts-extended = <&wakegic 0 56 4>, <&wakegic 0 55 4>, + <&tlmm 61 2>, <&wakegic 0 300 4>, + <&wakegic 0 301 4>, <&wakegic 0 302 4>, + <&wakegic 0 303 4>, <&wakegic 0 304 4>, + <&wakegic 0 305 4>, <&wakegic 0 306 4>, + <&wakegic 0 307 4>, <&wakegic 0 308 4>; + interrupt-names = "sbd-intr", "lpi-intr", + "phy-intr", "tx-ch0-intr", + "tx-ch1-intr", "tx-ch2-intr", + "tx-ch3-intr", "tx-ch4-intr", + "rx-ch0-intr", "rx-ch1-intr", + "rx-ch2-intr", "rx-ch3-intr"; + qcom,msm-bus,name = "emac"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <98 512 0 0>, <1 781 0 0>, /* No vote */ + <98 512 1250 0>, <1 781 0 40000>, /* 10Mbps vote */ + <98 512 12500 0>, <1 781 0 40000>, /* 100Mbps vote */ + <98 512 125000 0>, <1 781 0 40000>; /* 1000Mbps vote */ + qcom,bus-vector-names = "0", "10", "100", "1000"; + clocks = <&clock_gcc GCC_ETH_AXI_CLK>, + <&clock_gcc GCC_ETH_PTP_CLK>, + <&clock_gcc GCC_ETH_RGMII_CLK>, + <&clock_gcc GCC_ETH_SLAVE_AHB_CLK>; + clock-names = "eth_axi_clk", "eth_ptp_clk", + "eth_rgmii_clk", "eth_slave_ahb_clk"; + qcom,phy-reset = <&tlmm 60 GPIO_ACTIVE_HIGH>; + qcom,phy-intr-redirect = <&tlmm 61 GPIO_ACTIVE_LOW>; + /*gdsc_emac-supply = <&emac_gdsc>;*/ + pinctrl-names = "dev-emac-mdc", "dev-emac-mdio", + "dev-emac-rgmii_txd0_state", "dev-emac-rgmii_txd1_state", + "dev-emac-rgmii_txd2_state", "dev-emac-rgmii_txd3_state", + "dev-emac-rgmii_txc_state", "dev-emac-rgmii_tx_ctl_state", + "dev-emac-rgmii_rxd0_state", "dev-emac-rgmii_rxd1_state", + "dev-emac-rgmii_rxd2_state", "dev-emac-rgmii_rxd3_state", + "dev-emac-rgmii_rxc_state", "dev-emac-rgmii_rx_ctl_state", + "dev-emac-phy_intr"; + + pinctrl-0 = <&emac_mdc>; + pinctrl-1 = <&emac_mdio>; + pinctrl-2 = <&emac_rgmii_txd0>; + pinctrl-3 = <&emac_rgmii_txd1>; + pinctrl-4 = <&emac_rgmii_txd2>; + pinctrl-5 = <&emac_rgmii_txd3>; + pinctrl-6 = <&emac_rgmii_txc>; + pinctrl-7 = <&emac_rgmii_tx_ctl>; + pinctrl-8 = <&emac_rgmii_rxd0>; + pinctrl-9 = <&emac_rgmii_rxd1>; + pinctrl-10 = <&emac_rgmii_rxd2>; + pinctrl-11 = <&emac_rgmii_rxd3>; + pinctrl-12 = <&emac_rgmii_rxc>; + pinctrl-13 = <&emac_rgmii_rx_ctl>; + pinctrl-14 = <&emac_phy_intr>; + + io-macro-info { + io-macro-bypass-mode = <0>; + io-interface = "rgmii"; + }; + }; + + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-xtal-supply = <&pms405_l5>; + qca,bt-vdd-io-supply = <&pms405_l6>; + qca,bt-vdd-ldo-supply = <&pms405_l1>; + + qca,bt-vdd-xtal-voltage-level = <1800000 1900000>; + qca,bt-vdd-io-voltage-level = <1800000 1900000>; + qca,bt-vdd-ldo-voltage-level = <1300000 1350000>; + + qca,bt-vdd-xtal-current-level = <80000>; + qca,bt-vdd-io-current-level = <10000>; + qca,bt-vdd-ldo-current-level = <300000>; + }; + + qcom,icnss@18800000 { + compatible = "qcom,icnss"; + reg = <0x0A000000 0x800000>, + <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa"; + iommus = <&apps_smmu 0x400 0x1>; + interrupts = <0 277 0 /* CE0 */ >, + <0 278 0 /* CE1 */ >, + <0 279 0 /* CE2 */ >, + <0 280 0 /* CE3 */ >, + <0 281 0 /* CE4 */ >, + <0 282 0 /* CE5 */ >, + <0 283 0 /* CE6 */ >, + <0 284 0 /* CE7 */ >, + <0 285 0 /* CE8 */ >, + <0 286 0 /* CE9 */ >, + <0 287 0 /* CE10 */ >, + <0 288 0 /* CE11 */ >; + qcom,wlan-msa-memory = <0x100000>; + qcom,wlan-msa-fixed-region = <&wlan_msa_mem>; + vdd-cx-mx-supply = <&pms405_l2>; + vdd-1.8-xo-supply = <&pms405_l5>; + vdd-1.3-rfa-supply = <&pms405_l1>; + qcom,vdd-cx-mx-config = <1224000 1224000>; + qcom,smmu-s1-bypass; + qcom,hyp_disabled; + }; + + cnss_sdio: qcom,cnss_sdio { + compatible = "qcom,cnss_sdio"; + subsys-name = "AR6320"; + /** + * There is no vdd-wlan on board and this is not for DSRC. + * IO and XTAL share the same vreg. + **/ + vdd-wlan-io-supply = <&pms405_l5>; + qcom,cap-tsf-gpio = <&tlmm 42 1>; + qcom,wlan-ramdump-dynamic = <0x200000>; + qcom,msm-bus,name = "msm-cnss"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <79 512 0 0>, /* No vote */ + <79 512 6250 200000>, /* 50 Mbps */ + <79 512 25000 200000>, /* 200 Mbps */ + <79 512 2048000 4096000>; /* MAX */ + }; +}; + +#include "qcs405-gdsc.dtsi" +#include "pms405.dtsi" +#include "pms405-rpm-regulator.dtsi" +#include "qcs405-regulator.dtsi" +#include "qcs405-thermal.dtsi" +#include "qcs405-bus.dtsi" +#include "qcs405-audio.dtsi" + +&gdsc_mdss { + status = "ok"; +}; + +&gdsc_oxili_gx { + status = "ok"; +}; + +&blsp1_uart4_hs { + status = "ok"; +}; + +#include "qcs405-coresight.dtsi" +#include "qcs405-usb.dtsi" +#include "qcs405-pcie.dtsi" +#include "qcs405-mhi.dtsi" + +&i2c_5 { + smb1351_otg_supply: smb1351-charger@55 { + status = "disabled"; + compatible = "qcom,smb1351-charger"; + reg = <0x55>; + interrupt-parent = <&tlmm>; + interrupts = <107 IRQ_TYPE_LEVEL_LOW>; + qcom,float-voltage-mv = <4350>; + qcom,charging-timeout = <1536>; + qcom,recharge-thresh-mv = <200>; + qcom,iterm-ma = <100>; + regulator-name = "smb1351_otg_supply"; + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat>; + qcom,switch-freq = <2>; + dpdm-supply = <&usb2_phy0>; + qcom,otg-enable; + }; + + usb_typec: usb_typec@3d { + compatible = "nxp,5150a"; + reg = <0x3d>; + interrupt-parent = <&tlmm>; + interrupts = <35 IRQ_TYPE_LEVEL_LOW>; + pintctrl-names = "default"; + pinctrl-0 = <&nxp_i2c_intr>; + status = "disabled"; + }; +}; + +&pms405_gpios { + usb3_vbus_boost { + usb3_vbus_boost_default: usb3_vbus_boost_default { + pins = "gpio3"; + function = "normal"; + output-low; + power-source = <1>; + }; + }; + + usb3_vbus_det { + usb3_vbus_det_default: usb3_vbus_det_default { + pins = "gpio12"; + function = "normal"; + input-enable; + bias-pull-down; + power-source = <1>; + }; + }; +}; + +&soc { + usb3_extcon: usb3_extcon { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&tlmm 116 GPIO_ACTIVE_HIGH>; + vbus-gpio = <&pms405_gpios 12 GPIO_ACTIVE_HIGH>; + vbus-out-gpio = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&usb3_vbus_det_default + &usb3_id_det_default + &usb3_vbus_boost_default>; + }; +}; + +&usb3 { + extcon = <&usb3_extcon>; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + input-name = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&tlmm_gpio_key_active>; + + vol_mute { + label = "vol_mute"; + gpios = <&tlmm 21 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + debounce-interval = <15>; + gpio-key,wakeup; + linux,can-disable; + }; + + vol_down { + label = "vol_down"; + gpios = <&tlmm 54 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + debounce-interval = <15>; + gpio-key,wakeup; + linux,can-disable; + }; + + vol_up { + label = "vol_up"; + gpios = <&tlmm 52 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + debounce-interval = <15>; + gpio-key,wakeup; + linux,can-disable; + }; + + home { + label = "action"; + gpios = <&tlmm 115 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + debounce-interval = <15>; + gpio-key,wakeup; + linux,can-disable; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs410-iot-overlay.dts b/arch/arm/boot/dts/qcom/qcs410-iot-overlay.dts new file mode 100644 index 000000000000..327744a101c1 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs410-iot-overlay.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include "qcs410-iot.dtsi" + +/ { + model = "IOT"; + compatible = "qcom,qcs410-iot", "qcom,qcs410", "qcom,iot"; + qcom,msm-id = <406 0x0>; + qcom,board-id = <32 0>; +}; diff --git a/arch/arm/boot/dts/qcom/qcs410-iot.dts b/arch/arm/boot/dts/qcom/qcs410-iot.dts new file mode 100644 index 000000000000..bac1561fdc2a --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs410-iot.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "qcs410.dtsi" +#include "qcs410-iot.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS410 IOT"; + compatible = "qcom,qcs410-iot", "qcom,qcs410", "qcom,iot"; + qcom,board-id = <32 0>; +}; diff --git a/arch/arm/boot/dts/qcom/qcs410-iot.dtsi b/arch/arm/boot/dts/qcom/qcs410-iot.dtsi new file mode 100644 index 000000000000..20f1a5bdb466 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs410-iot.dtsi @@ -0,0 +1,165 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. QCS410 IOT"; + compatible = "qcom,qcs410-iot", "qcom,qcs410", "qcom,iot"; +}; + +&qupv3_se3_i2c { + status = "ok"; + #include "smb1390.dtsi" +}; + +&pm6150l_gpios { + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio2"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; + + irled { + irled_pwm: irled_pwm_default { + pins = "gpio6"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <0>; + bias-disable; + output-low; + }; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm6150l_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + linux,can-disable; + debounce-interval = <15>; + gpio-key,wakeup; + }; + }; + + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + #include "qg-batterydata-mlp356477-2800mah.dtsi" + }; +}; + +&pm6150l_wled { + qcom,string-cfg= <3>; + qcom,leds-per-string = <7>; + status = "ok"; +}; + +&pm6150l_lcdb { + status = "ok"; +}; + +&pm6150l_pwm_1 { + status = "okay"; +}; + +&pm6150_qg { + qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <100>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; +}; + +&pm6150_charger { + io-channels = <&pm6150_vadc ADC_USB_IN_V_16>, + <&pm6150_vadc ADC_USB_IN_I>, + <&pm6150_vadc ADC_CHG_TEMP>, + <&pm6150_vadc ADC_DIE_TEMP>, + <&pm6150_vadc ADC_AMUX_THM4_PU2>, + <&pm6150_vadc ADC_SBUx>, + <&pm6150_vadc ADC_VPH_PWR>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage"; + qcom,battery-data = <&mtp_batterydata>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,fcc-stepping-enable; + qcom,suspend-input-on-debug-batt; + qcom,sec-charger-config = <3>; + qcom,thermal-mitigation = <4200000 3500000 3000000 + 2500000 2000000 1500000 1000000 500000>; + dpdm-supply = <&qusb_phy0>; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; +}; + +&smb1390 { + /delete-property/ interrupts; + interrupts = <0x0 0xc2 0x0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1390_charger { + /delete-property/ compatible; + compatible = "qcom,smb1390-charger-psy"; + io-channels = <&pm6150_vadc ADC_AMUX_THM3>; + io-channel-names = "cp_die_temp"; + status = "ok"; +}; + +&pil_camera_mem { + reg = <0 0x8f800000 0 0x500000>; +}; + +&pil_modem_mem { + reg = <0 0x8fd00000 0 0x3100000>; +}; + +&L16A { + regulator-max-microvolt = <3304000>; +}; + +&L19A { + regulator-max-microvolt = <3304000>; +}; + +&L4C { + regulator-max-microvolt = <2912000>; +}; + +&L5C { + regulator-max-microvolt = <2912000>; +}; diff --git a/arch/arm/boot/dts/qcom/qcs410.dts b/arch/arm/boot/dts/qcom/qcs410.dts new file mode 100644 index 000000000000..e0b4e4685b83 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs410.dts @@ -0,0 +1,21 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "qcs410.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS410 SoC"; + compatible = "qcom,qcs410"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm/boot/dts/qcom/qcs410.dtsi b/arch/arm/boot/dts/qcom/qcs410.dtsi new file mode 100644 index 000000000000..0e9baa11f06b --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs410.dtsi @@ -0,0 +1,137 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm6150.dtsi" +#include "sm6150-pm.dtsi" +#include "sm6150-thermal-overlay.dtsi" +#include "sm6150-thermal.dtsi" +#include "sm6150-coresight.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS410 SoC"; + qcom,msm-name = "QCS410"; + qcom,msm-id = <406 0>; + + cpus { + /delete-node/ cpu@200; + /delete-node/ cpu@300; + /delete-node/ cpu@400; + /delete-node/ cpu@500; + + cpu-map { + cluster0 { + /delete-node/ core2; + /delete-node/ core3; + /delete-node/ core4; + /delete-node/ core5; + }; + }; + }; +}; + +&soc { + qcom,lpm-levels { + qcom,pm-cluster@0 { + qcom,pm-cpu@0 { + qcom,cpu = <&CPU0 &CPU1>; + }; + }; + }; + + dsu_pmu@0 { + cpus = <&CPU0>, <&CPU1>, <&CPU6>, <&CPU7>; + }; + + qcom,chd_silver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x18000058 0x18010058>; + qcom,config-arr = <0x18000060 0x18010060>; + }; + + /delete-node/ cti@7220000; + /delete-node/ cti@7320000; + /delete-node/ cti@7420000; + /delete-node/ cti@7520000; + /delete-node/ etm@7240000; + /delete-node/ etm@7340000; + /delete-node/ etm@7440000; + /delete-node/ etm@7540000; + cpuss_dump { + /delete-node/ qcom,l1_i_cache200; + /delete-node/ qcom,l1_i_cache300; + /delete-node/ qcom,l1_i_cache400; + /delete-node/ qcom,l1_i_cache500; + /delete-node/ qcom,l1_d_cache200; + /delete-node/ qcom,l1_d_cache300; + /delete-node/ qcom,l1_d_cache400; + /delete-node/ qcom,l1_d_cache500; + /delete-node/ qcom,l2_tlb_dump200; + /delete-node/ qcom,l2_tlb_dump300; + /delete-node/ qcom,l2_tlb_dump400; + /delete-node/ qcom,l2_tlb_dump500; + }; + + qcom,cpu0-cpu-l3-latmon { + qcom,cpulist = <&CPU0 &CPU1>; + }; + + qcom,cpu0-cpu-llcc-latmon { + qcom,cpulist = <&CPU0 &CPU1>; + }; + + qcom,cpu0-llcc-ddr-latmon { + qcom,cpulist = <&CPU0 &CPU1>; + }; + + qcom,cpu0-computemon { + qcom,cpulist = <&CPU0 &CPU1>; + }; + + funnel@7800000 { + ports { + /delete-node/ port@3; + /delete-node/ port@4; + /delete-node/ port@5; + /delete-node/ port@6; + }; + }; +}; + +&thermal_zones { + pm6150l-tz { + cooling-maps { + /delete-node/ trip0_cpu2; + /delete-node/ trip0_cpu3; + /delete-node/ trip0_cpu4; + /delete-node/ trip0_cpu5; + /delete-node/ trip1_cpu2; + /delete-node/ trip1_cpu3; + /delete-node/ trip1_cpu4; + /delete-node/ trip1_cpu5; + }; + }; + cpuss-0-step { + /delete-node/ cooling-maps; + }; + cpuss-1-step { + /delete-node/ cooling-maps; + }; + quiet-therm-step { + cooling-maps { + /delete-node/ skin_cpu2; + /delete-node/ skin_cpu3; + /delete-node/ skin_cpu4; + /delete-node/ skin_cpu5; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs610-camera-sensor-idp.dtsi b/arch/arm/boot/dts/qcom/qcs610-camera-sensor-idp.dtsi new file mode 100644 index 000000000000..7c915a6b72e9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs610-camera-sensor-idp.dtsi @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + ir_led: camera-ir-led@0 { + cell-index = <0>; + reg = <0x00>; + compatible = "qcom,camera-ir-led"; + pwms = <&pm6150l_pwm_1 0 0>; + enable-active-high; + pinctrl-names = "default", "cam_default", "cam_suspend"; + pinctrl-0 = <&irled_pwm>; + pinctrl-1 = <&cam_sensor_ir_cut_on>; + pinctrl-2 = <&cam_sensor_ir_cut_off>; + gpios = <&tlmm 73 0>, + <&tlmm 74 0>; + qcom,gpio-ir-p = <0>; + qcom,gpio-ir-m = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <0 0>; + qcom,gpio-req-tbl-label = "IR_CUT_FILTER_P", + "IR_CUT_FILTER_M"; + gpio-no-mux = <0>; + status = "ok"; + }; + + camera_ldo: gpio-regulator@0 { + compatible = "regulator-fixed"; + reg = <0x00 0x00>; + regulator-name = "camera_ldo"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&pm6150l_gpios 3 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_sensor_dvdd_en>; + vin-supply = <&pm6150l_s8>; + }; +}; + +&cam_cci { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&pm6150_l13>; + cam_vana-supply = <&pm6150l_l4>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + ir-led-src = <&ir_led>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2850000 1200000 0>; + rgltr-max-voltage = <1800000 2850000 1200000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 28 0>, + <&tlmm 47 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <37125000>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs610-iot-overlay.dts b/arch/arm/boot/dts/qcom/qcs610-iot-overlay.dts new file mode 100644 index 000000000000..0c740154ee48 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs610-iot-overlay.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include + +#include "qcs610-iot.dtsi" + +/ { + model = "IOT"; + compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot"; + qcom,msm-id = <401 0x0>; + qcom,board-id = <32 0>; +}; diff --git a/arch/arm/boot/dts/qcom/qcs610-iot.dts b/arch/arm/boot/dts/qcom/qcs610-iot.dts new file mode 100644 index 000000000000..76fd007b5f56 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs610-iot.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "qcs610-iot.dtsi" +#include "sm6150-audio-overlay.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS610 IOT"; + compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot"; + qcom,board-id = <32 0>; +}; + +&sm6150_snd { + /delete-property/ fsa4480-i2c-handle; +}; diff --git a/arch/arm/boot/dts/qcom/qcs610-iot.dtsi b/arch/arm/boot/dts/qcom/qcs610-iot.dtsi new file mode 100644 index 000000000000..16a4bca74ffa --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs610-iot.dtsi @@ -0,0 +1,447 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include "qcs610.dtsi" +#include "sm6150-sde.dtsi" +#include "sm6150-sde-pll.dtsi" +#include "sm6150-sde-display.dtsi" +#include "qcs610-camera-sensor-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS610 IOT"; + compatible = "qcom,qcs610-iot", "qcom,qcs610", "qcom,iot"; + qcom,board-id = <32 0>; +}; + +&qupv3_se3_i2c { + status = "ok"; + #include "smb1390.dtsi" +}; + +&fsa4480 { + status = "disabled"; +}; + +&pm6150l_gpios { + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio2"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; + + irled { + irled_pwm: irled_pwm_default { + pins = "gpio6"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <0>; + bias-disable; + output-low; + }; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm6150l_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + linux,can-disable; + debounce-interval = <15>; + gpio-key,wakeup; + }; + }; + + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + #include "qg-batterydata-mlp356477-2800mah.dtsi" + }; + + emac_hw: qcom,emac@20000 { + compatible = "qcom,emac-dwc-eqos"; + qcom,arm-smmu; + reg = <0x20000 0x10000>, + <0x36000 0x100>; + reg-names = "emac-base", "rgmii-base"; + dma-bit-mask = <32>; + emac-core-version = <7>; + interrupts-extended = <&pdc 0 660 4>, <&pdc 0 661 4>, + <&tlmm 76 2>, <&pdc 0 651 4>, + <&pdc 0 652 4>, <&pdc 0 653 4>, + <&pdc 0 654 4>, <&pdc 0 655 4>, + <&pdc 0 656 4>, <&pdc 0 657 4>, + <&pdc 0 658 4>, <&pdc 0 659 4>, + <&pdc 0 668 4>, <&pdc 0 669 4>; + interrupt-names = "sbd-intr", "lpi-intr", + "phy-intr", "tx-ch0-intr", + "tx-ch1-intr", "tx-ch2-intr", + "tx-ch3-intr", "tx-ch4-intr", + "rx-ch0-intr", "rx-ch1-intr", + "rx-ch2-intr", "rx-ch3-intr", + "ptp_pps_irq_0","ptp_pps_irq_1"; + qcom,msm-bus,name = "emac"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <98 512 0 0>, <1 781 0 0>, /* No vote */ + <98 512 1250 0>, <1 781 0 40000>, /* 10Mbps vote */ + <98 512 12500 0>, <1 781 0 40000>, /* 100Mbps vote */ + <98 512 125000 0>, <1 781 0 40000>; /* 1000Mbps vote */ + qcom,bus-vector-names = "0", "10", "100", "1000"; + clocks = <&clock_gcc GCC_EMAC_AXI_CLK>, + <&clock_gcc GCC_EMAC_PTP_CLK>, + <&clock_gcc GCC_EMAC_RGMII_CLK>, + <&clock_gcc GCC_EMAC_SLV_AHB_CLK>; + clock-names = "eth_axi_clk", "eth_ptp_clk", + "eth_rgmii_clk", "eth_slave_ahb_clk"; + qcom,phy-reset = <&tlmm 36 GPIO_ACTIVE_HIGH>; + qcom,phy-intr-redirect = <&tlmm 76 GPIO_ACTIVE_LOW>; + gdsc_emac-supply = <&emac_gdsc>; + pinctrl-names = "dev-emac-mdc", "dev-emac-mdio", + "dev-emac-rgmii_txd0_state", "dev-emac-rgmii_txd1_state", + "dev-emac-rgmii_txd2_state", "dev-emac-rgmii_txd3_state", + "dev-emac-rgmii_txc_state", "dev-emac-rgmii_tx_ctl_state", + "dev-emac-rgmii_rxd0_state", "dev-emac-rgmii_rxd1_state", + "dev-emac-rgmii_rxd2_state", "dev-emac-rgmii_rxd3_state", + "dev-emac-rgmii_rxc_state", "dev-emac-rgmii_rx_ctl_state", + "dev-emac-phy_intr", "dev-emac-phy_reset_state", + "dev-emac_pin_pps_0"; + + pinctrl-0 = <&emac_mdc>; + pinctrl-1 = <&emac_mdio>; + pinctrl-2 = <&emac_rgmii_txd0>; + pinctrl-3 = <&emac_rgmii_txd1>; + pinctrl-4 = <&emac_rgmii_txd2>; + pinctrl-5 = <&emac_rgmii_txd3>; + pinctrl-6 = <&emac_rgmii_txc>; + pinctrl-7 = <&emac_rgmii_tx_ctl>; + pinctrl-8 = <&emac_rgmii_rxd0>; + pinctrl-9 = <&emac_rgmii_rxd1>; + pinctrl-10 = <&emac_rgmii_rxd2>; + pinctrl-11 = <&emac_rgmii_rxd3>; + pinctrl-12 = <&emac_rgmii_rxc>; + pinctrl-13 = <&emac_rgmii_rx_ctl>; + pinctrl-14 = <&emac_phy_intr>; + pinctrl-15 = <&emac_phy_reset_state>; + pinctrl-16 = <&emac_pin_pps_0>; + vreg_emac_phy-supply = <&L19A>; + qcom,phyad_change; + + io-macro-info { + io-macro-bypass-mode = <0>; + io-interface = "rgmii"; + }; + emac_emb_smmu: emac_emb_smmu { + compatible = "qcom,emac-smmu-embedded"; + iommus = <&apps_smmu 0x1C0 0x0>; + qcom,iova-mapping = <0x80000000 0x40000000>; + }; + }; + +}; + +&emac_phy_intr { + mux { + pins = "gpio76"; + function = "gpio"; + }; + + config { + pins = "gpio76"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + +&emac_phy_reset_state { + mux { + pins = "gpio36"; + function = "gpio"; + }; + + config { + pins = "gpio36"; + bias-pull-up; + drive-strength = <16>; + }; + }; + +&pm6150l_wled { + qcom,string-cfg= <3>; + qcom,leds-per-string = <7>; + status = "ok"; +}; + +&pm6150l_lcdb { + status = "ok"; +}; + +&pm6150l_pwm_1 { + status = "okay"; +}; + +&pm6150_qg { + qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <100>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; +}; + +&pm6150_charger { + io-channels = <&pm6150_vadc ADC_USB_IN_V_16>, + <&pm6150_vadc ADC_USB_IN_I>, + <&pm6150_vadc ADC_CHG_TEMP>, + <&pm6150_vadc ADC_DIE_TEMP>, + <&pm6150_vadc ADC_AMUX_THM4_PU2>, + <&pm6150_vadc ADC_SBUx>, + <&pm6150_vadc ADC_VPH_PWR>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage"; + qcom,battery-data = <&mtp_batterydata>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,fcc-stepping-enable; + qcom,suspend-input-on-debug-batt; + qcom,sec-charger-config = <3>; + qcom,thermal-mitigation = <4200000 3500000 3000000 + 2500000 2000000 1500000 1000000 500000>; + dpdm-supply = <&qusb_phy0>; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; +}; + +&smb1390 { + /delete-property/ interrupts; + interrupts = <0x0 0xc2 0x0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1390_charger { + /delete-property/ compatible; + compatible = "qcom,smb1390-charger-psy"; + io-channels = <&pm6150_vadc ADC_AMUX_THM3>; + io-channel-names = "cp_die_temp"; + status = "ok"; +}; + +&qupv3_se0_2uart { + status = "ok"; +}; + +&qupv3_se7_4uart { + status = "ok"; +}; + +&pil_camera_mem { + reg = <0 0x8f800000 0 0x500000>; +}; + +&pil_modem_mem { + reg = <0 0x8fd00000 0 0x3100000>; +}; + +&sdhc_1 { + vdd-supply = <&pm6150l_l11>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&pm6150_l12>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm6150l_l9>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&pm6150l_l6>; + qcom,vdd-io-voltage-level = <1800000 3100000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; + +&L16A { + regulator-max-microvolt = <3304000>; +}; + +&L19A { + regulator-max-microvolt = <3304000>; +}; + +&L4C { + regulator-max-microvolt = <2912000>; +}; + +&L5C { + regulator-max-microvolt = <2912000>; +}; + +&sde_dp { + status="disabled"; +}; + +&mdss_dp_pll { + status="disabled"; +}; + +&mdss_mdp { + connectors = <&sde_rscc &sde_wb &sde_dsi>; +}; + +&qupv3_se1_i2c { + status = "ok"; + lt9611: lt,lt9611@3b { + compatible = "lt,lt9611"; + reg = <0x3b>; + interrupt-parent = <&tlmm>; + interrupts = <26 0>; + interrupt-names = "lt_irq"; + lt,irq-gpio = <&tlmm 26 0x0>; + lt,reset-gpio = <&tlmm 20 0x0>; + lt,hdmi-en-gpio = <&tlmm 79 0x0>; + instance_id = <0>; + lt,non-pluggable; + lt,preferred-mode = "1920x1080"; + + pinctrl-names = "default"; + pinctrl-0 = <<9611_pins>; + + vdd-supply = <&pm6150_l13>; + vcc-supply = <&pm6150_l16>; + + lt,supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + lt,supply-entry@0 { + reg = <0>; + lt,supply-name = "vcc"; + lt,supply-min-voltage = <3304000>; + lt,supply-max-voltage = <3304000>; + lt,supply-enable-load = <200000>; + lt,supply-post-on-sleep = <50>; + }; + + lt,supply-entry@1 { + reg = <1>; + lt,supply-name = "vdd"; + lt,supply-min-voltage = <1800000>; + lt,supply-max-voltage = <1800000>; + lt,supply-enable-load = <200000>; + lt,supply-post-on-sleep = <50>; + }; + }; + + lt,customize-modes { + lt,customize-mode-id@0 { + lt,mode-h-active = <1920>; + lt,mode-h-front-porch = <88>; + lt,mode-h-pulse-width = <44>; + lt,mode-h-back-porch = <148>; + lt,mode-h-active-high; + lt,mode-v-active = <1080>; + lt,mode-v-front-porch = <4>; + lt,mode-v-pulse-width = <5>; + lt,mode-v-back-porch = <36>; + lt,mode-v-active-high; + lt,mode-refresh-rate = <60>; + lt,mode-clock-in-khz = <148500>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lt9611_in: endpoint { + remote-endpoint = <&ext_dsi_out>; + }; + }; + }; + }; +}; + +&dsi_ext_bridge_hdmi_1080p { + qcom,mdss-dsi-ext-bridge = <0>; +}; + +&soc { + ext_dsi_bridge_display: qcom,dsi-display@50 { + label = "ext_dsi_bridge_display hdmi 1080p"; + qcom,dsi-display-active; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-panel = <&dsi_ext_bridge_hdmi_1080p>; + }; +}; + +&sde_dsi { + qcom,dsi-display-list = <&ext_dsi_bridge_display>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ext_dsi_out: endpoint { + remote-endpoint = <<9611_in>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcs610.dts b/arch/arm/boot/dts/qcom/qcs610.dts new file mode 100644 index 000000000000..d8706428c5e4 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs610.dts @@ -0,0 +1,21 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "qcs610.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS610 SoC"; + compatible = "qcom,qcs610"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm/boot/dts/qcom/qcs610.dtsi b/arch/arm/boot/dts/qcom/qcs610.dtsi new file mode 100644 index 000000000000..dfdbba966d75 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcs610.dtsi @@ -0,0 +1,29 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm6150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS610"; + qcom,msm-name = "QCS610"; + qcom,msm-id = <401 0>; +}; + +&soc { + qcom,rmnet-ipa { + status="disabled"; + }; +}; + +&ipa_hw { + status="disabled"; +}; diff --git a/arch/arm/boot/dts/qcom/qg-batterydata-alium-3600mah.dtsi b/arch/arm/boot/dts/qcom/qg-batterydata-alium-3600mah.dtsi new file mode 100644 index 000000000000..7c18fc182bdc --- /dev/null +++ b/arch/arm/boot/dts/qcom/qg-batterydata-alium-3600mah.dtsi @@ -0,0 +1,1048 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,alium_860_89032_0000_3600mAh { + /* Alium_860_89032_0000_3600mAh_averaged_MasterSlave_Jun15th2018 */ + qcom,max-voltage-uv = <4350000>; + qcom,fg-cc-cv-threshold-uv = <4340000>; + qcom,fastchg-current-ma = <5400>; + qcom,batt-id-kohm = <107>; + qcom,battery-beta = <4250>; + qcom,battery-therm-kohm = <100>; + qcom,battery-type = "Alium_860_89032_0000_3600mAh_Jun15th2018"; + qcom,qg-batt-profile-ver = <100>; + + qcom,jeita-fcc-ranges = <0 50 2500000 + 51 400 5400000 + 401 450 2500000>; + qcom,jeita-fv-ranges = <0 50 4250000 + 51 400 4350000 + 401 450 4250000>; + qcom,step-chg-ranges = <3600000 3800000 5400000 + 3801000 4300000 3600000 + 4301000 4350000 2500000>; + qcom,ocv-based-step-chg; + + /* COOL = 5 DegC, WARM = 40 DegC */ + qcom,jeita-soft-thresholds = <0x5314 0x25e3>; + /* COLD = 0 DegC, HOT = 45 DegC */ + qcom,jeita-hard-thresholds = <0x58cd 0x20b8>; + /* COOL hys = 8 DegC, WARM hys = 37 DegC */ + qcom,jeita-soft-hys-thresholds = <0x4f5e 0x2943>; + qcom,jeita-soft-fcc-ua = <2500000 2500000>; + qcom,jeita-soft-fv-uv = <4250000 4250000>; + + qcom,fcc1-temp-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-data = <3426 3519 3581 3613 3630>; + }; + + qcom,fcc2-temp-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-data = <3546 3576 3586 3588 3583 3583>; + }; + + qcom,pc-temp-v1-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <43078 43267 43365 43394 43399>, + <42839 43052 43147 43186 43196>, + <42609 42823 42920 42964 42981>, + <42392 42591 42693 42738 42759>, + <42186 42370 42469 42513 42535>, + <41983 42159 42248 42289 42310>, + <41776 41953 42032 42066 42085>, + <41565 41745 41820 41847 41863>, + <41376 41534 41607 41630 41645>, + <41226 41338 41393 41412 41426>, + <41086 41189 41206 41205 41212>, + <40873 41057 41063 41032 41014>, + <40523 40858 40918 40878 40833>, + <40155 40509 40680 40678 40639>, + <39917 40145 40325 40390 40407>, + <39757 39925 40039 40116 40180>, + <39638 39781 39894 39960 40010>, + <39541 39669 39779 39850 39877>, + <39455 39579 39646 39699 39715>, + <39364 39489 39487 39469 39489>, + <39266 39366 39306 39235 39257>, + <39165 39210 39096 39058 39072>, + <39060 39042 38900 38912 38919>, + <38955 38854 38767 38784 38785>, + <38859 38675 38671 38668 38668>, + <38773 38551 38581 38562 38562>, + <38692 38462 38490 38466 38462>, + <38619 38394 38403 38377 38369>, + <38552 38343 38327 38296 38283>, + <38491 38301 38257 38222 38203>, + <38439 38261 38195 38156 38132>, + <38392 38224 38142 38097 38067>, + <38348 38190 38095 38043 38010>, + <38306 38161 38052 37989 37952>, + <38265 38135 38015 37938 37895>, + <38223 38102 37976 37886 37836>, + <38181 38066 37935 37830 37771>, + <38128 38020 37890 37771 37701>, + <38054 37950 37823 37699 37623>, + <37964 37850 37727 37613 37538>, + <37862 37740 37617 37512 37439>, + <37739 37617 37494 37390 37318>, + <37601 37487 37361 37256 37185>, + <37448 37354 37221 37119 37052>, + <37327 37238 37120 37019 36955>, + <37241 37161 37057 36960 36898>, + <37209 37134 37035 36943 36881>, + <37182 37113 37018 36927 36865>, + <37146 37086 36991 36896 36829>, + <37036 36976 36855 36724 36634>, + <36712 36636 36510 36372 36278>, + <36253 36181 36056 35916 35819>, + <35673 35600 35476 35330 35231>, + <34889 34811 34685 34533 34429>, + <33644 33573 33450 33289 33175>, + <30000 30000 30000 30000 30000>; + }; + + qcom,pc-temp-v2-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <43405 43390 43380 43360 43310 43280>, + <43003 43066 43092 43094 43055 43033>, + <42659 42770 42823 42839 42808 42792>, + <42388 42505 42573 42597 42570 42556>, + <42183 42269 42342 42369 42341 42328>, + <41972 42046 42121 42146 42116 42104>, + <41647 41828 41907 41928 41893 41879>, + <41314 41618 41700 41715 41674 41657>, + <41242 41409 41488 41499 41455 41438>, + <41295 41194 41265 41273 41232 41219>, + <41338 41020 41073 41079 41031 41013>, + <41030 40918 40949 40949 40883 40839>, + <40301 40831 40837 40833 40747 40674>, + <39816 40619 40617 40621 40542 40474>, + <39553 40056 40158 40222 40214 40226>, + <39352 39574 39750 39893 39934 39999>, + <39187 39400 39544 39757 39792 39836>, + <39047 39287 39391 39659 39684 39694>, + <38903 39154 39240 39507 39524 39512>, + <38748 38998 39093 39269 39281 39271>, + <38600 38840 38951 39039 39045 39043>, + <38473 38688 38809 38867 38872 38870>, + <38360 38541 38673 38723 38728 38725>, + <38269 38408 38551 38598 38603 38600>, + <38195 38289 38441 38488 38492 38488>, + <38132 38186 38339 38387 38390 38385>, + <38076 38102 38245 38293 38296 38290>, + <38026 38033 38158 38206 38208 38200>, + <37976 37977 38077 38128 38127 38118>, + <37929 37931 38001 38058 38053 38043>, + <37882 37891 37932 37991 37985 37974>, + <37835 37852 37869 37926 37922 37912>, + <37786 37815 37814 37863 37863 37853>, + <37734 37776 37764 37798 37793 37778>, + <37680 37735 37722 37732 37704 37675>, + <37621 37692 37680 37666 37610 37565>, + <37558 37641 37633 37602 37526 37469>, + <37492 37582 37583 37538 37448 37384>, + <37421 37513 37524 37470 37374 37308>, + <37348 37429 37450 37396 37302 37235>, + <37274 37332 37362 37312 37222 37156>, + <37201 37229 37261 37208 37121 37056>, + <37130 37124 37145 37082 36997 36933>, + <37054 37029 37028 36964 36881 36820>, + <36966 36949 36952 36902 36830 36771>, + <36849 36873 36903 36875 36801 36743>, + <36768 36823 36880 36854 36784 36726>, + <36666 36763 36850 36823 36756 36699>, + <36509 36668 36775 36740 36671 36604>, + <36284 36467 36557 36486 36422 36338>, + <35954 36107 36161 36071 36005 35919>, + <35477 35597 35626 35539 35482 35397>, + <34808 34917 34941 34844 34796 34717>, + <33818 33942 34003 33928 33918 33830>, + <32458 32548 32795 32808 32663 32496>, + <28619 28270 28017 28020 27984 27930>; + }; + + qcom,pc-temp-z1-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <14545 13238 12041 11680 11593>, + <14523 13183 12045 11678 11602>, + <14531 13174 12043 11685 11612>, + <14535 13182 12039 11687 11616>, + <14547 13186 12035 11688 11618>, + <14571 13181 12033 11688 11620>, + <14591 13164 12034 11689 11623>, + <14582 13150 12035 11692 11626>, + <14551 13149 12037 11694 11629>, + <14518 13154 12041 11697 11631>, + <14486 13152 12045 11701 11634>, + <14452 13134 12047 11704 11639>, + <14403 13116 12047 11707 11643>, + <14352 13102 12043 11707 11644>, + <14318 13096 12036 11705 11644>, + <14291 13097 12033 11703 11644>, + <14262 13097 12036 11707 11647>, + <14226 13100 12042 11714 11653>, + <14194 13111 12052 11721 11659>, + <14181 13129 12065 11726 11663>, + <14179 13150 12076 11731 11667>, + <14186 13172 12085 11736 11672>, + <14195 13188 12093 11741 11676>, + <14207 13195 12101 11745 11681>, + <14215 13201 12109 11751 11686>, + <14220 13210 12116 11756 11690>, + <14223 13222 12123 11760 11695>, + <14228 13229 12130 11764 11699>, + <14239 13234 12137 11768 11703>, + <14255 13242 12143 11772 11707>, + <14279 13250 12149 11776 11711>, + <14302 13257 12154 11780 11716>, + <14310 13265 12160 11784 11720>, + <14314 13278 12166 11789 11725>, + <14320 13297 12174 11794 11729>, + <14343 13315 12181 11799 11733>, + <14395 13333 12189 11802 11736>, + <14443 13346 12197 11804 11738>, + <14481 13351 12202 11807 11740>, + <14512 13353 12205 11809 11741>, + <14514 13357 12209 11811 11742>, + <14472 13369 12217 11813 11744>, + <14451 13384 12223 11815 11745>, + <14446 13399 12224 11816 11746>, + <14433 13385 12228 11817 11746>, + <14447 13396 12231 11819 11746>, + <14441 13396 12232 11819 11745>, + <14440 13403 12233 11819 11746>, + <14431 13399 12239 11820 11747>, + <14460 13394 12241 11824 11750>, + <14470 13423 12251 11830 11755>, + <14506 13430 12275 11839 11760>, + <14485 13470 12295 11850 11770>, + <14544 13512 12338 11868 11782>, + <14544 13512 12338 11868 11782>, + <14544 13512 12338 11868 11782>; + }; + + qcom,pc-temp-z2-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <11192 9778 10257 10603 10910>, + <10253 10813 10276 10490 10558>, + <9726 10534 10287 10428 10436>, + <9734 10061 10282 10413 10412>, + <9760 9938 10269 10392 10406>, + <9775 9923 10261 10380 10404>, + <9777 9909 10257 10375 10408>, + <9772 9898 10258 10370 10412>, + <9765 9890 10262 10368 10412>, + <9755 9884 10265 10372 10421>, + <9746 9880 10259 10375 10444>, + <9750 9878 10227 10382 10452>, + <9766 9881 10199 10414 10451>, + <9772 9895 10216 10429 10452>, + <9752 9907 10260 10399 10450>, + <9717 9910 10282 10371 10439>, + <9701 9914 10279 10383 10449>, + <9697 9923 10269 10418 10506>, + <9693 9949 10295 10465 10551>, + <9686 9981 10388 10545 10559>, + <9673 10014 10446 10602 10559>, + <9662 10050 10419 10553 10531>, + <9655 10080 10371 10429 10478>, + <9649 10101 10339 10379 10444>, + <9631 10116 10316 10398 10420>, + <9588 10124 10303 10422 10405>, + <9554 10131 10300 10409 10406>, + <9540 10135 10301 10384 10415>, + <9483 10134 10309 10376 10426>, + <9426 10131 10329 10376 10445>, + <9408 10130 10351 10380 10472>, + <9395 10131 10373 10399 10506>, + <9386 10133 10396 10437 10548>, + <9378 10137 10420 10474 10594>, + <9372 10146 10446 10506 10651>, + <9368 10154 10463 10533 10695>, + <9374 10162 10468 10556 10712>, + <9380 10167 10471 10580 10722>, + <9389 10171 10479 10593 10733>, + <9398 10176 10491 10596 10745>, + <9397 10178 10497 10597 10753>, + <9384 10169 10490 10609 10755>, + <9380 10140 10483 10625 10759>, + <9386 9964 10481 10631 10781>, + <9324 9926 10454 10642 10811>, + <9305 9932 10438 10669 10808>, + <9287 9948 10463 10697 10858>, + <9289 9933 10557 10698 10889>, + <9274 9965 10622 10758 10917>, + <9278 9923 10533 10711 10837>, + <9316 9884 10462 10634 10693>, + <9326 9807 10425 10609 10671>, + <9285 9724 10395 10535 10591>, + <9245 9615 10285 10458 10500>, + <9245 9615 10285 10458 10500>, + <9245 9615 10285 10458 10500>; + }; + + qcom,pc-temp-z3-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <19525 19431 19373 19383 19355>, + <19784 19494 19408 19370 19350>, + <19920 19574 19438 19372 19351>, + <19937 19651 19450 19380 19356>, + <19918 19673 19455 19382 19359>, + <19895 19676 19456 19383 19362>, + <19884 19677 19454 19381 19362>, + <19879 19677 19451 19376 19359>, + <19877 19680 19448 19372 19355>, + <19874 19682 19446 19372 19353>, + <19872 19668 19440 19372 19352>, + <19877 19628 19423 19367 19352>, + <19894 19610 19400 19355 19349>, + <19909 19638 19406 19350 19345>, + <19892 19671 19439 19363 19347>, + <19843 19665 19457 19379 19351>, + <19796 19628 19436 19373 19348>, + <19760 19594 19408 19356 19338>, + <19726 19567 19407 19352 19335>, + <19697 19550 19425 19366 19342>, + <19672 19554 19438 19379 19351>, + <19654 19573 19439 19379 19357>, + <19644 19591 19439 19374 19361>, + <19636 19603 19437 19373 19362>, + <19628 19612 19434 19380 19360>, + <19619 19613 19433 19386 19358>, + <19607 19611 19439 19383 19356>, + <19596 19607 19445 19378 19354>, + <19583 19601 19446 19374 19352>, + <19567 19594 19444 19369 19350>, + <19549 19588 19442 19365 19348>, + <19530 19583 19439 19362 19345>, + <19514 19578 19434 19360 19342>, + <19499 19571 19431 19359 19338>, + <19486 19563 19429 19358 19334>, + <19479 19557 19426 19358 19332>, + <19483 19551 19422 19358 19332>, + <19491 19546 19418 19357 19334>, + <19513 19542 19415 19356 19334>, + <19535 19539 19414 19351 19331>, + <19526 19535 19412 19347 19329>, + <19496 19530 19410 19347 19330>, + <19483 19519 19408 19347 19330>, + <19481 19451 19404 19347 19331>, + <19372 19379 19382 19344 19327>, + <19345 19348 19360 19337 19320>, + <19337 19340 19358 19328 19312>, + <19339 19335 19342 19326 19312>, + <19316 19318 19331 19324 19309>, + <19320 19317 19352 19335 19324>, + <19371 19345 19355 19339 19331>, + <19418 19350 19357 19342 19332>, + <19442 19348 19353 19346 19335>, + <19464 19360 19359 19349 19340>, + <19464 19360 19359 19349 19340>, + <19464 19360 19359 19349 19340>; + }; + + qcom,pc-temp-z4-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <16385 15501 14962 14712 14715>, + <16621 15491 14959 14790 14777>, + <16602 15456 14922 14802 14786>, + <16518 15370 14881 14784 14773>, + <16384 15265 14843 14759 14750>, + <16241 15178 14812 14736 14726>, + <16119 15106 14786 14721 14710>, + <16009 15051 14764 14710 14700>, + <15894 15008 14752 14704 14694>, + <15746 14969 14746 14701 14689>, + <15604 14928 14744 14698 14685>, + <15557 14895 14744 14693 14681>, + <15579 14889 14745 14687 14673>, + <15600 14901 14749 14689 14670>, + <15554 14908 14754 14704 14683>, + <15436 14889 14752 14715 14696>, + <15339 14846 14732 14699 14686>, + <15282 14813 14713 14669 14663>, + <15245 14793 14712 14671 14662>, + <15230 14781 14722 14728 14708>, + <15221 14780 14742 14778 14758>, + <15217 14783 14794 14782 14763>, + <15221 14793 14846 14777 14751>, + <15227 14842 14846 14766 14737>, + <15232 14904 14815 14739 14722>, + <15237 14918 14783 14717 14709>, + <15244 14915 14759 14707 14700>, + <15250 14910 14740 14702 14693>, + <15262 14895 14729 14697 14687>, + <15275 14872 14722 14693 14682>, + <15283 14853 14717 14690 14677>, + <15290 14837 14715 14686 14673>, + <15294 14821 14714 14682 14670>, + <15292 14806 14713 14682 14669>, + <15285 14792 14713 14684 14672>, + <15265 14778 14712 14686 14677>, + <15218 14764 14710 14689 14683>, + <15171 14753 14707 14691 14689>, + <15100 14750 14704 14691 14691>, + <15036 14748 14701 14691 14688>, + <15028 14745 14698 14690 14685>, + <15035 14740 14695 14688 14684>, + <15033 14741 14690 14685 14683>, + <15011 14800 14682 14681 14680>, + <15037 14827 14679 14667 14668>, + <15046 14838 14675 14645 14644>, + <15051 14840 14669 14641 14637>, + <15043 14842 14681 14633 14624>, + <15056 14851 14689 14629 14622>, + <15040 14847 14670 14638 14636>, + <15003 14839 14678 14645 14640>, + <14990 14846 14681 14646 14645>, + <14996 14862 14691 14647 14646>, + <15017 14877 14695 14650 14646>, + <15017 14877 14695 14650 14646>, + <15017 14877 14695 14650 14646>; + }; + + qcom,pc-temp-z5-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <11068 11690 13464 19085 17868>, + <12016 12370 14843 18209 18510>, + <12567 13373 16287 18434 19041>, + <12767 14431 17166 19331 19871>, + <12906 14953 17644 19970 20772>, + <13043 15275 18035 20553 21985>, + <13254 15589 18448 20812 22838>, + <13520 16021 18878 20763 23075>, + <13787 16665 19253 20832 23069>, + <14074 17170 19532 21287 23403>, + <14425 17078 19373 21540 24108>, + <14893 16220 17894 20839 24888>, + <15428 16083 16100 18925 24832>, + <15715 18342 16976 18223 24189>, + <15770 20589 20553 20659 24472>, + <15797 20502 22513 23616 25498>, + <15834 19565 21295 23828 25788>, + <15830 19061 19385 22969 25708>, + <15750 18918 21990 23440 25684>, + <15580 18870 30436 27428 25707>, + <15309 20532 34653 30469 25746>, + <15057 25755 30884 27232 24220>, + <14852 31080 25218 20500 20766>, + <14649 35866 22212 18547 19399>, + <14406 39481 20440 20518 19854>, + <14102 39590 19963 22400 20596>, + <13801 37343 21441 23200 21434>, + <13549 34779 23939 23840 22513>, + <13290 32437 26091 24203 23750>, + <13021 30286 28345 24605 25226>, + <12746 29196 30150 25017 26620>, + <12479 28629 31211 25585 27804>, + <12282 28181 32038 26640 28805>, + <12126 27688 32872 28101 29029>, + <11990 27267 33745 30291 28636>, + <11896 27207 34089 31579 28289>, + <11945 27442 32771 31455 28513>, + <12049 27808 30864 31087 28942>, + <12350 28315 30537 30322 28828>, + <12671 28953 30633 27821 27284>, + <12642 29117 30687 26060 26101>, + <12299 27717 30577 26308 26287>, + <12208 24781 30313 26635 26505>, + <12309 16408 28848 26643 26112>, + <11428 13096 22891 26468 25271>, + <11198 12322 18301 26248 25109>, + <11112 12144 18213 22490 22887>, + <11116 12041 15832 22757 25790>, + <10935 11705 14733 23506 25696>, + <10976 11757 17791 27597 30144>, + <11440 12275 17295 25361 28944>, + <11648 12197 17311 24873 26253>, + <11657 11966 16067 25059 25290>, + <11600 11884 16052 23410 24581>, + <11600 11884 16052 23410 24581>, + <11600 11884 16052 23410 24581>; + }; + + qcom,pc-temp-z6-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <16538 15406 14813 14639 14611>, + <16749 15432 14830 14667 14637>, + <16795 15447 14830 14674 14643>, + <16769 15440 14820 14671 14641>, + <16699 15411 14805 14663 14634>, + <16612 15372 14791 14653 14625>, + <16540 15333 14779 14645 14619>, + <16482 15307 14768 14638 14613>, + <16423 15289 14762 14634 14608>, + <16352 15271 14759 14633 14606>, + <16282 15242 14755 14632 14604>, + <16243 15204 14746 14628 14603>, + <16229 15190 14734 14620 14598>, + <16213 15202 14738 14617 14595>, + <16158 15216 14756 14631 14602>, + <16064 15204 14764 14643 14610>, + <15984 15167 14745 14634 14604>, + <15930 15138 14722 14613 14590>, + <15887 15120 14722 14612 14588>, + <15858 15110 14737 14646 14613>, + <15836 15113 14757 14675 14640>, + <15826 15129 14785 14678 14644>, + <15826 15150 14807 14675 14644>, + <15831 15182 14806 14671 14642>, + <15836 15213 14793 14664 14635>, + <15841 15221 14782 14658 14628>, + <15846 15221 14776 14653 14623>, + <15850 15220 14772 14648 14620>, + <15854 15214 14769 14645 14617>, + <15856 15204 14766 14641 14614>, + <15856 15196 14763 14638 14611>, + <15856 15188 14761 14635 14608>, + <15855 15180 14760 14632 14605>, + <15853 15174 14759 14632 14604>, + <15851 15168 14759 14633 14604>, + <15851 15164 14758 14634 14604>, + <15853 15160 14756 14636 14607>, + <15855 15157 14754 14637 14611>, + <15855 15157 14752 14637 14612>, + <15854 15158 14751 14634 14610>, + <15851 15158 14750 14632 14608>, + <15842 15157 14749 14631 14608>, + <15832 15156 14747 14631 14607>, + <15821 15148 14743 14630 14607>, + <15777 15126 14731 14621 14600>, + <15764 15120 14719 14609 14585>, + <15763 15114 14716 14602 14578>, + <15759 15116 14713 14598 14572>, + <15757 15111 14711 14595 14570>, + <15765 15116 14716 14605 14584>, + <15777 15136 14723 14612 14591>, + <15805 15152 14732 14616 14594>, + <15840 15173 14739 14621 14598>, + <15893 15213 14754 14628 14605>, + <15893 15213 14754 14628 14605>, + <15893 15213 14754 14628 14605>; + }; + + qcom,pc-temp-y1-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <7598 6764 6071 5440 5223 5179>, + <7604 6767 6083 5439 5222 5181>, + <7616 6772 6090 5438 5222 5182>, + <7629 6778 6094 5436 5222 5184>, + <7640 6782 6096 5435 5223 5185>, + <7645 6784 6096 5434 5223 5187>, + <7644 6784 6092 5434 5224 5187>, + <7642 6784 6086 5434 5226 5188>, + <7635 6781 6085 5435 5228 5189>, + <7612 6774 6088 5436 5229 5190>, + <7594 6768 6090 5437 5231 5192>, + <7603 6766 6086 5437 5232 5193>, + <7624 6767 6080 5437 5234 5195>, + <7644 6772 6081 5438 5236 5197>, + <7668 6789 6096 5445 5241 5202>, + <7683 6807 6107 5453 5244 5204>, + <7674 6820 6111 5455 5244 5205>, + <7655 6831 6115 5458 5245 5205>, + <7640 6832 6116 5460 5246 5206>, + <7626 6817 6114 5461 5248 5209>, + <7619 6805 6114 5464 5251 5212>, + <7638 6807 6125 5468 5255 5216>, + <7673 6815 6139 5472 5259 5219>, + <7681 6821 6141 5477 5262 5223>, + <7680 6824 6136 5481 5265 5226>, + <7684 6828 6135 5485 5267 5230>, + <7689 6840 6144 5489 5270 5234>, + <7692 6860 6155 5494 5274 5237>, + <7690 6871 6158 5499 5277 5240>, + <7672 6876 6162 5505 5280 5242>, + <7648 6878 6167 5510 5283 5245>, + <7641 6875 6171 5515 5287 5248>, + <7643 6871 6175 5520 5290 5252>, + <7645 6871 6176 5523 5293 5255>, + <7649 6869 6177 5526 5296 5257>, + <7656 6867 6179 5529 5298 5259>, + <7671 6879 6183 5531 5300 5260>, + <7690 6895 6188 5533 5301 5261>, + <7693 6895 6193 5534 5301 5262>, + <7679 6883 6197 5535 5302 5262>, + <7669 6879 6202 5537 5303 5263>, + <7670 6885 6209 5541 5305 5265>, + <7670 6891 6220 5544 5306 5266>, + <7670 6898 6217 5546 5307 5267>, + <7674 6904 6224 5551 5310 5269>, + <7684 6923 6224 5553 5310 5270>, + <7689 6920 6233 5556 5310 5270>, + <7718 6926 6243 5556 5310 5270>, + <7735 6923 6251 5558 5311 5270>, + <7724 6942 6247 5561 5314 5272>, + <7721 6975 6265 5570 5317 5275>, + <7736 7003 6293 5585 5324 5280>, + <7777 7007 6312 5604 5331 5286>, + <7862 7038 6346 5623 5340 5292>, + <7862 7038 6346 5623 5340 5292>, + <7862 7038 6346 5623 5340 5292>; + }; + + qcom,pc-temp-y2-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <9686 10401 10680 11050 11104 11401>, + <9784 10367 10651 11029 11106 11345>, + <9844 10346 10618 11003 11105 11260>, + <9875 10335 10585 10974 11102 11170>, + <9887 10331 10557 10941 11096 11098>, + <9890 10330 10539 10906 11089 11068>, + <9836 10343 10530 10861 11080 11075>, + <9739 10365 10523 10815 11067 11086>, + <9714 10360 10518 10793 11048 11085>, + <9726 10302 10514 10780 11017 11066>, + <9749 10260 10512 10771 10981 11044>, + <9880 10338 10522 10756 10934 11003>, + <10116 10474 10547 10736 10885 10947>, + <10170 10505 10586 10738 10874 10940>, + <9944 10486 10664 10781 10896 10992>, + <9729 10473 10720 10835 10928 11033>, + <9701 10495 10746 10897 10988 11035>, + <9694 10532 10766 10960 11059 11032>, + <9688 10541 10781 10991 11079 11043>, + <9682 10540 10795 11004 11080 11097>, + <9677 10537 10806 11018 11082 11163>, + <9674 10483 10815 11049 11128 11225>, + <9672 10313 10824 11092 11200 11283>, + <9670 10193 10827 11124 11234 11325>, + <9667 10079 10832 11151 11254 11356>, + <9664 10012 10836 11169 11271 11377>, + <9663 9998 10834 11180 11289 11395>, + <9662 9984 10826 11184 11309 11414>, + <9661 9965 10822 11175 11317 11445>, + <9660 9940 10820 11150 11329 11500>, + <9659 9913 10815 11136 11341 11537>, + <9659 9889 10729 11139 11328 11522>, + <9658 9867 10574 11151 11311 11482>, + <9657 9842 10507 11164 11315 11466>, + <9656 9813 10490 11161 11321 11473>, + <9656 9786 10478 11140 11317 11478>, + <9655 9762 10470 11112 11316 11484>, + <9655 9732 10507 11097 11321 11496>, + <9654 9708 10556 11103 11323 11495>, + <9654 9694 10525 11104 11318 11473>, + <9654 9684 10426 11103 11314 11461>, + <9654 9675 10396 11106 11316 11468>, + <9654 9668 10406 11101 11314 11471>, + <9653 9662 10267 11078 11283 11464>, + <9653 9659 10199 11060 11283 11440>, + <9653 9659 10180 11025 11296 11394>, + <9653 9658 10256 11021 11274 11345>, + <9653 9657 10321 11043 11240 11336>, + <9653 9656 10323 11048 11247 11344>, + <9652 9656 10295 10982 11294 11322>, + <9652 9654 10240 10956 11255 11261>, + <9652 9653 10172 10913 11134 11175>, + <9652 9652 10118 10825 11023 11061>, + <9650 9652 10099 10780 10831 10826>, + <9650 9652 10099 10780 10831 10826>, + <9650 9652 10099 10780 10831 10826>; + }; + + qcom,pc-temp-y3-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <13434 13398 13345 13285 13280 13272>, + <13675 13407 13338 13284 13280 13274>, + <13823 13420 13334 13283 13280 13275>, + <13901 13433 13334 13283 13280 13277>, + <13931 13444 13336 13283 13280 13278>, + <13936 13449 13340 13285 13280 13278>, + <13804 13449 13347 13288 13280 13278>, + <13564 13448 13355 13293 13281 13278>, + <13499 13451 13358 13295 13281 13278>, + <13498 13470 13359 13296 13281 13277>, + <13499 13484 13360 13296 13281 13277>, + <13523 13470 13373 13303 13284 13279>, + <13572 13441 13392 13313 13289 13282>, + <13584 13425 13393 13314 13290 13283>, + <13548 13416 13371 13310 13288 13282>, + <13516 13410 13351 13307 13286 13282>, + <13520 13407 13346 13309 13288 13282>, + <13536 13405 13343 13313 13292 13283>, + <13543 13402 13339 13313 13292 13283>, + <13545 13397 13334 13305 13287 13280>, + <13546 13391 13329 13296 13283 13277>, + <13548 13381 13324 13288 13281 13276>, + <13552 13365 13319 13283 13280 13275>, + <13557 13351 13318 13282 13279 13275>, + <13568 13340 13317 13283 13278 13275>, + <13586 13335 13317 13284 13278 13274>, + <13605 13336 13317 13283 13278 13274>, + <13625 13339 13317 13283 13277 13274>, + <13647 13343 13317 13285 13277 13274>, + <13675 13347 13317 13289 13277 13273>, + <13709 13352 13317 13292 13277 13273>, + <13746 13357 13312 13293 13278 13273>, + <13786 13364 13305 13292 13278 13274>, + <13834 13372 13302 13292 13279 13274>, + <13889 13385 13303 13290 13278 13274>, + <13952 13400 13304 13288 13278 13273>, + <14017 13416 13307 13286 13278 13273>, + <14082 13434 13314 13284 13277 13273>, + <14146 13456 13320 13283 13277 13273>, + <14209 13488 13324 13283 13277 13273>, + <14273 13532 13327 13283 13277 13273>, + <14339 13585 13333 13283 13278 13274>, + <14405 13648 13342 13283 13278 13274>, + <14482 13731 13345 13284 13278 13274>, + <14570 13843 13353 13283 13278 13274>, + <14605 13890 13360 13291 13279 13276>, + <14655 13886 13365 13292 13281 13277>, + <14684 13912 13378 13296 13283 13280>, + <14733 14009 13393 13298 13282 13280>, + <14859 14104 13394 13294 13281 13277>, + <14999 14246 13402 13296 13280 13277>, + <15153 14472 13423 13301 13283 13281>, + <15376 14712 13458 13305 13286 13284>, + <16172 14971 13514 13315 13290 13286>, + <16172 14971 13514 13315 13290 13286>, + <16172 14971 13514 13315 13290 13286>; + }; + + qcom,pc-temp-y4-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <17845 16850 16626 16493 16453 16452>, + <17707 16859 16623 16499 16453 16450>, + <17643 16875 16623 16504 16455 16449>, + <17641 16896 16626 16507 16456 16448>, + <17685 16923 16631 16509 16458 16448>, + <17761 16953 16638 16510 16459 16448>, + <17959 16995 16646 16508 16461 16449>, + <18315 17038 16657 16506 16462 16452>, + <18708 17060 16668 16506 16465 16454>, + <19236 17069 16679 16513 16469 16457>, + <19572 17084 16696 16524 16475 16461>, + <19006 17415 16799 16542 16489 16473>, + <17760 17958 16951 16564 16509 16488>, + <17274 17986 16977 16573 16513 16492>, + <17223 17320 16899 16575 16509 16491>, + <17197 16817 16810 16579 16507 16490>, + <17184 16821 16750 16620 16529 16506>, + <17165 16866 16699 16681 16570 16536>, + <17135 16877 16663 16682 16576 16541>, + <17076 16837 16634 16593 16532 16509>, + <17012 16792 16611 16517 16486 16475>, + <16969 16768 16596 16504 16468 16461>, + <16936 16750 16584 16498 16457 16451>, + <16927 16747 16578 16495 16456 16450>, + <16931 16735 16574 16491 16456 16450>, + <16939 16719 16571 16489 16457 16451>, + <16945 16707 16570 16491 16459 16453>, + <16955 16695 16570 16493 16462 16456>, + <16966 16694 16569 16494 16465 16460>, + <16978 16706 16564 16496 16471 16465>, + <16990 16724 16560 16498 16478 16472>, + <17002 16743 16564 16500 16488 16483>, + <17014 16767 16573 16502 16499 16496>, + <17027 16792 16580 16500 16501 16498>, + <17040 16818 16585 16489 16484 16481>, + <17052 16845 16589 16478 16463 16460>, + <17064 16879 16594 16475 16452 16451>, + <17077 16927 16600 16473 16446 16447>, + <17095 16964 16604 16474 16446 16448>, + <17121 16978 16617 16477 16450 16453>, + <17160 16988 16637 16480 16455 16458>, + <17211 16994 16652 16483 16456 16459>, + <17278 17008 16664 16484 16454 16456>, + <17363 17031 16681 16481 16445 16443>, + <17450 17090 16711 16491 16449 16446>, + <17435 17135 16736 16501 16471 16474>, + <17438 17159 16742 16516 16496 16504>, + <17389 17194 16787 16546 16537 16546>, + <17360 17262 16870 16574 16540 16536>, + <17381 17283 16862 16542 16494 16484>, + <17398 17284 16856 16542 16480 16473>, + <17425 17312 16891 16573 16496 16487>, + <17507 17393 16998 16635 16528 16517>, + <18186 17570 17197 16862 16705 16664>, + <18186 17570 17197 16862 16705 16664>, + <18186 17570 17197 16862 16705 16664>; + }; + + qcom,pc-temp-y5-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <8712 13450 15024 13637 17779 13876>, + <8712 13482 14393 13094 17299 16002>, + <9887 13538 13920 12763 16795 17370>, + <12171 13602 13593 12592 16319 18144>, + <13352 13655 13402 12528 15924 18488>, + <13712 13682 13338 12519 15663 18564>, + <12526 13686 13491 13011 15524 18119>, + <10345 13688 13732 13797 15423 17285>, + <9855 13494 13762 13896 15233 16665>, + <10836 12338 13637 13520 14742 16018>, + <12278 11512 13460 13263 14463 15589>, + <14305 12246 13117 13605 14692 15613>, + <16658 13838 12700 14184 15051 15805>, + <17024 14948 12908 14300 15117 15807>, + <14139 15828 14686 14149 14970 15538>, + <11513 16242 16074 14033 14913 15280>, + <11523 16069 16259 14411 15080 15197>, + <11996 15810 16323 15261 15416 15147>, + <12172 15770 16274 15815 15959 15251>, + <12062 15859 16079 16180 16933 16031>, + <11868 15956 15846 16328 17499 16947>, + <11620 15469 15368 15383 17703 17632>, + <11312 13975 14705 13688 17924 18203>, + <11115 12872 14496 13266 17959 18431>, + <11014 12058 14552 13626 17682 18509>, + <10964 11631 14629 13920 17362 18511>, + <10973 11596 14709 13944 17173 18320>, + <10988 11605 14796 13932 17044 17852>, + <10995 11588 14900 14573 17019 17407>, + <11030 11538 15113 16622 17008 17007>, + <11086 11527 15270 18010 17024 16810>, + <11136 11527 14539 18405 17391 17083>, + <11177 11500 13186 18651 18220 17910>, + <11216 11497 12702 18616 19096 18783>, + <11256 11585 12708 17851 20108 19561>, + <11296 11690 12725 16773 20954 20137>, + <11333 11737 12833 15892 21243 20622>, + <11364 11658 13487 15086 21079 21066>, + <11372 11570 14099 14616 20668 21138>, + <11354 11602 14046 14527 20112 20711>, + <11333 11673 13559 14611 19900 20367>, + <11347 11689 13647 14598 20136 20790>, + <11447 11633 14091 14488 20830 22215>, + <11628 11564 13261 14690 21851 23634>, + <11886 11464 12890 13840 19650 20132>, + <12228 11536 12810 15945 17300 17267>, + <12464 11547 13361 15880 17100 16566>, + <12844 11910 14094 16530 16574 16161>, + <12886 12441 14613 16353 15911 15963>, + <12844 12583 14513 15967 17037 16654>, + <12567 12345 14561 17027 17428 17457>, + <12151 12056 14328 17704 18241 18950>, + <11887 11870 14282 17302 18299 19121>, + <11109 11677 14642 17219 17830 18283>, + <11109 11677 14642 17219 17830 18283>, + <11109 11677 14642 17219 17830 18283>; + }; + + qcom,pc-temp-y6-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <6900 5639 5266 5065 5021 5010>, + <6907 5646 5261 5064 5021 5011>, + <6911 5654 5258 5063 5021 5012>, + <6911 5662 5258 5064 5021 5013>, + <6908 5670 5260 5065 5022 5013>, + <6903 5678 5262 5066 5023 5014>, + <6855 5686 5268 5068 5023 5015>, + <6776 5694 5276 5071 5025 5015>, + <6772 5702 5281 5074 5026 5016>, + <6911 5708 5283 5076 5027 5017>, + <7024 5719 5288 5079 5029 5018>, + <6900 5804 5324 5090 5036 5023>, + <6611 5932 5379 5103 5045 5030>, + <6465 5932 5387 5106 5047 5032>, + <6414 5744 5349 5105 5045 5031>, + <6390 5602 5310 5104 5043 5031>, + <6395 5604 5291 5117 5051 5036>, + <6409 5621 5276 5138 5065 5045>, + <6413 5625 5263 5138 5067 5047>, + <6412 5613 5251 5107 5051 5035>, + <6410 5600 5242 5078 5035 5023>, + <6413 5590 5235 5069 5028 5018>, + <6426 5582 5230 5064 5025 5015>, + <6444 5577 5229 5063 5024 5015>, + <6469 5575 5230 5063 5024 5015>, + <6500 5574 5231 5064 5024 5016>, + <6530 5579 5232 5065 5025 5016>, + <6560 5589 5235 5066 5026 5017>, + <6592 5602 5237 5068 5027 5018>, + <6630 5619 5238 5072 5029 5020>, + <6673 5639 5239 5076 5031 5022>, + <6719 5661 5240 5078 5035 5026>, + <6770 5688 5241 5079 5039 5030>, + <6823 5717 5243 5078 5040 5031>, + <6880 5750 5247 5074 5035 5026>, + <6940 5787 5251 5070 5029 5020>, + <7001 5830 5256 5068 5026 5018>, + <7062 5880 5264 5067 5024 5016>, + <7124 5938 5274 5066 5024 5017>, + <7187 6002 5285 5067 5025 5018>, + <7249 6076 5296 5069 5027 5020>, + <7312 6161 5311 5070 5028 5021>, + <7379 6261 5328 5071 5027 5020>, + <7458 6383 5344 5072 5025 5017>, + <7552 6532 5369 5074 5027 5018>, + <7589 6585 5388 5083 5033 5027>, + <7631 6596 5395 5089 5042 5037>, + <7646 6631 5423 5100 5055 5051>, + <7684 6743 5466 5110 5056 5048>, + <7789 6847 5472 5099 5042 5031>, + <7903 6977 5491 5102 5038 5029>, + <8038 7181 5547 5117 5046 5036>, + <8244 7391 5646 5141 5058 5047>, + <9160 7653 5795 5217 5112 5092>, + <9160 7653 5795 5217 5112 5092>, + <9160 7653 5795 5217 5112 5092>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qg-batterydata-ascent-3450mah.dtsi b/arch/arm/boot/dts/qcom/qg-batterydata-ascent-3450mah.dtsi new file mode 100644 index 000000000000..8095f0cbf680 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qg-batterydata-ascent-3450mah.dtsi @@ -0,0 +1,1042 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +qcom,ascent_3450mah { + /* Ascent_wConn_3450mAh_Fresh_averaged_MasterSlave_Feb7th2018 */ + qcom,max-voltage-uv = <4350000>; + qcom,fg-cc-cv-threshold-uv = <4340000>; + qcom,fastchg-current-ma = <3450>; + qcom,batt-id-kohm = <60>; + qcom,battery-beta = <3435>; + qcom,battery-therm-kohm = <68>; + qcom,battery-type = + "Ascent_wConn_3450mAh_Fresh_averaged_MasterSlave_Feb7th2018"; + qcom,qg-batt-profile-ver = <100>; + + qcom,jeita-fcc-ranges = <0 50 1725000 + 51 400 3450000 + 401 450 2760000>; + qcom,jeita-fv-ranges = <0 50 4250000 + 51 400 4350000 + 401 450 4250000>; + qcom,step-chg-ranges = <3600000 3800000 3450000 + 3801000 4300000 2760000 + 4301000 4350000 2070000>; + qcom,ocv-based-step-chg; + + /* COOL = 5 DegC, WARM = 40 DegC */ + qcom,jeita-soft-thresholds = <0x44bd 0x1fc4>; + /* COLD = 0 DegC, HOT = 45 DegC */ + qcom,jeita-hard-thresholds = <0x4aa5 0x1bfb>; + + /* COOL hys = 8 DegC, WARM hys = 37 DegC */ + qcom,jeita-soft-hys-thresholds = <0x4126 0x223e>; + qcom,jeita-soft-fcc-ua = <1725000 2760000>; + qcom,jeita-soft-fv-uv = <4250000 4250000>; + + qcom,fcc1-temp-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-data = <3377 3428 3481 3496 3500>; + }; + + qcom,fcc2-temp-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-data = <3480 3482 3476 3492 3478 3466>; + }; + + qcom,pc-temp-v1-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <43212 43315 43370 43380 43383>, + <42963 43071 43141 43149 43152>, + <42723 42832 42902 42916 42922>, + <42488 42597 42662 42683 42693>, + <42262 42367 42430 42454 42465>, + <42043 42143 42202 42225 42238>, + <41832 41924 41976 41999 42013>, + <41624 41709 41754 41775 41791>, + <41419 41497 41536 41556 41571>, + <41220 41288 41322 41341 41355>, + <41039 41091 41113 41132 41143>, + <40866 40911 40916 40928 40936>, + <40676 40732 40729 40729 40734>, + <40449 40526 40541 40538 40541>, + <40230 40302 40340 40351 40355>, + <40061 40115 40146 40170 40176>, + <39918 39974 39984 40002 40007>, + <39787 39846 39843 39845 39846>, + <39672 39712 39697 39690 39689>, + <39560 39579 39548 39536 39538>, + <39426 39419 39388 39376 39384>, + <39271 39170 39192 39187 39198>, + <39112 38928 38961 38960 38967>, + <38934 38809 38788 38776 38775>, + <38764 38736 38674 38650 38646>, + <38660 38665 38581 38546 38539>, + <38589 38587 38491 38448 38439>, + <38533 38513 38408 38359 38347>, + <38487 38444 38334 38278 38263>, + <38448 38381 38265 38204 38187>, + <38407 38323 38204 38138 38118>, + <38364 38269 38149 38078 38055>, + <38322 38219 38099 38026 37999>, + <38284 38175 38053 37975 37942>, + <38249 38137 38014 37930 37889>, + <38211 38098 37974 37884 37834>, + <38174 38061 37930 37831 37767>, + <38129 38020 37882 37771 37691>, + <38055 37954 37816 37698 37610>, + <37946 37848 37718 37605 37524>, + <37825 37726 37602 37497 37426>, + <37689 37595 37474 37372 37301>, + <37541 37451 37332 37231 37156>, + <37372 37290 37178 37080 36999>, + <37271 37162 37061 36964 36886>, + <37191 37093 36992 36897 36819>, + <37157 37064 36970 36870 36798>, + <37128 37039 36949 36844 36770>, + <37084 37007 36903 36788 36714>, + <36927 36851 36683 36562 36488>, + <36555 36481 36290 36180 36108>, + <36071 35999 35771 35687 35620>, + <35450 35376 35098 35050 34994>, + <34604 34523 34174 34184 34150>, + <33275 33138 32725 32851 32862>, + <30000 30000 30000 30000 30000>; + }; + + qcom,pc-temp-v2-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <43425 43415 43385 43360 43315 43295>, + <43070 43109 43097 43094 43052 43033>, + <42748 42821 42826 42838 42799 42781>, + <42462 42555 42571 42594 42557 42541>, + <42208 42308 42333 42361 42326 42312>, + <41968 42072 42101 42133 42099 42086>, + <41736 41844 41872 41904 41872 41860>, + <41516 41625 41649 41680 41649 41637>, + <41303 41405 41431 41460 41430 41419>, + <41100 41186 41217 41243 41215 41204>, + <40896 40979 41012 41034 41005 40994>, + <40694 40796 40826 40840 40802 40789>, + <40482 40616 40642 40648 40604 40590>, + <40220 40407 40432 40445 40411 40399>, + <39903 40175 40199 40233 40222 40214>, + <39636 39954 39996 40043 40042 40036>, + <39443 39759 39844 39886 39877 39868>, + <39272 39570 39700 39736 39717 39706>, + <39091 39370 39511 39573 39556 39547>, + <38908 39162 39283 39399 39396 39391>, + <38742 38973 39072 39208 39217 39217>, + <38591 38806 38886 38975 38988 38994>, + <38460 38655 38721 38760 38766 38771>, + <38358 38519 38585 38613 38613 38614>, + <38274 38396 38468 38496 38494 38494>, + <38201 38287 38362 38390 38388 38387>, + <38138 38189 38265 38294 38291 38288>, + <38080 38106 38177 38206 38202 38198>, + <38027 38039 38096 38126 38120 38114>, + <37980 37983 38021 38051 38044 38037>, + <37934 37935 37954 37984 37976 37967>, + <37889 37895 37891 37921 37915 37905>, + <37843 37856 37838 37862 37856 37846>, + <37795 37815 37799 37803 37790 37781>, + <37746 37774 37768 37746 37720 37707>, + <37692 37727 37728 37685 37643 37621>, + <37633 37677 37677 37620 37554 37517>, + <37568 37618 37617 37550 37465 37411>, + <37491 37546 37548 37475 37387 37327>, + <37404 37459 37466 37395 37313 37256>, + <37310 37360 37369 37301 37226 37174>, + <37206 37243 37246 37187 37117 37069>, + <37103 37111 37106 37050 36988 36945>, + <37005 36964 36946 36900 36839 36796>, + <36909 36860 36837 36818 36761 36712>, + <36808 36782 36769 36775 36718 36673>, + <36746 36740 36732 36741 36690 36651>, + <36670 36688 36684 36692 36649 36612>, + <36553 36594 36591 36575 36542 36528>, + <36329 36380 36368 36272 36271 36278>, + <35961 35991 35957 35796 35833 35867>, + <35436 35452 35401 35193 35271 35340>, + <34709 34745 34680 34409 34550 34676>, + <33672 33759 33677 33330 33585 33791>, + <31857 32191 32244 31867 32001 32517>, + <28160 28896 29014 27510 28586 29617>; + }; + + qcom,pc-temp-z1-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <13703 12983 12375 12138 12079>, + <13647 12967 12370 12145 12092>, + <13621 12953 12363 12143 12093>, + <13606 12942 12357 12142 12093>, + <13594 12927 12349 12140 12093>, + <13585 12916 12342 12137 12093>, + <13577 12905 12339 12136 12092>, + <13569 12898 12337 12135 12092>, + <13560 12896 12337 12135 12091>, + <13551 12895 12339 12135 12091>, + <13540 12896 12342 12136 12091>, + <13527 12899 12342 12136 12091>, + <13512 12901 12342 12137 12093>, + <13488 12896 12342 12139 12095>, + <13469 12887 12343 12141 12097>, + <13469 12883 12347 12144 12098>, + <13473 12891 12352 12147 12101>, + <13478 12904 12360 12151 12103>, + <13489 12912 12369 12155 12106>, + <13502 12919 12378 12160 12109>, + <13514 12927 12387 12165 12113>, + <13525 12937 12396 12171 12117>, + <13538 12948 12404 12177 12122>, + <13555 12957 12412 12184 12127>, + <13572 12965 12422 12189 12131>, + <13578 12971 12431 12195 12135>, + <13580 12978 12440 12200 12139>, + <13582 12985 12448 12206 12143>, + <13594 12992 12456 12212 12147>, + <13613 13004 12464 12218 12151>, + <13625 13010 12472 12224 12156>, + <13631 13010 12479 12230 12160>, + <13632 13010 12486 12237 12165>, + <13627 13015 12494 12244 12171>, + <13618 13033 12505 12253 12177>, + <13619 13047 12517 12262 12183>, + <13629 13056 12529 12271 12190>, + <13640 13065 12541 12280 12196>, + <13647 13068 12553 12290 12203>, + <13654 13070 12565 12301 12210>, + <13663 13071 12577 12311 12217>, + <13678 13085 12588 12322 12224>, + <13694 13098 12598 12332 12232>, + <13718 13107 12607 12344 12239>, + <13717 13110 12621 12356 12248>, + <13717 13111 12638 12367 12256>, + <13693 13110 12640 12374 12262>, + <13712 13131 12642 12382 12269>, + <13714 13118 12659 12395 12280>, + <13717 13140 12677 12408 12291>, + <13717 13160 12678 12422 12303>, + <13740 13166 12691 12436 12316>, + <13739 13183 12711 12456 12332>, + <13754 13201 12735 12479 12355>, + <13754 13201 12735 12479 12355>, + <13754 13201 12735 12479 12355>; + }; + + qcom,pc-temp-z2-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <9983 10351 10639 10481 10418>, + <10020 10341 10669 10329 10279>, + <10051 10333 10528 10319 10282>, + <10083 10331 10397 10312 10281>, + <10100 10329 10358 10299 10263>, + <10094 10325 10328 10285 10234>, + <10081 10303 10324 10279 10227>, + <10069 10281 10328 10277 10237>, + <10058 10278 10330 10276 10251>, + <10050 10280 10326 10276 10266>, + <10044 10285 10321 10281 10280>, + <10039 10298 10323 10288 10285>, + <10038 10310 10324 10308 10284>, + <10045 10309 10318 10321 10285>, + <10054 10304 10304 10319 10295>, + <10056 10302 10291 10314 10309>, + <10056 10312 10297 10316 10321>, + <10058 10329 10320 10326 10335>, + <10070 10353 10339 10334 10341>, + <10090 10386 10349 10339 10346>, + <10111 10400 10358 10343 10354>, + <10138 10396 10373 10334 10340>, + <10157 10388 10395 10289 10270>, + <10169 10381 10400 10243 10212>, + <10178 10372 10354 10197 10174>, + <10183 10364 10306 10161 10144>, + <10190 10352 10304 10160 10141>, + <10194 10341 10307 10170 10149>, + <10185 10335 10310 10181 10158>, + <10169 10332 10311 10196 10169>, + <10165 10332 10314 10216 10183>, + <10168 10343 10327 10238 10202>, + <10171 10357 10356 10267 10226>, + <10175 10368 10381 10298 10253>, + <10180 10376 10405 10333 10288>, + <10183 10384 10422 10367 10326>, + <10186 10393 10431 10393 10358>, + <10189 10403 10438 10416 10387>, + <10187 10410 10442 10437 10405>, + <10181 10419 10455 10461 10418>, + <10175 10423 10465 10476 10426>, + <10164 10407 10466 10476 10430>, + <10152 10385 10468 10474 10428>, + <10142 10373 10453 10473 10402>, + <10064 10371 10455 10479 10389>, + <10173 10285 10486 10517 10402>, + <10003 10290 10490 10530 10416>, + <10151 10295 10531 10566 10477>, + <10255 10515 10588 10612 10540>, + <10077 10376 10556 10524 10421>, + <9948 10240 10480 10454 10314>, + <9854 10122 10384 10398 10256>, + <9640 9998 10319 10342 10182>, + <9440 9830 10255 10261 10065>, + <9440 9830 10255 10261 10065>, + <9440 9830 10255 10261 10065>; + }; + + qcom,pc-temp-z3-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <19441 19367 19362 19326 19316>, + <19560 19428 19358 19334 19329>, + <19615 19467 19373 19341 19335>, + <19645 19480 19383 19346 19340>, + <19658 19487 19385 19351 19344>, + <19657 19488 19387 19354 19347>, + <19657 19486 19386 19355 19348>, + <19655 19483 19384 19354 19347>, + <19651 19481 19382 19352 19346>, + <19647 19479 19380 19350 19345>, + <19645 19477 19378 19347 19344>, + <19642 19470 19377 19345 19342>, + <19642 19464 19374 19345 19342>, + <19642 19464 19372 19344 19341>, + <19643 19467 19372 19343 19338>, + <19639 19467 19372 19342 19336>, + <19626 19460 19371 19340 19334>, + <19615 19450 19369 19338 19332>, + <19604 19448 19368 19337 19330>, + <19596 19446 19368 19337 19328>, + <19597 19447 19369 19337 19326>, + <19605 19452 19372 19340 19328>, + <19612 19460 19378 19350 19341>, + <19619 19462 19386 19357 19350>, + <19626 19464 19394 19361 19353>, + <19627 19466 19401 19364 19355>, + <19626 19472 19400 19364 19355>, + <19624 19480 19398 19362 19352>, + <19620 19480 19395 19359 19349>, + <19615 19476 19391 19356 19346>, + <19611 19473 19388 19353 19343>, + <19609 19469 19384 19350 19340>, + <19606 19466 19381 19347 19336>, + <19604 19463 19379 19343 19332>, + <19601 19461 19377 19338 19327>, + <19597 19458 19375 19335 19324>, + <19592 19454 19373 19334 19325>, + <19587 19451 19370 19334 19329>, + <19584 19448 19368 19334 19330>, + <19582 19446 19366 19334 19328>, + <19579 19443 19364 19334 19326>, + <19575 19441 19362 19334 19326>, + <19571 19438 19360 19334 19327>, + <19565 19434 19359 19336 19329>, + <19361 19423 19353 19335 19328>, + <19262 19382 19344 19323 19324>, + <19263 19371 19336 19321 19317>, + <19261 19361 19332 19317 19313>, + <19261 19273 19326 19317 19309>, + <19262 19274 19335 19327 19319>, + <19263 19303 19337 19330 19324>, + <19263 19274 19357 19333 19327>, + <19266 19275 19361 19337 19335>, + <19272 19280 19368 19349 19345>, + <19272 19280 19368 19349 19345>, + <19272 19280 19368 19349 19345>; + }; + + qcom,pc-temp-z4-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <15627 15107 14765 14761 14758>, + <15711 15099 14864 14812 14796>, + <15693 15080 14843 14798 14788>, + <15530 15036 14821 14778 14775>, + <15355 14952 14794 14760 14761>, + <15246 14887 14764 14740 14745>, + <15155 14845 14741 14726 14731>, + <15085 14812 14721 14713 14719>, + <15031 14784 14710 14705 14711>, + <14985 14760 14705 14700 14707>, + <14938 14745 14702 14697 14705>, + <14895 14735 14696 14693 14702>, + <14876 14729 14689 14688 14699>, + <14872 14730 14686 14684 14697>, + <14869 14735 14686 14681 14694>, + <14856 14737 14686 14680 14692>, + <14830 14720 14682 14677 14689>, + <14808 14702 14673 14672 14684>, + <14790 14701 14669 14669 14681>, + <14778 14706 14676 14670 14679>, + <14782 14717 14687 14675 14677>, + <14805 14815 14716 14690 14685>, + <14835 14927 14778 14733 14726>, + <14898 14927 14803 14755 14750>, + <14965 14883 14774 14738 14735>, + <14974 14842 14741 14715 14712>, + <14963 14813 14728 14705 14703>, + <14950 14789 14721 14700 14699>, + <14932 14778 14717 14696 14696>, + <14910 14771 14715 14693 14692>, + <14892 14767 14713 14691 14688>, + <14878 14766 14712 14688 14683>, + <14867 14765 14712 14684 14677>, + <14856 14764 14710 14681 14673>, + <14847 14763 14709 14676 14668>, + <14838 14761 14706 14673 14666>, + <14826 14756 14703 14673 14669>, + <14816 14748 14700 14674 14680>, + <14809 14744 14697 14674 14683>, + <14804 14742 14695 14673 14677>, + <14797 14739 14693 14671 14673>, + <14787 14730 14687 14667 14673>, + <14774 14718 14678 14663 14675>, + <14753 14708 14673 14662 14682>, + <14897 14683 14660 14653 14674>, + <14965 14689 14638 14630 14635>, + <14964 14694 14635 14621 14624>, + <14958 14699 14630 14614 14617>, + <14951 14794 14633 14616 14620>, + <14945 14795 14637 14644 14655>, + <14957 14769 14642 14654 14664>, + <14968 14805 14636 14660 14668>, + <14977 14809 14655 14668 14668>, + <14993 14817 14684 14674 14665>, + <14993 14817 14684 14674 14665>, + <14993 14817 14684 14674 14665>; + }; + + qcom,pc-temp-z5-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <11983 12740 15393 15537 15330>, + <13357 14824 16249 17310 17529>, + <14286 16482 17811 18377 18523>, + <14945 17642 19175 19223 19510>, + <15486 18555 20024 20275 20513>, + <15957 19327 20723 21346 21540>, + <16368 19918 21568 22345 22519>, + <16781 20541 22514 23454 23469>, + <17187 21683 23120 24074 24236>, + <17674 23224 23449 23971 24698>, + <18442 24060 23713 23757 25052>, + <19483 24549 23914 23816 25554>, + <20437 24925 24207 24637 26312>, + <21361 25257 24451 25542 26851>, + <22105 25909 24697 26092 27021>, + <22478 26475 25087 26614 27131>, + <22735 27141 26348 27394 27470>, + <23076 28081 28954 28566 28331>, + <23809 29715 30229 29356 28825>, + <24938 32251 30431 29724 28646>, + <27176 33544 30446 29885 28135>, + <31932 33025 28578 28445 26783>, + <35226 31860 23567 23249 22747>, + <36819 29994 21621 20580 20432>, + <37874 26035 23092 21806 21763>, + <37147 24128 25214 23841 23948>, + <34993 26078 27156 25488 25430>, + <32825 29127 29386 27105 26647>, + <30980 31187 31134 28441 27481>, + <29376 32887 32400 29515 28206>, + <28873 34208 33430 30375 28775>, + <28786 35400 34311 31101 29161>, + <28801 36250 35051 31824 29873>, + <28836 36325 35497 32045 30283>, + <28862 36122 35938 31861 30590>, + <28907 35854 36221 31646 31106>, + <28980 35186 35497 31570 32686>, + <29132 34291 33694 31549 35494>, + <29670 33796 32315 31543 36261>, + <30652 33516 31332 31469 34185>, + <30992 33114 30388 31412 32325>, + <29938 32130 29262 32046 32870>, + <29033 30867 28327 33225 34089>, + <28928 29512 27958 34867 35083>, + <16971 28826 27177 35407 35456>, + <11113 18542 25875 28236 38118>, + <11084 16735 22486 31621 32274>, + <11037 15601 21798 36765 39261>, + <11035 11499 20071 40032 37713>, + <11055 11574 22201 35765 26327>, + <11017 12415 21829 29484 22484>, + <10951 11419 39496 26044 20817>, + <10890 11348 40899 24307 20580>, + <10822 11392 37952 25288 21070>, + <10822 11392 37952 25288 21070>, + <10822 11392 37952 25288 21070>; + }; + + qcom,pc-temp-z6-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <15711 15103 14773 14710 14694>, + <15778 15117 14813 14736 14718>, + <15776 15120 14809 14733 14717>, + <15702 15106 14804 14728 14716>, + <15620 15065 14793 14722 14713>, + <15561 15031 14779 14715 14707>, + <15508 15007 14768 14709 14701>, + <15467 14987 14758 14703 14696>, + <15435 14971 14751 14698 14692>, + <15407 14959 14748 14695 14689>, + <15379 14949 14746 14692 14687>, + <15353 14940 14743 14689 14685>, + <15339 14935 14739 14687 14684>, + <15332 14935 14736 14685 14682>, + <15326 14938 14737 14684 14680>, + <15316 14939 14738 14683 14678>, + <15302 14930 14736 14681 14676>, + <15293 14921 14733 14679 14673>, + <15289 14921 14732 14677 14671>, + <15286 14926 14736 14678 14670>, + <15291 14936 14744 14682 14669>, + <15312 14986 14761 14691 14674>, + <15338 15040 14795 14718 14702>, + <15373 15042 14808 14732 14717>, + <15408 15027 14802 14727 14713>, + <15415 15016 14795 14720 14706>, + <15414 15011 14791 14717 14702>, + <15412 15007 14788 14714 14699>, + <15408 15006 14786 14712 14697>, + <15402 15004 14785 14710 14694>, + <15399 15004 14784 14708 14691>, + <15398 15005 14784 14706 14688>, + <15397 15006 14784 14704 14684>, + <15397 15009 14784 14701 14680>, + <15398 15012 14784 14699 14677>, + <15400 15015 14785 14696 14674>, + <15402 15016 14785 14697 14677>, + <15405 15017 14786 14699 14684>, + <15410 15020 14787 14700 14687>, + <15416 15026 14789 14702 14685>, + <15423 15031 14791 14703 14683>, + <15430 15034 14791 14703 14684>, + <15437 15037 14791 14704 14687>, + <15444 15040 14792 14706 14693>, + <15425 15039 14789 14704 14690>, + <15419 15030 14781 14691 14673>, + <15424 15030 14778 14688 14665>, + <15425 15032 14777 14685 14661>, + <15431 15036 14780 14688 14662>, + <15438 15047 14792 14708 14685>, + <15458 15060 14801 14718 14695>, + <15477 15072 14815 14726 14702>, + <15501 15088 14835 14737 14710>, + <15534 15114 14862 14753 14720>, + <15534 15114 14862 14753 14720>, + <15534 15114 14862 14753 14720>; + }; + + qcom,pc-temp-y1-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <6963 6363 6007 5630 5512 5470>, + <6945 6361 6003 5629 5510 5471>, + <6934 6357 5999 5628 5508 5471>, + <6929 6354 5995 5627 5506 5471>, + <6928 6353 5992 5626 5505 5470>, + <6928 6357 5988 5625 5503 5470>, + <6934 6366 5985 5624 5502 5469>, + <6942 6374 5981 5624 5501 5467>, + <6939 6374 5982 5623 5500 5467>, + <6920 6366 5984 5624 5499 5467>, + <6910 6360 5985 5624 5498 5466>, + <6919 6357 5980 5623 5498 5466>, + <6931 6356 5973 5622 5498 5465>, + <6935 6362 5973 5622 5499 5465>, + <6938 6380 5978 5625 5500 5466>, + <6939 6390 5981 5628 5501 5467>, + <6942 6389 5985 5631 5501 5468>, + <6946 6387 5990 5634 5502 5469>, + <6943 6388 5989 5637 5503 5470>, + <6932 6391 5988 5639 5506 5471>, + <6929 6394 5987 5643 5508 5472>, + <6957 6397 5989 5647 5510 5473>, + <6985 6400 5994 5653 5513 5475>, + <6976 6405 6001 5658 5515 5478>, + <6942 6414 6012 5663 5518 5480>, + <6928 6418 6018 5668 5522 5483>, + <6934 6419 6019 5674 5525 5486>, + <6942 6418 6020 5681 5529 5488>, + <6951 6418 6021 5687 5533 5491>, + <6972 6418 6023 5692 5537 5493>, + <6978 6418 6025 5698 5541 5497>, + <6971 6422 6028 5705 5545 5500>, + <6961 6425 6032 5712 5550 5504>, + <6947 6422 6038 5720 5554 5507>, + <6929 6416 6048 5727 5559 5509>, + <6925 6416 6055 5734 5563 5512>, + <6932 6428 6059 5741 5569 5516>, + <6939 6438 6062 5748 5575 5522>, + <6939 6433 6063 5757 5580 5526>, + <6942 6422 6064 5767 5585 5529>, + <6944 6417 6067 5775 5591 5533>, + <6946 6416 6077 5783 5596 5537>, + <6941 6418 6083 5787 5603 5541>, + <6923 6429 6090 5790 5610 5546>, + <6953 6428 6086 5808 5622 5555>, + <6932 6433 6091 5813 5631 5561>, + <6928 6433 6099 5818 5635 5565>, + <6933 6442 6113 5834 5640 5567>, + <6932 6430 6105 5835 5645 5571>, + <6936 6436 6106 5848 5654 5578>, + <6965 6440 6099 5858 5666 5585>, + <6990 6464 6110 5873 5684 5600>, + <7027 6445 6123 5887 5704 5613>, + <7064 6471 6136 5914 5726 5633>, + <7064 6471 6136 5914 5726 5633>, + <7064 6471 6136 5914 5726 5633>; + }; + + qcom,pc-temp-y2-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <9643 10780 11037 11216 11097 11009>, + <9653 10747 10993 11177 11076 11016>, + <9867 10710 10945 11129 11053 11018>, + <10082 10673 10898 11080 11031 11018>, + <10246 10642 10860 11037 11010 11015>, + <10308 10624 10837 11007 10992 11010>, + <10281 10616 10826 10987 10977 10981>, + <10241 10610 10820 10968 10962 10937>, + <10275 10600 10816 10953 10942 10920>, + <10440 10586 10802 10939 10913 10908>, + <10531 10580 10792 10927 10894 10901>, + <10522 10610 10786 10915 10881 10897>, + <10502 10665 10780 10900 10869 10890>, + <10430 10721 10797 10878 10869 10877>, + <10226 10789 10873 10846 10876 10849>, + <10115 10817 10940 10834 10878 10831>, + <9949 10805 10988 10876 10871 10840>, + <9749 10791 11021 10939 10863 10860>, + <9704 10791 11014 10991 10869 10866>, + <9683 10795 10979 11041 10898 10870>, + <9677 10801 10965 11063 10936 10877>, + <9676 10808 10997 11078 11004 10940>, + <9676 10820 11042 11093 11066 11026>, + <9674 10836 11062 11099 11074 11055>, + <9670 10861 11077 11105 11063 11066>, + <9667 10915 11082 11111 11064 11068>, + <9665 11341 11085 11126 11092 11072>, + <9663 11748 11091 11149 11125 11083>, + <9661 11516 11099 11179 11148 11096>, + <9659 10816 11110 11217 11174 11118>, + <9658 10376 11118 11236 11190 11131>, + <9657 10155 11117 11245 11208 11140>, + <9656 10000 11109 11252 11224 11152>, + <9655 9892 11094 11259 11233 11175>, + <9654 9812 11060 11260 11250 11208>, + <9654 9762 11020 11250 11255 11218>, + <9653 9725 10915 11227 11244 11186>, + <9653 9701 10784 11207 11227 11146>, + <9653 9688 10695 11192 11211 11135>, + <9652 9678 10615 11172 11194 11131>, + <9652 9671 10480 11143 11192 11126>, + <9652 9665 10201 11106 11216 11112>, + <9651 9661 10108 11076 11220 11105>, + <9651 9658 10159 11042 11183 11120>, + <9651 9656 9965 10929 11157 11073>, + <9651 9654 9856 10889 11090 11023>, + <9651 9653 9796 10823 11057 10968>, + <9650 9653 9741 10794 11051 10955>, + <9650 9652 9696 10740 11029 10918>, + <9650 9652 9680 10652 10968 10907>, + <9650 9651 9670 10540 10916 10868>, + <9649 9651 9663 10397 10801 10776>, + <9648 9650 9657 10262 10712 10696>, + <9648 9650 9654 10448 10584 10596>, + <9648 9650 9654 10448 10584 10596>, + <9648 9650 9654 10448 10584 10596>; + }; + + qcom,pc-temp-y3-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <13491 13351 13296 13276 13275 13272>, + <13481 13348 13297 13278 13275 13272>, + <13476 13346 13298 13280 13275 13273>, + <13476 13347 13300 13282 13276 13274>, + <13480 13349 13302 13283 13276 13274>, + <13486 13352 13303 13283 13276 13275>, + <13513 13358 13303 13283 13276 13275>, + <13546 13363 13304 13283 13276 13275>, + <13543 13365 13306 13283 13277 13275>, + <13505 13365 13310 13284 13278 13275>, + <13476 13366 13315 13285 13278 13276>, + <13465 13371 13319 13285 13278 13276>, + <13456 13377 13322 13285 13278 13276>, + <13446 13376 13322 13286 13278 13276>, + <13434 13369 13321 13288 13279 13277>, + <13428 13363 13320 13290 13279 13277>, + <13428 13359 13318 13291 13280 13278>, + <13428 13354 13316 13292 13282 13278>, + <13414 13349 13313 13292 13283 13279>, + <13377 13343 13308 13291 13283 13281>, + <13356 13338 13304 13290 13284 13281>, + <13351 13336 13301 13286 13280 13278>, + <13349 13333 13299 13283 13276 13274>, + <13354 13323 13298 13282 13275 13273>, + <13374 13301 13297 13281 13275 13273>, + <13397 13289 13297 13281 13275 13273>, + <13424 13273 13297 13280 13275 13273>, + <13457 13259 13297 13280 13275 13273>, + <13494 13259 13296 13280 13275 13273>, + <13537 13259 13296 13280 13275 13273>, + <13586 13260 13295 13280 13274 13272>, + <13644 13261 13291 13280 13274 13272>, + <13708 13262 13288 13279 13274 13272>, + <13777 13264 13289 13279 13274 13272>, + <13853 13268 13293 13279 13273 13272>, + <13939 13274 13295 13279 13273 13272>, + <14040 13285 13294 13279 13274 13272>, + <14153 13299 13292 13280 13274 13273>, + <14276 13317 13292 13279 13274 13273>, + <14412 13340 13293 13279 13274 13273>, + <14564 13372 13291 13279 13274 13273>, + <14738 13423 13271 13280 13275 13273>, + <14925 13493 13262 13280 13275 13273>, + <15128 13598 13261 13280 13274 13273>, + <15354 13729 13263 13279 13275 13274>, + <15547 13885 13266 13284 13276 13275>, + <15700 13996 13270 13284 13277 13277>, + <15883 14139 13280 13288 13279 13277>, + <16098 14305 13309 13290 13280 13277>, + <16340 14489 13343 13292 13280 13276>, + <16656 14726 13389 13294 13281 13277>, + <17634 15025 13481 13299 13283 13278>, + <19636 15401 13635 13309 13286 13283>, + <22946 16005 13899 13335 13293 13287>, + <22946 16005 13899 13335 13293 13287>, + <22946 16005 13899 13335 13293 13287>; + }; + + qcom,pc-temp-y4-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <16973 16623 16526 16458 16452 16456>, + <16999 16632 16525 16457 16452 16456>, + <17030 16641 16525 16457 16452 16456>, + <17060 16652 16526 16457 16452 16456>, + <17082 16663 16528 16457 16452 16456>, + <17089 16674 16531 16457 16452 16456>, + <17077 16687 16535 16459 16452 16456>, + <17059 16701 16539 16462 16453 16456>, + <17098 16711 16545 16465 16453 16456>, + <17276 16720 16552 16468 16454 16457>, + <17396 16735 16563 16473 16455 16457>, + <17426 16824 16584 16480 16458 16458>, + <17443 16930 16612 16490 16461 16460>, + <17384 16951 16638 16498 16465 16462>, + <17155 16958 16663 16504 16470 16465>, + <17028 16959 16695 16515 16476 16469>, + <17014 16934 16758 16539 16486 16475>, + <17005 16887 16816 16571 16502 16486>, + <16980 16831 16800 16609 16530 16506>, + <16933 16754 16713 16656 16576 16541>, + <16886 16692 16635 16664 16593 16558>, + <16837 16644 16572 16570 16535 16521>, + <16797 16610 16522 16475 16468 16470>, + <16783 16607 16507 16460 16455 16458>, + <16776 16623 16498 16454 16451 16455>, + <16770 16632 16494 16453 16449 16454>, + <16765 16645 16493 16454 16449 16453>, + <16761 16659 16493 16455 16448 16453>, + <16761 16662 16492 16457 16449 16453>, + <16761 16663 16493 16461 16452 16454>, + <16762 16667 16493 16466 16456 16455>, + <16764 16677 16492 16474 16464 16461>, + <16767 16687 16492 16479 16471 16470>, + <16770 16690 16494 16478 16474 16476>, + <16775 16693 16500 16474 16474 16483>, + <16778 16693 16505 16467 16471 16482>, + <16782 16689 16508 16455 16458 16467>, + <16784 16685 16510 16448 16447 16453>, + <16783 16685 16511 16449 16450 16455>, + <16781 16683 16512 16452 16456 16465>, + <16779 16681 16517 16455 16459 16471>, + <16770 16670 16558 16460 16458 16470>, + <16768 16654 16579 16464 16456 16468>, + <16776 16634 16584 16465 16448 16452>, + <16801 16629 16593 16474 16448 16444>, + <16819 16647 16617 16493 16467 16470>, + <16856 16669 16641 16507 16488 16496>, + <16905 16699 16672 16536 16520 16521>, + <16944 16754 16675 16565 16529 16536>, + <16949 16780 16683 16555 16503 16488>, + <16941 16767 16681 16554 16495 16479>, + <17078 16794 16695 16582 16508 16485>, + <17565 16874 16751 16646 16545 16510>, + <19162 17124 16888 16859 16671 16581>, + <19162 17124 16888 16859 16671 16581>, + <19162 17124 16888 16859 16671 16581>; + }; + + qcom,pc-temp-y5-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <11501 16034 14767 13793 19407 15565>, + <11603 15822 15156 15683 19413 16938>, + <11875 15497 15333 17017 19416 18058>, + <12285 15152 15352 17855 19416 18894>, + <12803 14881 15266 18259 19413 19416>, + <13403 14778 15128 18284 19405 19590>, + <14551 14807 14793 17405 18933 19301>, + <15710 14848 14419 16236 18269 18809>, + <15425 14688 14471 15943 18195 18561>, + <13533 13983 14951 15873 18327 18385>, + <12513 13556 15219 15744 18394 18198>, + <13803 13493 14892 15050 17832 17726>, + <15473 13460 14418 14306 16921 17099>, + <15394 13744 14254 14381 16318 16821>, + <14258 14851 14181 14869 15815 16673>, + <13562 15643 14199 15070 15556 16471>, + <13428 15965 14556 14786 15450 15954>, + <13274 16199 15160 14490 15387 15465>, + <12936 16398 15863 14755 15446 15449>, + <12423 16588 16824 15793 15777 15650>, + <11952 16732 17460 16919 16267 15980>, + <11476 16879 17821 18292 17600 16933>, + <11117 16964 18087 19430 19112 18163>, + <11033 16245 18242 19821 19838 19000>, + <11009 14141 18325 19945 20331 19696>, + <11024 12876 18331 19914 20756 20093>, + <11056 11798 18517 19842 21457 20297>, + <11084 10948 18759 19785 21999 20418>, + <11132 10879 18828 19716 21658 20286>, + <11232 10862 18868 19575 20509 19563>, + <11269 10868 18768 19409 19604 18813>, + <11345 11005 17096 19184 18920 18072>, + <11421 11165 15478 19049 18499 17524>, + <11456 11261 16038 19331 18661 17776>, + <11520 11350 17571 20041 19331 19034>, + <11543 11387 18037 20606 20274 20444>, + <11613 11553 17270 21412 23017 22060>, + <11678 11697 16300 21789 25208 23225>, + <11640 11640 15861 20914 24442 22731>, + <11545 11511 15530 19618 22425 21047>, + <11506 11463 14798 19274 21559 20283>, + <11457 11412 12697 19217 21506 20308>, + <11415 11500 11853 18717 21719 20486>, + <11368 11742 11779 17923 22443 22679>, + <11364 11818 11639 16687 21754 22971>, + <11379 11581 11310 17555 18408 18279>, + <11464 11576 11214 16686 17313 17483>, + <11729 11969 11315 17033 16467 15409>, + <12142 11899 11677 16717 15881 14424>, + <11979 11895 11966 17491 17177 15372>, + <11649 12007 11983 17478 18213 16253>, + <11017 11938 11964 17190 17836 15973>, + <10265 11845 11923 16780 17343 17751>, + <9626 11312 12185 16916 17400 17911>, + <9626 11312 12185 16916 17400 17911>, + <9626 11312 12185 16916 17400 17911>; + }; + + qcom,pc-temp-y6-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <6106 5405 5178 5064 5046 5042>, + <6097 5401 5177 5064 5046 5042>, + <6092 5400 5176 5065 5046 5042>, + <6089 5400 5176 5066 5047 5043>, + <6088 5401 5176 5067 5047 5044>, + <6088 5403 5176 5067 5047 5044>, + <6090 5407 5176 5068 5047 5044>, + <6094 5413 5177 5068 5047 5044>, + <6102 5416 5178 5069 5047 5044>, + <6117 5418 5182 5071 5048 5044>, + <6129 5422 5187 5073 5049 5045>, + <6135 5450 5195 5075 5050 5045>, + <6139 5483 5204 5078 5051 5046>, + <6123 5488 5211 5081 5052 5047>, + <6059 5490 5218 5085 5054 5048>, + <6027 5490 5226 5089 5056 5050>, + <6030 5484 5243 5097 5060 5052>, + <6034 5472 5259 5107 5066 5055>, + <6032 5457 5253 5118 5075 5062>, + <6027 5435 5225 5131 5088 5073>, + <6025 5421 5201 5133 5093 5078>, + <6031 5414 5182 5104 5074 5065>, + <6042 5409 5169 5075 5052 5048>, + <6061 5410 5167 5071 5048 5044>, + <6095 5412 5166 5069 5047 5043>, + <6132 5415 5166 5069 5046 5042>, + <6169 5421 5168 5070 5047 5042>, + <6210 5431 5171 5071 5047 5042>, + <6254 5444 5175 5073 5048 5043>, + <6302 5464 5178 5075 5049 5043>, + <6354 5486 5181 5078 5050 5044>, + <6411 5511 5183 5081 5052 5046>, + <6471 5539 5185 5083 5055 5048>, + <6535 5569 5192 5084 5056 5050>, + <6602 5603 5205 5084 5056 5053>, + <6677 5640 5216 5084 5056 5053>, + <6759 5681 5225 5083 5053 5049>, + <6849 5727 5234 5083 5051 5046>, + <6948 5778 5244 5084 5052 5047>, + <7058 5835 5257 5087 5055 5050>, + <7178 5899 5273 5091 5057 5052>, + <7313 5971 5295 5095 5058 5052>, + <7461 6060 5322 5099 5058 5052>, + <7625 6170 5355 5104 5056 5049>, + <7801 6295 5404 5112 5059 5048>, + <7952 6438 5465 5127 5066 5057>, + <8083 6542 5513 5135 5074 5067>, + <8233 6666 5574 5150 5086 5075>, + <8404 6813 5646 5166 5090 5080>, + <8597 6972 5725 5172 5084 5066>, + <8831 7159 5819 5184 5085 5065>, + <9655 7408 5955 5214 5093 5070>, + <11356 7725 6149 5262 5110 5083>, + <14260 8288 6430 5374 5157 5109>, + <14260 8288 6430 5374 5157 5109>, + <14260 8288 6430 5374 5157 5109>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qg-batterydata-mlp356477-2800mah.dtsi b/arch/arm/boot/dts/qcom/qg-batterydata-mlp356477-2800mah.dtsi new file mode 100644 index 000000000000..b39d11b6fa54 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qg-batterydata-mlp356477-2800mah.dtsi @@ -0,0 +1,1044 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,mlp356477_2800mah { + /* mlp356477_2800mah_averaged_MasterSlave_Mar13th2018 */ + qcom,max-voltage-uv = <4400000>; + qcom,fg-cc-cv-threshold-mv = <4390>; + qcom,fastchg-current-ma = <4200>; + qcom,batt-id-kohm = <82>; + qcom,battery-beta = <4250>; + qcom,battery-therm-kohm = <100>; + qcom,battery-type = + "mlp356477_2800mah_averaged_MasterSlave_Mar13th2018"; + qcom,qg-batt-profile-ver = <100>; + + qcom,jeita-fcc-ranges = <0 150 560000 + 151 450 4200000 + 451 550 2380000>; + qcom,jeita-fv-ranges = <0 150 4150000 + 151 450 4400000 + 451 550 4150000>; + + /* COOL = 15 DegC, WARM = 45 DegC */ + qcom,jeita-soft-thresholds = <0x4621 0x20b8>; + /* COLD = 0 DegC, HOT = 55 DegC */ + qcom,jeita-hard-thresholds = <0x58cd 0x181d>; + /* COOL hys = 18 DegC, WARM hys = 42 DegC */ + qcom,jeita-soft-hys-thresholds = <0x4206 0x23c0>; + qcom,jeita-soft-fcc-ua = <560000 2380000>; + qcom,jeita-soft-fv-uv = <4150000 4150000>; + + qcom,fcc1-temp-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-data = <2715 2788 2861 2898 2908>; + }; + + qcom,fcc2-temp-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-data = <2864 2846 2860 2868 2865 2865>; + }; + + qcom,pc-temp-v1-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <43494 43682 43812 43865 43879>, + <43243 43420 43582 43645 43659>, + <42984 43174 43350 43418 43434>, + <42737 42940 43115 43191 43208>, + <42506 42710 42878 42958 42978>, + <42287 42479 42641 42722 42746>, + <42087 42250 42407 42489 42514>, + <41903 42027 42175 42255 42281>, + <41709 41807 41948 42023 42050>, + <41489 41592 41723 41794 41822>, + <41265 41381 41502 41568 41596>, + <41069 41176 41286 41348 41374>, + <40898 40982 41074 41131 41155>, + <40720 40799 40871 40921 40942>, + <40501 40613 40673 40716 40735>, + <40269 40405 40482 40518 40534>, + <40088 40193 40295 40329 40343>, + <39955 40022 40116 40148 40162>, + <39834 39894 39952 39975 39988>, + <39708 39765 39807 39818 39827>, + <39583 39577 39645 39659 39667>, + <39447 39345 39420 39461 39475>, + <39277 39148 39173 39221 39239>, + <39089 38991 38991 39014 39028>, + <38930 38860 38851 38860 38868>, + <38794 38758 38733 38728 38732>, + <38683 38676 38628 38611 38612>, + <38607 38602 38535 38507 38505>, + <38548 38529 38451 38414 38409>, + <38501 38462 38373 38327 38317>, + <38466 38407 38305 38251 38234>, + <38437 38360 38245 38182 38160>, + <38405 38317 38193 38121 38092>, + <38366 38277 38147 38067 38030>, + <38329 38240 38109 38022 37980>, + <38300 38203 38069 37977 37929>, + <38273 38170 38027 37921 37863>, + <38236 38130 37980 37857 37784>, + <38162 38057 37912 37781 37700>, + <38062 37946 37816 37690 37609>, + <37947 37830 37704 37585 37507>, + <37801 37713 37578 37463 37382>, + <37644 37575 37436 37322 37239>, + <37473 37394 37270 37162 37082>, + <37320 37251 37129 37032 36959>, + <37220 37161 37058 36960 36899>, + <37185 37129 37033 36942 36880>, + <37156 37103 37014 36927 36865>, + <37120 37070 36988 36902 36835>, + <37014 36957 36885 36755 36652>, + <36682 36593 36544 36398 36287>, + <36204 36109 36077 35921 35807>, + <35597 35486 35476 35307 35181>, + <34771 34630 34656 34460 34321>, + <33460 33262 33379 33128 32955>, + <30000 30000 30000 30000 30000>; + }; + + qcom,pc-temp-v2-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <43865 43850 43830 43805 43740 43725>, + <43432 43429 43514 43528 43481 43467>, + <43037 43064 43219 43264 43228 43216>, + <42685 42767 42948 43012 42983 42973>, + <42369 42526 42700 42773 42744 42738>, + <42075 42296 42458 42537 42509 42505>, + <41776 42059 42213 42303 42277 42272>, + <41517 41822 41972 42071 42047 42041>, + <41353 41571 41739 41843 41820 41814>, + <41239 41298 41515 41619 41595 41589>, + <41095 41069 41297 41398 41374 41368>, + <40895 40928 41088 41181 41158 41151>, + <40650 40808 40884 40967 40946 40938>, + <40329 40611 40677 40763 40742 40734>, + <39941 40284 40461 40566 40541 40534>, + <39654 39989 40259 40373 40348 40342>, + <39456 39811 40087 40180 40164 40158>, + <39278 39662 39920 39993 39985 39980>, + <39086 39459 39722 39821 39814 39808>, + <38900 39184 39492 39664 39651 39646>, + <38740 38924 39264 39483 39469 39466>, + <38598 38721 39048 39237 39230 39230>, + <38480 38546 38846 38982 38986 38989>, + <38386 38403 38678 38799 38809 38813>, + <38308 38282 38535 38654 38669 38674>, + <38240 38189 38406 38530 38547 38552>, + <38182 38125 38286 38419 38438 38442>, + <38127 38075 38179 38320 38341 38343>, + <38076 38030 38090 38229 38250 38250>, + <38028 37992 38012 38144 38166 38164>, + <37978 37955 37949 38066 38089 38086>, + <37927 37916 37900 37993 38019 38016>, + <37875 37875 37857 37925 37953 37949>, + <37820 37832 37817 37860 37884 37875>, + <37763 37788 37781 37801 37812 37795>, + <37699 37738 37740 37738 37728 37702>, + <37630 37680 37688 37671 37625 37587>, + <37555 37613 37625 37600 37519 37469>, + <37475 37537 37552 37525 37430 37374>, + <37392 37448 37465 37446 37352 37292>, + <37308 37349 37363 37353 37263 37200>, + <37222 37237 37238 37238 37151 37088>, + <37133 37114 37101 37106 37022 36960>, + <37035 36989 36957 36952 36870 36813>, + <36935 36875 36859 36862 36807 36758>, + <36817 36792 36792 36828 36785 36734>, + <36752 36754 36762 36812 36769 36719>, + <36667 36707 36710 36780 36736 36687>, + <36541 36633 36613 36721 36656 36581>, + <36342 36472 36411 36517 36379 36276>, + <36024 36149 36031 36113 35946 35829>, + <35575 35650 35485 35584 35386 35258>, + <34953 34964 34771 34884 34643 34500>, + <34073 34007 33739 33902 33598 33440>, + <32647 32474 32144 32393 32025 31829>, + <30018 28051 26513 28737 27554 26991>; + }; + + qcom,pc-temp-z1-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <14442 13243 12339 11979 11839>, + <14411 13218 12328 11916 11773>, + <14392 13199 12294 11893 11756>, + <14384 13180 12273 11879 11745>, + <14381 13174 12263 11870 11738>, + <14377 13179 12257 11863 11735>, + <14369 13182 12253 11858 11731>, + <14358 13175 12250 11851 11726>, + <14349 13158 12248 11847 11722>, + <14339 13146 12242 11845 11720>, + <14332 13143 12237 11845 11719>, + <14327 13144 12237 11844 11718>, + <14321 13142 12238 11840 11716>, + <14313 13135 12234 11837 11715>, + <14306 13128 12222 11835 11714>, + <14299 13120 12215 11834 11714>, + <14293 13113 12211 11833 11713>, + <14293 13111 12203 11830 11714>, + <14297 13119 12202 11828 11715>, + <14304 13129 12210 11831 11716>, + <14312 13133 12215 11837 11718>, + <14318 13130 12221 11841 11721>, + <14319 13125 12230 11843 11726>, + <14320 13135 12234 11846 11730>, + <14324 13151 12236 11852 11734>, + <14340 13158 12238 11860 11737>, + <14358 13165 12247 11865 11741>, + <14373 13167 12258 11870 11747>, + <14389 13165 12260 11873 11752>, + <14394 13167 12258 11877 11757>, + <14373 13169 12256 11880 11760>, + <14334 13168 12253 11886 11764>, + <14321 13167 12247 11892 11768>, + <14348 13170 12248 11897 11772>, + <14378 13177 12260 11901 11778>, + <14371 13182 12271 11905 11783>, + <14343 13188 12277 11910 11788>, + <14331 13194 12283 11917 11792>, + <14346 13205 12290 11924 11797>, + <14369 13219 12300 11931 11803>, + <14389 13228 12307 11937 11809>, + <14412 13237 12311 11941 11815>, + <14410 13245 12315 11945 11820>, + <14367 13259 12315 11949 11823>, + <14429 13239 12311 11954 11824>, + <14440 13243 12333 11959 11830>, + <14452 13241 12320 11961 11828>, + <14443 13243 12329 11964 11831>, + <14484 13241 12332 11968 11836>, + <14448 13263 12343 11977 11845>, + <14473 13293 12346 11988 11856>, + <14501 13300 12357 12000 11864>, + <14521 13333 12374 12015 11879>, + <14603 13373 12420 12034 11897>, + <14603 13373 12420 12034 11897>, + <14603 13373 12420 12034 11897>; + }; + + qcom,pc-temp-z2-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <9070 11213 10264 10349 10299>, + <9403 10211 10276 10386 10313>, + <9826 10116 10342 10430 10322>, + <9983 10114 10362 10447 10350>, + <9978 10115 10368 10437 10342>, + <9967 10120 10372 10407 10282>, + <9846 10126 10371 10393 10237>, + <9534 10132 10368 10388 10217>, + <9372 10137 10365 10382 10206>, + <9574 10141 10365 10378 10208>, + <9873 10143 10365 10386 10216>, + <9940 10145 10357 10384 10231>, + <9908 10147 10346 10370 10273>, + <9890 10148 10344 10357 10310>, + <9864 10149 10352 10353 10325>, + <9749 10147 10354 10353 10336>, + <9714 10144 10347 10355 10342>, + <10069 10146 10343 10360 10343>, + <10530 10156 10344 10366 10344>, + <10637 10166 10343 10378 10353>, + <10631 10154 10344 10396 10363>, + <10605 10119 10374 10405 10360>, + <10392 10103 10415 10412 10326>, + <10061 10118 10414 10414 10294>, + <9958 10135 10371 10402 10266>, + <9962 10132 10339 10387 10241>, + <9968 10117 10335 10377 10241>, + <9971 10107 10337 10360 10253>, + <9975 10109 10342 10353 10270>, + <9977 10112 10351 10373 10299>, + <9855 10116 10359 10397 10330>, + <9628 10123 10362 10398 10343>, + <9563 10131 10365 10389 10349>, + <9597 10143 10370 10392 10366>, + <9647 10159 10379 10443 10415>, + <9714 10166 10389 10499 10464>, + <9809 10169 10397 10520 10486>, + <9844 10172 10405 10533 10511>, + <9756 10186 10432 10548 10531>, + <9631 10212 10505 10586 10563>, + <9541 10225 10551 10621 10587>, + <9445 10161 10538 10637 10540>, + <9378 10144 10527 10646 10468>, + <9335 10322 10539 10611 10495>, + <9269 13378 10554 10627 10491>, + <9218 14361 10475 10629 10534>, + <9220 14794 10469 10642 10588>, + <9212 15070 10496 10651 10586>, + <9188 13785 10469 10739 10647>, + <9170 13219 10622 10694 10458>, + <9151 12652 10655 10557 10325>, + <9135 12236 10610 10495 10272>, + <9116 11644 10496 10432 10195>, + <9081 11027 10456 10300 10139>, + <9081 11027 10456 10300 10139>, + <9081 11027 10456 10300 10139>; + }; + + qcom,pc-temp-z3-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <19308 19258 19367 19369 19345>, + <19567 19611 19463 19395 19370>, + <19850 19705 19512 19411 19381>, + <19967 19740 19520 19416 19385>, + <19987 19749 19515 19414 19384>, + <19996 19735 19507 19405 19379>, + <19860 19713 19499 19400 19373>, + <19484 19698 19492 19395 19369>, + <19288 19687 19483 19391 19365>, + <19508 19679 19473 19388 19362>, + <19829 19673 19467 19382 19358>, + <19858 19667 19463 19378 19357>, + <19678 19660 19461 19372 19355>, + <19567 19648 19461 19369 19353>, + <19627 19641 19463 19369 19353>, + <19647 19646 19465 19368 19355>, + <19577 19654 19458 19367 19355>, + <19415 19653 19447 19366 19345>, + <19268 19631 19443 19365 19337>, + <19258 19613 19443 19365 19337>, + <19258 19623 19446 19366 19337>, + <19260 19652 19459 19374 19342>, + <19450 19665 19480 19393 19364>, + <19797 19666 19494 19403 19379>, + <19919 19667 19506 19402 19379>, + <19924 19671 19511 19400 19378>, + <19927 19681 19507 19400 19374>, + <19922 19686 19499 19400 19366>, + <19906 19684 19492 19399 19360>, + <19891 19680 19487 19397 19359>, + <19798 19673 19482 19393 19359>, + <19639 19661 19476 19390 19359>, + <19579 19650 19470 19386 19357>, + <19566 19644 19465 19382 19355>, + <19553 19639 19460 19380 19352>, + <19468 19636 19457 19378 19348>, + <19316 19630 19455 19375 19346>, + <19261 19624 19453 19373 19344>, + <19262 19618 19450 19371 19343>, + <19263 19609 19443 19369 19345>, + <19264 19576 19437 19368 19347>, + <19267 19367 19435 19368 19350>, + <19269 19261 19432 19367 19353>, + <19270 19260 19421 19365 19353>, + <19274 19257 19413 19361 19354>, + <19278 19257 19368 19354 19332>, + <19278 19257 19367 19346 19332>, + <19279 19257 19362 19331 19323>, + <19282 19257 19368 19326 19327>, + <19284 19257 19354 19338 19350>, + <19287 19257 19361 19346 19348>, + <19290 19257 19368 19356 19347>, + <19295 19257 19370 19353 19356>, + <19308 19258 19392 19382 19373>, + <19308 19258 19392 19382 19373>, + <19308 19258 19392 19382 19373>; + }; + + qcom,pc-temp-z4-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <16598 15992 15337 14972 14879>, + <16815 16035 15386 15059 14940>, + <16561 15923 15277 14982 14899>, + <16283 15657 15173 14901 14842>, + <15982 15436 15082 14879 14824>, + <15774 15304 15020 14868 14816>, + <15800 15207 14988 14856 14809>, + <15941 15154 14966 14843 14802>, + <16005 15119 14946 14830 14794>, + <15750 15094 14928 14818 14785>, + <15383 15076 14912 14807 14775>, + <15316 15063 14897 14797 14766>, + <15433 15048 14884 14788 14757>, + <15501 15033 14874 14778 14748>, + <15463 15025 14866 14769 14737>, + <15509 15037 14860 14760 14725>, + <15596 15057 14852 14751 14718>, + <15677 15056 14841 14742 14715>, + <15729 15002 14835 14738 14712>, + <15708 14951 14832 14736 14709>, + <15684 15017 14833 14735 14707>, + <15650 15207 14923 14756 14718>, + <15508 15302 15068 14837 14777>, + <15298 15313 15091 14879 14814>, + <15235 15319 15040 14870 14809>, + <15282 15294 14989 14855 14800>, + <15330 15200 14962 14841 14793>, + <15320 15131 14943 14826 14787>, + <15270 15105 14932 14814 14780>, + <15232 15088 14926 14805 14771>, + <15276 15076 14923 14798 14761>, + <15373 15065 14921 14794 14754>, + <15397 15057 14920 14791 14747>, + <15385 15051 14919 14789 14742>, + <15376 15043 14916 14787 14738>, + <15430 15036 14914 14786 14736>, + <15544 15016 14915 14794 14745>, + <15577 14998 14918 14811 14767>, + <15550 14991 14917 14816 14774>, + <15520 14987 14909 14811 14768>, + <15502 14998 14896 14803 14760>, + <15491 15139 14873 14788 14752>, + <15475 15211 14850 14774 14747>, + <15445 15195 14842 14774 14750>, + <15345 15130 14813 14764 14741>, + <15318 15079 14802 14736 14721>, + <15308 15066 14777 14720 14700>, + <15301 15057 14757 14705 14684>, + <15285 15045 14739 14698 14668>, + <15274 15053 14775 14717 14688>, + <15294 15076 14782 14719 14696>, + <15311 15080 14778 14712 14701>, + <15326 15091 14779 14719 14701>, + <15354 15108 14768 14706 14703>, + <15354 15108 14768 14706 14703>, + <15354 15108 14768 14706 14703>; + }; + + qcom,pc-temp-z5-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <10764 10957 12110 13794 13670>, + <11745 12925 13686 14768 14977>, + <12716 14010 14746 16056 16445>, + <13404 14718 15521 16744 17361>, + <13905 15321 16180 16789 17415>, + <14200 15933 16545 16568 17166>, + <13611 16455 16653 16420 16940>, + <11869 16730 16710 16364 16838>, + <10978 16895 16699 16401 16763>, + <12521 17062 16594 16402 16659>, + <14783 17315 16549 16292 16587>, + <15011 17507 16656 16178 16634>, + <13819 17490 16845 16003 16770>, + <13134 17527 17100 15977 16943>, + <13823 17638 17538 16159 17435>, + <14192 17626 17786 16425 18421>, + <13660 17482 17557 16723 18632>, + <12194 17384 17254 17131 17493>, + <10877 17447 17366 17305 16542>, + <10795 17704 18253 17609 16717>, + <10808 18910 18937 18108 17070>, + <10857 21136 18167 17900 17037>, + <13850 21892 16713 16569 16529>, + <19285 19957 16394 15708 16174>, + <21102 17736 16736 15560 16006>, + <20977 17560 17186 15557 15832>, + <20752 18050 17734 15845 15773>, + <20272 18693 18431 16567 15708>, + <19413 19705 19132 17289 15707>, + <18772 20743 19927 17959 16182>, + <17386 21034 20581 18611 16967>, + <15327 21059 21018 19179 17620>, + <14631 21034 21355 19699 18403>, + <14512 21133 21507 20256 19056>, + <14338 21373 21604 21000 19675>, + <13329 21460 21643 21494 20064>, + <11563 21322 21601 20994 19488>, + <10927 21163 21493 19730 18023>, + <10937 21134 21270 19156 17559>, + <10948 21040 20651 18991 17865>, + <10942 20318 20135 18929 18319>, + <10912 14582 19994 18903 18925>, + <10885 11608 19761 18788 19444>, + <10861 11587 18126 17802 18686>, + <10871 11314 17978 17266 18426>, + <10857 11130 15054 17271 15914>, + <10841 11088 15214 17078 16658>, + <10831 11067 15184 16484 17071>, + <10841 11046 15966 16365 19357>, + <10877 11142 14378 15551 19427>, + <10922 11156 14140 15626 17699>, + <10887 11109 14272 16679 16814>, + <10848 11069 14202 15606 17668>, + <10790 10995 15166 19180 19716>, + <10790 10995 15166 19180 19716>, + <10790 10995 15166 19180 19716>; + }; + + qcom,pc-temp-z6-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <17029 15901 15123 14807 14723>, + <17156 16022 15165 14844 14750>, + <17081 15990 15131 14815 14734>, + <16977 15851 15090 14780 14711>, + <16818 15720 15039 14766 14700>, + <16645 15630 15000 14756 14693>, + <16486 15560 14978 14746 14686>, + <16331 15519 14962 14737 14680>, + <16255 15490 14945 14728 14674>, + <16244 15468 14929 14720 14668>, + <16238 15452 14916 14712 14662>, + <16217 15438 14905 14704 14656>, + <16172 15422 14897 14697 14651>, + <16139 15401 14891 14691 14646>, + <16146 15390 14887 14686 14642>, + <16166 15395 14883 14681 14638>, + <16163 15403 14876 14677 14633>, + <16120 15402 14866 14672 14627>, + <16076 15372 14862 14670 14622>, + <16063 15345 14862 14670 14621>, + <16057 15380 14865 14671 14621>, + <16055 15480 14915 14684 14629>, + <16092 15533 14991 14732 14668>, + <16168 15543 15006 14757 14692>, + <16218 15549 14992 14753 14691>, + <16251 15541 14976 14746 14687>, + <16270 15511 14964 14741 14683>, + <16266 15488 14954 14735 14676>, + <16246 15479 14948 14730 14671>, + <16227 15473 14944 14726 14666>, + <16204 15467 14942 14722 14662>, + <16176 15459 14941 14719 14659>, + <16164 15454 14939 14716 14657>, + <16159 15453 14938 14715 14654>, + <16154 15453 14937 14714 14651>, + <16145 15453 14936 14714 14649>, + <16133 15450 14939 14717 14652>, + <16130 15447 14943 14725 14662>, + <16133 15449 14943 14727 14665>, + <16139 15454 14940 14725 14664>, + <16147 15454 14936 14723 14663>, + <16161 15429 14929 14718 14662>, + <16171 15417 14922 14712 14662>, + <16178 15424 14918 14713 14664>, + <16162 15408 14909 14708 14663>, + <16165 15399 14883 14694 14643>, + <16168 15398 14875 14684 14633>, + <16172 15401 14867 14670 14622>, + <16179 15405 14866 14665 14618>, + <16193 15425 14881 14682 14641>, + <16228 15451 14892 14690 14645>, + <16262 15468 14902 14695 14650>, + <16300 15497 14912 14700 14657>, + <16361 15535 14930 14716 14672>, + <16361 15535 14930 14716 14672>, + <16361 15535 14930 14716 14672>; + }; + + qcom,pc-temp-y1-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <7929 6704 6050 5566 5322 5235>, + <8028 6701 6050 5560 5320 5234>, + <8101 6693 6051 5554 5318 5233>, + <8151 6684 6051 5548 5316 5231>, + <8179 6676 6052 5543 5313 5230>, + <8186 6673 6053 5540 5311 5228>, + <8157 6667 6054 5539 5308 5225>, + <8120 6659 6054 5538 5305 5222>, + <8110 6663 6055 5536 5302 5222>, + <8104 6693 6056 5529 5299 5222>, + <8099 6717 6055 5525 5298 5222>, + <8120 6716 6050 5525 5297 5220>, + <8146 6707 6044 5526 5296 5217>, + <8147 6706 6044 5528 5295 5216>, + <8147 6707 6049 5533 5293 5217>, + <8146 6709 6052 5536 5291 5217>, + <8135 6705 6053 5534 5290 5219>, + <8119 6699 6055 5532 5288 5221>, + <8100 6700 6057 5532 5289 5221>, + <8079 6708 6062 5531 5290 5220>, + <8070 6715 6065 5531 5292 5219>, + <8070 6712 6067 5532 5294 5220>, + <8076 6706 6071 5532 5296 5222>, + <8117 6703 6071 5532 5297 5223>, + <8170 6702 6070 5532 5298 5225>, + <8167 6702 6069 5532 5299 5227>, + <8118 6700 6068 5535 5301 5229>, + <8084 6699 6065 5539 5305 5232>, + <8087 6697 6062 5540 5309 5236>, + <8100 6691 6059 5541 5311 5240>, + <8092 6688 6059 5542 5314 5243>, + <8059 6691 6063 5546 5317 5244>, + <8043 6695 6069 5550 5320 5245>, + <8027 6693 6072 5553 5324 5247>, + <8011 6677 6077 5556 5329 5251>, + <8021 6667 6080 5558 5333 5255>, + <8050 6679 6081 5563 5336 5258>, + <8082 6697 6082 5568 5339 5261>, + <8123 6698 6085 5570 5342 5263>, + <8148 6684 6094 5571 5348 5265>, + <8101 6675 6101 5572 5352 5268>, + <8041 6691 6098 5581 5353 5271>, + <8104 6707 6096 5586 5356 5275>, + <8088 6704 6102 5586 5363 5282>, + <8048 6708 6104 5593 5368 5284>, + <8055 6725 6098 5595 5370 5288>, + <8059 6724 6114 5601 5370 5288>, + <8092 6743 6089 5598 5376 5290>, + <8157 6750 6086 5605 5374 5291>, + <8197 6722 6104 5609 5381 5293>, + <8269 6738 6105 5608 5384 5292>, + <8288 6759 6112 5624 5392 5304>, + <8380 6766 6128 5643 5400 5313>, + <8422 6779 6149 5656 5417 5324>, + <8422 6779 6149 5656 5417 5324>, + <8422 6779 6149 5656 5417 5324>; + }; + + qcom,pc-temp-y2-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <9654 9643 10639 11070 11121 11086>, + <9654 9643 10662 11056 11097 11058>, + <9655 9643 10675 11037 11063 11029>, + <9655 9871 10680 11014 11027 11001>, + <9656 10190 10680 10988 10997 10976>, + <9656 10325 10677 10959 10981 10958>, + <9657 10308 10664 10918 10973 10946>, + <9657 10282 10644 10881 10967 10935>, + <9657 10301 10632 10875 10959 10916>, + <9658 10440 10623 10874 10933 10882>, + <9658 10534 10619 10874 10919 10864>, + <9658 10489 10626 10869 10936 10874>, + <9659 10417 10643 10861 10961 10888>, + <9658 10413 10676 10856 10952 10885>, + <9657 10487 10748 10851 10897 10860>, + <9657 10553 10801 10851 10866 10840>, + <9657 10580 10826 10885 10876 10837>, + <9657 10597 10843 10946 10896 10845>, + <9657 10521 10842 11018 10943 10884>, + <9656 10042 10822 11115 11060 10984>, + <9656 9696 10809 11159 11120 11034>, + <9656 9682 10815 11129 11098 11013>, + <9656 9676 10826 11091 11071 10987>, + <9656 9675 10835 11085 11079 11009>, + <9656 9676 10846 11088 11121 11106>, + <9655 9676 10848 11093 11154 11162>, + <9655 9675 10684 11108 11176 11166>, + <9655 9671 10460 11130 11199 11168>, + <9655 9668 10652 11152 11224 11182>, + <9654 9665 11565 11178 11263 11214>, + <9654 9662 12069 11192 11286 11238>, + <9654 9660 11796 11199 11310 11257>, + <9654 9659 11319 11203 11338 11277>, + <9654 9657 10963 11202 11344 11307>, + <9654 9656 10643 11198 11320 11345>, + <9654 9655 10423 11189 11299 11359>, + <9653 9654 10140 11148 11294 11325>, + <9653 9653 9828 11108 11301 11280>, + <9653 9653 9733 11099 11301 11271>, + <9653 9653 9707 11096 11290 11278>, + <9653 9652 9692 11071 11287 11277>, + <9653 9652 9681 10975 11329 11250>, + <9653 9652 9674 10939 11356 11231>, + <9653 9652 9668 10913 11303 11229>, + <9653 9652 9664 10802 11253 11135>, + <9653 9652 9663 10839 11180 11044>, + <9653 9652 9661 10832 11146 11009>, + <9652 9652 9660 10811 11105 10962>, + <9652 9651 9659 10794 11061 10965>, + <9651 9651 9658 10764 11053 10938>, + <9650 9651 9658 10711 10981 10871>, + <9650 9651 9656 10651 10927 10829>, + <9649 9651 9654 10594 10851 10747>, + <9648 9651 9654 10531 10798 10659>, + <9648 9651 9654 10531 10798 10659>, + <9648 9651 9654 10531 10798 10659>; + }; + + qcom,pc-temp-y3-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <14501 13677 13390 13309 13301 13279>, + <14412 13657 13393 13309 13294 13279>, + <14328 13634 13397 13311 13289 13279>, + <14249 13612 13400 13312 13285 13279>, + <14179 13596 13403 13314 13283 13279>, + <14117 13590 13406 13315 13282 13279>, + <14063 13594 13408 13315 13283 13280>, + <14017 13600 13410 13316 13286 13281>, + <13976 13594 13412 13317 13287 13282>, + <13939 13548 13416 13319 13287 13282>, + <13929 13515 13419 13321 13287 13282>, + <13957 13513 13421 13322 13289 13282>, + <13986 13512 13423 13323 13291 13282>, + <13945 13509 13422 13325 13291 13283>, + <13843 13504 13414 13328 13291 13284>, + <13803 13497 13407 13329 13291 13286>, + <13797 13488 13401 13328 13292 13287>, + <13793 13478 13395 13325 13294 13288>, + <13788 13470 13387 13324 13297 13290>, + <13783 13465 13376 13323 13301 13294>, + <13783 13458 13367 13322 13303 13296>, + <13788 13428 13360 13315 13297 13290>, + <13796 13384 13354 13306 13287 13281>, + <13814 13362 13349 13303 13283 13278>, + <13843 13349 13346 13300 13281 13277>, + <13874 13344 13341 13299 13280 13277>, + <13910 13351 13308 13299 13280 13277>, + <13952 13369 13266 13299 13282 13277>, + <13999 13391 13259 13298 13282 13277>, + <14052 13422 13259 13299 13283 13277>, + <14110 13460 13258 13299 13283 13277>, + <14174 13503 13258 13298 13283 13277>, + <14243 13554 13259 13298 13283 13277>, + <14318 13615 13263 13298 13283 13277>, + <14398 13690 13285 13299 13283 13278>, + <14481 13777 13302 13299 13283 13278>, + <14568 13879 13294 13296 13281 13277>, + <14658 13996 13281 13292 13279 13276>, + <14750 14118 13282 13292 13278 13276>, + <14850 14247 13299 13292 13277 13277>, + <14963 14377 13319 13293 13277 13277>, + <15082 14502 13343 13295 13277 13278>, + <15198 14624 13368 13298 13277 13278>, + <15302 14737 13402 13303 13278 13276>, + <15264 14824 13470 13304 13280 13278>, + <15439 14801 13476 13307 13284 13280>, + <15557 14824 13517 13316 13291 13286>, + <15783 14890 13560 13319 13292 13287>, + <16058 14961 13607 13332 13295 13287>, + <16423 15021 13665 13332 13292 13286>, + <16935 15095 13703 13333 13294 13286>, + <17701 15215 13779 13341 13296 13289>, + <18847 15382 13934 13350 13299 13292>, + <20636 15571 14143 13370 13308 13299>, + <20636 15571 14143 13370 13308 13299>, + <20636 15571 14143 13370 13308 13299>; + }; + + qcom,pc-temp-y4-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <17448 17305 16798 16610 16483 16470>, + <17520 17330 16862 16610 16486 16469>, + <17601 17378 16934 16609 16489 16468>, + <17679 17433 17001 16608 16491 16467>, + <17744 17479 17051 16607 16493 16467>, + <17783 17501 17070 16605 16493 16466>, + <17798 17503 17059 16603 16493 16466>, + <17813 17504 17041 16601 16492 16466>, + <17918 17511 17030 16599 16493 16466>, + <18180 17550 17023 16599 16497 16470>, + <18279 17608 17020 16599 16500 16473>, + <18148 17742 17034 16602 16502 16478>, + <17945 17902 17062 16609 16506 16483>, + <17736 17876 17086 16619 16512 16487>, + <17506 17547 17110 16638 16523 16492>, + <17399 17320 17134 16659 16535 16498>, + <17363 17344 17161 16679 16546 16506>, + <17328 17386 17183 16703 16560 16518>, + <17266 17370 17170 16748 16586 16537>, + <17193 17216 17080 16821 16630 16569>, + <17141 17060 16974 16852 16651 16585>, + <17100 16974 16865 16754 16602 16552>, + <17077 16908 16761 16616 16529 16502>, + <17070 16873 16703 16567 16502 16483>, + <17066 16851 16662 16543 16489 16473>, + <17066 16841 16647 16535 16485 16469>, + <17066 16841 16681 16535 16485 16470>, + <17067 16842 16727 16535 16487 16471>, + <17070 16843 16732 16537 16489 16474>, + <17074 16844 16721 16543 16497 16482>, + <17079 16845 16716 16549 16507 16491>, + <17088 16852 16721 16554 16521 16504>, + <17095 16866 16730 16558 16535 16515>, + <17099 16879 16732 16556 16540 16518>, + <17103 16893 16714 16549 16540 16515>, + <17111 16906 16704 16540 16534 16509>, + <17124 16920 16735 16528 16505 16492>, + <17134 16932 16784 16517 16477 16475>, + <17142 16941 16805 16517 16476 16471>, + <17149 16947 16815 16522 16479 16469>, + <17157 16950 16818 16530 16481 16469>, + <17167 16948 16818 16544 16482 16469>, + <17187 16945 16817 16555 16481 16467>, + <17208 16947 16815 16561 16471 16454>, + <17140 16965 16826 16575 16477 16456>, + <17176 16961 16849 16584 16493 16477>, + <17202 16977 16893 16606 16503 16495>, + <17281 17046 16954 16635 16528 16531>, + <17390 17107 17025 16679 16557 16532>, + <17524 17131 17054 16682 16515 16493>, + <17690 17101 17038 16673 16527 16498>, + <17978 17060 17051 16712 16548 16514>, + <18577 17063 17124 16764 16588 16554>, + <20156 17135 17255 16879 16727 16719>, + <20156 17135 17255 16879 16727 16719>, + <20156 17135 17255 16879 16727 16719>; + }; + + qcom,pc-temp-y5-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <10030 8712 14223 14774 19943 16308>, + <10448 8888 14349 15148 18667 15835>, + <10794 10562 14526 15365 17009 15457>, + <11054 12204 14713 15466 15353 15176>, + <11214 13579 14867 15489 14086 14997>, + <11260 14452 14948 15472 13593 14920>, + <11143 14948 14973 15335 13800 15003>, + <11001 15270 14986 15151 14123 15144>, + <11151 15028 14986 15098 14118 15087>, + <11850 13370 14973 15056 13826 14716>, + <12871 12246 14930 14978 13664 14315>, + <15188 13353 14287 14743 13788 13961>, + <17100 15163 13386 14398 13870 13634>, + <15786 15495 13334 14078 13643 13482>, + <12439 15197 13853 13740 13191 13549>, + <11406 14993 14346 13497 12887 13638>, + <11547 15443 14672 13207 12793 13546>, + <11662 16191 15006 12923 12796 13423>, + <11574 16138 15417 13004 13001 13548>, + <11364 14708 15994 13654 13569 14033>, + <11181 13284 16419 14434 14193 14440>, + <10986 12599 16670 15491 14905 14826>, + <10835 12068 16832 16433 15541 15160>, + <10734 11544 16827 16644 15650 15196>, + <10666 10962 16682 16591 15306 15346>, + <10655 10655 16390 16622 15048 15474>, + <10654 10648 14341 16597 15293 15494>, + <10654 10645 11728 16540 15744 15472>, + <10689 10665 11156 16578 15865 15229>, + <10734 10802 11032 16695 15749 14663>, + <10745 10946 10959 16756 15607 14352>, + <10765 11017 10901 16831 15502 14290>, + <10797 11076 10865 16959 15400 14311>, + <10882 11177 11054 17363 15705 14665>, + <10953 11367 12196 18097 16573 15740>, + <10940 11520 13011 18310 16919 16424>, + <10897 11584 12496 17269 16620 16376>, + <10863 11627 11602 15914 16091 16215>, + <10835 11630 11486 15213 15448 16327>, + <10820 11595 11681 14700 14692 16543>, + <10867 11570 11787 14330 14365 16550>, + <10955 11579 11797 14105 14243 16259>, + <11030 11596 11778 14219 14209 16346>, + <11029 11509 11647 14611 15058 16893>, + <11044 11331 11779 14198 14882 16382>, + <11143 11388 11508 14156 14882 14589>, + <11321 11488 11654 14603 16012 16142>, + <11356 11493 11662 14001 15040 14960>, + <11206 11613 11939 14918 15399 14828>, + <10932 11747 12726 15439 17093 17327>, + <10539 11665 12655 15981 17753 17255>, + <10263 11585 12280 16288 17881 17960>, + <9994 11459 12118 16141 17436 18200>, + <9668 11818 11932 16090 17352 17825>, + <9668 11818 11932 16090 17352 17825>, + <9668 11818 11932 16090 17352 17825>; + }; + + qcom,pc-temp-y6-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <7467 6132 5538 5158 5055 5027>, + <7418 6176 5550 5158 5053 5026>, + <7371 6205 5557 5158 5050 5025>, + <7326 6223 5561 5157 5048 5025>, + <7283 6232 5562 5156 5046 5025>, + <7242 6234 5562 5154 5046 5025>, + <7194 6227 5555 5152 5046 5025>, + <7159 6211 5540 5150 5047 5026>, + <7167 6191 5531 5149 5047 5027>, + <7202 6161 5522 5149 5048 5028>, + <7216 6144 5519 5149 5049 5029>, + <7195 6170 5520 5150 5051 5030>, + <7155 6214 5522 5151 5053 5031>, + <7075 6207 5523 5154 5055 5033>, + <6953 6119 5523 5160 5058 5035>, + <6899 6058 5522 5167 5061 5038>, + <6884 6060 5524 5172 5065 5041>, + <6872 6065 5527 5177 5070 5045>, + <6853 6054 5521 5188 5079 5052>, + <6834 5986 5487 5208 5095 5064>, + <6828 5923 5449 5216 5102 5070>, + <6826 5892 5413 5184 5083 5056>, + <6825 5871 5381 5138 5056 5035>, + <6839 5868 5365 5122 5045 5028>, + <6867 5872 5355 5114 5040 5024>, + <6893 5878 5349 5111 5038 5023>, + <6923 5895 5343 5112 5039 5023>, + <6956 5926 5339 5113 5040 5024>, + <6991 5960 5339 5115 5042 5026>, + <7030 5999 5342 5118 5045 5028>, + <7074 6044 5346 5121 5048 5031>, + <7122 6096 5354 5124 5053 5034>, + <7175 6156 5367 5126 5057 5038>, + <7232 6222 5383 5127 5059 5039>, + <7293 6297 5405 5127 5060 5039>, + <7357 6380 5430 5127 5058 5038>, + <7425 6470 5458 5124 5049 5032>, + <7495 6568 5491 5120 5041 5027>, + <7567 6667 5530 5121 5040 5027>, + <7643 6768 5579 5127 5041 5027>, + <7727 6867 5632 5133 5042 5028>, + <7816 6963 5689 5144 5044 5028>, + <7908 7053 5751 5155 5044 5028>, + <7994 7135 5817 5167 5043 5024>, + <7959 7206 5905 5181 5046 5026>, + <8096 7192 5921 5188 5056 5034>, + <8195 7214 5976 5205 5063 5044>, + <8412 7280 6034 5219 5072 5055>, + <8678 7350 6096 5248 5083 5055>, + <9031 7405 6155 5252 5069 5043>, + <9521 7454 6196 5257 5074 5046>, + <10251 7535 6282 5285 5084 5053>, + <11352 7666 6442 5320 5100 5069>, + <13075 7846 6646 5385 5148 5123>, + <13075 7846 6646 5385 5148 5123>, + <13075 7846 6646 5385 5148 5123>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qg-batterydata-mlp466076-3200mah.dtsi b/arch/arm/boot/dts/qcom/qg-batterydata-mlp466076-3200mah.dtsi new file mode 100644 index 000000000000..ce65243a20ae --- /dev/null +++ b/arch/arm/boot/dts/qcom/qg-batterydata-mlp466076-3200mah.dtsi @@ -0,0 +1,1044 @@ + +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,mlp466076_3200mAh { + /* mlp466076_3200mAh_averaged_MasterSlave_Sept28th2018 */ + qcom,max-voltage-uv = <4400000>; + qcom,fg-cc-cv-threshold-mv = <4390>; + qcom,fastchg-current-ma = <6000>; + qcom,batt-id-kohm = <133>; + qcom,battery-beta = <4250>; + qcom,battery-therm-kohm = <100>; + qcom,battery-type = + "mlp466076_3200mAh_averaged_MasterSlave_Sept28th2018"; + qcom,qg-batt-profile-ver = <100>; + + qcom,jeita-fcc-ranges = <0 150 650000 + 151 450 4875000 + 451 550 1625000>; + qcom,jeita-fv-ranges = <0 150 4150000 + 151 450 4400000 + 451 550 4150000>; + /* COOL = 15 DegC, WARM = 45 DegC */ + qcom,jeita-soft-thresholds = <0x4621 0x20b8>; + /* COLD = 0 DegC, HOT = 55 DegC */ + qcom,jeita-hard-thresholds = <0x58cd 0x181d>; + /* COOL hys = 18 DegC, WARM hys = 42 DegC */ + qcom,jeita-soft-hys-thresholds = <0x4206 0x23c0>; + qcom,jeita-soft-fcc-ua = <650000 1625000>; + qcom,jeita-soft-fv-uv = <4150000 4150000>; + + qcom,fcc1-temp-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-data = <3205 3248 3306 3328 3328>; + }; + + qcom,fcc2-temp-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-data = <3118 3203 3253 3314 3327 3333>; + }; + + qcom,pc-temp-v1-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <43662 43765 43827 43854 43857>, + <43465 43592 43648 43679 43680>, + <43244 43371 43441 43477 43474>, + <43004 43143 43219 43263 43254>, + <42786 42919 42991 43039 43024>, + <42603 42692 42762 42806 42790>, + <42425 42464 42530 42568 42557>, + <42215 42239 42301 42330 42326>, + <41980 42016 42073 42096 42101>, + <41759 41797 41849 41866 41875>, + <41557 41584 41627 41642 41650>, + <41362 41378 41411 41424 41428>, + <41163 41178 41202 41209 41210>, + <40961 40977 41001 40999 40999>, + <40760 40772 40799 40794 40793>, + <40563 40570 40594 40597 40597>, + <40358 40372 40396 40405 40407>, + <40145 40178 40221 40225 40226>, + <39945 40002 40053 40053 40050>, + <39789 39854 39847 39858 39853>, + <39654 39711 39576 39612 39620>, + <39531 39519 39339 39375 39391>, + <39412 39263 39176 39190 39200>, + <39282 39052 39040 39032 39031>, + <39133 38917 38919 38892 38884>, + <38984 38816 38812 38767 38758>, + <38858 38736 38712 38655 38645>, + <38756 38672 38614 38553 38541>, + <38668 38609 38524 38459 38444>, + <38595 38544 38445 38374 38354>, + <38533 38483 38374 38297 38270>, + <38475 38429 38310 38226 38195>, + <38430 38379 38253 38166 38130>, + <38401 38330 38199 38107 38067>, + <38377 38287 38153 38049 38003>, + <38346 38242 38109 37990 37936>, + <38285 38194 38057 37927 37867>, + <38212 38141 37997 37860 37794>, + <38144 38070 37923 37783 37713>, + <38069 37964 37822 37685 37612>, + <37974 37836 37698 37571 37495>, + <37837 37691 37560 37439 37359>, + <37673 37537 37406 37289 37206>, + <37502 37409 37248 37138 37064>, + <37345 37284 37128 37023 36958>, + <37238 37184 37066 36969 36904>, + <37204 37151 37050 36949 36887>, + <37171 37121 37032 36932 36873>, + <37134 37087 36999 36898 36835>, + <37025 36967 36850 36728 36642>, + <36701 36632 36509 36379 36285>, + <36239 36167 36048 35916 35824>, + <35649 35576 35460 35327 35236>, + <34852 34778 34666 34533 34443>, + <33622 33561 33462 33330 33238>, + <30000 30000 30000 30000 30000>; + }; + + qcom,pc-temp-v2-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <43390 43645 43750 43815 43800 43795>, + <42983 43258 43441 43569 43578 43582>, + <42608 42904 43149 43327 43354 43366>, + <42270 42588 42877 43089 43129 43145>, + <41961 42304 42623 42856 42904 42921>, + <41683 42042 42377 42623 42676 42694>, + <41438 41791 42134 42391 42446 42463>, + <41238 41546 41897 42160 42215 42232>, + <41062 41317 41666 41934 41987 42003>, + <40846 41113 41438 41710 41760 41775>, + <40569 40968 41219 41489 41537 41550>, + <40319 40809 41018 41270 41319 41329>, + <40103 40562 40827 41057 41104 41111>, + <39844 40259 40633 40856 40895 40900>, + <39546 39953 40421 40658 40689 40693>, + <39304 39745 40200 40455 40490 40494>, + <39117 39574 39983 40245 40297 40302>, + <38956 39378 39768 40043 40107 40114>, + <38793 39156 39546 39861 39925 39933>, + <38644 38938 39315 39676 39735 39743>, + <38519 38742 39102 39446 39499 39505>, + <38411 38566 38911 39183 39234 39243>, + <38324 38421 38746 38973 39029 39041>, + <38257 38302 38600 38817 38875 38887>, + <38199 38211 38469 38683 38741 38752>, + <38146 38145 38351 38560 38617 38628>, + <38098 38091 38245 38450 38505 38515>, + <38052 38045 38150 38347 38400 38409>, + <38006 38004 38065 38253 38304 38311>, + <37961 37964 37993 38163 38214 38219>, + <37916 37925 37937 38080 38133 38135>, + <37869 37885 37889 38001 38057 38057>, + <37819 37842 37844 37926 37987 37985>, + <37765 37793 37800 37855 37919 37914>, + <37706 37743 37753 37784 37834 37819>, + <37641 37692 37702 37716 37722 37690>, + <37572 37633 37642 37647 37608 37564>, + <37495 37562 37573 37569 37511 37461>, + <37414 37476 37492 37486 37421 37368>, + <37330 37382 37399 37399 37334 37278>, + <37241 37277 37290 37309 37247 37186>, + <37150 37164 37167 37199 37139 37073>, + <37061 37043 37037 37065 37012 36948>, + <36974 36929 36917 36918 36864 36803>, + <36874 36836 36835 36850 36812 36762>, + <36760 36750 36766 36819 36788 36738>, + <36690 36703 36735 36797 36767 36721>, + <36594 36645 36672 36765 36742 36693>, + <36441 36551 36563 36683 36669 36598>, + <36215 36353 36313 36466 36433 36312>, + <35901 36016 35927 36050 36018 35886>, + <35430 35532 35419 35522 35495 35356>, + <34781 34891 34751 34850 34822 34674>, + <33883 34005 33839 33929 33926 33799>, + <32534 32590 32567 32727 32712 32584>, + <30011 30004 30001 30000 30000 29999>; + }; + + qcom,pc-temp-z1-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <13336 12737 12245 12063 12028>, + <13321 12715 12202 12029 11977>, + <13325 12709 12216 11985 11908>, + <13384 12694 12186 11976 11728>, + <13496 12676 12160 11969 11639>, + <13923 12659 12154 11893 11631>, + <14348 12649 12151 11776 11626>, + <14398 12645 12146 11753 11623>, + <14405 12639 12138 11752 11620>, + <14400 12606 12131 11751 11617>, + <14362 12571 12127 11749 11615>, + <14304 12567 12126 11745 11614>, + <14258 12571 12126 11742 11613>, + <14214 12572 12126 11740 11610>, + <14183 12588 12124 11738 11609>, + <14141 12697 12117 11737 11609>, + <14075 12810 12113 11737 11609>, + <14011 12906 12116 11737 11610>, + <13963 12974 12123 11738 11610>, + <13946 12991 12124 11740 11610>, + <13939 12997 12122 11742 11610>, + <13933 12991 12120 11744 11612>, + <13934 12994 12127 11747 11614>, + <13946 13005 12137 11750 11617>, + <13955 13003 12140 11754 11620>, + <13948 12997 12140 11759 11622>, + <13954 12995 12141 11762 11626>, + <13959 12996 12143 11764 11629>, + <13950 12997 12146 11765 11633>, + <13956 13000 12149 11768 11637>, + <13993 13006 12155 11775 11641>, + <14015 13018 12157 11780 11645>, + <14022 13035 12158 11783 11649>, + <14016 13041 12160 11786 11653>, + <14003 13041 12168 11789 11656>, + <13991 13044 12179 11793 11660>, + <13999 13058 12183 11799 11664>, + <14034 13080 12184 11809 11669>, + <14066 13093 12185 11817 11674>, + <14095 13109 12200 11820 11679>, + <14119 13123 12216 11822 11684>, + <14122 13124 12214 11823 11687>, + <14096 13124 12204 11830 11690>, + <14077 13123 12206 11831 11693>, + <14091 13131 12216 11832 11695>, + <14132 13134 12220 11839 11701>, + <14111 13151 12226 11842 11703>, + <14099 13131 12231 11845 11707>, + <14137 13170 12238 11848 11710>, + <14113 13167 12233 11864 11717>, + <14164 13173 12257 11862 11720>, + <14159 13211 12252 11883 11727>, + <14137 13247 12286 11882 11736>, + <14149 13284 12290 11888 11745>, + <14149 13284 12290 11888 11745>, + <14149 13284 12290 11888 11745>; + }; + + qcom,pc-temp-z2-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <9618 9833 10273 10587 10613>, + <9717 10071 10235 10423 10322>, + <9767 10199 10360 10416 10359>, + <10027 10256 10382 10432 10417>, + <10146 10256 10391 10426 10403>, + <9854 10234 10380 10416 10359>, + <9540 10218 10359 10403 10313>, + <9614 10214 10345 10400 10300>, + <9875 10209 10334 10415 10313>, + <9964 10204 10329 10423 10330>, + <9958 10204 10339 10396 10336>, + <9950 10208 10353 10348 10338>, + <9946 10211 10359 10338 10339>, + <9943 10216 10362 10358 10338>, + <9910 10210 10368 10373 10337>, + <9742 10146 10380 10369 10343>, + <9638 10109 10390 10356 10357>, + <9760 10123 10389 10353 10377>, + <9935 10139 10383 10357 10397>, + <9965 10142 10386 10365 10410>, + <9980 10142 10400 10404 10416>, + <10008 10144 10410 10463 10423>, + <9880 10150 10391 10527 10467>, + <9720 10157 10363 10588 10536>, + <9779 10171 10371 10588 10530>, + <9972 10186 10419 10538 10402>, + <10034 10188 10442 10493 10311>, + <10027 10183 10423 10474 10309>, + <10024 10181 10403 10462 10323>, + <10022 10188 10403 10460 10329>, + <10021 10197 10406 10460 10328>, + <10020 10201 10411 10461 10334>, + <10019 10205 10425 10482 10364>, + <9912 10208 10438 10519 10399>, + <9718 10212 10445 10557 10436>, + <9686 10216 10450 10599 10488>, + <9872 10220 10457 10630 10512>, + <10038 10226 10465 10653 10510>, + <9970 10229 10473 10670 10510>, + <9661 10232 10488 10685 10521>, + <9424 10234 10501 10695 10542>, + <9380 10229 10497 10686 10581>, + <9360 10221 10485 10657 10635>, + <9344 10401 10482 10661 10609>, + <9319 11186 10491 10661 10585>, + <9305 13142 10504 10625 10613>, + <9304 13559 10476 10620 10613>, + <9293 12008 10464 10612 10648>, + <9279 11863 10466 10654 10747>, + <9266 12115 10555 10704 10597>, + <9244 11992 10590 10647 10489>, + <9219 10653 10578 10583 10440>, + <9180 10297 10596 10530 10382>, + <9154 9949 10524 10471 10317>, + <9154 9949 10524 10471 10317>, + <9154 9949 10524 10471 10317>; + }; + + qcom,pc-temp-z3-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <19375 19363 19375 19346 19348>, + <19394 19375 19412 19383 19378>, + <19468 19500 19455 19415 19392>, + <19623 19565 19476 19435 19361>, + <19700 19580 19486 19440 19348>, + <19658 19588 19489 19420 19361>, + <19609 19591 19491 19387 19372>, + <19662 19591 19490 19383 19370>, + <19814 19591 19488 19389 19364>, + <19862 19588 19485 19390 19359>, + <19847 19579 19478 19384 19358>, + <19826 19569 19471 19377 19357>, + <19811 19561 19468 19374 19357>, + <19800 19556 19465 19374 19356>, + <19764 19563 19463 19374 19354>, + <19601 19599 19463 19372 19350>, + <19493 19623 19463 19370 19346>, + <19603 19630 19460 19369 19343>, + <19740 19634 19456 19368 19342>, + <19729 19629 19457 19367 19342>, + <19717 19622 19467 19370 19344>, + <19700 19624 19473 19373 19349>, + <19575 19644 19462 19377 19360>, + <19507 19655 19447 19383 19375>, + <19642 19654 19449 19389 19380>, + <19829 19652 19464 19402 19380>, + <19889 19647 19475 19411 19380>, + <19884 19641 19480 19408 19376>, + <19880 19639 19483 19403 19371>, + <19873 19638 19481 19398 19368>, + <19863 19638 19475 19393 19365>, + <19854 19636 19471 19388 19362>, + <19843 19634 19468 19385 19358>, + <19752 19632 19465 19381 19355>, + <19596 19631 19462 19379 19352>, + <19561 19629 19459 19378 19349>, + <19674 19626 19457 19377 19348>, + <19773 19619 19455 19377 19347>, + <19709 19612 19453 19377 19346>, + <19460 19605 19449 19376 19347>, + <19282 19598 19443 19373 19349>, + <19273 19594 19440 19370 19351>, + <19274 19589 19438 19367 19354>, + <19274 19383 19434 19366 19352>, + <19275 19258 19424 19363 19345>, + <19276 19257 19403 19344 19332>, + <19276 19257 19383 19344 19331>, + <19277 19258 19361 19345 19324>, + <19278 19258 19366 19342 19319>, + <19279 19258 19361 19347 19341>, + <19281 19258 19350 19351 19347>, + <19284 19259 19346 19357 19349>, + <19291 19260 19336 19360 19351>, + <19296 19262 19330 19362 19356>, + <19296 19262 19330 19362 19356>, + <19296 19262 19330 19362 19356>; + }; + + qcom,pc-temp-z4-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <15630 15273 15043 14960 14945>, + <15689 15382 15065 14963 14961>, + <15723 15346 15157 15020 14973>, + <15654 15257 15080 15001 14877>, + <15621 15154 14988 14931 14792>, + <15743 15055 14927 14858 14759>, + <15853 14981 14873 14788 14737>, + <15756 14922 14829 14752 14722>, + <15538 14876 14792 14733 14715>, + <15404 14844 14769 14721 14709>, + <15340 14819 14759 14716 14702>, + <15293 14799 14752 14713 14694>, + <15250 14783 14746 14708 14686>, + <15214 14773 14740 14701 14680>, + <15227 14774 14739 14695 14676>, + <15369 14801 14741 14692 14673>, + <15468 14820 14744 14690 14671>, + <15361 14830 14738 14688 14670>, + <15201 14832 14727 14685 14667>, + <15170 14815 14736 14690 14675>, + <15151 14789 14815 14750 14721>, + <15127 14804 14877 14806 14764>, + <15219 14885 14892 14809 14763>, + <15278 14938 14900 14802 14751>, + <15140 14940 14888 14791 14740>, + <14941 14935 14845 14762 14727>, + <14880 14921 14812 14737 14714>, + <14888 14894 14794 14726 14706>, + <14891 14871 14782 14720 14700>, + <14891 14857 14780 14716 14695>, + <14888 14844 14779 14715 14691>, + <14884 14834 14779 14714 14689>, + <14879 14825 14781 14714 14688>, + <14953 14818 14783 14714 14687>, + <15095 14813 14783 14718 14692>, + <15118 14807 14782 14727 14704>, + <14978 14801 14782 14731 14709>, + <14853 14795 14780 14732 14711>, + <14902 14789 14778 14733 14711>, + <15140 14785 14771 14729 14708>, + <15315 14780 14761 14722 14703>, + <15314 14769 14752 14717 14701>, + <15291 14758 14742 14712 14699>, + <15259 14934 14730 14706 14695>, + <15156 15013 14704 14693 14685>, + <15078 14949 14666 14661 14654>, + <15075 14945 14675 14647 14643>, + <15071 14942 14689 14634 14634>, + <15063 14935 14681 14635 14635>, + <15049 14927 14694 14647 14637>, + <15057 14938 14712 14649 14640>, + <15071 14942 14718 14646 14641>, + <15084 14949 14731 14644 14640>, + <15105 14958 14742 14645 14638>, + <15105 14958 14742 14645 14638>, + <15105 14958 14742 14645 14638>; + }; + + qcom,pc-temp-z5-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <12124 12072 13157 13174 13606>, + <12994 13000 14804 15085 15154>, + <13587 14583 15791 16396 16870>, + <13874 15964 16772 16919 15801>, + <13884 16939 17839 17371 16041>, + <13288 17849 18811 17290 17992>, + <12752 18889 19806 17211 20051>, + <13155 20252 21035 17957 20337>, + <14211 21670 22602 19862 19980>, + <14723 22477 23646 20935 19733>, + <14736 22953 24200 20677 20042>, + <14649 23096 24568 19994 20872>, + <14721 23386 24733 19863 21792>, + <14828 23940 25087 20680 22627>, + <14648 25256 25600 21530 22979>, + <13383 26083 27040 21835 22568>, + <12564 25447 28188 22062 21924>, + <14450 24954 27982 22511 21937>, + <16825 25408 27494 23231 22542>, + <16732 25757 28143 23429 22575>, + <16303 26250 33310 22605 21080>, + <15711 28817 36779 21685 19879>, + <13993 36697 31028 20502 19380>, + <16429 41291 22626 18349 18894>, + <23300 39174 21659 17982 18992>, + <29454 35310 22858 20629 20165>, + <31867 32664 24466 23458 21295>, + <32326 30650 27410 25252 22111>, + <32352 30008 30586 26767 23020>, + <31698 30713 32388 28065 24313>, + <30597 31769 33715 29167 26079>, + <29641 32615 34902 30229 27629>, + <28570 33593 36165 31554 29266>, + <25166 34668 36865 32469 30251>, + <20184 36022 36864 32454 29500>, + <18967 36995 36786 32263 28117>, + <21737 37027 36538 32001 27361>, + <24117 36857 35657 31514 25956>, + <22175 36546 34649 30833 24906>, + <15699 35485 33710 29804 25141>, + <11242 34238 32735 28436 25578>, + <10985 33611 31645 26834 26096>, + <10984 32850 30651 25139 26981>, + <10998 19087 30705 25214 25567>, + <11145 11243 30585 25077 23501>, + <11257 11255 29211 23396 23355>, + <11216 11222 22088 26638 26212>, + <11217 11211 16895 30416 25864>, + <11223 11229 17933 28658 22675>, + <11260 11323 17117 24401 28538>, + <11268 11309 15536 23343 28235>, + <11186 11276 14888 24817 26689>, + <11117 11246 13952 24826 26557>, + <11073 11186 13396 24230 27076>, + <11073 11186 13396 24230 27076>, + <11073 11186 13396 24230 27076>; + }; + + qcom,pc-temp-z6-lut { + qcom,lut-col-legend = <0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200>, + <9000 8800 8600 8400 8200>, + <8000 7800 7600 7400 7200>, + <7000 6800 6600 6400 6200>, + <6000 5800 5600 5400 5200>, + <5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200>, + <3000 2800 2600 2400 2200>, + <2000 1800 1600 1400 1200>, + <1000 900 800 700 600>, + <500 400 300 200 100>, + <0>; + qcom,lut-data = <16016 15401 15028 14870 14848>, + <15996 15430 15032 14874 14857>, + <16013 15428 15075 14902 14845>, + <16033 15402 15037 14897 14721>, + <16086 15344 14991 14863 14651>, + <16361 15274 14956 14789 14644>, + <16617 15223 14923 14701 14637>, + <16582 15181 14896 14678 14629>, + <16509 15146 14871 14671 14622>, + <16437 15116 14854 14665 14616>, + <16363 15091 14843 14658 14611>, + <16293 15068 14836 14652 14607>, + <16231 15048 14830 14648 14603>, + <16173 15033 14826 14645 14600>, + <16114 15039 14823 14642 14596>, + <16055 15104 14821 14639 14593>, + <16013 15166 14819 14636 14590>, + <15987 15206 14815 14635 14588>, + <15960 15231 14810 14633 14587>, + <15927 15226 14815 14636 14590>, + <15890 15215 14856 14663 14611>, + <15856 15224 14886 14690 14632>, + <15831 15272 14888 14694 14639>, + <15823 15302 14886 14695 14642>, + <15833 15304 14882 14695 14642>, + <15847 15302 14874 14690 14637>, + <15856 15296 14868 14684 14631>, + <15863 15284 14864 14679 14625>, + <15866 15276 14862 14675 14621>, + <15866 15272 14861 14671 14617>, + <15865 15269 14859 14668 14615>, + <15862 15267 14859 14666 14613>, + <15859 15265 14860 14665 14610>, + <15852 15265 14861 14664 14609>, + <15844 15268 14863 14666 14610>, + <15842 15271 14865 14670 14614>, + <15848 15272 14866 14673 14617>, + <15853 15272 14868 14675 14618>, + <15851 15272 14869 14676 14618>, + <15844 15275 14867 14675 14618>, + <15839 15279 14864 14672 14617>, + <15842 15282 14863 14669 14618>, + <15846 15284 14862 14667 14620>, + <15845 15274 14860 14666 14618>, + <15825 15253 14851 14661 14611>, + <15802 15242 14830 14638 14592>, + <15802 15243 14825 14633 14586>, + <15804 15246 14823 14629 14579>, + <15809 15251 14826 14629 14578>, + <15817 15257 14834 14638 14591>, + <15831 15272 14842 14644 14598>, + <15851 15287 14848 14648 14600>, + <15875 15306 14857 14652 14603>, + <15910 15332 14869 14657 14608>, + <15910 15332 14869 14657 14608>, + <15910 15332 14869 14657 14608>; + }; + + qcom,pc-temp-y1-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <7469 6760 6042 5497 5274 5198>, + <7455 6707 6039 5495 5279 5198>, + <7446 6674 6036 5493 5282 5198>, + <7441 6657 6033 5492 5283 5196>, + <7439 6651 6030 5492 5282 5194>, + <7438 6650 6029 5492 5281 5191>, + <7435 6671 6029 5490 5278 5188>, + <7457 6694 6031 5488 5274 5184>, + <7493 6691 6032 5488 5271 5182>, + <7523 6673 6036 5489 5269 5179>, + <7534 6667 6039 5489 5266 5178>, + <7533 6670 6042 5486 5262 5176>, + <7509 6674 6043 5484 5260 5175>, + <7462 6673 6041 5488 5259 5174>, + <7430 6668 6043 5496 5258 5173>, + <7429 6670 6047 5497 5257 5173>, + <7440 6686 6046 5494 5255 5172>, + <7451 6697 6045 5491 5254 5172>, + <7461 6689 6051 5490 5254 5171>, + <7470 6688 6064 5489 5254 5171>, + <7467 6709 6073 5490 5254 5172>, + <7453 6738 6074 5493 5256 5173>, + <7447 6737 6069 5494 5257 5174>, + <7466 6706 6057 5493 5258 5174>, + <7488 6684 6045 5492 5259 5175>, + <7488 6689 6045 5497 5260 5176>, + <7479 6704 6053 5504 5261 5179>, + <7481 6706 6065 5507 5263 5180>, + <7480 6690 6067 5505 5266 5180>, + <7474 6678 6068 5504 5269 5181>, + <7470 6685 6071 5506 5271 5183>, + <7475 6700 6068 5510 5272 5186>, + <7487 6701 6058 5510 5274 5188>, + <7506 6693 6054 5511 5278 5190>, + <7505 6688 6053 5514 5282 5193>, + <7479 6697 6054 5525 5287 5196>, + <7461 6709 6058 5534 5290 5198>, + <7474 6706 6065 5532 5290 5201>, + <7509 6692 6071 5525 5289 5204>, + <7535 6679 6068 5523 5290 5206>, + <7557 6670 6052 5530 5294 5207>, + <7562 6667 6053 5530 5299 5210>, + <7500 6668 6060 5522 5304 5215>, + <7457 6704 6072 5530 5307 5216>, + <7452 6712 6072 5531 5305 5219>, + <7456 6691 6057 5530 5309 5222>, + <7457 6715 6070 5540 5311 5222>, + <7463 6729 6073 5535 5310 5225>, + <7518 6729 6079 5539 5324 5221>, + <7582 6694 6086 5548 5318 5222>, + <7580 6700 6062 5567 5316 5228>, + <7670 6739 6071 5571 5325 5234>, + <7673 6736 6087 5567 5337 5241>, + <7747 6806 6107 5572 5339 5245>, + <7747 6806 6107 5572 5339 5245>, + <7747 6806 6107 5572 5339 5245>; + }; + + qcom,pc-temp-y2-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <9654 9670 10551 11010 11144 11132>, + <9654 9664 10572 11003 11122 11113>, + <9654 9666 10596 10986 11100 11091>, + <9655 9674 10618 10965 11080 11067>, + <9655 9685 10634 10947 11062 11042>, + <9655 9700 10639 10938 11050 11014>, + <9655 9826 10635 10918 11042 10979>, + <9655 9962 10629 10897 11034 10951>, + <9656 9921 10625 10894 11006 10941>, + <9656 9908 10620 10889 10959 10936>, + <9655 10020 10617 10888 10942 10937>, + <9655 10154 10637 10888 10942 10942>, + <9656 10128 10673 10889 10944 10946>, + <9655 9942 10721 10887 10956 10950>, + <9655 9749 10784 10886 10981 10953>, + <9655 9706 10811 10900 11006 10948>, + <9655 9705 10823 10951 11037 10930>, + <9655 9700 10828 11000 11067 10930>, + <9655 9692 10813 11041 11113 11023>, + <9655 9685 10791 11070 11148 11118>, + <9655 9680 10790 11066 11141 11127>, + <9655 9676 10807 11047 11122 11129>, + <9655 9674 10824 11039 11127 11139>, + <9654 9674 10780 11055 11159 11171>, + <9654 9673 10518 11070 11188 11189>, + <9654 9671 10349 11080 11202 11180>, + <9654 9669 10440 11101 11206 11175>, + <9654 9666 10556 11106 11215 11189>, + <9654 9665 10441 11109 11252 11206>, + <9654 9663 10297 11110 11284 11234>, + <9654 9661 10243 11114 11292 11309>, + <9654 9660 10211 11117 11300 11366>, + <9654 9659 10170 11102 11321 11364>, + <9654 9657 10101 11060 11352 11337>, + <9654 9656 9980 11044 11359 11314>, + <9654 9656 9877 11079 11336 11289>, + <9654 9655 9821 11113 11306 11280>, + <9654 9654 9774 11098 11289 11291>, + <9654 9654 9727 11051 11276 11300>, + <9654 9654 9699 11010 11276 11302>, + <9654 9654 9686 10969 11341 11310>, + <9654 9653 9680 10925 11388 11308>, + <9654 9653 9674 10873 11365 11311>, + <9654 9653 9668 10788 11287 11336>, + <9653 9653 9665 10704 11273 11333>, + <9653 9653 9663 10732 11295 11236>, + <9653 9653 9662 10795 11303 11164>, + <9653 9653 9661 10797 11232 11154>, + <9653 9653 9660 10768 11213 11165>, + <9652 9653 9659 10741 11214 11105>, + <9651 9653 9658 10661 11159 11059>, + <9650 9652 9657 10616 11088 11003>, + <9650 9651 9656 10566 10982 10904>, + <9648 9650 9655 10519 10871 10771>, + <9648 9650 9655 10519 10871 10771>, + <9648 9650 9655 10519 10871 10771>; + }; + + qcom,pc-temp-y3-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <14894 13675 13387 13307 13288 13282>, + <14761 13671 13390 13308 13286 13280>, + <14612 13660 13393 13309 13284 13279>, + <14466 13645 13396 13310 13283 13278>, + <14339 13628 13399 13311 13282 13278>, + <14251 13610 13402 13312 13282 13278>, + <14211 13592 13404 13313 13283 13278>, + <14196 13568 13406 13313 13284 13279>, + <14179 13541 13408 13314 13284 13279>, + <14129 13512 13411 13315 13283 13280>, + <14073 13500 13412 13316 13283 13280>, + <14057 13502 13412 13316 13285 13281>, + <14063 13505 13412 13317 13287 13281>, + <14032 13507 13410 13317 13288 13280>, + <13973 13505 13404 13318 13290 13280>, + <13957 13504 13396 13318 13290 13280>, + <13957 13504 13389 13319 13291 13282>, + <13959 13496 13381 13319 13291 13284>, + <13962 13479 13372 13318 13293 13287>, + <13967 13456 13362 13315 13295 13288>, + <13982 13429 13355 13311 13292 13285>, + <14014 13403 13350 13305 13285 13279>, + <14050 13387 13346 13301 13283 13277>, + <14095 13378 13340 13298 13282 13277>, + <14145 13378 13330 13297 13282 13277>, + <14193 13390 13318 13296 13281 13276>, + <14243 13411 13306 13296 13279 13276>, + <14295 13435 13293 13296 13279 13276>, + <14353 13462 13273 13296 13279 13276>, + <14413 13494 13260 13295 13280 13276>, + <14474 13533 13260 13295 13280 13275>, + <14537 13580 13261 13294 13281 13275>, + <14602 13634 13261 13294 13281 13276>, + <14670 13695 13261 13293 13282 13276>, + <14736 13767 13264 13293 13282 13276>, + <14799 13851 13282 13294 13280 13276>, + <14862 13945 13312 13294 13279 13275>, + <14926 14048 13331 13291 13279 13275>, + <14990 14162 13335 13284 13279 13275>, + <15053 14281 13336 13283 13278 13275>, + <15115 14406 13343 13290 13278 13275>, + <15180 14531 13361 13293 13278 13275>, + <15247 14652 13395 13294 13277 13275>, + <15325 14760 13446 13296 13277 13274>, + <15372 14809 13489 13296 13278 13275>, + <15544 14923 13525 13303 13280 13277>, + <15659 14973 13563 13309 13281 13280>, + <15786 14998 13617 13315 13286 13283>, + <15982 14992 13666 13319 13288 13283>, + <16341 15053 13698 13323 13286 13281>, + <16796 15132 13761 13324 13287 13281>, + <17451 15263 13864 13331 13289 13283>, + <18369 15740 13993 13343 13291 13285>, + <19582 16580 14194 13360 13296 13288>, + <19582 16580 14194 13360 13296 13288>, + <19582 16580 14194 13360 13296 13288>; + }; + + qcom,pc-temp-y4-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <17253 17133 16743 16577 16480 16460>, + <17386 17231 16792 16587 16483 16461>, + <17568 17323 16861 16596 16486 16461>, + <17760 17403 16932 16602 16488 16461>, + <17920 17464 16989 16607 16489 16461>, + <18007 17499 17012 16608 16489 16461>, + <18009 17502 17012 16606 16488 16461>, + <17988 17500 17010 16602 16487 16462>, + <17999 17543 17006 16600 16488 16463>, + <18041 17680 16996 16599 16491 16465>, + <17967 17812 16989 16599 16494 16467>, + <17844 17840 17026 16601 16497 16469>, + <17736 17724 17085 16607 16500 16472>, + <17602 17539 17128 16618 16505 16479>, + <17436 17339 17166 16635 16511 16487>, + <17320 17297 17151 16652 16520 16495>, + <17244 17301 17110 16668 16534 16503>, + <17191 17252 17064 16689 16553 16515>, + <17124 17151 17004 16737 16591 16542>, + <17061 17040 16905 16780 16622 16564>, + <17025 16955 16810 16741 16596 16545>, + <17000 16890 16734 16612 16522 16494>, + <16985 16845 16684 16548 16487 16471>, + <16978 16817 16665 16531 16476 16462>, + <16977 16803 16663 16522 16471 16460>, + <16983 16798 16662 16519 16472 16460>, + <16991 16794 16658 16518 16474 16461>, + <17001 16792 16662 16518 16477 16464>, + <17010 16794 16686 16521 16481 16468>, + <17020 16799 16701 16525 16486 16473>, + <17027 16808 16700 16529 16495 16481>, + <17033 16819 16703 16532 16507 16490>, + <17039 16831 16711 16532 16521 16502>, + <17046 16844 16721 16528 16536 16513>, + <17054 16856 16725 16523 16536 16511>, + <17064 16874 16716 16507 16502 16483>, + <17071 16892 16701 16493 16470 16463>, + <17073 16896 16700 16494 16460 16460>, + <17074 16895 16718 16497 16455 16458>, + <17078 16898 16740 16501 16456 16458>, + <17086 16907 16756 16509 16461 16460>, + <17100 16916 16766 16520 16461 16457>, + <17127 16927 16777 16533 16464 16458>, + <17151 16945 16788 16535 16451 16440>, + <17171 16968 16822 16535 16453 16444>, + <17277 17044 16856 16576 16475 16464>, + <17341 17101 16922 16610 16490 16483>, + <17410 17129 16953 16651 16514 16518>, + <17486 17107 17015 16692 16536 16519>, + <17605 17116 17023 16691 16503 16472>, + <17753 17101 17030 16669 16495 16475>, + <17998 17092 17063 16706 16514 16494>, + <18444 17292 17132 16776 16554 16536>, + <19473 17868 17327 16903 16672 16712>, + <19473 17868 17327 16903 16672 16712>, + <19473 17868 17327 16903 16672 16712>; + }; + + qcom,pc-temp-y5-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <10911 10298 14213 16701 17755 21052>, + <10898 10547 14445 16766 17305 19443>, + <10949 10923 14667 16781 16536 18148>, + <11030 11360 14873 16758 15705 17155>, + <11105 11790 15060 16708 15066 16451>, + <11140 12156 15225 16638 14868 16040>, + <11427 12622 15397 16476 14926 16016>, + <12770 12870 15521 16320 14987 16092>, + <13889 12496 15526 16267 14730 15883>, + <13648 12382 15474 16192 14147 15511>, + <12823 13043 15351 16067 14037 15384>, + <13350 13999 14703 15767 14366 15172>, + <14369 14322 14084 15374 14619 14868>, + <13835 13655 14198 14817 14642 14286>, + <12387 13207 14689 14237 14597 13690>, + <11862 13518 15158 14092 14432 13665>, + <11843 14013 15618 14088 14125 13889>, + <11872 14061 16032 14147 14029 14160>, + <11697 13724 16290 14567 14307 14509>, + <11496 13360 16491 15286 14746 14893>, + <11296 12874 16629 16221 15422 15320>, + <11018 12157 16685 17422 16386 15876>, + <10915 11509 16661 17766 16912 16362>, + <10937 11055 16364 17245 17282 17294>, + <10949 10862 15125 16788 17482 17704>, + <10928 10863 14139 16796 17047 17507>, + <10893 10892 13688 16847 16257 17185>, + <10862 10972 13103 16906 15960 16859>, + <10846 11049 11861 16955 16035 16391>, + <10863 11085 11085 16970 16245 16032>, + <10920 11156 11094 16960 16494 15813>, + <11002 11238 11065 16985 16807 15733>, + <11078 11244 11007 17138 17386 15954>, + <11131 11221 10960 17460 18188 16486>, + <11133 11274 11023 17775 18436 17083>, + <11097 11459 11423 18423 18423 17731>, + <11069 11605 11910 18965 18423 18211>, + <11060 11618 12071 17553 19122 18678>, + <11055 11604 12039 14324 19839 19105>, + <11037 11603 11978 13643 19020 19029>, + <11002 11612 11919 15021 17826 18387>, + <10971 11599 11823 15233 17990 17895>, + <10972 11465 11745 14656 16514 17780>, + <11158 11428 11876 14911 18206 19748>, + <11212 11498 11959 14662 17928 18323>, + <11369 11538 11852 15035 16485 16557>, + <11571 11627 12089 15093 15314 16819>, + <11625 11902 12653 15141 16476 16374>, + <11579 12519 13295 14848 16431 16247>, + <11380 12618 13272 15759 17268 17871>, + <11028 12392 13194 15990 18549 17841>, + <10501 11978 13207 15787 18547 18581>, + <10084 11290 12982 15884 18113 18317>, + <9775 10649 12845 16062 18034 18316>, + <9775 10649 12845 16062 18034 18316>, + <9775 10649 12845 16062 18034 18316>; + }; + + qcom,pc-temp-y6-lut { + qcom,lut-col-legend = <(-10) 0 10 25 40 50>; + qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, + <8800 8600 8400 8200 8000 7800>, + <7600 7400 7200 7000 6800 6600>, + <6400 6200 6000 5800 5600 5400>, + <5200 5000 4800 4600 4400 4200>, + <4000 3800 3600 3400 3200 3000>, + <2800 2600 2400 2200 2000 1800>, + <1600 1400 1200 1000 900 800>, + <700 600 500 400 300 200>, + <100 0>; + qcom,lut-data = <7509 6257 5552 5162 5046 5022>, + <7463 6254 5559 5162 5046 5021>, + <7413 6247 5566 5163 5045 5020>, + <7363 6237 5570 5163 5044 5019>, + <7317 6225 5572 5162 5044 5018>, + <7278 6214 5572 5162 5043 5018>, + <7243 6201 5566 5160 5043 5018>, + <7222 6185 5556 5157 5042 5019>, + <7224 6169 5548 5155 5042 5019>, + <7201 6173 5539 5153 5042 5020>, + <7139 6196 5532 5152 5042 5020>, + <7087 6209 5536 5152 5044 5021>, + <7056 6178 5547 5152 5046 5022>, + <6999 6115 5554 5154 5048 5024>, + <6917 6048 5556 5158 5050 5025>, + <6873 6034 5546 5163 5053 5028>, + <6851 6036 5529 5167 5057 5031>, + <6842 6018 5510 5173 5063 5036>, + <6825 5983 5485 5185 5075 5045>, + <6811 5944 5450 5195 5085 5053>, + <6818 5914 5419 5182 5075 5045>, + <6840 5894 5395 5141 5049 5026>, + <6866 5889 5380 5120 5037 5018>, + <6900 5891 5370 5113 5033 5015>, + <6939 5897 5361 5110 5032 5014>, + <6977 5914 5357 5110 5032 5014>, + <7015 5942 5356 5110 5032 5015>, + <7055 5972 5354 5110 5032 5015>, + <7098 6006 5353 5112 5034 5016>, + <7142 6046 5355 5114 5036 5018>, + <7189 6091 5362 5117 5039 5020>, + <7238 6142 5372 5119 5043 5023>, + <7287 6197 5384 5120 5048 5027>, + <7337 6258 5398 5120 5054 5031>, + <7385 6325 5416 5120 5054 5030>, + <7432 6399 5439 5119 5044 5022>, + <7479 6479 5466 5117 5034 5017>, + <7525 6560 5497 5117 5032 5016>, + <7573 6645 5535 5117 5031 5016>, + <7622 6734 5578 5119 5031 5016>, + <7671 6829 5627 5130 5033 5017>, + <7725 6923 5681 5142 5034 5016>, + <7782 7014 5743 5151 5035 5017>, + <7845 7098 5815 5160 5032 5012>, + <7891 7143 5876 5164 5035 5014>, + <8048 7251 5926 5190 5043 5022>, + <8152 7306 5983 5210 5048 5029>, + <8272 7333 6038 5233 5060 5042>, + <8457 7327 6100 5254 5067 5042>, + <8797 7374 6135 5262 5057 5027>, + <9221 7430 6200 5263 5056 5028>, + <9832 7529 6307 5294 5065 5036>, + <10714 7994 6439 5339 5079 5051>, + <11882 8845 6653 5404 5118 5105>, + <11882 8845 6653 5404 5118 5105>, + <11882 8845 6653 5404 5118 5105>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/quin-vm-common.dtsi b/arch/arm/boot/dts/qcom/quin-vm-common.dtsi new file mode 100644 index 000000000000..3d353aa5dfca --- /dev/null +++ b/arch/arm/boot/dts/qcom/quin-vm-common.dtsi @@ -0,0 +1,251 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 cgroup.memory=nokmem,nosocket"; + }; + + soc: soc { }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + + qseecom_mem: qseecom_region@0x9e400000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x1000000>; + }; + }; + + firmware: firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; + }; + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev="/dev/block/platform/vdevs/1c0f0000.virtio_blk/vdc"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait"; + status = "ok"; + }; + }; + }; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + virtual-interrupt-parent = "gic"; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + clock_gcc: qcom,gcc { + compatible = "qcom,dummycc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_rpmh: qcom,rpmh { + compatible = "qcom,dummycc"; + #clock-cells = <1>; + }; + + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = <25>; + qcom,ion-heap-type = "SYSTEM"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = <27>; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@19 { /* QSEECOM TA HEAP */ + reg = <19>; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; + }; + + hab: qcom,hab { + compatible = "qcom,hab"; + vmid = <2>; + + mmidgrp100: mmidgrp100 { + grp-start-id = <100>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp200: mmidgrp200 { + grp-start-id = <200>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp300: mmidgrp300 { + grp-start-id = <300>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp400: mmidgrp400 { + grp-start-id = <400>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp500: mmidgrp500 { + grp-start-id = <500>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp600: mmidgrp600 { + grp-start-id = <600>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp700: mmidgrp700 { + grp-start-id = <700>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp800: mmidgrp800 { + grp-start-id = <800>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp900: mmidgrp900 { + grp-start-id = <900>; + role = "fe"; + remote-vmids = <0>; + }; + + mmidgrp1000: mmidgrp1000 { + grp-start-id = <1000>; + role = "fe"; + remote-vmids = <0>; + }; + }; + + sde_kms_hyp: qcom,sde_kms_hyp@ae00000 { + compatible = "qcom,sde-kms-hyp"; + qcom,client-id = "7815"; + }; + + wdog: qcom,wdt@17c10000{ + compatible = "qcom,msm-watchdog"; + reg = <0x17c10000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 0 0>, <0 1 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + qcom,scandump-sizes = <0x10100 0x10100 0x10100 0x10100 + 0x18100 0x18100 0x18100 0x18100>; + }; + + qcom,msm-imem@14680000 { + compatible = "qcom,msm-imem"; + reg = <0x14680000 0x1000>; + ranges = <0x0 0x14680000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 32>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 12>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 200>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 200>; + }; + }; + + vm_restart: restart { + compatible = "qcom,vm-restart"; + status = "ok"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/rgb-panel-st7789v.dtsi b/arch/arm/boot/dts/qcom/rgb-panel-st7789v.dtsi new file mode 100644 index 000000000000..9f18064b5c7d --- /dev/null +++ b/arch/arm/boot/dts/qcom/rgb-panel-st7789v.dtsi @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + rgb_st7789v: qcom,mdss_rgb_st7789v { + qcom,mdss-rgb-panel-name = "st7789v LCD rgb panel"; + qcom,mdss-rgb-panel-framerate = <60>; + qcom,mdss-rgb-panel-width = <240>; + qcom,mdss-rgb-panel-height = <320>; + qcom,mdss-rgb-h-front-porch = <38>; + qcom,mdss-rgb-h-back-porch = <10>; + qcom,mdss-rgb-h-pulse-width = <10>; + qcom,mdss-rgb-h-sync-skew = <0>; + qcom,mdss-rgb-v-back-porch = <4>; + qcom,mdss-rgb-v-front-porch = <8>; + qcom,mdss-rgb-v-pulse-width = <4>; + qcom,mdss-rgb-bpp = <18>; + qcom,mdss-rgb-panel-clockrate = <6000000>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sa515m-ccard-pcie-ep.dts b/arch/arm/boot/dts/qcom/sa515m-ccard-pcie-ep.dts new file mode 100644 index 000000000000..7bd092eebb5c --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa515m-ccard-pcie-ep.dts @@ -0,0 +1,46 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa515m-ccard.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA515M CCARD PCIE-EP"; + compatible = "qcom,sa515m-ccard", + "qcom,sdxprairie", "qcom,ccard"; + qcom,board-id = <25 1>, <25 0x101>; +}; + +&restart_pshold { + qcom,force-warm-reboot; +}; + +&cnss_qca6390 { + status = "disabled"; +}; + +&ipa_hw { + qcom,use-ipa-in-mhi-mode; +}; + +&pcie0 { + status = "disabled"; +}; + +&pcie_ep { + status = "ok"; +}; + +&mhi_device { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/sa515m-ccard-usb-ep.dts b/arch/arm/boot/dts/qcom/sa515m-ccard-usb-ep.dts new file mode 100644 index 000000000000..14c0248a591e --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa515m-ccard-usb-ep.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa515m-ccard.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA515M CCARD USB-EP"; + compatible = "qcom,sa515m-ccard", + "qcom,sdxprairie", "qcom,ccard"; + qcom,board-id = <25 2>, <25 0x102>; +}; diff --git a/arch/arm/boot/dts/qcom/sa515m-ccard.dts b/arch/arm/boot/dts/qcom/sa515m-ccard.dts new file mode 100644 index 000000000000..1fc00a911c00 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa515m-ccard.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa515m-ccard.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA515M CCARD"; + compatible = "qcom,sa515m-ccard", + "qcom,sdxprairie", "qcom,ccard"; + qcom,board-id = <25 0>, <25 0x100>; +}; diff --git a/arch/arm/boot/dts/qcom/sa515m-ccard.dtsi b/arch/arm/boot/dts/qcom/sa515m-ccard.dtsi new file mode 100644 index 000000000000..6eb3f9aa57b7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa515m-ccard.dtsi @@ -0,0 +1,132 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdxprairie.dtsi" +#include "sdxprairie-mtp.dtsi" + +&soc { + /delete-node/ qcom,battery-data; + + codec_vreg: regulator-codec-tlv320aic3x { + compatible = "regulator-fixed"; + regulator-name = "codec_vreg"; + startup-delay-us = <100>; + gpio = <&tlmm 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +/* delete pm8150b nodes */ +&thermal_zones { + /delete-node/ pm8150b-wp-therm; + /delete-node/ pm8150b_tz; + /delete-node/ pm8150b-ibat-lvl0; + /delete-node/ pm8150b-ibat-lvl1; + /delete-node/ pm8150b-vbat-lvl0; + /delete-node/ pm8150b-vbat-lvl1; + /delete-node/ pm8150b-vbat-lvl2; + /delete-node/ soc; +}; + +&usb { + extcon = <&vbus_detect>; +}; + +&spmi_bus { + /delete-node/ qpnp,fg; + /delete-node/ bcl@1d00; + /delete-node/ qcom,usb-pdphy@1700; + /delete-node/ qcom,qpnp-smb5; + /delete-node/ adc_tm@3500; + /delete-node/ vadc@3100; + /delete-node/ qcom,pm8150b@2; + /delete-node/ qcom,pm8150b@3; +}; + +&qnand_1 { + status = "ok"; +}; + +&blsp1_uart2b_hs { + status = "okay"; +}; + +&blsp1_uart4a_hs { + status = "okay"; +}; + +&vbus_detect { + status = "okay"; +}; + +&snd_934x { + status = "disabled"; +}; + +&wcd9xxx_intc { + status = "disabled"; +}; + +&clock_audio_up { + status = "disabled"; +}; + +&wcd_rst_gpio { + status = "disabled"; +}; + + +&wcd934x_cdc { + status = "disabled"; +}; + +&spi_2 { + status = "okay"; + + can-controller@0 { + compatible = "qcom,nxp,mpc5746c"; + reg = <0>; + interrupt-parent = <&tlmm>; + interrupts = <88 0>; + spi-max-frequency = <5000000>; + qcom,clk-freq-mhz = <40000000>; + qcom,max-can-channels = <1>; + qcom,bits-per-word = <8>; + qcom,support-can-fd; + }; +}; + +&i2c_3 { + tlv320aic3x_codec: tlv320aic3x@18 { + compatible = "ti,tlv320aic3x"; + reg = <0x18>; + gpio-reset = <&tlmm 92 0>; + reset-inverted; + AVDD-supply = <&codec_vreg>; + IOVDD-supply = <&codec_vreg>; + }; +}; + +&i2c_4 { + status = "okay"; +}; + +&emac_hw { + /delete-property/ vreg_rgmii-supply; + pinctrl-names = "default"; + pinctrl-0 = <&vreg_rgmii_off_default>; +}; + +&vreg_rgmii_io_pads { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155-adp-air-overlay.dts b/arch/arm/boot/dts/qcom/sa6155-adp-air-overlay.dts new file mode 100644 index 000000000000..72a605e98aaa --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155-adp-air-overlay.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include + +#include "sa6155-adp-air.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155 ADP-AIR"; + compatible = "qcom,sa6155-adp-air", "qcom,sa6155", "qcom,adp-air"; + qcom,msm-id = <384 0x0>; + qcom,board-id = <0x03010019 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155-adp-air.dts b/arch/arm/boot/dts/qcom/sa6155-adp-air.dts new file mode 100644 index 000000000000..bff3d522a4c9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155-adp-air.dts @@ -0,0 +1,21 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include "sa6155.dtsi" +#include "sa6155-adp-air.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155 ADP-AIR"; + compatible = "qcom,sa6155-adp-air", "qcom,sa6155", "qcom,adp-air"; + qcom,board-id = <0x03010019 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155-adp-air.dtsi b/arch/arm/boot/dts/qcom/sa6155-adp-air.dtsi new file mode 100644 index 000000000000..61a1491c3e6e --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155-adp-air.dtsi @@ -0,0 +1,267 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include "sa6155-cnss.dtsi" + +&bluetooth_ext { + status = "ok"; +}; + +&qupv3_se6_spi { + status = "ok"; + can-controller@0 { + compatible = "qcom,nxp,mpc5746c"; + reg = <0>; + interrupt-parent = <&tlmm>; + interrupts = <40 0>; + spi-max-frequency = <5000000>; + qcom,clk-freq-mhz = <40000000>; + qcom,max-can-channels = <1>; + qcom,bits-per-word = <8>; + qcom,support-can-fd; + }; +}; + +&soc { + qcom,lpass@62400000 { + status = "ok"; + }; + + qcom,glink { + modem { + status = "disabled"; + }; + }; + + ss5_pwr_ctrl0 { + compatible = "gnss_sirf"; + pinctrl-0 = <&ss5_pwr_ctrl_rst_on>; + ssVreset-gpio = <&tlmm 87 1>; + ssVonoff-gpio = <&tlmm 18 1>; + }; + + hsi2s: qcom,hsi2s { + compatible = "qcom,hsi2s"; + number-of-interfaces = <2>; + reg = <0x1B40000 0x28000>; + reg-names = "lpa_if"; + interrupts = ; + clocks = <&clock_gcc GCC_SDR_CORE_CLK>, + <&clock_gcc GCC_SDR_WR0_MEM_CLK>, + <&clock_gcc GCC_SDR_WR1_MEM_CLK>, + <&clock_gcc GCC_SDR_WR2_MEM_CLK>, + <&clock_gcc GCC_SDR_CSR_HCLK>; + clock-names = "core_clk", "wr0_mem_clk", + "wr1_mem_clk", "wr2_mem_clk", + "csr_hclk"; + + sdr0: qcom,hs0_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs0_i2s_sck_active &hs0_i2s_data0_active + &hs0_i2s_data1_active>; + pinctrl-1 = <&hs0_i2s_sck_sleep &hs0_i2s_data0_sleep + &hs0_i2s_data1_sleep>; + clocks = <&clock_gcc GCC_SDR_PRI_MI2S_CLK>; + clock-names = "pri_mi2s_clk"; + iommus = <&apps_smmu 0x035C 0x0>; + qcom,smmu-s1-bypass; + qcom,iova-mapping = <0x0 0xFFFFFFFF>; + }; + + sdr1: qcom,hs1_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs1_i2s_sck_active &hs1_i2s_data0_active + &hs1_i2s_data1_active>; + pinctrl-1 = <&hs1_i2s_sck_sleep &hs1_i2s_data0_sleep + &hs1_i2s_data1_sleep>; + clocks = <&clock_gcc GCC_SDR_SEC_MI2S_CLK>; + clock-names = "sec_mi2s_clk"; + iommus = <&apps_smmu 0x035D 0x0>; + qcom,smmu-s1-bypass; + qcom,iova-mapping = <0x0 0xFFFFFFFF>; + }; + }; + + emac_hw: qcom,emac@20000 { + compatible = "qcom,emac-dwc-eqos"; + qcom,arm-smmu; + reg = <0x20000 0x10000>, + <0x36000 0x100>; + reg-names = "emac-base", "rgmii-base"; + dma-bit-mask = <32>; + emac-core-version = <7>; + interrupts-extended = <&pdc 0 660 4>, <&pdc 0 661 4>, + <&tlmm 121 2>, <&pdc 0 651 4>, + <&pdc 0 652 4>, <&pdc 0 653 4>, + <&pdc 0 654 4>, <&pdc 0 655 4>, + <&pdc 0 656 4>, <&pdc 0 657 4>, + <&pdc 0 658 4>, <&pdc 0 659 4>, + <&pdc 0 668 4>, <&pdc 0 669 4>; + interrupt-names = "sbd-intr", "lpi-intr", + "phy-intr", "tx-ch0-intr", + "tx-ch1-intr", "tx-ch2-intr", + "tx-ch3-intr", "tx-ch4-intr", + "rx-ch0-intr", "rx-ch1-intr", + "rx-ch2-intr", "rx-ch3-intr", + "ptp_pps_irq_0","ptp_pps_irq_1"; + qcom,msm-bus,name = "emac"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <98 512 0 0>, <1 781 0 0>, /* No vote */ + <98 512 1250 0>, <1 781 0 40000>, /* 10Mbps vote */ + <98 512 12500 0>, <1 781 0 40000>, /* 100Mbps vote */ + <98 512 125000 0>, <1 781 0 40000>; /* 1000Mbps vote */ + qcom,bus-vector-names = "0", "10", "100", "1000"; + clocks = <&clock_gcc GCC_EMAC_AXI_CLK>, + <&clock_gcc GCC_EMAC_PTP_CLK>, + <&clock_gcc GCC_EMAC_RGMII_CLK>, + <&clock_gcc GCC_EMAC_SLV_AHB_CLK>; + clock-names = "eth_axi_clk", "eth_ptp_clk", + "eth_rgmii_clk", "eth_slave_ahb_clk"; + qcom,phy-reset = <&tlmm 104 GPIO_ACTIVE_HIGH>; + qcom,phy-intr-redirect = <&tlmm 121 GPIO_ACTIVE_LOW>; + gdsc_emac-supply = <&emac_gdsc>; + pinctrl-names = "dev-emac-mdc", "dev-emac-mdio", + "dev-emac-rgmii_txd0_state", "dev-emac-rgmii_txd1_state", + "dev-emac-rgmii_txd2_state", "dev-emac-rgmii_txd3_state", + "dev-emac-rgmii_txc_state", "dev-emac-rgmii_tx_ctl_state", + "dev-emac-rgmii_rxd0_state", "dev-emac-rgmii_rxd1_state", + "dev-emac-rgmii_rxd2_state", "dev-emac-rgmii_rxd3_state", + "dev-emac-rgmii_rxc_state", "dev-emac-rgmii_rx_ctl_state", + "dev-emac-phy_intr", "dev-emac-phy_reset_state", + "dev-emac_pin_pps_0", "dev-emac-rgmii_rxc_suspend_state", + "dev-emac-rgmii_rxc_resume_state"; + + pinctrl-0 = <&emac_mdc>; + pinctrl-1 = <&emac_mdio>; + pinctrl-2 = <&emac_rgmii_txd0>; + pinctrl-3 = <&emac_rgmii_txd1>; + pinctrl-4 = <&emac_rgmii_txd2>; + pinctrl-5 = <&emac_rgmii_txd3>; + pinctrl-6 = <&emac_rgmii_txc>; + pinctrl-7 = <&emac_rgmii_tx_ctl>; + pinctrl-8 = <&emac_rgmii_rxd0>; + pinctrl-9 = <&emac_rgmii_rxd1>; + pinctrl-10 = <&emac_rgmii_rxd2>; + pinctrl-11 = <&emac_rgmii_rxd3>; + pinctrl-12 = <&emac_rgmii_rxc>; + pinctrl-13 = <&emac_rgmii_rx_ctl>; + pinctrl-14 = <&emac_phy_intr>; + pinctrl-15 = <&emac_phy_reset_state>; + pinctrl-16 = <&emac_pin_pps_0>; + pinctrl-17 = <&emac_rgmii_rxc_suspend>; + pinctrl-18 = <&emac_rgmii_rxc_resume>; + + io-macro-info { + io-macro-bypass-mode = <0>; + io-interface = "rgmii"; + }; + emac_emb_smmu: emac_emb_smmu { + compatible = "qcom,emac-smmu-embedded"; + iommus = <&apps_smmu 0x1C0 0x0>; + qcom,iova-mapping = <0x80000000 0x40000000>; + }; + }; + +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v3-660"; + + vdda-phy-supply = <&pm6155_1_l5>; /* 0.9v */ + vdda-pll-supply = <&pm6155_1_l12>; + vdda-phy-max-microamp = <30000>; + vdda-pll-max-microamp = <12000>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm6155_1_l17>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm6155_1_s4>; + vcc-max-microamp = <800000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm6155_1_l11>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vddp-ref-clk-min-uV = <1232000>; + qcom,vddp-ref-clk-max-uV = <1260000>; + + status = "ok"; +}; + +&sdhc_1 { + vdd-supply = <&pm6155_1_l17>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&pm6155_1_s4>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm6155_1_l10>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&pm6155_1_l2>; + qcom,vdd-io-voltage-level = <1800000 3100000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&tlmm 99 1>; + + status = "ok"; +}; + +&usb0 { + qcom,host-poweroff-in-pm-suspend; +}; + +&usb1 { + status = "ok"; + qcom,default-mode-host; + qcom,host-poweroff-in-pm-suspend; +}; + +&qupv3_se0_2uart { + status = "ok"; +}; + +&qupv3_se4_2uart { + status = "ok"; +}; + +&qupv3_se7_4uart { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155-adp-star-overlay.dts b/arch/arm/boot/dts/qcom/sa6155-adp-star-overlay.dts new file mode 100644 index 000000000000..4eb2f21bd0f6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155-adp-star-overlay.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include + +#include "sa6155-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155 ADP-STAR"; + compatible = "qcom,sa6155-adp-star", "qcom,sa6155", "qcom,adp-star"; + qcom,msm-id = <384 0x0>; + qcom,board-id = <0x10019 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155-adp-star.dts b/arch/arm/boot/dts/qcom/sa6155-adp-star.dts new file mode 100644 index 000000000000..488ca5c4d303 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155-adp-star.dts @@ -0,0 +1,21 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include "sa6155.dtsi" +#include "sa6155-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155 ADP-STAR"; + compatible = "qcom,sa6155-adp-star", "qcom,sa6155", "qcom,adp-star"; + qcom,board-id = <0x10019 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155-adp-star.dtsi b/arch/arm/boot/dts/qcom/sa6155-adp-star.dtsi new file mode 100644 index 000000000000..78c3bce754e6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155-adp-star.dtsi @@ -0,0 +1,275 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include "sa6155-cnss.dtsi" + +&bluetooth_ext { + status = "ok"; +}; + +&qupv3_se6_spi { + status = "ok"; + can-controller@0 { + compatible = "qcom,nxp,mpc5746c"; + reg = <0>; + interrupt-parent = <&tlmm>; + interrupts = <40 0>; + spi-max-frequency = <5000000>; + qcom,clk-freq-mhz = <40000000>; + qcom,max-can-channels = <1>; + qcom,bits-per-word = <8>; + qcom,support-can-fd; + }; +}; + +&soc { + qcom,lpass@62400000 { + status = "ok"; + }; + + qcom,glink { + modem { + status = "disabled"; + }; + }; + + hsi2s: qcom,hsi2s { + compatible = "qcom,hsi2s"; + number-of-interfaces = <2>; + reg = <0x1B40000 0x28000>; + reg-names = "lpa_if"; + interrupts = ; + clocks = <&clock_gcc GCC_SDR_CORE_CLK>, + <&clock_gcc GCC_SDR_WR0_MEM_CLK>, + <&clock_gcc GCC_SDR_WR1_MEM_CLK>, + <&clock_gcc GCC_SDR_WR2_MEM_CLK>, + <&clock_gcc GCC_SDR_CSR_HCLK>; + clock-names = "core_clk", "wr0_mem_clk", + "wr1_mem_clk", "wr2_mem_clk", + "csr_hclk"; + + sdr0: qcom,hs0_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs0_i2s_sck_active &hs0_i2s_data0_active + &hs0_i2s_data1_active>; + pinctrl-1 = <&hs0_i2s_sck_sleep &hs0_i2s_data0_sleep + &hs0_i2s_data1_sleep>; + clocks = <&clock_gcc GCC_SDR_PRI_MI2S_CLK>; + clock-names = "pri_mi2s_clk"; + iommus = <&apps_smmu 0x035C 0x0>; + qcom,smmu-s1-bypass; + qcom,iova-mapping = <0x0 0xFFFFFFFF>; + }; + + sdr1: qcom,hs1_i2s { + compatible = "qcom,hsi2s-interface"; + minor-number = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hs1_i2s_sck_active &hs1_i2s_data0_active + &hs1_i2s_data1_active>; + pinctrl-1 = <&hs1_i2s_sck_sleep &hs1_i2s_data0_sleep + &hs1_i2s_data1_sleep>; + clocks = <&clock_gcc GCC_SDR_SEC_MI2S_CLK>; + clock-names = "sec_mi2s_clk"; + iommus = <&apps_smmu 0x035D 0x0>; + qcom,smmu-s1-bypass; + qcom,iova-mapping = <0x0 0xFFFFFFFF>; + }; + }; + + emac_hw: qcom,emac@20000 { + compatible = "qcom,emac-dwc-eqos"; + qcom,arm-smmu; + reg = <0x20000 0x10000>, + <0x36000 0x100>; + reg-names = "emac-base", "rgmii-base"; + dma-bit-mask = <32>; + emac-core-version = <7>; + interrupts-extended = <&pdc 0 660 4>, <&pdc 0 661 4>, + <&tlmm 121 2>, <&pdc 0 651 4>, + <&pdc 0 652 4>, <&pdc 0 653 4>, + <&pdc 0 654 4>, <&pdc 0 655 4>, + <&pdc 0 656 4>, <&pdc 0 657 4>, + <&pdc 0 658 4>, <&pdc 0 659 4>, + <&pdc 0 668 4>, <&pdc 0 669 4>; + interrupt-names = "sbd-intr", "lpi-intr", + "phy-intr", "tx-ch0-intr", + "tx-ch1-intr", "tx-ch2-intr", + "tx-ch3-intr", "tx-ch4-intr", + "rx-ch0-intr", "rx-ch1-intr", + "rx-ch2-intr", "rx-ch3-intr", + "ptp_pps_irq_0","ptp_pps_irq_1"; + qcom,msm-bus,name = "emac"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <98 512 0 0>, <1 781 0 0>, /* No vote */ + <98 512 1250 0>, <1 781 0 40000>, /* 10Mbps vote */ + <98 512 12500 0>, <1 781 0 40000>, /* 100Mbps vote */ + <98 512 125000 0>, <1 781 0 40000>; /* 1000Mbps vote */ + qcom,bus-vector-names = "0", "10", "100", "1000"; + clocks = <&clock_gcc GCC_EMAC_AXI_CLK>, + <&clock_gcc GCC_EMAC_PTP_CLK>, + <&clock_gcc GCC_EMAC_RGMII_CLK>, + <&clock_gcc GCC_EMAC_SLV_AHB_CLK>; + clock-names = "eth_axi_clk", "eth_ptp_clk", + "eth_rgmii_clk", "eth_slave_ahb_clk"; + qcom,phy-reset = <&tlmm 104 GPIO_ACTIVE_HIGH>; + qcom,phy-intr-redirect = <&tlmm 121 GPIO_ACTIVE_LOW>; + gdsc_emac-supply = <&emac_gdsc>; + pinctrl-names = "dev-emac-mdc", "dev-emac-mdio", + "dev-emac-rgmii_txd0_state", "dev-emac-rgmii_txd1_state", + "dev-emac-rgmii_txd2_state", "dev-emac-rgmii_txd3_state", + "dev-emac-rgmii_txc_state", "dev-emac-rgmii_tx_ctl_state", + "dev-emac-rgmii_rxd0_state", "dev-emac-rgmii_rxd1_state", + "dev-emac-rgmii_rxd2_state", "dev-emac-rgmii_rxd3_state", + "dev-emac-rgmii_rxc_state", "dev-emac-rgmii_rx_ctl_state", + "dev-emac-phy_intr", "dev-emac-phy_reset_state", + "dev-emac_pin_pps_0", "dev-emac-rgmii_rxc_suspend_state", + "dev-emac-rgmii_rxc_resume_state"; + + pinctrl-0 = <&emac_mdc>; + pinctrl-1 = <&emac_mdio>; + pinctrl-2 = <&emac_rgmii_txd0>; + pinctrl-3 = <&emac_rgmii_txd1>; + pinctrl-4 = <&emac_rgmii_txd2>; + pinctrl-5 = <&emac_rgmii_txd3>; + pinctrl-6 = <&emac_rgmii_txc>; + pinctrl-7 = <&emac_rgmii_tx_ctl>; + pinctrl-8 = <&emac_rgmii_rxd0>; + pinctrl-9 = <&emac_rgmii_rxd1>; + pinctrl-10 = <&emac_rgmii_rxd2>; + pinctrl-11 = <&emac_rgmii_rxd3>; + pinctrl-12 = <&emac_rgmii_rxc>; + pinctrl-13 = <&emac_rgmii_rx_ctl>; + pinctrl-14 = <&emac_phy_intr>; + pinctrl-15 = <&emac_phy_reset_state>; + pinctrl-16 = <&emac_pin_pps_0>; + pinctrl-17 = <&emac_rgmii_rxc_suspend>; + pinctrl-18 = <&emac_rgmii_rxc_resume>; + + io-macro-info { + io-macro-bypass-mode = <0>; + io-interface = "rgmii"; + }; + emac_emb_smmu: emac_emb_smmu { + compatible = "qcom,emac-smmu-embedded"; + iommus = <&apps_smmu 0x1C0 0x0>; + qcom,iova-mapping = <0x80000000 0x40000000>; + }; + }; + +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v3-660"; + + vdda-phy-supply = <&pm6155_1_l5>; /* 0.9v */ + vdda-pll-supply = <&pm6155_1_l12>; + vdda-phy-max-microamp = <30000>; + vdda-pll-max-microamp = <12000>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm6155_1_l17>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm6155_1_s4>; + vcc-max-microamp = <800000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm6155_1_l11>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vddp-ref-clk-min-uV = <1232000>; + qcom,vddp-ref-clk-max-uV = <1260000>; + + status = "ok"; +}; + +&sdhc_1 { + vdd-supply = <&pm6155_1_l17>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&pm6155_1_s4>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm6155_1_l10>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&pm6155_1_l2>; + qcom,vdd-io-voltage-level = <1800000 3100000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&tlmm 99 1>; + + status = "ok"; +}; + +&usb0 { + qcom,default-mode-none; + qcom,host-poweroff-in-pm-suspend; +}; + +&qusb_phy0 { + qcom,usb-hs-ac-bitmask = <0x30>; + qcom,usb-hs-ac-value = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_hs_ac_en_default>; +}; + +&usb1 { + status = "ok"; + qcom,default-mode-host; + qcom,host-poweroff-in-pm-suspend; +}; + +&qusb_phy1 { + qcom,usb-hs-ac-bitmask = <0xc0>; + qcom,usb-hs-ac-value = <0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_hs_ac_en_default>; +}; + +&qupv3_se0_2uart { + status = "ok"; +}; + +&qupv3_se5_i2c { + status = "ok"; +}; + +&qupv3_se7_4uart { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155-audio.dtsi b/arch/arm/boot/dts/qcom/sa6155-audio.dtsi new file mode 100644 index 000000000000..ccff6e021534 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155-audio.dtsi @@ -0,0 +1,597 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "sm6150-lpi.dtsi" + +&soc { + tdm_pri_rx: qcom,msm-dai-tdm-pri-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37120>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36864 36866 36868 36870>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <0>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <1>; + qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>; + dai_pri_tdm_rx_0: qcom,msm-dai-q6-tdm-pri-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36864>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_1: qcom,msm-dai-q6-tdm-pri-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36866>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_2: qcom,msm-dai-q6-tdm-pri-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36868>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_3: qcom,msm-dai-q6-tdm-pri-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36870>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_pri_tx: qcom,msm-dai-tdm-pri-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37121>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36865 36867 36869 36871>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <0>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <1>; + qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>; + dai_pri_tdm_tx_0: qcom,msm-dai-q6-tdm-pri-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36865>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_1: qcom,msm-dai-q6-tdm-pri-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36867>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_2: qcom,msm-dai-q6-tdm-pri-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36869>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_3: qcom,msm-dai-q6-tdm-pri-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36871>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sec_rx: qcom,msm-dai-tdm-sec-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37136>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36880 36882 36884 + 36886 36894>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sec_tdm_rx_0: qcom,msm-dai-q6-tdm-sec-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36880>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_1: qcom,msm-dai-q6-tdm-sec-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36882>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_2: qcom,msm-dai-q6-tdm-sec-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36884>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_3: qcom,msm-dai-q6-tdm-sec-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36886>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_7: qcom,msm-dai-q6-tdm-sec-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36894>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sec_tx: qcom,msm-dai-tdm-sec-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37137>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36881 36883 36885 36887>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sec_tdm_tx_0: qcom,msm-dai-q6-tdm-sec-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36881>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_1: qcom,msm-dai-q6-tdm-sec-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36883>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_2: qcom,msm-dai-q6-tdm-sec-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36885>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_3: qcom,msm-dai-q6-tdm-sec-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36887>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_tert_rx: qcom,msm-dai-tdm-tert-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37152>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36896 36898 36900 + 36902 36904>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&ter_i2s_sck_active &ter_i2s_data0_active + &ter_i2s_data1_active>; + pinctrl-1 = <&ter_i2s_sck_sleep &ter_i2s_data0_sleep + &ter_i2s_data1_sleep>; + dai_tert_tdm_rx_0: qcom,msm-dai-q6-tdm-tert-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36896>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_1: qcom,msm-dai-q6-tdm-tert-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36898>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_2: qcom,msm-dai-q6-tdm-tert-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36900>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_3: qcom,msm-dai-q6-tdm-tert-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36902>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_4: qcom,msm-dai-q6-tdm-tert-rx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36904>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_tert_tx: qcom,msm-dai-tdm-tert-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37153>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36897 36899 36901 + 36903 36911>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_tert_tdm_tx_0: qcom,msm-dai-q6-tdm-tert-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36897>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_1: qcom,msm-dai-q6-tdm-tert-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36899>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_2: qcom,msm-dai-q6-tdm-tert-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36901>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_3: qcom,msm-dai-q6-tdm-tert-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36903>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_7: qcom,msm-dai-q6-tdm-tert-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36911>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quat_rx: qcom,msm-dai-tdm-quat-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37168>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36912 36914 36916 + 36918 36926>; + qcom,msm-cpudai-tdm-lane-mask = /bits/ 16 <3>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&quat_tdm_sclk_active &quat_tdm_ws_active + &quat_tdm_data0_active &quat_tdm_data1_active>; + pinctrl-1 = <&quat_tdm_sclk_sleep &quat_tdm_ws_sleep + &quat_tdm_data0_sleep &quat_tdm_data1_sleep>; + dai_quat_tdm_rx_0: qcom,msm-dai-q6-tdm-quat-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36912>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_1: qcom,msm-dai-q6-tdm-quat-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36914>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_2: qcom,msm-dai-q6-tdm-quat-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36916>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_3: qcom,msm-dai-q6-tdm-quat-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36918>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + dai_quat_tdm_rx_7: qcom,msm-dai-q6-tdm-quat-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36926>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quat_tx: qcom,msm-dai-tdm-quat-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37169>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36913 36915 36917 + 36919 36927>; + qcom,msm-cpudai-tdm-lane-mask = /bits/ 16 <12>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_quat_tdm_tx_0: qcom,msm-dai-q6-tdm-quat-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36913>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_1: qcom,msm-dai-q6-tdm-quat-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36915>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_2: qcom,msm-dai-q6-tdm-quat-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36917>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_3: qcom,msm-dai-q6-tdm-quat-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36919>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_7: qcom,msm-dai-q6-tdm-quat-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36927>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quin_rx: qcom,msm-dai-tdm-quin-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37184>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36928 36930 36932 + 36934 36942>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <0>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&quin_tdm_sclk_active &quin_tdm_ws_active + &quin_tdm_data0_active &quin_tdm_data1_active>; + pinctrl-1 = <&quin_tdm_sclk_sleep &quin_tdm_ws_sleep + &quin_tdm_data0_sleep &quin_tdm_data1_sleep>; + dai_quin_tdm_rx_0: qcom,msm-dai-q6-tdm-quin-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36928>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_1: qcom,msm-dai-q6-tdm-quin-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36930>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_2: qcom,msm-dai-q6-tdm-quin-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36932>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_3: qcom,msm-dai-q6-tdm-quin-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36934>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + dai_quin_tdm_rx_7: qcom,msm-dai-q6-tdm-quin-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36942>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quin_tx: qcom,msm-dai-tdm-quin-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37185>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36929 36931 36933 + 36935 36943>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <0>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_quin_tdm_tx_0: qcom,msm-dai-q6-tdm-quin-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36929>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_1: qcom,msm-dai-q6-tdm-quin-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36931>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_2: qcom,msm-dai-q6-tdm-quin-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36933>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_3: qcom,msm-dai-q6-tdm-quin-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36935>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + dai_quin_tdm_tx_7: qcom,msm-dai-q6-tdm-quin-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36943>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + dai_pri_auxpcm: qcom,msm-pri-auxpcm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pri_aux_pcm_sck_active &pri_aux_pcm_ws_active + &pri_aux_pcm_data0_active &pri_aux_pcm_data1_active>; + pinctrl-1 = <&pri_aux_pcm_sck_sleep &pri_aux_pcm_ws_sleep + &pri_aux_pcm_data0_sleep &pri_aux_pcm_data1_sleep>; + }; +}; + +&audio_apr { + status = "ok"; + q6core: qcom,q6core-audio { + status = "ok"; + sm6150_snd: sound { + status = "disabled"; + }; + + bolero: bolero-cdc { + status = "disabled"; + }; + }; +}; + +&q6core { + sound-adp-star { + compatible = "qcom,sa6155-asoc-snd-adp-star"; + qcom,model = "sa6155-adp-star-snd-card"; + qcom,mi2s-audio-intf; + qcom,auxpcm-audio-intf; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; + + qcom,tert-tdm-gpios = <&tdm_tert_rx>; + qcom,quat-tdm-gpios = <&tdm_quat_rx>; + qcom,quin-tdm-gpios = <&tdm_quin_rx>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>, <&loopback1>, <&pcm_dtmf>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", + "msm-pcm-dtmf"; + asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_rx_1>, + <&dai_pri_tdm_rx_2>, <&dai_pri_tdm_rx_3>, + <&dai_pri_tdm_tx_0>, <&dai_pri_tdm_tx_1>, + <&dai_pri_tdm_tx_2>, <&dai_pri_tdm_tx_3>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_rx_1>, + <&dai_sec_tdm_rx_2>, <&dai_sec_tdm_rx_3>, + <&dai_sec_tdm_rx_7>, <&dai_sec_tdm_tx_0>, + <&dai_sec_tdm_tx_1>, <&dai_sec_tdm_tx_2>, + <&dai_sec_tdm_tx_3>, <&dai_tert_tdm_rx_0>, + <&dai_tert_tdm_rx_1>, <&dai_tert_tdm_rx_2>, + <&dai_tert_tdm_rx_3>, <&dai_tert_tdm_rx_4>, + <&dai_tert_tdm_tx_0>, <&dai_tert_tdm_tx_1>, + <&dai_tert_tdm_tx_2>, <&dai_tert_tdm_tx_3>, + <&dai_tert_tdm_tx_7>, <&dai_quat_tdm_rx_0>, + <&dai_quat_tdm_rx_1>, <&dai_quat_tdm_rx_2>, + <&dai_quat_tdm_rx_3>, <&dai_quat_tdm_rx_7>, + <&dai_quat_tdm_tx_0>, <&dai_quat_tdm_tx_1>, + <&dai_quat_tdm_tx_2>, <&dai_quat_tdm_tx_3>, + <&dai_quat_tdm_tx_7>, <&dai_quin_tdm_rx_0>, + <&dai_quin_tdm_rx_1>, <&dai_quin_tdm_rx_2>, + <&dai_quin_tdm_rx_3>, <&dai_quin_tdm_rx_7>, + <&dai_quin_tdm_tx_0>, <&dai_quin_tdm_tx_1>, + <&dai_quin_tdm_tx_2>, <&dai_quin_tdm_tx_3>, + <&dai_quin_tdm_tx_7>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", + "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", + "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", + "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", + "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36866", + "msm-dai-q6-tdm.36868", "msm-dai-q6-tdm.36870", + "msm-dai-q6-tdm.36865", "msm-dai-q6-tdm.36867", + "msm-dai-q6-tdm.36869", "msm-dai-q6-tdm.36871", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36882", + "msm-dai-q6-tdm.36884", "msm-dai-q6-tdm.36886", + "msm-dai-q6-tdm.36894", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36883", "msm-dai-q6-tdm.36885", + "msm-dai-q6-tdm.36887", "msm-dai-q6-tdm.36896", + "msm-dai-q6-tdm.36898", "msm-dai-q6-tdm.36900", + "msm-dai-q6-tdm.36902", "msm-dai-q6-tdm.36904", + "msm-dai-q6-tdm.36897", "msm-dai-q6-tdm.36899", + "msm-dai-q6-tdm.36901", "msm-dai-q6-tdm.36903", + "msm-dai-q6-tdm.36911", "msm-dai-q6-tdm.36912", + "msm-dai-q6-tdm.36914", "msm-dai-q6-tdm.36916", + "msm-dai-q6-tdm.36918", "msm-dai-q6-tdm.36926", + "msm-dai-q6-tdm.36913", "msm-dai-q6-tdm.36915", + "msm-dai-q6-tdm.36917", "msm-dai-q6-tdm.36919", + "msm-dai-q6-tdm.36927", "msm-dai-q6-tdm.36928", + "msm-dai-q6-tdm.36930", "msm-dai-q6-tdm.36932", + "msm-dai-q6-tdm.36934", "msm-dai-q6-tdm.36942", + "msm-dai-q6-tdm.36929", "msm-dai-q6-tdm.36931", + "msm-dai-q6-tdm.36933", "msm-dai-q6-tdm.36935", + "msm-dai-q6-tdm.36943"; + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>; + }; +}; + +&qupv3_se4_i2c { + status = "disabled"; +}; + +&slim_aud { + status = "disabled"; + iommu_slim_aud_ctrl_cb { + status = "disabled"; + }; + msm_dai_slim { + status = "disabled"; + }; +}; + +&qupv3_se10_spi { + status = "ok"; + spi_codec@0 { + compatible = "qcom,spi-msm-codec-slave"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-cpha; + }; +}; + diff --git a/arch/arm/boot/dts/qcom/sa6155-cnss.dtsi b/arch/arm/boot/dts/qcom/sa6155-cnss.dtsi new file mode 100644 index 000000000000..948571cab28c --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155-cnss.dtsi @@ -0,0 +1,223 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + /* PWR_CTR1_VDD_1P8 supply */ + vreg_conn_1p8: vreg_conn_1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p8"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pm6155_1_gpios 1 0>; + }; + + /* PWR_CTR2_VDD_PA supply */ + vreg_conn_pa: vreg_conn_pa { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_pa"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pm6155_1_gpios 6 0>; + }; + + vreg_wlan: vreg_wlan { + compatible = "qcom,stub-regulator"; + regulator-name = "vreg_wlan"; + }; + + bluetooth_ext: bt_qca6174 { + compatible = "qca,qca6174"; + /* BT_EN */ + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_active>; + qca,bt-reset-gpio = <&tlmm 85 0>; + /* PWR_CTR1_VDD_PA */ + qca,bt-vdd-pa-supply = <&vreg_conn_pa>; + qca,bt-chip-pwd-supply = <&vreg_conn_1p8>; + qca,bt-vdd-vm-supply = <&pm6155_1_s6>; + qca,bt-vdd-5a-supply = <&pm6155_1_s5>; + qca,bt-vdd-vh-supply = <&pm6155_1_l15>; + + qca,bt-vdd-vm-voltage-level = <1370000 1370000>; + qca,bt-vdd-5a-voltage-level = <2040000 2040000>; + qca,bt-vdd-vh-voltage-level = <1904000 1904000>; + + qca,bt-vdd-vm-current-level = <0>; + qca,bt-vdd-5a-current-level = <0>; + qca,bt-vdd-vh-current-level = <450000>; + + status = "disabled"; + }; + + cnss_pcie: qcom,cnss-qca-converged { + compatible = "qcom,cnss-qca-converged"; + + qcom,converged-dt; + qcom,wlan-rc-num = <0>; + qcom,bus-type=<0>; + qcom,notify-modem-status; + qcom,msm-bus,name = "msm-cnss"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, <1 512 0 0>, + /* Upto 200 Mbps */ + <45 512 41421 655360>, <1 512 41421 655360>, + /* Upto 400 Mbps */ + <45 512 98572 655360>, <1 512 98572 1600000>, + /* Upto 800 Mbps */ + <45 512 207108 1146880>, <1 512 207108 3124992>; + + #address-cells=<1>; + #size-cells=<1>; + ranges = <0x10000000 0x10000000 0x10000000>, + <0x20000000 0x20000000 0x10000>, + <0xa0000000 0xa0000000 0x10000000>, + <0xb0000000 0xb0000000 0x10000>; + + vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; + vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>; + vdd-wlan-supply = <&vreg_wlan>; + vdd-wlan-rfa1-supply = <&pm6155_1_s6>; + vdd-wlan-rfa2-supply = <&pm6155_1_s5>; + vdd-wlan-rfa3-supply = <&pm6155_1_l15>; + + wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2"; + qcom,vdd-wlan-ctrl1-info = <0 0 0 0>; + qcom,vdd-wlan-ctrl2-info = <0 0 0 0>; + + wlan-en-gpio = <&tlmm 98 0>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + + chip_cfg@0 { + reg = <0x10000000 0x10000000>, + <0x20000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + + supported-ids = <0x003e>; + wlan_vregs = "vdd-wlan"; + qcom,vdd-wlan-info = <0 0 0 10>; + + qcom,smmu-s1-enable; + qcom,wlan-ramdump-dynamic = <0x200000>; + }; + + chip_cfg@1 { + reg = <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + + supported-ids = <0x1101>; + wlan_vregs = "vdd-wlan-rfa1", "vdd-wlan-rfa2", + "vdd-wlan-rfa3"; + qcom,vdd-wlan-rfa1-info = <1350000 1350000 0 0>; + qcom,vdd-wlan-rfa2-info = <2040000 2040000 0 0>; + qcom,vdd-wlan-rfa3-info = <1904000 1904000 0 0>; + + qcom,wlan-ramdump-dynamic = <0x400000>; + mhi,max-channels = <30>; + mhi,timeout = <10000>; + + mhi_channels { + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155-display.dtsi b/arch/arm/boot/dts/qcom/sa6155-display.dtsi new file mode 100644 index 000000000000..8e203077e4c9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155-display.dtsi @@ -0,0 +1,227 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "dsi-panel-ext-bridge-1080p.dtsi" + +&tlmm { + ioexp_intr_active: ioexp_intr_active { + mux { + pins = "gpio58"; + function = "gpio"; + }; + config { + pins = "gpio58"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + ioexp_reset_active: ioexp_reset_active { + mux { + pins = "gpio3"; + function = "gpio"; + }; + config { + pins = "gpio3"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; +}; + +&sde_dp { + qcom,ext-disp = <&ext_disp>; + qcom,dp-hpd-gpio = <&ioexp 8 0>; + + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; + pinctrl-0 = <&dp_hpd_cfg_pins>; + pinctrl-1 = <&dp_hpd_cfg_pins>; + + vdda-1p2-supply = <&pm6155_1_l11>; + vdda-0p9-supply = <&pm6155_1_l5>; + /delete-property/ qcom,dp-aux-switch; + qcom,mst-enable; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; +}; + +/* FSA & Rotator not required in Auto */ +&qupv3_se3_i2c { + status = "disabled"; +}; + +&mdss_rotator { + status = "disabled"; +}; + +&qupv3_se2_i2c { + + status = "ok"; + + pinctrl-0 = <&qupv3_se2_i2c_active + &ioexp_intr_active + &ioexp_reset_active>; + + ioexp: gpio@3e { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1509q"; + reg = <0x3e>; + interrupt-parent = <&tlmm>; + interrupts = <58 0>; + gpio-controller; + interrupt-controller; + semtech,probe-reset; + + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_hpd_cfg_pins + &dsi1_cdet_cfg_pins + &dp_hpd_cfg_pins>; + + dsi1_hpd_cfg_pins: gpio0-cfg { + pins = "gpio0"; + bias-pull-up; + }; + + dsi1_cdet_cfg_pins: gpio1-cfg { + pins = "gpio1"; + bias-pull-down; + }; + + dp_hpd_cfg_pins: gpio8-cfg { + pins = "gpio8"; + bias-pull-down; + }; + }; + + i2c-mux@77 { + compatible = "nxp,pca9542"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + anx_7625_1: anx7625@2c { + compatible = "analogix,anx7625"; + reg = <0x2c>; + interrupt-parent = <&ioexp>; + interrupts = <0 0>; + cbl_det-gpio = <&ioexp 1 0>; + power_en-gpio = <&tlmm 4 0>; + reset_n-gpio = <&tlmm 5 0>; + }; + }; + }; +}; + +&anx_7625_1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + anx_7625_1_in: endpoint { + remote-endpoint = <&dsi_anx_7625_1_out>; + }; + }; + }; +}; + +&dsi_ext_bridge_1080p { + qcom,mdss-dsi-ext-bridge = <0>; +}; + +&soc { + dsi_anx_7625_1: qcom,dsi-display@17 { + label = "dsi_anx_7625_1"; + qcom,dsi-display-active; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_ext_bridge_1080p>; + }; + + dsi_dp1: qcom,dsi-display@1 { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + + clocks = <&mdss_dsi0_pll BYTE0_MUX_CLK>, + <&mdss_dsi0_pll PIX0_MUX_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0"; + + + qcom,dsi-display-list = + <&dsi_anx_7625_1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_anx_7625_1_out: endpoint { + remote-endpoint = <&anx_7625_1_in>; + }; + }; + }; + }; + + sde_wb: qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display"; + }; + + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + qcom,rmnet-ipa { + status="disabled"; + }; +}; + +&mdss_dsi_phy0 { + qcom,panel-force-clock-lane-hs; +}; + +&mdss_mdp { + connectors = <&sde_rscc &dsi_dp1 &sde_wb &sde_dp>; +}; + diff --git a/arch/arm/boot/dts/qcom/sa6155-pcie.dtsi b/arch/arm/boot/dts/qcom/sa6155-pcie.dtsi new file mode 100644 index 000000000000..d22818a1f459 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155-pcie.dtsi @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + pcie0: qcom,pcie@1c08000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x1c08000 0x4000>, + <0x1c0e000 0x1000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>, + <0x40200000 0x100000>, + <0x40300000 0x1fd00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>; + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc 0 140 0 + 0 0 0 1 &intc 0 149 0 + 0 0 0 2 &intc 0 150 0 + 0 0 0 3 &intc 0 151 0 + 0 0 0 4 &intc 0 152 0>; + + qcom,phy-sequence = <0x0800 0x01 0x0 + 0x0804 0x03 0x0 + 0x0034 0x18 0x0 + 0x0038 0x10 0x0 + 0x0070 0x0f 0x0 + 0x00c8 0x01 0x0 + 0x0128 0x00 0x0 + 0x0144 0xff 0x0 + 0x0148 0x1f 0x0 + 0x0194 0x06 0x0 + 0x0048 0x0f 0x0 + 0x0178 0x00 0x0 + 0x019c 0x01 0x0 + 0x018c 0x20 0x0 + 0x0184 0x0a 0x0 + 0x00b4 0x20 0x0 + 0x000c 0x09 0x0 + 0x00ac 0x04 0x0 + 0x00d0 0x82 0x0 + 0x00e4 0x03 0x0 + 0x00e0 0x55 0x0 + 0x00dc 0x55 0x0 + 0x0054 0x00 0x0 + 0x0050 0x0d 0x0 + 0x004c 0x04 0x0 + 0x0174 0x35 0x0 + 0x003c 0x02 0x0 + 0x0040 0x1f 0x0 + 0x0078 0x04 0x0 + 0x0084 0x16 0x0 + 0x0090 0x30 0x0 + 0x010c 0x00 0x0 + 0x0108 0x80 0x0 + 0x00a8 0x01 0x0 + 0x000c 0x0a 0x0 + 0x0010 0x01 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0014 0x02 0x0 + 0x0018 0x00 0x0 + 0x0024 0x2f 0x0 + 0x0028 0x19 0x0 + 0x0268 0x45 0x0 + 0x0194 0x06 0x0 + 0x024c 0x02 0x0 + 0x02ac 0x12 0x0 + 0x0510 0x1c 0x0 + 0x051c 0x14 0x0 + 0x04d8 0x01 0x0 + 0x04dc 0x00 0x0 + 0x04e0 0xdb 0x0 + 0x0448 0x4b 0x0 + 0x041c 0x04 0x0 + 0x0410 0x04 0x0 + 0x0074 0x19 0x0 + 0x0854 0x04 0x0 + 0x09ac 0x00 0x0 + 0x08a0 0x40 0x0 + 0x09e0 0x00 0x0 + 0x09dc 0x40 0x0 + 0x09a8 0x00 0x0 + 0x08a4 0x40 0x0 + 0x08a8 0x73 0x0 + 0x09b0 0x07 0x0 + 0x09d8 0x99 0x0 + 0x0824 0x15 0x0 + 0x0828 0x0e 0x0 + 0x0800 0x00 0x0 + 0x0808 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + + perst-gpio = <&tlmm 101 0>; + wake-gpio = <&tlmm 100 0>; + + gdsc-vdd-supply = <&pcie_0_gdsc>; + vreg-1.8-supply = <&L12A>; + vreg-0.9-supply = <&L5A>; + + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1.8-voltage-level = <1800000 1800000 24000>; + qcom,vreg-0.9-voltage-level = <925000 925000 24000>; + qcom,vreg-cx-voltage-level = ; + + msi-parent = <&pcie0_msi>; + + qcom,no-l0s-supported; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; + + qcom,max-link-speed = <0x2>; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x20000000>; + + qcom,phy-status-offset = <0x974>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x804>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <0>; + + qcom,pcie-phy-ver = <2609>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x0400>; + + iommu-map = <0x0 &apps_smmu 0x0400 0x1>, + <0x100 &apps_smmu 0x0401 0x1>, + <0x200 &apps_smmu 0x0402 0x1>, + <0x300 &apps_smmu 0x0403 0x1>, + <0x400 &apps_smmu 0x0404 0x1>, + <0x500 &apps_smmu 0x0405 0x1>, + <0x600 &apps_smmu 0x0406 0x1>, + <0x700 &apps_smmu 0x0407 0x1>, + <0x800 &apps_smmu 0x0408 0x1>, + <0x900 &apps_smmu 0x0409 0x1>, + <0xa00 &apps_smmu 0x040a 0x1>, + <0xb00 &apps_smmu 0x040b 0x1>, + <0xc00 &apps_smmu 0x040c 0x1>, + <0xd00 &apps_smmu 0x040d 0x1>, + <0xe00 &apps_smmu 0x040e 0x1>, + <0xf00 &apps_smmu 0x040f 0x1>; + + qcom,msm-bus,name = "pcie0"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 500 800>; + + clocks = <&clock_gcc GCC_PCIE_0_PIPE_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_PCIE_0_AUX_CLK>, + <&clock_gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&clock_gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&clock_gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&clock_gcc GCC_PCIE_0_CLKREF_CLK>, + <&clock_gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&clock_gcc GCC_PCIE0_PHY_REFGEN_CLK>, + <&clock_gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", + "pcie_phy_refgen_clk", "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&clock_gcc GCC_PCIE_0_BCR>, + <&clock_gcc GCC_PCIE_0_PHY_BCR>; + + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + }; + + pcie0_msi: qcom,pcie0_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155-pmic.dtsi b/arch/arm/boot/dts/qcom/sa6155-pmic.dtsi new file mode 100644 index 000000000000..3e00782bcd68 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155-pmic.dtsi @@ -0,0 +1,319 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Remove regulator nodes specific to SM6150 */ +&soc { + /delete-node/ rpmh-regulator-mxlvl; + /delete-node/ rpmh-regulator-cxlvl; + /delete-node/ rpmh-regulator-smpc1; + /delete-node/ rpmh-regulator-smpc2; + /delete-node/ rpmh-regulator-modemlvl; + /delete-node/ rpmh-regulator-smpc8; + /delete-node/ rpmh-regulator-ldoa1; + /delete-node/ rpmh-regulator-ldoa2; + /delete-node/ rpmh-regulator-ldoa3; + /delete-node/ rpmh-regulator-ldoa4; + /delete-node/ rpmh-regulator-ldoa5; + /delete-node/ rpmh-regulator-ldoa6; + /delete-node/ rpmh-regulator-lmxlvl; + /delete-node/ rpmh-regulator-lcxlvl; + /delete-node/ rpmh-regulator-ldoa9; + /delete-node/ rpmh-regulator-ldoa10; + /delete-node/ rpmh-regulator-ldoa11; + /delete-node/ rpmh-regulator-ldoa12; + /delete-node/ rpmh-regulator-ldoa13; + /delete-node/ rpmh-regulator-ldoa14; + /delete-node/ rpmh-regulator-ldoa15; + /delete-node/ rpmh-regulator-ldoa16; + /delete-node/ rpmh-regulator-ldoa17; + /delete-node/ rpmh-regulator-ldoa18; + /delete-node/ rpmh-regulator-ldoa19; + /delete-node/ rpmh-regulator-ldoc1; + /delete-node/ rpmh-regulator-ldoc2; + /delete-node/ rpmh-regulator-ldoc3; + /delete-node/ rpmh-regulator-ldoc4; + /delete-node/ rpmh-regulator-ldoc5; + /delete-node/ rpmh-regulator-ldoc6; + /delete-node/ rpmh-regulator-ldoc7; + /delete-node/ rpmh-regulator-ldoc8; + /delete-node/ rpmh-regulator-ldoc9; + /delete-node/ rpmh-regulator-ldoc10; + /delete-node/ rpmh-regulator-ldoc11; + /delete-node/ rpmh-regulator-bobc1; +}; + +&qusb_phy0 { + /delete-property/ vdd-supply; + /delete-property/ vdda18-supply; + /delete-property/ vdda33-supply; +}; + +&qusb_phy1 { + /delete-property/ vdd-supply; + /delete-property/ vdda18-supply; + /delete-property/ vdda33-supply; +}; + +&usb0 { + /delete-property/ extcon; + /delete-property/ vbus_dwc3-supply; +}; + +&pm6150_pdphy { + /delete-property/ vdd-pdphy-supply; +}; + +&usb_qmp_phy { + /delete-property/ vdd-supply; + /delete-property/ core-supply; +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&pm6155_1_l11>; +}; + +&sde_dp { + vdda-1p2-supply = <&pm6155_1_l11>; + vdda-0p9-supply = <&pm6155_1_l5>; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&pm6155_1_l5>; +}; + +&cam_csiphy0 { + /delete-property/ mipi-csi-vdd-supply; +}; + +&cam_csiphy1 { + /delete-property/ mipi-csi-vdd-supply; +}; + +&cam_csiphy2 { + /delete-property/ mipi-csi-vdd-supply; +}; + +&bluetooth { + /delete-property/ qca,bt-vdd-core-supply; + /delete-property/ qca,bt-vdd-pa-supply; + /delete-property/ qca,bt-vdd-ldo-supply; +}; + +&icnss { + /delete-property/ vdd-cx-mx-supply; + /delete-property/ vdd-1.8-xo-supply ; + /delete-property/ vdd-1.3-rfa-supply; + /delete-property/ vdd-3.3-ch0-supply; +}; + +&soc { + qcom,lpass@62400000 { + vdd_cx-supply = <&VDD_CX_LEVEL>; + }; +}; + + +&spmi_bus { + /delete-node/ qcom,pm6150@0; + /delete-node/ qcom,pm6150@1; + /delete-node/ qcom,pm6150l@4; + /delete-node/ qcom,pm6150l@5; +}; + +&thermal_zones { + /delete-node/ pm6150l-tz; + /delete-node/ pm6150-tz; + /delete-node/ pm6150-ibat-lvl0; + /delete-node/ pm6150-ibat-lvl1; + /delete-node/ pm6150-vbat-lvl0; + /delete-node/ pm6150-vbat-lvl1; + /delete-node/ pm6150-vbat-lvl2; + /delete-node/ pm6150l-vph-lvl0; + /delete-node/ pm6150l-vph-lvl1; + /delete-node/ pm6150l-vph-lvl2; + /delete-node/ xo-therm; + /delete-node/ sdm-therm; + /delete-node/ conn-therm; + /delete-node/ emmc_ufs-therm; + /delete-node/ rf_pa0_therm-therm; + /delete-node/ camera_flash-therm; + /delete-node/ quiet-therm; + /delete-node/ quiet-therm-step; + /delete-node/ aoss-lowf; + /delete-node/ cpuss-0-lowf; + /delete-node/ cpuss-1-lowf; + /delete-node/ cpuss-2-lowf; + /delete-node/ cpuss-3-lowf; + /delete-node/ cpu-1-0-lowf; + /delete-node/ cpu-1-1-lowf; + /delete-node/ cpu-1-2-lowf; + /delete-node/ cpu-1-3-lowf; + /delete-node/ gpu-lowf; + /delete-node/ q6-hvx-lowf; + /delete-node/ mdm-core-lowf; + /delete-node/ video-lowf; + /delete-node/ display-lowf; + /delete-node/ wlan-lowf; + /delete-node/ camera-lowf; + soc { + /delete-property/ thermal-sensors; + }; +}; + +#include "sa6155-regulator.dtsi" +#include "pm6155.dtsi" + +&spmi_bus { + qcom,pm6155@0 { + pm6155_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-vdd-reference = <1875>; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel node */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm1 { + reg = ; + label = "pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm2 { + reg = ; + label = "pa_therm2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + }; + + pm6155_adc_tm: adc_tm@3500 { + compatible = "qcom,adc-tm5"; + reg = <0x3500 0x100>; + interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "thr-int-en"; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + io-channels = <&pm6155_vadc ADC_XO_THERM_PU2>, + <&pm6155_vadc ADC_AMUX_THM1_PU2>, + <&pm6155_vadc ADC_AMUX_THM2_PU2>; + + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm2 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + }; + }; +}; + +&thermal_zones { + xo-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6155_adc_tm ADC_XO_THERM_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-therm1-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6155_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-therm2-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6155_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155-regulator.dtsi b/arch/arm/boot/dts/qcom/sa6155-regulator.dtsi new file mode 100644 index 000000000000..b7745ffd32da --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155-regulator.dtsi @@ -0,0 +1,537 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + rpmh-regulator-smpa2 { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "cx.lvl"; + + VDD_CX_LEVEL: VDD_MX_LEVEL: + S2A_LEVEL: pm6155_1_s2_level: regulator-pm6155-1-s2-level { + regulator-name = "pm6155_1_s2_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + + VDD_CX_LEVEL_AO: VDD_MX_LEVEL_AO: S2A_LEVEL_AO: + pm6155_1_s2_level_ao: regulator-pm6155-1-s2-level-ao { + regulator-name = "pm6155_1_s2_level_ao"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + }; + + rpmh-regulator-smpa3 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpa3"; + S3A: pm6155_1_s3: regulator-pm6155-1-s3 { + regulator-name = "pm6155_1_s3"; + qcom,set = ; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <650000>; + qcom,init-voltage = <600000>; + }; + }; + + rpmh-regulator-smpa4 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpa4"; + S4A: pm6155_1_s4: regulator-pm6155-1-s4 { + regulator-name = "pm6155_1_s4"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1829000>; + qcom,init-voltage = <1800000>; + }; + }; + + rpmh-regulator-smpa5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpa5"; + S5A: pm6155_1_s5: regulator-pm6155-1-s5 { + regulator-name = "pm6155_1_s5"; + qcom,set = ; + regulator-min-microvolt = <1896000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1896000>; + }; + }; + + rpmh-regulator-smpa6 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpa6"; + S6A: pm6155_1_s6: regulator-pm6155-1-s6 { + regulator-name = "pm6155_1_s6"; + qcom,set = ; + regulator-min-microvolt = <947000>; + regulator-max-microvolt = <1404000>; + qcom,init-voltage = <947000>; + }; + }; + + rpmh-regulator-ldoa1 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L1A: pm6155_1_l1: regulator-pm6155-1-l1 { + regulator-name = "pm6155_1_l1"; + qcom,set = ; + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <852000>; + qcom,init-voltage = <488000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa2 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L2A: pm6155_1_l2: regulator-pm6155-1-l2 { + regulator-name = "pm6155_1_l2"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3100000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa3 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L3A: pm6155_1_l3: regulator-pm6155-1-l3 { + regulator-name = "pm6155_1_l3"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1248000>; + qcom,init-voltage = <1000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L5A: pm6155_1_l5: regulator-pm6155-1-l5 { + regulator-name = "pm6155_1_l5"; + qcom,set = ; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + qcom,init-voltage = <875000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa7 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L7A: pm6155_1_l7: regulator-pm6155-1-l7 { + regulator-name = "pm6155_1_l7"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa8 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa8"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L8A: pm6155_1_l8: regulator-pm6155-1-l8 { + regulator-name = "pm6155_1_l8"; + qcom,set = ; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1350000>; + qcom,init-voltage = <1150000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa9 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L9A: pm6155_1_l9: regulator-pm6155-1-l9 { + regulator-name = "pm6155_1_l9"; + qcom,set = ; + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1232000>; + qcom,init-voltage = <1232000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa10 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L10A: pm6155_1_l10: regulator-pm6155-1-l10 { + regulator-name = "pm6155_1_l10"; + qcom,set = ; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <2950000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa11 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L11A: pm6155_1_l11: regulator-pm6155-1-l11 { + regulator-name = "pm6155_1_l11"; + qcom,set = ; + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1260000>; + qcom,init-voltage = <1232000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa12 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L12A: pm6155_1_l12: regulator-pm6155-1-l12 { + regulator-name = "pm6155_1_l12"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1890000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa13 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L13A: pm6155_1_l13: regulator-pm6155-1-l13 { + regulator-name = "pm6155_1_l13"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3230000>; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa15 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa15"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L15A: pm6155_1_l15: regulator-pm6155-1-l15 { + regulator-name = "pm6155_1_l15"; + qcom,set = ; + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <1904000>; + qcom,init-voltage = <1904000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa16 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L16A: pm6155_1_l16: regulator-pm6155-1-l16 { + regulator-name = "pm6155_1_l16"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa17 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L17A: pm6155_1_l17: regulator-pm6155-1-l17 { + regulator-name = "pm6155_1_l17"; + qcom,set = ; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; + }; + }; + + /* PM6155 S1 - VDD_MSS supply */ + rpmh-regulator-modemlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "mss.lvl"; + + VDD_MSS_LEVEL: + S1C_LEVEL: pm6155_2_s1_level: regulator-pm6155-2-s1-level { + regulator-name = "pm6155_2_s1_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ldoc2 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L2C: pm6155_2_l2: regulator-pm6155-2-l2 { + regulator-name = "pm6155_2_l2"; + qcom,set = ; + regulator-min-microvolt = <2430000>; + regulator-max-microvolt = <2970000>; + qcom,init-voltage = <2430000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc3 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L3C: pm6155_2_l3: regulator-pm6155-2-l3 { + regulator-name = "pm6155_2_l3"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1252000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc4 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L4C: pm6155_2_l4: regulator-pm6155-2-l4 { + regulator-name = "pm6155_2_l4"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1252000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc13 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L13C: pm6155_2_l13: regulator-pm6155-2-l13 { + regulator-name = "pm6155_2_l13"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc14 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc14"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L14C: pm6155_2_l14: regulator-pm6155-2-l14 { + regulator-name = "pm6155_2_l14"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1850000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc16 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L16C: pm6155_2_l16: regulator-pm6155-2-l16 { + regulator-name = "pm6155_2_l16"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc17 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L17C: pm6155_2_l17: regulator-pm6155-2-l17 { + regulator-name = "pm6155_2_l17"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc18 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc18"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L18C: pm6155_2_l18: regulator-pm6155-2-l18 { + regulator-name = "pm6155_2_l18"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1050000>; + qcom,init-voltage = <1000000>; + qcom,init-mode = ; + }; + }; +}; + diff --git a/arch/arm/boot/dts/qcom/sa6155.dts b/arch/arm/boot/dts/qcom/sa6155.dts new file mode 100644 index 000000000000..7ee1fede6906 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa6155.dtsi" +#include "sa6155-cnss.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155 SoC"; + compatible = "qcom,sa6155"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155.dtsi b/arch/arm/boot/dts/qcom/sa6155.dtsi new file mode 100644 index 000000000000..1bf14ec01b4a --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155.dtsi @@ -0,0 +1,485 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm6150.dtsi" +#include "sa6155-pmic.dtsi" +#include "sa6155-display.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155"; + compatible = "qcom,sa6155"; + qcom,msm-name = "SA6155"; + qcom,msm-id = <384 0x10000>; + + aliases { + pci-domain0 = &pcie0; /* PCIe0 domain */ + }; +}; + +&tpdm_west { + status = "disabled"; +}; + +&qusb_phy0 { + vdd-supply = <&L5A>; + vdda18-supply = <&L12A>; + vdda33-supply = <&L13A>; +}; + +&usb_qmp_phy { + vdd-supply = <&L5A>; + core-supply = <&L12A>; +}; + +&qusb_phy1 { + vdd-supply = <&L5A>; + vdda18-supply = <&L12A>; + vdda33-supply = <&L13A>; +}; + +&ipa_hw { + status="disabled"; +}; + +&mdss_dsi0_pll { + /delete-property/ qcom,dsi-pll-ssc-en; +}; + +&slpi_tlmm { + status = "ok"; +}; + +&clock_gcc { + compatible = "qcom,gcc-sa6155", "syscon"; + /delete-property/ protected-clocks; +}; + +&clock_videocc { + compatible = "qcom,videocc-sa6155", "syscon"; +}; + +&clock_dispcc { + compatible = "qcom,dispcc-sa6155", "syscon"; +}; + +&clock_scc { + compatible = "qcom,scc-sa6155", "syscon"; + vdd_scc_cx-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&clock_camcc { + compatible = "qcom,camcc-sa6155", "syscon"; + vdd_mx-supply = <&VDD_CX_LEVEL>; +}; + +&clock_gpucc { + compatible = "qcom,gpucc-sa6155", "syscon"; + vdd_mx-supply = <&VDD_CX_LEVEL>; +}; + +#include "sa6155-pcie.dtsi" + +&soc { + qfprom: qfprom@780130 { + compatible = "qcom,qfprom"; + reg = <0x00780130 0x4>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + }; +}; + +&thermal_zones { + lmh-dcvs-00 { + trips { + active-config { + temperature = <105000>; + hysteresis = <40000>; + }; + }; + }; + + lmh-dcvs-01 { + trips { + active-config { + temperature = <105000>; + hysteresis = <40000>; + }; + }; + }; +}; + +/* GPU power level overrides */ +&msm_gpu { + /* + * Speed-bin zero is default speed bin. + * For rest of the speed bins, speed-bin value + * is calulated as FMAX/4.8 MHz round up to zero + * decimal places. + */ + qcom,gpu-pwrlevel-bins { + #address-cells = <1>; + #size-cells = <0>; + + compatible="qcom,gpu-pwrlevel-bins"; + + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <0>; + + qcom,initial-pwrlevel = <5>; + qcom,ca-target-pwrlevel = <3>; + + /* TURBO */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <845000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <745000000>; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <650000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <500000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <435000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <290000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <177>; + + qcom,initial-pwrlevel = <5>; + qcom,ca-target-pwrlevel = <3>; + + /* TURBO */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <845000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <745000000>; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <650000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <500000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <435000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <290000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <156>; + + qcom,initial-pwrlevel = <4>; + qcom,ca-target-pwrlevel = <2>; + + /* NOM L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <745000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <650000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <500000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <435000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <290000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-3 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <136>; + + qcom,initial-pwrlevel = <3>; + qcom,ca-target-pwrlevel = <1>; + + /* NOM */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <650000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <500000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <435000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <290000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-4 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <105>; + + qcom,initial-pwrlevel = <1>; + qcom,ca-target-pwrlevel = <2>; + + /* SVS L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <500000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <435000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <290000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-5 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <73>; + + qcom,initial-pwrlevel = <1>; + qcom,ca-target-pwrlevel = <0>; + + /* SVS */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <350000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <290000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155p-adp-air-overlay.dts b/arch/arm/boot/dts/qcom/sa6155p-adp-air-overlay.dts new file mode 100644 index 000000000000..2d61e9f82b26 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155p-adp-air-overlay.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "sa6155-adp-air.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-AIR"; + compatible = "qcom,sa6155p-adp-air", "qcom,sa6155p", "qcom,adp-air"; + qcom,msm-id = <377 0x0>, <380 0>; + qcom,board-id = <0x03010019 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155p-adp-air.dts b/arch/arm/boot/dts/qcom/sa6155p-adp-air.dts new file mode 100644 index 000000000000..45096df226d6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155p-adp-air.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa6155p.dtsi" +#include "sa6155-adp-air.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-AIR"; + compatible = "qcom,sa6155p-adp-air", "qcom,sa6155p", "qcom,adp-air"; + qcom,board-id = <0x03010019 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155p-adp-star-overlay.dts b/arch/arm/boot/dts/qcom/sa6155p-adp-star-overlay.dts new file mode 100644 index 000000000000..af524dee576b --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155p-adp-star-overlay.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "sa6155-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-STAR"; + compatible = "qcom,sa6155p-adp-star", "qcom,sa6155p", "qcom,adp-star"; + qcom,msm-id = <377 0x0>, <380 0>; + qcom,board-id = <0x10019 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155p-adp-star.dts b/arch/arm/boot/dts/qcom/sa6155p-adp-star.dts new file mode 100644 index 000000000000..745b4a834f69 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155p-adp-star.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa6155p.dtsi" +#include "sa6155-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-STAR"; + compatible = "qcom,sa6155p-adp-star", "qcom,sa6155p", "qcom,adp-star"; + qcom,board-id = <0x10019 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155p-v2-adp-air-overlay.dts b/arch/arm/boot/dts/qcom/sa6155p-v2-adp-air-overlay.dts new file mode 100644 index 000000000000..7e1af6237373 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155p-v2-adp-air-overlay.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "sa6155-adp-air.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-AIR V2"; + compatible = "qcom,sa6155p-adp-air", "qcom,sa6155p", "qcom,adp-air"; + qcom,msm-id = <377 0x0>, <380 0>; + qcom,board-id = <0x03020019 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155p-v2-adp-air.dts b/arch/arm/boot/dts/qcom/sa6155p-v2-adp-air.dts new file mode 100644 index 000000000000..9227291501bb --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155p-v2-adp-air.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa6155p.dtsi" +#include "sa6155-adp-air.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-AIR V2"; + compatible = "qcom,sa6155p-adp-air", "qcom,sa6155p", "qcom,adp-air"; + qcom,board-id = <0x03020019 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155p-v2-adp-star-overlay.dts b/arch/arm/boot/dts/qcom/sa6155p-v2-adp-star-overlay.dts new file mode 100644 index 000000000000..c2d16fa9c655 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155p-v2-adp-star-overlay.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "sa6155-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-STAR V2"; + compatible = "qcom,sa6155p-adp-star", "qcom,sa6155p", "qcom,adp-star"; + qcom,msm-id = <377 0x0>, <380 0>; + qcom,board-id = <0x020019 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155p-v2-adp-star.dts b/arch/arm/boot/dts/qcom/sa6155p-v2-adp-star.dts new file mode 100644 index 000000000000..00a89805920b --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155p-v2-adp-star.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa6155p.dtsi" +#include "sa6155-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P ADP-STAR V2"; + compatible = "qcom,sa6155p-adp-star", "qcom,sa6155p", "qcom,adp-star"; + qcom,board-id = <0x020019 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155p-vm-pcie.dtsi b/arch/arm/boot/dts/qcom/sa6155p-vm-pcie.dtsi new file mode 100644 index 000000000000..ff0e56593e78 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155p-vm-pcie.dtsi @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + pcie0: qcom,pcie@1c08000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x1c08000 0x4000>, + <0x1c0e000 0x1000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>, + <0x40200000 0x100000>, + <0x40300000 0x1fd00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>; + interrupts = <0 140 0>, <0 149 0>, <0 150 0>, <0 151 0>, + <0 152 0>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + + qcom,phy-sequence = <0x0800 0x01 0x0 + 0x0804 0x03 0x0 + 0x0034 0x18 0x0 + 0x0038 0x10 0x0 + 0x0294 0x06 0x0 + 0x00c8 0x01 0x0 + 0x0128 0x00 0x0 + 0x0144 0xff 0x0 + 0x0148 0x1f 0x0 + 0x0070 0x0f 0x0 + 0x0048 0x0f 0x0 + 0x0178 0x00 0x0 + 0x019c 0x01 0x0 + 0x018c 0x20 0x0 + 0x0184 0x0a 0x0 + 0x00b4 0x20 0x0 + 0x000c 0x09 0x0 + 0x00ac 0x04 0x0 + 0x00d0 0x82 0x0 + 0x00e4 0x03 0x0 + 0x00e0 0x55 0x0 + 0x00dc 0x55 0x0 + 0x0054 0x00 0x0 + 0x0050 0x0d 0x0 + 0x004c 0x04 0x0 + 0x0174 0x33 0x0 + 0x003c 0x02 0x0 + 0x0040 0x1f 0x0 + 0x0078 0x0b 0x0 + 0x0084 0x16 0x0 + 0x0090 0x28 0x0 + 0x010c 0x00 0x0 + 0x0108 0x80 0x0 + 0x0010 0x01 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0014 0x02 0x0 + 0x0018 0x00 0x0 + 0x0024 0x2f 0x0 + 0x0028 0x19 0x0 + 0x0268 0x45 0x0 + 0x0194 0x06 0x0 + 0x024c 0x02 0x0 + 0x02ac 0x12 0x0 + 0x0510 0x1c 0x0 + 0x051c 0x14 0x0 + 0x04d8 0x01 0x0 + 0x04dc 0x00 0x0 + 0x04e0 0xdb 0x0 + 0x0448 0x4b 0x0 + 0x041c 0x04 0x0 + 0x0410 0x04 0x0 + 0x0074 0x19 0x0 + 0x0854 0x04 0x0 + 0x09ac 0x00 0x0 + 0x08a0 0x40 0x0 + 0x09e0 0x00 0x0 + 0x09dc 0x40 0x0 + 0x09a8 0x00 0x0 + 0x08a4 0x40 0x0 + 0x08a8 0x73 0x0 + 0x0518 0x99 0x0 + 0x0824 0x15 0x0 + 0x0828 0x0e 0x0 + 0x09b0 0x07 0x0 + 0x0800 0x00 0x0 + 0x0808 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + + perst-gpio = <&tlmm 101 0>; + wake-gpio = <&tlmm 100 0>; + + gdsc-vdd-supply = <&pcie_0_gdsc>; + vreg-1.8-supply = <&pm6155_1_l12>; + vreg-0.9-supply = <&pm6155_1_l5>; + + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1.8-voltage-level = <1800000 1800000 24000>; + qcom,vreg-0.9-voltage-level = <925000 925000 24000>; + qcom,vreg-cx-voltage-level = ; + + msi-parent = <&pcie0_msi>; + + qcom,no-l0s-supported; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; + + qcom,max-link-speed = <0x2>; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x20000000>; + + qcom,phy-status-offset = <0x974>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x804>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <0>; + + qcom,pcie-phy-ver = <0x10>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x0400>; + + iommu-map = <0x0 &apps_smmu 0x0400 0x1>, + <0x100 &apps_smmu 0x0401 0x1>, + <0x200 &apps_smmu 0x0402 0x1>, + <0x300 &apps_smmu 0x0403 0x1>, + <0x400 &apps_smmu 0x0404 0x1>, + <0x500 &apps_smmu 0x0405 0x1>, + <0x600 &apps_smmu 0x0406 0x1>, + <0x700 &apps_smmu 0x0407 0x1>, + <0x800 &apps_smmu 0x0408 0x1>, + <0x900 &apps_smmu 0x0409 0x1>, + <0xa00 &apps_smmu 0x040a 0x1>, + <0xb00 &apps_smmu 0x040b 0x1>, + <0xc00 &apps_smmu 0x040c 0x1>, + <0xd00 &apps_smmu 0x040d 0x1>, + <0xe00 &apps_smmu 0x040e 0x1>, + <0xf00 &apps_smmu 0x040f 0x1>; + + qcom,msm-bus,name = "pcie0"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 500 800>; + + clocks = <&clock_virt GCC_PCIE_0_PIPE_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_virt GCC_PCIE_0_AUX_CLK>, + <&clock_virt GCC_PCIE_0_CFG_AHB_CLK>, + <&clock_virt GCC_PCIE_0_MSTR_AXI_CLK>, + <&clock_virt GCC_PCIE_0_SLV_AXI_CLK>, + <&clock_virt GCC_PCIE_0_CLKREF_CLK>, + <&clock_virt GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&clock_virt GCC_PCIE0_PHY_REFGEN_CLK>, + <&clock_virt GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", + "pcie_phy_refgen_clk", "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&clock_virt GCC_PCIE_0_BCR>, + <&clock_virt GCC_PCIE_0_PHY_BCR>; + + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + status = "disabled"; + }; + + pcie0_msi: qcom,pcie0_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155p-vm-pinctrl.dtsi b/arch/arm/boot/dts/qcom/sa6155p-vm-pinctrl.dtsi new file mode 100644 index 000000000000..cd591f8ee4fc --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155p-vm-pinctrl.dtsi @@ -0,0 +1,1783 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + tlmm: pinctrl@03000000 { + compatible = "qcom,sm6150-pinctrl"; + reg = <0x03000000 0xdc2000>, <0x17c000f0 0x60>; + reg-names = "pinctrl", "spi_cfg"; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + ufs_dev_reset_assert: ufs_dev_reset_assert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * UFS_RESET driver strengths are having + * different values/steps compared to typical + * GPIO drive strengths. + * + * Following table clarifies: + * + * HDRV value | UFS_RESET | Typical GPIO + * (dec) | (mA) | (mA) + * 0 | 0.8 | 2 + * 1 | 1.55 | 4 + * 2 | 2.35 | 6 + * 3 | 3.1 | 8 + * 4 | 3.9 | 10 + * 5 | 4.65 | 12 + * 6 | 5.4 | 14 + * 7 | 6.15 | 16 + * + * POR value for UFS_RESET HDRV is 3 which means + * 3.1mA and we want to use that. Hence just + * specify 8mA to "drive-strength" binding and + * that should result into writing 3 to HDRV + * field. + */ + drive-strength = <8>; /* default: 3.1 mA */ + output-low; /* active low reset */ + }; + }; + + ufs_dev_reset_deassert: ufs_dev_reset_deassert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * default: 3.1 mA + * check comments under ufs_dev_reset_assert + */ + drive-strength = <8>; + output-high; /* active low reset */ + }; + }; + + /* QUPv3_0 South SE mappings */ + /* SE 0 pin mappings */ + qupv3_se0_2uart_pins: qupv3_se0_2uart_pins { + qupv3_se0_2uart_active: qupv3_se0_2uart_active { + mux { + pins = "gpio16", "gpio17"; + function = "qup00"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se0_2uart_sleep: qupv3_se0_2uart_sleep { + mux { + pins = "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + /* SE 1 pin mappings */ + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_active: qupv3_se1_i2c_active { + mux { + pins = "gpio4", "gpio5"; + function = "qup01"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + /* SE 2 pin mappings */ + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "qup02"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_active: qupv3_se2_spi_active { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "qup02"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + fpc_reset_int { + fpc_reset_low: reset_low { + mux { + pins = "gpio101"; + function = "fpc_reset_gpio_low"; + }; + config { + pins = "gpio101"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + fpc_reset_high: reset_high { + mux { + pins = "gpio101"; + function = "fpc_reset_gpio_high"; + }; + + config { + pins = "gpio101"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + fpc_int_low: int_low { + mux { + pins = "gpio93"; + }; + config { + pins = "gpio93"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + }; + + /* SE 3 pin mappings */ + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_active: qupv3_se3_i2c_active { + mux { + pins = "gpio18", "gpio19"; + function = "qup03"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + /* QUPv3_1 North instances */ + /* SE 4 pin mappings */ + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_active: qupv3_se4_i2c_active { + mux { + pins = "gpio20", "gpio21"; + function = "qup10"; + }; + + config { + pins = "gpio20", "gpio21"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio20", "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se4_spi_pins: qupv3_se4_spi_pins { + qupv3_se4_spi_active: qupv3_se4_spi_active { + mux { + pins = "gpio20", "gpio21", "gpio22", + "gpio23"; + function = "qup10"; + }; + + config { + pins = "gpio20", "gpio21", "gpio22", + "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { + mux { + pins = "gpio20", "gpio21", "gpio22", + "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21", "gpio22", + "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 5 pin mappings */ + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_active: qupv3_se5_i2c_active { + mux { + pins = "gpio14", "gpio15"; + function = "qup11"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 86 NFC Read Interrupt */ + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 86 NFC Read Interrupt */ + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_active: nfc_enable_active { + /* active state */ + mux { + /* 84: Enable 85: Firmware */ + pins = "gpio84", "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio84", "gpio85"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + /* sleep state */ + mux { + /* 84: Enable 85: Firmware */ + pins = "gpio84", "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio84", "gpio85"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_clk_req_active: nfc_clk_req_active { + /* active state */ + mux { + /* GPIO 50: NFC CLOCK REQUEST */ + pins = "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio50"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_clk_req_suspend: nfc_clk_req_suspend { + /* sleep state */ + mux { + /* GPIO 50: NFC CLOCK REQUEST */ + pins = "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio50"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + + /* SE 6 pin mappings */ + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_active: qupv3_se6_i2c_active { + mux { + pins = "gpio6", "gpio7"; + function = "qup12"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_active: qupv3_se6_spi_active { + mux { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + function = "qup12"; + }; + + config { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 7 pin mappings */ + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_active: qupv3_se7_i2c_active { + mux { + pins = "gpio10", "gpio11"; + function = "qup13"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se7_spi_pins: qupv3_se7_spi_pins { + qupv3_se7_spi_active: qupv3_se7_spi_active { + mux { + pins = "gpio10", "gpio11", "gpio12", + "gpio13"; + function = "qup13"; + }; + + config { + pins = "gpio10", "gpio11", "gpio12", + "gpio13"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_sleep: qupv3_se7_spi_sleep { + mux { + pins = "gpio10", "gpio11", "gpio12", + "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio10", "gpio11", "gpio12", + "gpio13"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se7_4uart_pins: qupv3_se7_4uart_pins { + qupv3_se7_ctsrx: qupv3_se7_ctsrx { + mux { + pins = "gpio10", "gpio13"; + function = "qup13"; + }; + + config { + pins = "gpio10", "gpio13"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_rts: qupv3_se7_rts { + mux { + pins = "gpio11"; + function = "qup13"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se7_tx: qupv3_se7_tx { + mux { + pins = "gpio12"; + function = "qup13"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio91"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio91"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + fsa_usbc_ana_en_n@114 { + fsa_usbc_ana_en: fsa_usbc_ana_en { + mux { + pins = "gpio114"; + function = "gpio"; + }; + + config { + pins = "gpio114"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + }; + + pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio90"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio90"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + bias-disable; + drive-strength = <16>; + }; + }; + + sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + sde_dp_switch_active: sde_dp_switch_active { + mux { + pins = "gpio49"; + function = "gpio"; + }; + + config { + pins = "gpio49"; + bias-pull-up; /* pull up */ + output-high; + drive-strength = <2>; + }; + }; + + sde_dp_switch_suspend: sde_dp_switch_suspend { + mux { + pins = "gpio49"; + function = "gpio"; + }; + + config { + pins = "gpio49"; + bias-pull-down; + output-low; + drive-strength = <2>; + }; + }; + + sde_dp_connector_enable: sde_dp_connector_enable { + mux { + pins = "gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio44"; + bias-pull-up; + output-high; + drive-strength = <2>; + }; + }; + + sde_dp_hotplug_ctrl: sde_dp_hotplug_ctrl { + mux { + pins = "gpio103"; + function = "debug_hot"; + }; + + config { + pins = "gpio103"; + bias-disable; + input-enable; + drive-strength = <2>; + }; + }; + + sde_dp_hotplug_tlmm: sde_dp_hotplug_tlmm { + mux { + pins = "gpio103"; + function = "gpio"; + }; + + config { + pins = "gpio103"; + bias-disable; + input-enable; + drive-strength = <2>; + }; + }; + + + + /* SDC pin type */ + sdc1_clk_on: sdc1_clk_on { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc1_clk_off: sdc1_clk_off { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_cmd_on: sdc1_cmd_on { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_cmd_off: sdc1_cmd_off { + config { + pins = "sdc1_cmd"; + num-grp-pins = <1>; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_data_on: sdc1_data_on { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_data_off: sdc1_data_off { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_rclk_on: sdc1_rclk_on { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc1_rclk_off: sdc1_rclk_off { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_on: cd_on { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_cd_off: cd_off { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; + bias-disable; + }; + }; + + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio98"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio98"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + }; + + wsa_swr_clk_pin { + wsa_swr_clk_sleep: wsa_swr_clk_sleep { + mux { + pins = "gpio111"; + function = "WSA_CLK"; + }; + + config { + pins = "gpio111"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + wsa_swr_clk_active: wsa_swr_clk_active { + mux { + pins = "gpio111"; + function = "WSA_CLK"; + }; + + config { + pins = "gpio111"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + }; + + wsa_swr_data_pin { + wsa_swr_data_sleep: wsa_swr_data_sleep { + mux { + pins = "gpio110"; + function = "WSA_DATA"; + }; + + config { + pins = "gpio110"; + drive-strength = <4>; + bias-bus-hold; + }; + }; + + wsa_swr_data_active: wsa_swr_data_active { + mux { + pins = "gpio110"; + function = "WSA_DATA"; + }; + + config { + pins = "gpio110"; + drive-strength = <4>; + bias-bus-hold; + }; + }; + }; + + /* WSA speaker reset pins */ + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio108"; + function = "gpio"; + }; + + config { + pins = "gpio108"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio108"; + function = "gpio"; + }; + + config { + pins = "gpio108"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + spkr_2_sd_n { + spkr_2_sd_n_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio109"; + function = "gpio"; + }; + + config { + pins = "gpio109"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_2_sd_n_active: spkr_2_sd_n_active { + mux { + pins = "gpio109"; + function = "gpio"; + }; + + config { + pins = "gpio109"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + wcd9xxx_intr { + wcd_intr_default: wcd_intr_default{ + mux { + pins = "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio122"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + ter_i2s_sck_ws { + ter_i2s_sck_sleep: ter_i2s_sck_sleep { + mux { + pins = "gpio115", "gpio116"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio115", "gpio116"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + ter_i2s_sck_active: ter_i2s_sck_active { + mux { + pins = "gpio115", "gpio116"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio115", "gpio116"; + drive-strength = <8>; /* 8 mA */ + input-enable; + }; + }; + }; + + ter_i2s_data0 { + ter_i2s_data0_sleep: ter_i2s_data0_sleep { + mux { + pins = "gpio117"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio117"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + ter_i2s_data0_active: ter_i2s_data0_active { + mux { + pins = "gpio117"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio117"; + drive-strength = <8>; /* 8 mA */ + input-enable; + }; + }; + }; + + ter_i2s_data1 { + ter_i2s_data1_sleep: ter_i2s_data1_sleep { + mux { + pins = "gpio118"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio118"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + ter_i2s_data1_active: ter_i2s_data1_active { + mux { + pins = "gpio118"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio118"; + drive-strength = <8>; /* 8 mA */ + output-high; + }; + }; + }; + + pcie0 { + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio90"; + function = "pcie_clk"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio100"; + function = "gpio"; + }; + + config { + pins = "gpio100"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_active { + ts_int_active: ts_int_active { + mux { + pins = "gpio89"; + function = "gpio"; + }; + + config { + pins = "gpio89"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio89"; + function = "gpio"; + }; + + config { + pins = "gpio89"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_reset_active { + ts_reset_active: ts_reset_active { + mux { + pins = "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio88"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + ts_release: ts_release { + mux { + pins = "gpio89", "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio89", "gpio88"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + cci0_active: cci0_active { + mux { + /* CLK, DATA */ + pins = "gpio32", "gpio33"; + function = "cci_i2c"; + }; + + config { + pins = "gpio32", "gpio33"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio32", "gpio33"; + function = "cci_i2c"; + }; + + config { + pins = "gpio32", "gpio33"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA */ + pins = "gpio34", "gpio35"; + function = "cci_i2c"; + }; + + config { + pins = "gpio34", "gpio35"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio34", "gpio35"; + function = "cci_i2c"; + }; + + config { + pins = "gpio34", "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio28"; + function = "cam_mclk"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio28"; + function = "cam_mclk"; + }; + + config { + pins = "gpio28"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_active: cam_sensor_rear_active { + /* RESET */ + mux { + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_suspend: cam_sensor_rear_suspend { + /* RESET */ + mux { + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_front_active: cam_sensor_front_active { + /* RESET */ + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_suspend: cam_sensor_front_suspend { + /* RESET */ + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_rear2_active: cam_sensor_rear2_active { + /* RESET */ + mux { + pins = "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio45"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear2_suspend: cam_sensor_rear2_suspend { + /* RESET */ + mux { + pins = "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio45"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio29"; + function = "cam_mclk"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio29"; + function = "cam_mclk"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio30"; + function = "cam_mclk"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio30"; + function = "cam_mclk"; + }; + + config { + pins = "gpio30"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + flash_led3_front { + flash_led3_front_en: flash_led3_front_en { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + drive_strength = <2>; + output-high; + bias-disable; + }; + }; + + flash_led3_front_dis: flash_led3_front_dis { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + drive_strength = <2>; + output-low; + bias-disable; + }; + }; + }; + emac { + emac_mdc: emac_mdc { + mux { + pins = "gpio113"; + function = "rgmii_mdc"; + }; + + config { + pins = "gpio113"; + bias-pull-up; + }; + }; + emac_mdio: emac_mdio { + mux { + pins = "gpio114"; + function = "rgmii_mdio"; + }; + + config { + pins = "gpio114"; + bias-pull-up; + }; + }; + + emac_rgmii_txd0: emac_rgmii_txd0 { + mux { + pins = "gpio96"; + function = "rgmii_txd0"; + }; + + config { + pins = "gpio96"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txd1: emac_rgmii_txd1 { + mux { + pins = "gpio95"; + function = "rgmii_txd1"; + }; + + config { + pins = "gpio95"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txd2: emac_rgmii_txd2 { + mux { + pins = "gpio94"; + function = "rgmii_txd2"; + }; + + config { + pins = "gpio94"; + bias-pull-up; + drive-strength = <16>; + }; + }; + emac_rgmii_txd3: emac_rgmii_txd3 { + mux { + pins = "gpio93"; + function = "rgmii_txd3"; + }; + + config { + pins = "gpio93"; + bias-pull-up; + drive-strength = <16>; + }; + }; + emac_rgmii_txc: emac_rgmii_txc { + mux { + pins = "gpio92"; + function = "rgmii_txc"; + }; + + config { + pins = "gpio92"; + bias-pull-up; + drive-strength = <16>; + }; + }; + emac_rgmii_tx_ctl: emac_rgmii_tx_ctl { + mux { + pins = "gpio97"; + function = "rgmii_tx"; + }; + + config { + pins = "gpio97"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + + emac_rgmii_rxd0: emac_rgmii_rxd0 { + mux { + pins = "gpio83"; + function = "rgmii_rxd0"; + }; + + config { + pins = "gpio83"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2MA */ + }; + }; + + emac_rgmii_rxd1: emac_rgmii_rxd1 { + mux { + pins = "gpio82"; + function = "rgmii_rxd1"; + }; + + config { + pins = "gpio82"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_rgmii_rxd2: emac_rgmii_rxd2 { + mux { + pins = "gpio81"; + function = "rgmii_rxd2"; + }; + + config { + pins = "gpio81"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + emac_rgmii_rxd3: emac_rgmii_rxd3 { + mux { + pins = "gpio103"; + function = "rgmii_rxd3"; + }; + + config { + pins = "gpio103"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + emac_rgmii_rxc: emac_rgmii_rxc { + mux { + pins = "gpio102"; + function = "rgmii_rxc"; + }; + + config { + pins = "gpio102"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + emac_rgmii_rx_ctl: emac_rgmii_rx_ctl { + mux { + pins = "gpio112"; + function = "rgmii_rx"; + }; + + config { + pins = "gpio112"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + emac_phy_intr: emac_phy_intr { + mux { + pins = "gpio121"; + function = "emac_phy"; + }; + + config { + pins = "gpio121"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + emac_phy_reset_state: emac_phy_reset_state { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + bias-pull-up; + drive-strength = <16>; + }; + }; + emac_pin_pps_0: emac_pin_pps_0 { + mux { + pins = "gpio91"; + function = "rgmii_sync"; + }; + + config { + pins = "gpio91"; + bias-pull-up; + drive-strength = <16>; + }; + }; + }; + + bt_en_active: bt_en_active { + mux { + pins = "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio85"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + usb0_hs_ac_en_default: usb0_hs_ac_en_default { + mux { + pins = "gpio88"; + function = "usb0_hs_ac"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; + bias-disable; + }; + }; + + usb1_hs_ac_en_default: usb1_hs_ac_en_default { + mux { + pins = "gpio89"; + function = "usb1_hs_ac"; + }; + + config { + pins = "gpio89"; + drive-strength = <2>; + bias-disable; + }; + }; + }; +}; + diff --git a/arch/arm/boot/dts/qcom/sa6155p-vm-qupv3.dtsi b/arch/arm/boot/dts/qcom/sa6155p-vm-qupv3.dtsi new file mode 100644 index 000000000000..a3b8ff0bb9ef --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155p-vm-qupv3.dtsi @@ -0,0 +1,450 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + /* + * QUPv3 North & South Instances + * North 0 : SE 4 + * North 1 : SE 5 + * North 2 : SE 6 + * North 3 : SE 7 + * South 0 : SE 0 + * South 1 : SE 1 + * South 2 : SE 2 + * South 3 : SE 3 + */ + + /* QUPv3 South Instances */ + qupv3_0: qcom,qupv3_0_geni_se@8c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x8c0000 0x6000>; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; + qcom,iommu-s1-bypass; + + iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0xc3 0x0>; + }; + }; + + /* Debug UART Instance for CDP/MTP platform */ + qupv3_se0_2uart: qcom,qup_uart@0x880000 { + compatible = "qcom,msm-geni-console"; + reg = <0x880000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP0_S0_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_2uart_active>; + pinctrl-1 = <&qupv3_se0_2uart_sleep>; + interrupts = ; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* I2C */ + qupv3_se1_i2c: i2c@884000 { + compatible = "qcom,i2c-geni"; + reg = <0x884000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP0_S1_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@888000 { + compatible = "qcom,i2c-geni"; + reg = <0x888000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP0_S2_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@88c000 { + compatible = "qcom,i2c-geni"; + reg = <0x88c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP0_S3_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se2_spi: spi@888000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x888000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP0_S2_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* QUPv3 North instances */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0xac0000 0x6000>; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; + qcom,iommu-s1-bypass; + + iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0x363 0x0>; + }; + }; + + /* I2C */ + qupv3_se4_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP1_S0_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP1_S1_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@a88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP1_S2_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se7_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP1_S3_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se4_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa80000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP1_S0_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se6_spi: spi@a88000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa88000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP1_S2_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se7_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP1_S3_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_active>; + pinctrl-1 = <&qupv3_se7_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* + * HS UART instances. HS UART usecases can be supported on these + * instances only. + */ + qupv3_se7_4uart: qcom,qup_uart@0xa8c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP1_S3_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>, + <&qupv3_se7_tx>; + pinctrl-1 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>, + <&qupv3_se7_tx>; + interrupts = ; + status = "disabled"; + qcom,wakeup-byte = <0xFD>; + qcom,wrapper-core = <&qupv3_1>; + }; + + /* QUPv3 SSC Instances */ + qupv3_2: qcom,qupv3_2_geni_se@626c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x626c0000 0x6000>; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; + qcom,iommu-s1-bypass; + + iommu_qupv3_2_geni_se_cb: qcom,iommu_qupv3_2_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0x1783 0x0>; + }; + }; + + /* I2C */ + qupv3_se8_i2c: i2c@62680000 { + compatible = "qcom,i2c-geni"; + reg = <0x62680000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt_scc SCC_QUPV3_SE0_CLK>, + <&clock_virt_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_virt_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@62684000 { + compatible = "qcom,i2c-geni"; + reg = <0x62684000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt_scc SCC_QUPV3_SE1_CLK>, + <&clock_virt_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_virt_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se10_i2c: i2c@62688000 { + compatible = "qcom,i2c-geni"; + reg = <0x62688000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt_scc SCC_QUPV3_SE2_CLK>, + <&clock_virt_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_virt_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_i2c_active>; + pinctrl-1 = <&qupv3_se10_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se11_i2c: i2c@6268c000 { + compatible = "qcom,i2c-geni"; + reg = <0x6268c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt_scc SCC_QUPV3_SE3_CLK>, + <&clock_virt_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_virt_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_i2c_active>; + pinctrl-1 = <&qupv3_se11_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se12_i2c: i2c@62690000 { + compatible = "qcom,i2c-geni"; + reg = <0x62690000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt_scc SCC_QUPV3_SE4_CLK>, + <&clock_virt_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_virt_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_i2c_active>; + pinctrl-1 = <&qupv3_se12_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se13_i2c: i2c@62694000 { + compatible = "qcom,i2c-geni"; + reg = <0x62694000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt_scc SCC_QUPV3_SE5_CLK>, + <&clock_virt_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_virt_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_i2c_active>; + pinctrl-1 = <&qupv3_se13_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se9_spi: spi@62684000 { + compatible = "qcom,spi-geni"; + reg = <0x62684000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt_scc SCC_QUPV3_SE1_CLK>, + <&clock_virt_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_virt_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se10_spi: spi@62688000 { + compatible = "qcom,spi-geni"; + reg = <0x62688000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt_scc SCC_QUPV3_SE2_CLK>, + <&clock_virt_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_virt_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_spi_active>; + pinctrl-1 = <&qupv3_se10_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155p-vm-usb.dtsi b/arch/arm/boot/dts/qcom/sa6155p-vm-usb.dtsi new file mode 100644 index 000000000000..3db66cf1455f --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155p-vm-usb.dtsi @@ -0,0 +1,404 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&soc { + /* Primary USB port related controller */ + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x140 0x0>; + qcom,smmu-s1-bypass; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <0 489 0>, <0 130 0>, <0 486 0>, <0 488 0>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&usb30_prim_gdsc>; + dpdm-supply = <&qusb_phy0>; + clocks = <&clock_virt GCC_USB30_PRIM_MASTER_CLK>, + <&clock_virt GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&clock_virt GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&clock_virt GCC_USB3_PRIM_CLKREF_CLK>, + <&clock_virt GCC_USB30_PRIM_SLEEP_CLK>, + <&clock_virt GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "xo", "sleep_clk", "utmi_clk"; + + resets = <&clock_virt GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + qcom,pm-qos-latency = <61>; + status = "disabled"; + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xcd00>; + interrupts = <0 133 0>; + usb-phy = <&qusb_phy0>, <&usb_nop_phy>; + tx-fifo-resize; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + usb-core-id = <0>; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + + usbbam: qcom,usbbam@a704000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa704000 0x17000>; + interrupts = <0 132 0>; + + qcom,usb-bam-fifo-baseaddr = <0x146a6000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + status = "disabled"; + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + /* Primary USB port related High Speed PHY */ + qusb_phy0: qusb@88e2000 { + compatible = "qcom,qusb2phy"; + reg = <0x88e2000 0x180>, + <0x01fcb250 0x4>, + <0x007801f8 0x4>, + <0x01fcb3e4 0x4>; + reg-names = "qusb_phy_base", + "tcsr_clamp_dig_n_1p8", + "tune2_efuse_addr", + "tcsr_conn_box_spare_0"; + + vdd-supply = <&pm6150_l4>; + vdda18-supply = <&pm6150_l11>; + vdda33-supply = <&pm6150_l17>; + qcom,vdd-voltage-level = <0 925000 975000>; + qcom,tune2-efuse-bit-pos = <25>; + qcom,tune2-efuse-num-bits = <4>; + qcom,qusb-phy-init-seq = <0xc8 0x80 + 0xb3 0x84 + 0x83 0x88 + 0xc0 0x8c + 0x30 0x08 + 0x79 0x0c + 0x21 0x10 + 0x14 0x9c + 0x9f 0x1c + 0x00 0x18>; + phy_type = "utmi"; + qcom,phy-clk-scheme = "cml"; + qcom,major-rev = <1>; + + /* USB2PHY gets clock directly from CXO pad + * connected to differential pin cxo_core_in_1p8_vdda. + */ + clocks = <&clock_gcc RPMH_CXO_CLK>, + <&clock_virt GCC_AHB2PHY_WEST_CLK>; + clock-names = "ref_clk_src", "cfg_ahb_clk"; + + resets = <&clock_virt GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + status = "disabled"; + }; + + /* Primary USB port related QMP USB PHY */ + usb_qmp_phy: ssphy@88e6000 { + compatible = "qcom,usb-ssphy-qmp-usb3-or-dp"; + reg = <0x88e6000 0x1000>, + <0x01fcb244 0x4>; + reg-names = "qmp_phy_base", + "vls_clamp_reg"; + + vdd-supply = <&pm6150_l4>; + core-supply = <&pm6150_l11>; + qcom,vdd-voltage-level = <0 925000 975000>; + qcom,core-voltage-level = <0 1800000 1800000>; + qcom,qmp-phy-init-seq = + /* */ + <0xac 0x14 0x00 + 0x34 0x08 0x00 + 0x174 0x30 0x00 + 0x3c 0x06 0x00 + 0xb4 0x00 0x00 + 0xb8 0x08 0x00 + 0x70 0x0f 0x00 + 0x19c 0x01 0x00 + 0x178 0x00 0x00 + 0xd0 0x82 0x00 + 0xdc 0x55 0x00 + 0xe0 0x55 0x00 + 0xe4 0x03 0x00 + 0x78 0x0b 0x00 + 0x84 0x16 0x00 + 0x90 0x28 0x00 + 0x108 0x80 0x00 + 0x10c 0x00 0x00 + 0x184 0x0a 0x00 + 0x4c 0x15 0x00 + 0x50 0x34 0x00 + 0x54 0x00 0x00 + 0xc8 0x00 0x00 + 0x18c 0x00 0x00 + 0xcc 0x00 0x00 + 0x128 0x00 0x00 + 0x0c 0x0a 0x00 + 0x10 0x01 0x00 + 0x1c 0x31 0x00 + 0x20 0x01 0x00 + 0x14 0x00 0x00 + 0x18 0x00 0x00 + 0x24 0xde 0x00 + 0x28 0x07 0x00 + 0x48 0x0f 0x00 + 0x194 0x06 0x00 + 0x100 0x80 0x00 + 0xa8 0x01 0x00 + 0x430 0x0b 0x00 + 0x830 0x0b 0x00 + 0x444 0x00 0x00 + 0x844 0x00 0x00 + 0x43c 0x00 0x00 + 0x83c 0x00 0x00 + 0x440 0x00 0x00 + 0x840 0x00 0x00 + 0x408 0x0a 0x00 + 0x808 0x0a 0x00 + 0x414 0x06 0x00 + 0x814 0x06 0x00 + 0x434 0x75 0x00 + 0x834 0x75 0x00 + 0x4d4 0x02 0x00 + 0x8d4 0x02 0x00 + 0x4d8 0x4e 0x00 + 0x8d8 0x4e 0x00 + 0x4dc 0x18 0x00 + 0x8dc 0x18 0x00 + 0x4f8 0x77 0x00 + 0x8f8 0x77 0x00 + 0x4fc 0x80 0x00 + 0x8fc 0x80 0x00 + 0x4c0 0x0a 0x00 + 0x8c0 0x0a 0x00 + 0x504 0x03 0x00 + 0x904 0x03 0x00 + 0x50c 0x16 0x00 + 0x90c 0x16 0x00 + 0x500 0x00 0x00 + 0x900 0x00 0x00 + 0x564 0x00 0x00 + 0x964 0x00 0x00 + 0x260 0x10 0x00 + 0x660 0x10 0x00 + 0x2a4 0x12 0x00 + 0x6a4 0x12 0x00 + 0x28c 0xc6 0x00 + 0x68c 0xc6 0x00 + 0x244 0x00 0x00 + 0x644 0x00 0x00 + 0x248 0x00 0x00 + 0x648 0x00 0x00 + 0xc0c 0x9f 0x00 + 0xc24 0x17 0x00 + 0xc28 0x0f 0x00 + 0xcc8 0x83 0x00 + 0xcc4 0x02 0x00 + 0xccc 0x09 0x00 + 0xcd0 0xa2 0x00 + 0xcd4 0x85 0x00 + 0xc80 0xd1 0x00 + 0xc84 0x1f 0x00 + 0xc88 0x47 0x00 + 0xcb8 0x75 0x00 + 0xcbc 0x13 0x00 + 0xcb0 0x86 0x00 + 0xca0 0x04 0x00 + 0xc8c 0x44 0x00 + 0xc70 0xe7 0x00 + 0xc74 0x03 0x00 + 0xc78 0x40 0x00 + 0xc7c 0x00 0x00 + 0xdd8 0x88 0x00 + 0xffffffff 0xffffffff 0x00>; + + qcom,qmp-phy-reg-offset = + <0xd74 /* USB3_PHY_PCS_STATUS */ + 0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */ + 0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */ + 0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */ + 0xc00 /* USB3_PHY_SW_RESET */ + 0xc08 /* USB3_PHY_START */ + 0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */ + + clocks = <&clock_virt GCC_USB3_PRIM_PHY_AUX_CLK>, + <&clock_virt GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_gcc RPMH_CXO_CLK>, + <&clock_virt GCC_USB3_PRIM_CLKREF_CLK>, + <&clock_virt GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&clock_virt GCC_AHB2PHY_WEST_CLK>; + + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk", "cfg_ahb_clk"; + + resets = <&clock_virt GCC_USB3_PHY_PRIM_SP0_BCR>, + <&clock_virt GCC_USB3PHY_PHY_PRIM_SP0_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + status = "disabled"; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x172f 0x0>; + qcom,usb-audio-stream-id = <0xf>; + qcom,usb-audio-intr-num = <2>; + status = "disabled"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + /* Secondary USB port related controller */ + usb1: hsusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa800000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0xE0 0x0>; + qcom,smmu-s1-bypass; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <0 491 0>, <0 663 0>, <0 490 0>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&usb20_sec_gdsc>; + clocks = <&clock_virt GCC_USB20_SEC_MASTER_CLK>, + <&clock_virt GCC_CFG_NOC_USB2_SEC_AXI_CLK>, + <&clock_virt GCC_AGGRE_USB2_SEC_AXI_CLK>, + <&clock_virt GCC_USB3_SEC_CLKREF_CLK>, + <&clock_virt GCC_USB20_SEC_SLEEP_CLK>, + <&clock_virt GCC_USB20_SEC_MOCK_UTMI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "xo", "sleep_clk", "utmi_clk"; + + resets = <&clock_virt GCC_USB20_SEC_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <120000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + qcom,charging-disabled; + + status = "disabled"; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0xa800000 0xcd00>; + interrupts = <0 664 0>; + usb-phy = <&qusb_phy1>, <&usb_nop_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + usb-core-id = <1>; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + /* Secondary USB port related High Speed PHY */ + qusb_phy1: qusb@88e3000 { + compatible = "qcom,qusb2phy"; + reg = <0x88e3000 0x180>, + <0x01fcb3e4 0x4>; + reg-names = "qusb_phy_base", + "tcsr_conn_box_spare_0"; + + vdd-supply = <&pm6150_l4>; + vdda18-supply = <&pm6150_l11>; + vdda33-supply = <&pm6150_l17>; + qcom,vdd-voltage-level = <0 925000 975000>; + qcom,qusb-phy-init-seq = <0xc8 0x80 + 0xb3 0x84 + 0x83 0x88 + 0xc0 0x8c + 0x30 0x08 + 0x79 0x0c + 0x21 0x10 + 0x14 0x9c + 0x9f 0x1c + 0x00 0x18>; + phy_type = "utmi"; + qcom,phy-clk-scheme = "cml"; + qcom,major-rev = <1>; + qcom,hold-reset; + + /* USB2PHY gets clock directly from CXO pad + * connected to differential pin cxo_core_in_1p8_vdda. + */ + clocks = <&clock_gcc RPMH_CXO_CLK>, + <&clock_virt GCC_AHB2PHY_WEST_CLK>; + clock-names = "ref_clk_src", "cfg_ahb_clk"; + + resets = <&clock_virt GCC_QUSB2PHY_SEC_BCR>; + reset-names = "phy_reset"; + status = "disabled"; + }; + +}; diff --git a/arch/arm/boot/dts/qcom/sa6155p-vm.dts b/arch/arm/boot/dts/qcom/sa6155p-vm.dts new file mode 100644 index 000000000000..0caf78c1b2e6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155p-vm.dts @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa6155p-vm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P Virtual Machine"; + compatible = "qcom,sa6155p"; + qcom,pmic-name = "PM6150"; + qcom,board-id = <0 0>; +}; + +&slpi_tlmm { + status = "ok"; +}; + +&apps_smmu { + status = "ok"; +}; + +&usb0 { + status = "ok"; +}; + +&qusb_phy0 { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie0 { + status = "ok"; +}; + +&sdhc_2 { + status = "ok"; +}; + diff --git a/arch/arm/boot/dts/qcom/sa6155p-vm.dtsi b/arch/arm/boot/dts/qcom/sa6155p-vm.dtsi new file mode 100644 index 000000000000..7432a67530ed --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155p-vm.dtsi @@ -0,0 +1,351 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "skeleton64.dtsi" +#include +#include +#include +#include +#include "quin-vm-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P Virtual Machine"; + qcom,msm-name = "SA6155P"; + qcom,msm-id = <377 0x0>; + + aliases { + pci-domain0 = &pcie0; /* PCIe0 domain */ + }; + + aliases { + sdhc2 = &sdhc_2; /* SDC2 SD Card slot */ + }; + + reserved_memory: reserved-memory { + + pmem_shared: pmem_shared_region@a1600000 { + reg = <0x0 0xa1600000 0x0 0x20000000>; + label = "pmem_shared_mem"; + }; + }; +}; + +&soc { + clock_virt: qcom,virt-gcc { + compatible = "qcom,virt-clk-sm6150-gcc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_virt_scc: qcom,virt-scc { + compatible = "qcom,virt-clk-sm6150-scc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + apps_smmu: apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x80000>, + <0x150c2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + status = "disabled"; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + status = "ok"; + }; + + usb30_prim_gdsc: usb30_prim_gdsc { + compatible = "qcom,stub-regulator"; + regulator-name = "usb30_prim_gdsc"; + status = "ok"; + }; + + usb20_sec_gdsc: usb20_sec_gdsc { + compatible = "qcom,stub-regulator"; + regulator-name = "usb20_sec_gdsc"; + status = "ok"; + }; + + pm6150_l11: regulator-pm6150-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l11"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1890000>; + status = "ok"; + }; + + pm6150_l4: regulator-pm6150-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + status = "ok"; + }; + + pm6150_l17: regulator-pm6150-l17 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l17"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3230000>; + status = "ok"; + }; + + qcom_seecom: qseecom@86d00000 { + compatible = "qcom,qseecom"; + reg = <0x86d00000 0xe00000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,no-clock-support; + qcom,qsee-reentrancy-support = <2>; + }; + + pm6155_1_l10: regulator-pm6155-1-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6155_1_l10"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + status = "ok"; + }; + + pm6155_1_l2: regulator-pm6155-1-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6155_1_l2"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3100000>; + status = "ok"; + }; + + pm6155_1_l12: regulator-pm6155-1-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6155_1_l12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1890000>; + status = "ok"; + }; + + pm6155_1_l5: regulator-pm6155-1-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6155_1_l5"; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + status = "ok"; + }; + + VDD_CX_LEVEL: VDD_MX_LEVEL: S2A_LEVEL: + pm6155_1_s2_level: regulator-pm6155-1-s2-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6155_1_s2_level"; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + }; + + pcie_0_gdsc: pcie_0_gdsc { + compatible = "qcom,stub-regulator"; + regulator-name = "pcie_0_gdsc"; + status = "okay"; + }; + + vreg_wlan: vreg_wlan { + compatible = "qcom,stub-regulator"; + regulator-name = "vreg_wlan"; + }; + + cnss_pcie: qcom,cnss { + compatible = "qcom,cnss"; + wlan-en-gpio = <&tlmm 98 0>; + vdd-wlan-supply = <&vreg_wlan>; + reg = <0x10000000 0x10000000>, + <0x20000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + qcom,smmu-s1-enable; + qcom,notify-modem-status; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + qcom,wlan-rc-num = <0>; + qcom,wlan-ramdump-dynamic = <0x200000>; + + qcom,msm-bus,name = "msm-cnss"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, <1 512 0 0>, + /* Upto 200 Mbps */ + <45 512 41421 655360>, <1 512 41421 655360>, + /* Upto 400 Mbps */ + <45 512 98572 655360>, <1 512 98572 1600000>, + /* Upto 800 Mbps */ + <45 512 207108 1146880>, <1 512 207108 3124992>; + }; + + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x8804000 0x1000>; + reg-names = "hc_mem"; + interrupts = <0 204 0>, <0 222 0>; + interrupt-names = "hc_irq", "pwr_irq"; + qcom,bus-width = <4>; + qcom,large-address-bus; + qcom,clk-rates = <400000 20000000 25000000 + 50000000 100000000 202000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", + "SDR104"; + qcom,devfreq,freq-table = <50000000 202000000>; + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <81 512 0 0>, <1 608 0 0>, + /* 400 KB/s*/ + <81 512 1046 1600>, + <1 608 1600 1600>, + /* 20 MB/s */ + <81 512 52286 80000>, + <1 608 80000 80000>, + /* 25 MB/s */ + <81 512 65360 100000>, + <1 608 100000 100000>, + /* 50 MB/s */ + <81 512 130718 200000>, + <1 608 133320 133320>, + /* 100 MB/s */ + <81 512 261438 200000>, + <1 608 150000 150000>, + /* 200 MB/s */ + <81 512 261438 400000>, + <1 608 300000 300000>, + /* Max. bandwidth */ + <81 512 1338562 4096000>, + <1 608 1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100750000 200000000 4294967295>; + /* PM QoS */ + qcom,pm-qos-irq-type = "affine_irq"; + qcom,pm-qos-irq-latency = <67 67>; + qcom,pm-qos-cpu-groups = <0x3f 0xc0>; + qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>; + clocks = <&clock_virt GCC_SDCC2_AHB_CLK>, + <&clock_virt GCC_SDCC2_APPS_CLK>; + clock-names = "iface_clk", "core_clk"; + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642C 0x0 0x0 0x00010800 0x80040868>; + + vdd-supply = <&pm6155_1_l10>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + vdd-io-supply = <&pm6155_1_l2>; + qcom,vdd-io-voltage-level = <1800000 3100000>; + qcom,vdd-io-current-level = <0 22000>; + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on + &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off + &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + cd-gpios = <&tlmm 99 1>; + + status = "disabled"; + }; +}; + +#include "sa6155p-vm-pinctrl.dtsi" +#include "sm6150-slpi-pinctrl.dtsi" +#include "sa6155p-vm-qupv3.dtsi" +#include "sa6155p-vm-usb.dtsi" +#include "sa8155-vm-audio.dtsi" +#include "sa6155p-vm-pcie.dtsi" diff --git a/arch/arm/boot/dts/qcom/sa6155p.dts b/arch/arm/boot/dts/qcom/sa6155p.dts new file mode 100644 index 000000000000..980ec1b96776 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155p.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa6155p.dtsi" +#include "sa6155-cnss.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P SoC"; + compatible = "qcom,sa6155p"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa6155p.dtsi b/arch/arm/boot/dts/qcom/sa6155p.dtsi new file mode 100644 index 000000000000..48d82ceec6ba --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa6155p.dtsi @@ -0,0 +1,517 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm6150.dtsi" +#include "sa6155-pmic.dtsi" +#include "sa6155-display.dtsi" +#include "sm6150-camera-sensor-adp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA6155P"; + qcom,msm-name = "SA6155P"; + qcom,msm-id = <377 0>, <380 0>; + + aliases { + pci-domain0 = &pcie0; /* PCIe0 domain */ + }; +}; + +/* Delete second instance of pm6155 definitions for APQ version */ +&spmi_bus { + /delete-node/ qcom,pm6155@4; + /delete-node/ qcom,pm6155@5; +}; + +&soc { + /delete-node/ rpmh-regulator-modemlvl; + /delete-node/ rpmh-regulator-ldoc2; + /delete-node/ rpmh-regulator-ldoc3; + /delete-node/ rpmh-regulator-ldoc4; + /delete-node/ rpmh-regulator-ldoc13; + /delete-node/ rpmh-regulator-ldoc14; + /delete-node/ rpmh-regulator-ldoc16; + /delete-node/ rpmh-regulator-ldoc17; + /delete-node/ rpmh-regulator-ldoc18; + /delete-node/ bt_wcn3990; + + qcom,rmnet-ipa { + status="disabled"; + }; + qfprom: qfprom@780130 { + compatible = "qcom,qfprom"; + reg = <0x00780130 0x4>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + }; +}; + +&ipa_hw { + status="disabled"; +}; + +&pil_modem { + /delete-property/ vdd_mss-supply; +}; + +&qusb_phy0 { + reg = <0x88e2000 0x180>, + <0x007801f8 0x4>, + <0x01fcb3e4 0x4>; + reg-names = "qusb_phy_base", + "tune2_efuse_addr", + "tcsr_conn_box_spare_0"; + vdd-supply = <&L5A>; + vdda18-supply = <&L12A>; + vdda33-supply = <&L13A>; +}; + +&tpdm_west { + status = "disabled"; +}; + +&usb_qmp_phy { + vdd-supply = <&L5A>; + core-supply = <&L12A>; +}; + +&qusb_phy1 { + vdd-supply = <&L5A>; + vdda18-supply = <&L12A>; + vdda33-supply = <&L13A>; +}; + +&mdss_dsi0_pll { + /delete-property/ qcom,dsi-pll-ssc-en; +}; + +&slpi_tlmm { + status = "ok"; +}; + +&clock_gcc { + compatible = "qcom,gcc-sa6155", "syscon"; + /delete-property/ protected-clocks; +}; + +&clock_videocc { + compatible = "qcom,videocc-sa6155", "syscon"; +}; + +&clock_dispcc { + compatible = "qcom,dispcc-sa6155", "syscon"; +}; + +&clock_scc { + compatible = "qcom,scc-sa6155", "syscon"; + vdd_scc_cx-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&clock_camcc { + compatible = "qcom,camcc-sa6155", "syscon"; + vdd_mx-supply = <&VDD_CX_LEVEL>; +}; + +&clock_gpucc { + compatible = "qcom,gpucc-sa6155", "syscon"; + vdd_mx-supply = <&VDD_CX_LEVEL>; +}; + +&thermal_zones { + lmh-dcvs-00 { + trips { + active-config { + temperature = <105000>; + hysteresis = <40000>; + }; + }; + }; + + lmh-dcvs-01 { + trips { + active-config { + temperature = <105000>; + hysteresis = <40000>; + }; + }; + }; +}; + +/* GPU power level overrides */ +&msm_gpu { + /* + * Speed-bin zero is default speed bin. + * For rest of the speed bins, speed-bin value + * is calulated as FMAX/4.8 MHz round up to zero + * decimal places. + */ + qcom,gpu-pwrlevel-bins { + #address-cells = <1>; + #size-cells = <0>; + + compatible="qcom,gpu-pwrlevel-bins"; + + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <0>; + + qcom,initial-pwrlevel = <5>; + qcom,ca-target-pwrlevel = <3>; + + /* TURBO */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <845000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <745000000>; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <650000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <500000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <435000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <290000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <177>; + + qcom,initial-pwrlevel = <5>; + qcom,ca-target-pwrlevel = <3>; + + /* TURBO */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <845000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <745000000>; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <650000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <500000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <435000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <290000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <156>; + + qcom,initial-pwrlevel = <4>; + qcom,ca-target-pwrlevel = <2>; + + /* NOM L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <745000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <650000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <500000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <435000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <290000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-3 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <136>; + + qcom,initial-pwrlevel = <3>; + qcom,ca-target-pwrlevel = <1>; + + /* NOM */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <650000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <500000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <435000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <290000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-4 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <105>; + + qcom,initial-pwrlevel = <1>; + qcom,ca-target-pwrlevel = <2>; + + /* SVS L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <500000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <435000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <290000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-5 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <73>; + + qcom,initial-pwrlevel = <1>; + qcom,ca-target-pwrlevel = <0>; + + /* SVS */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <350000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <290000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + }; +}; + +/* Audio device tree */ +#include "sa6155-audio.dtsi" +#include "sa6155-pcie.dtsi" diff --git a/arch/arm/boot/dts/qcom/sa8155-adp-alcor-display.dtsi b/arch/arm/boot/dts/qcom/sa8155-adp-alcor-display.dtsi new file mode 100644 index 000000000000..7de3fa3b22ba --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-adp-alcor-display.dtsi @@ -0,0 +1,91 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&tlmm { + dp_hpd_cfg_pins: dp_hpd_cfg_pins { + mux { + pins = "gpio48"; + function = "gpio"; + }; + config { + pins = "gpio48"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + dp_redriver_en: dp_redriver_en { + mux { + pins = "gpio47"; + function = "gpio"; + }; + config { + pins = "gpio47"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; +}; + +&sde_dp { + qcom,ext-disp = <&ext_disp>; + qcom,dp-hpd-gpio = <&tlmm 48 0>; + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep", + "mdss_dp_hpd_active"; + pinctrl-0 = <&dp_hpd_cfg_pins &dp_redriver_en>; + pinctrl-1 = <&dp_hpd_cfg_pins &dp_redriver_en>; + pinctrl-2 = <&dp_hpd_cfg_pins &dp_redriver_en>; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + + refgen: refgen-regulator@88e7000 { + compatible = "qcom,refgen-regulator"; + reg = <0x88e7000 0x60>; + regulator-name = "refgen"; + regulator-enable-ramp-delay = <5>; + }; + + sde_wb: qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display"; + }; + + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; +}; + +&mdss_mdp { + connectors = <&sde_rscc &sde_dp &sde_wb>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-adp-alcor-overlay.dts b/arch/arm/boot/dts/qcom/sa8155-adp-alcor-overlay.dts new file mode 100644 index 000000000000..b720b0e75e41 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-adp-alcor-overlay.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include "sa8155-adp-alcor.dtsi" + +/ { + model = "ADP-ALCOR"; + compatible = "qcom,sa8155-adp-alcor", "qcom,sa8155", + "qcom,adp-alcor"; + qcom,board-id = <0x02000019 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-adp-alcor.dts b/arch/arm/boot/dts/qcom/sa8155-adp-alcor.dts new file mode 100644 index 000000000000..5b52009c8ea3 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-adp-alcor.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa8155-v2.dtsi" +#include "sa8155-adp-alcor.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155 ADP ALCOR"; + compatible = "qcom,sa8155-adp-alcor", "qcom,sa8155", "qcom,adp-alcor"; + qcom,board-id = <0x02000019 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-adp-alcor.dtsi b/arch/arm/boot/dts/qcom/sa8155-adp-alcor.dtsi new file mode 100644 index 000000000000..b069a273e75f --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-adp-alcor.dtsi @@ -0,0 +1,98 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sa8155-adp-common.dtsi" +#include "sa8155-adp-alcor-display.dtsi" + +&qupv3_se0_spi { + can-controller@0 { + qcom,use_qtimer = <1>; /* 0:Disable, 1:Enable */ + }; +}; + +&pcie1 { + qcom,boot-option = <0x0>; +}; + +&pcie_rc1 { + aqc_x4: aquantia,aqc107@pcie_rc1 { + reg = <0 0 0 0 0>; + compatible = "aquantia,aqc-107"; + pci-ids = + "1d6a:0001", + "1d6a:d107", + "1d6a:07b1", + "1d6a:87b1", + "1d6a:d108", + "1d6a:08b1", + "1d6a:88b1", + "1d6a:d109", + "1d6a:09b1", + "1d6a:89b1", + "1d6a:d100", + "1d6a:00b1", + "1d6a:80b1", + "1d6a:11b1", + "1d6a:91b1", + "1d6a:51b1", + "1d6a:12b1", + "1d6a:92b1", + "1d6a:52b1"; + + qcom,smmu; + qcom,smmu-iova-base = /bits/ 64 <0x20000000>; + qcom,smmu-iova-size = /bits/ 64 <0x40000000>; + + qcom,smmu-attr-atomic; + qcom,smmu-attr-s1-bypass; + }; +}; + +&pcie_rc1 { + nvme_x8: qcom,nvme@pcie_rc1 { + reg = <0 0 0 0 0>; + compatible = "qcom,nvme"; + pci-ids = + "8086:0953", + "8086:0a54", + "8086:0a55", + "8086:f1a5", + "8086:f1a5", + "1c58:0003", + "1c58:0023", + "1c5c:1327", + "1c5f:0540", + "144d:a821", + "144d:a822", + "144d:a808", + "1d1d:1f1f", + "1d1d:2807", + "1d1d:2601", + "106b:2001", + "106b:2003", + "1179:0115", + "1179:0116"; + + qcom,smmu; + qcom,smmu-iova-base = /bits/ 64 <0x20000000>; + qcom,smmu-iova-size = /bits/ 64 <0x40000000>; + + qcom,smmu-attr-atomic; + qcom,smmu-attr-s1-bypass; + }; +}; + +&qupv3_se10_i2c { + asm330@6a { + qcom,use_qtimer = <1>; /* 0:Disable 1:Enable */ + }; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-adp-common.dtsi b/arch/arm/boot/dts/qcom/sa8155-adp-common.dtsi new file mode 100644 index 000000000000..16e671cfb580 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-adp-common.dtsi @@ -0,0 +1,249 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "sa8155-pmic-overlay.dtsi" +#include "sa8155-cnss.dtsi" + +&qupv3_se0_spi { + status = "ok"; + + #address-cells = <1>; + #size-cells = <0>; + + can-controller@0 { + compatible = "qcom,nxp,mpc5746c"; + reg = <0>; + interrupt-parent = <&tlmm>; + interrupts = <38 0>; + spi-max-frequency = <5000000>; + qcom,clk-freq-mhz = <40000000>; + qcom,max-can-channels = <1>; + qcom,bits-per-word = <8>; + qcom,support-can-fd; + }; +}; + +&qupv3_se12_2uart { + status = "ok"; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + +&qupv3_se3_spi { + status = "disabled"; +}; + +&qupv3_se4_i2c { + status = "ok"; +}; + +&qupv3_se10_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + asm330@6a { + compatible = "st,asm330lhh"; + reg = <0x6a>; + vio-supply = <&pm8150_2_l7>; + vdd-supply = <&pm8150_2_l16>; + interrupt-parent = <&tlmm>; + interrupts = <41 IRQ_TYPE_EDGE_RISING>, + <42 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&sensor_int1_default + &sensor_int2_default>; + sensor_int1_default: sensor_int1_default { + pins = "gpio41"; + drive-strength = <16>; + bias-pull-up; + }; + sensor_int2_default: sensor_int2_default { + pins = "gpio42"; + drive-strength = <16>; + bias-pull-up; + }; + }; +}; + +&pil_modem { + status = "disabled"; +}; + +&soc { + qcom,lpass@17300000 { + status = "ok"; + qcom,pil-force-shutdown; + }; + + qcom,ssc@5c00000 { + status = "disabled"; + }; + + qcom,glink { + modem { + status = "disabled"; + }; + }; + + qcom,turing@8300000 { + status = "ok"; + }; + + qcom,venus@aae0000 { + status = "ok"; + }; + + qcom,spss@1880000 { + status = "ok"; + }; + + qcom,npu@0x9800000 { + status = "ok"; + }; + + qcom,rmnet-ipa { + status = "disabled"; + }; + + qcom,ipa_fws { + status = "disabled"; + }; + + qcom,msm-cdsp-loader { + status = "ok"; + }; + + ssc_sensors: qcom,msm-ssc-sensors { + status = "disabled"; + }; + + ipa_hw: qcom,ipa@1e00000 { + status = "disabled"; + }; + + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_home_default + &key_vol_up_default>; + + home { + label = "home"; + gpios = <&pm8150_1_gpios 1 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + + vol_up { + label = "volume_up"; + gpios = <&pm8150_1_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4"; + + vdda-pll-supply = <&pm8150_2_l8>; + vdda-phy-max-microamp = <87100>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8150_1_l10>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm8150_1_s4>; + vcc-max-microamp = <750000>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&pm8150_2_l5>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm8150_1_l17>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8150_2_l13>; + qcom,vdd-io-voltage-level = <1808000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on + &sdc2_cmd_on &sdc2_data_on &storage_cd_default>; + pinctrl-1 = <&sdc2_clk_off + &sdc2_cmd_off &sdc2_data_off &storage_cd_default>; + + cd-gpios = <&pm8150_1_gpios 4 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; + +&usb0 { + qcom,default-mode-none; + qcom,host-poweroff-in-pm-suspend; + dwc3@a600000 { + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + }; +}; + +&usb2_phy0 { + qcom,param-override-seq = + <0x43 0x70 + 0x01 0xb0>; + pinctrl-names = "default"; + pinctrl-0 = <&usb2phy_ac_en1_default>; +}; + +&usb_qmp_dp_phy { + status = "disabled"; +}; + +&usb1 { + status = "ok"; + qcom,default-mode-host; + qcom,host-poweroff-in-pm-suspend; +}; + +&usb2_phy1 { + qcom,param-override-seq = <0x01 0xb0>; + pinctrl-names = "default"; + pinctrl-0 = <&usb2phy_ac_en2_default>; +}; + +&shared_meta { + parts = "vbmeta,boot,system,vendor,dtbo"; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-adp-star-display.dtsi b/arch/arm/boot/dts/qcom/sa8155-adp-star-display.dtsi new file mode 100644 index 000000000000..1ab460283332 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-adp-star-display.dtsi @@ -0,0 +1,319 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&tlmm { + ioexp_intr_active: ioexp_intr_active { + mux { + pins = "gpio48"; + function = "gpio"; + }; + config { + pins = "gpio48"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + ioexp_reset_active: ioexp_reset_active { + mux { + pins = "gpio30"; + function = "gpio"; + }; + config { + pins = "gpio30"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; +}; + +&sde_dp { + qcom,ext-disp = <&ext_disp>; + qcom,dp-hpd-gpio = <&ioexp 8 0>; + + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; + pinctrl-0 = <&dp_hpd_cfg_pins>; + pinctrl-1 = <&dp_hpd_cfg_pins>; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; +}; + +&qupv3_se15_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + + pinctrl-0 = <&qupv3_se15_i2c_active + &ioexp_intr_active + &ioexp_reset_active>; + + ioexp: gpio@3e { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1509q"; + reg = <0x3e>; + interrupt-parent = <&tlmm>; + interrupts = <48 0>; + gpio-controller; + interrupt-controller; + semtech,probe-reset; + + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_hpd_cfg_pins + &dsi1_cdet_cfg_pins + &dsi2_hpd_cfg_pins + &dsi2_cdet_cfg_pins + &dp_hpd_cfg_pins>; + + dsi1_hpd_cfg_pins: gpio0-cfg { + pins = "gpio0"; + bias-pull-up; + }; + + dsi1_cdet_cfg_pins: gpio1-cfg { + pins = "gpio1"; + bias-pull-down; + }; + + dsi2_hpd_cfg_pins: gpio2-cfg { + pins = "gpio2"; + bias-pull-up; + }; + + dsi2_cdet_cfg_pins: gpio3-cfg { + pins = "gpio3"; + bias-pull-down; + }; + + dp_hpd_cfg_pins: gpio8-cfg { + pins = "gpio8"; + bias-pull-down; + }; + }; + + i2c-mux@77 { + compatible = "nxp,pca9542"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + anx_7625_1: anx7625@2c { + compatible = "analogix,anx7625"; + reg = <0x2c>; + interrupt-parent = <&ioexp>; + interrupts = <0 0>; + cbl_det-gpio = <&ioexp 1 0>; + power_en-gpio = <&tlmm 47 0>; + reset_n-gpio = <&tlmm 49 0>; + }; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + anx_7625_2: anx7625@2c { + compatible = "analogix,anx7625"; + reg = <0x2c>; + interrupt-parent = <&ioexp>; + interrupts = <2 0>; + cbl_det-gpio = <&ioexp 3 0>; + power_en-gpio = <&tlmm 87 0>; + reset_n-gpio = <&tlmm 29 0>; + }; + }; + }; +}; + +&anx_7625_1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + anx_7625_1_in: endpoint { + remote-endpoint = <&dsi_anx_7625_1_out>; + }; + }; + }; +}; + +&anx_7625_2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + anx_7625_2_in: endpoint { + remote-endpoint = <&dsi_anx_7625_2_out>; + }; + }; + }; +}; + +#include "dsi-panel-ext-bridge-1080p.dtsi" + +&dsi_ext_bridge_1080p { + qcom,mdss-dsi-ext-bridge = <0>; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1E 08 07 24 22 + 08 08 05 02 04 00 19 17]; + }; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + + dsi_anx_7625_1: qcom,dsi-display@17 { + label = "dsi_anx_7625_1"; + qcom,dsi-display-active; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_ext_bridge_1080p>; + }; + + dsi_anx_7625_2: qcom,dsi-display@18 { + label = "dsi_anx_7625_2"; + qcom,dsi-display-active; + qcom,display-type = "secondary"; + + qcom,dsi-ctrl-num = <1>; + qcom,dsi-phy-num = <1>; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,dsi-panel = <&dsi_ext_bridge_1080p>; + }; + + dsi_dp1: qcom,dsi-display@1 { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, + <&mdss_dsi0_pll PCLK_MUX_0_CLK>, + <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, + <&mdss_dsi1_pll PCLK_MUX_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,dsi-display-list = + <&dsi_anx_7625_1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_anx_7625_1_out: endpoint { + remote-endpoint = <&anx_7625_1_in>; + }; + }; + }; + }; + + dsi_dp2: qcom,dsi-display@2 { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, + <&mdss_dsi0_pll PCLK_MUX_0_CLK>, + <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, + <&mdss_dsi1_pll PCLK_MUX_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,dsi-display-list = + <&dsi_anx_7625_2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_anx_7625_2_out: endpoint { + remote-endpoint = <&anx_7625_2_in>; + }; + }; + }; + }; + + refgen: refgen-regulator@88e7000 { + compatible = "qcom,refgen-regulator"; + reg = <0x88e7000 0x60>; + regulator-name = "refgen"; + regulator-enable-ramp-delay = <5>; + }; + + sde_wb: qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display"; + }; + + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; +}; + +&mdss_dsi_phy0 { + qcom,panel-force-clock-lane-hs; +}; + +&mdss_dsi_phy1 { + qcom,panel-force-clock-lane-hs; +}; + +&mdss_mdp { + connectors = <&sde_rscc &dsi_dp1 &dsi_dp2 &sde_dp &sde_wb>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-adp-star-overlay.dts b/arch/arm/boot/dts/qcom/sa8155-adp-star-overlay.dts new file mode 100644 index 000000000000..4dd522713b20 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-adp-star-overlay.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include + +#include "sa8155-adp-star.dtsi" + +/ { + model = "ADP-STAR"; + compatible = "qcom,sa8155-adp-star", "qcom,sa8155", + "qcom,adp-star"; + qcom,board-id = <25 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-adp-star.dts b/arch/arm/boot/dts/qcom/sa8155-adp-star.dts new file mode 100644 index 000000000000..351ce2b1a19f --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-adp-star.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include "sa8155-v1.dtsi" +#include "sa8155-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155 ADP-STAR"; + compatible = "qcom,sa8155-adp-star", "qcom,sa8155", + "qcom,adp-star"; + qcom,board-id = <25 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-adp-star.dtsi b/arch/arm/boot/dts/qcom/sa8155-adp-star.dtsi new file mode 100644 index 000000000000..b1f546fbfc68 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-adp-star.dtsi @@ -0,0 +1,52 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sa8155-adp-common.dtsi" +#include "sa8155-adp-star-display.dtsi" + +&pcie1 { + qcom,boot-option = <0x0>; +}; + +&pcie_rc1 { + nvme_x8: qcom,nvme@pcie_rc1 { + reg = <0 0 0 0 0>; + compatible = "qcom,nvme"; + pci-ids = + "8086:0953", + "8086:0a54", + "8086:0a55", + "8086:f1a5", + "8086:f1a5", + "1c58:0003", + "1c58:0023", + "1c5c:1327", + "1c5f:0540", + "144d:a821", + "144d:a822", + "144d:a808", + "1d1d:1f1f", + "1d1d:2807", + "1d1d:2601", + "106b:2001", + "106b:2003", + "1179:0115", + "1179:0116"; + + qcom,smmu; + qcom,smmu-iova-base = /bits/ 64 <0x20000000>; + qcom,smmu-iova-size = /bits/ 64 <0x40000000>; + + qcom,smmu-attr-atomic; + qcom,smmu-attr-s1-bypass; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-audio.dtsi b/arch/arm/boot/dts/qcom/sa8155-audio.dtsi new file mode 100644 index 000000000000..8a0a1c793982 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-audio.dtsi @@ -0,0 +1,614 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tdm_pri_rx: qcom,msm-dai-tdm-pri-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37120>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36864 36866 36868 36870>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <0>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <1>; + qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>; + dai_pri_tdm_rx_0: qcom,msm-dai-q6-tdm-pri-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36864>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_1: qcom,msm-dai-q6-tdm-pri-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36866>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_2: qcom,msm-dai-q6-tdm-pri-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36868>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_3: qcom,msm-dai-q6-tdm-pri-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36870>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_pri_tx: qcom,msm-dai-tdm-pri-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37121>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36865 36867 36869 36871>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <0>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <1>; + qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>; + dai_pri_tdm_tx_0: qcom,msm-dai-q6-tdm-pri-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36865>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_1: qcom,msm-dai-q6-tdm-pri-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36867>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_2: qcom,msm-dai-q6-tdm-pri-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36869>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_3: qcom,msm-dai-q6-tdm-pri-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36871>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sec_rx: qcom,msm-dai-tdm-sec-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37136>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36880 36882 36884 + 36886 36894>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <0>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sec_tdm_active &sec_tdm_din_active + &sec_tdm_dout_active>; + pinctrl-1 = <&sec_tdm_sleep &sec_tdm_din_sleep + &sec_tdm_dout_sleep>; + dai_sec_tdm_rx_0: qcom,msm-dai-q6-tdm-sec-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36880>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_1: qcom,msm-dai-q6-tdm-sec-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36882>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_2: qcom,msm-dai-q6-tdm-sec-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36884>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_3: qcom,msm-dai-q6-tdm-sec-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36886>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_7: qcom,msm-dai-q6-tdm-sec-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36894>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_sec_tx: qcom,msm-dai-tdm-sec-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37137>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36881 36883 36885 36887>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <0>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sec_tdm_tx_0: qcom,msm-dai-q6-tdm-sec-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36881>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_1: qcom,msm-dai-q6-tdm-sec-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36883>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_2: qcom,msm-dai-q6-tdm-sec-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36885>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_3: qcom,msm-dai-q6-tdm-sec-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36887>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_tert_rx: qcom,msm-dai-tdm-tert-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37152>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36896 36898 36900 + 36902 36904>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&tert_tdm_active &tert_tdm_din_active + &tert_tdm_dout_active>; + pinctrl-1 = <&tert_tdm_sleep &tert_tdm_din_sleep + &tert_tdm_dout_sleep>; + dai_tert_tdm_rx_0: qcom,msm-dai-q6-tdm-tert-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36896>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_1: qcom,msm-dai-q6-tdm-tert-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36898>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_2: qcom,msm-dai-q6-tdm-tert-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36900>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_3: qcom,msm-dai-q6-tdm-tert-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36902>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_4: qcom,msm-dai-q6-tdm-tert-rx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36904>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_tert_tx: qcom,msm-dai-tdm-tert-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37153>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36897 36899 36901 + 36903 36911>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_tert_tdm_tx_0: qcom,msm-dai-q6-tdm-tert-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36897>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_1: qcom,msm-dai-q6-tdm-tert-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36899>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_2: qcom,msm-dai-q6-tdm-tert-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36901>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_3: qcom,msm-dai-q6-tdm-tert-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36903>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_7: qcom,msm-dai-q6-tdm-tert-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36911>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quat_rx: qcom,msm-dai-tdm-quat-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37168>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36912 36914 36916 + 36918 36926>; + qcom,msm-cpudai-tdm-lane-mask = /bits/ 16 <3>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&quat_tdm_active &quat_tdm_din_active + &quat_tdm_dout_active>; + pinctrl-1 = <&quat_tdm_sleep &quat_tdm_din_sleep + &quat_tdm_dout_sleep>; + dai_quat_tdm_rx_0: qcom,msm-dai-q6-tdm-quat-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36912>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_1: qcom,msm-dai-q6-tdm-quat-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36914>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_2: qcom,msm-dai-q6-tdm-quat-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36916>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_3: qcom,msm-dai-q6-tdm-quat-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36918>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + dai_quat_tdm_rx_7: qcom,msm-dai-q6-tdm-quat-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36926>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quat_tx: qcom,msm-dai-tdm-quat-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37169>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36913 36915 36917 + 36919 36927>; + qcom,msm-cpudai-tdm-lane-mask = /bits/ 16 <12>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_quat_tdm_tx_0: qcom,msm-dai-q6-tdm-quat-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36913>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_1: qcom,msm-dai-q6-tdm-quat-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36915>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_2: qcom,msm-dai-q6-tdm-quat-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36917>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_3: qcom,msm-dai-q6-tdm-quat-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36919>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_7: qcom,msm-dai-q6-tdm-quat-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36927>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quin_rx: qcom,msm-dai-tdm-quin-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37184>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36928 36930 36932 + 36934 36942>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&quin_tdm_active &quin_tdm_din_active + &quin_tdm_dout_active>; + pinctrl-1 = <&quin_tdm_sleep &quin_tdm_din_sleep + &quin_tdm_dout_sleep>; + dai_quin_tdm_rx_0: qcom,msm-dai-q6-tdm-quin-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36928>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_1: qcom,msm-dai-q6-tdm-quin-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36930>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_2: qcom,msm-dai-q6-tdm-quin-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36932>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_3: qcom,msm-dai-q6-tdm-quin-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36934>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + dai_quin_tdm_rx_7: qcom,msm-dai-q6-tdm-quin-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36942>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + tdm_quin_tx: qcom,msm-dai-tdm-quin-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37185>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36929 36931 36933 + 36935 36943>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_quin_tdm_tx_0: qcom,msm-dai-q6-tdm-quin-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36929>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_1: qcom,msm-dai-q6-tdm-quin-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36931>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_2: qcom,msm-dai-q6-tdm-quin-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36933>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_3: qcom,msm-dai-q6-tdm-quin-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36935>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + dai_quin_tdm_tx_7: qcom,msm-dai-q6-tdm-quin-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36943>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + dai_pri_auxpcm: qcom,msm-pri-auxpcm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pri_aux_pcm_clk_active &pri_aux_pcm_sync_active + &pri_aux_pcm_din_active &pri_aux_pcm_dout_active>; + pinctrl-1 = <&pri_aux_pcm_clk_sleep &pri_aux_pcm_sync_sleep + &pri_aux_pcm_din_sleep &pri_aux_pcm_dout_sleep>; + }; +}; + +&audio_apr { + q6core: qcom,q6core-audio { + compatible = "qcom,q6core-audio"; + }; + + snd_9360: sound-pahu { + status = "disabled"; + }; + + snd_934x: sound-tavil { + status = "disabled"; + }; +}; + +&q6core { + sound-adp-star { + compatible = "qcom,sa8155-asoc-snd-adp-star"; + qcom,model = "sa8155-adp-star-snd-card"; + qcom,mi2s-audio-intf; + qcom,auxpcm-audio-intf; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; + + qcom,sec-tdm-gpios = <&tdm_sec_rx>; + qcom,tert-tdm-gpios = <&tdm_tert_rx>; + qcom,quat-tdm-gpios = <&tdm_quat_rx>; + qcom,quin-tdm-gpios = <&tdm_quin_rx>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>, <&loopback1>, <&pcm_dtmf>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", + "msm-pcm-dtmf"; + asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_rx_1>, + <&dai_pri_tdm_rx_2>, <&dai_pri_tdm_rx_3>, + <&dai_pri_tdm_tx_0>, <&dai_pri_tdm_tx_1>, + <&dai_pri_tdm_tx_2>, <&dai_pri_tdm_tx_3>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_rx_1>, + <&dai_sec_tdm_rx_2>, <&dai_sec_tdm_rx_3>, + <&dai_sec_tdm_rx_7>, <&dai_sec_tdm_tx_0>, + <&dai_sec_tdm_tx_1>, <&dai_sec_tdm_tx_2>, + <&dai_sec_tdm_tx_3>, <&dai_tert_tdm_rx_0>, + <&dai_tert_tdm_rx_1>, <&dai_tert_tdm_rx_2>, + <&dai_tert_tdm_rx_3>, <&dai_tert_tdm_rx_4>, + <&dai_tert_tdm_tx_0>, <&dai_tert_tdm_tx_1>, + <&dai_tert_tdm_tx_2>, <&dai_tert_tdm_tx_3>, + <&dai_tert_tdm_tx_7>, <&dai_quat_tdm_rx_0>, + <&dai_quat_tdm_rx_1>, <&dai_quat_tdm_rx_2>, + <&dai_quat_tdm_rx_3>, <&dai_quat_tdm_rx_7>, + <&dai_quat_tdm_tx_0>, <&dai_quat_tdm_tx_1>, + <&dai_quat_tdm_tx_2>, <&dai_quat_tdm_tx_3>, + <&dai_quat_tdm_tx_7>, <&dai_quin_tdm_rx_0>, + <&dai_quin_tdm_rx_1>, <&dai_quin_tdm_rx_2>, + <&dai_quin_tdm_rx_3>, <&dai_quin_tdm_rx_7>, + <&dai_quin_tdm_tx_0>, <&dai_quin_tdm_tx_1>, + <&dai_quin_tdm_tx_2>, <&dai_quin_tdm_tx_3>, + <&dai_quin_tdm_tx_7>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", + "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", + "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", + "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", + "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36866", + "msm-dai-q6-tdm.36868", "msm-dai-q6-tdm.36870", + "msm-dai-q6-tdm.36865", "msm-dai-q6-tdm.36867", + "msm-dai-q6-tdm.36869", "msm-dai-q6-tdm.36871", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36882", + "msm-dai-q6-tdm.36884", "msm-dai-q6-tdm.36886", + "msm-dai-q6-tdm.36894", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36883", "msm-dai-q6-tdm.36885", + "msm-dai-q6-tdm.36887", "msm-dai-q6-tdm.36896", + "msm-dai-q6-tdm.36898", "msm-dai-q6-tdm.36900", + "msm-dai-q6-tdm.36902", "msm-dai-q6-tdm.36904", + "msm-dai-q6-tdm.36897", "msm-dai-q6-tdm.36899", + "msm-dai-q6-tdm.36901", "msm-dai-q6-tdm.36903", + "msm-dai-q6-tdm.36911", "msm-dai-q6-tdm.36912", + "msm-dai-q6-tdm.36914", "msm-dai-q6-tdm.36916", + "msm-dai-q6-tdm.36918", "msm-dai-q6-tdm.36926", + "msm-dai-q6-tdm.36913", "msm-dai-q6-tdm.36915", + "msm-dai-q6-tdm.36917", "msm-dai-q6-tdm.36919", + "msm-dai-q6-tdm.36927", "msm-dai-q6-tdm.36928", + "msm-dai-q6-tdm.36930", "msm-dai-q6-tdm.36932", + "msm-dai-q6-tdm.36934", "msm-dai-q6-tdm.36942", + "msm-dai-q6-tdm.36929", "msm-dai-q6-tdm.36931", + "msm-dai-q6-tdm.36933", "msm-dai-q6-tdm.36935", + "msm-dai-q6-tdm.36943"; + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>; + }; +}; + +&qupv3_se4_i2c { + status = "disabled"; +}; + +&qupv3_se20_i2c { + status = "ok"; + + pinctrl-0 = <&qupv3_se20_i2c_active + &audio_ioexp_reset_active>; + + gpio@3e { + compatible = "semtech,sx1509q"; + reg = <0x3e>; + semtech,probe-reset; + }; +}; + +&slim_aud { + status = "disabled"; + iommu_slim_aud_ctrl_cb { + status = "disabled"; + }; + msm_dai_slim { + status = "disabled"; + }; +}; + +&qupv3_se22_spi { + status = "ok"; + spi_codec@0 { + compatible = "qcom,spi-msm-codec-slave"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-cpha; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-camera-sensor.dtsi b/arch/arm/boot/dts/qcom/sa8155-camera-sensor.dtsi new file mode 100644 index 000000000000..9bac609b3b04 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-camera-sensor.dtsi @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&cam_cci0 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&pm8150_1_s4>; + cam_bob-supply = <&pm8150_1_s4>; + cam_vana-supply = <&pm8150_1_s4>; + cam_vdig-supply = <&pm8150_1_s4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + gpios = <&tlmm 13 0>, + <&tlmm 21 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_bob-supply = <&pm8150_1_s4>; + cam_vdig-supply = <&pm8150_1_s4>; + cam_vio-supply = <&pm8150_1_s4>; + cam_vana-supply = <&pm8150_1_s4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + gpios = <&tlmm 14 0>, + <&tlmm 22 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&pm8150_1_s4>; + cam_bob-supply = <&pm8150_1_s4>; + cam_vana-supply = <&pm8150_1_s4>; + cam_vdig-supply = <&pm8150_1_s4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + gpios = <&tlmm 15 0>, + <&tlmm 23 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x03>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&pm8150_1_s4>; + cam_bob-supply = <&pm8150_1_s4>; + cam_vana-supply = <&pm8150_1_s4>; + cam_vdig-supply = <&pm8150_1_s4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + gpios = <&tlmm 16 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-cnss.dtsi b/arch/arm/boot/dts/qcom/sa8155-cnss.dtsi new file mode 100644 index 000000000000..2fa828eba6fc --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-cnss.dtsi @@ -0,0 +1,350 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + /* Rome 3.3V supply */ + vreg_wlan: vreg_wlan { + compatible = "qcom,stub-regulator"; + regulator-name = "vreg_wlan"; + }; + + /* PWR_CTR2_VDD_1P8 supply */ + vreg_conn_1p8: vreg_conn_1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p8"; + pinctrl-names = "default"; + pinctrl-0 = <&conn_power_1p8_active>; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm 173 0>; + }; + + /* PWR_CTR1_VDD_PA supply */ + vreg_conn_pa: vreg_conn_pa { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_pa"; + pinctrl-names = "default"; + pinctrl-0 = <&conn_power_pa_active>; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm 174 0>; + }; + + bluetooth: bt_qca6174 { + compatible = "qca,qca6174"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_active>; + /* BT_EN */ + qca,bt-reset-gpio = <&tlmm 172 0>; + /* PWR_CTR1_VDD_PA */ + qca,bt-vdd-pa-supply = <&vreg_conn_pa>; + /* PWR_CTR2_VDD_1P8 */ + qca,bt-chip-pwd-supply = <&vreg_conn_1p8>; + qca,bt-vdd-vl-supply = <&pm8150_1_s6>; + qca,bt-vdd-vm-supply = <&pm8150_2_s4>; + qca,bt-vdd-5c-supply = <&pm8150_2_s5>; + qca,bt-vdd-vh-supply = <&pm8150_2_l15>; + + qca,bt-vdd-vl-voltage-level = <1055000 1055000>; + qca,bt-vdd-vm-voltage-level = <1370000 1370000>; + qca,bt-vdd-5c-voltage-level = <2040000 2040000>; + qca,bt-vdd-vh-voltage-level = <1900000 1900000>; + + qca,bt-vdd-vl-current-level = <0>; + qca,bt-vdd-vm-current-level = <0>; + qca,bt-vdd-5c-current-level = <0>; + qca,bt-vdd-vh-current-level = <450000>; + }; + + qcom,cnss-qca6390@a0000000 { + status = "disabled"; + }; + + cnss_pcie: qcom,cnss-qca-converged { + compatible = "qcom,cnss-qca-converged"; + + qcom,converged-dt; + qcom,wlan-rc-num = <0>; + qcom,bus-type=<0>; + qcom,notify-modem-status; + qcom,msm-bus,name = "msm-cnss"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, <1 512 0 0>, + /* Upto 200 Mbps */ + <45 512 41421 655360>, <1 512 41421 655360>, + /* Upto 400 Mbps */ + <45 512 98572 655360>, <1 512 98572 1600000>, + /* Upto 800 Mbps */ + <45 512 207108 1146880>, <1 512 207108 3124992>; + + #address-cells=<1>; + #size-cells=<1>; + ranges = <0x10000000 0x10000000 0x10000000>, + <0x20000000 0x20000000 0x10000>, + <0xa0000000 0xa0000000 0x10000000>, + <0xb0000000 0xb0000000 0x10000>; + + vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; + vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>; + vdd-wlan-supply = <&vreg_wlan>; + vdd-wlan-aon-supply = <&pm8150_1_s6>; + vdd-wlan-rfa1-supply = <&pm8150_2_s4>; + vdd-wlan-rfa2-supply = <&pm8150_2_s5>; + vdd-wlan-rfa3-supply = <&pm8150_2_l15>; + + wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2"; + qcom,vdd-wlan-ctrl1-info = <0 0 0 0>; + qcom,vdd-wlan-ctrl2-info = <0 0 0 0>; + wlan-en-gpio = <&tlmm 169 0>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + + chip_cfg@0 { + reg = <0x10000000 0x10000000>, + <0x20000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + + supported-ids = <0x003e>; + wlan_vregs = "vdd-wlan"; + qcom,vdd-wlan-info = <0 0 0 10>; + + qcom,smmu-s1-enable; + qcom,wlan-ramdump-dynamic = <0x200000>; + }; + + chip_cfg@1 { + reg = <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + + supported-ids = <0x1101>; + wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", + "vdd-wlan-rfa2", "vdd-wlan-rfa3"; + qcom,vdd-wlan-aon-info = <1055000 1055000 0 0>; + qcom,vdd-wlan-rfa1-info = <1370000 1370000 0 0>; + qcom,vdd-wlan-rfa2-info = <2040000 2040000 0 0>; + qcom,vdd-wlan-rfa3-info = <1900000 1900000 450000 0>; + + qcom,wlan-ramdump-dynamic = <0x400000>; + mhi,max-channels = <30>; + mhi,timeout = <10000>; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + }; + + chip_cfg@2 { + reg = <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + + supported-ids = <0x1102>; + wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", + "vdd-wlan-rfa2", "vdd-wlan-rfa3"; + qcom,vdd-wlan-aon-info = <1055000 1055000 0 0>; + qcom,vdd-wlan-rfa1-info = <1370000 1370000 0 0>; + qcom,vdd-wlan-rfa2-info = <2040000 2040000 0 0>; + qcom,vdd-wlan-rfa3-info = <1900000 1900000 0 0>; + + qcom,wlan-ramdump-dynamic = <0x300000>; + mhi,max-channels = <30>; + mhi,timeout = <10000>; + mhi,ee = <0x3>, <0x4>; + mhi,ee-names = "SBL", "RDDM"; + mhi,bhie-offset = <0x0324>; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@16 { + reg = <16>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@17 { + reg = <17>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-pmic-overlay.dtsi b/arch/arm/boot/dts/qcom/sa8155-pmic-overlay.dtsi new file mode 100644 index 000000000000..eac33fe3888a --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-pmic-overlay.dtsi @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "pm8150.dtsi" + +pm8150_1_tz: &pm8150_tz { +}; + +pm8150_1_clkdiv: &pm8150_clkdiv { + clock-output-names = "pm8150_1_div_clk1", "pm8150_1_div_clk2"; +}; + +pm8150_1_rtc: &pm8150_rtc { +}; + +pm8150_1_gpios: &pm8150_gpios { + interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>, + <0x0 0xc2 0 IRQ_TYPE_NONE>, + <0x0 0xc3 0 IRQ_TYPE_NONE>, + <0x0 0xc5 0 IRQ_TYPE_NONE>, + <0x0 0xc8 0 IRQ_TYPE_NONE>, + <0x0 0xc9 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8150_1_gpio1", "pm8150_1_gpio3", + "pm8150_1_gpio4", "pm8150_1_gpio6", + "pm8150_1_gpio9", "pm8150_1_gpio10"; + qcom,gpios-disallowed = <2 5 7 8>; +}; + +/* PM8150_2: */ +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + + qcom,pm8150@4 { + compatible = "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + }; + + pm8150_2_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00 0x200>; + #clock-cells = <1>; + qcom,num-clkdivs = <2>; + clock-output-names = "pm8150_2_div_clk1", + "pm8150_2_div_clk2"; + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + }; + + pm8150_2_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0xa00>; + interrupts = <0x4 0xc0 0 IRQ_TYPE_NONE>, + <0x4 0xc2 0 IRQ_TYPE_NONE>, + <0x4 0xc3 0 IRQ_TYPE_NONE>, + <0x4 0xc5 0 IRQ_TYPE_NONE>, + <0x4 0xc7 0 IRQ_TYPE_NONE>, + <0x4 0xc8 0 IRQ_TYPE_NONE>, + <0x4 0xc9 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8150_2_gpio1", "pm8150_2_gpio3", + "pm8150_2_gpio4", "pm8150_2_gpio6", + "pm8150_2_gpio8", "pm8150_2_gpio9", + "pm8150_2_gpio10"; + gpio-controller; + #gpio-cells = <2>; + qcom,gpios-disallowed = <2 5 7>; + }; + }; + + qcom,pm8150@5 { + compatible ="qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +/* PMIC GPIO pin control configurations: */ +&pm8150_1_gpios { + key_home { + key_home_default: key_home_default { + pins = "gpio1"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; + + storage_sd_detect { + storage_cd_default: storage_cd_default { + pins = "gpio4"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; + + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-regulator.dtsi b/arch/arm/boot/dts/qcom/sa8155-regulator.dtsi new file mode 100644 index 000000000000..33e45516d62d --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-regulator.dtsi @@ -0,0 +1,726 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + /* RPMh regulators: */ + + rpmh-regulator-smpa4 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpa4"; + S4A: pm8150_1_s4: regulator-pm8150-1-s4 { + regulator-name = "pm8150_1_s4"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + }; + }; + + rpmh-regulator-smpa5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpa5"; + S5A: pm8150_1_s5: regulator-pm8150-1-s5 { + regulator-name = "pm8150_1_s5"; + qcom,set = ; + regulator-min-microvolt = <1824000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1824000>; + }; + }; + + rpmh-regulator-smpa6 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpa6"; + S6A: pm8150_1_s6: regulator-pm8150-1-s6 { + regulator-name = "pm8150_1_s6"; + qcom,set = ; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1352000>; + qcom,init-voltage = <600000>; + }; + }; + + rpmh-regulator-smpa7 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpa7"; + S7A: pm8150_1_s7: regulator-pm8150-1-s7 { + regulator-name = "pm8150_1_s7"; + qcom,set = ; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + qcom,init-voltage = <600000>; + }; + }; + + /* PM8150_1 S8 = VDD_MODEM supply */ + rpmh-regulator-msslvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "mss.lvl"; + S1A_LEVEL: pm8150_1_s8_level: regulator-pm8150-1-s8-level { + regulator-name = "pm8150_1_s8_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + rpmh-regulator-ldoa1 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L1A: pm8150_1_l1: regulator-pm8150-1-l1 { + regulator-name = "pm8150_1_l1"; + qcom,set = ; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + qcom,init-voltage = <752000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa2 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L2A: pm8150_1_l2: regulator-pm8150-1-l2 { + regulator-name = "pm8150_1_l2"; + qcom,set = ; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + qcom,init-voltage = <3072000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa3 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L3A: pm8150_1_l3: regulator-pm8150-1-l3 { + regulator-name = "pm8150_1_l3"; + qcom,set = ; + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <932000>; + qcom,init-voltage = <480000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + + L5A: pm8150_1_l5: regulator-pm8150-1-l5 { + regulator-name = "pm8150_1_l5"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <888000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + + L5A_AO: pm8150_1_l5_ao: regulator-pm8150-1-l5-ao { + regulator-name = "pm8150_1_l5_ao"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <888000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + + regulator-pm8150-1-l5-so { + regulator-name = "pm8150_1_l5_so"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <888000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + qcom,init-enable = <0>; + }; + }; + + rpmh-regulator-ldoa6 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L6A: pm8150_1_l6: regulator-pm8150-1-l6 { + regulator-name = "pm8150_1_l6"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa7 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L7A: pm8150_1_l7: regulator-pm8150-1-l7 { + regulator-name = "pm8150_1_l7"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa10 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L10A: pm8150_1_l10: regulator-pm8150-1-l10 { + regulator-name = "pm8150_1_l10"; + qcom,set = ; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <2504000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa11 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L11A: pm8150_1_l11: regulator-pm8150-1-l11 { + regulator-name = "pm8150_1_l11"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa12 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L12A: pm8150_1_l12: regulator-pm8150-1-l12 { + regulator-name = "pm8150_1_l12"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + + L12A_AO: pm8150_1_l12_ao: regulator-pm8150-1-l12-ao { + regulator-name = "pm8150_1_l12_ao"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + + regulator-pm8150-1-l12-so { + regulator-name = "pm8150_1_l12_so"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + qcom,init-enable = <0>; + }; + }; + + rpmh-regulator-ldoa13 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L13A: pm8150_1_l13: regulator-pm8150-1-l13 { + regulator-name = "pm8150_1_l13"; + qcom,set = ; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + qcom,init-voltage = <2704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa15 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa15"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L15A: pm8150_1_l15: regulator-pm8150-1-l15 { + regulator-name = "pm8150_1_l15"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1704000>; + qcom,init-voltage = <1704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa16 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L16A: pm8150_1_l16: regulator-pm8150-1-l16 { + regulator-name = "pm8150_1_l16"; + qcom,set = ; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <2704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa17 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L17A: pm8150_1_l17: regulator-pm8150-1-l17 { + regulator-name = "pm8150_1_l17"; + qcom,set = ; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <2704000>; + qcom,init-mode = ; + }; + }; + + /* PM8150_2 S3 + S2 + S1 = 3 phase VDD_GFX supply */ + rpmh-regulator-gfxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "gfx.lvl"; + S3C_LEVEL: pm8150_2_s3_level: regulator-pm8150-2-s3-level { + regulator-name = "pm8150_2_s3_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + rpmh-regulator-smpc4 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpc4"; + S4C: pm8150_2_s4: regulator-pm8150-2-s4 { + regulator-name = "pm8150_2_s4"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + qcom,init-voltage = <800000>; + }; + }; + + rpmh-regulator-smpc5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpc5"; + S5C: pm8150_2_s5: regulator-pm8150-2-s5 { + regulator-name = "pm8150_2_s5"; + qcom,set = ; + regulator-min-microvolt = <1824000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1824000>; + }; + }; + + rpmh-regulator-smpc6 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpc6"; + S6C: pm8150_2_s6: regulator-pm8150-2-s6 { + regulator-name = "pm8150_2_s6"; + qcom,set = ; + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + qcom,init-voltage = <1128000>; + }; + }; + + /* PM8150_2 S9 + S8 + S7 = VDD_CX supply */ + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "cx.lvl"; + pm8150_2_s9_level-parent-supply = <&VDD_MX_LEVEL>; + pm8150_2_s9_level_ao-parent-supply = <&VDD_MX_LEVEL_AO>; + + VDD_CX_LEVEL: VDD_MMCX_LEVEL: + S9C_LEVEL: pm8150_2_s9_level: regulator-pm8150-2-s9-level { + regulator-name = "pm8150_2_s9_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + + VDD_CX_LEVEL_AO: VDD_MMCX_LEVEL_AO: S9C_LEVEL_AO: + pm8150_2_s9_level_ao: regulator-pm8150-2-s9-level-ao { + regulator-name = "pm8150_2_s9_level_ao"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + + cx_cdev: regulator-cdev { + compatible = "qcom,rpmh-reg-cdev"; + mboxes = <&qmp_aop 0>; + qcom,reg-resource-name = "cx"; + #cooling-cells = <2>; + }; + }; + + /* PM8150_2 S10 = VDD_MX supply */ + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "mx.lvl"; + + VDD_MX_LEVEL: + S10C_LEVEL: pm8150_2_s10_level: regulator-pm8150-2-s10-level { + regulator-name = "pm8150_2_s10_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + VDD_MX_LEVEL_AO: S10C_LEVEL_AO: + pm8150_2_s10_level_ao: regulator-pm8150-2-s10-level-ao { + regulator-name = "pm8150_2_s10_level_ao"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + mx_cdev: mx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&VDD_MX_LEVEL>; + regulator-levels = ; + #cooling-cells = <2>; + }; + }; + + rpmh-regulator-ldoc1 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L1C: pm8150_2_l1: regulator-pm8150-2-l1 { + regulator-name = "pm8150_2_l1"; + qcom,set = ; + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1304000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc2 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L2C: pm8150_2_l2: regulator-pm8150-2-l2 { + regulator-name = "pm8150_2_l2"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + qcom,init-voltage = <1704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L5C: pm8150_2_l5: regulator-pm8150-2-l5 { + regulator-name = "pm8150_2_l5"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc7 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L7C: pm8150_2_l7: regulator-pm8150-2-l7 { + regulator-name = "pm8150_2_l7"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc8 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc8"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L8C: pm8150_2_l8: regulator-pm8150-2-l8 { + regulator-name = "pm8150_2_l8"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + /* PM8150_2 L11 = VDD_EBI supply */ + rpmh-regulator-ebilvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ebi.lvl"; + L11C_LEVEL: pm8150_2_l11_level: regulator-pm8150-2-l11-level { + regulator-name = "pm8150_2_l11_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + ebi_cdev: regulator-cdev { + compatible = "qcom,rpmh-reg-cdev"; + mboxes = <&qmp_aop 0>; + qcom,reg-resource-name = "ebi"; + #cooling-cells = <2>; + }; + }; + + rpmh-regulator-ldoc12 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L12C: pm8150_2_l12: regulator-pm8150-2-l12 { + regulator-name = "pm8150_2_l12"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1888000>; + qcom,init-voltage = <1704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc13 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L13C: pm8150_2_l13: regulator-pm8150-2-l13 { + regulator-name = "pm8150_2_l13"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc15 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc15"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L15C: pm8150_2_l15: regulator-pm8150-2-l15 { + regulator-name = "pm8150_2_l15"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc16 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L16C: pm8150_2_l16: regulator-pm8150-2-l16 { + regulator-name = "pm8150_2_l16"; + qcom,set = ; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3008000>; + qcom,init-voltage = <2704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc18 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc18"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + proxy-supply = <&pm8150_2_l18>; + L18C: pm8150_2_l18: regulator-pm8150-2-l18 { + regulator-name = "pm8150_2_l18"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <23800>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-v1.dtsi b/arch/arm/boot/dts/qcom/sa8155-v1.dtsi new file mode 100644 index 000000000000..24b43228ab9c --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-v1.dtsi @@ -0,0 +1,21 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm8150.dtsi" +#include "sa8155.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155"; + compatible = "qcom,sa8155"; + qcom,msm-name = "SA8155 V1"; + qcom,msm-id = <362 0x10000>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-v2-adp-air-overlay.dts b/arch/arm/boot/dts/qcom/sa8155-v2-adp-air-overlay.dts new file mode 100644 index 000000000000..8c51bb3a1019 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-v2-adp-air-overlay.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include "sa8155-adp-common.dtsi" +#include "sa8155-adp-star-display.dtsi" + +/ { + model = "ADP-AIR"; + compatible = "qcom,sa8155-v2-adp-air", "qcom,sa8155", + "qcom,adp-air"; + qcom,board-id = <0X01000019 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-v2-adp-air.dts b/arch/arm/boot/dts/qcom/sa8155-v2-adp-air.dts new file mode 100644 index 000000000000..0cdfaf5a8da6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-v2-adp-air.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa8155-v2.dtsi" +#include "sa8155-adp-common.dtsi" +#include "sa8155-adp-star-display.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155 V2 ADP AIR"; + compatible = "qcom,sa8155-v2-adp-air", "qcom,sa8155", "qcom,adp-air"; + qcom,board-id = <0x01000019 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-v2-adp-star.dts b/arch/arm/boot/dts/qcom/sa8155-v2-adp-star.dts new file mode 100644 index 000000000000..7f411ed1e62e --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-v2-adp-star.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa8155-v2.dtsi" +#include "sa8155-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155 V2 ADP STAR"; + compatible = "qcom,sa8155-adp-star", "qcom,sa8155", "qcom,adp-star"; + qcom,board-id = <25 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-v2.dts b/arch/arm/boot/dts/qcom/sa8155-v2.dts new file mode 100644 index 000000000000..321b22c54ef5 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-v2.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa8155-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155 v2 SoC"; + compatible = "qcom,sa8155"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; + +&android_q_fstab { + /delete-node/ odm; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-v2.dtsi b/arch/arm/boot/dts/qcom/sa8155-v2.dtsi new file mode 100644 index 000000000000..b43385b399fb --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-v2.dtsi @@ -0,0 +1,147 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm8150-v2.dtsi" +#include "sa8155.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155 V2"; + qcom,msm-name = "SA8155 V2"; + qcom,msm-id = <362 0x20000>; +}; + +&emac_hw { + emac-core-version = <4>; + early-ethernet-en; +}; + +&ufsphy_mem { + vdda-phy-supply = <&pm8150_1_l5>; +}; + +/* GPU frequency overrides */ +&soc { + gpu_opp_table_v2: gpu_opp_table_v2 { + compatible = "operating-points-v2"; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = ; + }; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; + opp-microvolt = ; + }; + + opp-585000000 { + opp-hz = /bits/ 64 <585000000>; + opp-microvolt = ; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = ; + }; + + opp-427000000 { + opp-hz = /bits/ 64 <427000000>; + opp-microvolt = ; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + opp-microvolt = ; + }; + + opp-257000000 { + opp-hz = /bits/ 64 <257000000>; + opp-microvolt = ; + }; + + }; +}; + +/* GPU power level overrides */ +&msm_gpu { + qcom,initial-pwrlevel = <4>; + /delete-node/qcom,gpu-pwrlevel-bins; + qcom,gpu-pwrlevels { + compatible = "qcom,gpu-pwrlevels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <700000000>; + qcom,bus-freq = <10>; + qcom,bus-min = <8>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <675000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <585000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <500000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <427000000>; + qcom,bus-freq = <6>; + qcom,bus-min = <5>; + qcom,bus-max = <9>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <345000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <3>; + qcom,bus-max = <8>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <257000000>; + qcom,bus-freq = <2>; + qcom,bus-min = <1>; + qcom,bus-max = <8>; + }; + + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-vm-audio.dtsi b/arch/arm/boot/dts/qcom/sa8155-vm-audio.dtsi new file mode 100644 index 000000000000..e101ced50d9d --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-vm-audio.dtsi @@ -0,0 +1,534 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msm-audio-lpass.dtsi" + +&soc { + qcom,msm-dai-tdm-pri-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37120>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36864 36866 36868 36870>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <0>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <1>; + qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>; + dai_pri_tdm_rx_0: qcom,msm-dai-q6-tdm-pri-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36864>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_1: qcom,msm-dai-q6-tdm-pri-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36866>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_2: qcom,msm-dai-q6-tdm-pri-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36868>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_rx_3: qcom,msm-dai-q6-tdm-pri-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36870>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-pri-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37121>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36865 36867 36869 36871>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <0>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <1>; + qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>; + dai_pri_tdm_tx_0: qcom,msm-dai-q6-tdm-pri-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36865>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_1: qcom,msm-dai-q6-tdm-pri-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36867>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_2: qcom,msm-dai-q6-tdm-pri-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36869>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_pri_tdm_tx_3: qcom,msm-dai-q6-tdm-pri-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36871>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-sec-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37136>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36880 36882 36884 + 36886 36894>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <0>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sec_tdm_rx_0: qcom,msm-dai-q6-tdm-sec-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36880>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_1: qcom,msm-dai-q6-tdm-sec-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36882>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_2: qcom,msm-dai-q6-tdm-sec-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36884>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_3: qcom,msm-dai-q6-tdm-sec-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36886>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_rx_7: qcom,msm-dai-q6-tdm-sec-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36894>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-sec-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37137>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36881 36883 36885 36887>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <0>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sec_tdm_tx_0: qcom,msm-dai-q6-tdm-sec-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36881>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_1: qcom,msm-dai-q6-tdm-sec-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36883>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_2: qcom,msm-dai-q6-tdm-sec-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36885>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_sec_tdm_tx_3: qcom,msm-dai-q6-tdm-sec-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36887>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-tert-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37152>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36896 36898 36900 + 36902 36904>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_tert_tdm_rx_0: qcom,msm-dai-q6-tdm-tert-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36896>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_1: qcom,msm-dai-q6-tdm-tert-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36898>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_2: qcom,msm-dai-q6-tdm-tert-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36900>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_3: qcom,msm-dai-q6-tdm-tert-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36902>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_rx_4: qcom,msm-dai-q6-tdm-tert-rx-4 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36904>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-tert-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37153>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36897 36899 36901 + 36903 36911>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_tert_tdm_tx_0: qcom,msm-dai-q6-tdm-tert-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36897>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_1: qcom,msm-dai-q6-tdm-tert-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36899>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_2: qcom,msm-dai-q6-tdm-tert-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36901>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_3: qcom,msm-dai-q6-tdm-tert-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36903>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_tert_tdm_tx_7: qcom,msm-dai-q6-tdm-tert-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36911>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-quat-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37168>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36912 36914 36916 + 36918 36926>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + qcom,msm-cpudai-tdm-lane-mask = /bits/ 16 <3>; + dai_quat_tdm_rx_0: qcom,msm-dai-q6-tdm-quat-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36912>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_1: qcom,msm-dai-q6-tdm-quat-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36914>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_2: qcom,msm-dai-q6-tdm-quat-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36916>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_rx_3: qcom,msm-dai-q6-tdm-quat-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36918>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + dai_quat_tdm_rx_7: qcom,msm-dai-q6-tdm-quat-rx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36926>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-quat-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37169>; + qcom,msm-cpudai-tdm-group-num-ports = <5>; + qcom,msm-cpudai-tdm-group-port-id = <36913 36915 36917 + 36919 36927>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + qcom,msm-cpudai-tdm-lane-mask = /bits/ 16 <12>; + dai_quat_tdm_tx_0: qcom,msm-dai-q6-tdm-quat-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36913>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_1: qcom,msm-dai-q6-tdm-quat-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36915>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_2: qcom,msm-dai-q6-tdm-quat-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36917>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_3: qcom,msm-dai-q6-tdm-quat-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36919>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quat_tdm_tx_7: qcom,msm-dai-q6-tdm-quat-tx-7 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36927>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-quin-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37184>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36928 36930 36932 36934>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_quin_tdm_rx_0: qcom,msm-dai-q6-tdm-quin-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36928>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_1: qcom,msm-dai-q6-tdm-quin-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36930>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_2: qcom,msm-dai-q6-tdm-quin-rx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36932>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_rx_3: qcom,msm-dai-q6-tdm-quin-rx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36934>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-quin-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37185>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36929 36931 36933 36935>; + qcom,msm-cpudai-tdm-clk-rate = <24576000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_quin_tdm_tx_0: qcom,msm-dai-q6-tdm-quin-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36929>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_1: qcom,msm-dai-q6-tdm-quin-tx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36931>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_2: qcom,msm-dai-q6-tdm-quin-tx-2 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36933>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + dai_quin_tdm_tx_3: qcom,msm-dai-q6-tdm-quin-tx-3 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36935>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,avtimer@170f7000 { + compatible = "qcom,avtimer"; + reg = <0x170f700c 0x4>, + <0x170f7010 0x4>; + reg-names = "avtimer_lsb_addr", "avtimer_msb_addr"; + qcom,clk-div = <192>; + qcom,clk-mult = <10>; + }; +}; + +&audio_apr { + q6core: qcom,q6core-audio { + compatible = "qcom,q6core-audio"; + }; +}; + +&q6core { + sound-adp-star { + compatible = "qcom,sa8155-asoc-snd-adp-star"; + qcom,model = "sa8155-adp-star-snd-card"; + qcom,mi2s-audio-intf; + qcom,auxpcm-audio-intf; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>, <&loopback1>, <&pcm_dtmf>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq", "msm-pcm-loopback.1", + "msm-pcm-dtmf"; + asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_rx_1>, + <&dai_pri_tdm_rx_2>, <&dai_pri_tdm_rx_3>, + <&dai_pri_tdm_tx_0>, <&dai_pri_tdm_tx_1>, + <&dai_pri_tdm_tx_2>, <&dai_pri_tdm_tx_3>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_rx_1>, + <&dai_sec_tdm_rx_2>, <&dai_sec_tdm_rx_3>, + <&dai_sec_tdm_rx_7>, <&dai_sec_tdm_tx_0>, + <&dai_sec_tdm_tx_1>, <&dai_sec_tdm_tx_2>, + <&dai_sec_tdm_tx_3>, <&dai_tert_tdm_rx_0>, + <&dai_tert_tdm_rx_1>, <&dai_tert_tdm_rx_2>, + <&dai_tert_tdm_rx_3>, <&dai_tert_tdm_rx_4>, + <&dai_tert_tdm_tx_0>, <&dai_tert_tdm_tx_1>, + <&dai_tert_tdm_tx_2>, <&dai_tert_tdm_tx_3>, + <&dai_tert_tdm_tx_7>, <&dai_quat_tdm_rx_0>, + <&dai_quat_tdm_rx_1>, <&dai_quat_tdm_rx_2>, + <&dai_quat_tdm_rx_3>, <&dai_quat_tdm_rx_7>, + <&dai_quat_tdm_tx_0>, <&dai_quat_tdm_tx_1>, + <&dai_quat_tdm_tx_2>, <&dai_quat_tdm_tx_3>, + <&dai_quat_tdm_tx_7>, <&dai_quin_tdm_rx_0>, + <&dai_quin_tdm_rx_1>, <&dai_quin_tdm_rx_2>, + <&dai_quin_tdm_rx_3>, <&dai_quin_tdm_tx_0>, + <&dai_quin_tdm_tx_1>, <&dai_quin_tdm_tx_2>, + <&dai_quin_tdm_tx_3>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", + "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", + "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", + "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", + "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36866", + "msm-dai-q6-tdm.36868", "msm-dai-q6-tdm.36870", + "msm-dai-q6-tdm.36865", "msm-dai-q6-tdm.36867", + "msm-dai-q6-tdm.36869", "msm-dai-q6-tdm.36871", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36882", + "msm-dai-q6-tdm.36884", "msm-dai-q6-tdm.36886", + "msm-dai-q6-tdm.36894", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36883", "msm-dai-q6-tdm.36885", + "msm-dai-q6-tdm.36887", "msm-dai-q6-tdm.36896", + "msm-dai-q6-tdm.36898", "msm-dai-q6-tdm.36900", + "msm-dai-q6-tdm.36902", "msm-dai-q6-tdm.36904", + "msm-dai-q6-tdm.36897", "msm-dai-q6-tdm.36899", + "msm-dai-q6-tdm.36901", "msm-dai-q6-tdm.36903", + "msm-dai-q6-tdm.36911", "msm-dai-q6-tdm.36912", + "msm-dai-q6-tdm.36914", "msm-dai-q6-tdm.36916", + "msm-dai-q6-tdm.36918", "msm-dai-q6-tdm.36926", + "msm-dai-q6-tdm.36913", "msm-dai-q6-tdm.36915", + "msm-dai-q6-tdm.36917", "msm-dai-q6-tdm.36919", + "msm-dai-q6-tdm.36927", "msm-dai-q6-tdm.36928", + "msm-dai-q6-tdm.36930", "msm-dai-q6-tdm.36932", + "msm-dai-q6-tdm.36934", "msm-dai-q6-tdm.36929", + "msm-dai-q6-tdm.36931", "msm-dai-q6-tdm.36933", + "msm-dai-q6-tdm.36935"; + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>; + }; +}; + diff --git a/arch/arm/boot/dts/qcom/sa8155-vm-la-mt.dts b/arch/arm/boot/dts/qcom/sa8155-vm-la-mt.dts new file mode 100644 index 000000000000..ad4132c52f38 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-vm-la-mt.dts @@ -0,0 +1,30 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa8155-vm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155 Virtual Machine"; + compatible = "qcom,sa8155"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; + +&slpi_tlmm { + status = "ok"; +}; + +&apps_smmu { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-vm-lv-mt.dts b/arch/arm/boot/dts/qcom/sa8155-vm-lv-mt.dts new file mode 100644 index 000000000000..c2a9e394cbaa --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-vm-lv-mt.dts @@ -0,0 +1,59 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa8155-vm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155 Virtual Machine"; + compatible = "qcom,sa8155"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; + +&hab { + vmid = <3>; +}; + +&slpi_tlmm { + status = "ok"; +}; + +&apps_smmu { + status = "ok"; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + +&usb0 { + status = "ok"; +}; + +&usb2_phy0 { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie0 { + status = "ok"; +}; + +&sde_kms_hyp { + /delete-property/ qcom,client-id; + qcom,client-id = "7816"; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-vm-lv.dts b/arch/arm/boot/dts/qcom/sa8155-vm-lv.dts new file mode 100644 index 000000000000..28aa9ce98841 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-vm-lv.dts @@ -0,0 +1,47 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa8155-vm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155 Virtual Machine"; + compatible = "qcom,sa8155"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; + +&slpi_tlmm { + status = "ok"; +}; + +&apps_smmu { + status = "ok"; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + +&usb0 { + status = "ok"; +}; + +&usb2_phy0 { + status = "ok"; +}; + +&sde_kms_hyp { + /delete-property/ qcom,client-id; + qcom,client-id = "7816"; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-vm-mhi.dtsi b/arch/arm/boot/dts/qcom/sa8155-vm-mhi.dtsi new file mode 100644 index 000000000000..285f9cd79b28 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-vm-mhi.dtsi @@ -0,0 +1,551 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&pcie_rc0 { + reg = <0 0 0 0 0>; + + mhi_1: qcom,mhi@0 { + reg = <0 0 0 0 0 >; + + pci-ids = "17cb:0305", "17cb:0306"; + + /* controller specific configuration */ + qcom,smmu-cfg = <0x3>; + qcom,msm-bus,name = "mhi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 1200000000 650000000>; + + /* mhi bus specific settings */ + mhi,max-channels = <110>; + mhi,timeout = <2000>; + + #address-cells = <1>; + #size-cells = <0>; + + mhi_channels { + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@2 { + reg = <2>; + label = "SAHARA"; + mhi,num-elements = <128>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x2>; + }; + + mhi_chan@3 { + reg = <3>; + label = "SAHARA"; + mhi,num-elements = <128>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x2>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@8 { + reg = <8>; + label = "QDSS"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@9 { + reg = <9>; + label = "QDSS"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@10 { + reg = <10>; + label = "EFS"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@11 { + reg = <11>; + label = "EFS"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,wake-capable; + }; + + mhi_chan@14 { + reg = <14>; + label = "QMI0"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@15 { + reg = <15>; + label = "QMI0"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@16 { + reg = <16>; + label = "QMI1"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@17 { + reg = <17>; + label = "QMI1"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@18 { + reg = <18>; + label = "IP_CTRL"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@19 { + reg = <19>; + label = "IP_CTRL"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,auto-queue; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,auto-queue; + mhi,auto-start; + }; + + mhi_chan@22 { + reg = <22>; + label = "TF"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@23 { + reg = <23>; + label = "TF"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@25 { + reg = <25>; + label = "BL"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x2>; + mhi,auto-queue; + mhi,auto-start; + }; + + mhi_chan@26 { + reg = <26>; + label = "DCI"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@27 { + reg = <27>; + label = "DCI"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@32 { + reg = <32>; + label = "DUN"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@33 { + reg = <33>; + label = "DUN"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@100 { + reg = <100>; + label = "IP_HW0"; + mhi,num-elements = <512>; + mhi,event-ring = <4>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <3>; + mhi,ee = <0x4>; + mhi,db-mode-switch; + }; + + mhi_chan@101 { + reg = <101>; + label = "IP_HW0"; + mhi,num-elements = <512>; + mhi,event-ring = <5>; + mhi,chan-dir = <2>; + mhi,data-type = <4>; + mhi,doorbell-mode = <3>; + mhi,ee = <0x4>; + }; + + mhi_chan@102 { + reg = <102>; + label = "IP_HW_ADPL"; + mhi,event-ring = <6>; + mhi,chan-dir = <2>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + mhi,lpm-notify; + }; + + mhi_chan@103 { + reg = <103>; + label = "IP_HW_QDSS"; + mhi,num-elements = <128>; + mhi,event-ring = <7>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@104 { + reg = <104>; + label = "IP_HW_OFFLOAD_0"; + mhi,event-ring = <4>; + mhi,chan-dir = <1>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + }; + + mhi_chan@105 { + reg = <105>; + label = "IP_HW_OFFLOAD_0"; + mhi,event-ring = <5>; + mhi,chan-dir = <2>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + mhi,lpm-notify; + }; + + mhi_chan@107 { + reg = <107>; + label = "IP_HW_MHIP_1"; + mhi,event-ring = <10>; + mhi,chan-dir = <1>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + }; + + mhi_chan@108 { + reg = <108>; + label = "IP_HW_MHIP_1"; + mhi,event-ring = <11>; + mhi,chan-dir = <2>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + mhi,lpm-notify; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@2 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <3>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@3 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <4>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@4 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <5>; + mhi,chan = <100>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + }; + + mhi_event@5 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <6>; + mhi,chan = <101>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + }; + + mhi_event@6 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <7>; + mhi,chan = <102>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_event@7 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <8>; + mhi,chan = <103>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,hw-ev; + }; + + mhi_event@8 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <9>; + mhi,chan = <105>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_event@9 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <10>; + mhi,chan = <106>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_event@10 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <11>; + mhi,chan = <107>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_event@11 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <12>; + mhi,chan = <108>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + }; + + mhi_devices { + mhi_netdev_2: mhi_rmnet@0 { + reg = <0x0>; + mhi,chan = "IP_HW0"; + mhi,interface-name = "rmnet_mhi"; + mhi,mru = <0x8000>; + mhi,chan-skb; + }; + mhi_rmnet@1 { + reg = <0x1>; + mhi,chan = "IP_HW0_RSC"; + mhi,mru = <0x8000>; + mhi,rsc-parent = <&mhi_netdev_2>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-vm-pcie.dtsi b/arch/arm/boot/dts/qcom/sa8155-vm-pcie.dtsi new file mode 100644 index 000000000000..7f9595fb3cdd --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-vm-pcie.dtsi @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + pcie0: qcom,pcie@1c00000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x1c00000 0x4000>, + <0x1c06000 0x1000>, + <0x60000000 0xf1d>, + <0x60000f20 0xa8>, + <0x60001000 0x1000>, + <0x60100000 0x100000>, + <0x60200000 0x100000>, + <0x60300000 0x3d00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>; + interrupts = <0 140 0>, <0 149 0>, <0 150 0>, <0 151 0>, + <0 152 0>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + + qcom,phy-sequence = <0x0840 0x03 0x0 + 0x0094 0x08 0x0 + 0x0154 0x34 0x0 + 0x016c 0x08 0x0 + 0x0058 0x0f 0x0 + 0x00a4 0x42 0x0 + 0x0110 0x24 0x0 + 0x011c 0x03 0x0 + 0x0118 0xb4 0x0 + 0x010c 0x02 0x0 + 0x01bc 0x11 0x0 + 0x00bc 0x82 0x0 + 0x00d4 0x03 0x0 + 0x00d0 0x55 0x0 + 0x00cc 0x55 0x0 + 0x00b0 0x1a 0x0 + 0x00ac 0x0a 0x0 + 0x00c4 0x68 0x0 + 0x00e0 0x02 0x0 + 0x00dc 0xaa 0x0 + 0x00d8 0xab 0x0 + 0x00b8 0x34 0x0 + 0x00b4 0x14 0x0 + 0x0158 0x01 0x0 + 0x0074 0x06 0x0 + 0x007c 0x16 0x0 + 0x0084 0x36 0x0 + 0x0078 0x06 0x0 + 0x0080 0x16 0x0 + 0x0088 0x36 0x0 + 0x01b0 0x1e 0x0 + 0x01ac 0xb9 0x0 + 0x01b8 0x18 0x0 + 0x01b4 0x94 0x0 + 0x0050 0x07 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x029c 0x12 0x0 + 0x0284 0x35 0x0 + 0x023c 0x11 0x0 + 0x051c 0x03 0x0 + 0x0518 0x1c 0x0 + 0x0524 0x1e 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x05b4 0x04 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0510 0x17 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x04fc 0x00 0x0 + 0x04f8 0xc0 0x0 + 0x0460 0x30 0x0 + 0x0464 0xc0 0x0 + 0x05bc 0x0c 0x0 + 0x04dc 0x0d 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x09a4 0x01 0x0 + 0x0c90 0x00 0x0 + 0x0c40 0x01 0x0 + 0x0c48 0x01 0x0 + 0x0c50 0x00 0x0 + 0x0cbc 0x00 0x0 + 0x0ce0 0x58 0x0 + 0x0048 0x90 0x0 + 0x0c1c 0xc1 0x0 + 0x0988 0x88 0x0 + 0x0998 0x0b 0x0 + 0x08dc 0x0d 0x0 + 0x09ec 0x01 0x0 + 0x0800 0x00 0x0 + 0x0844 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + + perst-gpio = <&tlmm 35 0>; + wake-gpio = <&tlmm 37 0>; + + gdsc-vdd-supply = <&pcie_0_gdsc>; + vreg-1.8-supply = <&pm8150_2_l8>; + vreg-0.9-supply = <&pm8150_2_l18>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0.9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + msi-parent = <&pcie0_msi>; + + qcom,no-l0s-supported; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x4000000>; + + qcom,phy-status-offset = <0x814>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x840>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <0>; + + qcom,pcie-phy-ver = <2110>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x1d80>; + + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>, + <0x200 &apps_smmu 0x1d82 0x1>, + <0x300 &apps_smmu 0x1d83 0x1>, + <0x400 &apps_smmu 0x1d84 0x1>, + <0x500 &apps_smmu 0x1d85 0x1>, + <0x600 &apps_smmu 0x1d86 0x1>, + <0x700 &apps_smmu 0x1d87 0x1>, + <0x800 &apps_smmu 0x1d88 0x1>, + <0x900 &apps_smmu 0x1d89 0x1>, + <0xa00 &apps_smmu 0x1d8a 0x1>, + <0xb00 &apps_smmu 0x1d8b 0x1>, + <0xc00 &apps_smmu 0x1d8c 0x1>, + <0xd00 &apps_smmu 0x1d8d 0x1>, + <0xe00 &apps_smmu 0x1d8e 0x1>, + <0xf00 &apps_smmu 0x1d8f 0x1>; + + qcom,msm-bus,name = "pcie0"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 500 800>; + + clocks = <&clock_virt GCC_PCIE_0_PIPE_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_virt GCC_PCIE_0_AUX_CLK>, + <&clock_virt GCC_PCIE_0_CFG_AHB_CLK>, + <&clock_virt GCC_PCIE_0_MSTR_AXI_CLK>, + <&clock_virt GCC_PCIE_0_SLV_AXI_CLK>, + <&clock_virt GCC_PCIE_0_CLKREF_CLK>, + <&clock_virt GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&clock_virt GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&clock_virt GCC_PCIE0_PHY_REFGEN_CLK>, + <&clock_virt GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&clock_virt GCC_PCIE_0_BCR>, + <&clock_virt GCC_PCIE_0_PHY_BCR>; + + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + status = "disabled"; + + pcie_rc0: pcie_rc0 { + reg = <0 0 0 0 0>; + }; + }; + + pcie0_msi: qcom,pcie0_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-vm-pinctrl.dtsi b/arch/arm/boot/dts/qcom/sa8155-vm-pinctrl.dtsi new file mode 100644 index 000000000000..919fcc057493 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-vm-pinctrl.dtsi @@ -0,0 +1,25 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tlmm: pinctrl@03000000 { + compatible = "qcom,sm8150-pinctrl"; + reg = <0x03000000 0xdc2000>; + reg-names = "pinctrl"; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + diff --git a/arch/arm/boot/dts/qcom/sa8155-vm-qupv3.dtsi b/arch/arm/boot/dts/qcom/sa8155-vm-qupv3.dtsi new file mode 100644 index 000000000000..dd9bc5819ec8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-vm-qupv3.dtsi @@ -0,0 +1,960 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + /* QUPv3 South Instances */ + qupv3_0: qcom,qupv3_0_geni_se@8c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x8c0000 0x6000>; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; + qcom,iommu-s1-bypass; + + iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0xc3 0x0>; + }; + }; + + /* I2C */ + qupv3_se0_i2c: i2c@880000 { + compatible = "qcom,i2c-geni"; + reg = <0x880000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP0_S0_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@884000 { + compatible = "qcom,i2c-geni"; + reg = <0x884000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP0_S1_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@888000 { + compatible = "qcom,i2c-geni"; + reg = <0x888000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP0_S2_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@88c000 { + compatible = "qcom,i2c-geni"; + reg = <0x88c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP0_S3_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@890000 { + compatible = "qcom,i2c-geni"; + reg = <0x890000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP0_S4_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@894000 { + compatible = "qcom,i2c-geni"; + reg = <0x894000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP0_S5_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@898000 { + compatible = "qcom,i2c-geni"; + reg = <0x898000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP0_S6_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se7_i2c: i2c@89c000 { + compatible = "qcom,i2c-geni"; + reg = <0x89c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP0_S7_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se0_spi: spi@880000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x880000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP0_S0_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_spi: spi@884000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x884000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP0_S1_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_spi: spi@888000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x888000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP0_S2_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se3_spi: spi@88c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x88c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP0_S3_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se4_spi: spi@890000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x890000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP0_S4_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se5_spi: spi@894000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x894000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP0_S5_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se6_spi: spi@898000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x898000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP0_S6_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se7_spi: spi@89c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x89c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP0_S7_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_active>; + pinctrl-1 = <&qupv3_se7_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* QUPv3 North & East Instances + * North 0 : SE 8 + * North 1 : SE 9 + * North 2 : SE 10 + * North 3 : SE 11 + * North 4 : SE 12 + * North 5 : SE 16 + * East 0 : SE 17 + * East 1 : SE 18 + * East 2 : SE 19 + * East 3 : SE 13 + * East 4 : SE 14 + * East 5 : SE 15 + */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0xac0000 0x6000>; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; + qcom,iommu-s1-bypass; + + iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0x603 0x0>; + }; + }; + + /* 2-wire UART */ + + /* Debug UART Instance for CDP/MTP platform */ + qupv3_se12_2uart: qcom,qup_uart@0xa90000 { + compatible = "qcom,msm-geni-console"; + reg = <0xa90000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP1_S4_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_2uart_active>; + pinctrl-1 = <&qupv3_se12_2uart_sleep>; + interrupts = ; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* 4-wire UART */ + qupv3_se13_4uart: qcom,qup_uart@0xc8c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xc8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP2_S3_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "active", "sleep"; + pinctrl-0 = <&qupv3_se13_default_ctsrtsrx>, + <&qupv3_se13_default_tx>; + pinctrl-1 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>, + <&qupv3_se13_tx>; + pinctrl-2 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>, + <&qupv3_se13_tx>; + interrupts = ; + qcom,wrapper-core = <&qupv3_2>; + qcom,wakeup-byte = <0xFD>; + status = "disabled"; + }; + + /* I2C */ + qupv3_se8_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP1_S0_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP1_S1_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se10_i2c: i2c@a88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP1_S2_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_i2c_active>; + pinctrl-1 = <&qupv3_se10_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se11_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP1_S3_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_i2c_active>; + pinctrl-1 = <&qupv3_se11_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se12_i2c: i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP1_S4_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_i2c_active>; + pinctrl-1 = <&qupv3_se12_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se13_i2c: i2c@c8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xc8c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP2_S3_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_i2c_active>; + pinctrl-1 = <&qupv3_se13_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se8_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa80000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP1_S0_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_spi_active>; + pinctrl-1 = <&qupv3_se8_spi_active>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se9_spi: spi@a84000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa84000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP1_S1_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se10_spi: spi@a88000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa88000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP1_S2_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_spi_active>; + pinctrl-1 = <&qupv3_se10_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se11_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP1_S3_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_spi_active>; + pinctrl-1 = <&qupv3_se11_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se12_spi: spi@a90000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa90000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP1_S4_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_spi_active>; + pinctrl-1 = <&qupv3_se12_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se13_spi: spi@c8c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP2_S3_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_spi_active>; + pinctrl-1 = <&qupv3_se13_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + /* QUPv3 East Instances */ + qupv3_2: qcom,qupv3_2_geni_se@cc0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0xcc0000 0x6000>; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; + qcom,iommu-s1-bypass; + + iommu_qupv3_2_geni_se_cb: qcom,iommu_qupv3_2_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0x7a3 0x0>; + }; + }; + + /* I2C */ + qupv3_se14_i2c: i2c@0xc90000 { + compatible = "qcom,i2c-geni"; + reg = <0xc90000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP2_S4_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_i2c_active>; + pinctrl-1 = <&qupv3_se14_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se15_i2c: i2c@0xc94000 { + compatible = "qcom,i2c-geni"; + reg = <0xc94000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP2_S5_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_i2c_active>; + pinctrl-1 = <&qupv3_se15_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se16_i2c: i2c@0xa94000 { + compatible = "qcom,i2c-geni"; + reg = <0xa94000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP1_S5_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se16_i2c_active>; + pinctrl-1 = <&qupv3_se16_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se17_i2c: i2c@0xc80000 { + compatible = "qcom,i2c-geni"; + reg = <0xc80000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP2_S0_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se17_i2c_active>; + pinctrl-1 = <&qupv3_se17_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se18_i2c: i2c@0xc84000 { + compatible = "qcom,i2c-geni"; + reg = <0xc84000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP2_S1_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se18_i2c_active>; + pinctrl-1 = <&qupv3_se18_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se19_i2c: i2c@0xc88000 { + compatible = "qcom,i2c-geni"; + reg = <0xc88000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP2_S2_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se19_i2c_active>; + pinctrl-1 = <&qupv3_se19_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se14_spi: spi@c90000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc90000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP2_S4_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_spi_active>; + pinctrl-1 = <&qupv3_se14_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se15_spi: spi@c94000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc94000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP2_S5_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_spi_active>; + pinctrl-1 = <&qupv3_se15_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se16_spi: spi@a94000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa94000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP1_S5_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se16_spi_active>; + pinctrl-1 = <&qupv3_se16_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se17_spi: spi@c80000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc80000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP2_S0_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se17_spi_active>; + pinctrl-1 = <&qupv3_se17_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se18_spi: spi@c84000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc84000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP2_S1_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se18_spi_active>; + pinctrl-1 = <&qupv3_se18_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se19_spi: spi@c88000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc88000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt GCC_QUPV3_WRAP2_S2_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_virt GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se19_spi_active>; + pinctrl-1 = <&qupv3_se19_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + /* QUPv3 SSC Instances */ + qupv3_3: qcom,qupv3_3_geni_se@26c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x26c0000 0x6000>; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; + qcom,iommu-s1-bypass; + + iommu_qupv3_3_geni_se_cb: qcom,iommu_qupv3_3_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0x4e3 0x0>; + }; + }; + + /* I2C */ + qupv3_se20_i2c: i2c@2680000 { + compatible = "qcom,i2c-geni"; + reg = <0x2680000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt_scc SCC_QUPV3_SE0_CLK>, + <&clock_virt_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_virt_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se20_i2c_active>; + pinctrl-1 = <&qupv3_se20_i2c_sleep>; + qcom,wrapper-core = <&qupv3_3>; + status = "disabled"; + }; + + qupv3_se21_i2c: i2c@2684000 { + compatible = "qcom,i2c-geni"; + reg = <0x2684000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt_scc SCC_QUPV3_SE1_CLK>, + <&clock_virt_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_virt_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se21_i2c_active>; + pinctrl-1 = <&qupv3_se21_i2c_sleep>; + qcom,wrapper-core = <&qupv3_3>; + status = "disabled"; + }; + + qupv3_se22_i2c: i2c@2688000 { + compatible = "qcom,i2c-geni"; + reg = <0x2688000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt_scc SCC_QUPV3_SE2_CLK>, + <&clock_virt_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_virt_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se22_i2c_active>; + pinctrl-1 = <&qupv3_se22_i2c_sleep>; + qcom,wrapper-core = <&qupv3_3>; + status = "disabled"; + }; + + qupv3_se23_i2c: i2c@268c000 { + compatible = "qcom,i2c-geni"; + reg = <0x268c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt_scc SCC_QUPV3_SE3_CLK>, + <&clock_virt_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_virt_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se23_i2c_active>; + pinctrl-1 = <&qupv3_se23_i2c_sleep>; + qcom,wrapper-core = <&qupv3_3>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se21_spi: spi@2684000 { + compatible = "qcom,spi-geni"; + reg = <0x2684000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt_scc SCC_QUPV3_SE1_CLK>, + <&clock_virt_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_virt_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se21_spi_active>; + pinctrl-1 = <&qupv3_se21_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_3>; + status = "disabled"; + }; + + qupv3_se22_spi: spi@2688000 { + compatible = "qcom,spi-geni"; + reg = <0x2688000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_virt_scc SCC_QUPV3_SE2_CLK>, + <&clock_virt_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_virt_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se22_spi_active>; + pinctrl-1 = <&qupv3_se22_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_3>; + qcom,disable-dma; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-vm-usb.dtsi b/arch/arm/boot/dts/qcom/sa8155-vm-usb.dtsi new file mode 100644 index 000000000000..5e79647ad0f3 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-vm-usb.dtsi @@ -0,0 +1,542 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +&soc { + /* Primary USB port related controller */ + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a600000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x140 0x0>; + qcom,smmu-s1-bypass; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <0 489 0>, <0 130 0>, <0 486 0>, <0 488 0>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&usb30_prim_gdsc>; + dpdm-supply = <&usb2_phy0>; + clocks = <&clock_virt GCC_USB30_PRIM_MASTER_CLK>, + <&clock_virt GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&clock_virt GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&clock_virt GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&clock_virt GCC_USB30_PRIM_SLEEP_CLK>, + <&clock_virt GCC_USB3_PRIM_CLKREF_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&clock_virt GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + + status = "disabled"; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0x0a600000 0xcd00>; + interrupts = <0 133 0>; + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,ssp-u3-u0-quirk; + snps,usb3-u1u2-disable; + usb-core-id = <0>; + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + + usbbam: qcom,usbbam@a704000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa704000 0x17000>; + interrupts = <0 132 0>; + + qcom,usb-bam-fifo-baseaddr = <0x146bb000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + status = "disabled"; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + /* Primary USB port related High Speed PHY */ + usb2_phy0: hsphy@88e2000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e2000 0x110>, + <0x007801f8 0x4>; + reg-names = "hsusb_phy_base", + "phy_rcal_reg"; + + vdd-supply = <&pm8150_l5>; + vdda18-supply = <&pm8150_l12>; + vdda33-supply = <&pm8150_l2>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&clock_gcc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&clock_virt GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70>; + qcom,rcal-mask = <0x1e00000>; + + status = "disabled"; + }; + + /* Primary USB port related QMP USB DP Combo PHY */ + usb_qmp_dp_phy: ssphy@88e8000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88e8000 0x3000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&pm8150_l5>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&pm8150l_l3>; + qcom,vbus-valid-override; + qcom,link-training-reset; + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + + clocks = <&clock_virt GCC_USB3_PRIM_PHY_AUX_CLK>, + <&clock_virt GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_gcc RPMH_CXO_CLK>, + <&clock_virt GCC_USB3_PRIM_CLKREF_CLK>, + <&clock_virt GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&clock_virt GCC_USB3_DP_PHY_PRIM_BCR>, + <&clock_virt GCC_USB3_PHY_PRIM_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + + status = "disabled"; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x1b2f 0x0>; + qcom,usb-audio-stream-id = <0xf>; + qcom,usb-audio-intr-num = <2>; + status = "disabled"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + /* Secondary USB port related controller */ + usb1: ssusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a800000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x160 0x0>; + qcom,smmu-s1-bypass; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <0 491 0>, <0 135 0>, <0 487 0>, <0 490 0>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&usb30_sec_gdsc>; + clocks = <&clock_virt GCC_USB30_SEC_MASTER_CLK>, + <&clock_virt GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&clock_virt GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&clock_virt GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&clock_virt GCC_USB30_SEC_SLEEP_CLK>, + <&clock_virt GCC_USB3_SEC_CLKREF_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&clock_virt GCC_USB30_SEC_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + qcom,charging-disabled; + + status = "disabled"; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0x0a800000 0xcd00>; + interrupts = <0 138 0>; + usb-phy = <&usb2_phy1>, <&usb_qmp_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + usb-core-id = <1>; + tx-fifo-resize; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + + /* Primary USB port related High Speed PHY */ + usb2_phy1: hsphy@88e3000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e3000 0x110>, + <0x007801f8 0x4>; + reg-names = "hsusb_phy_base", + "phy_rcal_reg"; + + vdd-supply = <&pm8150_l5>; + vdda18-supply = <&pm8150_l12>; + vdda33-supply = <&pm8150_l2>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&clock_gcc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&clock_virt GCC_QUSB2PHY_SEC_BCR>; + reset-names = "phy_reset"; + qcom,rcal-mask = <0x1e00000>; + + status = "disabled"; + }; + + /* Secondary USB port related QMP PHY */ + usb_qmp_phy: ssphy@88eb000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x88eb000 0x1000>, + <0x088eb88c 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&pm8150_l5>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&pm8150l_l3>; + qcom,vbus-valid-override; + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + + clocks = <&clock_virt GCC_USB3_SEC_PHY_AUX_CLK>, + <&clock_virt GCC_USB3_SEC_PHY_PIPE_CLK>, + <&clock_gcc RPMH_CXO_CLK>, + <&clock_virt GCC_USB3_SEC_CLKREF_CLK>, + <&clock_virt GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&clock_virt GCC_USB3_PHY_SEC_BCR>, + <&clock_virt GCC_USB3PHY_PHY_SEC_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-vm.dts b/arch/arm/boot/dts/qcom/sa8155-vm.dts new file mode 100644 index 000000000000..8f9a719cd249 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-vm.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include "sa8155-vm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155 Virtual Machine"; + compatible = "qcom,sa8155"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; + +&slpi_tlmm { + status = "ok"; +}; + +&apps_smmu { + status = "ok"; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + +&usb0 { + status = "ok"; +}; + +&usb2_phy0 { + status = "ok"; +}; + +&pcie0_msi { + status = "ok"; +}; + +&pcie0 { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155-vm.dtsi b/arch/arm/boot/dts/qcom/sa8155-vm.dtsi new file mode 100644 index 000000000000..8ec724d101ac --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155-vm.dtsi @@ -0,0 +1,496 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#include "skeleton64.dtsi" +#include +#include +#include +#include +#include "quin-vm-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155 Virtual Machine"; + qcom,msm-name = "SA8155 V2"; + qcom,msm-id = <362 0x20000>; + + aliases { + pci-domain0 = &pcie0; /* PCIe0 domain */ + }; + + reserved_memory: reserved-memory { + + pmem_shared: pmem_shared_region@a0000000 { + reg = <0x0 0xa0000000 0x0 0x20000000>; + label = "pmem_shared_mem"; + }; + }; +}; + +&soc { + clock_virt: qcom,virtio-gcc { + compatible = "virtio,mmio"; + reg = <0x1c200000 0x1000>; + interrupts = <0 48 0>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_virt_scc: qcom,virtio-scc { + compatible = "virtio,mmio"; + reg = <0x1c300000 0x1000>; + interrupts = <0 49 0>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + apps_smmu: apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x15182000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + status = "disabled"; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + status = "disabled"; + }; + + S6A: pm8150_1_s6: regulator-pm8150-1-s6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_1_s6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1352000>; + qcom,init-voltage = <600000>; + }; + + S4C: pm8150_2_s4: regulator-pm8150-2-s4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_2_s4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + qcom,init-voltage = <800000>; + }; + + S5C: pm8150_2_s5: regulator-pm8150-2-s5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_2_s5"; + regulator-min-microvolt = <1824000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1824000>; + }; + + L15C: pm8150_2_l15: regulator-pm8150-2-l15 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_2_l15"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + qcom,init-voltage = <1800000>; + }; + + vreg_wlan: vreg_wlan { + compatible = "qcom,stub-regulator"; + regulator-name = "vreg_wlan"; + }; + + /* PWR_CTR2_VDD_1P8 supply */ + vreg_conn_1p8: vreg_conn_1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p8"; + pinctrl-names = "default"; + pinctrl-0 = <&conn_power_1p8_active>; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm 173 0>; + }; + + /* PWR_CTR1_VDD_PA supply */ + vreg_conn_pa: vreg_conn_pa { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_pa"; + pinctrl-names = "default"; + pinctrl-0 = <&conn_power_pa_active>; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&tlmm 174 0>; + }; + + pm8150_l2: regulator-pm8150-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_l2"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + qcom,init-voltage = <3072000>; + status = "okay"; + }; + + pm8150_l5: regulator-pm8150-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_l5"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <23800>; + qcom,init-voltage = <880000>; + status = "okay"; + }; + + pm8150_l12: regulator-pm8150-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_l12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + + pm8150l_l3: regulator-pm8150l-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150l_l3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <51800>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + + pm8150_2_l8: regulator-pm8150-2-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_2_l8"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + status = "okay"; + }; + + pm8150_2_l18: regulator-pm8150-2-l18 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_2_l18"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + status = "okay"; + }; + + VDD_CX_LEVEL: VDD_MMCX_LEVEL: + S9C_LEVEL: pm8150_2_s9_level: regulator-pm8150-2-s9-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_2_s9_level"; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + }; + + pcie_0_gdsc: pcie_0_gdsc { + compatible = "qcom,stub-regulator"; + regulator-name = "pcie_0_gdsc"; + status = "okay"; + }; + + usb30_prim_gdsc: usb30_prim_gdsc { + compatible = "qcom,stub-regulator"; + regulator-name = "usb30_prim_gdsc"; + status = "okay"; + }; + + usb30_sec_gdsc: usb30_sec_gdsc { + compatible = "qcom,stub-regulator"; + regulator-name = "usb30_sec_gdsc"; + status = "okay"; + }; + + qcom_seecom: qseecom@87900000 { + compatible = "qcom,qseecom"; + reg = <0x87900000 0x2200000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,no-clock-support; + qcom,qsee-reentrancy-support = <2>; + }; + + bluetooth: bt_qca6174 { + compatible = "qca,qca6174"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_active>; + /* BT_EN */ + qca,bt-reset-gpio = <&tlmm 172 0>; + /* PWR_CTR1_VDD_PA */ + qca,bt-vdd-pa-supply = <&vreg_conn_pa>; + /* PWR_CTR2_VDD_1P8 */ + qca,bt-chip-pwd-supply = <&vreg_conn_1p8>; + status = "ok"; + }; + + qcom,cnss-qca-converged { + compatible = "qcom,cnss-qca-converged"; + + qcom,converged-dt; + qcom,wlan-rc-num = <0>; + qcom,bus-type=<0>; + qcom,notify-modem-status; + qcom,msm-bus,name = "msm-cnss"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, <1 512 0 0>, + /* Upto 200 Mbps */ + <45 512 41421 655360>, <1 512 41421 655360>, + /* Upto 400 Mbps */ + <45 512 98572 655360>, <1 512 98572 1600000>, + /* Upto 800 Mbps */ + <45 512 207108 1146880>, <1 512 207108 3124992>; + + #address-cells=<1>; + #size-cells=<1>; + ranges = <0x10000000 0x10000000 0x10000000>, + <0x20000000 0x20000000 0x10000>, + <0xa0000000 0xa0000000 0x10000000>, + <0xb0000000 0xb0000000 0x10000>; + + vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; + vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>; + vdd-wlan-supply = <&vreg_wlan>; + vdd-wlan-aon-supply = <&pm8150_1_s6>; + vdd-wlan-rfa1-supply = <&pm8150_2_s4>; + vdd-wlan-rfa2-supply = <&pm8150_2_s5>; + vdd-wlan-rfa3-supply = <&pm8150_2_l15>; + + wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2"; + qcom,vdd-wlan-ctrl1-info = <0 0 0 0>; + qcom,vdd-wlan-ctrl2-info = <0 0 0 0>; + wlan-en-gpio = <&tlmm 169 0>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + + chip_cfg@0 { + reg = <0x10000000 0x10000000>, + <0x20000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + + supported-ids = <0x003e>; + wlan_vregs = "vdd-wlan"; + qcom,vdd-wlan-info = <0 0 0 10>; + + qcom,smmu-s1-enable; + qcom,wlan-ramdump-dynamic = <0x200000>; + }; + + chip_cfg@1 { + reg = <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + + supported-ids = <0x1101>; + wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1", + "vdd-wlan-rfa2", "vdd-wlan-rfa3"; + qcom,vdd-wlan-aon-info = <1055000 1055000 0 0>; + qcom,vdd-wlan-rfa1-info = <1350000 1350000 0 0>; + qcom,vdd-wlan-rfa2-info = <2040000 2040000 0 0>; + qcom,vdd-wlan-rfa3-info = <1900000 1900000 0 0>; + + qcom,wlan-ramdump-dynamic = <0x400000>; + mhi,max-channels = <30>; + mhi,timeout = <10000>; + + mhi_channels { + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + }; + }; +}; + +#include "sm8150-pinctrl.dtsi" +#include "sm8150-slpi-pinctrl.dtsi" +#include "sa8155-vm-qupv3.dtsi" +#include "sa8155-vm-usb.dtsi" +#include "sa8155-vm-audio.dtsi" +#include "sa8155-vm-pcie.dtsi" +#include "sa8155-vm-mhi.dtsi" + +&tlmm { + dirconn-list = <37 216 1>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155.dts b/arch/arm/boot/dts/qcom/sa8155.dts new file mode 100644 index 000000000000..92c580175184 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa8155-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155 SoC"; + compatible = "qcom,sa8155"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; + +&android_q_fstab { + /delete-node/ odm; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155.dtsi b/arch/arm/boot/dts/qcom/sa8155.dtsi new file mode 100644 index 000000000000..9e1752d2f128 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155.dtsi @@ -0,0 +1,610 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/ { + aliases { + i2c7 = &qupv3_se20_i2c; + }; +}; + +/* Remove regulator nodes specific to SA8155 */ +&soc { + /delete-node/ regulator-pm8150-s4; + /delete-node/ rpmh-regulator-msslvl; + /delete-node/ rpmh-regulator-smpa2; + /delete-node/ rpmh-regulator-ebilvl; + /delete-node/ rpmh-regulator-smpa5; + /delete-node/ rpmh-regulator-smpa6; + /delete-node/ rpmh-regulator-ldoa1; + /delete-node/ rpmh-regulator-ldoa2; + /delete-node/ rpmh-regulator-ldoa3; + /delete-node/ rpmh-regulator-lmxlvl; + /delete-node/ rpmh-regulator-ldoa5; + /delete-node/ rpmh-regulator-ldoa6; + /delete-node/ rpmh-regulator-ldoa7; + /delete-node/ rpmh-regulator-lcxlvl; + /delete-node/ rpmh-regulator-ldoa9; + /delete-node/ rpmh-regulator-ldoa10; + /delete-node/ rpmh-regulator-ldoa11; + /delete-node/ rpmh-regulator-ldoa12; + /delete-node/ rpmh-regulator-ldoa13; + /delete-node/ rpmh-regulator-ldoa14; + /delete-node/ rpmh-regulator-ldoa15; + /delete-node/ rpmh-regulator-ldoa16; + /delete-node/ rpmh-regulator-ldoa17; + /delete-node/ rpmh-regulator-smpc1; + /delete-node/ rpmh-regulator-gfxlvl; + /delete-node/ rpmh-regulator-mxlvl; + /delete-node/ rpmh-regulator-mmcxlvl; + /delete-node/ rpmh-regulator-cxlvl; + /delete-node/ rpmh-regulator-smpc8; + /delete-node/ rpmh-regulator-ldoc1; + /delete-node/ rpmh-regulator-ldoc2; + /delete-node/ rpmh-regulator-ldoc3; + /delete-node/ rpmh-regulator-ldoc4; + /delete-node/ rpmh-regulator-ldoc5; + /delete-node/ rpmh-regulator-ldoc6; + /delete-node/ rpmh-regulator-ldoc7; + /delete-node/ rpmh-regulator-ldoc8; + /delete-node/ rpmh-regulator-ldoc9; + /delete-node/ rpmh-regulator-ldoc10; + /delete-node/ rpmh-regulator-ldoc11; + /delete-node/ rpmh-regulator-bobc1; + /delete-node/ rpmh-regulator-smpf2; + /delete-node/ rpmh-regulator-ldof2; + /delete-node/ rpmh-regulator-ldof5; + /delete-node/ rpmh-regulator-ldof6; +}; + +/* Add regulator nodes specific to SA8155 */ +#include "sa8155-regulator.dtsi" + +&slpi_tlmm { + status = "ok"; +}; + +&cam_csiphy0 { + mipi-csi-vdd-supply = <&pm8150_2_l8>; +}; + +&cam_csiphy1 { + mipi-csi-vdd-supply = <&pm8150_2_l8>; +}; + +&cam_csiphy2 { + mipi-csi-vdd-supply = <&pm8150_2_l8>; +}; + +&cam_csiphy3 { + mipi-csi-vdd-supply = <&pm8150_2_l8>; +}; + +&pcie0 { + vreg-1.8-supply = <&pm8150_2_l8>; + vreg-0.9-supply = <&pm8150_2_l18>; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; +}; + +&pcie1 { + vreg-1.8-supply = <&pm8150_2_l8>; + vreg-0.9-supply = <&pm8150_2_l18>; +}; + +&pcie_ep { + vreg-1.8-supply = <&pm8150_2_l8>; + vreg-0.9-supply = <&pm8150_2_l18>; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&pm8150_2_l18>; +}; + +&mdss_dsi_phy1 { + vdda-0p9-supply = <&pm8150_2_l18>; +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&pm8150_2_l8>; +}; + +&mdss_dsi1 { + vdda-1p2-supply = <&pm8150_2_l8>; +}; + +&sde_dp { + vdda-1p2-supply = <&pm8150_2_l8>; + vdda-0p9-supply = <&pm8150_2_l18>; +}; + +&lmh_dcvs1 { + isens_vref_0p8-supply = <&pm8150_1_l5_ao>; + isens_vref_1p8-supply = <&pm8150_1_l12_ao>; +}; + +&usb2_phy0 { + vdd-supply = <&pm8150_1_l5>; + vdda18-supply = <&pm8150_1_l12>; + vdda33-supply = <&pm8150_1_l2>; +}; + +&usb_qmp_dp_phy { + vdd-supply = <&pm8150_1_l5>; + core-supply = <&pm8150_2_l8>; +}; + +&usb2_phy1 { + vdd-supply = <&pm8150_1_l5>; + vdda18-supply = <&pm8150_1_l12>; + vdda33-supply = <&pm8150_1_l2>; + status = "ok"; +}; + +&usb_qmp_phy { + vdd-supply = <&pm8150_1_l5>; + core-supply = <&pm8150_2_l8>; + status = "ok"; +}; + +&icnss { + vdd-cx-mx-supply = <&pm8150_1_l1>; + vdd-1.8-xo-supply = <&pm8150_1_l7>; + vdd-1.3-rfa-supply = <&pm8150_2_l1>; + /delete-property/ vdd-3.3-ch0-supply; +}; + +&pil_ssc { + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; +}; + +&pil_modem { + vdd_mss-supply = <&pm8150_1_s8_level>; +}; + +&wil6210 { + /delete-property/ vddio-supply; +}; + +&gpu_gx_gdsc { + parent-supply = <&pm8150_2_s3_level>; + vdd_parent-supply = <&pm8150_2_s3_level>; +}; + +&ufsphy_mem { + vdda-phy-supply = <&pm8150_2_l18>; +}; + +&clock_scc { + vdd_scc_cx-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&msm_cdsp_rm { + /delete-property/ qcom,compute-cx-limit-en; + /delete-property/ qcom,compute-priority-mode; +}; + +&thermal_zones { + aoss0-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + cpu-0-0-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + cpu-0-1-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + cpu-0-2-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + cpu-0-3-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + cpuss-0-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + cpuss-1-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + cpu-1-0-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + cpu-1-1-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + cpu-1-2-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + cpu-1-3-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + cpu-1-4-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + cpu-1-5-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + cpu-1-6-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + cpu-1-7-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + gpuss-0-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + aoss-1-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + cwlan-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + video-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + ddr-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + q6-hvx-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + camera-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + cmpss-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + mdm-core-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + npu-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + mdm-vec-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + mdm-scl-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + gpuss-1-lowf { + cooling-maps { + /delete-node/ mmcx_vdd_cdev; + }; + }; + + lmh-dcvs-01 { + trips { + active-config { + temperature = <105000>; + hysteresis = <40000>; + }; + }; + }; + + lmh-dcvs-00 { + trips { + active-config { + temperature = <105000>; + hysteresis = <40000>; + }; + }; + }; + + gpuss-max-step { + trips { + gpu-trip0 { + temperature = <100000>; + }; + }; + }; + + pop-mem-step { + status = "disabled"; + }; + + npu-step { + trips { + npu-trip0 { + temperature = <105000>; + }; + }; + }; + + cpu-0-0-step { + trips { + cpu00-config { + temperature = <115000>; + }; + }; + }; + + cpu-0-1-step { + trips { + cpu01-config { + temperature = <115000>; + }; + }; + }; + + cpu-0-2-step { + trips { + cpu02-config { + temperature = <115000>; + }; + }; + }; + + cpu-0-3-step { + trips { + cpu03-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-0-step { + trips { + cpu10-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-1-step { + trips { + cpu11-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-2-step { + trips { + cpu12-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-3-step { + trips { + cpu13-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-4-step { + trips { + cpu14-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-5-step { + trips { + cpu15-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-6-step { + trips { + cpu16-config { + temperature = <115000>; + }; + }; + }; + + cpu-1-7-step { + trips { + cpu17-config { + temperature = <115000>; + }; + }; + }; + + q6-hvx-step { + trips { + q6-hvx-step0 { + temperature = <105000>; + }; + q6-hvx-step1 { + temperature = <115000>; + }; + }; + }; +}; + +&mdss_dsi0_pll { + /delete-property/ qcom,dsi-pll-ssc-en; +}; + +&mdss_dsi1_pll { + /delete-property/ qcom,dsi-pll-ssc-en; +}; + +&mdss_mdp { + qcom,sde-mixer-display-pref = "primary", "none", "none", + "none", "none", "none"; +}; + +#include + +&soc { + emac_hw: qcom,emac@00020000 { + compatible = "qcom,emac-dwc-eqos"; + qcom,arm-smmu; + emac-core-version = <2>; + reg = <0x20000 0x10000>, + <0x36000 0x100>, + <0x3D00000 0x300000>; + reg-names = "emac-base", "rgmii-base", "tlmm-central-base"; + interrupts-extended = <&pdc 0 689 4>, <&pdc 0 699 4>, + <&tlmm 124 2>, <&pdc 0 691 4>, + <&pdc 0 692 4>, <&pdc 0 693 4>, + <&pdc 0 694 4>, <&pdc 0 695 4>, + <&pdc 0 696 4>, <&pdc 0 697 4>, + <&pdc 0 698 4>, <&pdc 0 699 4>; + interrupt-names = "sbd-intr", "lpi-intr", + "phy-intr", "tx-ch0-intr", + "tx-ch1-intr", "tx-ch2-intr", + "tx-ch3-intr", "tx-ch4-intr", + "rx-ch0-intr", "rx-ch1-intr", + "rx-ch2-intr", "rx-ch3-intr"; + qcom,msm-bus,name = "emac"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <98 512 0 0>, <1 781 0 0>, /* No vote */ + <98 512 2500 0>, <1 781 0 40000>, /* 10Mbps vote */ + <98 512 25000 0>, <1 781 0 40000>, /* 100Mbps vote */ + <98 512 250000 0>, <1 781 0 40000>; /* 1000Mbps vote */ + qcom,bus-vector-names = "0", "10", "100", "1000"; + clocks = <&clock_gcc GCC_EMAC_AXI_CLK>, + <&clock_gcc GCC_EMAC_PTP_CLK>, + <&clock_gcc GCC_EMAC_RGMII_CLK>, + <&clock_gcc GCC_EMAC_SLV_AHB_CLK>; + clock-names = "emac_axi_clk", "emac_ptp_clk", + "emac_rgmii_clk", "emac_slv_ahb_clk"; + qcom,phy-reset = <&tlmm 79 GPIO_ACTIVE_HIGH>; + qcom,phy-intr-redirect = <&tlmm 124 GPIO_ACTIVE_LOW>; + gdsc_emac-supply = <&emac_gdsc>; + pinctrl-names = "dev-emac-mdc", + "dev-emac-mdio", + "dev-emac-rgmii_txd0_state", + "dev-emac-rgmii_txd1_state", + "dev-emac-rgmii_txd2_state", + "dev-emac-rgmii_txd3_state", + "dev-emac-rgmii_txc_state", + "dev-emac-rgmii_tx_ctl_state", + "dev-emac-rgmii_rxd0_state", + "dev-emac-rgmii_rxd1_state", + "dev-emac-rgmii_rxd2_state", + "dev-emac-rgmii_rxd3_state", + "dev-emac-rgmii_rxc_state", + "dev-emac-rgmii_rx_ctl_state", + "dev-emac-phy_intr", + "dev-emac-phy_reset_state", + "dev-emac_pin_pps_0"; + + pinctrl-0 = <&emac_mdc>; + pinctrl-1 = <&emac_mdio>; + + pinctrl-2 = <&emac_rgmii_txd0>; + pinctrl-3 = <&emac_rgmii_txd1>; + pinctrl-4 = <&emac_rgmii_txd2>; + pinctrl-5 = <&emac_rgmii_txd3>; + pinctrl-6 = <&emac_rgmii_txc>; + pinctrl-7 = <&emac_rgmii_tx_ctl>; + + pinctrl-8 = <&emac_rgmii_rxd0>; + pinctrl-9 = <&emac_rgmii_rxd1>; + pinctrl-10 = <&emac_rgmii_rxd2>; + pinctrl-11 = <&emac_rgmii_rxd3>; + pinctrl-12 = <&emac_rgmii_rxc>; + pinctrl-13 = <&emac_rgmii_rx_ctl>; + pinctrl-14 = <&emac_phy_intr>; + pinctrl-15 = <&emac_phy_reset_state>; + pinctrl-16 = <&emac_pin_pps_0>; + + io-macro-info { + io-macro-bypass-mode = <0>; + io-interface = "rgmii"; + }; + emac_emb_smmu: emac_emb_smmu { + compatible = "qcom,emac-smmu-embedded"; + iommus = <&apps_smmu 0x3C0 0x0>; + qcom,iova-mapping = <0x80000000 0x40000000>; + }; + }; + + qcom,rmnet-ipa { + status="disabled"; + }; + + qfprom: qfprom@780130 { + compatible = "qcom,qfprom"; + reg = <0x00780130 0x4>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + }; + + /include/ "dm-verity-boot.dtsi" +}; + +&ipa_hw { + status="disabled"; +}; + +#include "sa8155-audio.dtsi" +#include "sa8155-camera-sensor.dtsi" diff --git a/arch/arm/boot/dts/qcom/sa8155p-adp-alcor-overlay.dts b/arch/arm/boot/dts/qcom/sa8155p-adp-alcor-overlay.dts new file mode 100644 index 000000000000..339ee4912543 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155p-adp-alcor-overlay.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include "sa8155-adp-alcor.dtsi" + +/ { + model = "ADP-ALCOR"; + compatible = "qcom,sa8155p-adp-alcor", "qcom,sa8155p", + "qcom,adp-alcor"; + qcom,board-id = <0x02000019 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155p-adp-alcor.dts b/arch/arm/boot/dts/qcom/sa8155p-adp-alcor.dts new file mode 100644 index 000000000000..eddf12f9a8aa --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155p-adp-alcor.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa8155p-v2.dtsi" +#include "sa8155-adp-alcor.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155P ADP ALCOR"; + compatible = "qcom,sa8155p-adp-alcor", "qcom,sa8155p", + "qcom,adp-alcor"; + qcom,board-id = <0x02000019 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155p-adp-star-overlay.dts b/arch/arm/boot/dts/qcom/sa8155p-adp-star-overlay.dts new file mode 100644 index 000000000000..6c8c6688da1a --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155p-adp-star-overlay.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include + +#include "sa8155-adp-star.dtsi" + +/ { + model = "ADP-STAR"; + compatible = "qcom,sa8155p-adp-star", "qcom,sa8155p", + "qcom,adp-star"; + qcom,board-id = <25 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155p-adp-star.dts b/arch/arm/boot/dts/qcom/sa8155p-adp-star.dts new file mode 100644 index 000000000000..8a7aaea2e24c --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155p-adp-star.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include "sa8155p.dtsi" +#include "sa8155-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155P ADP-STAR"; + compatible = "qcom,sa8155p-adp-star", "qcom,sa8155p", + "qcom,adp-star"; + qcom,board-id = <25 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155p-v2-adp-air-overlay.dts b/arch/arm/boot/dts/qcom/sa8155p-v2-adp-air-overlay.dts new file mode 100644 index 000000000000..c89b831b1d85 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155p-v2-adp-air-overlay.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include "sa8155-adp-common.dtsi" +#include "sa8155-adp-star-display.dtsi" + +/ { + model = "ADP-AIR"; + compatible = "qcom,sa8155p-v2-adp-air", "qcom,sa8155p", + "qcom,adp-air"; + qcom,board-id = <0x01000019 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155p-v2-adp-air.dts b/arch/arm/boot/dts/qcom/sa8155p-v2-adp-air.dts new file mode 100644 index 000000000000..fd1abc71f9ae --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155p-v2-adp-air.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa8155p-v2.dtsi" +#include "sa8155-adp-common.dtsi" +#include "sa8155-adp-star-display.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155P V2 ADP AIR"; + compatible = "qcom,sa8155p-v2-adp-air", "qcom,sa8155p", "qcom,adp-air"; + qcom,board-id = <0x01000019 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155p-v2-adp-star.dts b/arch/arm/boot/dts/qcom/sa8155p-v2-adp-star.dts new file mode 100644 index 000000000000..838d96387275 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155p-v2-adp-star.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa8155p-v2.dtsi" +#include "sa8155-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155P V2 ADP STAR"; + compatible = "qcom,sa8155p-adp-star", "qcom,sa8155p", "qcom,adp-star"; + qcom,board-id = <25 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155p-v2.dts b/arch/arm/boot/dts/qcom/sa8155p-v2.dts new file mode 100644 index 000000000000..42efaea63947 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155p-v2.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa8155p-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155P v2 SoC"; + compatible = "qcom,sa8155p"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; + +&android_q_fstab { + /delete-node/ odm; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155p-v2.dtsi b/arch/arm/boot/dts/qcom/sa8155p-v2.dtsi new file mode 100644 index 000000000000..ac6ec4a18d72 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155p-v2.dtsi @@ -0,0 +1,19 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sa8155-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155P v2"; + qcom,msm-name = "SA8155P v2"; + qcom,msm-id = <367 0x20000>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155p.dts b/arch/arm/boot/dts/qcom/sa8155p.dts new file mode 100644 index 000000000000..439d81e05125 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155p.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa8155p.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155P SoC"; + compatible = "qcom,sa8155p"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; + +&android_q_fstab { + /delete-node/ odm; +}; diff --git a/arch/arm/boot/dts/qcom/sa8155p.dtsi b/arch/arm/boot/dts/qcom/sa8155p.dtsi new file mode 100644 index 000000000000..7d70bb52ed77 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8155p.dtsi @@ -0,0 +1,20 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sa8155-v1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8155P "; + qcom,msm-name = "SA8155P V1"; + compatible = "qcom,sa8155p"; + qcom,msm-id = <367 0x10000>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8195-pmic.dtsi b/arch/arm/boot/dts/qcom/sa8195-pmic.dtsi new file mode 100644 index 000000000000..2cdf7df42ed9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8195-pmic.dtsi @@ -0,0 +1,121 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Remove regulator nodes specific to sdmshrike */ +&soc { + /* Stub regulators */ + /delete-node/ regulator-pm8150_1-s4; + + /* Logical rails */ + /delete-node/ rpmh-regulator-cxlvl; + /delete-node/ rpmh-regulator-mxlvl; + /delete-node/ rpmh-regulator-gfxlvl; + /delete-node/ rpmh-regulator-lmxlvl; + /delete-node/ rpmh-regulator-lcxlvl; + /delete-node/ rpmh-regulator-mmcxlvl; + /delete-node/ rpmh-regulator-msslvl; + /delete-node/ rpmh-regulator-ebilvl; + + /* PM8150_1 regulators */ + /delete-node/ rpmh-regulator-smpa5; + /delete-node/ rpmh-regulator-ldoa3; + /delete-node/ rpmh-regulator-ldoa5; + /delete-node/ rpmh-regulator-ldoa6; + /delete-node/ rpmh-regulator-ldoa7; + /delete-node/ rpmh-regulator-ldoa9; + /delete-node/ rpmh-regulator-ldoa11; + /delete-node/ rpmh-regulator-ldoa12; + /delete-node/ rpmh-regulator-ldoa13; + /delete-node/ rpmh-regulator-ldoa15; + /delete-node/ rpmh-regulator-ldoa16; + /delete-node/ rpmh-regulator-ldoa18; + /delete-node/ rpmh-regulator-smpe4; + /delete-node/ rpmh-regulator-smpe5; + /delete-node/ rpmh-regulator-ldoe1; + /delete-node/ rpmh-regulator-ldoe2; + /delete-node/ rpmh-regulator-ldoe5; + /delete-node/ rpmh-regulator-ldoe7; + /delete-node/ rpmh-regulator-ldoe10; + /delete-node/ rpmh-regulator-ldoe13; + /delete-node/ rpmh-regulator-ldoe14; + /delete-node/ rpmh-regulator-ldoe15; + /delete-node/ rpmh-regulator-ldoe16; + /delete-node/ rpmh-regulator-ldoe17; + /delete-node/ rpmh-regulator-smpc6; + /delete-node/ rpmh-regulator-smpc7; + /delete-node/ rpmh-regulator-smpc8; + /delete-node/ rpmh-regulator-ldoc1; + /delete-node/ rpmh-regulator-ldoc2; + /delete-node/ rpmh-regulator-ldoc3; + /delete-node/ rpmh-regulator-ldoc4; + /delete-node/ rpmh-regulator-ldoc6; + /delete-node/ rpmh-regulator-ldoc7; + /delete-node/ rpmh-regulator-ldoc8; + /delete-node/ rpmh-regulator-ldoc9; + /delete-node/ rpmh-regulator-ldoc10; + /delete-node/ rpmh-regulator-ldoc11; + /delete-node/ rpmh-regulator-bobc1; + + /* refgen-regulator@88e7000 */ + /delete-node/ refgen; +}; + +&usb2_phy0 { + /delete-property/ vdd-supply; + /delete-property/ vdda18-supply; + /delete-property/ vdda33-supply; +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&pm8195_1_l9>; +}; + +&mdss_dsi1 { + vdda-1p2-supply = <&pm8195_1_l9>; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&pm8195_3_l5>; +}; + +&mdss_dsi_phy1 { + vdda-0p9-supply = <&pm8195_3_l5>; +}; + +&clock_cpucc { + lmh_dcvs1: qcom,limits-dcvs@18350800 { + isens_vref_0p8-supply = <&pm8195_3_l5>; + isens-vref-0p8-settings = <880000 880000 20000>; + isens_vref_1p8-supply = <&pm8195_1_l12>; + isens-vref-1p8-settings = <1800000 1800000 20000>; + }; +}; + + +&soc { + qcom,lpass@17300000 { + vdd_cx-supply = <&VDD_CX_LEVEL>; + }; + clock_camcc: qcom,camcc@ad00000 { + vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + }; +}; + +&gpu_gx_gdsc { + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; +}; + +#include "sa8195p-regulator.dtsi" +#include "pm8195.dtsi" + diff --git a/arch/arm/boot/dts/qcom/sa8195-vm.dts b/arch/arm/boot/dts/qcom/sa8195-vm.dts new file mode 100644 index 000000000000..12807e33cf4e --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8195-vm.dts @@ -0,0 +1,38 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa8195-vm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195 Virtual Machine"; + compatible = "qcom,sa8195p"; + qcom,pmic-name = "PM8195"; + qcom,board-id = <0 0>; +}; + +&slpi_tlmm { + status = "ok"; +}; + +&apps_smmu { + status = "ok"; +}; + +&usb0 { + status = "ok"; +}; + +&usb2_phy0 { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/sa8195-vm.dtsi b/arch/arm/boot/dts/qcom/sa8195-vm.dtsi new file mode 100644 index 000000000000..12c910533271 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8195-vm.dtsi @@ -0,0 +1,207 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "skeleton64.dtsi" +#include +#include +#include +#include "quin-vm-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195 Virtual Machine"; + qcom,msm-name = "SA8195P"; + qcom,msm-id = <405 0x20000>; + + reserved_memory: reserved-memory { + + pmem_shared: pmem_shared_region@a0000000 { + reg = <0x0 0xa0000000 0x0 0x20000000>; + label = "pmem_shared_mem"; + }; + }; +}; + +&soc { + clock_virt: qcom,virt-gcc { + compatible = "qcom,virt-clk-sm8150-gcc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_virt_scc: qcom,virt-scc { + compatible = "qcom,virt-clk-sm8150-scc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + apps_smmu: apps-smmu@0x15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x15182000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + qcom,disable-atos; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + status = "disabled"; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + status = "disabled"; + }; + + pm8150_l2: regulator-pm8150-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_l2"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + qcom,init-voltage = <3072000>; + status = "okay"; + }; + + pm8150_l5: regulator-pm8150-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_l5"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <23800>; + qcom,init-voltage = <880000>; + status = "okay"; + }; + + pm8150_l12: regulator-pm8150-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_l12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + + pm8150l_l3: regulator-pm8150l-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150l_l3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <51800>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + + usb30_prim_gdsc: usb30_prim_gdsc { + compatible = "qcom,stub-regulator"; + regulator-name = "usb30_prim_gdsc"; + status = "okay"; + }; + + usb30_sec_gdsc: usb30_sec_gdsc { + compatible = "qcom,stub-regulator"; + regulator-name = "usb30_sec_gdsc"; + status = "okay"; + }; +}; + +#include "sdmshrike-pinctrl.dtsi" +#include "sm8150-slpi-pinctrl.dtsi" +#include "sa8155-vm-qupv3.dtsi" +#include "sa8155-vm-usb.dtsi" +#include "sa8155-vm-audio.dtsi" diff --git a/arch/arm/boot/dts/qcom/sa8195p-adp-star-display.dtsi b/arch/arm/boot/dts/qcom/sa8195p-adp-star-display.dtsi new file mode 100644 index 000000000000..24262a3a9614 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8195p-adp-star-display.dtsi @@ -0,0 +1,306 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&tlmm { + ioexp_intr_active: ioexp_intr_active { + mux { + pins = "gpio84"; + function = "gpio"; + }; + config { + pins = "gpio84"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + ioexp_reset_active: ioexp_reset_active { + mux { + pins = "gpio30"; + function = "gpio"; + }; + config { + pins = "gpio30"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; +}; + +&sde_dp { + qcom,ext-disp = <&ext_disp>; + qcom,dp-hpd-gpio = <&ioexp 8 0>; + + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; + pinctrl-0 = <&dp_hpd_cfg_pins>; + pinctrl-1 = <&dp_hpd_cfg_pins>; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; +}; + +&qupv3_se15_i2c { + status = "ok"; + + pinctrl-0 = <&qupv3_se15_i2c_active + &ioexp_intr_active + &ioexp_reset_active>; + + ioexp: gpio@3e { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1509q"; + reg = <0x3e>; + interrupt-parent = <&tlmm>; + interrupts = <84 0>; + gpio-controller; + interrupt-controller; + semtech,probe-reset; + + pinctrl-names = "default"; + pinctrl-0 = <&dsi1_hpd_cfg_pins + &dsi1_cdet_cfg_pins + &dsi2_hpd_cfg_pins + &dsi2_cdet_cfg_pins + &dp_hpd_cfg_pins>; + + dsi1_hpd_cfg_pins: gpio0-cfg { + pins = "gpio0"; + bias-pull-up; + }; + + dsi1_cdet_cfg_pins: gpio1-cfg { + pins = "gpio1"; + bias-pull-down; + }; + + dsi2_hpd_cfg_pins: gpio2-cfg { + pins = "gpio2"; + bias-pull-up; + }; + + dsi2_cdet_cfg_pins: gpio3-cfg { + pins = "gpio3"; + bias-pull-down; + }; + + dp_hpd_cfg_pins: gpio8-cfg { + pins = "gpio8"; + bias-pull-down; + }; + }; + + i2c-mux@77 { + compatible = "nxp,pca9542"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + anx_7625_1: anx7625@2c { + compatible = "analogix,anx7625"; + reg = <0x2c>; + interrupt-parent = <&ioexp>; + interrupts = <0 0>; + cbl_det-gpio = <&ioexp 1 0>; + power_en-gpio = <&tlmm 83 0>; + reset_n-gpio = <&tlmm 49 0>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + anx_7625_2: anx7625@2c { + compatible = "analogix,anx7625"; + reg = <0x2c>; + interrupt-parent = <&ioexp>; + interrupts = <2 0>; + cbl_det-gpio = <&ioexp 3 0>; + power_en-gpio = <&tlmm 87 0>; + reset_n-gpio = <&tlmm 29 0>; + }; + }; + }; +}; + +&anx_7625_1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + anx_7625_1_in: endpoint { + remote-endpoint = <&dsi_anx_7625_1_out>; + }; + }; + }; +}; + +&anx_7625_2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + anx_7625_2_in: endpoint { + remote-endpoint = <&dsi_anx_7625_2_out>; + }; + }; + }; +}; + +#include "dsi-panel-ext-bridge-1080p.dtsi" + +&dsi_ext_bridge_1080p { + qcom,mdss-dsi-ext-bridge = <0>; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1E 08 07 24 22 + 08 08 05 02 04 00 19 17]; + }; + }; +}; + +&soc { + dsi_anx_7625_1: qcom,dsi-display@17 { + label = "dsi_anx_7625_1"; + qcom,dsi-display-active; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_ext_bridge_1080p>; + }; + + dsi_anx_7625_2: qcom,dsi-display@18 { + label = "dsi_anx_7625_2"; + qcom,dsi-display-active; + qcom,display-type = "secondary"; + + qcom,dsi-ctrl-num = <1>; + qcom,dsi-phy-num = <1>; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,dsi-panel = <&dsi_ext_bridge_1080p>; + }; + + dsi_dp1: qcom,dsi-display@1 { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, + <&mdss_dsi0_pll PCLK_MUX_0_CLK>, + <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, + <&mdss_dsi1_pll PCLK_MUX_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,dsi-display-list = + <&dsi_anx_7625_1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_anx_7625_1_out: endpoint { + remote-endpoint = <&anx_7625_1_in>; + }; + }; + }; + }; + + dsi_dp2: qcom,dsi-display@2 { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, + <&mdss_dsi0_pll PCLK_MUX_0_CLK>, + <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, + <&mdss_dsi1_pll PCLK_MUX_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,dsi-display-list = + <&dsi_anx_7625_2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_anx_7625_2_out: endpoint { + remote-endpoint = <&anx_7625_2_in>; + }; + }; + }; + }; + + sde_wb: qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display"; + }; + + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; +}; + +&mdss_dsi_phy0 { + qcom,panel-force-clock-lane-hs; +}; + +&mdss_dsi_phy1 { + qcom,panel-force-clock-lane-hs; +}; + +&mdss_mdp { + connectors = <&dsi_dp1 &dsi_dp2 &sde_dp &sde_wb>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8195p-adp-star-overlay.dts b/arch/arm/boot/dts/qcom/sa8195p-adp-star-overlay.dts new file mode 100644 index 000000000000..d7752bd2ecec --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8195p-adp-star-overlay.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include "sa8195p-adp-star.dtsi" + +/ { + model = "ADP-STAR"; + compatible = "qcom,sa8195p-adp-star", "qcom,sa8195p", + "qcom,adp-star"; + qcom,board-id = <25 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8195p-adp-star.dts b/arch/arm/boot/dts/qcom/sa8195p-adp-star.dts new file mode 100644 index 000000000000..f8af71a03889 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8195p-adp-star.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include "sa8195p.dtsi" +#include "sa8195p-adp-star.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195P ADP-STAR"; + compatible = "qcom,sa8195p-adp-star", "qcom,sa8195p", + "qcom,adp-star"; + qcom,board-id = <25 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8195p-adp-star.dtsi b/arch/arm/boot/dts/qcom/sa8195p-adp-star.dtsi new file mode 100644 index 000000000000..02e46d986949 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8195p-adp-star.dtsi @@ -0,0 +1,36 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&qupv3_se0_spi { + status = "ok"; + + #address-cells = <1>; + #size-cells = <0>; + + can-controller@0 { + compatible = "qcom,nxp,mpc5746c"; + reg = <0>; + interrupt-parent = <&tlmm>; + interrupts = <38 0>; + spi-max-frequency = <5000000>; + qcom,clk-freq-mhz = <40000000>; + qcom,max-can-channels = <1>; + qcom,bits-per-word = <8>; + qcom,support-can-fd; + }; +}; + +&qupv3_se12_2uart { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/sa8195p-pcie.dtsi b/arch/arm/boot/dts/qcom/sa8195p-pcie.dtsi new file mode 100644 index 000000000000..f49c8f87f505 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8195p-pcie.dtsi @@ -0,0 +1,805 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + pcie0: qcom,pcie@1c00000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x1c00000 0x4000>, + <0x1c06000 0x1000>, + <0x60000000 0xf1d>, + <0x60000f20 0xa8>, + <0x60001000 0x1000>, + <0x60100000 0x100000>, + <0x60200000 0x100000>, + <0x60300000 0x3d00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>; + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = < 0 0 0 0 &intc 0 140 0 + 0 0 0 1 &intc 0 149 0 + 0 0 0 2 &intc 0 150 0 + 0 0 0 3 &intc 0 151 0 + 0 0 0 4 &intc 0 152 0>; + + qcom,phy-sequence = <0x0840 0x03 0x0 + 0x0094 0x08 0x0 + 0x0154 0x34 0x0 + 0x016c 0x08 0x0 + 0x0058 0x0f 0x0 + 0x00a4 0x42 0x0 + 0x0110 0x24 0x0 + 0x011c 0x03 0x0 + 0x0118 0xb4 0x0 + 0x010c 0x02 0x0 + 0x01bc 0x11 0x0 + 0x00bc 0x82 0x0 + 0x00d4 0x03 0x0 + 0x00d0 0x55 0x0 + 0x00cc 0x55 0x0 + 0x00b0 0x1a 0x0 + 0x00ac 0x0a 0x0 + 0x00c4 0x68 0x0 + 0x00e0 0x02 0x0 + 0x00dc 0xaa 0x0 + 0x00d8 0xab 0x0 + 0x00b8 0x34 0x0 + 0x00b4 0x14 0x0 + 0x0158 0x01 0x0 + 0x0074 0x06 0x0 + 0x007c 0x16 0x0 + 0x0084 0x36 0x0 + 0x0078 0x06 0x0 + 0x0080 0x16 0x0 + 0x0088 0x36 0x0 + 0x01b0 0x1e 0x0 + 0x01ac 0xb9 0x0 + 0x01b8 0x18 0x0 + 0x01b4 0x94 0x0 + 0x0050 0x07 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x029c 0x12 0x0 + 0x0284 0x35 0x0 + 0x023c 0x11 0x0 + 0x051c 0x03 0x0 + 0x0518 0x1c 0x0 + 0x0524 0x1e 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x05b4 0x04 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0510 0x17 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x04fc 0x00 0x0 + 0x04f8 0xc0 0x0 + 0x0460 0x30 0x0 + 0x0464 0xc0 0x0 + 0x05bc 0x0c 0x0 + 0x04dc 0x0d 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x09a4 0x01 0x0 + 0x0c90 0x00 0x0 + 0x0c40 0x01 0x0 + 0x0c48 0x01 0x0 + 0x0c50 0x00 0x0 + 0x0cbc 0x00 0x0 + 0x0ce0 0x58 0x0 + 0x0048 0x90 0x0 + 0x0c1c 0xc1 0x0 + 0x0988 0x88 0x0 + 0x0998 0x0b 0x0 + 0x08dc 0x0d 0x0 + 0x09ec 0x01 0x0 + 0x0800 0x00 0x0 + 0x0844 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + + perst-gpio = <&tlmm 35 0>; + wake-gpio = <&tlmm 37 0>; + + gdsc-vdd-supply = <&pcie_0_gdsc>; + vreg-1.8-supply = <&pm8195_1_l9>; + vreg-0.9-supply = <&pm8195_3_l5>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0.9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + msi-parent = <&pcie0_msi>; + + qcom,no-l0s-supported; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x4000000>; + + qcom,phy-status-offset = <0x814>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x840>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <0>; + + qcom,pcie-phy-ver = <2110>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x1d80>; + + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>, + <0x200 &apps_smmu 0x1d82 0x1>, + <0x300 &apps_smmu 0x1d83 0x1>, + <0x400 &apps_smmu 0x1d84 0x1>, + <0x500 &apps_smmu 0x1d85 0x1>, + <0x600 &apps_smmu 0x1d86 0x1>, + <0x700 &apps_smmu 0x1d87 0x1>, + <0x800 &apps_smmu 0x1d88 0x1>, + <0x900 &apps_smmu 0x1d89 0x1>, + <0xa00 &apps_smmu 0x1d8a 0x1>, + <0xb00 &apps_smmu 0x1d8b 0x1>, + <0xc00 &apps_smmu 0x1d8c 0x1>, + <0xd00 &apps_smmu 0x1d8d 0x1>, + <0xe00 &apps_smmu 0x1d8e 0x1>, + <0xf00 &apps_smmu 0x1d8f 0x1>; + + qcom,msm-bus,name = "pcie0"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 500 800>; + + clocks = <&clock_gcc GCC_PCIE_0_PIPE_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_PCIE_0_AUX_CLK>, + <&clock_gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&clock_gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&clock_gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&clock_gcc GCC_PCIE_0_CLKREF_CLK>, + <&clock_gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&clock_gcc GCC_PCIE0_PHY_REFGEN_CLK>, + <&clock_gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&clock_gcc GCC_PCIE_0_BCR>, + <&clock_gcc GCC_PCIE_0_PHY_BCR>; + + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + pcie_rc0: pcie_rc0 { + reg = <0 0 0 0 0>; + pci-ids = "17cb:0108"; + }; + }; + + pcie0_msi: qcom,pcie0_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupt-parent = <&pdc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pcie1: qcom,pcie@1c08000 { + compatible = "qcom,pci-msm"; + cell-index = <1>; + + reg = <0x1c08000 0x4000>, + <0x1c0e000 0x2000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>, + <0x40200000 0x100000>, + <0x40300000 0x1fd00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>; + interrupt-parent = <&pcie1>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc 0 306 0 + 0 0 0 1 &intc 0 434 0 + 0 0 0 2 &intc 0 435 0 + 0 0 0 3 &intc 0 438 0 + 0 0 0 4 &intc 0 439 0>; + + qcom,phy-sequence = <0x0a40 0x03 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0048 0x90 0x0 + 0x0058 0x0f 0x0 + 0x0074 0x06 0x0 + 0x0078 0x06 0x0 + 0x007c 0x16 0x0 + 0x0080 0x16 0x0 + 0x0084 0x36 0x0 + 0x0088 0x36 0x0 + 0x0094 0x08 0x0 + 0x00a4 0x42 0x0 + 0x00ac 0x0a 0x0 + 0x00b0 0x1a 0x0 + 0x00b4 0x14 0x0 + 0x00b8 0x34 0x0 + 0x00bc 0x82 0x0 + 0x00c4 0x68 0x0 + 0x00cc 0x55 0x0 + 0x00d0 0x55 0x0 + 0x00d4 0x03 0x0 + 0x00d8 0xab 0x0 + 0x00dc 0xaa 0x0 + 0x00e0 0x02 0x0 + 0x010c 0x02 0x0 + 0x0110 0x24 0x0 + 0x0118 0xb4 0x0 + 0x011c 0x03 0x0 + 0x0154 0x34 0x0 + 0x0158 0x01 0x0 + 0x016c 0x08 0x0 + 0x01ac 0xb9 0x0 + 0x01b0 0x1e 0x0 + 0x01b4 0x94 0x0 + 0x01b8 0x18 0x0 + 0x01bc 0x11 0x0 + 0x023c 0x11 0x0 + 0x0284 0x35 0x0 + 0x029c 0x12 0x0 + 0x0304 0x02 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0460 0x30 0x0 + 0x0464 0xc0 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x04dc 0x0d 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x04f8 0xc0 0x0 + 0x04fc 0x00 0x0 + 0x0510 0x17 0x0 + 0x0518 0x1c 0x0 + 0x051c 0x03 0x0 + 0x0524 0x1e 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x05bc 0x0c 0x0 + 0x063c 0x11 0x0 + 0x0684 0x35 0x0 + 0x069c 0x12 0x0 + 0x0704 0x20 0x0 + 0x0808 0x0c 0x0 + 0x0814 0x03 0x0 + 0x0834 0x7f 0x0 + 0x0844 0x70 0x0 + 0x0860 0x30 0x0 + 0x0864 0xc0 0x0 + 0x08d4 0x54 0x0 + 0x08d8 0x07 0x0 + 0x08dc 0x0d 0x0 + 0x08e8 0x00 0x0 + 0x08ec 0x0e 0x0 + 0x08f0 0x4a 0x0 + 0x08f4 0x0f 0x0 + 0x08f8 0xc0 0x0 + 0x08fc 0x00 0x0 + 0x0910 0x17 0x0 + 0x0918 0x1c 0x0 + 0x091c 0x03 0x0 + 0x0924 0x1e 0x0 + 0x0970 0xff 0x0 + 0x0974 0xff 0x0 + 0x0978 0xff 0x0 + 0x097c 0x7f 0x0 + 0x0980 0x66 0x0 + 0x0984 0x24 0x0 + 0x0988 0xe4 0x0 + 0x098c 0xec 0x0 + 0x0990 0x3b 0x0 + 0x0994 0x36 0x0 + 0x0998 0xd4 0x0 + 0x099c 0x54 0x0 + 0x09a0 0xdb 0x0 + 0x09a4 0x3b 0x0 + 0x09a8 0x31 0x0 + 0x09bc 0x0c 0x0 + 0x0adc 0x05 0x0 + 0x0b88 0x88 0x0 + 0x0b98 0x0b 0x0 + 0x0ba4 0x01 0x0 + 0x0bec 0x01 0x0 + 0x0e0c 0x0d 0x0 + 0x0e14 0x07 0x0 + 0x0e1c 0xc1 0x0 + 0x0e40 0x01 0x0 + 0x0e48 0x01 0x0 + 0x0e90 0x00 0x0 + 0x0ebc 0x00 0x0 + 0x0ee0 0x58 0x0 + 0x0a00 0x00 0x0 + 0x0a44 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_clkreq_default + &pcie1_perst_default + &pcie1_wake_default>; + + perst-gpio = <&tlmm 102 0>; + wake-gpio = <&tlmm 104 0>; + + gdsc-vdd-supply = <&pcie_1_gdsc>; + vreg-1.8-supply = <&pm8195_1_l9>; + vreg-0.9-supply = <&pm8195_3_l5>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0.9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + msi-parent = <&pcie1_msi>; + + qcom,no-l0s-supported; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x20000000>; + + qcom,phy-status-offset = <0xa14>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0xa40>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <1>; + + qcom,pcie-phy-ver = <2105>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x1e00>; + + iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, + <0x100 &apps_smmu 0x1e01 0x1>, + <0x200 &apps_smmu 0x1e02 0x1>, + <0x300 &apps_smmu 0x1e03 0x1>, + <0x400 &apps_smmu 0x1e04 0x1>, + <0x500 &apps_smmu 0x1e05 0x1>, + <0x600 &apps_smmu 0x1e06 0x1>, + <0x700 &apps_smmu 0x1e07 0x1>, + <0x800 &apps_smmu 0x1e08 0x1>, + <0x900 &apps_smmu 0x1e09 0x1>, + <0xa00 &apps_smmu 0x1e0a 0x1>, + <0xb00 &apps_smmu 0x1e0b 0x1>, + <0xc00 &apps_smmu 0x1e0c 0x1>, + <0xd00 &apps_smmu 0x1e0d 0x1>, + <0xe00 &apps_smmu 0x1e0e 0x1>, + <0xf00 &apps_smmu 0x1e0f 0x1>; + + qcom,msm-bus,name = "pcie1"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <100 512 0 0>, + <100 512 500 800>; + + clocks = <&clock_gcc GCC_PCIE_1_PIPE_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_PCIE_1_AUX_CLK>, + <&clock_gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&clock_gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&clock_gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&clock_gcc GCC_PCIE_1_CLKREF_CLK>, + <&clock_gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&clock_gcc GCC_PCIE1_PHY_REFGEN_CLK>, + <&clock_gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src", + "pcie_1_aux_clk", "pcie_1_cfg_ahb_clk", + "pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk", + "pcie_1_ldo", "pcie_1_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&clock_gcc GCC_PCIE_1_BCR>, + <&clock_gcc GCC_PCIE_1_PHY_BCR>; + + reset-names = "pcie_1_core_reset", + "pcie_1_phy_reset"; + + pcie_rc1: pcie_rc1 { + reg = <0 0 0 0 0>; + pci-ids = "17cb:0108"; + }; + }; + + pcie1_msi: qcom,pcie1_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupt-parent = <&pdc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pcie1_edma: qcom,pcie1_edma@40002000 { + compatible = "qcom,pci-edma"; + #dma-cells = <2>; + reg = <0x40002000 0x2000>; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-names = "pci-edma-int"; + }; + + pcie_ep: qcom,pcie@40004000 { + compatible = "qcom,pcie-ep"; + + reg = <0x40004000 0x1000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40002000 0x2000>, + <0x01c08000 0x3000>, + <0x01c0e000 0x2000>, + <0x01c0b000 0x1000>; + reg-names = "msi", "dm_core", "elbi", "iatu", "edma", "parf", + "phy", "mmio"; + + #address-cells = <0>; + interrupt-parent = <&pcie_ep>; + interrupts = <0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 306 0>; + interrupt-names = "int_global"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default + &pcie_ep_wake_default>; + + clkreq-gpio = <&tlmm 103 0>; + perst-gpio = <&tlmm 102 0>; + wake-gpio = <&tlmm 104 0>; + + gdsc-vdd-supply = <&pcie_1_gdsc>; + vreg-1.8-supply = <&pm8195_1_l9>; + vreg-0.9-supply = <&pm8195_3_l5>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0.9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + clocks = <&clock_gcc GCC_PCIE_1_PIPE_CLK>, + <&clock_gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&clock_gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&clock_gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&clock_gcc GCC_PCIE_1_AUX_CLK>, + <&clock_gcc GCC_PCIE_1_CLKREF_CLK>, + <&clock_gcc GCC_PCIE_PHY_AUX_CLK>, + <&clock_gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + + clock-names = "pcie_pipe_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_aux_clk", "pcie_ldo", "pcie_sleep_clk", + "pcie_slv_q2a_axi_clk"; + + resets = <&clock_gcc GCC_PCIE_1_BCR>, + <&clock_gcc GCC_PCIE_1_PHY_BCR>; + + reset-names = "pcie_core_reset", + "pcie_phy_reset"; + + qcom,msm-bus,name = "pcie-ep"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <100 512 0 0>, + <100 512 500 800>; + + qcom,pcie-link-speed = <3>; + qcom,pcie-phy-ver = <6>; + qcom,pcie-aggregated-irq; + qcom,pcie-mhi-a7-irq; + qcom,phy-status-reg = <0xa14>; + + qcom,phy-init = <0x0a40 0x01 0x0 0x1 + 0x0094 0x00 0x0 0x1 + 0x000c 0x02 0x0 0x1 + 0x004c 0x07 0x0 0x1 + 0x0050 0x07 0x0 0x1 + 0x0058 0x0f 0x0 0x1 + 0x0074 0x36 0x0 0x1 + 0x0078 0x36 0x0 0x1 + 0x007c 0x12 0x0 0x1 + 0x0080 0x12 0x0 0x1 + 0x0084 0x00 0x0 0x1 + 0x0088 0x00 0x0 0x1 + 0x00a4 0x42 0x0 0x1 + 0x00ac 0xff 0x0 0x1 + 0x00b0 0x04 0x0 0x1 + 0x00b4 0xff 0x0 0x1 + 0x00b8 0x09 0x0 0x1 + 0x00bc 0x19 0x0 0x1 + 0x00c4 0x14 0x0 0x1 + 0x00ec 0xfb 0x0 0x1 + 0x00f0 0x01 0x0 0x1 + 0x00f4 0xfb 0x0 0x1 + 0x00f8 0x01 0x0 0x1 + 0x010c 0x02 0x0 0x1 + 0x0110 0x24 0x0 0x1 + 0x0118 0xb4 0x0 0x1 + 0x011c 0x03 0x0 0x1 + 0x0158 0x01 0x0 0x1 + 0x016c 0x08 0x0 0x1 + 0x01ac 0x56 0x0 0x1 + 0x01b0 0x1d 0x0 0x1 + 0x01b4 0x78 0x0 0x1 + 0x01b8 0x17 0x0 0x1 + 0x0154 0x31 0x0 0x1 + 0x01bc 0x11 0x0 0x1 + 0x0284 0x05 0x0 0x1 + 0x029c 0x12 0x0 0x1 + 0x0414 0x04 0x0 0x1 + 0x0434 0x7f 0x0 0x1 + 0x0444 0x70 0x0 0x1 + 0x04d8 0x01 0x0 0x1 + 0x04ec 0x0e 0x0 0x1 + 0x04f0 0x4a 0x0 0x1 + 0x04f4 0x0f 0x0 0x1 + 0x04f8 0xc0 0x0 0x1 + 0x04fc 0x00 0x0 0x1 + 0x0510 0x17 0x0 0x1 + 0x0518 0x1c 0x0 0x1 + 0x051c 0x03 0x0 0x1 + 0x0524 0x14 0x0 0x1 + 0x05b4 0x04 0x0 0x1 + 0x0570 0xbd 0x0 0x1 + 0x0574 0xbd 0x0 0x1 + 0x0578 0x7f 0x0 0x1 + 0x057c 0xdb 0x0 0x1 + 0x0580 0x76 0x0 0x1 + 0x0584 0x24 0x0 0x1 + 0x0588 0xe4 0x0 0x1 + 0x058c 0xec 0x0 0x1 + 0x0590 0x39 0x0 0x1 + 0x0594 0x37 0x0 0x1 + 0x0598 0xd4 0x0 0x1 + 0x059c 0x54 0x0 0x1 + 0x05a0 0xdb 0x0 0x1 + 0x05a4 0x39 0x0 0x1 + 0x05a8 0x31 0x0 0x1 + 0x0684 0x05 0x0 0x1 + 0x069c 0x12 0x0 0x1 + 0x0814 0x04 0x0 0x1 + 0x0834 0x7f 0x0 0x1 + 0x0844 0x70 0x0 0x1 + 0x08d8 0x01 0x0 0x1 + 0x08ec 0x0e 0x0 0x1 + 0x08f0 0x4a 0x0 0x1 + 0x08f4 0x0f 0x0 0x1 + 0x08f8 0xc0 0x0 0x1 + 0x08fc 0x00 0x0 0x1 + 0x0910 0x17 0x0 0x1 + 0x0918 0x1c 0x0 0x1 + 0x091c 0x03 0x0 0x1 + 0x0924 0x14 0x0 0x1 + 0x09b4 0x04 0x0 0x1 + 0x0970 0xbd 0x0 0x1 + 0x0974 0xbd 0x0 0x1 + 0x0978 0x7f 0x0 0x1 + 0x097c 0xdb 0x0 0x1 + 0x0980 0x76 0x0 0x1 + 0x0984 0x24 0x0 0x1 + 0x0988 0xe4 0x0 0x1 + 0x098c 0xec 0x0 0x1 + 0x0990 0x39 0x0 0x1 + 0x0994 0x37 0x0 0x1 + 0x0998 0xd4 0x0 0x1 + 0x099c 0x54 0x0 0x1 + 0x09a0 0xdb 0x0 0x1 + 0x09a4 0x39 0x0 0x1 + 0x09a8 0x31 0x0 0x1 + 0x0a98 0x01 0x0 0x1 + 0x0abc 0x56 0x0 0x1 + 0x0adc 0x0d 0x0 0x1 + 0x0b88 0xaa 0x0 0x1 + 0x0ba4 0x01 0x0 0x1 + 0x0e0c 0x04 0x0 0x1 + 0x0e14 0x07 0x0 0x1 + 0x0e40 0x01 0x0 0x1 + 0x0e48 0x01 0x0 0x1 + 0x0e78 0x50 0x0 0x1 + 0x0ea0 0x11 0x0 0x1 + 0x0ebc 0x00 0x0 0x1 + 0x0ee0 0x58 0x0 0x1 + 0x0a00 0x00 0x0 0x1 + 0x0a44 0x03 0x0 0x1>; + + edma-parent = <&pcie1_edma>; + iommus = <&apps_smmu 0x1e00 0x0>; + qcom,pcie-edma; + status = "disabled"; + }; + + mhi_device: mhi_dev@1c0b000 { + compatible = "qcom,msm-mhi-dev"; + reg = <0x1c0b000 0x1000>; + reg-names = "mhi_mmio_base"; + qcom,mhi-ep-msi = <0>; + qcom,mhi-version = <0x1000000>; + qcom,use-pcie-edma; + dmas = <&pcie1_edma 0 0>, <&pcie1_edma 1 0>; + dma-names = "tx", "rx"; + interrupts = <0 440 0>; + interrupt-names = "mhi-device-inta"; + qcom,mhi-ifc-id = <0x010817cb>; + qcom,mhi-interrupt; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sa8195p-regulator.dtsi b/arch/arm/boot/dts/qcom/sa8195p-regulator.dtsi new file mode 100644 index 000000000000..b7696d23f8d7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8195p-regulator.dtsi @@ -0,0 +1,850 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + /* Stub regulator */ + /* + * RPMh does not provide support for PM8195 S4 because it is always-on + * at 1.8 V in auto mode. Therefore, use a stub regulator for S4. + */ + S4A: pm8195_s4: regulator-pm8195-s4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8195_s4"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + /* PM8195_1 S1 = VDD_EBI supply */ + rpmh-regulator-ebilvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ebi.lvl"; + S1A_LEVEL: pm8195_1_s1_level: regulator-pm8195-1-s1-level { + regulator-name = "pm8195_1_s1_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + ebi_cdev: regulator-cdev { + compatible = "qcom,rpmh-reg-cdev"; + mboxes = <&qmp_aop 0>; + qcom,reg-resource-name = "ebi"; + #cooling-cells = <2>; + }; + }; + + /* PM8195_1 S2 = VDDCX_MM supply */ + rpmh-regulator-mmcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "mmcx.lvl"; + + VDD_MMCX_LEVEL: + S7A_LEVEL: pm8195_1_s7_level: regulator-pm8195-1-s7-level { + regulator-name = "pm8195_1_s7_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + VDD_MMCX_LEVEL_AO: S7A_LEVEL_AO: + pm8195_1_s7_level_ao: regulator-pm8195-1-s7-level-ao { + regulator-name = "pm8195_1_s7_level_ao"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + mm_cx_cdev: mm-cx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&VDD_MMCX_LEVEL_AO>; + regulator-levels = ; + #cooling-cells = <2>; + }; + }; + + rpmh-regulator-smpa3 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpa3"; + S3A: pm8195_1_s3: regulator-pm8195-1-s3 { + regulator-name = "pm8195_1_s3"; + qcom,set = ; + regulator-min-microvolt = <788000>; + regulator-max-microvolt = <969000>; + qcom,init-voltage = <788000>; + }; + }; + + rpmh-regulator-smpa5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpa5"; + S5A: pm8195_1_s5: regulator-pm8195-1-s5 { + regulator-name = "pm8195_1_s5"; + qcom,set = ; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1000000>; + qcom,init-voltage = <900000>; + }; + }; + + rpmh-regulator-smpa6 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpa6"; + S6A: pm8195_1_s6: regulator-pm8195-1-s6 { + regulator-name = "pm8195_1_s6"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <800000>; + }; + }; + + rpmh-regulator-smpa2 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpa2"; + S2A: pm8195_1_s2: regulator-pm8195-1-s2 { + regulator-name = "pm8195_1_s2"; + qcom,set = ; + regulator-min-microvolt = <1179000>; + regulator-max-microvolt = <1379000>; + qcom,init-voltage = <1179000>; + }; + }; + + /* pm8195_1 S8 = VDD_MODEM supply */ + rpmh-regulator-msslvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "mss.lvl"; + VDD_MSS_LEVEL: + S8A_LEVEL: pm8195_1_s8_level: regulator-pm8195-1-s8-level { + regulator-name = "pm8195_1_s8_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + /* PM8195_1 S10 = VDD_MX supply */ + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "mx.lvl"; + + VDD_MX_LEVEL: + S10A_LEVEL: pm8195_1_s10_level: regulator-pm8195-1-s10-level { + regulator-name = "pm8195_1_s10_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + VDD_MX_LEVEL_AO: S10A_LEVEL_AO: + pm8195_1_s10_level_ao: regulator-pm8195-1-s10-level-ao { + regulator-name = "pm8195_1_s10_level_ao"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + mx_cdev: mx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&VDD_MX_LEVEL>; + regulator-levels = ; + #cooling-cells = <2>; + }; + }; + + rpmh-regulator-ldoa2 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L2A: pm8195_1_l2: regulator-pm8195-1-l2 { + regulator-name = "pm8195_1_l2"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa3 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L3A: pm8195_1_l3: regulator-pm8195-1-l3 { + regulator-name = "pm8195_1_l3"; + qcom,set = ; + regulator-min-microvolt = <760000>; + regulator-max-microvolt = <816000>; + qcom,init-voltage = <760000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L5A: pm8195_1_l5: regulator-pm8195-1-l5 { + regulator-name = "pm8195_1_l5"; + qcom,set = ; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <880000>; + qcom,init-voltage = <720000>; + qcom,init-mode = ; + }; + }; + + /* DSI display 1.2 */ + rpmh-regulator-ldoa9 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L9A: pm8195_1_l9: regulator-pm8195-1-l9 { + regulator-name = "pm8195_1_l9"; + qcom,set = ; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + qcom,init-voltage = <1150000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa10 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L10A: pm8195_1_l10: regulator-pm8195-1-l10 { + regulator-name = "pm8195_1_l10"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <2700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa11 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L11A: pm8195_1_l11: regulator-pm8195-1-l11 { + regulator-name = "pm8195_1_l11"; + qcom,set = ; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1100000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa12 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L12A: pm8195_1_l12: regulator-pm8195-1-l12 { + regulator-name = "pm8195_1_l12"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1890000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa13 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L13A: pm8195_1_l13: regulator-pm8195-1-l13 { + regulator-name = "pm8195_1_l13"; + qcom,set = ; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2900000>; + qcom,init-voltage = <2500000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa15 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa15"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L15A: pm8195_1_l15: regulator-pm8195-1-l15 { + regulator-name = "pm8195_1_l15"; + qcom,set = ; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1751000>; + qcom,init-voltage = <1700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa16 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L16A: pm8195_1_l16: regulator-pm8195-1-l16 { + regulator-name = "pm8195_1_l16"; + qcom,set = ; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2900000>; + qcom,init-voltage = <2500000>; + qcom,init-mode = ; + }; + }; + + + rpmh-regulator-ldoa17 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L17A: pm8195_1_l17: regulator-pm8195-1-l17 { + regulator-name = "pm8195_1_l17"; + qcom,set = ; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <1700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa18 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa18"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L18A: pm8195_1_l18: regulator-pm8195-1-l18 { + regulator-name = "pm8195_1_l18"; + qcom,set = ; + regulator-min-microvolt = <831000>; + regulator-max-microvolt = <918000>; + qcom,init-voltage = <831000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-smpc1 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpc1"; + S1C: pm8195_2_s1: regulator-pm8195-2-s1 { + regulator-name = "pm8195_2_s1"; + qcom,set = ; + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <648000>; + qcom,init-voltage = <570000>; + }; + }; + + rpmh-regulator-smpc2 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpc2"; + S2C: pm8195_2_s2: regulator-pm8195-2-s2 { + regulator-name = "pm8195_2_s2"; + qcom,set = ; + regulator-min-microvolt = <1060000>; + regulator-max-microvolt = <1170000>; + qcom,init-voltage = <1060000>; + }; + }; + + rpmh-regulator-smpc4 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpc4"; + S4C: pm8195_2_s4: regulator-pm8195-2-s4 { + regulator-name = "pm8195_2_s4"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1620000>; + }; + }; + + rpmh-regulator-smpc5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpc5"; + S5C: pm8195_2_s5: regulator-pm8195-2-s5 { + regulator-name = "pm8195_2_s5"; + qcom,set = ; + regulator-min-microvolt = <1713000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1713000>; + }; + }; + + /* PM8195_2 S10 + S9 + S8 + S7 + S6 = VDD_GFX supply */ + rpmh-regulator-gfxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "gfx.lvl"; + VDD_GFX: + S10C_LEVEL: pm8195_2_s10_level: regulator-pm8195-2-s10-level { + regulator-name = "pm8195_2_s10_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + rpmh-regulator-ldoc2 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L2C: pm8195_2_l2: regulator-pm8195-2-l2 { + regulator-name = "pm8195_2_l2"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3330000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L5C: pm8195_2_l5: regulator-pm8195-2-l5 { + regulator-name = "pm8195_2_l5"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc7 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L7C: pm8195_2_l7: regulator-pm8195-2-l7 { + regulator-name = "pm8195_2_l7"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc10 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L10C: pm8195_2_l10: regulator-pm8195-2-l10 { + regulator-name = "pm8195_2_l10"; + qcom,set = ; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1620000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc11 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L11C: pm8195_2_l11: regulator-pm8195-2-l11 { + regulator-name = "pm8195_2_l11"; + qcom,set = ; + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1236000>; + qcom,init-voltage = <1144000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc12 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L12C: pm8195_2_l12: regulator-pm8195-2-l12 { + regulator-name = "pm8195_2_l12"; + qcom,set = ; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1700000>; + qcom,init-mode = ; + }; + }; + + + /* PM8195_3 S3 + S2 + S1 = VDD_CX supply */ + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "cx.lvl"; + pm8195_3_s3_level-parent-supply = <&VDD_MX_LEVEL>; + pm8195_3_s3_level_ao-parent-supply = <&VDD_MX_LEVEL_AO>; + + VDD_CX_LEVEL: + S3E_LEVEL: pm8195_3_s3_level: regulator-pm8195-3-s3-level { + regulator-name = "pm8195_3_s3_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + + VDD_CX_LEVEL_AO: S3E_LEVEL_AO: + pm8195_3_s3_level_ao: regulator-pm8195-3-s3-level-ao { + regulator-name = "pm8195_3_s3_level_ao"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + cx_cdev: regulator-cdev { + compatible = "qcom,rpmh-reg-cdev"; + mboxes = <&qmp_aop 0>; + qcom,reg-resource-name = "cx"; + #cooling-cells = <2>; + }; + }; + + rpmh-regulator-smpe4 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpe4"; + S4E: pm8195_3_s4: regulator-pm8195-3-s4 { + regulator-name = "pm8195_3_s4"; + qcom,set = ; + regulator-min-microvolt = <402000>; + regulator-max-microvolt = <1980000>; + qcom,init-voltage = <402000>; + }; + }; + + rpmh-regulator-smpe5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpe5"; + S5E: pm8195_3_s5: regulator-pm8195-3-s5 { + regulator-name = "pm8195_3_s5"; + qcom,set = ; + regulator-min-microvolt = <1811000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1811000>; + }; + }; + + /* PM8195_3 L4 - LPI_MX supply */ + rpmh-regulator-lmxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "lmx.lvl"; + L4E_LEVEL: pm8195_3_l4_level: regulator-pm8195-3-l4 { + regulator-name = "pm8195_3_l4_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ldoe5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L5E: pm8195_3_l5: regulator-pm8195-3-l5 { + regulator-name = "pm8195_3_l5"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <920000>; + qcom,init-voltage = <800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe7 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L7E: pm8195_3_l7: regulator-pm8195-3-l7 { + regulator-name = "pm8195_3_l7"; + qcom,set = ; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1700000>; + qcom,init-mode = ; + }; + }; + + /* pm8195_3 L8 - LPI_CX supply */ + rpmh-regulator-lcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "lcx.lvl"; + L8E_LEVEL: pm8195_3_l8_level: regulator-pm8195-3-l8 { + regulator-name = "pm8195_3_l8_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ldoe9 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L9E: pm8195_3_l9: regulator-pm8195-3-l9 { + regulator-name = "pm8195_3_l9"; + qcom,set = ; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + qcom,init-voltage = <830000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe10 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L10E: pm8195_3_l10: regulator-pm8195-3-l10 { + regulator-name = "pm8195_3_l10"; + qcom,set = ; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3544000>; + qcom,init-voltage = <2500000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe12 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L12E: pm8195_3_l12: regulator-pm8195-3-l12 { + regulator-name = "pm8195_3_l12"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe16 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L16E: pm8195_3_l16: regulator-pm8195-3-l16 { + regulator-name = "pm8195_3_l16"; + qcom,set = ; + regulator-min-microvolt = <2921000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <2921000>; + qcom,init-mode = ; + }; + }; + + + rpmh-regulator-ldoe17 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L17E: pm8195_3_l17: regulator-pm8195-3-l17 { + regulator-name = "pm8195_3_l17"; + qcom,set = ; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <2900000>; + qcom,init-mode = ; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sa8195p.dts b/arch/arm/boot/dts/qcom/sa8195p.dts new file mode 100644 index 000000000000..da96aeda0b5d --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8195p.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sa8195p.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195P AU SoC"; + compatible = "qcom,sdmshrike"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sa8195p.dtsi b/arch/arm/boot/dts/qcom/sa8195p.dtsi new file mode 100644 index 000000000000..237ab398e218 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sa8195p.dtsi @@ -0,0 +1,108 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdmshrike-v2.dtsi" +#include "sa8155-audio.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195P"; + qcom,msm-name = "SA8195P"; + qcom,msm-id = <405 0x20000>; +}; + +#include +&soc { + emac_hw: qcom,emac@00020000 { + compatible = "qcom,emac-dwc-eqos"; + qcom,arm-smmu; + emac-core-version = <3>; + reg = <0x20000 0x10000>, + <0x36000 0x100>, + <0x3D00000 0x300000>; + reg-names = "emac-base", "rgmii-base", "tlmm-central-base"; + interrupts-extended = <&pdc 0 689 4>, <&pdc 0 700 4>, + <&tlmm 124 2>, <&pdc 0 691 4>, + <&pdc 0 692 4>, <&pdc 0 693 4>, + <&pdc 0 694 4>, <&pdc 0 695 4>, + <&pdc 0 696 4>, <&pdc 0 697 4>, + <&pdc 0 698 4>, <&pdc 0 699 4>; + interrupt-names = "sbd-intr", "lpi-intr", + "phy-intr", "tx-ch0-intr", + "tx-ch1-intr", "tx-ch2-intr", + "tx-ch3-intr", "tx-ch4-intr", + "rx-ch0-intr", "rx-ch1-intr", + "rx-ch2-intr", "rx-ch3-intr"; + qcom,msm-bus,name = "emac"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <98 512 0 0>, <1 781 0 0>, /* No vote */ + <98 512 2500 0>, <1 781 0 40000>, /* 10Mbps vote */ + <98 512 25000 0>, <1 781 0 40000>, /* 100Mbps vote */ + <98 512 250000 0>, <1 781 0 40000>; /* 1000Mbps vote */ + qcom,bus-vector-names = "0", "10", "100", "1000"; + clocks = <&clock_gcc GCC_EMAC_AXI_CLK>, + <&clock_gcc GCC_EMAC_PTP_CLK>, + <&clock_gcc GCC_EMAC_RGMII_CLK>, + <&clock_gcc GCC_EMAC_SLV_AHB_CLK>; + clock-names = "emac_axi_clk", "emac_ptp_clk", + "emac_rgmii_clk", "emac_slv_ahb_clk"; + qcom,phy-reset = <&tlmm 79 GPIO_ACTIVE_HIGH>; + qcom,phy-intr-redirect = <&tlmm 124 GPIO_ACTIVE_LOW>; + gdsc_emac-supply = <&emac_gdsc>; + pinctrl-names = "dev-emac-mdc", + "dev-emac-mdio", + "dev-emac-rgmii_txd0_state", + "dev-emac-rgmii_txd1_state", + "dev-emac-rgmii_txd2_state", + "dev-emac-rgmii_txd3_state", + "dev-emac-rgmii_txc_state", + "dev-emac-rgmii_tx_ctl_state", + "dev-emac-rgmii_rxd0_state", + "dev-emac-rgmii_rxd1_state", + "dev-emac-rgmii_rxd2_state", + "dev-emac-rgmii_rxd3_state", + "dev-emac-rgmii_rxc_state", + "dev-emac-rgmii_rx_ctl_state", + "dev-emac-phy_intr", + "dev-emac-phy_reset_state"; + + pinctrl-0 = <&emac_mdc>; + pinctrl-1 = <&emac_mdio>; + + pinctrl-2 = <&emac_rgmii_txd0>; + pinctrl-3 = <&emac_rgmii_txd1>; + pinctrl-4 = <&emac_rgmii_txd2>; + pinctrl-5 = <&emac_rgmii_txd3>; + pinctrl-6 = <&emac_rgmii_txc>; + pinctrl-7 = <&emac_rgmii_tx_ctl>; + + pinctrl-8 = <&emac_rgmii_rxd0>; + pinctrl-9 = <&emac_rgmii_rxd1>; + pinctrl-10 = <&emac_rgmii_rxd2>; + pinctrl-11 = <&emac_rgmii_rxd3>; + pinctrl-12 = <&emac_rgmii_rxc>; + pinctrl-13 = <&emac_rgmii_rx_ctl>; + pinctrl-14 = <&emac_phy_intr>; + pinctrl-15 = <&emac_phy_reset_state>; + + io-macro-info { + io-macro-bypass-mode = <0>; + io-interface = "rgmii"; + }; + emac_emb_smmu: emac_emb_smmu { + compatible = "qcom,emac-smmu-embedded"; + iommus = <&apps_smmu 0x7C0 0x0>; + qcom,iova-mapping = <0x80000000 0x40000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-atp-overlay.dts b/arch/arm/boot/dts/qcom/sdmmagpie-atp-overlay.dts new file mode 100644 index 000000000000..53555bbaf0ba --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-atp-overlay.dts @@ -0,0 +1,32 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "sdmmagpie-atp.dtsi" +#include "sdmmagpie-ext-codec-audio-overlay.dtsi" +#include "sdmmagpie-external-codec.dtsi" + +/ { + model = "ATP"; + compatible = "qcom,sdmmagpie-atp", "qcom,sdmmagpie", "qcom,atp"; + qcom,msm-id = <365 0x0>; + qcom,board-id = <33 0>; +}; + +&dsi_sw43404_amoled_video_display { + qcom,dsi-display-active; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-atp.dts b/arch/arm/boot/dts/qcom/sdmmagpie-atp.dts new file mode 100644 index 000000000000..a4b9dbfdae78 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-atp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdmmagpie.dtsi" +#include "sdmmagpie-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDMMAGPIE PM6150 ATP"; + compatible = "qcom,sdmmagpie-atp", "qcom,sdmmagpie", "qcom,atp"; + qcom,board-id = <33 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-atp.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-atp.dtsi new file mode 100644 index 000000000000..b32c6be9d708 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-atp.dtsi @@ -0,0 +1,387 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "sdmmagpie-thermal-overlay.dtsi" + +#include +#include +#include +#include +#include "sdmmagpie-sde-display.dtsi" +#include "sdmmagpie-camera-sensor-idp.dtsi" + +&soc { + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + #include "qg-batterydata-mlp466076-3200mah.dtsi" + }; +}; + +&qupv3_se8_2uart { + status = "ok"; +}; + +&qupv3_se3_4uart { + status = "ok"; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v3"; + + vdda-phy-supply = <&pm6150_l4>; /* 0.88v */ + vdda-pll-supply = <&pm6150l_l3>; /* 1.2v */ + vdda-phy-max-microamp = <62900>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm6150_l19>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm6150_l12>; + vcc-max-microamp = <600000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm6150l_l3>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&qupv3_se2_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 37 0x00>; + qcom,nq-ven = <&tlmm 12 0x00>; + qcom,nq-firm = <&tlmm 36 0x00>; + qcom,nq-clkreq = <&tlmm 31 0x00>; + qcom,nq-esepwr = <&tlmm 94 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <37 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active + &nfc_clk_req_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend + &nfc_clk_req_suspend>; + }; +}; + +&sdhc_1 { + vdd-supply = <&pm6150_l19>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&pm6150_l12>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm6150l_l9>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&pm6150l_l6>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; + +&dsi_sw43404_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sw43404_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sw43404_amoled_fhd_plus_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_dual_sharp_wqhd_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; + qcom,platform-en-gpio = <&pm6150l_gpios 4 0>; + qcom,platform-bklight-en-gpio = <&pm6150l_gpios 5 0>; +}; + +&dsi_dual_sharp_wqhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; + qcom,platform-en-gpio = <&pm6150l_gpios 4 0>; + qcom,platform-bklight-en-gpio = <&pm6150l_gpios 5 0>; +}; + +&dsi_rm69298_truly_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_rm69298_truly_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_nt35695b_truly_fhd_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 11 0>; + qcom,platform-sec-reset-gpio = <&pm6150l_gpios 11 0>; + qcom,platform-en-gpio = <&pm6150l_gpios 4 0>; + qcom,platform-bklight-en-gpio = <&pm6150l_gpios 5 0>; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 11 0>; + qcom,platform-sec-reset-gpio = <&pm6150l_gpios 11 0>; + qcom,platform-en-gpio = <&pm6150l_gpios 4 0>; + qcom,platform-bklight-en-gpio = <&pm6150l_gpios 5 0>; + qcom,platform-te-gpio = <&tlmm 11 0>; +}; + +&sde_dp { + qcom,dp-aux-switch = <&fsa4480>; +}; + +&qupv3_se7_i2c { + status = "ok"; + st_fts@49 { + compatible = "st,fts"; + reg = <0x49>; + interrupt-parent = <&tlmm>; + interrupts = <9 0x2008>; + vdd-supply = <&pm6150_l10>; + avdd-supply = <&pm6150l_l7>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + st,irq-gpio = <&tlmm 9 0x2008>; + st,reset-gpio = <&tlmm 8 0x00>; + st,regulator_dvdd = "vdd"; + st,regulator_avdd = "avdd"; + st,x-flip; + st,y-flip; + }; +}; + +&pm6150_qg { + qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <100>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; +}; + +&pm6150_charger { + io-channels = <&pm6150_vadc ADC_USB_IN_V_16>, + <&pm6150_vadc ADC_USB_IN_I>, + <&pm6150_vadc ADC_CHG_TEMP>, + <&pm6150_vadc ADC_DIE_TEMP>, + <&pm6150l_vadc ADC_AMUX_THM1_PU2>, + <&pm6150_vadc ADC_SBUx>, + <&pm6150_vadc ADC_VPH_PWR>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage"; + qcom,battery-data = <&mtp_batterydata>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,fcc-stepping-enable; + qcom,suspend-input-on-debug-batt; + qcom,sec-charger-config = <3>; + qcom,thermal-mitigation = <4200000 3500000 3000000 + 2500000 2000000 1500000 1000000 500000>; + dpdm-supply = <&qusb_phy0>; +}; + +&pm6150_gpios { + smb_stat { + smb_stat_default: smb_stat_default { + pins = "gpio3"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = <0>; + }; + }; +}; + +&qupv3_se9_i2c { + status = "ok"; + #include "smb1390.dtsi" + #include "smb1355.dtsi" +}; + +&smb1355 { + /delete-property/ interrupts; + interrupts = <0x0 0xc2 0x0 IRQ_TYPE_LEVEL_LOW>; + status = "ok"; +}; + +&smb1355_charger { + status = "ok"; +}; + +&smb1390 { + /delete-property/ interrupts; + interrupts = <0x0 0xc2 0x0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1390_charger { + compatible = "qcom,smb1390-charger-psy"; + io-channels = <&pm6150l_vadc ADC_AMUX_THM2>; + io-channel-names = "cp_die_temp"; + status = "ok"; +}; + +&pm6150l_gpios { + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio2"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm6150l_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + linux,can-disable; + debounce-interval = <15>; + gpio-key,wakeup; + }; + }; +}; + +&thermal_zones { + quiet-therm-step { + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-audio-overlay.dtsi new file mode 100644 index 000000000000..f367b810b138 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-audio-overlay.dtsi @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm6150-audio-overlay.dtsi" + +&swr0 { + interrupts = <0 295 0>; +}; + +&swr1 { + interrupts = <0 297 0>; +}; + +&swr2 { + qcom,swr-wakeup-required = <0>; + interrupts = <0 296 0>, <0 500 0>; + interrupt-names = "swr_master_irq", "swr_wake_irq"; +}; + +&sm6150_snd { + qcom,model = "sm6150-wcd9375-snd-card"; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-audio.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-audio.dtsi new file mode 100644 index 000000000000..ef1c61a7c73d --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-audio.dtsi @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm6150-audio.dtsi" + +&msm_audio_ion { + iommus = <&apps_smmu 0x1b21 0x0>; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll-bus.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-bus.dtsi similarity index 77% rename from arch/arm64/boot/dts/qcom/atoll-bus.dtsi rename to arch/arm/boot/dts/qcom/sdmmagpie-bus.dtsi index 4d89e1db6489..3f614178c8ac 100644 --- a/arch/arm64/boot/dts/qcom/atoll-bus.dtsi +++ b/arch/arm/boot/dts/qcom/sdmmagpie-bus.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -16,27 +16,24 @@ &soc { ad_hoc_bus: ad-hoc-bus { compatible = "qcom,msm-bus-device"; - reg = <0x16E0000 0x15080>, - <0x1700000 0x1F880>, + reg = <0x16E0000 0x11080>, + <0x1700000 0x1F080>, <0x1500000 0x28000>, <0x9160000 0x03200>, <0x9680000 0x3E200>, - <0x1620000 0x4000>, + <0x1380000 0x40000>, <0x1740000 0x1C100>, - <0x1620000 0x17080>, - <0x1620000 0x4000>, - <0x1700000 0x1F880>, - <0x9990000 0x1600>, - <0x1620000 0x4000>, - <0x1620000 0x4000>; + <0x1620000 0x18080>, + <0x1620000 0x40000>, + <0x1620000 0x40000>, + <0x80A8000 0x01400>; reg-names = "aggre1_noc-base", "aggre2_noc-base", "config_noc-base", "dc_noc-base", "gem_noc-base", "mc_virt-base", "mmss_noc-base", "system_noc-base", - "ipa_virt-base", "compute_noc-base", - "npu_noc-base", "qup_virt-base", - "camnoc_virt-base"; + "ipa_virt-base", "camnoc_virt-base", + "compute_noc-base"; mbox-names = "apps_rsc", "disp_rsc"; mboxes = <&apps_rsc 0 &disp_rsc 0>; @@ -53,7 +50,7 @@ cell-id = ; label = "disp_rsc"; qcom,rsc-dev; - qcom,req_state = <3>; + qcom,req_state = <2>; }; /*BCMs*/ @@ -97,114 +94,106 @@ qcom,bcm-dev; }; - bcm_co0: bcm-co0 { - cell-id = ; - label = "CO0"; - qcom,bcm-name = "CO0"; - qcom,rscs = <&rsc_apps>; - qcom,bcm-dev; - }; - - bcm_ce0: bcm-ce0 { - cell-id = ; - label = "CE0"; - qcom,bcm-name = "CE0"; + bcm_mm1: bcm-mm1 { + cell-id = ; + label = "MM1"; + qcom,bcm-name = "MM1"; qcom,rscs = <&rsc_apps>; qcom,bcm-dev; }; - bcm_ip0: bcm-ip0 { - cell-id = ; - label = "IP0"; - qcom,bcm-name = "IP0"; + bcm_sh2: bcm-sh2 { + cell-id = ; + label = "SH2"; + qcom,bcm-name = "SH2"; qcom,rscs = <&rsc_apps>; qcom,bcm-dev; }; - bcm_cn0: bcm-cn0 { - cell-id = ; - label = "CN0"; - qcom,bcm-name = "CN0"; + bcm_sh3: bcm-sh3 { + cell-id = ; + label = "SH3"; + qcom,bcm-name = "SH3"; qcom,rscs = <&rsc_apps>; qcom,bcm-dev; }; - bcm_mm1: bcm-mm1 { - cell-id = ; - label = "MM1"; - qcom,bcm-name = "MM1"; + bcm_mm2: bcm-mm2 { + cell-id = ; + label = "MM2"; + qcom,bcm-name = "MM2"; qcom,rscs = <&rsc_apps>; qcom,bcm-dev; }; - bcm_cn1: bcm-cn1 { - cell-id = ; - label = "CN1"; - qcom,bcm-name = "CN1"; + bcm_mm3: bcm-mm3 { + cell-id = ; + label = "MM3"; + qcom,bcm-name = "MM3"; qcom,rscs = <&rsc_apps>; qcom,bcm-dev; }; - bcm_sh2: bcm-sh2 { - cell-id = ; - label = "SH2"; - qcom,bcm-name = "SH2"; + bcm_sh5: bcm-sh5 { + cell-id = ; + label = "SH5"; + qcom,bcm-name = "SH5"; qcom,rscs = <&rsc_apps>; qcom,bcm-dev; }; - bcm_mm2: bcm-mm2 { - cell-id = ; - label = "MM2"; - qcom,bcm-name = "MM2"; + bcm_sn0: bcm-sn0 { + cell-id = ; + label = "SN0"; + qcom,bcm-name = "SN0"; qcom,rscs = <&rsc_apps>; qcom,bcm-dev; }; - bcm_co2: bcm-co2 { - cell-id = ; - label = "CO2"; - qcom,bcm-name = "CO2"; + bcm_sh8: bcm-sh8 { + cell-id = ; + label = "SH8"; + qcom,bcm-name = "SH8"; qcom,rscs = <&rsc_apps>; qcom,bcm-dev; }; - bcm_qup0: bcm-qup0 { - cell-id = ; - label = "QUP0"; - qcom,bcm-name = "QUP0"; + bcm_sh10: bcm-sh10 { + cell-id = ; + label = "SH10"; + qcom,bcm-name = "SH10"; qcom,rscs = <&rsc_apps>; qcom,bcm-dev; }; - bcm_sh3: bcm-sh3 { - cell-id = ; - label = "SH3"; - qcom,bcm-name = "SH3"; + bcm_ce0: bcm-ce0 { + cell-id = ; + label = "CE0"; + qcom,bcm-name = "CE0"; qcom,rscs = <&rsc_apps>; qcom,bcm-dev; }; - bcm_co3: bcm-co3 { - cell-id = ; - label = "CO3"; - qcom,bcm-name = "CO3"; + bcm_ip0: bcm-ip0 { + cell-id = ; + label = "IP0"; + qcom,bcm-name = "IP0"; qcom,rscs = <&rsc_apps>; qcom,bcm-dev; }; - bcm_sh4: bcm-sh4 { - cell-id = ; - label = "SH4"; - qcom,bcm-name = "SH4"; + bcm_cn0: bcm-cn0 { + cell-id = ; + label = "CN0"; + qcom,bcm-name = "CN0"; qcom,rscs = <&rsc_apps>; qcom,bcm-dev; }; - bcm_sn0: bcm-sn0 { - cell-id = ; - label = "SN0"; - qcom,bcm-name = "SN0"; + bcm_qup0: bcm-qup0 { + cell-id = ; + label = "QUP0"; + qcom,bcm-name = "QUP0"; qcom,rscs = <&rsc_apps>; qcom,bcm-dev; }; @@ -225,14 +214,6 @@ qcom,bcm-dev; }; - bcm_sn3: bcm-sn3 { - cell-id = ; - label = "SN3"; - qcom,bcm-name = "SN3"; - qcom,rscs = <&rsc_apps>; - qcom,bcm-dev; - }; - bcm_sn4: bcm-sn4 { cell-id = ; label = "SN4"; @@ -241,14 +222,6 @@ qcom,bcm-dev; }; - bcm_sn7: bcm-sn7 { - cell-id = ; - label = "SN7"; - qcom,bcm-name = "SN7"; - qcom,rscs = <&rsc_apps>; - qcom,bcm-dev; - }; - bcm_sn9: bcm-sn9 { cell-id = ; label = "SN9"; @@ -257,10 +230,10 @@ qcom,bcm-dev; }; - bcm_sn10: bcm-sn10 { - cell-id = ; - label = "SN10"; - qcom,bcm-name = "SN10"; + bcm_sn11: bcm-sn11 { + cell-id = ; + label = "SN11"; + qcom,bcm-name = "SN11"; qcom,rscs = <&rsc_apps>; qcom,bcm-dev; }; @@ -273,6 +246,22 @@ qcom,bcm-dev; }; + bcm_sn14: bcm-sn14 { + cell-id = ; + label = "SN14"; + qcom,bcm-name = "SN14"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn15: bcm-sn15 { + cell-id = ; + label = "SN15"; + qcom,bcm-name = "SN15"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + bcm_acv_display: bcm-acv_display { cell-id = ; label = "ACV_DISPLAY"; @@ -329,8 +318,16 @@ qcom,bcm-dev; }; + bcm_mm3_display: bcm-mm3_display { + cell-id = ; + label = "MM3_DISPLAY"; + qcom,bcm-name = "MM3"; + qcom,rscs = <&rsc_disp>; + qcom,bcm-dev; + }; + /*Buses*/ - fab_aggre1_noc: fab-aggre1_noc { + fab_aggre1_noc: fab-aggre1_noc{ cell-id = ; label = "fab-aggre1_noc"; qcom,fab-dev; @@ -338,12 +335,11 @@ qcom,qos-off = <4096>; qcom,base-offset = <16384>; qcom,sbm-offset = <0>; - qcom,bypass-qos-prg; qcom,bus-type = <1>; clocks = <>; }; - fab_aggre2_noc: fab-aggre2_noc { + fab_aggre2_noc: fab-aggre2_noc{ cell-id = ; label = "fab-aggre2_noc"; qcom,fab-dev; @@ -351,25 +347,36 @@ qcom,qos-off = <4096>; qcom,base-offset = <20480>; qcom,sbm-offset = <0>; - qcom,bypass-qos-prg; qcom,bus-type = <1>; clocks = <>; }; - fab_compute_noc: fab-compute_noc { + fab_camnoc_virt: fab-camnoc_virt{ + cell-id = ; + label = "fab-camnoc_virt"; + qcom,fab-dev; + qcom,base-name = "camnoc_virt-base"; + qcom,qos-off = <0>; + qcom,base-offset = <0>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + clocks = <>; + }; + + fab_compute_noc: fab-compute_noc{ cell-id = ; label = "fab-compute_noc"; qcom,fab-dev; qcom,base-name = "compute_noc-base"; qcom,qos-off = <4096>; - qcom,base-offset = <57344>; + qcom,base-offset = <0>; qcom,sbm-offset = <0>; qcom,bypass-qos-prg; qcom,bus-type = <1>; clocks = <>; }; - fab_config_noc: fab-config_noc { + fab_config_noc: fab-config_noc{ cell-id = ; label = "fab-config_noc"; qcom,fab-dev; @@ -382,7 +389,7 @@ clocks = <>; }; - fab_dc_noc: fab-dc_noc { + fab_dc_noc: fab-dc_noc{ cell-id = ; label = "fab-dc_noc"; qcom,fab-dev; @@ -395,7 +402,7 @@ clocks = <>; }; - fab_gem_noc: fab-gem_noc { + fab_gem_noc: fab-gem_noc{ cell-id = ; label = "fab-gem_noc"; qcom,fab-dev; @@ -403,12 +410,11 @@ qcom,qos-off = <128>; qcom,base-offset = <176128>; qcom,sbm-offset = <0>; - qcom,bypass-qos-prg; qcom,bus-type = <1>; clocks = <>; }; - fab_ipa_virt: fab-ipa_virt { + fab_ipa_virt: fab-ipa_virt{ cell-id = ; label = "fab-ipa_virt"; qcom,fab-dev; @@ -420,7 +426,7 @@ clocks = <>; }; - fab_mc_virt: fab-mc_virt { + fab_mc_virt: fab-mc_virt{ cell-id = ; label = "fab-mc_virt"; qcom,fab-dev; @@ -432,58 +438,31 @@ clocks = <>; }; - fab_mmss_noc: fab-mmss_noc { + fab_mmss_noc: fab-mmss_noc{ cell-id = ; label = "fab-mmss_noc"; qcom,fab-dev; qcom,base-name = "mmss_noc-base"; - qcom,qos-off = <4096>; + qcom,qos-off = <128>; qcom,base-offset = <36864>; qcom,sbm-offset = <0>; - qcom,bypass-qos-prg; - qcom,bus-type = <1>; - clocks = <>; - }; - - fab_npu_noc: fab-npu_noc { - cell-id = ; - label = "fab-npu_noc"; - qcom,fab-dev; - qcom,base-name = "npu_noc-base"; - qcom,qos-off = <0>; - qcom,base-offset = <0>; - qcom,sbm-offset = <0>; - qcom,bypass-qos-prg; qcom,bus-type = <1>; clocks = <>; }; - fab_qup_virt: fab-qup_virt { - cell-id = ; - label = "fab-qup_virt"; - qcom,fab-dev; - qcom,base-name = "qup_virt-base"; - qcom,qos-off = <0>; - qcom,base-offset = <0>; - qcom,sbm-offset = <0>; - qcom,bypass-qos-prg; - clocks = <>; - }; - - fab_system_noc: fab-system_noc { + fab_system_noc: fab-system_noc{ cell-id = ; label = "fab-system_noc"; qcom,fab-dev; qcom,base-name = "system_noc-base"; qcom,qos-off = <4096>; - qcom,base-offset = <45056>; + qcom,base-offset = <40960>; qcom,sbm-offset = <0>; - qcom,bypass-qos-prg; qcom,bus-type = <1>; clocks = <>; }; - fab_gem_noc_display: fab-gem_noc_display { + fab_gem_noc_display: fab-gem_noc_display{ cell-id = ; label = "fab-gem_noc_display"; qcom,fab-dev; @@ -496,7 +475,7 @@ clocks = <>; }; - fab_mc_virt_display: fab-mc_virt_display { + fab_mc_virt_display: fab-mc_virt_display{ cell-id = ; label = "fab-mc_virt_display"; qcom,fab-dev; @@ -508,12 +487,12 @@ clocks = <>; }; - fab_mmss_noc_display: fab-mmss_noc_display { + fab_mmss_noc_display: fab-mmss_noc_display{ cell-id = ; label = "fab-mmss_noc_display"; qcom,fab-dev; qcom,base-name = "mmss_noc-base"; - qcom,qos-off = <4096>; + qcom,qos-off = <128>; qcom,base-offset = <36864>; qcom,sbm-offset = <0>; qcom,bypass-qos-prg; @@ -521,18 +500,6 @@ clocks = <>; }; - fab_camnoc_virt: fab-camnoc_virt{ - cell-id = ; - label = "fab-camnoc_virt"; - qcom,fab-dev; - qcom,base-name = "camnoc_virt-base"; - qcom,qos-off = <0>; - qcom,base-offset = <0>; - qcom,sbm-offset = <0>; - qcom,bypass-qos-prg; - clocks = <>; - }; - /*Masters*/ mas_qhm_a1noc_cfg: mas-qhm-a1noc-cfg { cell-id = ; @@ -543,29 +510,27 @@ qcom,bus-dev = <&fab_aggre1_noc>; }; - mas_qhm_qspi: mas-qhm-qspi { - cell-id = ; - label = "mas-qhm-qspi"; + mas_qhm_qup_center: mas-qhm-qup-center { + cell-id = ; + label = "mas-qhm-qup-center"; qcom,buswidth = <4>; qcom,agg-ports = <1>; qcom,qport = <5>; qcom,connections = <&slv_qns_a1noc_snoc>; qcom,bus-dev = <&fab_aggre1_noc>; - qcom,bcms = <&bcm_cn1>; + qcom,bcms = <&bcm_qup0>; qcom,ap-owned; qcom,prio = <2>; }; - mas_qhm_qup_0: mas-qhm-qup-0 { - cell-id = ; - label = "mas-qhm-qup-0"; + mas_qhm_tsif: mas-qhm-tsif { + cell-id = ; + label = "mas-qhm-tsif"; qcom,buswidth = <4>; qcom,agg-ports = <1>; - qcom,qport = <6>; qcom,connections = <&slv_qns_a1noc_snoc>; qcom,bus-dev = <&fab_aggre1_noc>; - qcom,ap-owned; - qcom,prio = <2>; + qcom,bcms = <&bcm_cn0>; }; mas_xm_emmc: mas-xm-emmc { @@ -576,7 +541,7 @@ qcom,qport = <3>; qcom,connections = <&slv_qns_a1noc_snoc>; qcom,bus-dev = <&fab_aggre1_noc>; - qcom,bcms = <&bcm_cn1>; + qcom,bcms = <&bcm_cn0>; qcom,ap-owned; qcom,prio = <2>; }; @@ -589,7 +554,20 @@ qcom,qport = <1>; qcom,connections = <&slv_qns_a1noc_snoc>; qcom,bus-dev = <&fab_aggre1_noc>; - qcom,bcms = <&bcm_cn1>; + qcom,bcms = <&bcm_cn0>; + qcom,ap-owned; + qcom,prio = <2>; + }; + + mas_xm_sdc4: mas-xm-sdc4 { + cell-id = ; + label = "mas-xm-sdc4"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <2>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,bcms = <&bcm_cn0>; qcom,ap-owned; qcom,prio = <2>; }; @@ -604,6 +582,12 @@ qcom,bus-dev = <&fab_aggre1_noc>; qcom,ap-owned; qcom,prio = <2>; + qcom,node-qos-clks { + clocks = + <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; + clock-names = + "clk-aggre-ufs-phy-axi-no-rate"; + }; }; mas_qhm_a2noc_cfg: mas-qhm-a2noc-cfg { @@ -620,23 +604,37 @@ label = "mas-qhm-qdss-bam"; qcom,buswidth = <4>; qcom,agg-ports = <1>; - qcom,qport = <6>; + qcom,qport = <8>; qcom,connections = <&slv_qns_a2noc_snoc>; qcom,bus-dev = <&fab_aggre2_noc>; qcom,ap-owned; qcom,prio = <2>; }; - mas_qhm_qup_1: mas-qhm-qup-1 { + mas_qhm_qup_north: mas-qhm-qup-north { cell-id = ; - label = "mas-qhm-qup-1"; + label = "mas-qhm-qup-north"; qcom,buswidth = <4>; qcom,agg-ports = <1>; - qcom,qport = <4>; + qcom,qport = <0>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,bcms = <&bcm_qup0>; + qcom,ap-owned; + qcom,prio = <2>; + }; + + mas_qnm_cnoc: mas-qnm-cnoc { + cell-id = ; + label = "mas-qnm-cnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <3>; qcom,connections = <&slv_qns_a2noc_snoc>; qcom,bus-dev = <&fab_aggre2_noc>; qcom,ap-owned; qcom,prio = <2>; + qcom,forwarding; }; mas_qxm_crypto: mas-qxm-crypto { @@ -668,12 +666,24 @@ qcom,node-qos-bcms = <7035 0 1>; }; + mas_xm_pcie3_0: mas-xm-pcie3-0 { + cell-id = ; + label = "mas-xm-pcie3-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <11>; + qcom,connections = <&slv_qns_pcie_gemnoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,ap-owned; + qcom,prio = <2>; + }; + mas_xm_qdss_etr: mas-xm-qdss-etr { cell-id = ; label = "mas-xm-qdss-etr"; qcom,buswidth = <8>; qcom,agg-ports = <1>; - qcom,qport = <7>; + qcom,qport = <9>; qcom,connections = <&slv_qns_a2noc_snoc>; qcom,bus-dev = <&fab_aggre2_noc>; qcom,ap-owned; @@ -685,26 +695,32 @@ label = "mas-xm-usb3-0"; qcom,buswidth = <8>; qcom,agg-ports = <1>; - qcom,qport = <8>; + qcom,qport = <12>; qcom,connections = <&slv_qns_a2noc_snoc>; qcom,bus-dev = <&fab_aggre2_noc>; qcom,ap-owned; qcom,prio = <2>; + qcom,node-qos-clks { + clocks = + <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + clock-names = + "clk-aggre-usb3-prim-axi-no-rate"; + }; }; mas_qxm_camnoc_hf0_uncomp: mas-qxm-camnoc-hf0-uncomp { cell-id = ; label = "mas-qxm-camnoc-hf0-uncomp"; qcom,buswidth = <32>; - qcom,agg-ports = <1>; + qcom,agg-ports = <2>; qcom,connections = <&slv_qns_camnoc_uncomp>; qcom,bus-dev = <&fab_camnoc_virt>; qcom,bcms = <&bcm_mm1>; }; - mas_qxm_camnoc_hf1_uncomp: mas-qxm-camnoc-hf1-uncomp { - cell-id = ; - label = "mas-qxm-camnoc-hf1-uncomp"; + mas_qxm_camnoc_rt_uncomp: mas-qxm-camnoc-rt-uncomp { + cell-id = ; + label = "mas-qxm-camnoc-rt-uncomp"; qcom,buswidth = <32>; qcom,agg-ports = <1>; qcom,connections = <&slv_qns_camnoc_uncomp>; @@ -722,32 +738,37 @@ qcom,bcms = <&bcm_mm1>; }; + mas_qxm_camnoc_nrt_uncomp: mas-qxm-camnoc-nrt-uncomp { + cell-id = ; + label = "mas-qxm-camnoc-nrt-uncomp"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_camnoc_uncomp>; + qcom,bus-dev = <&fab_camnoc_virt>; + qcom,bcms = <&bcm_mm1>; + }; + mas_qnm_npu: mas-qnm-npu { cell-id = ; label = "mas-qnm-npu"; qcom,buswidth = <32>; - qcom,agg-ports = <2>; - qcom,qport = <1 3>; + qcom,agg-ports = <1>; + qcom,qport = <1>; qcom,connections = <&slv_qns_cdsp_gemnoc>; qcom,bus-dev = <&fab_compute_noc>; - qcom,bcms = <&bcm_co2>; + qcom,bcms = <&bcm_sh10>; qcom,ap-owned; qcom,prio = <0>; - qcom,forwarding; }; - mas_qxm_npu_dsp: mas-qxm-npu-dsp { - cell-id = ; - label = "mas-qxm-npu-dsp"; - qcom,buswidth = <8>; + mas_qhm_spdm: mas-qhm-spdm { + cell-id = ; + label = "mas-qhm-spdm"; + qcom,buswidth = <4>; qcom,agg-ports = <1>; - qcom,qport = <5>; - qcom,connections = <&slv_qns_cdsp_gemnoc>; - qcom,bus-dev = <&fab_compute_noc>; - qcom,bcms = <&bcm_co3>; - qcom,ap-owned; - qcom,prio = <0>; - qcom,forwarding; + qcom,connections = <&slv_qns_cnoc_a2noc>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; }; mas_qnm_snoc: mas-qnm-snoc { @@ -755,34 +776,32 @@ label = "mas-qnm-snoc"; qcom,buswidth = <8>; qcom,agg-ports = <1>; - qcom,connections = <&slv_qhs_tlmm_3 &slv_qhs_tlmm_2 - &slv_qhs_camera_cfg &slv_qhs_sdc2 - &slv_qhs_mnoc_cfg &slv_qhs_ufs_mem_cfg - &slv_qhs_qm_cfg &slv_qhs_snoc_cfg - &slv_qhs_qm_mpu_cfg &slv_qhs_glm &slv_qhs_pdm - &slv_qhs_camera_nrt_throttle_cfg - &slv_qhs_a2_noc_cfg &slv_qhs_qdss_cfg - &slv_qhs_vsense_ctrl_cfg - &slv_qhs_camera_rt_throttle_cfg - &slv_qhs_npu_dsp_throttle_cfg - &slv_qhs_display_cfg &slv_qhs_qspi - &slv_qhs_display_throttle_cfg &slv_qhs_tlmm_1 - &slv_qhs_tcsr &slv_qhs_dcc_cfg - &slv_qhs_ddrss_cfg - &slv_qhs_display_rt_throttle_cfg - &slv_qhs_ahb2phy2 &slv_qhs_npu_cfg - &slv_qhs_ahb2phy0 &slv_qhs_gpuss_cfg - &slv_qhs_boot_rom &slv_qhs_venus_cfg - &slv_qhs_ipa &slv_qhs_security - &slv_qhs_aop &slv_qhs_imem_cfg - &slv_qhs_mss_cfg &slv_srvc_cnoc - &slv_qhs_usb3_0 &slv_qhs_venus_throttle_cfg - &slv_qhs_cpr_cx &slv_qhs_a1_noc_cfg - &slv_qhs_aoss &slv_qhs_prng - &slv_qhs_npu_dma_throttle_cfg &slv_qhs_emmc_cfg - &slv_qhs_crypto0_cfg &slv_qhs_pimem_cfg - &slv_qhs_cpr_mx &slv_qhs_qup0 - &slv_qhs_qup1 &slv_qhs_clk_ctl>; + qcom,connections = <&slv_qhs_tlmm_south + &slv_qhs_camera_cfg &slv_qhs_sdc4 + &slv_qhs_sdc2 &slv_qhs_mnoc_cfg + &slv_qhs_ufs_mem_cfg &slv_qhs_qupv3_center + &slv_qhs_glm &slv_qhs_pdm + &slv_qhs_camera_nrt_throttle_cfg + &slv_qhs_a2_noc_cfg &slv_qhs_qdss_cfg + &slv_qhs_camera_rt_throttle_cfg + &slv_qhs_display_cfg &slv_qhs_pcie_cfg + &slv_qhs_display_throttle_cfg &slv_qhs_tcsr + &slv_qhs_venus_cvp_throttle_cfg + &slv_qhs_ddrss_cfg &slv_qhs_ahb2phy_north + &slv_qhs_snoc_cfg &slv_qhs_gpuss_cfg + &slv_qhs_venus_cfg &slv_qhs_tsif + &slv_qhs_compute_dsp_cfg &slv_qhs_clk_ctl + &slv_qhs_aop &slv_qhs_qupv3_north + &slv_qhs_ahb2phy_south &slv_srvc_cnoc + &slv_qhs_ahb2phy_west &slv_qhs_usb3_0 + &slv_qhs_venus_throttle_cfg &slv_qhs_ipa + &slv_qhs_cpr_cx &slv_qhs_tlmm_west + &slv_qhs_a1_noc_cfg &slv_qhs_aoss + &slv_qhs_prng &slv_qhs_vsense_ctrl_cfg + &slv_qhs_emmc_cfg &slv_qhs_spdm + &slv_qhs_crypto0_cfg &slv_qhs_pimem_cfg + &slv_qhs_tlmm_north &slv_qhs_cpr_mx + &slv_qhs_imem_cfg>; qcom,bus-dev = <&fab_config_noc>; qcom,bcms = <&bcm_cn0>; }; @@ -792,36 +811,33 @@ label = "mas-xm-qdss-dap"; qcom,buswidth = <8>; qcom,agg-ports = <1>; - qcom,connections = <&slv_qhs_tlmm_3 &slv_qhs_tlmm_2 - &slv_qhs_camera_cfg &slv_qhs_sdc2 - &slv_qhs_mnoc_cfg &slv_qhs_ufs_mem_cfg - &slv_qhs_qm_cfg &slv_qhs_snoc_cfg - &slv_qhs_qm_mpu_cfg &slv_qhs_glm &slv_qhs_pdm - &slv_qhs_camera_nrt_throttle_cfg - &slv_qhs_a2_noc_cfg &slv_qhs_qdss_cfg - &slv_qhs_vsense_ctrl_cfg - &slv_qhs_camera_rt_throttle_cfg - &slv_qhs_npu_dsp_throttle_cfg - &slv_qhs_display_cfg &slv_qhs_qspi - &slv_qhs_display_throttle_cfg &slv_qhs_tlmm_1 - &slv_qhs_tcsr &slv_qhs_dcc_cfg - &slv_qhs_ddrss_cfg - &slv_qhs_display_rt_throttle_cfg - &slv_qhs_ahb2phy2 &slv_qhs_npu_cfg - &slv_qhs_ahb2phy0 &slv_qhs_gpuss_cfg - &slv_qhs_boot_rom &slv_qhs_venus_cfg - &slv_qhs_ipa &slv_qhs_security - &slv_qhs_aop &slv_qhs_imem_cfg - &slv_qhs_mss_cfg &slv_srvc_cnoc - &slv_qhs_usb3_0 &slv_qhs_venus_throttle_cfg - &slv_qhs_cpr_cx &slv_qhs_a1_noc_cfg - &slv_qhs_aoss &slv_qhs_prng - &slv_qhs_npu_dma_throttle_cfg &slv_qhs_emmc_cfg - &slv_qhs_crypto0_cfg &slv_qhs_pimem_cfg - &slv_qhs_cpr_mx &slv_qhs_qup0 - &slv_qhs_qup1 &slv_qhs_clk_ctl>; + qcom,connections = <&slv_qhs_tlmm_south + &slv_qhs_camera_cfg &slv_qhs_sdc4 + &slv_qhs_sdc2 &slv_qhs_mnoc_cfg + &slv_qhs_ufs_mem_cfg &slv_qhs_qupv3_center + &slv_qhs_glm &slv_qhs_pdm + &slv_qhs_camera_nrt_throttle_cfg + &slv_qhs_a2_noc_cfg &slv_qhs_qdss_cfg + &slv_qhs_camera_rt_throttle_cfg + &slv_qhs_display_cfg &slv_qhs_pcie_cfg + &slv_qhs_display_throttle_cfg &slv_qhs_tcsr + &slv_qhs_venus_cvp_throttle_cfg + &slv_qhs_ddrss_cfg &slv_qns_cnoc_a2noc + &slv_qhs_ahb2phy_north &slv_qhs_snoc_cfg + &slv_qhs_gpuss_cfg &slv_qhs_venus_cfg + &slv_qhs_tsif &slv_qhs_compute_dsp_cfg + &slv_qhs_clk_ctl &slv_qhs_aop + &slv_qhs_qupv3_north &slv_qhs_ahb2phy_south + &slv_srvc_cnoc &slv_qhs_ahb2phy_west + &slv_qhs_usb3_0 &slv_qhs_venus_throttle_cfg + &slv_qhs_ipa &slv_qhs_cpr_cx + &slv_qhs_tlmm_west &slv_qhs_a1_noc_cfg + &slv_qhs_aoss &slv_qhs_prng + &slv_qhs_vsense_ctrl_cfg &slv_qhs_emmc_cfg + &slv_qhs_spdm &slv_qhs_crypto0_cfg + &slv_qhs_pimem_cfg &slv_qhs_tlmm_north + &slv_qhs_cpr_mx &slv_qhs_imem_cfg>; qcom,bus-dev = <&fab_config_noc>; - qcom,bcms = <&bcm_cn0>; }; mas_qhm_cnoc_dc_noc: mas-qhm-cnoc-dc-noc { @@ -840,11 +856,12 @@ qcom,agg-ports = <1>; qcom,qport = <96 98>; qcom,connections = <&slv_qns_llcc - &slv_qns_gem_noc_snoc>; + &slv_qns_gem_noc_snoc>; qcom,bus-dev = <&fab_gem_noc>; - qcom,bcms = <&bcm_sh4>; + qcom,bcms = <&bcm_sh5>; qcom,ap-owned; qcom,prio = <0>; + qcom,forwarding; }; mas_acm_sys_tcu: mas-acm-sys-tcu { @@ -854,9 +871,9 @@ qcom,agg-ports = <1>; qcom,qport = <384>; qcom,connections = <&slv_qns_llcc - &slv_qns_gem_noc_snoc>; + &slv_qns_gem_noc_snoc>; qcom,bus-dev = <&fab_gem_noc>; - qcom,bcms = <&bcm_sh2>; + qcom,bcms = <&bcm_sh3>; qcom,ap-owned; qcom,prio = <6>; }; @@ -867,7 +884,7 @@ qcom,buswidth = <4>; qcom,agg-ports = <1>; qcom,connections = <&slv_srvc_gemnoc - &slv_qhs_mdsp_ms_mpu_cfg>; + &slv_qhs_mdsp_ms_mpu_cfg>; qcom,bus-dev = <&fab_gem_noc>; }; @@ -878,9 +895,8 @@ qcom,agg-ports = <1>; qcom,qport = <64>; qcom,connections = <&slv_qns_llcc - &slv_qns_gem_noc_snoc>; + &slv_qns_gem_noc_snoc>; qcom,bus-dev = <&fab_gem_noc>; - qcom,bcms = <&bcm_sh3>; qcom,ap-owned; qcom,prio = <0>; }; @@ -889,8 +905,8 @@ cell-id = ; label = "mas-qnm-mnoc-hf"; qcom,buswidth = <32>; - qcom,agg-ports = <1>; - qcom,qport = <128>; + qcom,agg-ports = <2>; + qcom,qport = <128 129>; qcom,connections = <&slv_qns_llcc>; qcom,bus-dev = <&fab_gem_noc>; qcom,ap-owned; @@ -906,7 +922,7 @@ qcom,agg-ports = <1>; qcom,qport = <320>; qcom,connections = <&slv_qns_llcc - &slv_qns_gem_noc_snoc>; + &slv_qns_gem_noc_snoc>; qcom,bus-dev = <&fab_gem_noc>; qcom,ap-owned; qcom,prio = <0>; @@ -914,6 +930,19 @@ qcom,node-qos-bcms = <7012 0 1>; }; + mas_qnm_pcie: mas-qnm-pcie { + cell-id = ; + label = "mas-qnm-pcie"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <224>; + qcom,connections = <&slv_qns_llcc + &slv_qns_gem_noc_snoc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <2>; + }; + mas_qnm_snoc_gc: mas-qnm-snoc-gc { cell-id = ; label = "mas-qnm-snoc-gc"; @@ -947,7 +976,7 @@ qcom,agg-ports = <2>; qcom,qport = <288 289>; qcom,connections = <&slv_qns_llcc - &slv_qns_gem_noc_snoc>; + &slv_qns_gem_noc_snoc>; qcom,bus-dev = <&fab_gem_noc>; qcom,ap-owned; qcom,prio = <0>; @@ -979,31 +1008,47 @@ qcom,agg-ports = <1>; qcom,connections = <&slv_srvc_mnoc>; qcom,bus-dev = <&fab_mmss_noc>; - qcom,bcms = <&bcm_mm1>; }; - mas_qxm_camnoc_hf0: mas-qxm-camnoc-hf0 { + mas_qxm_camnoc_hf: mas-qxm-camnoc-hf { cell-id = ; - label = "mas-qxm-camnoc-hf0"; + label = "mas-qxm-camnoc-hf"; qcom,buswidth = <32>; - qcom,agg-ports = <1>; - qcom,qport = <1>; + qcom,agg-ports = <2>; + qcom,qport = <32 64>; qcom,connections = <&slv_qns_mem_noc_hf>; qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm1>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + qcom,node-qos-bcms = <7012 0 1>; + }; + + mas_qxm_camnoc_nrt: mas-qxm-camnoc-nrt { + cell-id = ; + label = "mas-qxm-camnoc-nrt"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <258>; + qcom,connections = <&slv_qns2_mem_noc>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm2>; qcom,ap-owned; qcom,prio = <0>; qcom,forwarding; qcom,node-qos-bcms = <7012 0 1>; }; - mas_qxm_camnoc_hf1: mas-qxm-camnoc-hf1 { - cell-id = ; - label = "mas-qxm-camnoc-hf1"; + mas_qxm_camnoc_rt: mas-qxm-camnoc-rt { + cell-id = ; + label = "mas-qxm-camnoc-rt"; qcom,buswidth = <32>; qcom,agg-ports = <1>; - qcom,qport = <2>; + qcom,qport = <257>; qcom,connections = <&slv_qns_mem_noc_hf>; qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm1>; qcom,ap-owned; qcom,prio = <0>; qcom,forwarding; @@ -1016,8 +1061,9 @@ qcom,buswidth = <32>; qcom,agg-ports = <1>; qcom,qport = <0>; - qcom,connections = <&slv_qns_mem_noc_sf>; + qcom,connections = <&slv_qns2_mem_noc>; qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm3>; qcom,ap-owned; qcom,prio = <0>; qcom,forwarding; @@ -1029,7 +1075,7 @@ label = "mas-qxm-mdp0"; qcom,buswidth = <32>; qcom,agg-ports = <1>; - qcom,qport = <3>; + qcom,qport = <96>; qcom,connections = <&slv_qns_mem_noc_hf>; qcom,bus-dev = <&fab_mmss_noc>; qcom,bcms = <&bcm_mm1>; @@ -1039,13 +1085,13 @@ qcom,node-qos-bcms = <7012 0 1>; }; - mas_qxm_rot: mas-qxm-rot { - cell-id = ; - label = "mas-qxm-rot"; - qcom,buswidth = <16>; + mas_qxm_mdp1: mas-qxm-mdp1 { + cell-id = ; + label = "mas-qxm-mdp1"; + qcom,buswidth = <32>; qcom,agg-ports = <1>; - qcom,qport = <5>; - qcom,connections = <&slv_qns_mem_noc_sf>; + qcom,qport = <128>; + qcom,connections = <&slv_qns_mem_noc_hf>; qcom,bus-dev = <&fab_mmss_noc>; qcom,bcms = <&bcm_mm1>; qcom,ap-owned; @@ -1054,75 +1100,64 @@ qcom,node-qos-bcms = <7012 0 1>; }; - mas_qxm_venus0: mas-qxm-venus0 { - cell-id = ; - label = "mas-qxm-venus0"; + mas_qxm_rot: mas-qxm-rot { + cell-id = ; + label = "mas-qxm-rot"; qcom,buswidth = <32>; qcom,agg-ports = <1>; - qcom,qport = <6>; - qcom,connections = <&slv_qns_mem_noc_sf>; + qcom,qport = <160>; + qcom,connections = <&slv_qns2_mem_noc>; qcom,bus-dev = <&fab_mmss_noc>; - qcom,bcms = <&bcm_mm1>; + qcom,bcms = <&bcm_mm3>; qcom,ap-owned; qcom,prio = <0>; qcom,forwarding; qcom,node-qos-bcms = <7012 0 1>; }; - mas_qxm_venus_arm9: mas-qxm-venus-arm9 { - cell-id = ; - label = "mas-qxm-venus-arm9"; - qcom,buswidth = <8>; + mas_qxm_venus0: mas-qxm-venus0 { + cell-id = ; + label = "mas-qxm-venus0"; + qcom,buswidth = <32>; qcom,agg-ports = <1>; - qcom,qport = <8>; - qcom,connections = <&slv_qns_mem_noc_sf>; + qcom,qport = <192>; + qcom,connections = <&slv_qns2_mem_noc>; qcom,bus-dev = <&fab_mmss_noc>; - qcom,bcms = <&bcm_mm1>; + qcom,bcms = <&bcm_mm3>; qcom,ap-owned; - qcom,prio = <5>; + qcom,prio = <0>; qcom,forwarding; qcom,node-qos-bcms = <7012 0 1>; }; - mas_amm_npu_sys: mas-amm-npu-sys { - cell-id = ; - label = "mas-amm-npu-sys"; + mas_qxm_venus1: mas-qxm-venus1 { + cell-id = ; + label = "mas-qxm-venus1"; qcom,buswidth = <32>; - qcom,agg-ports = <2>; - qcom,connections = <&slv_qns_npu_sys>; - qcom,bus-dev = <&fab_npu_noc>; - }; - - mas_qhm_npu_cfg: mas-qhm-npu-cfg { - cell-id = ; - label = "mas-qhm-npu-cfg"; - qcom,buswidth = <4>; qcom,agg-ports = <1>; - qcom,connections = <&slv_srvc_noc &slv_qhs_isense - &slv_qhs_llm &slv_qhs_dma_bwmon &slv_qhs_cp - &slv_qhs_tcm &slv_qhs_cal_dp0 - &slv_qhs_dpm>; - qcom,bus-dev = <&fab_npu_noc>; - }; - - mas_qup_core_master_0: mas-qup-core-master-0 { - cell-id = ; - label = "mas-qup-core-master-0"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,connections = <&slv_qup_core_slave_0>; - qcom,bus-dev = <&fab_qup_virt>; - qcom,bcms = <&bcm_qup0>; + qcom,qport = <224>; + qcom,connections = <&slv_qns2_mem_noc>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm3>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + qcom,node-qos-bcms = <7012 0 1>; }; - mas_qup_core_master_1: mas-qup-core-master-1 { - cell-id = ; - label = "mas-qup-core-master-1"; - qcom,buswidth = <4>; + mas_qxm_venus_arm9: mas-qxm-venus-arm9 { + cell-id = ; + label = "mas-qxm-venus-arm9"; + qcom,buswidth = <8>; qcom,agg-ports = <1>; - qcom,connections = <&slv_qup_core_slave_1>; - qcom,bus-dev = <&fab_qup_virt>; - qcom,bcms = <&bcm_qup0>; + qcom,qport = <256>; + qcom,connections = <&slv_qns2_mem_noc>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm3>; + qcom,ap-owned; + qcom,prio = <5>; + qcom,forwarding; + qcom,node-qos-bcms = <7012 0 1>; }; mas_qhm_snoc_cfg: mas-qhm-snoc-cfg { @@ -1139,11 +1174,12 @@ label = "mas-qnm-aggre1-noc"; qcom,buswidth = <16>; qcom,agg-ports = <1>; - qcom,connections = <&slv_qns_gemnoc_sf &slv_qxs_pimem - &slv_qxs_imem &slv_qhs_apss &slv_qns_cnoc - &slv_xs_qdss_stm>; + qcom,connections = <&slv_qns_gemnoc_sf + &slv_qxs_pimem &slv_qxs_imem + &slv_qhs_apss &slv_qns_cnoc + &slv_xs_qdss_stm>; qcom,bus-dev = <&fab_system_noc>; - qcom,bcms = <&bcm_sn7>; + qcom,bcms = <&bcm_sn9>; }; mas_qnm_aggre2_noc: mas-qnm-aggre2-noc { @@ -1151,11 +1187,12 @@ label = "mas-qnm-aggre2-noc"; qcom,buswidth = <16>; qcom,agg-ports = <1>; - qcom,connections = <&slv_qns_gemnoc_sf &slv_qxs_pimem - &slv_qxs_imem &slv_qhs_apss &slv_qns_cnoc - &slv_xs_sys_tcu_cfg &slv_xs_qdss_stm>; + qcom,connections = <&slv_qns_gemnoc_sf + &slv_qxs_pimem &slv_qxs_imem + &slv_qhs_apss &slv_qns_cnoc + &slv_xs_sys_tcu_cfg &slv_xs_qdss_stm>; qcom,bus-dev = <&fab_system_noc>; - qcom,bcms = <&bcm_sn9>; + qcom,bcms = <&bcm_sn11>; }; mas_qnm_gemnoc: mas-qnm-gemnoc { @@ -1164,10 +1201,10 @@ qcom,buswidth = <8>; qcom,agg-ports = <1>; qcom,connections = <&slv_qxs_pimem &slv_qxs_imem - &slv_qhs_apss &slv_qns_cnoc - &slv_xs_sys_tcu_cfg &slv_xs_qdss_stm>; + &slv_qhs_apss &slv_qns_cnoc + &slv_xs_sys_tcu_cfg &slv_xs_qdss_stm>; qcom,bus-dev = <&fab_system_noc>; - qcom,bcms = <&bcm_sn12>; + qcom,bcms = <&bcm_sn15>; }; mas_qxm_pimem: mas-qxm-pimem { @@ -1175,20 +1212,44 @@ label = "mas-qxm-pimem"; qcom,buswidth = <8>; qcom,agg-ports = <1>; - qcom,qport = <2>; + qcom,qport = <3>; qcom,connections = <&slv_qns_gemnoc_gc &slv_qxs_imem>; qcom,bus-dev = <&fab_system_noc>; - qcom,bcms = <&bcm_sn2>; + qcom,bcms = <&bcm_sn12>; + qcom,ap-owned; + qcom,prio = <2>; + qcom,forwarding; + }; + + mas_xm_gic: mas-xm-gic { + cell-id = ; + label = "mas-xm-gic"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <0>; + qcom,connections = <&slv_qns_gemnoc_gc &slv_qxs_imem>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn12>; qcom,ap-owned; qcom,prio = <2>; + qcom,forwarding; + }; + + mas_alc: mas-alc { + cell-id = ; + label = "mas-alc"; + qcom,buswidth = <1>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_mc_virt>; + qcom,bcms = <&bcm_alc>; }; mas_qnm_mnoc_hf_display: mas-qnm-mnoc-hf_display { cell-id = ; label = "mas-qnm-mnoc-hf_display"; qcom,buswidth = <32>; - qcom,agg-ports = <1>; - qcom,qport = <128>; + qcom,agg-ports = <2>; + qcom,qport = <128 129>; qcom,connections = <&slv_qns_llcc_display>; qcom,bus-dev = <&fab_gem_noc_display>; }; @@ -1217,7 +1278,18 @@ label = "mas-qxm-mdp0_display"; qcom,buswidth = <32>; qcom,agg-ports = <1>; - qcom,qport = <3>; + qcom,qport = <96>; + qcom,connections = <&slv_qns_mem_noc_hf_display>; + qcom,bus-dev = <&fab_mmss_noc_display>; + qcom,bcms = <&bcm_mm1_display>; + }; + + mas_qxm_mdp1_display: mas-qxm-mdp1_display { + cell-id = ; + label = "mas-qxm-mdp1_display"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <128>; qcom,connections = <&slv_qns_mem_noc_hf_display>; qcom,bus-dev = <&fab_mmss_noc_display>; qcom,bcms = <&bcm_mm1_display>; @@ -1226,12 +1298,12 @@ mas_qxm_rot_display: mas-qxm-rot_display { cell-id = ; label = "mas-qxm-rot_display"; - qcom,buswidth = <16>; + qcom,buswidth = <32>; qcom,agg-ports = <1>; - qcom,qport = <5>; - qcom,connections = <&slv_qns_mem_noc_sf_display>; + qcom,qport = <160>; + qcom,connections = <&slv_qns2_mem_noc_display>; qcom,bus-dev = <&fab_mmss_noc_display>; - qcom,bcms = <&bcm_mm1_display>; + qcom,bcms = <&bcm_mm3_display>; }; /*Slaves*/ @@ -1242,6 +1314,7 @@ qcom,agg-ports = <1>; qcom,bus-dev = <&fab_aggre1_noc>; qcom,connections = <&mas_qnm_aggre1_noc>; + qcom,bcms = <&bcm_sn9>; }; slv_srvc_aggre1_noc:slv-srvc-aggre1-noc { @@ -1259,6 +1332,17 @@ qcom,agg-ports = <1>; qcom,bus-dev = <&fab_aggre2_noc>; qcom,connections = <&mas_qnm_aggre2_noc>; + qcom,bcms = <&bcm_sn11>; + }; + + slv_qns_pcie_gemnoc:slv-qns-pcie-gemnoc { + cell-id = ; + label = "slv-qns-pcie-gemnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,connections = <&mas_qnm_pcie>; + qcom,bcms = <&bcm_sn14>; }; slv_srvc_aggre2_noc:slv-srvc-aggre2-noc { @@ -1284,7 +1368,7 @@ qcom,agg-ports = <1>; qcom,bus-dev = <&fab_compute_noc>; qcom,connections = <&mas_qnm_cmpnoc>; - qcom,bcms = <&bcm_co0>; + qcom,bcms = <&bcm_sh8>; }; slv_qhs_a1_noc_cfg:slv-qhs-a1-noc-cfg { @@ -1307,22 +1391,31 @@ qcom,bcms = <&bcm_cn0>; }; - slv_qhs_ahb2phy0:slv-qhs-ahb2phy0 { + slv_qhs_ahb2phy_north:slv-qhs-ahb2phy-north { + cell-id = ; + label = "slv-qhs-ahb2phy-north"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_ahb2phy_south:slv-qhs-ahb2phy-south { cell-id = ; - label = "slv-qhs-ahb2phy0"; + label = "slv-qhs-ahb2phy-south"; qcom,buswidth = <4>; qcom,agg-ports = <1>; qcom,bus-dev = <&fab_config_noc>; qcom,bcms = <&bcm_cn0>; }; - slv_qhs_ahb2phy2:slv-qhs-ahb2phy2 { - cell-id = ; - label = "slv-qhs-ahb2phy2"; + slv_qhs_ahb2phy_west:slv-qhs-ahb2phy-west { + cell-id = ; + label = "slv-qhs-ahb2phy-west"; qcom,buswidth = <4>; qcom,agg-ports = <1>; qcom,bus-dev = <&fab_config_noc>; - qcom,bcms = <&bcm_cn1>; + qcom,bcms = <&bcm_cn0>; }; slv_qhs_aop:slv-qhs-aop { @@ -1343,15 +1436,6 @@ qcom,bcms = <&bcm_cn0>; }; - slv_qhs_boot_rom:slv-qhs-boot-rom { - cell-id = ; - label = "slv-qhs-boot-rom"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_config_noc>; - qcom,bcms = <&bcm_cn0>; - }; - slv_qhs_camera_cfg:slv-qhs-camera-cfg { cell-id = ; label = "slv-qhs-camera-cfg"; @@ -1359,6 +1443,7 @@ qcom,agg-ports = <1>; qcom,bus-dev = <&fab_config_noc>; qcom,bcms = <&bcm_cn0>; + qcom,disable-ports = <70 71>; }; slv_qhs_camera_nrt_throttle_cfg:slv-qhs-camera-nrt-thrott-cfg { @@ -1388,6 +1473,15 @@ qcom,bcms = <&bcm_cn0>; }; + slv_qhs_compute_dsp_cfg:slv-qhs-compute-dsp-cfg { + cell-id = ; + label = "slv-qhs-compute-dsp-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + slv_qhs_cpr_cx:slv-qhs-cpr-cx { cell-id = ; label = "slv-qhs-cpr-cx"; @@ -1415,15 +1509,6 @@ qcom,bcms = <&bcm_cn0>; }; - slv_qhs_dcc_cfg:slv-qhs-dcc-cfg { - cell-id = ; - label = "slv-qhs-dcc-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_config_noc>; - qcom,bcms = <&bcm_cn0>; - }; - slv_qhs_ddrss_cfg:slv-qhs-ddrss-cfg { cell-id = ; label = "slv-qhs-ddrss-cfg"; @@ -1441,15 +1526,7 @@ qcom,agg-ports = <1>; qcom,bus-dev = <&fab_config_noc>; qcom,bcms = <&bcm_cn0>; - }; - - slv_qhs_display_rt_throttle_cfg:slv-qhs-display-rt-throt-cfg { - cell-id = ; - label = "slv-qhs-display-rt-throttle-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_config_noc>; - qcom,bcms = <&bcm_cn0>; + qcom,disable-ports = <72 73>; }; slv_qhs_display_throttle_cfg:slv-qhs-display-throttle-cfg { @@ -1467,7 +1544,7 @@ qcom,buswidth = <4>; qcom,agg-ports = <1>; qcom,bus-dev = <&fab_config_noc>; - qcom,bcms = <&bcm_cn1>; + qcom,bcms = <&bcm_cn0>; }; slv_qhs_glm:slv-qhs-glm { @@ -1516,37 +1593,9 @@ qcom,bcms = <&bcm_cn0>; }; - slv_qhs_mss_cfg:slv-qhs-mss-cfg { - cell-id = ; - label = "slv-qhs-mss-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_config_noc>; - qcom,bcms = <&bcm_cn0>; - }; - - slv_qhs_npu_cfg:slv-qhs-npu-cfg { - cell-id = ; - label = "slv-qhs-npu-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_config_noc>; - qcom,connections = <&mas_qhm_npu_cfg>; - qcom,bcms = <&bcm_cn0>; - }; - - slv_qhs_npu_dma_throttle_cfg:slv-qhs-npu-dma-throttle-cfg { - cell-id = ; - label = "slv-qhs-npu-dma-throttle-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_config_noc>; - qcom,bcms = <&bcm_cn0>; - }; - - slv_qhs_npu_dsp_throttle_cfg:slv-qhs-npu-dsp-throttle-cfg { - cell-id = ; - label = "slv-qhs-npu-dsp-throttle-cfg"; + slv_qhs_pcie_cfg:slv-qhs-pcie-cfg { + cell-id = ; + label = "slv-qhs-pcie-cfg"; qcom,buswidth = <4>; qcom,agg-ports = <1>; qcom,bus-dev = <&fab_config_noc>; @@ -1559,7 +1608,7 @@ qcom,buswidth = <4>; qcom,agg-ports = <1>; qcom,bus-dev = <&fab_config_noc>; - qcom,bcms = <&bcm_cn1>; + qcom,bcms = <&bcm_cn0>; }; slv_qhs_pimem_cfg:slv-qhs-pimem-cfg { @@ -1589,45 +1638,18 @@ qcom,bcms = <&bcm_cn0>; }; - slv_qhs_qm_cfg:slv-qhs-qm-cfg { - cell-id = ; - label = "slv-qhs-qm-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_config_noc>; - qcom,bcms = <&bcm_cn0>; - }; - - slv_qhs_qm_mpu_cfg:slv-qhs-qm-mpu-cfg { - cell-id = ; - label = "slv-qhs-qm-mpu-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_config_noc>; - qcom,bcms = <&bcm_cn0>; - }; - - slv_qhs_qspi:slv-qhs-qspi { - cell-id = ; - label = "slv-qhs-qspi"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_config_noc>; - qcom,bcms = <&bcm_cn1>; - }; - - slv_qhs_qup0:slv-qhs-qup0 { + slv_qhs_qupv3_center:slv-qhs-qupv3-center { cell-id = ; - label = "slv-qhs-qup0"; + label = "slv-qhs-qupv3-center"; qcom,buswidth = <4>; qcom,agg-ports = <1>; qcom,bus-dev = <&fab_config_noc>; qcom,bcms = <&bcm_cn0>; }; - slv_qhs_qup1:slv-qhs-qup1 { + slv_qhs_qupv3_north:slv-qhs-qupv3-north { cell-id = ; - label = "slv-qhs-qup1"; + label = "slv-qhs-qupv3-north"; qcom,buswidth = <4>; qcom,agg-ports = <1>; qcom,bus-dev = <&fab_config_noc>; @@ -1640,12 +1662,12 @@ qcom,buswidth = <4>; qcom,agg-ports = <1>; qcom,bus-dev = <&fab_config_noc>; - qcom,bcms = <&bcm_cn1>; + qcom,bcms = <&bcm_cn0>; }; - slv_qhs_security:slv-qhs-security { - cell-id = ; - label = "slv-qhs-security"; + slv_qhs_sdc4:slv-qhs-sdc4 { + cell-id = ; + label = "slv-qhs-sdc4"; qcom,buswidth = <4>; qcom,agg-ports = <1>; qcom,bus-dev = <&fab_config_noc>; @@ -1662,6 +1684,15 @@ qcom,bcms = <&bcm_cn0>; }; + slv_qhs_spdm:slv-qhs-spdm { + cell-id = ; + label = "slv-qhs-spdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + slv_qhs_tcsr:slv-qhs-tcsr { cell-id = ; label = "slv-qhs-tcsr"; @@ -1671,27 +1702,36 @@ qcom,bcms = <&bcm_cn0>; }; - slv_qhs_tlmm_1:slv-qhs-tlmm-1 { - cell-id = ; - label = "slv-qhs-tlmm-1"; + slv_qhs_tlmm_north:slv-qhs-tlmm-north { + cell-id = ; + label = "slv-qhs-tlmm-north"; qcom,buswidth = <4>; qcom,agg-ports = <1>; qcom,bus-dev = <&fab_config_noc>; qcom,bcms = <&bcm_cn0>; }; - slv_qhs_tlmm_2:slv-qhs-tlmm-2 { - cell-id = ; - label = "slv-qhs-tlmm-2"; + slv_qhs_tlmm_south:slv-qhs-tlmm-south { + cell-id = ; + label = "slv-qhs-tlmm-south"; qcom,buswidth = <4>; qcom,agg-ports = <1>; qcom,bus-dev = <&fab_config_noc>; qcom,bcms = <&bcm_cn0>; }; - slv_qhs_tlmm_3:slv-qhs-tlmm-3 { - cell-id = ; - label = "slv-qhs-tlmm-3"; + slv_qhs_tlmm_west:slv-qhs-tlmm-west { + cell-id = ; + label = "slv-qhs-tlmm-west"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_tsif:slv-qhs-tsif { + cell-id = ; + label = "slv-qhs-tsif"; qcom,buswidth = <4>; qcom,agg-ports = <1>; qcom,bus-dev = <&fab_config_noc>; @@ -1723,6 +1763,16 @@ qcom,agg-ports = <1>; qcom,bus-dev = <&fab_config_noc>; qcom,bcms = <&bcm_cn0>; + qcom,disable-ports = <75 76>; + }; + + slv_qhs_venus_cvp_throttle_cfg:slv-qhs-venus-cvp-throttle-cfg { + cell-id = ; + label = "slv-qhs-venus-cvp-throttle-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; }; slv_qhs_venus_throttle_cfg:slv-qhs-venus-throttle-cfg { @@ -1743,6 +1793,16 @@ qcom,bcms = <&bcm_cn0>; }; + slv_qns_cnoc_a2noc:slv-qns-cnoc-a2noc { + cell-id = ; + label = "slv-qns-cnoc-a2noc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,connections = <&mas_qnm_cnoc>; + qcom,bcms = <&bcm_cn0>; + }; + slv_srvc_cnoc:slv-srvc-cnoc { cell-id = ; label = "slv-srvc-cnoc"; @@ -1784,13 +1844,14 @@ qcom,agg-ports = <1>; qcom,bus-dev = <&fab_gem_noc>; qcom,connections = <&mas_qnm_gemnoc>; + qcom,bcms = <&bcm_sh2>; }; slv_qns_llcc:slv-qns-llcc { cell-id = ; label = "slv-qns-llcc"; qcom,buswidth = <16>; - qcom,agg-ports = <1>; + qcom,agg-ports = <2>; qcom,bus-dev = <&fab_gem_noc>; qcom,connections = <&mas_llcc_mc>; qcom,bcms = <&bcm_sh0>; @@ -1822,24 +1883,24 @@ qcom,bcms = <&bcm_mc0>, <&bcm_acv>; }; - slv_qns_mem_noc_hf:slv-qns-mem-noc-hf { - cell-id = ; - label = "slv-qns-mem-noc-hf"; + slv_qns2_mem_noc:slv-qns2-mem-noc { + cell-id = ; + label = "slv-qns2-mem-noc"; qcom,buswidth = <32>; qcom,agg-ports = <1>; qcom,bus-dev = <&fab_mmss_noc>; - qcom,connections = <&mas_qnm_mnoc_hf>; - qcom,bcms = <&bcm_mm0>; + qcom,connections = <&mas_qnm_mnoc_sf>; + qcom,bcms = <&bcm_mm2>; }; - slv_qns_mem_noc_sf:slv-qns-mem-noc-sf { - cell-id = ; - label = "slv-qns-mem-noc-sf"; + slv_qns_mem_noc_hf:slv-qns-mem-noc-hf { + cell-id = ; + label = "slv-qns-mem-noc-hf"; qcom,buswidth = <32>; - qcom,agg-ports = <1>; + qcom,agg-ports = <2>; qcom,bus-dev = <&fab_mmss_noc>; - qcom,connections = <&mas_qnm_mnoc_sf>; - qcom,bcms = <&bcm_mm2>; + qcom,connections = <&mas_qnm_mnoc_hf>; + qcom,bcms = <&bcm_mm0>; }; slv_srvc_mnoc:slv-srvc-mnoc { @@ -1850,94 +1911,6 @@ qcom,bus-dev = <&fab_mmss_noc>; }; - slv_qhs_cal_dp0:slv-qhs-cal-dp0 { - cell-id = ; - label = "slv-qhs-cal-dp0"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_npu_noc>; - }; - - slv_qhs_cp:slv-qhs-cp { - cell-id = ; - label = "slv-qhs-cp"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_npu_noc>; - }; - - slv_qhs_dma_bwmon:slv-qhs-dma-bwmon { - cell-id = ; - label = "slv-qhs-dma-bwmon"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_npu_noc>; - }; - - slv_qhs_dpm:slv-qhs-dpm { - cell-id = ; - label = "slv-qhs-dpm"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_npu_noc>; - }; - - slv_qhs_isense:slv-qhs-isense { - cell-id = ; - label = "slv-qhs-isense"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_npu_noc>; - }; - - slv_qhs_llm:slv-qhs-llm { - cell-id = ; - label = "slv-qhs-llm"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_npu_noc>; - }; - - slv_qhs_tcm:slv-qhs-tcm { - cell-id = ; - label = "slv-qhs-tcm"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_npu_noc>; - }; - - slv_qns_npu_sys:slv-qns-npu-sys { - cell-id = ; - label = "slv-qns-npu-sys"; - qcom,buswidth = <32>; - qcom,agg-ports = <2>; - qcom,bus-dev = <&fab_npu_noc>; - }; - - slv_srvc_noc:slv-srvc-noc { - cell-id = ; - label = "slv-srvc-noc"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_npu_noc>; - }; - - slv_qup_core_slave_0:slv-qup-core-slave-0 { - cell-id = ; - label = "slv-qup-core-slave-0"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_qup_virt>; - }; - - slv_qup_core_slave_1:slv-qup-core-slave-1 { - cell-id = ; - label = "slv-qup-core-slave-1"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_qup_virt>; - }; - slv_qhs_apss:slv-qhs-apss { cell-id = ; label = "slv-qhs-apss"; @@ -1990,7 +1963,7 @@ qcom,buswidth = <8>; qcom,agg-ports = <1>; qcom,bus-dev = <&fab_system_noc>; - qcom,bcms = <&bcm_sn3>; + qcom,bcms = <&bcm_sn4>; }; slv_srvc_snoc:slv-srvc-snoc { @@ -2007,7 +1980,6 @@ qcom,buswidth = <4>; qcom,agg-ports = <1>; qcom,bus-dev = <&fab_system_noc>; - qcom,bcms = <&bcm_sn4>; }; slv_xs_sys_tcu_cfg:slv-xs-sys-tcu-cfg { @@ -2022,7 +1994,7 @@ cell-id = ; label = "slv-qns-llcc_display"; qcom,buswidth = <16>; - qcom,agg-ports = <1>; + qcom,agg-ports = <2>; qcom,bus-dev = <&fab_gem_noc_display>; qcom,connections = <&mas_llcc_mc_display>; qcom,bcms = <&bcm_sh0_display>; @@ -2037,24 +2009,24 @@ qcom,bcms = <&bcm_mc0_display>, <&bcm_acv_display>; }; - slv_qns_mem_noc_hf_display:slv-qns-mem-noc-hf_display { - cell-id = ; - label = "slv-qns-mem-noc-hf_display"; + slv_qns2_mem_noc_display:slv-qns2-mem-noc_display { + cell-id = ; + label = "slv-qns2-mem-noc_display"; qcom,buswidth = <32>; qcom,agg-ports = <1>; qcom,bus-dev = <&fab_mmss_noc_display>; - qcom,connections = <&mas_qnm_mnoc_hf_display>; - qcom,bcms = <&bcm_mm0_display>; + qcom,connections = <&mas_qnm_mnoc_sf_display>; + qcom,bcms = <&bcm_mm2_display>; }; - slv_qns_mem_noc_sf_display:slv-qns-mem-noc-sf_display { - cell-id = ; - label = "slv-qns-mem-noc-sf_display"; + slv_qns_mem_noc_hf_display:slv-qns-mem-noc-hf_display { + cell-id = ; + label = "slv-qns-mem-noc-hf_display"; qcom,buswidth = <32>; - qcom,agg-ports = <1>; + qcom,agg-ports = <2>; qcom,bus-dev = <&fab_mmss_noc_display>; - qcom,connections = <&mas_qnm_mnoc_sf_display>; - qcom,bcms = <&bcm_mm2_display>; + qcom,connections = <&mas_qnm_mnoc_hf_display>; + qcom,bcms = <&bcm_mm0_display>; }; }; }; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-camera-sensor-idp.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-camera-sensor-idp.dtsi new file mode 100644 index 000000000000..baf25c4013ef --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-camera-sensor-idp.dtsi @@ -0,0 +1,617 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2 &pm6150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2 &pm6150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux2: qcom,camera-flash@2 { + cell-index = <2>; + reg = <0x02 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2 &pm6150l_switch2>; + status = "ok"; + }; +}; + +&cam_cci0 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; + + actuator_rear: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2900000>; + rgltr-max-voltage = <2900000>; + rgltr-load-current = <100000>; + }; + + actuator_rear_aux: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2900000>; + rgltr-max-voltage = <2900000>; + rgltr-load-current = <100000>; + }; + + actuator_triple_tele: qcom,actuator@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2900000>; + rgltr-max-voltage = <2900000>; + rgltr-load-current = <100000>; + }; + + eeprom_rear: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1100000 0 2900000>; + rgltr-max-voltage = <1800000 2800000 1100000 0 2900000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 13 0>, + <&pm8009_gpios 1 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1200000 0 2900000>; + rgltr-max-voltage = <1800000 2800000 1200000 0 2900000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 14 0>, + <&pm8009_gpios 2 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 15 0>, + <&pm8009_gpios 4 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear_aux: qcom,eeprom@3 { + cell-index = <3>; + reg = <0x3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1100000 0 2900000>; + rgltr-max-voltage = <1800000 2800000 1100000 0 2900000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 13 0>, + <&pm8009_gpios 1 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_uw: qcom,eeprom@4 { + cell-index = <4>; + reg = <0x4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 15 0>, + <&pm8009_gpios 4 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + eeprom-src = <&eeprom_rear>; + actuator-src = <&actuator_rear>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1100000 0>; + rgltr-max-voltage = <1800000 2800000 1100000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 13 0>, + <&pm8009_gpios 1 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + actuator-src = <&actuator_rear_aux>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 14 0>, + <&pm8009_gpios 2 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x2>; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 15 0>, + <&pm8009_gpios 4 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x3>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_rear_aux>; + actuator-src = <&actuator_rear_aux>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 14 0>, + <&pm8009_gpios 2 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + reg = <0x4>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + eeprom-src = <&eeprom_rear>; + actuator-src = <&actuator_rear>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 13 0>, + <&pm8009_gpios 1 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + reg = <0x5>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_triple_rear_aux>; + actuator-src = <&actuator_triple_tele>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 14 0>, + <&pm8009_gpios 2 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@6 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + reg = <0x6>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_uw>; + led-flash-src = <&led_flash_rear_aux2>; + actuator-src = <&actuator_rear_aux>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 15 0>, + <&pm8009_gpios 4 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; + + +&pm8009_gpios { + cam_sensor_rear_active: cam_sensor_rear_active { + pins = "gpio1"; + function = "normal"; + power-source = <1>; + bias-disable; + }; + cam_sensor_rear_suspend: cam_sensor_rear_suspend { + pins = "gpio1"; + function = "normal"; + power-source = <1>; + bias-pull-down; + }; + + cam_sensor_rear2_active: cam_sensor_rear2_active { + pins = "gpio2"; + function = "normal"; + power-source = <1>; + bias-disable; + }; + cam_sensor_rear2_suspend: cam_sensor_rear2_suspend { + pins = "gpio2"; + function = "normal"; + power-source = <1>; + bias-pull-down; + }; + + cam_sensor_front_active: cam_sensor_front_active { + pins = "gpio4"; + function = "normal"; + power-source = <1>; + bias-disable; + }; + cam_sensor_front_suspend: cam_sensor_front_suspend { + pins = "gpio4"; + function = "normal"; + power-source = <1>; + bias-pull-down; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll-camera-sensor-qrd.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-camera-sensor-qrd.dtsi similarity index 67% rename from arch/arm64/boot/dts/qcom/atoll-camera-sensor-qrd.dtsi rename to arch/arm/boot/dts/qcom/sdmmagpie-camera-sensor-qrd.dtsi index 5171112d06df..0ce969d7e8f0 100644 --- a/arch/arm64/boot/dts/qcom/atoll-camera-sensor-qrd.dtsi +++ b/arch/arm/boot/dts/qcom/sdmmagpie-camera-sensor-qrd.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -10,8 +10,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - -#include +#include &soc { led_flash_rear: qcom,camera-flash@0 { @@ -33,34 +32,24 @@ switch-source = <&pm6150l_switch2 &pm6150l_switch2>; status = "ok"; }; +}; - vreg_tof: regulator-dbb1 { - compatible = "regulator-fixed"; - regulator-name = "vdd_tof"; - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - gpio = <&tlmm 118 GPIO_ACTIVE_HIGH>; - startup-delay-us = <1000>; - enable-active-high; - }; - +&cam_cci0 { qcom,cam-res-mgr { compatible = "qcom,cam-res-mgr"; status = "ok"; }; -}; -&cam_cci0 { actuator_rear: qcom,actuator@0 { cell-index = <0>; reg = <0x0>; compatible = "qcom,actuator"; cci-master = <0>; - cam_vaf-supply = <&L6P>; + cam_vaf-supply = <&pm8009_s2>; regulator-names = "cam_vaf"; rgltr-cntrl-support; - rgltr-min-voltage = <2800000>; - rgltr-max-voltage = <2800000>; + rgltr-min-voltage = <2900000>; + rgltr-max-voltage = <2900000>; rgltr-load-current = <100000>; }; @@ -68,17 +57,17 @@ cell-index = <0>; reg = <0>; compatible = "qcom,eeprom"; - cam_vio-supply = <&L5P>; - cam_vana-supply = <&L4P>; - cam_vdig-supply = <&L1P>; + actuator-src = <&actuator_rear>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l4>; cam_clk-supply = <&titan_top_gdsc>; - cam_vaf-supply = <&L6P>; regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk", "cam_vaf"; + "cam_clk"; rgltr-cntrl-support; - rgltr-min-voltage = <1800000 2800000 1104000 0 2800000>; - rgltr-max-voltage = <1800000 2800000 1104000 0 2800000>; - rgltr-load-current = <0 80000 105000 0 100000>; + rgltr-min-voltage = <1800000 2850000 1200000 0>; + rgltr-max-voltage = <1800000 2850000 1200000 0>; + rgltr-load-current = <0 80000 105000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk0_active @@ -86,7 +75,7 @@ pinctrl-1 = <&cam_sensor_mclk0_suspend &cam_sensor_rear_suspend>; gpios = <&tlmm 13 0>, - <&tlmm 30 0>; + <&pm8009_gpios 1 0>; gpio-reset = <1>; gpio-req-tbl-num = <0 1>; gpio-req-tbl-flags = <1 0>; @@ -101,20 +90,57 @@ clock-rates = <24000000>; }; + eeprom_rear_aux: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2850000 1200000 0>; + rgltr-max-voltage = <1800000 2850000 1200000 0>; + rgltr-load-current = <105000 0 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 14 0>, + <&pm8009_gpios 2 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + eeprom_front: qcom,eeprom@2 { cell-index = <2>; reg = <0x2>; compatible = "qcom,eeprom"; - cam_vio-supply = <&L5P>; - cam_vana-supply = <&L3P>; - cam_vdig-supply = <&L1P>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; cam_clk-supply = <&titan_top_gdsc>; regulator-names = "cam_vio", "cam_vana", "cam_vdig", "cam_clk"; rgltr-cntrl-support; - rgltr-min-voltage = <1800000 2800000 1104000 0>; - rgltr-max-voltage = <1800000 2800000 1104000 0>; - rgltr-load-current = <0 80000 105000 0>; + rgltr-min-voltage = <1800000 2850000 1200000 0>; + rgltr-max-voltage = <1800000 2850000 1200000 0>; + rgltr-load-current = <0 80000 105000 0 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk2_active @@ -122,15 +148,15 @@ pinctrl-1 = <&cam_sensor_mclk2_suspend &cam_sensor_front_suspend>; gpios = <&tlmm 15 0>, - <&tlmm 29 0>; + <&pm8009_gpios 4 0>; gpio-reset = <1>; gpio-req-tbl-num = <0 1>; gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2"; sensor-mode = <0>; - cci-device = <0>; - cci-master = <1>; + cci-device = <1>; + cci-master = <0>; status = "ok"; clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; clock-names = "cam_clk"; @@ -149,15 +175,15 @@ led-flash-src = <&led_flash_rear>; eeprom-src = <&eeprom_rear>; actuator-src = <&actuator_rear>; - cam_vio-supply = <&L5P>; - cam_vana-supply = <&L4P>; - cam_vdig-supply = <&L1P>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; cam_clk-supply = <&titan_top_gdsc>; regulator-names = "cam_vio", "cam_vana", "cam_vdig", "cam_clk"; rgltr-cntrl-support; - rgltr-min-voltage = <1800000 2800000 1104000 0>; - rgltr-max-voltage = <1800000 2800000 1104000 0>; + rgltr-min-voltage = <1800000 2800000 1100000 0>; + rgltr-max-voltage = <1800000 2800000 1100000 0>; rgltr-load-current = <0 80000 105000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -166,7 +192,7 @@ pinctrl-1 = <&cam_sensor_mclk0_suspend &cam_sensor_rear_suspend>; gpios = <&tlmm 13 0>, - <&tlmm 30 0>; + <&pm8009_gpios 1 0>; gpio-reset = <1>; gpio-req-tbl-num = <0 1>; gpio-req-tbl-flags = <1 0>; @@ -190,15 +216,16 @@ sensor-position-pitch = <0>; sensor-position-yaw = <180>; led-flash-src = <&led_flash_rear_aux>; - cam_vio-supply = <&L5P>; - cam_vana-supply = <&L3P>; - cam_vdig-supply = <&L2P>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l4>; cam_clk-supply = <&titan_top_gdsc>; regulator-names = "cam_vio", "cam_vana", "cam_vdig", "cam_clk"; rgltr-cntrl-support; - rgltr-min-voltage = <1800000 2800000 1104000 0>; - rgltr-max-voltage = <1800000 2800000 1104000 0>; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; rgltr-load-current = <0 80000 105000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -207,7 +234,7 @@ pinctrl-1 = <&cam_sensor_mclk1_suspend &cam_sensor_rear2_suspend>; gpios = <&tlmm 14 0>, - <&tlmm 25 0>; + <&pm8009_gpios 2 0>; gpio-reset = <1>; gpio-req-tbl-num = <0 1>; gpio-req-tbl-flags = <1 0>; @@ -225,21 +252,21 @@ qcom,cam-sensor@2 { cell-index = <2>; compatible = "qcom,cam-sensor"; - reg = <0x2>; + reg = <0x02>; csiphy-sd-index = <2>; sensor-position-roll = <270>; sensor-position-pitch = <0>; sensor-position-yaw = <0>; eeprom-src = <&eeprom_front>; - cam_vio-supply = <&L5P>; - cam_vana-supply = <&L3P>; - cam_vdig-supply = <&L1P>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; cam_clk-supply = <&titan_top_gdsc>; regulator-names = "cam_vio", "cam_vana", "cam_vdig", "cam_clk"; rgltr-cntrl-support; - rgltr-min-voltage = <1800000 2800000 1104000 0>; - rgltr-max-voltage = <1800000 2800000 1104000 0>; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; rgltr-load-current = <0 80000 105000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -248,15 +275,15 @@ pinctrl-1 = <&cam_sensor_mclk2_suspend &cam_sensor_front_suspend>; gpios = <&tlmm 15 0>, - <&tlmm 29 0>; + <&pm8009_gpios 4 0>; gpio-reset = <1>; gpio-req-tbl-num = <0 1>; gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK2", "CAM_RESET2"; sensor-mode = <0>; - cci-device = <0>; - cci-master = <1>; + cci-device = <1>; + cci-master = <0>; status = "ok"; clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; clock-names = "cam_clk"; @@ -265,44 +292,44 @@ }; }; -&cam_cci1 { - qcom,cam-sensor@3 { - cell-index = <3>; - compatible = "qcom,cam-sensor"; - reg = <0x3>; - csiphy-sd-index = <3>; - sensor-position-roll = <90>; - sensor-position-pitch = <0>; - sensor-position-yaw = <180>; - cam_vio-supply = <&L5P>; - cam_vdig-supply = <&vreg_tof>; - cam_clk-supply = <&titan_top_gdsc>; - regulator-names = "cam_vio", "cam_vdig", - "cam_clk"; - rgltr-cntrl-support; - rgltr-min-voltage = <1800000 3600000 0>; - rgltr-max-voltage = <1800000 3600000 0>; - rgltr-load-current = <0 120000 0>; - gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk3_active - &cam_sensor_tof_active>; - pinctrl-1 = <&cam_sensor_mclk3_suspend - &cam_sensor_tof_suspend>; - gpios = <&tlmm 16 0>, - <&tlmm 24 0>; - gpio-reset = <1>; - gpio-req-tbl-num = <0 1>; - gpio-req-tbl-flags = <1 0>; - gpio-req-tbl-label = "CAMIF_MCLK3", - "CAM_RESET3"; - sensor-mode = <0>; - cci-device = <1>; - cci-master = <0>; - status = "ok"; - clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; - clock-names = "cam_clk"; - clock-cntl-level = "turbo"; - clock-rates = <24000000>; + +&pm8009_gpios { + cam_sensor_rear_active: cam_sensor_rear_active { + pins = "gpio1"; + function = "normal"; + power-source = <1>; + bias-disable; + }; + cam_sensor_rear_suspend: cam_sensor_rear_suspend { + pins = "gpio1"; + function = "normal"; + power-source = <1>; + bias-pull-down; + }; + + cam_sensor_rear2_active: cam_sensor_rear2_active { + pins = "gpio2"; + function = "normal"; + power-source = <1>; + bias-disable; + }; + cam_sensor_rear2_suspend: cam_sensor_rear2_suspend { + pins = "gpio2"; + function = "normal"; + power-source = <1>; + bias-pull-down; + }; + + cam_sensor_front_active: cam_sensor_front_active { + pins = "gpio4"; + function = "normal"; + power-source = <1>; + bias-disable; + }; + cam_sensor_front_suspend: cam_sensor_front_suspend { + pins = "gpio4"; + function = "normal"; + power-source = <1>; + bias-pull-down; }; }; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-camera.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-camera.dtsi new file mode 100644 index 000000000000..955f23495de8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-camera.dtsi @@ -0,0 +1,1241 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + cam_csiphy0: qcom,csiphy@ace0000 { + cell-index = <0>; + compatible = "qcom,csiphy-v1.2", "qcom,csiphy"; + reg = <0x0ace0000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe0000>; + interrupts = <0 477 0>; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen"; + gdscr-supply = <&titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&pm6150l_l3>; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY0_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "svs", "svs_l1", "turbo"; + clock-rates = + <384000000 0 300000000 0>, + <400000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy@ace2000{ + cell-index = <1>; + compatible = "qcom,csiphy-v1.2", "qcom,csiphy"; + reg = <0xace2000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe2000>; + interrupts = <0 478 0>; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen"; + gdscr-supply = <&titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&pm6150l_l3>; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY0_CLK>, + <&clock_camcc CAM_CC_CSIPHY1_CLK>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "svs", "svs_l1", "turbo"; + clock-rates = + <384000000 0 0 300000000 0>, + <400000000 0 0 300000000 0>, + <400000000 0 0 300000000 0>; + + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy@ace4000 { + cell-index = <2>; + compatible = "qcom,csiphy-v1.2", "qcom,csiphy"; + reg = <0xace4000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe4000>; + interrupts = <0 479 0>; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen"; + gdscr-supply = <&titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&pm6150l_l3>; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY0_CLK>, + <&clock_camcc CAM_CC_CSIPHY2_CLK>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "svs", "svs_l1", "turbo"; + clock-rates = + <384000000 0 0 300000000 0>, + <400000000 0 0 300000000 0>, + <400000000 0 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy@ace6000 { + cell-index = <3>; + compatible = "qcom,csiphy-v1.2", "qcom,csiphy"; + reg = <0xace6000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe6000>; + interrupts = <0 607 0>; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen"; + gdscr-supply = <&titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&pm6150l_l3>; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY0_CLK>, + <&clock_camcc CAM_CC_CSIPHY3_CLK>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + src-clock-name = "csi3phytimer_clk_src"; + clock-cntl-level = "svs", "svs_l1", "turbo"; + clock-rates = + <384000000 0 0 300000000 0>, + <400000000 0 0 300000000 0>, + <400000000 0 0 300000000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci@ac4a000 { + cell-index = <0>; + compatible = "qcom,cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xac4a000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x4a000>; + interrupt-names = "cci"; + interrupts = <0 460 0>; + status = "ok"; + gdscr-supply = <&titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&clock_camcc CAM_CC_CCI_0_CLK>, + <&clock_camcc CAM_CC_CCI_0_CLK_SRC>; + clock-names = "cci_0_clk", + "cci_0_clk_src"; + src-clock-name = "cci_0_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <0 37500000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 17 0>, + <&tlmm 18 0>, + <&tlmm 19 0>, + <&tlmm 20 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci@ac4b000 { + cell-index = <1>; + compatible = "qcom,cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xac4b000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x4b000>; + interrupt-names = "cci"; + interrupts = <0 461 0>; + status = "ok"; + gdscr-supply = <&titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&clock_camcc CAM_CC_CCI_1_CLK>, + <&clock_camcc CAM_CC_CCI_1_CLK_SRC>; + clock-names = "cci_clk", + "cci_1_clk_src"; + src-clock-name = "cci_1_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <0 37500000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci2_active>; + pinctrl-1 = <&cci2_suspend>; + gpios = <&tlmm 27 0>, + <&tlmm 28 0>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA2", + "CCI_I2C_CLK2"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu"; + status = "ok"; + + msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x900 0x460>, + <&apps_smmu 0xD00 0x460>, + <&apps_smmu 0x880 0x460>, + <&apps_smmu 0xC80 0x460>, + <&apps_smmu 0x820 0x440>, + <&apps_smmu 0xC20 0x440>, + <&apps_smmu 0x920 0x460>, + <&apps_smmu 0xD20 0x460>, + <&apps_smmu 0x8A0 0x460>, + <&apps_smmu 0xCA0 0x460>, + <&apps_smmu 0x940 0x460>, + <&apps_smmu 0xD40 0x460>, + <&apps_smmu 0x8C0 0x460>, + <&apps_smmu 0xCC0 0x460>; + label = "ife"; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1280 0x20>, + <&apps_smmu 0x12A0 0x20>; + label = "jpeg"; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_icp_fw { + compatible = "qcom,msm-cam-smmu-fw-dev"; + label="icp"; + memory-region = <&pil_camera_mem>; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1180 0x0>, + <&apps_smmu 0x11E0 0x0>, + <&apps_smmu 0x11A0 0x0>, + <&apps_smmu 0x1200 0x0>, + <&apps_smmu 0x1260 0x0>, + <&apps_smmu 0x1220 0x0>, + <&apps_smmu 0x1042 0x0>, + <&apps_smmu 0x1300 0x60>, + <&apps_smmu 0x1320 0x60>; + label = "icp"; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-firmware { + /* Firmware region is 5MB */ + iova-region-name = "firmware"; + iova-region-start = <0x0>; + iova-region-len = <0x500000>; + iova-region-id = <0x0>; + status = "ok"; + }; + + iova-mem-region-shared { + /* Shared region is 150MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x9600000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-secondary-heap { + /* Secondary heap region is 1MB long */ + iova-region-name = "secheap"; + iova-region-start = <0x10A00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x4>; + status = "ok"; + }; + + iova-mem-region-io { + /* IO region is approximately 3 GB */ + iova-region-name = "io"; + iova-region-start = <0x10C00000>; + iova-region-len = <0xA9C00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x10B00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1000 0x0>; + label = "cpas-cdm0"; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + label = "cam-secure"; + qcom,secure-cb; + }; + + msm_cam_smmu_fd { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x12C0 0x20>, + <&apps_smmu 0x12E0 0x20>; + label = "fd"; + fd_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_lrme { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x11C0 0x0>, + <&apps_smmu 0x1240 0x0>; + label = "lrme"; + lrme_iova_mem_map: iova-mem-map { + iova-mem-region-shared { + /* Shared region is 100MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x6400000>; + iova-region-id = <0x1>; + status = "ok"; + }; + /* IO region is approximately 3.3 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0xd800000>; + iova-region-len = <0xd2800000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc", + "fd", + "lrmecdm"; + status = "ok"; + }; + + qcom,cpas-cdm0@ac48000 { + cell-index = <0>; + compatible = "qcom,cam170-cpas-cdm0"; + label = "cpas-cdm"; + reg = <0xac48000 0x1000>; + reg-names = "cpas-cdm"; + reg-cam-base = <0x48000>; + interrupts = <0 468 0>; + interrupt-names = "cpas-cdm"; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = "cam_cc_cpas_slow_ahb_clk", + "cam_cc_cpas_ahb_clk"; + clocks = <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0 0>; + clock-cntl-level = "svs"; + cdm-client-names = "ife"; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; + + cam_csid0: qcom,csid0@acb3000 { + cell-index = <0>; + compatible = "qcom,csid175_200"; + reg-names = "csid"; + reg = <0xacb3000 0x1000>; + reg-cam-base = <0xb3000>; + interrupt-names = "csid"; + interrupts = <0 464 0>; + regulator-names = "camss", "ife0"; + camss-supply = <&titan_top_gdsc>; + ife0-supply = <&ife_0_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <300000000 0 0 0 380000000 0 0>, + <384000000 0 0 0 510000000 0 0>, + <400000000 0 0 0 637000000 0 0>, + <400000000 0 0 0 760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe0: qcom,vfe0@acaf000 { + cell-index = <0>; + compatible = "qcom,vfe175_130"; + reg-names = "ife"; + reg = <0xacaf000 0x5200>; + reg-cam-base = <0xaf000>; + interrupt-names = "ife"; + interrupts = <0 465 0>; + regulator-names = "camss", "ife0"; + camss-supply = <&titan_top_gdsc>; + ife0-supply = <&ife_0_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <380000000 0 0>, + <510000000 0 0>, + <637000000 0 0>, + <760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <760000000>; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 3>; + status = "ok"; + }; + + cam_csid1: qcom,csid1@acba000 { + cell-index = <1>; + compatible = "qcom,csid175_200"; + reg-names = "csid"; + reg = <0xacba000 0x1000>; + reg-cam-base = <0xba000>; + interrupt-names = "csid"; + interrupts = <0 466 0>; + regulator-names = "camss", "ife1"; + camss-supply = <&titan_top_gdsc>; + ife1-supply = <&ife_1_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <300000000 0 0 0 380000000 0 0>, + <384000000 0 0 0 510000000 0 0>, + <400000000 0 0 0 637000000 0 0>, + <400000000 0 0 0 760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe1: qcom,vfe1@acb6000 { + cell-index = <1>; + compatible = "qcom,vfe175_130"; + reg-names = "ife"; + reg = <0xacb6000 0x5200>; + reg-cam-base = <0xb6000>; + interrupt-names = "ife"; + interrupts = <0 467 0>; + regulator-names = "camss", "ife1"; + camss-supply = <&titan_top_gdsc>; + ife1-supply = <&ife_1_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <380000000 0 0>, + <510000000 0 0>, + <637000000 0 0>, + <760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&clock_camcc CAM_CC_IFE_1_DSP_CLK>; + clock-rates-option = <760000000>; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 3>; + status = "ok"; + }; + + cam_csid_lite0: qcom,csid-lite0@acc8000 { + cell-index = <2>; + compatible = "qcom,csid-lite175"; + reg-names = "csid-lite"; + reg = <0xacc8000 0x1000>; + reg-cam-base = <0xc8000>; + interrupt-names = "csid-lite"; + interrupts = <0 438 0>; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <300000000 0 0 0 320000000 0>, + <384000000 0 0 0 400000000 0>, + <400000000 0 0 0 480000000 0>, + <400000000 0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite0: qcom,vfe-lite0@acc4000 { + cell-index = <2>; + compatible = "qcom,vfe-lite175"; + reg-names = "ife-lite"; + reg = <0xacc4000 0x4000>; + reg-cam-base = <0xc4000>; + interrupt-names = "ife-lite"; + interrupts = <0 434 0>; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <320000000 0>, + <400000000 0>, + <480000000 0>, + <600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,a5", + "qcom,ipe0", + "qcom,ipe1", + "qcom,bps"; + num-a5 = <1>; + num-ipe = <2>; + num-bps = <1>; + icp_pc_en; + status = "ok"; + }; + + cam_a5: qcom,a5@ac00000 { + cell-index = <0>; + compatible = "qcom,cam-a5"; + reg = <0xac00000 0x6000>, + <0xac10000 0x8000>, + <0xac18000 0x3000>; + reg-names = "a5_qgic", "a5_sierra", "a5_csr"; + reg-cam-base = <0x00000 0x10000 0x18000>; + interrupts = <0 463 0>; + interrupt-names = "a5"; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = + "soc_fast_ahb", + "icp_ahb_clk", + "icp_clk_src", + "icp_clk"; + clocks = + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_ICP_AHB_CLK>, + <&clock_camcc CAM_CC_ICP_CLK_SRC>, + <&clock_camcc CAM_CC_ICP_CLK>; + + clock-rates = + <200000000 0 400000000 0>, + <400000000 0 600000000 0>; + clock-cntl-level = "svs", "turbo"; + fw_name = "CAMERA_ICP.elf"; + ubwc-cfg = <0x73 0x1CF>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0 { + cell-index = <0>; + compatible = "qcom,cam-ipe"; + reg = <0xac87000 0x3000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x87000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&ipe_0_gdsc>; + clock-names = + "ipe_0_ahb_clk", + "ipe_0_areg_clk", + "ipe_0_axi_clk", + "ipe_0_clk_src", + "ipe_0_clk"; + src-clock-name = "ipe_0_clk_src"; + clock-control-debugfs = "true"; + clocks = + <&clock_camcc CAM_CC_IPE_0_AHB_CLK>, + <&clock_camcc CAM_CC_IPE_0_AREG_CLK>, + <&clock_camcc CAM_CC_IPE_0_AXI_CLK>, + <&clock_camcc CAM_CC_IPE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IPE_0_CLK>; + + clock-rates = + <0 0 0 340000000 0>, + <0 0 0 430000000 0>, + <0 0 0 520000000 0>, + <0 0 0 600000000 0>, + <0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 3>; + status = "ok"; + }; + + cam_ipe1: qcom,ipe1 { + cell-index = <1>; + compatible = "qcom,cam-ipe"; + reg = <0xac91000 0x3000>; + reg-names = "ipe1_top"; + reg-cam-base = <0x91000>; + regulator-names = "ipe1-vdd"; + ipe1-vdd-supply = <&ipe_1_gdsc>; + clock-names = + "ipe_1_ahb_clk", + "ipe_1_areg_clk", + "ipe_1_axi_clk", + "ipe_1_clk_src", + "ipe_1_clk"; + src-clock-name = "ipe_1_clk_src"; + clock-control-debugfs = "true"; + clocks = + <&clock_camcc CAM_CC_IPE_1_AHB_CLK>, + <&clock_camcc CAM_CC_IPE_1_AREG_CLK>, + <&clock_camcc CAM_CC_IPE_1_AXI_CLK>, + <&clock_camcc CAM_CC_IPE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IPE_1_CLK>; + + clock-rates = + <0 0 0 340000000 0>, + <0 0 0 430000000 0>, + <0 0 0 520000000 0>, + <0 0 0 600000000 0>, + <0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 3>; + status = "ok"; + }; + + cam_bps: qcom,bps { + cell-index = <0>; + compatible = "qcom,cam-bps"; + reg = <0xac6f000 0x3000>; + reg-names = "bps_top"; + reg-cam-base = <0x6f000>; + regulator-names = "bps-vdd"; + bps-vdd-supply = <&bps_gdsc>; + clock-names = + "bps_ahb_clk", + "bps_areg_clk", + "bps_axi_clk", + "bps_clk_src", + "bps_clk"; + src-clock-name = "bps_clk_src"; + clock-control-debugfs = "true"; + clocks = + <&clock_camcc CAM_CC_BPS_AHB_CLK>, + <&clock_camcc CAM_CC_BPS_AREG_CLK>, + <&clock_camcc CAM_CC_BPS_AXI_CLK>, + <&clock_camcc CAM_CC_BPS_CLK_SRC>, + <&clock_camcc CAM_CC_BPS_CLK>; + + clock-rates = + <0 0 0 200000000 0>, + <0 0 0 400000000 0>, + <0 0 0 480000000 0>, + <0 0 0 600000000 0>, + <0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 3>; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc", + "qcom,jpegdma"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + cam_jpeg_enc: qcom,jpegenc@ac4e000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc"; + reg-names = "jpege_hw"; + reg = <0xac4e000 0x4000>; + reg-cam-base = <0x4e000>; + interrupt-names = "jpeg"; + interrupts = <0 474 0>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = + "jpegenc_clk_src", + "jpegenc_clk"; + clocks = + <&clock_camcc CAM_CC_JPEG_CLK_SRC>, + <&clock_camcc CAM_CC_JPEG_CLK>; + + clock-rates = <600000000 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "nominal"; + status = "ok"; + }; + + cam_jpeg_dma: qcom,jpegdma@ac52000{ + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma"; + reg-names = "jpegdma_hw"; + reg = <0xac52000 0x4000>; + reg-cam-base = <0x52000>; + interrupt-names = "jpegdma"; + interrupts = <0 475 0>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = + "jpegdma_clk_src", + "jpegdma_clk"; + clocks = + <&clock_camcc CAM_CC_JPEG_CLK_SRC>, + <&clock_camcc CAM_CC_JPEG_CLK>; + + clock-rates = <600000000 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "nominal"; + status = "ok"; + }; + + qcom,cam-fd { + compatible = "qcom,cam-fd"; + compat-hw-name = "qcom,fd"; + num-fd = <1>; + status = "ok"; + }; + + cam_fd: qcom,fd@ac5a000 { + cell-index = <0>; + compatible = "qcom,fd501"; + reg-names = "fd_core", "fd_wrapper"; + reg = <0xac5a000 0x1000>, + <0xac5b000 0x400>; + reg-cam-base = <0x5a000 0x5b000>; + interrupt-names = "fd"; + interrupts = <0 462 0>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = + "fd_core_clk_src", + "fd_core_clk", + "fd_core_uar_clk"; + clocks = + <&clock_camcc CAM_CC_FD_CORE_CLK_SRC>, + <&clock_camcc CAM_CC_FD_CORE_CLK>, + <&clock_camcc CAM_CC_FD_CORE_UAR_CLK>; + src-clock-name = "fd_core_clk_src"; + clock-control-debugfs = "true"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + clock-rates = + <380000000 0 0>, + <384000000 0 0>, + <480000000 0 0>, + <600000000 0 0>; + status = "ok"; + }; + + qcom,cam-lrme { + compatible = "qcom,cam-lrme"; + arch-compat = "lrme"; + status = "ok"; + }; + + cam_lrme: qcom,lrme@ac6b000 { + cell-index = <0>; + compatible = "qcom,lrme"; + reg-names = "lrme"; + reg = <0xac6b000 0xa00>; + reg-cam-base = <0x6b000>; + interrupt-names = "lrme"; + interrupts = <0 476 0>; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = + "lrme_clk_src", + "lrme_clk"; + clocks = + <&clock_camcc CAM_CC_LRME_CLK_SRC>, + <&clock_camcc CAM_CC_LRME_CLK>; + clock-rates = + <240000000 0>, + <300000000 0>, + <320000000 0>, + <400000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "lrme_clk_src"; + status = "ok"; + }; + + qcom,cam-cpas@ac40000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + status = "ok"; + reg-names = "cam_cpas_top", "cam_camnoc"; + reg = <0xac40000 0x1000>, + <0xac42000 0x6000>; + reg-cam-base = <0x40000 0x42000>; + interrupt-names = "cpas_camnoc"; + interrupts = <0 459 0>; + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = + "gcc_ahb_clk", + "gcc_axi_hf_clk", + "gcc_axi_sf_clk", + "slow_ahb_clk_src", + "cpas_ahb_clk", + "camnoc_axi_clk_src", + "camnoc_axi_clk"; + clocks = + <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_HF_AXI_CLK>, + <&clock_gcc GCC_CAMERA_SF_AXI_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; + src-clock-name = "camnoc_axi_clk_src"; + clock-rates = + <0 0 0 0 0 0 0>, + <0 0 0 80000000 0 150000000 0>, + <0 0 0 80000000 0 240000000 0>, + <0 0 0 80000000 0 320000000 0>, + <0 0 0 80000000 0 400000000 0>, + <0 0 0 80000000 0 480000000 0>; + clock-cntl-level = "suspend", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 3>; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + qcom,msm-bus,name = "cam_ahb"; + qcom,msm-bus,num-cases = <6>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + , + , + , + ; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "suspend", + "minsvs", "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", + "cci0", "cci1", + "csid0", "csid1", "csid2", + "iferdi0", "ifenrdi0", "iferdi1", "ifenrdi1", + "iferdi2", "ifenrdi2", + "ipe0", "ipe1", "cam-cdm-intf0", "cpas-cdm0", + "bps0", "icp0", "jpeg-dma0", "jpeg-enc0", + "fd0", "lrmecpas0"; + client-axi-port-names = + "cam_hf_0", "cam_hf_0", "cam_hf_0", "cam_hf_0", + "cam_sf_0", "cam_sf_0", + "cam_hf_0", "cam_hf_0", "cam_hf_0", + "cam_hf_1", "cam_hf_0", "cam_hf_1", "cam_hf_0", + "cam_hf_1", "cam_hf_0", + "cam_sf_0", "cam_sf_0", "cam_sf_0", "cam_sf_0", + "cam_sf_0", "cam_sf_1", "cam_sf_0", "cam_sf_0", + "cam_sf_0", "cam_sf_0"; + client-bus-camnoc-based; + qcom,axi-port-list { + qcom,axi-port1 { + /* this port is clubbed port of two ports + * (READ and PIX ports) + */ + qcom,axi-port-name = "cam_hf_0"; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + qcom,msm-bus,name = "cam_hf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + qcom,axi-port-camnoc { + qcom,msm-bus,name = "cam_hf_0_camnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + qcom,axi-port2 { + /* this port is for rdi only WR*/ + qcom,axi-port-name = "cam_hf_1"; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + qcom,msm-bus,name = "cam_hf_1_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + qcom,axi-port-camnoc { + qcom,msm-bus,name = "cam_hf_1_camnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + qcom,axi-port3 { + qcom,axi-port-name = "cam_sf_0"; + qcom,axi-port-mnoc { + qcom,msm-bus,name = "cam_sf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + qcom,axi-port-camnoc { + qcom,msm-bus,name = "cam_sf_0_camnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + qcom,axi-port4 { + qcom,axi-port-name = "cam_sf_1"; + qcom,axi-port-mnoc { + qcom,msm-bus,name = "cam_sf_1_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + qcom,axi-port-camnoc { + qcom,msm-bus,name = "cam_sf_1_camnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-coresight.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-coresight.dtsi new file mode 100644 index 000000000000..30659c13fd84 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-coresight.dtsi @@ -0,0 +1,2721 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + + csr: csr@6001000 { + compatible = "qcom,coresight-csr"; + reg = <0x6001000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-csr"; + + qcom,usb-bam-support; + qcom,hwctrl-set-support; + qcom,set-byte-cntr-support; + qcom,blk-size = <1>; + }; + + replicator_qdss: replicator@6046000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b909>; + + reg = <0x6046000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out_tmc_etr: endpoint { + remote-endpoint = + <&tmc_etr_in_replicator>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_replicator1_in: endpoint { + remote-endpoint= + <&replicator1_in_replicator_out>; + }; + }; + + port@2 { + reg = <0>; + replicator_in_tmc_etf: endpoint { + slave-mode; + remote-endpoint = + <&tmc_etf_out_replicator>; + }; + }; + }; + }; + + replicator_qdss1: replicator@604a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b909>; + + reg = <0x604a000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-qdss1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <1>; + replicator1_out_funnel_swao: endpoint { + remote-endpoint= + <&funnel_swao_in_replicator1_out>; + }; + }; + + port@1 { + reg = <1>; + replicator1_in_replicator_out: endpoint { + slave-mode; + remote-endpoint= + <&replicator_out_replicator1_in>; + }; + }; + }; + }; + + tmc_etr: tmc@6048000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + + reg = <0x6048000 0x1000>, + <0x6064000 0x15000>; + reg-names = "tmc-base", "bam-base"; + + iommus = <&apps_smmu 0x05e0 0>, + <&apps_smmu 0x04a0 0>; + + arm,buffer-size = <0x400000>; + + coresight-name = "coresight-tmc-etr"; + coresight-ctis = <&cti0 &cti0>; + coresight-csr = <&csr>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + port { + tmc_etr_in_replicator: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_tmc_etr>; + }; + }; + }; + + tmc_etf: tmc@6047000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + + reg = <0x6047000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etf"; + coresight-ctis = <&cti0 &cti0>; + arm,default-sink; + coresight-csr = <&csr>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tmc_etf_out_replicator: endpoint { + remote-endpoint = + <&replicator_in_tmc_etf>; + }; + }; + + port@1 { + reg = <1>; + tmc_etf_in_funnel_merg: endpoint { + slave-mode; + remote-endpoint = + <&funnel_merg_out_tmc_etf>; + }; + }; + }; + + }; + + funnel_merg: funnel@6045000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6045000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-merg"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_merg_out_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_in_funnel_merg>; + }; + }; + + port@1 { + reg = <0>; + funnel_merg_in_funnel_in0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in0_out_funnel_merg>; + }; + }; + + port@2 { + reg = <1>; + funnel_merg_in_funnel_in1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in1_out_funnel_merg>; + }; + }; + + port@3 { + reg = <2>; + funnel_merg_in_funnel_in2: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in2_out_funnel_merg>; + }; + }; + }; + }; + + funnel_in0: funnel@0x6041000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6041000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in0_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in0>; + }; + }; + + port@1 { + reg = <4>; + funnel_in0_in_tpdm_lpass: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_lpass_out_funnel_in0>; + }; + }; + + port@2 { + reg = <4>; + funnel_in0_in_audio_etm0: endpoint { + slave-mode; + remote-endpoint = + <&audio_etm0_out_funnel_in0>; + }; + }; + + port@3 { + reg = <6>; + funnel_in0_in_funnel_qatb: endpoint { + slave-mode; + remote-endpoint = + <&funnel_qatb_out_funnel_in0>; + }; + }; + + port@4 { + reg = <7>; + funnel_in0_in_stm: endpoint { + slave-mode; + remote-endpoint = <&stm_out_funnel_in0>; + }; + }; + }; + }; + + audio_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-audio-etm0"; + qcom,inst-id = <5>; + + port { + audio_etm0_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_audio_etm0>; + }; + }; + }; + + funnel_in1: funnel@6042000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6042000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in1_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in1>; + }; + }; + + port@1 { + reg = <3>; + funnel_in1_in_modem_etm0: endpoint { + slave-mode; + remote-endpoint = + <&modem_etm0_out_funnel_in1>; + }; + }; + + port@2 { + reg = <4>; + funnel_in1_in_replicator_swao: endpoint { + slave-mode; + remote-endpoint = + <&replicator_swao_out_funnel_in1>; + }; + }; + + port@3 { + reg = <5>; + funnel_in1_in_funnel_modem: endpoint { + slave-mode; + remote-endpoint = + <&funnel_modem_out_funnel_in1>; + }; + }; + }; + }; + + funnel_modem: funnel@6832000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6832000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-modem"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_modem_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_modem>; + }; + }; + + port@1 { + reg = <0>; + funnel_modem_in_tpda_modem_0: endpoint { + slave-mode; + remote-endpoint = + <&tpda_modem_0_out_funnel_modem>; + }; + }; + + port@2 { + reg = <1>; + funnel_modem_in_tpda_modem_1: endpoint { + slave-mode; + remote-endpoint = + <&tpda_modem_1_out_funnel_modem>; + }; + }; + }; + }; + + tpda_modem0: tpda@6831000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6831000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-modem-0"; + + qcom,tpda-atid = <67>; + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_modem_0_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_tpda_modem_0>; + }; + }; + + port@1 { + reg = <0>; + tpda_modem_0_in_tpdm_modem_0: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_modem_0_out_tpda_modem_0>; + }; + }; + }; + }; + + tpda_modem1: tpda@6833000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6833000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-modem-1"; + + qcom,tpda-atid = <98>; + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_modem_1_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_tpda_modem_1>; + }; + }; + + port@1 { + reg = <0>; + tpda_modem_1_in_tpdm_modem_1: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_modem_1_out_tpda_modem_1>; + }; + }; + }; + }; + + tpdm_modem0: tpdm@6830000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6830000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-modem-0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_modem_0_out_tpda_modem_0: endpoint { + remote-endpoint = + <&tpda_modem_0_in_tpdm_modem_0>; + }; + }; + }; + + tpdm_modem1: tpdm@6834000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6834000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-modem-1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_modem_1_out_tpda_modem_1: endpoint { + remote-endpoint = + <&tpda_modem_1_in_tpdm_modem_1>; + }; + }; + }; + + modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem-etm0"; + qcom,inst-id = <2>; + + port { + modem_etm0_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_modem_etm0>; + }; + }; + }; + + dummy_eud: dummy_sink { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-eud"; + + qcom,dummy-sink; + port { + eud_in_replicator_swao: endpoint { + slave-mode; + remote-endpoint = + <&replicator_swao_out_eud>; + }; + }; + }; + + replicator_swao: replicator@6b0a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b909>; + + reg = <0x6b0a000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-swao"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* Always have EUD before funnel leading to ETR. If both + * sink are active we need to give preference to EUD + * over ETR + */ + port@0 { + reg = <1>; + replicator_swao_out_eud: endpoint { + remote-endpoint = + <&eud_in_replicator_swao>; + }; + }; + + port@1 { + reg = <0>; + replicator_swao_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_replicator_swao>; + }; + }; + + port@2 { + reg = <0>; + replicator_swao_in_tmc_etf_swao: endpoint { + slave-mode; + remote-endpoint = + <&tmc_etf_swao_out_replicator_swao>; + }; + }; + + }; + }; + + tmc_etf_swao: tmc@6b09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + + reg = <0x6b09000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etf-swao"; + coresight-csr = <&csr>; + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tmc_etf_swao_out_replicator_swao: endpoint { + remote-endpoint= + <&replicator_swao_in_tmc_etf_swao>; + }; + }; + + port@1 { + reg = <0>; + tmc_etf_swao_in_funnel_swao: endpoint { + slave-mode; + remote-endpoint= + <&funnel_swao_out_tmc_etf_swao>; + }; + }; + }; + + }; + + swao_csr: csr@6b0e000 { + compatible = "qcom,coresight-csr"; + reg = <0x6b0e000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-swao-csr"; + qcom,timestamp-support; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,blk-size = <1>; + }; + + funnel_swao: funnel@6b08000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6b08000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-swao"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_swao_out_tmc_etf_swao: endpoint { + remote-endpoint = + <&tmc_etf_swao_in_funnel_swao>; + }; + }; + + port@1 { + reg = <6>; + funnel_swao_in_replicator1_out: endpoint { + slave-mode; + remote-endpoint= + <&replicator1_out_funnel_swao>; + }; + }; + + port@2 { + reg = <7>; + funnel_swao_in_tpda_swao: endpoint { + slave-mode; + remote-endpoint= + <&tpda_swao_out_funnel_swao>; + }; + }; + }; + }; + + tpda_swao: tpda@6b01000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6b01000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-swao"; + + qcom,tpda-atid = <71>; + qcom,dsb-elem-size = <1 32>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_swao_out_funnel_swao: endpoint { + remote-endpoint = + <&funnel_swao_in_tpda_swao>; + }; + + }; + + port@1 { + reg = <0>; + tpda_swao_in_tpdm_swao0: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_swao0_out_tpda_swao>; + }; + }; + + port@2 { + reg = <1>; + tpda_swao_in_tpdm_swao1: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_swao1_out_tpda_swao>; + }; + + }; + }; + }; + + tpdm_swao0: tpdm@6b02000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + + reg = <0x6b02000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_swao0_out_tpda_swao: endpoint { + remote-endpoint = <&tpda_swao_in_tpdm_swao0>; + }; + }; + }; + + tpdm_swao1: tpdm@6b03000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6b03000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name="coresight-tpdm-swao-1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_swao1_out_tpda_swao: endpoint { + remote-endpoint = <&tpda_swao_in_tpdm_swao1>; + }; + }; + }; + + funnel_in2: funnel@6043000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6043000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in2_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in2>; + }; + }; + + port@1 { + reg = <2>; + funnel_in2_in_funnel_apss_merg: endpoint { + slave-mode; + remote-endpoint = + <&funnel_apss_merg_out_funnel_in2>; + }; + }; + }; + }; + + funnel_apss_merg: funnel@7810000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x7810000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss-merg"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss_merg_out_funnel_in2: endpoint { + remote-endpoint = + <&funnel_in2_in_funnel_apss_merg>; + }; + }; + + port@1 { + reg = <0>; + funnel_apss_merg_in_funnel_apss: endpoint { + slave-mode; + remote-endpoint = + <&funnel_apss_out_funnel_apss_merg>; + }; + }; + + port@2 { + reg = <2>; + funnel_apss_merg_in_tpda_olc: endpoint { + slave-mode; + remote-endpoint = + <&tpda_olc_out_funnel_apss_merg>; + }; + }; + + port@3 { + reg = <3>; + funnel_apss_merg_in_tpda_llm_silver: endpoint { + slave-mode; + remote-endpoint = + <&tpda_llm_silver_out_funnel_apss_merg>; + }; + }; + + port@4 { + reg = <4>; + funnel_apss_merg_in_tpda_llm_gold: endpoint { + slave-mode; + remote-endpoint = + <&tpda_llm_gold_out_funnel_apss_merg>; + }; + }; + + port@5 { + reg = <5>; + funnel_apss_merg_in_tpda_apss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_apss_out_funnel_apss_merg>; + }; + }; + }; + }; + + tpda_olc: tpda@7832000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x7832000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-olc"; + + qcom,tpda-atid = <69>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_olc_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_tpda_olc>; + }; + }; + port@1 { + reg = <0>; + tpda_olc_in_tpdm_olc: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_olc_out_tpda_olc>; + }; + }; + }; + }; + + tpdm_olc: tpdm@7830000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x7830000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-olc"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port{ + tpdm_olc_out_tpda_olc: endpoint { + remote-endpoint = <&tpda_olc_in_tpdm_olc>; + }; + }; + }; + + tpda_apss: tpda@7862000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x7862000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-apss"; + + qcom,tpda-atid = <66>; + qcom,dsb-elem-size = <0 32>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_apss_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_tpda_apss>; + }; + }; + + port@1 { + reg = <0>; + tpda_apss_in_tpdm_apss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_apss_out_tpda_apss>; + }; + }; + }; + }; + + tpdm_apss: tpdm@7860000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x7860000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-apss"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_apss_out_tpda_apss: endpoint { + remote-endpoint = <&tpda_apss_in_tpdm_apss>; + }; + }; + }; + + tpda_llm_silver: tpda@78c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x78c0000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-llm-silver"; + + qcom,tpda-atid = <72>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_llm_silver_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_tpda_llm_silver>; + }; + }; + + port@1 { + reg = <0>; + tpda_llm_silver_in_tpdm_llm_silver: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_llm_silver_out_tpda_llm_silver>; + }; + }; + }; + }; + + tpdm_llm_silver: tpdm@78a0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x78a0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-llm-silver"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_llm_silver_out_tpda_llm_silver: endpoint { + remote-endpoint = + <&tpda_llm_silver_in_tpdm_llm_silver>; + }; + }; + }; + + tpda_llm_gold: tpda@78d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x78d0000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-llm-gold"; + + qcom,tpda-atid = <73>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_llm_gold_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_tpda_llm_gold>; + }; + }; + + port@1 { + reg = <0>; + tpda_llm_gold_in_tpdm_llm_gold: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_llm_gold_out_tpda_llm_gold>; + }; + }; + }; + }; + + tpdm_llm_gold: tpdm@78b0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x78b0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-llm-gold"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_llm_gold_out_tpda_llm_gold: endpoint { + remote-endpoint = + <&tpda_llm_gold_in_tpdm_llm_gold>; + }; + }; + }; + funnel_apss: funnel@7800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x7800000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_funnel_apss>; + }; + }; + port@1 { + reg = <0>; + funnel_apss_in_etm0: endpoint { + slave-mode; + remote-endpoint = + <&etm0_out_funnel_apss>; + }; + }; + + port@2 { + reg = <1>; + funnel_apss_in_etm1: endpoint { + slave-mode; + remote-endpoint = + <&etm1_out_funnel_apss>; + }; + }; + + port@3 { + reg = <2>; + funnel_apss_in_etm2: endpoint { + slave-mode; + remote-endpoint = + <&etm2_out_funnel_apss>; + }; + }; + + port@4 { + reg = <3>; + funnel_apss_in_etm3: endpoint { + slave-mode; + remote-endpoint = + <&etm3_out_funnel_apss>; + }; + }; + + port@5 { + reg = <4>; + funnel_apss_in_etm4: endpoint { + slave-mode; + remote-endpoint = + <&etm4_out_funnel_apss>; + }; + }; + + port@6 { + reg = <5>; + funnel_apss_in_etm5: endpoint { + slave-mode; + remote-endpoint = + <&etm5_out_funnel_apss>; + }; + }; + + port@7 { + reg = <6>; + funnel_apss_in_etm6: endpoint { + slave-mode; + remote-endpoint = + <&etm6_out_funnel_apss>; + }; + }; + + port@8 { + reg = <7>; + funnel_apss_in_etm7: endpoint { + slave-mode; + remote-endpoint = + <&etm7_out_funnel_apss>; + }; + }; + }; + }; + + etm0: etm@7040000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7040000 0x1000>; + cpu = <&CPU0>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm0_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm0>; + }; + }; + }; + + etm1: etm@7140000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7140000 0x1000>; + cpu = <&CPU1>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm1_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm1>; + }; + }; + }; + + etm2: etm@7240000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7240000 0x1000>; + cpu = <&CPU2>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm2_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm2>; + }; + }; + }; + + etm3: etm@7340000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7340000 0x1000>; + cpu = <&CPU3>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm3"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm3_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm3>; + }; + }; + }; + + etm4: etm@7440000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7440000 0x1000>; + cpu = <&CPU4>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm4"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm4_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm4>; + }; + }; + }; + + etm5: etm@7540000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7540000 0x1000>; + cpu = <&CPU5>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm5"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm5_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm5>; + }; + }; + }; + + etm6: etm@7640000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7640000 0x1000>; + cpu = <&CPU6>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm6"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm6_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm6>; + }; + }; + }; + + etm7: etm@7740000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7740000 0x1000>; + cpu = <&CPU7>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm7"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm7_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm7>; + }; + }; + }; + + stm: stm@6002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b962>; + + reg = <0x6002000 0x1000>, + <0x16280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + coresight-name = "coresight-stm"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + stm_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_stm>; + }; + }; + + }; + + funnel_qatb: funnel@6005000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6005000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-qatb"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_qatb_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_qatb>; + }; + }; + + port@1 { + reg = <0>; + funnel_qatb_in_tpda: endpoint { + slave-mode; + remote-endpoint = + <&tpda_out_funnel_qatb>; + }; + }; + + port@2 { + reg = <3>; + funnel_qatb_in_funnel_dl_south_1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_dl_south_1_out_funnel_qatb>; + }; + }; + + port@3 { + reg = <5>; + funnel_qatb_in_funnel_turing_1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_turing_1_out_funnel_qatb>; + }; + }; + }; + }; + + funnel_dl_south_1: funnel_1@6b53000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6b58000 0x10>, + <0x6b53000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dl-south-1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl_south_1_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_funnel_dl_south_1>; + }; + }; + + port@1 { + reg = <2>; + funnel_dl_south_1_in_tpdm_wcss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_wcss_out_funnel_dl_south_1>; + }; + }; + }; + }; + + tpdm_lpass: dummy_source { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-tpdm-lpass"; + qcom,dummy-source; + + port { + tpdm_lpass_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_tpdm_lpass>; + }; + }; + }; + + tpdm_wcss: tpdm@699c000 { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-tpdm-wcss"; + qcom,dummy-source; + + port { + tpdm_wcss_out_funnel_dl_south_1: endpoint { + remote-endpoint = + <&funnel_dl_south_1_in_tpdm_wcss>; + }; + }; + }; + + tpda: tpda@6004000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6004000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda"; + + qcom,tpda-atid = <65>; + qcom,bc-elem-size = <10 32>, + <13 32>; + qcom,tc-elem-size = <13 32>; + qcom,dsb-elem-size = <0 32>, + <2 32>, + <3 32>, + <5 32>, + <6 32>, + <10 32>, + <11 32>, + <13 32>; + qcom,cmb-elem-size = <3 64>, + <7 64>, + <13 64>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_tpda>; + }; + + }; + + port@1 { + reg = <1>; + tpda_in_funnel_dl_mm: endpoint { + slave-mode; + remote-endpoint = + <&funnel_dl_mm_out_tpda>; + }; + }; + + port@2 { + reg = <2>; + tpda_in_tpdm_dl_center: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dl_center_out_tpda>; + }; + }; + + + port@3 { + reg = <3>; + tpda_in_funnel_dl_south: endpoint { + slave-mode; + remote-endpoint = + <&funnel_dl_south_out_tpda>; + }; + }; + + port@4 { + reg = <5>; + tpda_in_funnel_turing: endpoint { + slave-mode; + remote-endpoint = + <&funnel_turing_out_tpda>; + }; + }; + + port@5 { + reg = <6>; + tpda_in_funnel_ddr_0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_ddr_0_out_tpda>; + }; + }; + + port@6 { + reg = <7>; + tpda_in_funnel_gfx: endpoint { + slave-mode; + remote-endpoint = + <&funnel_gfx_out_tpda>; + }; + }; + + port@7 { + reg = <8>; + tpda_in_tpdm_vsense: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_vsense_out_tpda>; + }; + }; + + port@8 { + reg = <10>; + tpda_in_tpdm_prng: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_prng_out_tpda>; + }; + }; + + port@9 { + reg = <11>; + tpda_in_tpdm_north: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_north_out_tpda>; + }; + }; + + port@10 { + reg = <12>; + tpda_in_tpdm_qm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_qm_out_tpda>; + }; + }; + + port@11 { + reg = <13>; + tpda_in_tpdm_pimem: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_pimem_out_tpda>; + }; + }; + + port@12 { + reg = <14>; + tpda_in_tpdm_npu: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_npu_out_tpda>; + }; + }; + + port@13 { + reg = <15>; + tpda_in_tpdm_center: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_center_out_tpda>; + }; + }; + + port@14 { + reg = <17>; + tpda_in_tpdm_qdss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_qdss_out_tpda>; + }; + }; + }; + }; + + tpdm_qdss: tpdm@6006000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6006000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-qdss"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_qdss_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_tpdm_qdss>; + }; + }; + }; + + funnel_dl_mm: funnel@69C3000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x69C3000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dl-mm"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl_mm_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_funnel_dl_mm>; + }; + }; + + port@1 { + reg = <0>; + funnel_dl_mm_in_tpdm_dl_mm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dl_mm_out_funnel_dl_mm>; + }; + }; + }; + }; + + tpdm_dl_mm: tpdm@69c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x69c0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dl-mm"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_dl_mm_out_funnel_dl_mm: endpoint { + remote-endpoint = + <&funnel_dl_mm_in_tpdm_dl_mm>; + }; + }; + }; + + tpdm_dl_center: tpdm@6c28000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6c28000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dl-center"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_dl_center_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_dl_center>; + }; + }; + }; + + funnel_dl_south: funnel@6b53000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + reg = <0x6b53000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dl-south"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_dl_south_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_funnel_dl_south>; + }; + }; + + port@1 { + reg = <0>; + funnel_dl_south_in_tpdm_dl_south: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dl_south_out_funnel_dl_south>; + }; + }; + }; + }; + + tpdm_dl_south: tpdm@6b52000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6b52000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dl-south"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_dl_south_out_funnel_dl_south: endpoint { + remote-endpoint = + <&funnel_dl_south_in_tpdm_dl_south>; + }; + }; + }; + + funnel_turing: funnel@6861000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6861000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-turing"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_turing_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_funnel_turing>; + }; + }; + + port@1 { + reg = <0>; + funnel_turing_in_tpdm_turing: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_turing_out_funnel_turing>; + }; + }; + }; + }; + + funnel_turing1: funnel_1@6861000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6867010 0x10>, + <0x6861000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + + coresight-name = "coresight-funnel-turing1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + qcom,duplicate-funnel; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_turing_1_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_funnel_turing_1>; + }; + }; + + port@1 { + reg = <1>; + funnel_turing_1_in_turing_etm0: endpoint { + slave-mode; + remote-endpoint = + <&turing_etm0_out_funnel_turing_1>; + }; + }; + }; + }; + + turing_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-turing-etm0"; + qcom,inst-id = <13>; + + port{ + turing_etm0_out_funnel_turing_1: endpoint { + remote-endpoint = + <&funnel_turing_1_in_turing_etm0>; + }; + }; + }; + + tpdm_turing: tpdm@6860000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6860000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-turing"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_turing_out_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_in_tpdm_turing>; + }; + }; + }; + + funnel_ddr_0: funnel@6a05000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6a05000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-ddr-0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ddr_0_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_funnel_ddr_0>; + }; + }; + + port@1 { + reg = <0>; + funnel_ddr_0_in_tpdm_ddr: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_ddr_out_funnel_ddr_0>; + }; + }; + }; + }; + + tpdm_ddr: tpdm@6a00000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x06a00000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_ddr_out_funnel_ddr_0: endpoint { + remote-endpoint = <&funnel_ddr_0_in_tpdm_ddr>; + }; + }; + }; + + funnel_gfx: funnel@6943000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6943000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-gfx"; + + clocks = <&clock_aop QDSS_CLK>, + <&clock_gpucc GPU_CC_CX_APB_CLK>; + clock-names = "apb_pclk", "gpu_apb_clk"; + qcom,proxy-clks = "gpu_apb_clk"; + + status = "disabled"; + /* GDSC regulator names */ + regulator-names = "vddcx", "vdd"; + /* GDSC oxili regulators */ + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + qcom,proxy-regs = "vddcx", "vdd"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_gfx_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_funnel_gfx>; + }; + }; + + port@1 { + reg = <0>; + funnel_gfx_in_tpdm_gfx: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_gfx_out_funnel_gfx>; + }; + }; + }; + }; + + tpdm_gfx: tpdm@6940000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6940000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-gpu"; + + clocks = <&clock_aop QDSS_CLK>, + <&clock_gpucc GPU_CC_CX_APB_CLK>; + clock-names = "apb_pclk", "gpu_apb_clk"; + qcom,tpdm-clks = "gpu_apb_clk"; + + status = "disabled"; + /* GDSC regulator names */ + regulator-names = "vddcx", "vdd"; + /* GDSC oxili regulators */ + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + qcom,tpdm-regs = "vddcx", "vdd"; + + qcom,msr-fix-req; + + port { + tpdm_gfx_out_funnel_gfx: endpoint { + remote-endpoint = <&funnel_gfx_in_tpdm_gfx>; + }; + }; + }; + + tpdm_vsense: tpdm@6840000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6840000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-vsense"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port{ + tpdm_vsense_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_vsense>; + }; + }; + }; + + tpdm_prng: tpdm@684c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x684c000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-prng"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_prng_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_prng>; + }; + }; + }; + + tpdm_north: tpdm@6b48000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6b48000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-north"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_north_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_north>; + }; + }; + }; + + tpdm_qm: tpdm@69d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x69d0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-qm"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_qm_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_qm>; + }; + }; + }; + + + tpdm_pimem: tpdm@6850000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6850000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-pimem"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_pimem_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_pimem>; + }; + }; + }; + + tpdm_center: tpdm@6b44000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6b44000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-center"; + + qcom,msr-fix-req; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_center_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_center>; + }; + }; + }; + + hwevent: hwevent@0x014066f0 { + compatible = "qcom,coresight-hwevent"; + reg = <0x14066f0 0x4>, + <0x14166f0 0x4>, + <0x1406038 0x4>, + <0x1416038 0x4>; + reg-names = "ddr-ch0-cfg", "ddr-ch23-cfg", "ddr-ch0-ctrl", + "ddr-ch23-ctrl"; + + coresight-csr = <&csr>; + coresight-name = "coresight-hwevent"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_apss: cti@78e0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x78e0000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss_cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_apss: cti@78f0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x78f0000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss_cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti2_apss: cti@7900000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7900000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss_cti2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_ddr0: cti@6a02000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6a02000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_0_cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_ddr0: cti@6a03000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6a03000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_0_cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_ddr1: cti@6a10000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6a10000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_1_cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_ddr1: cti@6a11000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6a11000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_1_cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti2_ddr1: cti@6a12000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6a12000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_1_cti2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_dlmm: cti@69C1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x69C1000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlmm_cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_dlmm: cti@69C2000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x69C2000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlmm_cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_dlct: cti@6c29000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6c29000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct_cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_dlct: cti@6c2a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6c2a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct_cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_wcss: cti@69a4000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x69a4000 0x1000>; + reg-names = "cti-base"; + + status = "disabled"; + coresight-name = "coresight-cti-wcss_cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_wcss: cti@69a5000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x69a5000 0x1000>; + reg-names = "cti-base"; + + status = "disabled"; + coresight-name = "coresight-cti-wcss_cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti2_wcss: cti@69a6000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x69a6000 0x1000>; + reg-names = "cti-base"; + + status = "disabled"; + coresight-name = "coresight-cti-wcss_cti2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_mss_q6: cti@683b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x683b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-mss-q6"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_turing: cti@6867000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6867000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-turing"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_swao: cti@6b04000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b04000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_swao: cti@6b05000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b05000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti2_swao: cti@6b06000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b06000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti3_swao: cti@6b07000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b07000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti3"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_aop_m3: cti@6b21000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b21000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-aop-m3"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_titan: cti@6c13000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6c13000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-titan"; + + status = "disabled"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_venus_arm9: cti@6c20000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6c20000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-venus-arm9"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0: cti@6010000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6010000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti1: cti@6011000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6011000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti2: cti@6012000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6012000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti3: cti@6013000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6013000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti3"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti4: cti@6014000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6014000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti4"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti5: cti@6015000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6015000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti5"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti6: cti@6016000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6016000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti6"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti7: cti@6017000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6017000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti7"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti8: cti@6018000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6018000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti8"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti9: cti@6019000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6019000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti9"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti10: cti@601a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti10"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti11: cti@601b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti11"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti12: cti@601c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti12"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti13: cti@601d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601d000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti13"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti14: cti@601e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601e000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti14"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti15: cti@601f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601f000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti15"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + ipcb_tgu: tgu@6b0c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b999>; + reg = <0x06b0c000 0x1000>; + reg-names = "tgu-base"; + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <4>; + tgu-timer-counters = <8>; + + coresight-name = "coresight-tgu-ipcb"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + tpdm_npu: tpdm@69e1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x69e1000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-npu"; + + clocks = <&clock_aop QDSS_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_APB_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_CLK_SRC>, + <&clock_npucc NPU_CC_NPU_CORE_CTI_CLK>; + + clock-names = "apb_pclk", + "npu_core_apb_clk", + "npu_core_atb_clk", + "npu_core_clk", + "npu_core_clk_src", + "npu_core_cti_clk"; + + qcom,tpdm-clks = "npu_core_apb_clk", + "npu_core_atb_clk", + "npu_core_clk", + "npu_core_clk_src", + "npu_core_cti_clk"; + + vdd-supply = <&npu_core_gdsc>; + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,tpdm-regs = "vdd", "vdd_cx"; + + port{ + tpdm_npu_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_npu>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-dual-display-idp-overlay.dts b/arch/arm/boot/dts/qcom/sdmmagpie-dual-display-idp-overlay.dts new file mode 100644 index 000000000000..ac5362f001d0 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-dual-display-idp-overlay.dts @@ -0,0 +1,40 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "sdmmagpie-idp.dtsi" +#include "sdmmagpie-audio-overlay.dtsi" + +/ { + model = "Dual Display IDP"; + compatible = "qcom,sdmmagpie-idp", "qcom,sdmmagpie", "qcom,idp"; + qcom,msm-id = <365 0x0>; + qcom,board-id = <34 3>; +}; + +&dsi_sw43404_amoled_fhd_plus_cmd_display { + qcom,dsi-display-active; +}; + +&dsi_nt35695b_truly_fhd_cmd_sec_display { + qcom,dsi-display-active; +}; + +&mdss_mdp { + qcom,sde-mixer-display-pref = "primary", "none", "none", + "none", "none", "none"; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-dual-display-idp.dts b/arch/arm/boot/dts/qcom/sdmmagpie-dual-display-idp.dts new file mode 100644 index 000000000000..846be99eec0f --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-dual-display-idp.dts @@ -0,0 +1,35 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdmmagpie.dtsi" +#include "sdmmagpie-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDMMAGPIE PM6150 Dual Display IDP"; + compatible = "qcom,sdmmagpie-idp", "qcom,sdmmagpie", "qcom,idp"; + qcom,board-id = <34 3>; +}; + +&dsi_sw43404_amoled_fhd_plus_cmd_display { + qcom,dsi-display-active; +}; + +&dsi_nt35695b_truly_fhd_cmd_sec_display { + qcom,dsi-display-active; +}; + +&mdss_mdp { + qcom,sde-mixer-display-pref = "primary", "none", "none", + "none", "none", "none"; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-ext-codec-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-ext-codec-audio-overlay.dtsi new file mode 100644 index 000000000000..a237f441b527 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-ext-codec-audio-overlay.dtsi @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm6150-ext-codec-audio-overlay.dtsi" + +&wcd9xxx_intc { + qcom,gpio-connect = <&tlmm 58 0>; +}; + +&qupv3_se4_spi { + status = "disabled"; +}; + +&qupv3_se0_spi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-external-codec-idp-overlay.dts b/arch/arm/boot/dts/qcom/sdmmagpie-external-codec-idp-overlay.dts new file mode 100644 index 000000000000..1df5e2506c85 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-external-codec-idp-overlay.dts @@ -0,0 +1,28 @@ + +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include + +#include "sdmmagpie-idp.dtsi" +#include "sdmmagpie-ext-codec-audio-overlay.dtsi" +#include "sdmmagpie-external-codec.dtsi" + +/ { + model = "External Audio Codec IDP"; + compatible = "qcom,sdmmagpie-idp", "qcom,sdmmagpie", "qcom,idp"; + qcom,msm-id = <365 0x0>; + qcom,board-id = <34 1>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-external-codec-idp.dts b/arch/arm/boot/dts/qcom/sdmmagpie-external-codec-idp.dts new file mode 100644 index 000000000000..19ee94ec96ff --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-external-codec-idp.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdmmagpie.dtsi" +#include "sdmmagpie-idp.dtsi" +#include "sdmmagpie-ext-codec-audio-overlay.dtsi" +#include "sdmmagpie-external-codec.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDMMAGPIE PM6150 External Audio Codec IDP"; + compatible = "qcom,sdmmagpie-idp", "qcom,sdmmagpie", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-external-codec.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-external-codec.dtsi new file mode 100644 index 000000000000..36216dbfd3fb --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-external-codec.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm6150-external-codec.dtsi" diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-gdsc.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-gdsc.dtsi new file mode 100644 index 000000000000..2f816b374520 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-gdsc.dtsi @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + /* GDSCs in Global CC */ + pcie_0_gdsc: qcom,gdsc@16b004 { + compatible = "qcom,gdsc"; + regulator-name = "pcie_0_gdsc"; + reg = <0x16b004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + ufs_phy_gdsc: qcom,gdsc@177004 { + compatible = "qcom,gdsc"; + regulator-name = "ufs_phy_gdsc"; + reg = <0x177004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + usb30_prim_gdsc: qcom,gdsc@10f004 { + compatible = "qcom,gdsc"; + regulator-name = "usb30_prim_gdsc"; + reg = <0x10f004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc: qcom,gdsc@17d030 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc"; + reg = <0x17d030 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc: qcom,gdsc@17d03c { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc"; + reg = <0x17d03c 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_tbu1_gdsc: qcom,gdsc@17d034 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc"; + reg = <0x17d034 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_tbu2_gdsc: qcom,gdsc@17d038 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc"; + reg = <0x17d038 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d040 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; + reg = <0x17d040 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d048 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc"; + reg = <0x17d048 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@17d044 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc"; + reg = <0x17d044 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + /* GDSCs in Camera CC */ + bps_gdsc: qcom,gdsc@ad07004 { + compatible = "qcom,gdsc"; + regulator-name = "bps_gdsc"; + reg = <0xad07004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + ife_0_gdsc: qcom,gdsc@ad0a004 { + compatible = "qcom,gdsc"; + regulator-name = "ife_0_gdsc"; + reg = <0xad0a004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + ife_1_gdsc: qcom,gdsc@ad0b004 { + compatible = "qcom,gdsc"; + regulator-name = "ife_1_gdsc"; + reg = <0xad0b004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + ipe_0_gdsc: qcom,gdsc@ad08004 { + compatible = "qcom,gdsc"; + regulator-name = "ipe_0_gdsc"; + reg = <0xad08004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + ipe_1_gdsc: qcom,gdsc@ad09004 { + compatible = "qcom,gdsc"; + regulator-name = "ipe_1_gdsc"; + reg = <0xad09004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + titan_top_gdsc: qcom,gdsc@ad0c1c4 { + compatible = "qcom,gdsc"; + regulator-name = "titan_top_gdsc"; + reg = <0xad0c1c4 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + /* GDSCs in Display CC */ + mdss_core_gdsc: qcom,gdsc@0f03000 { + compatible = "qcom,gdsc"; + regulator-name = "mdss_core_gdsc"; + reg = <0xaf03000 0x4>; + qcom,poll-cfg-gdscr; + qcom,support-hw-trigger; + status = "disabled"; + proxy-supply = <&mdss_core_gdsc>; + qcom,proxy-consumer-enable; + }; + + /* GDSCs in Graphics CC */ + gpu_cx_hw_ctrl: syscon@5091540 { + compatible = "syscon"; + reg = <0x5091540 0x4>; + }; + + gpu_gx_domain_addr: syscon@0x5091508 { + compatible = "syscon"; + reg = <0x5091508 0x4>; + }; + + gpu_gx_sw_reset: syscon@0x5091008 { + compatible = "syscon"; + reg = <0x5091008 0x4>; + }; + + gpu_cx_gdsc: qcom,gdsc@509106c { + compatible = "qcom,gdsc"; + regulator-name = "gpu_cx_gdsc"; + reg = <0x509106c 0x4>; + hw-ctrl-addr = <&gpu_cx_hw_ctrl>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + qcom,clk-dis-wait-val = <8>; + status = "disabled"; + }; + + gpu_gx_gdsc: qcom,gdsc@509100c { + compatible = "qcom,gdsc"; + regulator-name = "gpu_gx_gdsc"; + reg = <0x509100c 0x4>; + qcom,poll-cfg-gdscr; + domain-addr = <&gpu_gx_domain_addr>; + sw-reset = <&gpu_gx_sw_reset>; + status = "disabled"; + }; + + /* GDSCs in Video CC */ + mvsc_gdsc: qcom,gdsc@0b00814 { + compatible = "qcom,gdsc"; + regulator-name = "mvsc_gdsc"; + reg = <0xab00814 0x4>; + status = "disabled"; + }; + + mvs0_gdsc: qcom,gdsc@ab00874 { + compatible = "qcom,gdsc"; + regulator-name = "mvs0_gdsc"; + reg = <0xab00874 0x4>; + status = "disabled"; + }; + + mvs1_gdsc: qcom,gdsc@ab008b4 { + compatible = "qcom,gdsc"; + regulator-name = "mvs1_gdsc"; + reg = <0xab008b4 0x4>; + status = "disabled"; + }; + + /* GDSCs in NPU CC */ + npu_core_gdsc: qcom,gdsc@9911028 { + compatible = "qcom,gdsc"; + regulator-name = "npu_core_gdsc"; + reg = <0x9911028 0x4>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-gpu.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-gpu.dtsi new file mode 100644 index 000000000000..1105923f9c36 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-gpu.dtsi @@ -0,0 +1,608 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + pil_gpu: qcom,kgsl-hyp { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <13>; + qcom,firmware-name = "a615_zap"; + }; + + msm_bus: qcom,kgsl-busmon{ + label = "kgsl-busmon"; + compatible = "qcom,kgsl-busmon"; + }; + + gpu_bw_tbl: gpu-bw-tbl { + compatible = "operating-points-v2"; + opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */ + opp-100 { opp-hz = /bits/ 64 < 381 >; }; /* 1.DDR:100 MHz */ + opp-200 { opp-hz = /bits/ 64 < 762 >; }; /* 2.DDR:200 MHz */ + opp-300 { opp-hz = /bits/ 64 < 1144 >; }; /* 3.DDR:300 MHz */ + opp-451 { opp-hz = /bits/ 64 < 1720 >; }; /* 4.DDR:451 MHz */ + opp-547 { opp-hz = /bits/ 64 < 2086 >; }; /* 5.DDR:547 MHz */ + opp-681 { opp-hz = /bits/ 64 < 2597 >; }; /* 6.DDR:681 MHz */ + opp-825 { opp-hz = /bits/ 64 < 3147 >; }; /* 7.DDR:825 MHz */ + opp-1017 { opp-hz = /bits/ 64 < 3879 >; }; /* 8.DDR:1017 MHz */ + opp-1353 { opp-hz = /bits/ 64 < 5161 >; }; /* 9.DDR:1353 MHz */ + opp-1555 { opp-hz = /bits/ 64 < 5931 >; }; /* 10.DDR:1555 MHz */ + opp-1804 { opp-hz = /bits/ 64 < 6881 >; }; /* 11.DDR:1804 MHz */ + }; + + gpubw: qcom,gpubw { + compatible = "qcom,devbw"; + governor = "bw_vbif"; + qcom,src-dst-ports = <26 512>; + operating-points-v2 = <&gpu_bw_tbl>; + }; + + msm_gpu: qcom,kgsl-3d0@5000000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; + status = "ok"; + reg = <0x5000000 0x40000>, + <0x5061000 0x800>, + <0x509e000 0x1000>, + <0x780000 0x6300>; + reg-names = "kgsl_3d0_reg_memory", + "cx_dbgc", "cx_misc", + "qfprom_memory"; + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + qcom,id = <0>; + + qcom,chipid = <0x06010800>; + + qcom,gpu-quirk-hfi-use-reg; + qcom,gpu-quirk-secvid-set-once; + + /* */ + qcom,idle-timeout = <80>; + qcom,no-nap; + + qcom,highest-bank-bit = <14>; + + qcom,min-access-length = <32>; + + qcom,ubwc-mode = <2>; + + /* size in bytes */ + qcom,snapshot-size = <1048576>; + + /* base addr, size */ + qcom,gpu-qdss-stm = <0x161c0000 0x40000>; + #cooling-cells = <2>; + + clocks = <&clock_gpucc GPU_CC_GX_GFX3D_CLK>, + <&clock_gpucc GPU_CC_CXO_CLK>, + <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gpucc GPU_CC_CX_GMU_CLK>; + + clock-names = "core_clk", "rbbmtimer_clk", "mem_clk", + "mem_iface_clk", "gmu_clk"; + + /* Bus Scale Settings */ + qcom,gpubw-dev = <&gpubw>; + qcom,bus-control; + qcom,msm-bus,name = "grp3d"; + qcom,bus-width = <32>; + qcom,msm-bus,num-cases = <12>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, + <26 512 0 400000>, /* 1 bus=100 */ + <26 512 0 800000>, /* 2 bus=200 */ + <26 512 0 1200000>, /* 3 bus=300 */ + <26 512 0 1804000>, /* 4 bus=451 */ + <26 512 0 2188000>, /* 5 bus=547 */ + <26 512 0 2724000>, /* 6 bus=681 */ + <26 512 0 3300000>, /* 7 bus=825 */ + <26 512 0 4068000>, /* 8 bus=1017 */ + <26 512 0 5412000>, /* 9 bus=1353 */ + <26 512 0 6220000>, /* 10 bus=1555 */ + <26 512 0 7216000>; /* 11 bus=1804 */ + + /* GDSC regulator names */ + regulator-names = "vddcx", "vdd"; + /* GDSC oxili regulators */ + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + + /* GPU related llc slices */ + cache-slice-names = "gpu", "gpuhtw"; + cache-slices = <&llcc 12>, <&llcc 11>; + + /* CPU latency parameter */ + qcom,pm-qos-active-latency = <67>; + qcom,pm-qos-wakeup-latency = <67>; + + /* Enable context aware freq. scaling */ + qcom,enable-ca-jump; + /* Context aware jump busy penalty in us */ + qcom,ca-busy-penalty = <12000>; + + qcom,gpu-speed-bin = <0x41a0 0x1fe00000 21>; + + /* GPU Mempools */ + qcom,gpu-mempools { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-allocate; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-allocate; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; + + /* + * Speed-bin zero is default speed bin. + * For rest of the speed bins, speed-bin value + * is calulated as FMAX/4.8 MHz round up to zero + * decimal places. + */ + qcom,gpu-pwrlevel-bins { + #address-cells = <1>; + #size-cells = <0>; + + compatible="qcom,gpu-pwrlevel-bins"; + + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <0>; + + qcom,initial-pwrlevel = <7>; + qcom,ca-target-pwrlevel = <5>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <825000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* TURBO */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <800000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <650000000>; + qcom,bus-freq = <10>; + qcom,bus-min = <8>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <565000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <430000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <355000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* LOW SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <267000000>; + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* LOW SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <180000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <4>; + }; + + /* XO */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <172>; + + qcom,initial-pwrlevel = <7>; + qcom,ca-target-pwrlevel = <5>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <825000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* TURBO */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <800000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <650000000>; + qcom,bus-freq = <10>; + qcom,bus-min = <8>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <565000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <430000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <355000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* LOW SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <267000000>; + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* LOW SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <180000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <4>; + }; + + /* XO */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <146>; + + qcom,initial-pwrlevel = <6>; + qcom,ca-target-pwrlevel = <4>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <700000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <650000000>; + qcom,bus-freq = <10>; + qcom,bus-min = <8>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <565000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <430000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <355000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* LOW SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <267000000>; + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* LOW SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <180000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <4>; + }; + + /* XO */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-3 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <128>; + + qcom,initial-pwrlevel = <5>; + qcom,ca-target-pwrlevel = <3>; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <610000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <565000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <430000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <10>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <355000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* LOW SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <267000000>; + qcom,bus-freq = <6>; + qcom,bus-min = <4>; + qcom,bus-max = <7>; + }; + + /* LOW SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <180000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <4>; + }; + + /* XO */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + }; + }; + + kgsl_msm_iommu: qcom,kgsl-iommu@5040000 { + compatible = "qcom,kgsl-smmu-v2"; + + reg = <0x05040000 0x10000>; + qcom,protect = <0x40000 0x10000>; + qcom,micro-mmu-control = <0x6000>; + + clocks = <&clock_gcc GCC_GPU_CFG_AHB_CLK>, + <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>; + + clock-names = "iface_clk", "mem_clk", "mem_iface_clk"; + + qcom,secure_align_mask = <0xfff>; + qcom,retention; + qcom,hyp_secure_alloc; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + label = "gfx3d_user"; + iommus = <&kgsl_smmu 0>; + qcom,gpu-offset = <0x48000>; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 2>; + }; + }; + + gmu: qcom,gmu@506a000 { + label = "kgsl-gmu"; + compatible = "qcom,gpu-gmu"; + + reg = <0x506a000 0x31000>, + <0xb290000 0x10000>, + <0xb490000 0x10000>; + reg-names = "kgsl_gmu_reg", + "kgsl_gmu_pdc_cfg", + "kgsl_gmu_pdc_seq"; + + interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>, + <0 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq"; + + qcom,msm-bus,name = "cnoc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 10036 0 0>, /* CNOC off */ + <26 10036 0 100>; /* CNOC on */ + + regulator-names = "vddcx", "vdd"; + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + + clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>, + <&clock_gpucc GPU_CC_CXO_CLK>, + <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>; + + clock-names = "gmu_clk", "cxo_clk", "axi_clk", + "memnoc_clk"; + + qcom,gmu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gmu-pwrlevels"; + + qcom,gmu-pwrlevel@0 { + reg = <0>; + qcom,gmu-freq = <0>; + }; + + qcom,gmu-pwrlevel@1 { + reg = <1>; + qcom,gmu-freq = <200000000>; + }; + }; + + gmu_user: gmu_user { + compatible = "qcom,smmu-gmu-user-cb"; + iommus = <&kgsl_smmu 4>; + }; + + gmu_kernel: gmu_kernel { + compatible = "qcom,smmu-gmu-kernel-cb"; + iommus = <&kgsl_smmu 5>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-idp-overlay.dts b/arch/arm/boot/dts/qcom/sdmmagpie-idp-overlay.dts new file mode 100644 index 000000000000..ec5e91ec0c33 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-idp-overlay.dts @@ -0,0 +1,31 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "sdmmagpie-idp.dtsi" +#include "sdmmagpie-audio-overlay.dtsi" + +/ { + model = "IDP"; + compatible = "qcom,sdmmagpie-idp", "qcom,sdmmagpie", "qcom,idp"; + qcom,msm-id = <365 0x0>; + qcom,board-id = <34 0>; +}; + +&dsi_sw43404_amoled_video_display { + qcom,dsi-display-active; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-idp.dts b/arch/arm/boot/dts/qcom/sdmmagpie-idp.dts new file mode 100644 index 000000000000..94fe65d40f09 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-idp.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdmmagpie.dtsi" +#include "sdmmagpie-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDMMAGPIE PM6150 IDP"; + compatible = "qcom,sdmmagpie-idp", "qcom,sdmmagpie", "qcom,idp"; + qcom,board-id = <34 0>; +}; + +&dsi_sw43404_amoled_video_display { + qcom,dsi-display-active; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-idp.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-idp.dtsi new file mode 100644 index 000000000000..5b7a01baa270 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-idp.dtsi @@ -0,0 +1,432 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "sdmmagpie-thermal-overlay.dtsi" + +#include +#include +#include +#include +#include "sdmmagpie-sde-display.dtsi" +#include "sdmmagpie-camera-sensor-idp.dtsi" + +&soc { + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + #include "qg-batterydata-mlp466076-3200mah.dtsi" + }; +}; + +&qupv3_se8_2uart { + status = "ok"; +}; + +&qupv3_se3_4uart { + status = "ok"; +}; + +&pm6150a_amoled { + status = "ok"; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v3"; + + vdda-phy-supply = <&pm6150_l4>; /* 0.88v */ + vdda-pll-supply = <&pm6150l_l3>; /* 1.2v */ + vdda-phy-max-microamp = <62900>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm6150_l19>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm6150_l12>; + vccq2-voltage-level = <1750000 1950000>; + vcc-max-microamp = <600000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm6150l_l3>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&qupv3_se2_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 37 0x00>; + qcom,nq-ven = <&tlmm 12 0x00>; + qcom,nq-firm = <&tlmm 36 0x00>; + qcom,nq-clkreq = <&tlmm 31 0x00>; + qcom,nq-esepwr = <&tlmm 94 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <37 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active + &nfc_clk_req_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend + &nfc_clk_req_suspend>; + }; +}; + +&sdhc_1 { + vdd-supply = <&pm6150_l19>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&pm6150_l12>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm6150l_l9>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&pm6150l_l6>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; + +&dsi_sw43404_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sw43404_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sw43404_amoled_fhd_plus_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_dual_sharp_wqhd_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; + qcom,platform-en-gpio = <&pm6150l_gpios 4 0>; + qcom,platform-bklight-en-gpio = <&pm6150l_gpios 5 0>; +}; + +&dsi_dual_sharp_wqhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; + qcom,platform-en-gpio = <&pm6150l_gpios 4 0>; + qcom,platform-bklight-en-gpio = <&pm6150l_gpios 5 0>; +}; + +&dsi_rm69298_truly_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_rm69298_truly_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_rm69299_visionox_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_nt35695b_truly_fhd_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 11 0>; + qcom,platform-sec-reset-gpio = <&pm6150l_gpios 11 0>; + qcom,platform-en-gpio = <&pm6150l_gpios 4 0>; + qcom,platform-bklight-en-gpio = <&pm6150l_gpios 5 0>; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 11 0>; + qcom,platform-sec-reset-gpio = <&pm6150l_gpios 11 0>; + qcom,platform-en-gpio = <&pm6150l_gpios 4 0>; + qcom,platform-bklight-en-gpio = <&pm6150l_gpios 5 0>; + qcom,platform-te-gpio = <&tlmm 11 0>; +}; + +&sde_dp { + qcom,dp-aux-switch = <&fsa4480>; +}; + +&qupv3_se7_i2c { + qcom,i2c-touch-active="st,fts"; + status = "ok"; + + st_fts@49 { + compatible = "st,fts"; + reg = <0x49>; + interrupt-parent = <&tlmm>; + interrupts = <9 0x2008>; + vdd-supply = <&pm6150_l10>; + avdd-supply = <&pm6150l_l7>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + st,irq-gpio = <&tlmm 9 0x2008>; + st,reset-gpio = <&tlmm 8 0x00>; + st,regulator_dvdd = "vdd"; + st,regulator_avdd = "avdd"; + st,x-flip; + st,y-flip; + }; + + synaptics_dsx@20 { + compatible = "synaptics,dsx-i2c"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <9 0x2008>; + vdd-supply = <&pm6150_l10>; + avdd-supply = <&pm6150l_l7>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + synaptics,pwr-reg-name = "avdd"; + synaptics,bus-reg-name = "vdd"; + synaptics,ub-i2c-addr = <0x20>; + synaptics,max-y-for-2d = <2159>; + synaptics,irq-gpio = <&tlmm 9 0x2008>; + synaptics,reset-gpio = <&tlmm 8 0x0>; + synaptics,irq-on-state = <0>; + synaptics,power-delay-ms = <200>; + synaptics,reset-delay-ms = <200>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + }; +}; + +&pm6150_qg { + qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <100>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; +}; + +&pm6150_charger { + io-channels = <&pm6150_vadc ADC_USB_IN_V_16>, + <&pm6150_vadc ADC_USB_IN_I>, + <&pm6150_vadc ADC_CHG_TEMP>, + <&pm6150_vadc ADC_DIE_TEMP>, + <&pm6150l_vadc ADC_AMUX_THM1_PU2>, + <&pm6150_vadc ADC_SBUx>, + <&pm6150_vadc ADC_VPH_PWR>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage"; + qcom,battery-data = <&mtp_batterydata>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,fcc-stepping-enable; + qcom,suspend-input-on-debug-batt; + qcom,sec-charger-config = <3>; + qcom,thermal-mitigation = <4200000 3500000 3000000 + 2500000 2000000 1500000 1000000 500000>; + dpdm-supply = <&qusb_phy0>; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; +}; + +&pm6150_gpios { + smb_stat { + smb_stat_default: smb_stat_default { + pins = "gpio3"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = <0>; + }; + }; +}; + +&qupv3_se9_i2c { + status = "ok"; + #include "smb1390.dtsi" + #include "smb1355.dtsi" +}; + +&smb1355 { + /delete-property/ interrupts; + interrupts = <0x0 0xc2 0x0 IRQ_TYPE_LEVEL_LOW>; + status = "ok"; +}; + +&smb1355_charger { + status = "ok"; +}; + +&smb1390 { + /delete-property/ interrupts; + interrupts = <0x0 0xc2 0x0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1390_charger { + compatible = "qcom,smb1390-charger-psy"; + io-channels = <&pm6150l_vadc ADC_AMUX_THM2>; + io-channel-names = "cp_die_temp"; + status = "ok"; +}; + +&pm6150l_gpios { + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio2"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm6150l_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + linux,can-disable; + debounce-interval = <15>; + gpio-key,wakeup; + }; + }; +}; + +&thermal_zones { + quiet-therm-step { + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-ion.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-ion.dtsi new file mode 100644 index 000000000000..053bf7caabc8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-ion.dtsi @@ -0,0 +1,62 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = <25>; + qcom,ion-heap-type = "SYSTEM"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = <27>; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@19 { /* QSEECOM TA HEAP */ + reg = <19>; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@13 { /* SPSS HEAP */ + reg = <13>; + memory-region = <&sp_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ + reg = <10>; + memory-region = <&secure_display_memory>; + qcom,ion-heap-type = "HYP_CMA"; + }; + + qcom,ion-heap@14 { /* SECURE CARVEOUT HEAP */ + reg = <14>; + qcom,ion-heap-type = "SECURE_CARVEOUT"; + cdsp { + memory-region = <&cdsp_sec_mem>; + token = <0x20000000>; + }; + }; + + qcom,ion-heap@9 { + reg = <9>; + qcom,ion-heap-type = "SYSTEM_SECURE"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-npu.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-npu.dtsi new file mode 100644 index 000000000000..f046593f5748 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-npu.dtsi @@ -0,0 +1,191 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + msm_npu: qcom,msm_npu@9800000 { + compatible = "qcom,msm-npu"; + reg = <0x9800000 0x40000>, + <0x9900000 0x10000>, + <0x9960200 0x600>, + <0x780000 0x7000>; + reg-names = "tcm", "core", "bwmon", "qfprom_physical"; + interrupts = , + , + ; + interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq"; + iommus = <&apps_smmu 0x1461 0x0>; + cache-slice-names = "npu"; + cache-slices = <&llcc 23>; + + clocks = <&clock_aop QDSS_CLK>, + <&clock_npucc NPU_CC_ARMWIC_CORE_CLK>, + <&clock_npucc NPU_CC_CAL_DP_CLK>, + <&clock_npucc NPU_CC_CAL_DP_CDC_CLK>, + <&clock_npucc NPU_CC_CONF_NOC_AHB_CLK>, + <&clock_npucc NPU_CC_COMP_NOC_AXI_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_CTI_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_APB_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>, + <&clock_npucc NPU_CC_NPU_CPC_CLK>, + <&clock_npucc NPU_CC_NPU_CPC_TIMER_CLK>, + <&clock_npucc NPU_CC_QTIMER_CORE_CLK>, + <&clock_npucc NPU_CC_SLEEP_CLK>, + <&clock_npucc NPU_CC_BWMON_CLK>, + <&clock_npucc NPU_CC_PERF_CNT_CLK>, + <&clock_npucc NPU_CC_BTO_CORE_CLK>, + <&clock_npucc NPU_CC_XO_CLK>; + clock-names = "qdss_clk", + "armwic_core_clk", + "cal_dp_clk", + "cal_dp_cdc_clk", + "conf_noc_ahb_clk", + "comp_noc_axi_clk", + "npu_core_clk", + "npu_core_cti_clk", + "npu_core_apb_clk", + "npu_core_atb_clk", + "npu_cpc_clk", + "npu_cpc_timer_clk", + "qtimer_core_clk", + "sleep_clk", + "bwmon_clk", + "perf_cnt_clk", + "bto_core_clk", + "xo_clk"; + vdd-supply = <&npu_core_gdsc>; + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,proxy-reg-names ="vdd", "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + mboxes = <&qmp_npu0 0>, <&qmp_npu1 0>; + mbox-names = "npu_low", "npu_high"; + #cooling-cells = <2>; + qcom,npubw-dev = <&npu_npu_ddr_bw>; + qcom,npu-cxlimit-enable; + qcom,npu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,npu-pwrlevels"; + initial-pwrlevel = <4>; + qcom,npu-pwrlevel@0 { + reg = <0>; + vreg = <1>; + clk-freq = <0 + 100000000 + 300000000 + 300000000 + 30000000 + 150000000 + 100000000 + 37500000 + 19200000 + 60000000 + 100000000 + 19200000 + 19200000 + 0 + 19200000 + 300000000 + 19200000 + 19200000>; + }; + qcom,npu-pwrlevel@1 { + reg = <1>; + vreg = <2>; + clk-freq = <0 + 150000000 + 400000000 + 400000000 + 37500000 + 200000000 + 150000000 + 75000000 + 19200000 + 120000000 + 150000000 + 19200000 + 19200000 + 0 + 19200000 + 400000000 + 19200000 + 19200000>; + }; + qcom,npu-pwrlevel@2 { + reg = <2>; + vreg = <3>; + clk-freq = <0 + 200000000 + 466500000 + 466500000 + 37500000 + 300000000 + 200000000 + 75000000 + 19200000 + 120000000 + 200000000 + 19200000 + 19200000 + 0 + 19200000 + 466500000 + 19200000 + 19200000>; + }; + qcom,npu-pwrlevel@3 { + reg = <3>; + vreg = <4>; + clk-freq = <0 + 300000000 + 600000000 + 600000000 + 75000000 + 403000000 + 300000000 + 150000000 + 19200000 + 240000000 + 300000000 + 19200000 + 19200000 + 0 + 19200000 + 600000000 + 19200000 + 19200000>; + }; + qcom,npu-pwrlevel@4 { + reg = <4>; + vreg = <6>; + clk-freq = <0 + 400000000 + 700000000 + 700000000 + 75000000 + 533000000 + 400000000 + 150000000 + 19200000 + 300000000 + 400000000 + 19200000 + 19200000 + 0 + 19200000 + 700000000 + 19200000 + 19200000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-pinctrl.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-pinctrl.dtsi new file mode 100644 index 000000000000..b2db82bb6abb --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-pinctrl.dtsi @@ -0,0 +1,1683 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tlmm: pinctrl@3400000 { + compatible = "qcom,sdmmagpie-pinctrl"; + reg = <0x03400000 0xdc2000>, <0x17c000f0 0x60>; + reg-names = "pinctrl", "spi_cfg"; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + ufs_dev_reset_assert: ufs_dev_reset_assert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * UFS_RESET driver strengths are having + * different values/steps compared to typical + * GPIO drive strengths. + * + * Following table clarifies: + * + * HDRV value | UFS_RESET | Typical GPIO + * (dec) | (mA) | (mA) + * 0 | 0.8 | 2 + * 1 | 1.55 | 4 + * 2 | 2.35 | 6 + * 3 | 3.1 | 8 + * 4 | 3.9 | 10 + * 5 | 4.65 | 12 + * 6 | 5.4 | 14 + * 7 | 6.15 | 16 + * + * POR value for UFS_RESET HDRV is 3 which means + * 3.1mA and we want to use that. Hence just + * specify 8mA to "drive-strength" binding and + * that should result into writing 3 to HDRV + * field. + */ + drive-strength = <8>; /* default: 3.1 mA */ + output-low; /* active low reset */ + }; + }; + + ufs_dev_reset_deassert: ufs_dev_reset_deassert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * default: 3.1 mA + * check comments under ufs_dev_reset_assert + */ + drive-strength = <8>; + output-high; /* active low reset */ + }; + }; + + /* QUPv3 South SE mappings */ + /* SE 0 pin mappings */ + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_active: qupv3_se0_i2c_active { + mux { + pins = "gpio49", "gpio50"; + function = "qup00"; + }; + + config { + pins = "gpio49", "gpio50"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio49", "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio49", "gpio50"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_active: qupv3_se0_spi_active { + mux { + pins = "gpio49", "gpio50", "gpio51", + "gpio52"; + function = "qup00"; + }; + + config { + pins = "gpio49", "gpio50", "gpio51", + "gpio52"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio49", "gpio50", "gpio51", + "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio49", "gpio50", "gpio51", + "gpio52"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 1 pin mappings */ + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_active: qupv3_se1_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "qup01"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_active: qupv3_se1_spi_active { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "qup01"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 2 pin mappings */ + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio34", "gpio35"; + function = "qup02"; + }; + + config { + pins = "gpio34", "gpio35"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio34", "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio34", "gpio35"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 37 NFC Read Interrupt */ + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 37 NFC Read Interrupt */ + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_active: nfc_enable_active { + /* active state */ + mux { + /* 12: Enable 36: Firmware */ + pins = "gpio12", "gpio36"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio36"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + /* sleep state */ + mux { + /* 12: Enable 36: Firmware */ + pins = "gpio12", "gpio36"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio36"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_clk_req_active: nfc_clk_req_active { + /* active state */ + mux { + /* GPIO 31: NFC CLOCK REQUEST */ + pins = "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio31"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_clk_req_suspend: nfc_clk_req_suspend { + /* sleep state */ + mux { + /* GPIO 31: NFC CLOCK REQUEST */ + pins = "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio31"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + + /* SE 3 pin mappings */ + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_active: qupv3_se3_i2c_active { + mux { + pins = "gpio38", "gpio39"; + function = "qup03"; + }; + + config { + pins = "gpio38", "gpio39"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio38", "gpio39"; + function = "gpio"; + }; + + config { + pins = "gpio38", "gpio39"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se3_4uart_pins: qupv3_se3_4uart_pins { + qupv3_se3_ctsrx: qupv3_se3_ctsrx { + mux { + pins = "gpio38", "gpio41"; + function = "qup03"; + }; + + config { + pins = "gpio38", "gpio41"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + qupv3_se3_rts: qupv3_se3_rts { + mux { + pins = "gpio39"; + function = "qup03"; + }; + + config { + pins = "gpio39"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se3_tx: qupv3_se3_tx { + mux { + pins = "gpio40"; + function = "qup03"; + }; + + config { + pins = "gpio40"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se3_spi_pins: qupv3_se3_spi_pins { + qupv3_se3_spi_active: qupv3_se3_spi_active { + mux { + pins = "gpio38", "gpio39", "gpio40", + "gpio41"; + function = "qup03"; + }; + + config { + pins = "gpio38", "gpio39", "gpio40", + "gpio41"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { + mux { + pins = "gpio38", "gpio39", "gpio40", + "gpio41"; + function = "gpio"; + }; + + config { + pins = "gpio38", "gpio39", "gpio40", + "gpio41"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + fpc_reset_int { + fpc_reset_low: reset_low { + mux { + pins = "gpio91"; + function = "gpio"; + }; + config { + pins = "gpio91"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + fpc_reset_high: reset_high { + mux { + pins = "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio91"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + fpc_int_low: int_low { + mux { + pins = "gpio90"; + function = "gpio"; + }; + config { + pins = "gpio90"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + }; + + + + /* SE 4 pin mappings */ + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_active: qupv3_se4_i2c_active { + mux { + pins = "gpio53", "gpio54"; + function = "qup04"; + }; + + config { + pins = "gpio53", "gpio54"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio53", "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio53", "gpio54"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se4_4uart_pins: qupv3_se4_4uart_pins { + qupv3_se4_ctsrx: qupv3_se4_ctsrx { + mux { + pins = "gpio53", "gpio56"; + function = "qup04"; + }; + + config { + pins = "gpio53", "gpio56"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + qupv3_se4_rts: qupv3_se4_rts { + mux { + pins = "gpio54"; + function = "qup04"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se4_tx: qupv3_se4_tx { + mux { + pins = "gpio55"; + function = "qup04"; + }; + + config { + pins = "gpio55"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se4_spi_pins: qupv3_se4_spi_pins { + qupv3_se4_spi_active: qupv3_se4_spi_active { + mux { + pins = "gpio53", "gpio54", "gpio55", + "gpio56"; + function = "qup04"; + }; + + config { + pins = "gpio53", "gpio54", "gpio55", + "gpio56"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { + mux { + pins = "gpio53", "gpio54", "gpio55", + "gpio56"; + function = "gpio"; + }; + + config { + pins = "gpio53", "gpio54", "gpio55", + "gpio56"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* QUPv3 North instances */ + /* SE 6 pin mappings */ + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_active: qupv3_se6_i2c_active { + mux { + pins = "gpio59", "gpio60"; + function = "qup10"; + }; + + config { + pins = "gpio59", "gpio60"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio59", "gpio60"; + function = "gpio"; + }; + + config { + pins = "gpio59", "gpio60"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_active: qupv3_se6_spi_active { + mux { + pins = "gpio59", "gpio60", "gpio61", + "gpio62"; + function = "qup10"; + }; + + config { + pins = "gpio59", "gpio60", "gpio61", + "gpio62"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio59", "gpio60", "gpio61", + "gpio62"; + function = "gpio"; + }; + + config { + pins = "gpio59", "gpio60", "gpio61", + "gpio62"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 7 pin mappings */ + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_active: qupv3_se7_i2c_active { + mux { + pins = "gpio6", "gpio7"; + function = "qup11"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se7_spi_pins: qupv3_se7_spi_pins { + qupv3_se7_spi_active: qupv3_se7_spi_active { + mux { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + function = "qup11"; + }; + + config { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_sleep: qupv3_se7_spi_sleep { + mux { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 8 pin mappings */ + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_active: qupv3_se8_i2c_active { + mux { + pins = "gpio42", "gpio43"; + function = "qup12"; + }; + + config { + pins = "gpio42", "gpio43"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio42", "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio42", "gpio43"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se8_2uart_pins: qupv3_se8_2uart_pins { + qupv3_se8_2uart_active: qupv3_se8_2uart_active { + mux { + pins = "gpio44", "gpio45"; + function = "qup12"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se8_2uart_sleep: qupv3_se8_2uart_sleep { + mux { + pins = "gpio44", "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio44", "gpio45"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se8_spi_pins: qupv3_se8_spi_pins { + qupv3_se8_spi_active: qupv3_se8_spi_active { + mux { + pins = "gpio42", "gpio43", "gpio44", + "gpio45"; + function = "qup12"; + }; + + config { + pins = "gpio42", "gpio43", "gpio44", + "gpio45"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { + mux { + pins = "gpio42", "gpio43", "gpio44", + "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio42", "gpio43", "gpio44", + "gpio45"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 9 pin mappings */ + qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { + qupv3_se9_i2c_active: qupv3_se9_i2c_active { + mux { + pins = "gpio46", "gpio47"; + function = "qup13"; + }; + + config { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { + mux { + pins = "gpio46", "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + /* SE 10 pin mappings */ + qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { + qupv3_se10_i2c_active: qupv3_se10_i2c_active { + mux { + pins = "gpio110", "gpio111"; + function = "qup14"; + }; + + config { + pins = "gpio110", "gpio111"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { + mux { + pins = "gpio110", "gpio111"; + function = "gpio"; + }; + + config { + pins = "gpio110", "gpio111"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se10_4uart_pins: qupv3_se10_4uart_pins { + qupv3_se10_ctsrx: qupv3_se10_ctsrx { + mux { + pins = "gpio110", "gpio113"; + function = "qup14"; + }; + + config { + pins = "gpio110", "gpio113"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + qupv3_se10_rts: qupv3_se10_rts { + mux { + pins = "gpio111"; + function = "qup14"; + }; + + config { + pins = "gpio111"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se10_tx: qupv3_se10_tx { + mux { + pins = "gpio112"; + function = "qup14"; + }; + + config { + pins = "gpio112"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se10_spi_pins: qupv3_se10_spi_pins { + qupv3_se10_spi_active: qupv3_se10_spi_active { + mux { + pins = "gpio110", "gpio111", "gpio112", + "gpio113"; + function = "qup14"; + }; + + config { + pins = "gpio110", "gpio111", "gpio112", + "gpio113"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { + mux { + pins = "gpio110", "gpio111", "gpio112", + "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio110", "gpio111", "gpio112", + "gpio113"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 11 pin mappings */ + qupv3_se11_i2c_pins: qupv3_se11_i2c_pins { + qupv3_se11_i2c_active: qupv3_se11_i2c_active { + mux { + pins = "gpio101", "gpio102"; + function = "qup15"; + }; + + config { + pins = "gpio101", "gpio102"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep { + mux { + pins = "gpio101", "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio101", "gpio102"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se11_4uart_pins: qupv3_se11_4uart_pins { + qupv3_se11_ctsrx: qupv3_se11_ctsrx { + mux { + pins = "gpio101", "gpio92"; + function = "qup15"; + }; + + config { + pins = "gpio101", "gpio92"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + qupv3_se11_rts: qupv3_se11_rts { + mux { + pins = "gpio102"; + function = "qup15"; + }; + + config { + pins = "gpio102"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se11_tx: qupv3_se11_tx { + mux { + pins = "gpio103"; + function = "qup15"; + }; + + config { + pins = "gpio103"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se11_spi_pins: qupv3_se11_spi_pins { + qupv3_se11_spi_active: qupv3_se11_spi_active { + mux { + pins = "gpio101", "gpio102", "gpio103", + "gpio92"; + function = "qup15"; + }; + + config { + pins = "gpio101", "gpio102", "gpio103", + "gpio92"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_sleep: qupv3_se11_spi_sleep { + mux { + pins = "gpio101", "gpio102", "gpio103", + "gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio101", "gpio102", "gpio103", + "gpio92"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio10"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio10"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + + sde_te1_active: sde_te1_active { + mux { + pins = "gpio11"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te1_suspend: sde_te1_suspend { + mux { + pins = "gpio11"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + sde_dp_aux_active: sde_dp_aux_active { + mux { + pins = "gpio42", "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio42", "gpio33"; + bias-disable = <0>; /* no pull */ + drive-strength = <8>; + }; + }; + + sde_dp_aux_suspend: sde_dp_aux_suspend { + mux { + pins = "gpio42", "gpio33"; + function = "gpio"; + }; + + config { + pins = "gpio42", "gpio33"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + bias-disable; + drive-strength = <16>; + }; + }; + + sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + wsa_swr_clk_pin { + wsa_swr_clk_sleep: wsa_swr_clk_sleep { + mux { + pins = "gpio49"; + function = "wsa_clk"; + }; + + config { + pins = "gpio49"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + wsa_swr_clk_active: wsa_swr_clk_active { + mux { + pins = "gpio49"; + function = "wsa_clk"; + }; + + config { + pins = "gpio49"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + }; + + wsa_swr_data_pin { + wsa_swr_data_sleep: wsa_swr_data_sleep { + mux { + pins = "gpio50"; + function = "wsa_data"; + }; + + config { + pins = "gpio50"; + drive-strength = <4>; + bias-bus-hold; + }; + }; + + wsa_swr_data_active: wsa_swr_data_active { + mux { + pins = "gpio50"; + function = "wsa_data"; + }; + + config { + pins = "gpio50"; + drive-strength = <4>; + bias-bus-hold; + }; + }; + }; + + /* WSA speaker reset pins */ + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio51"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio51"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + spkr_2_sd_n { + spkr_2_sd_n_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_2_sd_n_active: spkr_2_sd_n_active { + mux { + pins = "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio52"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + wcd9xxx_intr { + wcd_intr_default: wcd_intr_default{ + mux { + pins = "gpio58"; + function = "gpio"; + }; + + config { + pins = "gpio58"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + fsa_usbc_ana_en_n@42 { + fsa_usbc_ana_en: fsa_usbc_ana_en { + mux { + pins = "gpio42"; + function = "gpio"; + }; + + config { + pins = "gpio42"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + }; + + cci0_active: cci0_active { + mux { + /* CLK, DATA */ + pins = "gpio17","gpio18"; // Only 2 + function = "cci_i2c"; + }; + + config { + pins = "gpio17","gpio18"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio17","gpio18"; + function = "cci_i2c"; + }; + + config { + pins = "gpio17","gpio18"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA */ + pins = "gpio19","gpio20"; + function = "cci_i2c"; + }; + + config { + pins = "gpio19","gpio20"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio19","gpio20"; + function = "cci_i2c"; + }; + + config { + pins = "gpio19","gpio20"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_active: cci2_active { + mux { + /* CLK, DATA */ + pins = "gpio27","gpio28"; + function = "cci_i2c"; + }; + + config { + pins = "gpio27","gpio28"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_suspend: cci2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio27","gpio28"; + function = "cci_i2c"; + }; + + config { + pins = "gpio27","gpio28"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + /* SDC pin type */ + sdc1_clk_on: sdc1_clk_on { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc1_clk_off: sdc1_clk_off { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_cmd_on: sdc1_cmd_on { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_cmd_off: sdc1_cmd_off { + config { + pins = "sdc1_cmd"; + num-grp-pins = <1>; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_data_on: sdc1_data_on { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_data_off: sdc1_data_off { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_rclk_on: sdc1_rclk_on { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc1_rclk_off: sdc1_rclk_off { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_on: cd_on { + mux { + pins = "gpio69"; + function = "gpio"; + }; + + config { + pins = "gpio69"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_cd_off: cd_off { + mux { + pins = "gpio69"; + function = "gpio"; + }; + + config { + pins = "gpio69"; + drive-strength = <2>; + bias-disable; + }; + }; + + pmx_ts_active { + ts_active: ts_active { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio8"; + function = "gpio"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + pmx_ts_release { + ts_release: ts_release { + mux { + pins = "gpio9", "gpio8"; + function = "gpio"; + }; + + config { + pins = "gpio9", "gpio8"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + }; +}; + +&pm6150_gpios { + wcd934x_mclk { + wcd934x_mclk_default: wcd934x_mclk_default{ + pins = "gpio8"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <0>; + bias-disable; + output-low; + }; + }; +}; + +&pm6150l_gpios { + disp_pins { + disp_pins_default: disp_pins_default{ + pins = "gpio9"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <1>; + bias-disable; + output-low; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-pm.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-pm.dtsi new file mode 100644 index 000000000000..d62195111c45 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-pm.dtsi @@ -0,0 +1,170 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm-cluster@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + label = "L3"; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xfff>; + qcom,clstr-tmr-add = <1000>; + + qcom,pm-cluster-level@0 { /* D1 */ + reg = <0>; + label = "l3-wfi"; + qcom,psci-mode = <0x1>; + qcom,entry-latency-us = <660>; + qcom,exit-latency-us = <600>; + qcom,min-residency-us = <1260>; + }; + + qcom,pm-cluster-level@1 { /* D4 */ + reg = <1>; + label = "l3-pc"; + qcom,psci-mode = <0x4>; + qcom,entry-latency-us = <2752>; + qcom,exit-latency-us = <3048>; + qcom,min-residency-us = <6118>; + qcom,min-child-idx = <2>; + qcom,is-reset; + }; + + qcom,pm-cluster-level@2 { /* Cx Off */ + reg = <2>; + label = "cx-off"; + qcom,psci-mode = <0x224>; + qcom,entry-latency-us = <3638>; + qcom,exit-latency-us = <4562>; + qcom,min-residency-us = <8467>; + qcom,min-child-idx = <2>; + qcom,is-reset; + qcom,notify-rpm; + }; + + qcom,pm-cluster-level@3 { /* LLCC off, AOSS sleep */ + reg = <3>; + label = "llcc-off"; + qcom,psci-mode = <0xC24>; + qcom,entry-latency-us = <3263>; + qcom,exit-latency-us = <6562>; + qcom,min-residency-us = <9826>; + qcom,min-child-idx = <2>; + qcom,is-reset; + qcom,notify-rpm; + }; + + qcom,pm-cpu@0 { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,ref-stddev = <500>; + qcom,tmr-add = <1000>; + qcom,ref-premature-cnt = <1>; + qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 + &CPU5>; + + qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + label = "wfi"; + qcom,psci-cpu-mode = <0x1>; + qcom,entry-latency-us = <61>; + qcom,exit-latency-us = <60>; + qcom,min-residency-us = <121>; + }; + + qcom,pm-cpu-level@1 { /* C3 */ + reg = <1>; + label = "pc"; + qcom,psci-cpu-mode = <0x3>; + qcom,entry-latency-us = <549>; + qcom,exit-latency-us = <901>; + qcom,min-residency-us = <1774>; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + + qcom,pm-cpu-level@2 { /* C4 */ + reg = <2>; + label = "rail-pc"; + qcom,psci-cpu-mode = <0x4>; + qcom,entry-latency-us = <702>; + qcom,exit-latency-us = <915>; + qcom,min-residency-us = <4001>; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + + qcom,pm-cpu@1 { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,ref-stddev = <100>; + qcom,tmr-add = <100>; + qcom,ref-premature-cnt = <3>; + qcom,cpu = <&CPU6 &CPU7>; + + qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + label = "wfi"; + qcom,psci-cpu-mode = <0x1>; + qcom,entry-latency-us = <55>; + qcom,exit-latency-us = <66>; + qcom,min-residency-us = <121>; + }; + + qcom,pm-cpu-level@1 { /* C3 */ + reg = <1>; + label = "pc"; + qcom,psci-cpu-mode = <0x3>; + qcom,entry-latency-us = <523>; + qcom,exit-latency-us = <1244>; + qcom,min-residency-us = <2207>; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + + qcom,pm-cpu-level@2 { /* C4 */ + reg = <2>; + label = "rail-pc"; + qcom,psci-cpu-mode = <0x4>; + qcom,entry-latency-us = <526>; + qcom,exit-latency-us = <1854>; + qcom,min-residency-us = <5555>; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + }; + }; + + qcom,rpm-stats@c300000 { + compatible = "qcom,rpm-stats"; + reg = <0xc300000 0x1000>, <0xc3f0004 0x4>; + reg-names = "phys_addr_base", "offset_addr"; + qcom,num-records = <3>; + }; + + qcom,rpmh-master-stats@b221200 { + compatible = "qcom,rpmh-master-stats-v1"; + reg = <0xb221200 0x60>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-qrd-overlay.dts b/arch/arm/boot/dts/qcom/sdmmagpie-qrd-overlay.dts new file mode 100644 index 000000000000..1e26e1e66e9a --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-qrd-overlay.dts @@ -0,0 +1,70 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "sdmmagpie-audio-overlay.dtsi" +#include "sdmmagpie-qrd.dtsi" + +/ { + model = "QRD"; + compatible = "qcom,sdmmagpie-qrd", "qcom,sdmmagpie", "qcom,qrd"; + qcom,msm-id = <365 0x0>; + qcom,board-id = <11 0>; +}; + +&dsi_sw43404_amoled_video_display { + qcom,dsi-display-active; +}; + +&sm6150_snd { + qcom,model = "sm6150-wcd9375qrd-snd-card"; + qcom,audio-routing = + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Analog Mic2", + "TX DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "TX DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "TX DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "TX_AIF1 CAP", "VA_MCLK", + "TX_AIF2 CAP", "VA_MCLK", + "RX AIF1 PB", "VA_MCLK", + "RX AIF2 PB", "VA_MCLK", + "RX AIF3 PB", "VA_MCLK", + "RX AIF4 PB", "VA_MCLK", + "HPHL_OUT", "VA_MCLK", + "HPHR_OUT", "VA_MCLK", + "AUX_OUT", "VA_MCLK", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "IN3_AUX", "AUX_OUT", + "TX SWR_ADC0", "ADC1_OUTPUT", + "TX SWR_ADC2", "ADC2_OUTPUT", + "WSA SRC0_INP", "SRC0", + "WSA_TX DEC0_INP", "TX DEC0 MUX", + "WSA_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "SpkrLeft IN", "WSA_SPK1 OUT", + "WSA_SPK1 OUT", "VA_MCLK"; + qcom,wsa-max-devs = <1>; + qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0213>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrLeft"; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-qrd.dts b/arch/arm/boot/dts/qcom/sdmmagpie-qrd.dts new file mode 100644 index 000000000000..6738bb875b84 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-qrd.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdmmagpie.dtsi" +#include "sdmmagpie-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDMMAGPIE PM6150 QRD"; + compatible = "qcom,sdmmagpie-qrd", "qcom,sdmmagpie", "qcom,qrd"; + qcom,board-id = <11 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-qrd.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-qrd.dtsi new file mode 100644 index 000000000000..92ffe56d4e69 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-qrd.dtsi @@ -0,0 +1,431 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include "sdmmagpie-thermal-overlay.dtsi" + +#include "sdmmagpie-sde-display.dtsi" +#include "sdmmagpie-camera-sensor-qrd.dtsi" +&soc { + fpc1020 { + compatible = "fpc,fpc1020"; + interrupt-parent = <&tlmm>; + interrupts = <90 0>; + fpc,gpio_rst = <&tlmm 91 0x0>; + fpc,gpio_irq = <&tlmm 90 0>; + vcc_spi-supply = <&pm6150_l10>; + vdd_io-supply = <&pm6150_l10>; + vdd_ana-supply = <&pm6150_l10>; + fpc,enable-on-boot; + pinctrl-names = "fpc1020_reset_reset", + "fpc1020_reset_active", + "fpc1020_irq_active"; + pinctrl-0 = <&fpc_reset_low>; + pinctrl-1 = <&fpc_reset_high>; + pinctrl-2 = <&fpc_int_low>; + }; + + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + #include "qg-batterydata-mlp466076-3200mah.dtsi" + }; +}; + +&qupv3_se7_i2c{ + qcom,i2c-touch-active="st,fts"; + status = "ok"; + st_fts@49 { + compatible = "st,fts"; + reg = <0x49>; + interrupt-parent = <&tlmm>; + interrupts = <9 0x2008>; + vdd-supply = <&pm6150_l10>; + avdd-supply = <&pm6150l_l7>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + st,irq-gpio = <&tlmm 9 0x2008>; + st,reset-gpio = <&tlmm 8 0x00>; + st,regulator_dvdd = "vdd"; + st,regulator_avdd = "avdd"; + }; +}; + +&tlmm { + pmx_ts_active { + ts_active: ts_active { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio8"; + function = "gpio"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + +}; + +&qupv3_se8_2uart { + status = "ok"; +}; + +&qupv3_se3_4uart { + status = "ok"; +}; + +&pm6150a_amoled { + status = "ok"; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v3"; + + vdda-phy-supply = <&pm6150_l4>; /* 0.88v */ + vdda-pll-supply = <&pm6150l_l3>; /* 1.2v */ + vdda-phy-max-microamp = <62900>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm6150_l19>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm6150_l12>; + vccq2-voltage-level = <1750000 1950000>; + vcc-max-microamp = <600000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm6150l_l3>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&qupv3_se2_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 37 0x00>; + qcom,nq-ven = <&tlmm 12 0x00>; + qcom,nq-firm = <&tlmm 36 0x00>; + qcom,nq-clkreq = <&tlmm 31 0x00>; + qcom,nq-esepwr = <&tlmm 94 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <37 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active + &nfc_clk_req_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend + &nfc_clk_req_suspend>; + }; +}; + +&sdhc_1 { + vdd-supply = <&pm6150_l19>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&pm6150_l12>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm6150l_l9>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&pm6150l_l6>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&tlmm 69 GPIO_ACTIVE_HIGH>; + + status = "ok"; +}; + +&dsi_sw43404_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sw43404_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sw43404_amoled_fhd_plus_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; +}; + +&pm6150_qg { + qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <100>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; +}; + +&pm6150_charger { + io-channels = <&pm6150_vadc ADC_USB_IN_V_16>, + <&pm6150_vadc ADC_USB_IN_I>, + <&pm6150_vadc ADC_CHG_TEMP>, + <&pm6150_vadc ADC_DIE_TEMP>, + <&pm6150l_vadc ADC_AMUX_THM1_PU2>, + <&pm6150_vadc ADC_SBUx>, + <&pm6150_vadc ADC_VPH_PWR>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage"; + qcom,battery-data = <&mtp_batterydata>; + qcom,auto-recharge-soc = <98>; + qcom,sw-jeita-enable; + qcom,fcc-stepping-enable; + qcom,suspend-input-on-debug-batt; + qcom,sec-charger-config = <1>; + qcom,thermal-mitigation = <4200000 3500000 3000000 + 2500000 2000000 1500000 1000000 500000>; + dpdm-supply = <&qusb_phy0>; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; +}; + +&pm6150_gpios { + smb_stat { + smb_stat_default: smb_stat_default { + pins = "gpio3"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = <0>; + }; + }; +}; + +&qupv3_se9_i2c { + status = "ok"; + #include "smb1390.dtsi" +}; + +&smb1390 { + /delete-property/ interrupts; + interrupts = <0x0 0xc2 0x0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1390_charger { + compatible = "qcom,smb1390-charger-psy"; + io-channels = <&pm6150l_vadc ADC_AMUX_THM2>; + io-channel-names = "cp_die_temp"; + status = "ok"; +}; + +&pm6150l_gpios { + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio2"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm6150l_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + linux,can-disable; + debounce-interval = <15>; + gpio-key,wakeup; + }; + }; +}; + +&qusb_phy0 { + qcom,qusb-phy-init-seq = + /* */ + <0x23 0x210 /* PWR_CTRL1 */ + 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */ + 0x7c 0x18c /* PLL_CLOCK_INVERTERS */ + 0x80 0x2c /* PLL_CMODE */ + 0x0a 0x184 /* PLL_LOCK_DELAY */ + 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ + 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ + 0x20 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x21 0x214 /* PWR_CTRL2 */ + 0x00 0x220 /* IMP_CTRL1 */ + 0x18 0x224 /* IMP_CTRL2 */ + 0x37 0x240 /* TUNE1 */ + 0x29 0x244 /* TUNE2 */ + 0xca 0x248 /* TUNE3 */ + 0x04 0x24c /* TUNE4 */ + 0x03 0x250 /* TUNE5 */ + 0x00 0x23c /* CHG_CTRL2 */ + 0x22 0x210>; /* PWR_CTRL1 */ + + qcom,qusb-phy-host-init-seq = + /* */ + <0x23 0x210 /* PWR_CTRL1 */ + 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */ + 0x7c 0x18c /* PLL_CLOCK_INVERTERS */ + 0x80 0x2c /* PLL_CMODE */ + 0x0a 0x184 /* PLL_LOCK_DELAY */ + 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ + 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ + 0x20 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x21 0x214 /* PWR_CTRL2 */ + 0x00 0x220 /* IMP_CTRL1 */ + 0x18 0x224 /* IMP_CTRL2 */ + 0x37 0x240 /* TUNE1 */ + 0x29 0x244 /* TUNE2 */ + 0xca 0x248 /* TUNE3 */ + 0x04 0x24c /* TUNE4 */ + 0x03 0x250 /* TUNE5 */ + 0x00 0x23c /* CHG_CTRL2 */ + 0x22 0x210>; /* PWR_CTRL1 */ +}; + +&fsa4480 { + status = "disabled"; +}; + +&sde_dp { + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; + pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>; + pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>; + qcom,aux-en-gpio = <&tlmm 42 0>; + qcom,aux-sel-gpio = <&tlmm 33 0>; + qcom,dp-gpio-aux-switch; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-qupv3.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-qupv3.dtsi new file mode 100644 index 000000000000..b6987a2fa256 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-qupv3.dtsi @@ -0,0 +1,565 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + /* QUPv3 South instances */ + qupv3_0: qcom,qupv3_0_geni_se@0x8c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x8c0000 0x2000>; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; + qcom,iommu-s1-bypass; + + iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0x203 0x0>; + }; + }; + + /* I2C */ + qupv3_se0_i2c: i2c@0x880000 { + compatible = "qcom,i2c-geni"; + reg = <0x880000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + dmas = <&gpi_dma0 0 0 3 64 0>, + <&gpi_dma0 1 0 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@0x884000 { + compatible = "qcom,i2c-geni"; + reg = <0x884000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + dmas = <&gpi_dma0 0 1 3 64 0>, + <&gpi_dma0 1 1 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@0x888000 { + compatible = "qcom,i2c-geni"; + reg = <0x888000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + dmas = <&gpi_dma0 0 2 3 64 0>, + <&gpi_dma0 1 2 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@0x88c000 { + compatible = "qcom,i2c-geni"; + reg = <0x88c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + dmas = <&gpi_dma0 0 3 3 64 0>, + <&gpi_dma0 1 3 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@0x890000 { + compatible = "qcom,i2c-geni"; + reg = <0x890000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + dmas = <&gpi_dma0 0 4 3 64 0>, + <&gpi_dma0 1 4 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /*HS UART*/ + qupv3_se3_4uart: qcom,qup_uart@0x88c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x88c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>, + <&qupv3_se3_tx>; + pinctrl-1 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>, + <&qupv3_se3_tx>; + interrupts-extended = <&pdc GIC_SPI 604 0>, + <&tlmm 41 0>; + status = "disabled"; + qcom,wakeup-byte = <0xFD>; + qcom,wrapper-core = <&qupv3_0>; + }; + + qupv3_se4_4uart: qcom,qup_uart@0x890000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x890000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_ctsrx>, <&qupv3_se4_rts>, + <&qupv3_se4_tx>; + pinctrl-1 = <&qupv3_se4_ctsrx>, <&qupv3_se4_rts>, + <&qupv3_se4_tx>; + interrupts-extended = <&pdc GIC_SPI 605 0>, + <&tlmm 56 0>; + status = "disabled"; + qcom,wakeup-byte = <0xFD>; + qcom,wrapper-core = <&qupv3_0>; + }; + + /* SPI */ + qupv3_se0_spi: spi@0x880000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x880000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + dmas = <&gpi_dma0 0 0 1 64 0>, + <&gpi_dma0 1 0 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se1_spi: spi@0x884000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x884000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + dmas = <&gpi_dma0 0 1 1 64 0>, + <&gpi_dma0 1 1 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se3_spi: spi@0x88c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x88c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + dmas = <&gpi_dma0 0 3 1 64 0>, + <&gpi_dma0 1 3 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se4_spi: spi@0x890000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x890000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + dmas = <&gpi_dma0 0 4 1 64 0>, + <&gpi_dma0 1 4 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + + /* QUPv3 North Instances */ + qupv3_1: qcom,qupv3_1_geni_se@0xac0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0xac0000 0x2000>; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; + qcom,iommu-s1-bypass; + + iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0x4c3 0x0>; + }; + }; + + /* Debug UART Instance for CDP/MTP/RUMI platform */ + qupv3_se8_2uart: qcom,qup_uart@0xa88000 { + compatible = "qcom,msm-geni-console"; + reg = <0xa88000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_2uart_active>; + pinctrl-1 = <&qupv3_se8_2uart_sleep>; + interrupts = ; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* I2C */ + qupv3_se6_i2c: i2c@0xa80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + dmas = <&gpi_dma1 0 0 3 64 0>, + <&gpi_dma1 1 0 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se7_i2c: i2c@0xa84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + dmas = <&gpi_dma1 0 1 3 64 0>, + <&gpi_dma1 1 1 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se8_i2c: i2c@0xa88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + dmas = <&gpi_dma1 0 2 3 64 0>, + <&gpi_dma1 1 2 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@0xa8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + dmas = <&gpi_dma1 0 3 3 64 0>, + <&gpi_dma1 1 3 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se10_i2c: i2c@0xa90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + dmas = <&gpi_dma1 0 4 3 64 0>, + <&gpi_dma1 1 4 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_i2c_active>; + pinctrl-1 = <&qupv3_se10_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se11_i2c: i2c@0xa94000 { + compatible = "qcom,i2c-geni"; + reg = <0xa94000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + dmas = <&gpi_dma1 0 5 3 64 0>, + <&gpi_dma1 1 5 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_i2c_active>; + pinctrl-1 = <&qupv3_se11_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /*HS UART*/ + qupv3_se10_4uart: qcom,qup_uart@0xa90000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa90000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_ctsrx>, <&qupv3_se10_rts>, + <&qupv3_se10_tx>; + pinctrl-1 = <&qupv3_se10_ctsrx>, <&qupv3_se10_rts>, + <&qupv3_se10_tx>; + interrupts-extended = <&pdc GIC_SPI 357 0>, + <&tlmm 113 0>; + status = "disabled"; + qcom,wakeup-byte = <0xFD>; + qcom,wrapper-core = <&qupv3_1>; + }; + + qupv3_se11_4uart: qcom,qup_uart@0xa94000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa94000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_ctsrx>, <&qupv3_se11_rts>, + <&qupv3_se11_tx>; + pinctrl-1 = <&qupv3_se11_ctsrx>, <&qupv3_se11_rts>, + <&qupv3_se11_tx>; + interrupts-extended = <&pdc GIC_SPI 358 0>, + <&tlmm 92 0>; + status = "disabled"; + qcom,wakeup-byte = <0xFD>; + qcom,wrapper-core = <&qupv3_1>; + }; + + /* SPI */ + qupv3_se6_spi: spi@0xa80000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa80000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + dmas = <&gpi_dma1 0 0 1 64 0>, + <&gpi_dma1 1 0 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se7_spi: spi@0xa84000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa84000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_active>; + pinctrl-1 = <&qupv3_se7_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + dmas = <&gpi_dma1 0 1 1 64 0>, + <&gpi_dma1 1 1 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se8_spi: spi@0xa88000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa88000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_spi_active>; + pinctrl-1 = <&qupv3_se8_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + dmas = <&gpi_dma1 0 2 1 64 0>, + <&gpi_dma1 1 2 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se10_spi: spi@0xa90000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa90000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_spi_active>; + pinctrl-1 = <&qupv3_se10_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + dmas = <&gpi_dma1 0 4 1 64 0>, + <&gpi_dma1 1 4 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se11_spi: spi@0xa94000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa94000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_spi_active>; + pinctrl-1 = <&qupv3_se11_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + dmas = <&gpi_dma1 0 5 1 64 0>, + <&gpi_dma1 1 5 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll-regulator.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-regulator.dtsi similarity index 55% rename from arch/arm64/boot/dts/qcom/atoll-regulator.dtsi rename to arch/arm/boot/dts/qcom/sdmmagpie-regulator.dtsi index 3106ced89fc1..404111ea44dc 100644 --- a/arch/arm64/boot/dts/qcom/atoll-regulator.dtsi +++ b/arch/arm/boot/dts/qcom/sdmmagpie-regulator.dtsi @@ -1,5 +1,4 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -7,151 +6,180 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include &soc { - rpmh-regulator-cxlvl { + /* RPMh regulators */ + /* PM6150 S2 = VDD_GFX supply */ + rpmh-regulator-gfxlvl { compatible = "qcom,rpmh-arc-regulator"; mboxes = <&apps_rsc 0>; - qcom,resource-name = "cx.lvl"; - pm6150l-s1-level-parent-supply = <&VDD_MX_LEVEL>; - pm6150l-s1-level_ao-parent-supply = <&VDD_MX_LEVEL_AO>; - VDD_CX_LEVEL: - S1C_LEVEL: - pm6150l_s1_level: regulator-pm6150l-s1-level { - regulator-name = "pm6150l_s1_level"; + qcom,resource-name = "gfx.lvl"; + VDD_GFX_LEVEL: + S2A_LEVEL: pm6150_s2_level: regulator-pm6150-s2-level { + regulator-name = "pm6150_s2_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + /* pm6150 S3 = VDD_MX supply */ + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "mx.lvl"; + + VDD_MX_LEVEL: + S3A_LEVEL: pm6150_s3_level: regulator-pm6150-s3 { + regulator-name = "pm6150_s3_level"; qcom,set = ; regulator-min-microvolt = - ; + ; regulator-max-microvolt = - ; + ; qcom,init-voltage-level = - ; - qcom,min-dropout-voltage-level = <(-1)>; + ; }; - VDD_CX_LEVEL_AO: - S1C_LEVEL_AO: - pm6150l_s1_level_ao: regulator-pm6150l-s1-level-ao { - regulator-name = "pm6150l_s1_level_ao"; + VDD_MX_LEVEL_AO: + S3A_LEVEL_AO: pm6150_s3_level_ao: regulator-pm6150-s3-level-ao { + regulator-name = "pm6150_s3_level_ao"; qcom,set = ; regulator-min-microvolt = - ; + ; regulator-max-microvolt = - ; + ; qcom,init-voltage-level = - ; - qcom,min-dropout-voltage-level = <(-1)>; + ; }; - cx_cdev: regulator-cdev { - compatible = "qcom,rpmh-reg-cdev"; - mboxes = <&qmp_aop 0>; - qcom,reg-resource-name = "cx"; + mx_cdev: mx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&VDD_MX_LEVEL>; + regulator-levels = ; #cooling-cells = <2>; }; }; - rpmh-regulator-gfxlvl { - compatible = "qcom,rpmh-arc-regulator"; + rpmh-regulator-smpc1 { + compatible = "qcom,rpmh-vrm-regulator"; mboxes = <&apps_rsc 0>; - qcom,resource-name = "gfx.lvl"; - VDD_GFX_LEVEL: - S2A_LEVEL: - pm6150_s2_level: regulator-pm6150-s2-level { - regulator-name = "pm6150_s2_level"; + qcom,resource-name = "smpc1"; + S1C: pm6150l_s1: regulator-pm6150l-s1 { + regulator-name = "pm6150l_s1"; qcom,set = ; - regulator-min-microvolt = - ; - regulator-max-microvolt = - ; - qcom,init-voltage-level = - ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1000000>; }; }; - rpmh-regulator-mxlvl { + /* pm6150l S2 + S3 = 2 phase VDD_CX supply */ + rpmh-regulator-cxlvl { compatible = "qcom,rpmh-arc-regulator"; mboxes = <&apps_rsc 0>; - qcom,resource-name = "mx.lvl"; - VDD_MX_LEVEL: - S3A_LEVEL: - pm6150_s3_level: regulator-pm6150-s3-level { - regulator-name = "pm6150_s3_level"; + qcom,resource-name = "cx.lvl"; + pm6150l-s2-level-parent-supply = <&VDD_MX_LEVEL>; + pm6150l-s2-level_ao-parent-supply = <&VDD_MX_LEVEL_AO>; + + VDD_CX_LEVEL: + S2C_LEVEL: pm6150l_s2_level: regulator-pm6150l-s2 { + regulator-name = "pm6150l_s2_level"; qcom,set = ; regulator-min-microvolt = - ; + ; regulator-max-microvolt = - ; + ; qcom,init-voltage-level = - ; + ; + qcom,min-dropout-voltage-level = <(-1)>; }; - VDD_MX_LEVEL_AO: - S3A_LEVEL_AO: - pm6150_s3_level_ao: regulator-pm6150-s3-level-ao { - regulator-name = "pm6150_s3_level_ao"; + VDD_CX_LEVEL_AO: S2C_LEVEL_AO: + pm6150l_s2_level_ao: regulator-pm6150l-s2-level-ao { qcom,set = ; + regulator-name = "pm6150l_s2_level_ao"; regulator-min-microvolt = - ; + ; regulator-max-microvolt = - ; + ; qcom,init-voltage-level = - ; + ; + qcom,min-dropout-voltage-level = <(-1)>; }; - mx_cdev: mx-cdev-lvl { - compatible = "qcom,regulator-cooling-device"; - regulator-cdev-supply = <&VDD_MX_LEVEL>; - regulator-levels = ; + cx_cdev: regulator-cdev { + compatible = "qcom,rpmh-reg-cdev"; + mboxes = <&qmp_aop 0>; + qcom,reg-resource-name = "cx"; #cooling-cells = <2>; }; }; - rpmh-regulator-smpa1 { - compatible = "qcom,rpmh-vrm-regulator"; + /* pm6150l S7 = VDD_MSS supply */ + rpmh-regulator-modemlvl { + compatible = "qcom,rpmh-arc-regulator"; mboxes = <&apps_rsc 0>; - qcom,resource-name = "smpa1"; - S1A: - pm6150_s1: regulator-pm6150-s1 { - regulator-name = "pm6150_s1"; + qcom,resource-name = "mss.lvl"; + + VDD_MSS_LEVEL: + S7C_LEVEL: pm6150l_s7_level: regulator-pm6150l-s7 { + regulator-name = "pm6150l_s7_level"; qcom,set = ; - regulator-min-microvolt = <1128000>; - regulator-max-microvolt = <1128000>; - qcom,init-voltage = <1128000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; }; }; - rpmh-regulator-smpa4 { + rpmh-regulator-smpc8 { compatible = "qcom,rpmh-vrm-regulator"; mboxes = <&apps_rsc 0>; - qcom,resource-name = "smpa4"; - S4A: - pm6150_s4: regulator-pm6150-s4 { - regulator-name = "pm6150_s4"; + qcom,resource-name = "smpc8"; + S8C: pm6150l_s8: regulator-pm6150l-s8 { + regulator-name = "pm6150l_s8"; qcom,set = ; - regulator-min-microvolt = <824000>; - regulator-max-microvolt = <1120000>; - qcom,init-voltage = <824000>; + regulator-min-microvolt = <1120000>; + regulator-max-microvolt = <1408000>; + qcom,init-voltage = <1120000>; }; }; - rpmh-regulator-smpa5 { + rpmh-regulator-smpf1 { compatible = "qcom,rpmh-vrm-regulator"; mboxes = <&apps_rsc 0>; - qcom,resource-name = "smpa5"; - S5A: - pm6150_s5: regulator-pm6150-s5 { - regulator-name = "pm6150_s5"; + qcom,resource-name = "smpf1"; + S1F: pm8009_s1: regulator-pm8009-s1 { + regulator-name = "pm8009_s1"; qcom,set = ; - regulator-min-microvolt = <1744000>; - regulator-max-microvolt = <2040000>; - qcom,init-voltage = <1744000>; + regulator-min-microvolt = <1064000>; + regulator-max-microvolt = <1360000>; + qcom,init-voltage = <1064000>; + }; + }; + + rpmh-regulator-smpf2 { + compatible = "qcom,rpmh-xob-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpf2"; + S2F: pm8009_s2: regulator-pm8009-s2 { + regulator-name = "pm8009_s2"; + qcom,set = ; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; }; }; @@ -161,18 +189,16 @@ qcom,resource-name = "ldoa1"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L1A: - pm6150_l1: regulator-pm6150-l1 { + L1A: pm6150_l1: regulator-pm6150-l1 { regulator-name = "pm6150_l1"; qcom,set = ; - regulator-min-microvolt = <1178000>; - regulator-max-microvolt = <1256000>; - qcom,init-voltage = <1178000>; - qcom,init-mode = - ; + regulator-min-microvolt = <1096000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1096000>; + qcom,init-mode = ; }; }; @@ -182,18 +208,16 @@ qcom,resource-name = "ldoa2"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L2A: - pm6150_l2: regulator-pm6150-l2 { + L2A: pm6150_l2: regulator-pm6150-l2 { regulator-name = "pm6150_l2"; qcom,set = ; regulator-min-microvolt = <944000>; regulator-max-microvolt = <1056000>; qcom,init-voltage = <944000>; - qcom,init-mode = - ; + qcom,init-mode = ; }; }; @@ -203,18 +227,16 @@ qcom,resource-name = "ldoa3"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L3A: - pm6150_l3: regulator-pm6150-l3 { + L3A: pm6150_l3: regulator-pm6150-l3 { regulator-name = "pm6150_l3"; qcom,set = ; regulator-min-microvolt = <968000>; regulator-max-microvolt = <1064000>; qcom,init-voltage = <968000>; - qcom,init-mode = - ; + qcom,init-mode = ; }; }; @@ -224,18 +246,16 @@ qcom,resource-name = "ldoa4"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L4A: - pm6150_l4: regulator-pm6150-l4 { + L4A: pm6150_l4: regulator-pm6150-l4 { regulator-name = "pm6150_l4"; qcom,set = ; regulator-min-microvolt = <824000>; - regulator-max-microvolt = <928000>; + regulator-max-microvolt = <920000>; qcom,init-voltage = <824000>; - qcom,init-mode = - ; + qcom,init-mode = ; }; }; @@ -245,18 +265,16 @@ qcom,resource-name = "ldoa5"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L5A: - pm6150_l5: regulator-pm6150-l5 { + L5A: pm6150_l5: regulator-pm6150-l5 { regulator-name = "pm6150_l5"; qcom,set = ; - regulator-min-microvolt = <2496000>; - regulator-max-microvolt = <3000000>; - qcom,init-voltage = <2496000>; - qcom,init-mode = - ; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2800000>; + qcom,init-voltage = <2600000>; + qcom,init-mode = ; }; }; @@ -266,73 +284,73 @@ qcom,resource-name = "ldoa6"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L6A: - pm6150_l6: regulator-pm6150-l6 { + L6A: pm6150_l6: regulator-pm6150-l6 { regulator-name = "pm6150_l6"; qcom,set = ; - regulator-min-microvolt = <568000>; - regulator-max-microvolt = <648000>; - qcom,init-voltage = <568000>; - qcom,init-mode = - ; + regulator-min-microvolt = <1096000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1096000>; + qcom,init-mode = ; }; }; + /* pm6150 L7 = LPI_MX supply */ rpmh-regulator-lmxlvl { compatible = "qcom,rpmh-arc-regulator"; mboxes = <&apps_rsc 0>; qcom,resource-name = "lmx.lvl"; - L7A_LEVEL: - pm6150_l7_level: regulator-pm6150-l7-level { + LPI_MX_LEVEL: + L7A_LEVEL: pm6150_l7_level: regulator-pm6150-l7 { regulator-name = "pm6150_l7_level"; qcom,set = ; regulator-min-microvolt = - ; + ; regulator-max-microvolt = - ; + ; qcom,init-voltage-level = - ; + ; }; }; + /* pm6150 L8 = LPI_CX supply */ rpmh-regulator-lcxlvl { compatible = "qcom,rpmh-arc-regulator"; mboxes = <&apps_rsc 0>; qcom,resource-name = "lcx.lvl"; - L8A_LEVEL: - pm6150_l8_level: regulator-pm6150-l8-level { + LPI_CX_LEVEL: + L8A_LEVEL: pm6150_l8_level: regulator-pm6150-l8 { regulator-name = "pm6150_l8_level"; qcom,set = ; regulator-min-microvolt = - ; + ; regulator-max-microvolt = - ; + ; qcom,init-voltage-level = - ; + ; }; }; + /* pm6150 L9 = WCSS_CX supply */ rpmh-regulator-ldoa9 { compatible = "qcom,rpmh-vrm-regulator"; mboxes = <&apps_rsc 0>; qcom,resource-name = "ldoa9"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L9A: - pm6150_l9: regulator-pm6150-l9 { + WCSS_CX: + L9A: pm6150_l9: regulator-pm6150-l9 { regulator-name = "pm6150_l9"; qcom,set = ; - regulator-min-microvolt = <488000>; - regulator-max-microvolt = <800000>; - qcom,init-voltage = <488000>; - qcom,init-mode = - ; + regulator-min-microvolt = <624000>; + regulator-max-microvolt = <760000>; + qcom,init-voltage = <624000>; + qcom,init-mode = ; }; }; @@ -342,18 +360,16 @@ qcom,resource-name = "ldoa10"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; - qcom,mode-threshold-currents = <0 1>; - L10A: - pm6150_l10: regulator-pm6150-l10 { + ; + qcom,mode-threshold-currents = <0 10000>; + L10A: pm6150_l10: regulator-pm6150-l10 { regulator-name = "pm6150_l10"; qcom,set = ; - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <1720000>; regulator-max-microvolt = <1832000>; - qcom,init-voltage = <1800000>; - qcom,init-mode = - ; + qcom,init-voltage = <1720000>; + qcom,init-mode = ; }; }; @@ -363,18 +379,16 @@ qcom,resource-name = "ldoa11"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L11A: - pm6150_l11: regulator-pm6150-l11 { + L11A: pm6150_l11: regulator-pm6150-l11 { regulator-name = "pm6150_l11"; qcom,set = ; - regulator-min-microvolt = <1696000>; - regulator-max-microvolt = <1904000>; - qcom,init-voltage = <1696000>; - qcom,init-mode = - ; + regulator-min-microvolt = <1616000>; + regulator-max-microvolt = <1984000>; + qcom,init-voltage = <1616000>; + qcom,init-mode = ; }; }; @@ -384,18 +398,16 @@ qcom,resource-name = "ldoa12"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L12A: - pm6150_l12: regulator-pm6150-l12 { + L12A: pm6150_l12: regulator-pm6150-l12 { regulator-name = "pm6150_l12"; qcom,set = ; regulator-min-microvolt = <1696000>; regulator-max-microvolt = <1952000>; qcom,init-voltage = <1696000>; - qcom,init-mode = - ; + qcom,init-mode = ; }; }; @@ -405,18 +417,16 @@ qcom,resource-name = "ldoa13"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L13A: - pm6150_l13: regulator-pm6150-l13 { + L13A: pm6150_l13: regulator-pm6150-l13 { regulator-name = "pm6150_l13"; qcom,set = ; regulator-min-microvolt = <1696000>; regulator-max-microvolt = <1904000>; qcom,init-voltage = <1696000>; - qcom,init-mode = - ; + qcom,init-mode = ; }; }; @@ -426,18 +436,16 @@ qcom,resource-name = "ldoa14"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L14A: - pm6150_l14: regulator-pm6150-l14 { + L14A: pm6150_l14: regulator-pm6150-l14 { regulator-name = "pm6150_l14"; qcom,set = ; - regulator-min-microvolt = <1728000>; - regulator-max-microvolt = <1832000>; - qcom,init-voltage = <1728000>; - qcom,init-mode = - ; + regulator-min-microvolt = <1720000>; + regulator-max-microvolt = <1856000>; + qcom,init-voltage = <1720000>; + qcom,init-mode = ; }; }; @@ -447,18 +455,16 @@ qcom,resource-name = "ldoa15"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L15A: - pm6150_l15: regulator-pm6150-l15 { + L15A: pm6150_l15: regulator-pm6150-l15 { regulator-name = "pm6150_l15"; qcom,set = ; regulator-min-microvolt = <1696000>; regulator-max-microvolt = <1904000>; qcom,init-voltage = <1696000>; - qcom,init-mode = - ; + qcom,init-mode = ; }; }; @@ -468,18 +474,16 @@ qcom,resource-name = "ldoa16"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L16A: - pm6150_l16: regulator-pm6150-l16 { + L16A: pm6150_l16: regulator-pm6150-l16 { regulator-name = "pm6150_l16"; qcom,set = ; - regulator-min-microvolt = <2496000>; - regulator-max-microvolt = <3304000>; - qcom,init-voltage = <2496000>; - qcom,init-mode = - ; + regulator-min-microvolt = <2424000>; + regulator-max-microvolt = <2976000>; + qcom,init-voltage = <2424000>; + qcom,init-mode = ; }; }; @@ -489,39 +493,30 @@ qcom,resource-name = "ldoa17"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L17A: - pm6150_l17: regulator-pm6150-l17 { + pm6150_l17-parent-supply = <&pm6150_l11>; + + L17A: pm6150_l17: regulator-pm6150-l17 { regulator-name = "pm6150_l17"; qcom,set = ; - regulator-min-microvolt = <2920000>; + regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3232000>; - qcom,init-voltage = <2920000>; - qcom,init-mode = - ; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; }; }; rpmh-regulator-ldoa18 { - compatible = "qcom,rpmh-vrm-regulator"; + compatible = "qcom,rpmh-xob-regulator"; mboxes = <&apps_rsc 0>; qcom,resource-name = "ldoa18"; - qcom,regulator-type = "pmic5-ldo"; - qcom,supported-modes = - ; - qcom,mode-threshold-currents = <0 1>; - L18A: - pm6150_l18: regulator-pm6150-l18 { + L18A: pm6150_l18: regulator-pm6150-l18 { regulator-name = "pm6150_l18"; qcom,set = ; - regulator-min-microvolt = <2496000>; - regulator-max-microvolt = <3304000>; - qcom,init-voltage = <2496000>; - qcom,init-mode = - ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; }; }; @@ -531,50 +526,16 @@ qcom,resource-name = "ldoa19"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L19A: - pm6150_l19: regulator-pm6150-l19 { + L19A: pm6150_l19: regulator-pm6150-l19 { regulator-name = "pm6150_l19"; qcom,set = ; - regulator-min-microvolt = <2696000>; + regulator-min-microvolt = <2944000>; regulator-max-microvolt = <3304000>; - qcom,init-voltage = <2696000>; - qcom,init-mode = - ; - }; - }; - - rpmh-regulator-msslvl { - compatible = "qcom,rpmh-arc-regulator"; - mboxes = <&apps_rsc 0>; - qcom,resource-name = "mss.lvl"; - VDD_MSS_LEVEL: - S7C_LEVEL: - pm6150l_s7_level: regulator-pm6150l-s7-level { - regulator-name = "pm6150l_s7_level"; - qcom,set = ; - regulator-min-microvolt = - ; - regulator-max-microvolt = - ; - qcom,init-voltage-level = - ; - }; - }; - - rpmh-regulator-smpc8 { - compatible = "qcom,rpmh-vrm-regulator"; - mboxes = <&apps_rsc 0>; - qcom,resource-name = "smpc8"; - S8C: - pm6150l_s8: regulator-pm6150l-s8 { - regulator-name = "pm6150l_s8"; - qcom,set = ; - regulator-min-microvolt = <1120000>; - regulator-max-microvolt = <1408000>; - qcom,init-voltage = <1120000>; + qcom,init-voltage = <2944000>; + qcom,init-mode = ; }; }; @@ -584,18 +545,16 @@ qcom,resource-name = "ldoc1"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; - qcom,mode-threshold-currents = <0 1>; - L1C: - pm6150l_l1: regulator-pm6150l-l1 { + ; + qcom,mode-threshold-currents = <0 10000>; + L1C: pm6150l_l1: regulator-pm6150l-l1 { regulator-name = "pm6150l_l1"; qcom,set = ; regulator-min-microvolt = <1616000>; regulator-max-microvolt = <1984000>; qcom,init-voltage = <1616000>; - qcom,init-mode = - ; + qcom,init-mode = ; }; }; @@ -605,18 +564,16 @@ qcom,resource-name = "ldoc2"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; - qcom,mode-threshold-currents = <0 1>; - L2C: - pm6150l_l2: regulator-pm6150l-l2 { + ; + qcom,mode-threshold-currents = <0 10000>; + L2C: pm6150l_l2: regulator-pm6150l-l2 { regulator-name = "pm6150l_l2"; qcom,set = ; - regulator-min-microvolt = <1168000>; - regulator-max-microvolt = <1304000>; - qcom,init-voltage = <1168000>; - qcom,init-mode = - ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1352000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; }; }; @@ -626,18 +583,16 @@ qcom,resource-name = "ldoc3"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L3C: - pm6150l_l3: regulator-pm6150l-l3 { + L3C: pm6150l_l3: regulator-pm6150l-l3 { regulator-name = "pm6150l_l3"; qcom,set = ; regulator-min-microvolt = <1144000>; - regulator-max-microvolt = <1304000>; + regulator-max-microvolt = <1256000>; qcom,init-voltage = <1144000>; - qcom,init-mode = - ; + qcom,init-mode = ; }; }; @@ -647,18 +602,16 @@ qcom,resource-name = "ldoc4"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L4C: - pm6150l_l4: regulator-pm6150l-l4 { + L4C: pm6150l_l4: regulator-pm6150l-l4 { regulator-name = "pm6150l_l4"; qcom,set = ; regulator-min-microvolt = <1648000>; - regulator-max-microvolt = <3304000>; + regulator-max-microvolt = <2950000>; qcom,init-voltage = <1648000>; - qcom,init-mode = - ; + qcom,init-mode = ; }; }; @@ -668,18 +621,16 @@ qcom,resource-name = "ldoc5"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L5C: - pm6150l_l5: regulator-pm6150l-l5 { + L5C: pm6150l_l5: regulator-pm6150l-l5 { regulator-name = "pm6150l_l5"; qcom,set = ; regulator-min-microvolt = <1648000>; - regulator-max-microvolt = <3304000>; + regulator-max-microvolt = <2950000>; qcom,init-voltage = <1648000>; - qcom,init-mode = - ; + qcom,init-mode = ; }; }; @@ -689,18 +640,16 @@ qcom,resource-name = "ldoc6"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L6C: - pm6150l_l6: regulator-pm6150l-l6 { + L6C: pm6150l_l6: regulator-pm6150l-l6 { regulator-name = "pm6150l_l6"; qcom,set = ; - regulator-min-microvolt = <2696000>; - regulator-max-microvolt = <3304000>; - qcom,init-voltage = <2696000>; - qcom,init-mode = - ; + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3100000>; + qcom,init-voltage = <1648000>; + qcom,init-mode = ; }; }; @@ -710,18 +659,16 @@ qcom,resource-name = "ldoc7"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L7C: - pm6150l_l7: regulator-pm6150l-l7 { + L7C: pm6150l_l7: regulator-pm6150l-l7 { regulator-name = "pm6150l_l7"; qcom,set = ; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3312000>; qcom,init-voltage = <3000000>; - qcom,init-mode = - ; + qcom,init-mode = ; }; }; @@ -731,18 +678,16 @@ qcom,resource-name = "ldoc8"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L8C: - pm6150l_l8: regulator-pm6150l-l8 { + L8C: pm6150l_l8: regulator-pm6150l-l8 { regulator-name = "pm6150l_l8"; qcom,set = ; regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1904000>; + regulator-max-microvolt = <1900000>; qcom,init-voltage = <1800000>; - qcom,init-mode = - ; + qcom,init-mode = ; }; }; @@ -752,18 +697,16 @@ qcom,resource-name = "ldoc9"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L9C: - pm6150l_l9: regulator-pm6150l-l9 { + L9C: pm6150l_l9: regulator-pm6150l-l9 { regulator-name = "pm6150l_l9"; qcom,set = ; - regulator-min-microvolt = <2952000>; - regulator-max-microvolt = <3304000>; - qcom,init-voltage = <2952000>; - qcom,init-mode = - ; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <2950000>; + qcom,init-mode = ; }; }; @@ -773,18 +716,16 @@ qcom,resource-name = "ldoc10"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; - qcom,mode-threshold-currents = <0 1>; - L10C: - pm6150l_l10: regulator-pm6150l-l10 { + ; + qcom,mode-threshold-currents = <0 10000>; + L10C: pm6150l_l10: regulator-pm6150l-l10 { regulator-name = "pm6150l_l10"; qcom,set = ; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3400000>; - qcom,init-voltage = <3000000>; - qcom,init-mode = - ; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <3200000>; + qcom,init-mode = ; }; }; @@ -794,18 +735,16 @@ qcom,resource-name = "ldoc11"; qcom,regulator-type = "pmic5-ldo"; qcom,supported-modes = - ; + ; qcom,mode-threshold-currents = <0 1>; - L11C: - pm6150l_l11: regulator-pm6150l-l11 { + L11C: pm6150l_l11: regulator-pm6150l-l11 { regulator-name = "pm6150l_l11"; qcom,set = ; - regulator-min-microvolt = <3000000>; + regulator-min-microvolt = <2950000>; regulator-max-microvolt = <3400000>; - qcom,init-voltage = <3000000>; - qcom,init-mode = - ; + qcom,init-voltage = <2950000>; + qcom,init-mode = ; }; }; @@ -815,36 +754,134 @@ qcom,resource-name = "bobc1"; qcom,regulator-type = "pmic5-bob"; qcom,supported-modes = - ; - qcom,mode-threshold-currents = <0 1>; + ; + qcom,mode-threshold-currents = <0 1000000 2000000>; qcom,send-defaults; - BOB: - pm6150l_bob: regulator-pm6150l-bob { + + BOB: pm6150l_bob: regulator-pm6150l-bob { regulator-name = "pm6150l_bob"; qcom,set = ; - regulator-min-microvolt = <3008000>; + regulator-min-microvolt = <3296000>; regulator-max-microvolt = <3960000>; - qcom,init-voltage = <3008000>; - qcom,init-mode = - ; + qcom,init-voltage = <3296000>; + qcom,init-mode = ; }; - BOB_AO: - pm6150l_bob_ao: regulator-pm6150l-bob_ao { + BOB_AO: pm6150l_bob_ao: regulator-pm6150l-bob-ao { regulator-name = "pm6150l_bob_ao"; qcom,set = ; - regulator-min-microvolt = <3008000>; + regulator-min-microvolt = <3296000>; regulator-max-microvolt = <3960000>; - qcom,init-voltage = <3008000>; - qcom,init-mode = - ; + qcom,init-voltage = <3296000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldof1 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L1F: pm8009_l1: regulator-pm8009-l1 { + regulator-name = "pm8009_l1"; + qcom,set = ; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1100000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldof2 { + compatible = "qcom,rpmh-xob-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof2"; + L2F: pm8009_l2: regulator-pm8009-l2 { + regulator-name = "pm8009_l2"; + qcom,set = ; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + }; + + rpmh-regulator-ldof4 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L4F: pm8009_l4: regulator-pm8009-l4 { + regulator-name = "pm8009_l4"; + qcom,set = ; + regulator-min-microvolt = <1096000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1096000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldof5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L5F: pm8009_l5: regulator-pm8009-l5 { + regulator-name = "pm8009_l5"; + qcom,set = ; + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <2904000>; + qcom,init-voltage = <2696000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldof6 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L6F: pm8009_l6: regulator-pm8009-l6 { + regulator-name = "pm8009_l6"; + qcom,set = ; + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <2904000>; + qcom,init-voltage = <2696000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldof7 { + compatible = "qcom,rpmh-xob-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof7"; + L7F: pm8009_l7: regulator-pm8009-l7 { + regulator-name = "pm8009_l7"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; }; - refgen: refgen-regulator@88e7000 { + refgen: refgen-regulator@ff1000 { compatible = "qcom,refgen-regulator"; - reg = <0x88e7000 0x60>; + reg = <0xff1000 0x60>; regulator-name = "refgen"; regulator-enable-ramp-delay = <5>; proxy-supply = <&refgen>; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-rumi-overlay.dts b/arch/arm/boot/dts/qcom/sdmmagpie-rumi-overlay.dts new file mode 100644 index 000000000000..3fcb0dc3a2a6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-rumi-overlay.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "sdmmagpie-rumi.dtsi" + +/ { + model = "RUMI"; + compatible = "qcom,sdmmagpie-rumi", "qcom,sdmmagpie", "qcom,rumi"; + qcom,msm-id = <365 0x0>; + qcom,board-id = <15 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-rumi.dts b/arch/arm/boot/dts/qcom/sdmmagpie-rumi.dts new file mode 100644 index 000000000000..0534580ad2c6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-rumi.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdmmagpie.dtsi" +#include "sdmmagpie-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDMMAGPIE PM6150 RUMI"; + compatible = "qcom,sdmmagpie-rumi", "qcom,sdmmagpie", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-rumi.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-rumi.dtsi new file mode 100644 index 000000000000..9ea638381869 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-rumi.dtsi @@ -0,0 +1,192 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + usb_emu_phy: usb_emu_phy@a720000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x0a720000 0x9500>, + <0x0a6f8800 0x100>; + reg-names = "base", "qcratch_base"; + + qcom,emu-init-seq = <0xfff0 0x4 + 0xfff3 0x4 + 0x40 0x4 + 0xfff3 0x4 + 0xfff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x1a0 0x20 + 0x100000 0x3c + 0x0 0x3c + 0x10060 0x3c + 0x0 0x4>; + }; + + timer { + clock-frequency = <1000000>; + }; + + timer@0x17c00000 { + clock-frequency = <1000000>; + }; + + wdog: qcom,wdt@17c10000{ + status = "disabled"; + }; +}; + +&soc { + /delete-node/ rpmh-regulator-gfxlvl; + /delete-node/ rpmh-regulator-mxlvl; + /delete-node/ rpmh-regulator-cxlvl; + /delete-node/ rpmh-regulator-smpc1; + /delete-node/ rpmh-regulator-modemlvl; + /delete-node/ rpmh-regulator-smpc8; + /delete-node/ rpmh-regulator-ldoa1; + /delete-node/ rpmh-regulator-ldoa2; + /delete-node/ rpmh-regulator-ldoa3; + /delete-node/ rpmh-regulator-ldoa4; + /delete-node/ rpmh-regulator-ldoa5; + /delete-node/ rpmh-regulator-ldoa6; + /delete-node/ rpmh-regulator-lmxlvl; + /delete-node/ rpmh-regulator-lcxlvl; + /delete-node/ rpmh-regulator-ldoa9; + /delete-node/ rpmh-regulator-ldoa10; + /delete-node/ rpmh-regulator-ldoa11; + /delete-node/ rpmh-regulator-ldoa12; + /delete-node/ rpmh-regulator-ldoa13; + /delete-node/ rpmh-regulator-ldoa14; + /delete-node/ rpmh-regulator-ldoa15; + /delete-node/ rpmh-regulator-ldoa16; + /delete-node/ rpmh-regulator-ldoa17; + /delete-node/ rpmh-regulator-ldoa18; + /delete-node/ rpmh-regulator-ldoa19; + /delete-node/ rpmh-regulator-ldoc1; + /delete-node/ rpmh-regulator-ldoc2; + /delete-node/ rpmh-regulator-ldoc3; + /delete-node/ rpmh-regulator-ldoc4; + /delete-node/ rpmh-regulator-ldoc5; + /delete-node/ rpmh-regulator-ldoc6; + /delete-node/ rpmh-regulator-ldoc7; + /delete-node/ rpmh-regulator-ldoc8; + /delete-node/ rpmh-regulator-ldoc9; + /delete-node/ rpmh-regulator-ldoc10; + /delete-node/ rpmh-regulator-ldoc11; + /delete-node/ rpmh-regulator-bobc1; +}; + +&sdhc_1 { + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on + &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off + &sdc1_rclk_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000>; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + + /delete-property/qcom,devfreq,freq-table; + + status = "ok"; +}; + +&sdhc_2 { + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50"; + + /delete-property/qcom,devfreq,freq-table; + + status = "disabled"; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qrbtc-sdm845"; + + vdda-phy-supply = <&pm6150_l4>; /* 0.88v */ + vdda-pll-supply = <&pm6150l_l3>; /* 1.2v */ + vdda-phy-max-microamp = <62900>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + limit-tx-hs-gear = <1>; + limit-rx-hs-gear = <1>; + scsi-cmd-timeout = <300000>; + + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm6150_l19>; + vccq2-supply = <&pm6150_l12>; + vcc-max-microamp = <600000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm6150l_l3>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vddp-ref-clk-min-uV = <1200000>; + qcom,vddp-ref-clk-max-uV = <1200000>; + + qcom,disable-lpm; + rpm-level = <0>; + spm-level = <0>; + status = "ok"; +}; + + +&qupv3_se8_2uart { + status = "ok"; +}; + +&thermal_zones { + /delete-node/ aoss-0-lowf; + /delete-node/ cpu-0-0-lowf; + /delete-node/ cpu-1-0-lowf; + /delete-node/ gpuss-0-lowf; + /delete-node/ cwlan-lowf; + /delete-node/ audio-lowf; + /delete-node/ ddr-lowf; + /delete-node/ q6-hvx-lowf; + /delete-node/ camera-lowf; + /delete-node/ mdm-core-lowf; + /delete-node/ mdm-dsp-lowf; + /delete-node/ npu-lowf; + /delete-node/ video-lowf; +}; + +&usb0 { + /delete-property/ iommus; + /delete-property/ qcom,smmu-s1-bypass; + /delete-property/ USB3_GDSC-supply; + /delete-property/ extcon; + dwc3@a600000 { + usb-phy = <&usb_emu_phy>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + }; + qcom,usbbam@a704000 { + status = "disabled"; + }; +}; + +&qusb_phy0 { + status = "disabled"; +}; + +&usb_qmp_dp_phy { + status = "disabled"; +}; + +#include "sdmmagpie-stub-regulator.dtsi" diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-sde-display.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-sde-display.dtsi new file mode 100644 index 000000000000..4bbb187fa85b --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-sde-display.dtsi @@ -0,0 +1,742 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-sim-cmd.dtsi" +#include "dsi-panel-sim-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-video.dtsi" +#include "dsi-panel-sim-dualmipi-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" +#include "dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi" +#include "dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi" +#include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-sharp-dualdsi-wqhd-video.dtsi" +#include "dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi" +#include "dsi-panel-rm69298-truly-amoled-fhd-plus-video.dtsi" +#include "dsi-panel-rm69298-truly-amoled-fhd-plus-cmd.dtsi" +#include "dsi-panel-rm69299-visionox-amoled-fhd-plus-video.dtsi" +#include "dsi-panel-nt35695b-truly-fhd-video.dtsi" +#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi" +#include + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1904000>; + qcom,supply-enable-load = <32000>; + qcom,supply-disable-load = <80>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1904000>; + qcom,supply-enable-load = <32000>; + qcom,supply-disable-load = <80>; + }; + }; + + dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1904000>; + qcom,supply-enable-load = <32000>; + qcom,supply-disable-load = <80>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdda-3p3"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <13200>; + qcom,supply-disable-load = <80>; + }; + }; + + dsi_sw43404_amoled_video_display: qcom,dsi-display@0 { + label = "dsi_sw43404_amoled_video_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sw43404_amoled_video>; + }; + + dsi_sw43404_amoled_cmd_display: qcom,dsi-display@1 { + label = "dsi_sw43404_amoled_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sw43404_amoled_cmd>; + }; + + dsi_sw43404_amoled_fhd_plus_cmd_display: qcom,dsi-display@2 { + label = "dsi_sw43404_amoled_fhd_plus_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sw43404_amoled_fhd_plus_cmd>; + }; + + dsi_sim_vid_display: qcom,dsi-display@3 { + label = "dsi_sim_vid_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sim_vid>; + }; + + dsi_dual_sim_vid_display: qcom,dsi-display@4 { + label = "dsi_dual_sim_vid_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_dual_sim_vid>; + }; + + dsi_sim_cmd_display: qcom,dsi-display@5 { + label = "dsi_sim_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sim_cmd>; + }; + + dsi_dual_sim_cmd_display: qcom,dsi-display@6 { + label = "dsi_dual_sim_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_dual_sim_cmd>; + }; + + dsi_sim_dsc_375_cmd_display: qcom,dsi-display@7 { + label = "dsi_sim_dsc_375_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sim_dsc_375_cmd>; + }; + + dsi_dual_sim_dsc_375_cmd_display: qcom,dsi-display@8 { + label = "dsi_dual_sim_dsc_375_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_dual_sim_dsc_375_cmd>; + }; + + dsi_dual_sharp_wqhd_video_display: qcom,dsi-display@9 { + label = "dsi_dual_sharp_wqhd_video_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_dual_sharp_wqhd_video>; + }; + + dsi_dual_sharp_wqhd_cmd_display: qcom,dsi-display@10 { + label = "dsi_dual_sharp_wqhd_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_dual_sharp_wqhd_cmd>; + }; + + dsi_rm69298_truly_amoled_vid_display: qcom,dsi-display@11 { + label = "dsi_rm69298_truly_amoled_vid_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_rm69298_truly_amoled_video>; + }; + + dsi_rm69298_truly_amoled_cmd_display: qcom,dsi-display@12 { + label = "dsi_rm69298_truly_amoled_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_rm69298_truly_amoled_cmd>; + }; + + dsi_nt35695b_truly_fhd_video_display: qcom,dsi-display@13 { + label = "dsi_nt35695b_truly_fhd_video_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <1>; + qcom,dsi-phy-num = <1>; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_video>; + }; + + dsi_nt35695b_truly_fhd_cmd_display: qcom,dsi-display@14 { + label = "dsi_nt35695b_truly_fhd_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <1>; + qcom,dsi-phy-num = <1>; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_cmd>; + }; + + dsi_nt35695b_truly_fhd_video_sec_display: qcom,dsi-display@15 { + label = "dsi_nt35695b_truly_fhd_video_sec_display"; + qcom,display-type = "secondary"; + + qcom,dsi-ctrl-num = <1>; + qcom,dsi-phy-num = <1>; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_video>; + }; + + dsi_nt35695b_truly_fhd_cmd_sec_display: qcom,dsi-display@16 { + label = "dsi_nt35695b_truly_fhd_cmd_sec_display"; + qcom,display-type = "secondary"; + + qcom,dsi-ctrl-num = <1>; + qcom,dsi-phy-num = <1>; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_cmd>; + }; + + dsi_rm69299_visionox_amoled_vid_display: qcom,dsi-display@17 { + label = "dsi_rm69299_visionox_amoled_vid_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_rm69299_visionox_amoled_video>; + }; + + sde_dsi: qcom,dsi-display { + compatible = "qcom,dsi-display"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, + <&mdss_dsi0_pll PCLK_MUX_0_CLK>, + <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, + <&mdss_dsi1_pll PCLK_MUX_1_CLK>, + <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>, + <&mdss_dsi0_pll PCLK_SRC_0_CLK>, + <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>, + <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_te_active &disp_pins_default>; + pinctrl-1 = <&sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; + qcom,panel-te-source = <0>; + + vddio-supply = <&pm6150_l13>; + vdda-3p3-supply = <&pm6150_l18>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + + qcom,dsi-display-list = + <&dsi_sw43404_amoled_video_display + &dsi_sw43404_amoled_cmd_display + &dsi_sw43404_amoled_fhd_plus_cmd_display + &dsi_sim_vid_display + &dsi_dual_sim_vid_display + &dsi_sim_cmd_display + &dsi_dual_sim_cmd_display + &dsi_sim_dsc_375_cmd_display + &dsi_dual_sim_dsc_375_cmd_display + &dsi_dual_sharp_wqhd_video_display + &dsi_dual_sharp_wqhd_cmd_display + &dsi_rm69298_truly_amoled_vid_display + &dsi_rm69298_truly_amoled_cmd_display + &dsi_nt35695b_truly_fhd_video_display + &dsi_nt35695b_truly_fhd_cmd_display + &dsi_rm69299_visionox_amoled_vid_display>; + + }; + + sde_dsi1: qcom,dsi-display-secondary { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, + <&mdss_dsi0_pll PCLK_MUX_0_CLK>, + <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, + <&mdss_dsi1_pll PCLK_MUX_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_te1_active>; + pinctrl-1 = <&sde_te1_suspend>; + + qcom,platform-te-gpio = <&tlmm 11 0>; + qcom,panel-te-source = <1>; + + vddio-supply = <&pm6150_l13>; + vdda-3p3-supply = <&pm6150_l18>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + + qcom,dsi-display-list = + <&dsi_nt35695b_truly_fhd_video_sec_display + &dsi_nt35695b_truly_fhd_cmd_sec_display>; + }; + + sde_wb: qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display"; + }; +}; + +&sde_dp { + qcom,dp-usbpd-detection = <&pm6150_pdphy>; +}; + +&mdss_mdp { + connectors = <&sde_rscc &sde_wb &sde_dsi &sde_dp &sde_dsi1>; +}; + +&dsi_sw43404_amoled_video { + qcom,mdss-dsi-t-clk-post = <0x0A>; + qcom,mdss-dsi-t-clk-pre = <0x21>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-supported-dfps-list = <60 57 55>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp"; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1F 1E 05 + 05 03 02 04 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sw43404_amoled_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-t-clk-post = <0x0A>; + qcom,mdss-dsi-t-clk-pre = <0x21>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1F 1E 05 + 05 03 02 04 00]; + + qcom,mdss-mdp-transfer-time-us = <13000>; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 180 180 180 1440 180>; + }; + }; +}; + +&dsi_sw43404_amoled_fhd_plus_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-t-clk-post = <0x09>; + qcom,mdss-dsi-t-clk-pre = <0x1B>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 0F 03 03 1E 1D 04 + 04 02 03 04 00]; + qcom,mdss-dsi-panel-clockrate = <354585600>; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 270 270 270 1080 270>; + }; + }; +}; + +&dsi_dual_sharp_wqhd_video { + qcom,mdss-dsi-t-clk-post = <0x0c>; + qcom,mdss-dsi-t-clk-pre = <0x21>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-supported-dfps-list = <60 57 55>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp"; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = + <534712320 532484352 530256384 525800448 528028416>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 2e 08 0a 12 18 08 + 0b 09 03 04 00]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sharp_wqhd_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-t-clk-post = <0x0c>; + qcom,mdss-dsi-t-clk-pre = <0x21>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 2e 08 0a 12 18 08 + 0b 09 03 04 00]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 160 160 160 1440 160>; + }; + }; +}; + +&dsi_rm69298_truly_amoled_video { + qcom,mdss-dsi-t-clk-post = <0x0D>; + qcom,mdss-dsi-t-clk-pre = <0x30>; + qcom,dsi-supported-dfps-list = <60 57 53>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = + "dfps_immediate_porch_mode_vfp"; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1F 08 08 24 22 08 + 08 05 02 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_rm69298_truly_amoled_cmd { + qcom,mdss-dsi-t-clk-post = <0x0D>; + qcom,mdss-dsi-t-clk-pre = <0x30>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1F 08 08 24 22 08 + 08 05 02 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-t-clk-post = <0x0D>; + qcom,mdss-dsi-t-clk-pre = <0x2D>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 23 21 07 + 07 05 02 04 00]; + qcom,display-topology = <1 0 1>, + <2 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_vid { + qcom,mdss-dsi-t-clk-post = <0x0D>; + qcom,mdss-dsi-t-clk-pre = <0x2D>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 23 21 07 + 07 05 02 04 00]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-t-clk-post = <0x0C>; + qcom,mdss-dsi-t-clk-pre = <0x29>; + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07 + 07 04 02 04 00]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@1{ + qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07 + 07 04 02 04 00]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <540 40 540 40 540 40>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@2{ + qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07 + 07 04 02 04 00]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <360 40 360 40 360 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-t-clk-post = <0x0D>; + qcom,mdss-dsi-t-clk-pre = <0x2D>; + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09 + 09 06 02 04 00]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + timing@1{ + qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 23 21 07 + 07 05 02 04 00]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + timing@2{ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06 + 06 04 02 04 00]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-t-clk-post = <0x0D>; + qcom,mdss-dsi-t-clk-pre = <0x2D>; + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { /* 1080p */ + qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07 + 07 04 02 04 00]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + timing@1 { /* qhd */ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1F 05 + 05 03 02 04 00]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-t-clk-post = <0x0D>; + qcom,mdss-dsi-t-clk-pre = <0x2D>; + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { /* qhd */ + qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 23 21 07 + 07 05 02 04 00]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + timing@1 { /* 4k */ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06 + 06 04 02 04 00]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt35695b_truly_fhd_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-supported-dfps-list = <60 55 48>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,mdss-dsi-t-clk-post = <0x07>; + qcom,mdss-dsi-t-clk-pre = <0x1c>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1F 1E 05 + 05 03 02 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-t-clk-post = <0x07>; + qcom,mdss-dsi-t-clk-pre = <0x1c>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1F 1E 05 + 05 03 02 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_rm69299_visionox_amoled_video { + qcom,mdss-dsi-t-clk-post = <0x0E>; + qcom,mdss-dsi-t-clk-pre = <0x31>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 + 08 05 02 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll-sde-pll.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-sde-pll.dtsi similarity index 71% rename from arch/arm64/boot/dts/qcom/atoll-sde-pll.dtsi rename to arch/arm/boot/dts/qcom/sdmmagpie-sde-pll.dtsi index 9ecfc82d44a8..515cb56a5b7e 100644 --- a/arch/arm64/boot/dts/qcom/atoll-sde-pll.dtsi +++ b/arch/arm/boot/dts/qcom/sdmmagpie-sde-pll.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -25,6 +25,36 @@ clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; clock-names = "iface_clk"; clock-rate = <0>; + memory-region = <&dfps_data_memory>; + gdsc-supply = <&mdss_core_gdsc>; + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1_pll: qcom,mdss_dsi_pll@ae96a00 { + compatible = "qcom,mdss_dsi_pll_10nm"; + label = "MDSS DSI 1 PLL"; + cell-index = <1>; + #clock-cells = <1>; + reg = <0xae96a00 0x1e0>, + <0xae96400 0x800>, + <0xaf03000 0x8>, + <0xae96200 0x100>; + reg-names = "pll_base", "phy_base", "gdsc_base", + "dynamic_pll_base"; + clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + clock-rate = <0>; gdsc-supply = <&mdss_core_gdsc>; qcom,platform-supply-entries { #address-cells = <1>; @@ -41,7 +71,6 @@ }; mdss_dp_pll: qcom,mdss_dp_pll@ae90000 { - status = "disabled"; compatible = "qcom,mdss_dp_pll_10nm"; label = "MDSS DP PLL"; cell-index = <0>; @@ -78,6 +107,8 @@ qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; + }; }; + }; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-sde.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-sde.dtsi new file mode 100644 index 000000000000..ca96afac6846 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-sde.dtsi @@ -0,0 +1,690 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + compatible = "qcom,sde-kms"; + reg = <0x0ae00000 0x84208>, + <0x0aeb0000 0x2008>, + <0x0aeac000 0x214>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys"; + + clocks = + <&clock_gcc GCC_DISP_AHB_CLK>, + <&clock_gcc GCC_DISP_HF_AXI_CLK>, + <&clock_gcc GCC_DISP_SF_AXI_CLK>, + <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, + <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk", "rot_clk"; + clock-rate = <0 0 0 0 300000000 19200000 200000000 + 200000000>; + clock-max-rate = <0 0 0 0 430000000 19200000 430000000 + 430000000>; + qcom,dss-cx-ipeak = <&cx_ipeak_lm 4>; + + /* interrupt config */ + interrupts = <0 83 0>; + interrupt-controller; + #interrupt-cells = <1>; + iommus = <&apps_smmu 0x800 0x440>; + + #address-cells = <1>; + #size-cells = <0>; + + #power-domain-cells = <0>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x45c>; + + qcom,sde-ctl-off = <0x2000 0x2200 0x2400 + 0x2600 0x2800 0x2a00>; + qcom,sde-ctl-size = <0x1e0>; + qcom,sde-ctl-display-pref = "primary", "none", "none", + "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 + 0x48000 0x0 0x0>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none", "none", "none"; + + qcom,sde-mixer-cwb-pref = "none", "none", "cwb", + "cwb", "none", "none"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000 0x57000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dest-scaler-top-off = <0x00061000>; + qcom,sde-dest-scaler-top-size = <0x1c>; + qcom,sde-dest-scaler-off = <0x800 0x1000>; + qcom,sde-dest-scaler-size = <0xa0>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x3b8 24>; + + qcom,sde-intf-off = <0x6b000 0x6b800 + 0x6c000 0x6c800>; + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + + qcom,sde-pp-off = <0x71000 0x71800 + 0x72000 0x72800>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0>; + qcom,sde-pp-size = <0xd4>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1>; + + qcom,sde-merge-3d-off = <0x84000 0x84100>; + qcom,sde-merge-3d-size = <0x100>; + + qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + qcom,sde-dsc-off = <0x81000 0x81400>; + qcom,sde-dsc-size = <0x140>; + + qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "vig", "dma", "dma", "dma"; + + qcom,sde-sspp-off = <0x5000 0x7000 0x25000 0x27000 + 0x29000>; + qcom,sde-sspp-src-size = <0x1f0>; + + qcom,sde-sspp-xin-id = <0 4 1 5 9>; + qcom,sde-sspp-excl-rect = <1 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <4 5 1 2 3>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3 0 0>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-max-per-pipe-bw-kbps = <4500000 + 4500000 4500000 + 4500000 4500000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x2ac 0>, <0x2b4 0>, <0x2ac 8>, <0x2b4 8>, + <0x2bc 8>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-type = "qseedv3lite"; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <2880>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-mixer-blendstages = <0xb>; + qcom,sde-highest-bank-bit = <0x1>; + qcom,sde-ubwc-version = <0x200>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-idle-pc; + qcom,sde-has-dest-scaler; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-max-bw-low-kbps = <12800000>; + qcom,sde-max-bw-high-kbps = <12800000>; + qcom,sde-min-core-ib-kbps = <2400000>; + qcom,sde-min-llcc-ib-kbps = <800000>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + qcom,sde-dspp-ad-version = <0x00040000>; + qcom,sde-dspp-ad-off = <0x28000 0x27000>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1040>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + + /* macrotile & macrotile-qseed has the same configs */ + qcom,sde-danger-lut = <0x0000000f 0x0000ffff + 0x00000000 0x00000000 0x0000ffff>; + + qcom,sde-safe-lut-linear = <0 0xfff8>; + qcom,sde-safe-lut-macrotile = <0 0xf000>; + /* same as safe-lut-macrotile */ + qcom,sde-safe-lut-macrotile-qseed = <0 0xf000>; + qcom,sde-safe-lut-nrt = <0 0xffff>; + qcom,sde-safe-lut-cwb = <0 0xffff>; + + qcom,sde-qos-lut-linear = <0 0x00112222 0x22223357>; + qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>; + qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>; + qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>; + qcom,sde-qos-lut-cwb = <0 0x75300000 0x00000000>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + + qcom,sde-reg-dma-off = <0>; + qcom,sde-reg-dma-version = <0x00010001>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + + qcom,sde-secure-sid-mask = <0x4400801>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + qcom,sde-vig-gamut = <0x1d00 0x00050000>; + qcom,sde-vig-igc = <0x1d00 0x00050000>; + qcom,sde-vig-inverse-pma; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + qcom,sde-dma-igc = <0x400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x200>; + }; + dgm@1 { + qcom,sde-dma-igc = <0x1400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1200>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040001>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x801 0x440>; + }; + + /* data and reg bus scale settings */ + qcom,sde-data-bus { + qcom,msm-bus,name = "mdss_sde"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, <23 512 0 0>, + <22 512 0 6400000>, <23 512 0 6400000>, + <22 512 0 6400000>, <23 512 0 6400000>; + }; + + qcom,sde-reg-bus { + qcom,msm-bus,name = "mdss_reg"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 590 0 0>, + <1 590 0 76800>, + <1 590 0 150000>, + <1 590 0 300000>; + }; + }; + + sde_rscc: qcom,sde_rscc@af20000 { + cell-index = <0>; + compatible = "qcom,sde-rsc"; + reg = <0xaf20000 0x1c44>, + <0xaf30000 0x3fd4>; + reg-names = "drv", "wrapper"; + qcom,sde-rsc-version = <2>; + + vdd-supply = <&mdss_core_gdsc>; + clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, + <&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; + clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; + clock-rate = <0 0 0>; + + qcom,sde-dram-channels = <2>; + + mboxes = <&disp_rsc 0>; + mbox-names = "disp_rsc"; + + /* data and reg bus scale settings */ + qcom,sde-data-bus { + qcom,msm-bus,name = "disp_rsc_mnoc"; + qcom,msm-bus,active-only; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <20003 20515 0 0>, <20004 20515 0 0>, + <20003 20515 0 6400000>, <20004 20515 0 6400000>, + <20003 20515 0 6400000>, <20004 20515 0 6400000>; + }; + + qcom,sde-llcc-bus { + qcom,msm-bus,name = "disp_rsc_llcc"; + qcom,msm-bus,active-only; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <20001 20513 0 0>, + <20001 20513 0 6400000>, + <20001 20513 0 6400000>; + }; + + qcom,sde-ebi-bus { + qcom,msm-bus,name = "disp_rsc_ebi"; + qcom,msm-bus,active-only; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <20000 20512 0 0>, + <20000 20512 0 6400000>, + <20000 20512 0 6400000>; + }; + }; + + mdss_rotator: qcom,mdss_rotator@ae00000 { + compatible = "qcom,sde_rotator"; + reg = <0x0ae00000 0xac000>, + <0x0aeb8000 0x3000>; + reg-names = "mdp_phys", + "rot_vbif_phys"; + + #list-cells = <1>; + + qcom,mdss-rot-mode = <1>; + qcom,mdss-highest-bank-bit = <0x1>; + + /* Bus Scale Settings */ + qcom,msm-bus,name = "mdss_rotator"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <25 512 0 0>, + <25 512 0 6400000>, + <25 512 0 6400000>; + + rot-vdd-supply = <&mdss_core_gdsc>; + qcom,supply-names = "rot-vdd"; + + clocks = + <&clock_gcc GCC_DISP_AHB_CLK>, + <&clock_gcc GCC_DISP_SF_AXI_CLK>, + <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", + "iface_clk", "rot_clk"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <2 0>; + + power-domains = <&mdss_mdp>; + + /* Offline rotator QoS setting */ + qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>; + qcom,mdss-rot-vbif-memtype = <3 3>; + qcom,mdss-rot-cdp-setting = <1 1>; + qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>; + qcom,mdss-rot-danger-lut = <0x0 0x0>; + qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>; + + qcom,mdss-rot-qos-cpu-mask = <0xf>; + qcom,mdss-rot-qos-cpu-dma-latency = <75>; + + qcom,mdss-default-ot-rd-limit = <32>; + qcom,mdss-default-ot-wr-limit = <32>; + + qcom,mdss-sbuf-headroom = <20>; + + cache-slice-names = "rotator"; + cache-slices = <&llcc 4>; + + /* reg bus scale settings */ + rot_reg: qcom,rot-reg-bus { + qcom,msm-bus,name = "mdss_rot_reg"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 590 0 0>, + <1 590 0 76800>; + }; + + smmu_rot_unsec: qcom,smmu_rot_unsec_cb { + compatible = "qcom,smmu_sde_rot_unsec"; + iommus = <&apps_smmu 0x1020 0x0>; + }; + + smmu_rot_sec: qcom,smmu_rot_sec_cb { + compatible = "qcom,smmu_sde_rot_sec"; + iommus = <&apps_smmu 0x1021 0x0>; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.3"; + label = "dsi-ctrl-0"; + cell-index = <0>; + reg = <0xae94000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + vdda-1p2-supply = <&pm6150l_l3>; + clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", + "esc_clk"; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1144000>; + qcom,supply-max-voltage = <1232000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.3"; + label = "dsi-ctrl-1"; + cell-index = <1>; + reg = <0xae96000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <5 0>; + vdda-1p2-supply = <&pm6150l_l3>; + clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", + "esc_clk"; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1144000>; + qcom,supply-max-voltage = <1232000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 { + compatible = "qcom,dsi-phy-v3.0"; + label = "dsi-phy-0"; + cell-index = <0>; + reg = <0xae94400 0x7c0>, + <0xae94200 0x100>; + reg-names = "dsi_phy", "dyn_refresh_base"; + vdda-0p9-supply = <&pm6150_l4>; + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 80]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <824000>; + qcom,supply-max-voltage = <920000>; + qcom,supply-enable-load = <36000>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96400 { + compatible = "qcom,dsi-phy-v3.0"; + label = "dsi-phy-1"; + cell-index = <1>; + reg = <0xae96400 0x7c0>, + <0xae96200 0x100>; + reg-names = "dsi_phy", "dyn_refresh_base"; + vdda-0p9-supply = <&pm6150_l4>; + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 80]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <824000>; + qcom,supply-max-voltage = <920000>; + qcom,supply-enable-load = <36000>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + sde_dp: qcom,dp_display@0{ + cell-index = <0>; + compatible = "qcom,dp-display"; + + vdda-1p2-supply = <&pm6150l_l3>; + vdda-0p9-supply = <&pm6150_l4>; + + reg = <0xae90000 0x0dc>, + <0xae90200 0x0c0>, + <0xae90400 0x508>, + <0xae90a00 0x094>, + <0x88eaa00 0x200>, + <0x88ea200 0x200>, + <0x88ea600 0x200>, + <0xaf02000 0x1e0>, + <0x780000 0x621c>, + <0x88ea030 0x10>, + <0x88e8000 0x20>, + <0x0aee1000 0x034>, + <0xae91000 0x094>; + /* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */ + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_mmss_cc", "qfprom_physical", "dp_pll", + "usb3_dp_com", "hdcp_physical", "dp_p1"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, + <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + clock-names = "core_aux_clk", "core_usb_ahb_clk", + "core_usb_ref_clk_src", + "core_usb_ref_clk", "core_usb_pipe_clk", + "link_clk", "link_iface_clk", + "crypto_clk", "pixel_clk_rcg", "pixel_parent", + "pixel1_clk_rcg", "pixel1_parent", + "strm0_pixel_clk", "strm1_pixel_clk"; + + qcom,aux-cfg0-settings = [20 00]; + qcom,aux-cfg1-settings = [24 13 23 1d]; + qcom,aux-cfg2-settings = [28 24]; + qcom,aux-cfg3-settings = [2c 00]; + qcom,aux-cfg4-settings = [30 0a]; + qcom,aux-cfg5-settings = [34 26]; + qcom,aux-cfg6-settings = [38 0a]; + qcom,aux-cfg7-settings = [3c 03]; + qcom,aux-cfg8-settings = [40 bb]; + qcom,aux-cfg9-settings = [44 03]; + + qcom,max-pclk-frequency-khz = <675000>; + + qcom,ext-disp = <&ext_disp>; + + qcom,usbplug-cc-gpio = <&tlmm 104 0>; + + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; + pinctrl-0 = <&sde_dp_usbplug_cc_active>; + pinctrl-1 = <&sde_dp_usbplug_cc_suspend>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1144000>; + qcom,supply-max-voltage = <1232000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <824000>; + qcom,supply-max-voltage = <920000>; + qcom,supply-enable-load = <36000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-stub-regulator.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-stub-regulator.dtsi new file mode 100644 index 000000000000..368685e6d1be --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-stub-regulator.dtsi @@ -0,0 +1,352 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +/* TODO: Update volatge range once PGA is locked */ +/* Stub regulators */ + +/ { + /* PM6150 S2 = VDD_GFX supply */ + VDD_GFX_LEVEL: + pm6150_s2_level: regulator-pm6150-s2-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_s2_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + /* pm6150 S3 = VDD_MX supply */ + VDD_MX_LEVEL: + S3A_LEVEL: pm6150_s3_level: regulator-pm6150-s3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_s3_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + VDD_MX_LEVEL_AO: + S3A_LEVEL_AO: pm6150_s3_level_ao: regulator-pm6150-s3-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_s3_level_ao"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + S1C: pm6150l_s1: regulator-pm6150l-s1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_s1"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + }; + + /* pm6150l S2 + S3 = 2 phase VDD_CX supply */ + VDD_CX_LEVEL: + pm6150l_s2_level: regulator-pm6150l-s2-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_s2_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + VDD_CX_LEVEL_AO: + pm6150l_s2_level_ao: regulator-pm6150l-s2-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_s2_level_ao"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + /* pm6150l S7 = VDD_MSS supply */ + VDD_MSS_LEVEL: + S7C_LEVEL: pm6150l_s7_level: regulator-pm6150l-s7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_s7_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + S8C: pm6150l_s8: regulator-pm6150l-s8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_s8"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + }; + + L1A: pm6150_l1: regulator-pm6150-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1174000>; + regulator-max-microvolt = <1252000>; + }; + + L2A: pm6150_l2: regulator-pm6150-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <944000>; + regulator-max-microvolt = <1050000>; + }; + + L3A: pm6150_l3: regulator-pm6150-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <968000>; + regulator-max-microvolt = <1060000>; + }; + + L4A: pm6150_l4: regulator-pm6150-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <920000>; + }; + + L5A: pm6150_l5: regulator-pm6150-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2800000>; + }; + + L6A: pm6150_l6: regulator-pm6150-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1096000>; + regulator-max-microvolt = <1304000>; + }; + + /* pm6150 L7 = LPI_MX supply */ + LPI_MX_LEVEL: + L7A_LEVEL: pm6150_l7_level: regulator-pm6150-l7-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l7_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + /* pm6150 L8 = LPI_CX supply */ + LPI_CX_LEVEL: + L8A_LEVEL: pm6150_l8_level: regulator-pm6150-l8-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l8_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + /* pm6150 L9 = WCSS_CX supply */ + WCSS_CX: + L9A: pm6150_l9: regulator-pm6150-l9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <624000>; + regulator-max-microvolt = <760000>; + }; + + L10A: pm6150_l10: regulator-pm6150-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l10"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1720000>; + regulator-max-microvolt = <1832000>; + }; + + L11A: pm6150_l11: regulator-pm6150-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l11"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1616000>; + regulator-max-microvolt = <1984000>; + }; + + L12A: pm6150_l12: regulator-pm6150-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l12"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1952000>; + }; + + L13A: pm6150_l13: regulator-pm6150-l13 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l13"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1904000>; + }; + + L14A: pm6150_l14: regulator-pm6150-l14 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l14"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1720000>; + regulator-max-microvolt = <1856000>; + }; + + L15A: pm6150_l15: regulator-pm6150-l15 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l15"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1904000>; + }; + + L16A: pm6150_l16: regulator-pm6150-l16 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l16"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2424000>; + regulator-max-microvolt = <2976000>; + }; + + L17A: pm6150_l17: regulator-pm6150-l17 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l17"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3232000>; + }; + + L18A: pm6150_l18: regulator-pm6150-l18 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l18"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3008000>; + }; + + L19A: pm6150_l19: regulator-pm6150-l19 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l19"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <3304000>; + }; + + L1C: pm6150l_l1: regulator-pm6150l-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1616000>; + regulator-max-microvolt = <1984000>; + }; + + L2C: pm6150l_l2: regulator-pm6150l-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1352000>; + }; + + L3C: pm6150l_l3: regulator-pm6150l-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1256000>; + }; + + L4C: pm6150l_l4: regulator-pm6150l-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2950000>; + }; + + L5C: pm6150l_l5: regulator-pm6150l-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2950000>; + }; + + L6C: pm6150l_l6: regulator-pm6150l-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l6"; + qcom,hpm-min-load = <5000>; + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3100000>; + }; + + L7C: pm6150l_l7: regulator-pm6150l-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + }; + + L8C: pm6150l_l8: regulator-pm6150l-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + L9C: pm6150l_l9: regulator-pm6150l-l9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + }; + + L10C: pm6150l_l10: regulator-pm6150l-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l10"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3312000>; + }; + + L11C: pm6150l_l11: regulator-pm6150l-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l11"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3400000>; + }; + + BOB: pm6150l_bob: regulator-pm6150l-bob { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_bob"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + }; + + BOB_AO: pm6150l_bob_ao: regulator-pm6150l-bob-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_bob_ao"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-thermal-overlay.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-thermal-overlay.dtsi new file mode 100644 index 000000000000..f47d16937319 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-thermal-overlay.dtsi @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include + +&thermal_zones { + pm6150-tz { + cooling-maps { + trip0_bat { + trip = <&pm6150_trip0>; + cooling-device = + <&pm6150_charger (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip1_bat { + trip = <&pm6150_trip1>; + cooling-device = + <&pm6150_charger THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm6150l-tz { + cooling-maps { + trip0_cpu0 { + trip = <&pm6150l_trip0>; + cooling-device = + <&CPU0 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu1 { + trip = <&pm6150l_trip0>; + cooling-device = + <&CPU1 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu2 { + trip = <&pm6150l_trip0>; + cooling-device = + <&CPU2 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu3 { + trip = <&pm6150l_trip0>; + cooling-device = + <&CPU3 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu4 { + trip = <&pm6150l_trip0>; + cooling-device = + <&CPU4 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu5 { + trip = <&pm6150l_trip0>; + cooling-device = + <&CPU5 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu6 { + trip = <&pm6150l_trip0>; + cooling-device = + <&CPU6 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu7 { + trip = <&pm6150l_trip0>; + cooling-device = + <&CPU7 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip1_cpu1 { + trip = <&pm6150l_trip1>; + cooling-device = + <&CPU1 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu2 { + trip = <&pm6150l_trip1>; + cooling-device = + <&CPU2 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu3 { + trip = <&pm6150l_trip1>; + cooling-device = + <&CPU3 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu4 { + trip = <&pm6150l_trip1>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu5 { + trip = <&pm6150l_trip1>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu6 { + trip = <&pm6150l_trip1>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu7 { + trip = <&pm6150l_trip1>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm6150-vbat-lvl0 { + cooling-maps { + vbat_cpu6 { + trip = <&vbat_lvl0>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + vbat_cpu7 { + trip = <&vbat_lvl0>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm6150-ibat-lvl0 { + cooling-maps { + ibat_cpu6 { + trip = <&ibat_lvl0>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + ibat_cpu7 { + trip = <&ibat_lvl0>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + soc { + cooling-maps { + soc_cpu6 { + trip = <&soc_trip>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + soc_cpu7 { + trip = <&soc_trip>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; +}; + +&mdss_mdp { + #cooling-cells = <2>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-thermal.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-thermal.dtsi new file mode 100644 index 000000000000..d426faa62bce --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-thermal.dtsi @@ -0,0 +1,1912 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&clock_cpucc { + #address-cells = <1>; + #size-cells = <1>; + lmh_dcvs0: qcom,limits-dcvs@18358800 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + qcom,affinity = <0>; + reg = <0x18358800 0x1000>, + <0x18323000 0x1000>; + #thermal-sensor-cells = <0>; + }; + + lmh_dcvs1: qcom,limits-dcvs@18350800 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + qcom,affinity = <1>; + reg = <0x18350800 0x1000>, + <0x18325800 0x1000>; + #thermal-sensor-cells = <0>; + }; +}; + +&soc { + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + modem { + qcom,instance-id = <0x0>; + + modem_pa: modem_pa { + qcom,qmi-dev-name = "pa"; + #cooling-cells = <2>; + }; + + modem_proc: modem_proc { + qcom,qmi-dev-name = "modem"; + #cooling-cells = <2>; + }; + + modem_current: modem_current { + qcom,qmi-dev-name = "modem_current"; + #cooling-cells = <2>; + }; + + modem_skin: modem_skin { + qcom,qmi-dev-name = "modem_skin"; + #cooling-cells = <2>; + }; + + modem_vdd: modem_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + + adsp { + qcom,instance-id = <0x1>; + + adsp_vdd: adsp_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + + cdsp { + qcom,instance-id = <0x43>; + + cdsp_vdd: cdsp_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + }; + + cxip_cdev: cxip-cdev@1fed000 { + compatible = "qcom,cxip-lm-cooling-device"; + reg = <0x1fed000 0x8004>; + qcom,thermal-client-offset = <0x8000>; + qcom,bypass-client-list = <0x3004>; + #cooling-cells = <2>; + }; +}; + +&thermal_zones { + aoss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 0>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 1>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 3>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-4-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-5-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 0>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cwlan-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 1>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + audio-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 2>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + ddr-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + q6-hvx-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 5>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-core-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 6>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-dsp-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 7>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + npu-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + video-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 9>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + xo-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6150_adc_tm ADC_XO_THERM_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + rf-pa0-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6150_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + rf-pa1-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6150_adc_tm ADC_AMUX_THM3_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6150_adc_tm ADC_AMUX_THM4_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6150l_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + camera-ftherm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6150l_adc_tm ADC_AMUX_THM3_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + nvm-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6150l_adc_tm ADC_GPIO4_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + lmh-dcvs-00 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&lmh_dcvs0>; + wake-capable-sensor; + + trips { + active-config { + temperature = <95000>; + hysteresis = <30000>; + type = "passive"; + }; + }; + }; + + lmh-dcvs-01 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&lmh_dcvs1>; + wake-capable-sensor; + + trips { + active-config { + temperature = <95000>; + hysteresis = <30000>; + type = "passive"; + }; + }; + }; + + gpuss-max-step { + polling-delay-passive = <10>; + polling-delay = <100>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + gpu_trip: gpu-trip { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + }; + cooling-maps { + gpu_cdev { + trip = <&gpu_trip>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-0-max-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + silver-trip { + temperature = <120000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + cpu-1-max-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + gold-trip { + temperature = <120000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + cpu-0-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 1>; + wake-capable-sensor; + trips { + cpu0_config: cpu0-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&cpu0_config>; + cooling-device = + <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-0-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 2>; + wake-capable-sensor; + trips { + cpu1_config: cpu1-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu1_cdev { + trip = <&cpu1_config>; + cooling-device = + <&CPU1 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-0-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 3>; + wake-capable-sensor; + trips { + cpu2_config: cpu2-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu2_cdev { + trip = <&cpu2_config>; + cooling-device = + <&CPU2 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-0-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 4>; + wake-capable-sensor; + trips { + cpu3_config: cpu3-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu3_cdev { + trip = <&cpu3_config>; + cooling-device = + <&CPU3 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-0-4-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 5>; + wake-capable-sensor; + trips { + cpu4_config: cpu4-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu4_cdev { + trip = <&cpu4_config>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-0-5-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 6>; + wake-capable-sensor; + trips { + cpu5_config: cpu5-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu5_cdev { + trip = <&cpu5_config>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 9>; + wake-capable-sensor; + trips { + cpu6_0_config: cpu6-0-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu6_cdev { + trip = <&cpu6_0_config>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 10>; + wake-capable-sensor; + trips { + cpu6_1_config: cpu6-1-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu6_cdev { + trip = <&cpu6_1_config>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 11>; + wake-capable-sensor; + trips { + cpu7_0_config: cpu7-0-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu7_cdev { + trip = <&cpu7_0_config>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 12>; + wake-capable-sensor; + trips { + cpu7_1_config: cpu7-1-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu7_cdev { + trip = <&cpu7_1_config>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + aoss-0-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 0>; + wake-capable-sensor; + tracks-low; + trips { + aoss0_trip: aoss0-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&aoss0_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&aoss0_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + cpu-0-0-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 1>; + wake-capable-sensor; + tracks-low; + trips { + cpu_0_0_trip: cpu-0-0-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&cpu_0_0_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&cpu_0_0_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&cpu_0_0_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&cpu_0_0_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&cpu_0_0_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&cpu_0_0_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&cpu_0_0_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&cpu_0_0_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + cpu-1-0-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 9>; + wake-capable-sensor; + tracks-low; + trips { + cpu_1_0_trip: cpu-1-0-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&cpu_1_0_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&cpu_1_0_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&cpu_1_0_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&cpu_1_0_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&cpu_1_0_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&cpu_1_0_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&cpu_1_0_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&cpu_1_0_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + gpuss-0-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 13>; + wake-capable-sensor; + tracks-low; + trips { + gpuss_0_trip: gpuss-0-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&gpuss_0_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&gpuss_0_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&gpuss_0_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&gpuss_0_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&gpuss_0_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&gpuss_0_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&gpuss_0_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&gpuss_0_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + cwlan-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens1 1>; + wake-capable-sensor; + tracks-low; + trips { + cwlan_trip: cwlan-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&cwlan_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&cwlan_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&cwlan_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&cwlan_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&cwlan_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&cwlan_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&cwlan_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&cwlan_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + audio-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens1 2>; + wake-capable-sensor; + tracks-low; + trips { + audio_trip: audio-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&audio_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&audio_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&audio_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&audio_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&audio_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&audio_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&audio_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&audio_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + ddr-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens1 3>; + wake-capable-sensor; + tracks-low; + trips { + ddr_trip: ddr-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&ddr_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&ddr_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&ddr_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&ddr_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&ddr_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&ddr_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&ddr_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&ddr_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + q6-hvx-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens1 4>; + wake-capable-sensor; + tracks-low; + trips { + q6_hvx_trip: q6-hvx-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&q6_hvx_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&q6_hvx_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&q6_hvx_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&q6_hvx_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&q6_hvx_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&q6_hvx_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&q6_hvx_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&q6_hvx_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + camera-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens1 5>; + wake-capable-sensor; + tracks-low; + trips { + camera_trip: camera-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&camera_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&camera_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + mdm-core-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens1 6>; + wake-capable-sensor; + tracks-low; + trips { + mdm_core_trip: mdm-core-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + mdm-dsp-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens1 7>; + wake-capable-sensor; + tracks-low; + trips { + mdm_dsp_trip: mdm-dsp-lowf-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&mdm_dsp_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&mdm_dsp_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&mdm_dsp_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&mdm_dsp_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&mdm_dsp_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&mdm_dsp_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&mdm_dsp_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&mdm_dsp_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + npu-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens1 8>; + wake-capable-sensor; + tracks-low; + trips { + npu_trip: npu-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&npu_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&npu_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&npu_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&npu_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&npu_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&npu_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&npu_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&npu_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + video-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens1 9>; + wake-capable-sensor; + tracks-low; + trips { + video_trip: video-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&video_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&video_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&video_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&video_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&video_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&video_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&video_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&video_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + npu-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + npu_trip0: npu-trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + }; + cooling-maps { + npu_cdev { + trip = <&npu_trip0>; + cooling-device = + <&msm_npu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + q6-hvx-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + q6_hvx_trip0: q6-hvx-trip0 { + temperature = <95000>; + hysteresis = <20000>; + type = "passive"; + }; + + q6_hvx_trip1: q6-hvx-trip1 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + q6_hvx_trip2: q6-hvx-trip2 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cxip-cdev { + trip = <&q6_hvx_trip0>; + cooling-device = <&cxip_cdev 1 1>; + }; + + cdsp-cdev0 { + trip = <&q6_hvx_trip1>; + cooling-device = <&msm_cdsp_rm + THERMAL_NO_LIMIT 4>; + }; + + cdsp-cdev1 { + trip = <&q6_hvx_trip2>; + cooling-device = <&msm_cdsp_rm 4 4>; + }; + }; + }; + + quiet-therm-step { + polling-delay-passive = <1000>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6150_adc_tm ADC_AMUX_THM4_PU2>; + wake-capable-sensor; + trips { + batt_trip0: batt-trip0 { + temperature = <43000>; + hysteresis = <4000>; + type = "passive"; + }; + batt_trip1: batt-trip1 { + temperature = <45000>; + hysteresis = <2000>; + type = "passive"; + }; + batt_trip2: batt-trip2 { + temperature = <47000>; + hysteresis = <2000>; + type = "passive"; + }; + modem_trip0: modem-trip0 { + temperature = <48000>; + hysteresis = <4000>; + type = "passive"; + }; + batt_trip3: batt-trip3 { + temperature = <49000>; + hysteresis = <2000>; + type = "passive"; + }; + modem_trip1_hvx_trip: modem-trip1-hvx-trip { + temperature = <50000>; + hysteresis = <2000>; + type = "passive"; + }; + gold_trip: gold-trip { + temperature = <50000>; + hysteresis = <0>; + type = "passive"; + }; + batt_trip4: batt-trip4 { + temperature = <51000>; + hysteresis = <2000>; + type = "passive"; + }; + skin_gpu_trip: skin-gpu-trip { + temperature = <52000>; + hysteresis = <4000>; + type = "passive"; + }; + modem_trip2: modem-trip2 { + temperature = <52000>; + hysteresis = <2000>; + type = "passive"; + }; + silver_trip: silver-trip { + temperature = <54000>; + hysteresis = <0>; + type = "passive"; + }; + modem_trip3: modem-trip3 { + temperature = <58000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + + cooling-maps { + skin_cpu6 { + trip = <&gold_trip>; + cooling-device = + /* throttle from fmax to 1708800KHz */ + <&CPU6 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-9)>; + }; + skin_cpu7 { + trip = <&gold_trip>; + cooling-device = + <&CPU7 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-9)>; + }; + skin_cpu0 { + trip = <&silver_trip>; + /* throttle from fmax to 1497600KHz */ + cooling-device = <&CPU0 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-7)>; + }; + skin_cpu1 { + trip = <&silver_trip>; + cooling-device = <&CPU1 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-7)>; + }; + skin_cpu2 { + trip = <&silver_trip>; + cooling-device = <&CPU2 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-7)>; + }; + skin_cpu3 { + trip = <&silver_trip>; + cooling-device = <&CPU3 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-7)>; + }; + skin_cpu4 { + trip = <&silver_trip>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-7)>; + }; + skin_cpu5 { + trip = <&silver_trip>; + cooling-device = <&CPU5 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-7)>; + }; + skin_gpu { + trip = <&skin_gpu_trip>; + /* throttle from fmax to 650000000 Hz */ + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + modem_lvl1 { + trip = <&modem_trip1_hvx_trip>; + cooling-device = <&modem_pa 1 1>; + }; + modem_lvl2 { + trip = <&modem_trip2>; + cooling-device = <&modem_pa 2 2>; + }; + modem_lvl3 { + trip = <&modem_trip3>; + cooling-device = <&modem_pa 3 3>; + }; + modem_proc_lvl1 { + trip = <&modem_trip0>; + cooling-device = <&modem_proc 1 1>; + }; + modem_proc_lvl3 { + trip = <&modem_trip3>; + cooling-device = <&modem_proc 3 3>; + }; + cdsp_cdev1 { + trip = <&modem_trip1_hvx_trip>; + cooling-device = <&msm_cdsp_rm 4 4>; + }; + battery_lvl0 { + trip = <&batt_trip0>; + cooling-device = <&pm6150_charger 1 1>; + }; + battery_lvl1 { + trip = <&batt_trip1>; + cooling-device = <&pm6150_charger 2 2>; + }; + battery_lvl2 { + trip = <&batt_trip2>; + cooling-device = <&pm6150_charger 4 4>; + }; + battery_lvl3 { + trip = <&batt_trip3>; + cooling-device = <&pm6150_charger 5 5>; + }; + battery_lvl4 { + trip = <&batt_trip4>; + cooling-device = <&pm6150_charger 6 6>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-usb.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-usb.dtsi new file mode 100644 index 000000000000..367be23a8c81 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-usb.dtsi @@ -0,0 +1,375 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&soc { + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a600000 0x100000>; + reg-names = "core_base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <0 489 0>, <0 130 0>, <0 486 0>, <0 488 0>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + USB3_GDSC-supply = <&usb30_prim_gdsc>; + dpdm-supply = <&qusb_phy0>; + qcom,use-pdc-interrupts; + + clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>, + <&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&clock_gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <133333333>; + qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + qcom,pm-qos-latency = <62>; + + qcom,msm-bus,name = "usb0"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <3>; + qcom,msm-bus,vectors-KBps = + /* suspend vote */ + , + , + , + + /* nominal vote */ + , + , + , + + /* svs vote */ + , + , + , + + /* min vote */ + , + , + ; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0x0a600000 0xcd00>; + interrupts = <0 133 0>; + usb-phy = <&qusb_phy0>, <&usb_qmp_dp_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + usb-core-id = <0>; + tx-fifo-resize; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + + qcom,usbbam@a704000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa704000 0x17000>; + interrupts = <0 132 0>; + + qcom,usb-bam-fifo-baseaddr = <0x146a6000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + /* Primary USB port related QUSB2 PHY */ + qusb_phy0: qusb@88e2000 { + compatible = "qcom,qusb2phy-v2"; + reg = <0x088e2000 0x400>, + <0x00780200 0x4>, + <0x088e7014 0x4>; + reg-names = "qusb_phy_base", "efuse_addr", + "refgen_north_bg_reg_addr"; + + qcom,efuse-bit-pos = <25>; + qcom,efuse-num-bits = <3>; + vdd-supply = <&pm6150_l4>; + vdda18-supply = <&pm6150_l11>; + vdda33-supply = <&pm6150_l17>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,qusb-phy-reg-offset = + <0x240 /* QUSB2PHY_PORT_TUNE1 */ + 0x1a0 /* QUSB2PHY_PLL_COMMON_STATUS_ONE */ + 0x210 /* QUSB2PHY_PWR_CTRL1 */ + 0x230 /* QUSB2PHY_INTR_CTRL */ + 0x0a8 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE */ + 0x254 /* QUSB2PHY_TEST1 */ + 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x27c /* QUSB2PHY_DEBUG_CTRL1 */ + 0x280 /* QUSB2PHY_DEBUG_CTRL2 */ + 0x2a0>; /* QUSB2PHY_STAT5 */ + + qcom,qusb-phy-init-seq = + /* */ + <0x23 0x210 /* PWR_CTRL1 */ + 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */ + 0x7c 0x18c /* PLL_CLOCK_INVERTERS */ + 0x80 0x2c /* PLL_CMODE */ + 0x0a 0x184 /* PLL_LOCK_DELAY */ + 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ + 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ + 0x22 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x21 0x214 /* PWR_CTRL2 */ + 0x08 0x220 /* IMP_CTRL1 */ + 0x58 0x224 /* IMP_CTRL2 */ + 0x45 0x240 /* TUNE1 */ + 0x29 0x244 /* TUNE2 */ + 0xca 0x248 /* TUNE3 */ + 0x04 0x24c /* TUNE4 */ + 0x03 0x250 /* TUNE5 */ + 0x30 0x23c /* CHG_CTRL2 */ + 0x22 0x210>; /* PWR_CTRL1 */ + + qcom,qusb-phy-host-init-seq = + /* */ + <0x23 0x210 /* PWR_CTRL1 */ + 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */ + 0x7c 0x18c /* PLL_CLOCK_INVERTERS */ + 0x80 0x2c /* PLL_CMODE */ + 0x0a 0x184 /* PLL_LOCK_DELAY */ + 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ + 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ + 0x22 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x21 0x214 /* PWR_CTRL2 */ + 0x08 0x220 /* IMP_CTRL1 */ + 0x58 0x224 /* IMP_CTRL2 */ + 0x45 0x240 /* TUNE1 */ + 0x29 0x244 /* TUNE2 */ + 0xca 0x248 /* TUNE3 */ + 0x04 0x24c /* TUNE4 */ + 0x03 0x250 /* TUNE5 */ + 0x30 0x23c /* CHG_CTRL2 */ + 0x22 0x210>; /* PWR_CTRL1 */ + + phy_type= "utmi"; + clocks = <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; + clock-names = "ref_clk_src", "cfg_ahb_clk"; + + resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + /* Primary USB port related QMP USB DP Combo PHY */ + usb_qmp_dp_phy: ssphy@88e8000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88e8000 0x3000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&pm6150_l4>; + qcom,vdd-voltage-level = <0 880000 880000>; + core-supply = <&pm6150l_l3>; + extcon = <&pm6150_pdphy>; + qcom,vbus-valid-override; + qcom,qmp-phy-init-seq = + /* */ + <0x1048 0x07 0x00 /* COM_PLL_IVCO */ + 0x1080 0x14 0x00 /* COM_SYSCLK_EN_SEL */ + 0x1034 0x08 0x00 /* COM_BIAS_EN_CLKBUFLR_EN */ + 0x1138 0x30 0x00 /* COM_CLK_SELECT */ + 0x103c 0x02 0x00 /* COM_SYS_CLK_CTRL */ + 0x108c 0x08 0x00 /* COM_RESETSM_CNTRL2 */ + 0x115c 0x16 0x00 /* COM_CMN_CONFIG */ + 0x1164 0x01 0x00 /* COM_SVS_MODE_CLK_SEL */ + 0x113c 0x80 0x00 /* COM_HSCLK_SEL */ + 0x10b0 0x82 0x00 /* COM_DEC_START_MODE0 */ + 0x10b8 0xab 0x00 /* COM_DIV_FRAC_START1_MODE0 */ + 0x10bc 0xea 0x00 /* COM_DIV_FRAC_START2_MODE0 */ + 0x10c0 0x02 0x00 /* COM_DIV_FRAC_START3_MODE0 */ + 0x1060 0x06 0x00 /* COM_CP_CTRL_MODE0 */ + 0x1068 0x16 0x00 /* COM_PLL_RCTRL_MODE0 */ + 0x1070 0x36 0x00 /* COM_PLL_CCTRL_MODE0 */ + 0x10dc 0x00 0x00 /* COM_INTEGLOOP_GAIN1_MODE0 */ + 0x10d8 0x3f 0x00 /* COM_INTEGLOOP_GAIN0_MODE0 */ + 0x10f8 0x01 0x00 /* COM_VCO_TUNE2_MODE0 */ + 0x10f4 0xc9 0x00 /* COM_VCO_TUNE1_MODE0 */ + 0x1148 0x0a 0x00 /* COM_CORECLK_DIV_MODE0 */ + 0x10a0 0x00 0x00 /* COM_LOCK_CMP3_MODE0 */ + 0x109c 0x34 0x00 /* COM_LOCK_CMP2_MODE0 */ + 0x1098 0x15 0x00 /* COM_LOCK_CMP1_MODE0 */ + 0x1090 0x04 0x00 /* COM_LOCK_CMP_EN */ + 0x1154 0x00 0x00 /* COM_CORE_CLK_EN */ + 0x1094 0x00 0x00 /* COM_LOCK_CMP_CFG */ + 0x10f0 0x00 0x00 /* COM_VCO_TUNE_MAP */ + 0x1040 0x0a 0x00 /* COM_SYSCLK_BUF_ENABLE */ + 0x1010 0x01 0x00 /* COM_SSC_EN_CENTER */ + 0x101c 0x31 0x00 /* COM_SSC_PER1 */ + 0x1020 0x01 0x00 /* COM_SSC_PER2 */ + 0x1014 0x00 0x00 /* COM_SSC_ADJ_PER1 */ + 0x1018 0x00 0x00 /* COM_SSC_ADJ_PER2 */ + 0x1024 0x85 0x00 /* COM_SSC_STEP_SIZE1 */ + 0x1028 0x07 0x00 /* COM_SSC_STEP_SIZE2 */ + 0x1430 0x0b 0x00 /* RXA_UCDR_FASTLOCK_FO_GAIN */ + 0x14d4 0x0f 0x00 /* RXA_RX_EQU_ADAPTOR_CNTRL2 */ + 0x14d8 0x4e 0x00 /* RXA_RX_EQU_ADAPTOR_CNTRL3 */ + 0x14dc 0x18 0x00 /* RXA_RX_EQU_ADAPTOR_CNTRL4 */ + 0x14f8 0x77 0x00 /* RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */ + 0x14fc 0x80 0x00 /* RXA_RX_OFFSET_ADAPTOR_CNTRL2 */ + 0x1504 0x03 0x00 /* RXA_SIGDET_CNTRL */ + 0x150c 0x16 0x00 /* RXA_SIGDET_DEGLITCH_CNTRL */ + 0x1564 0x05 0x00 /* RXA_RX_MODE_00 */ + 0x14c0 0x03 0x00 /* RXA_VGA_CAL_CNTRL2 */ + 0x1830 0x0b 0x00 /* RXB_UCDR_FASTLOCK_FO_GAIN */ + 0x18d4 0x0f 0x00 /* RXB_RX_EQU_ADAPTOR_CNTRL2 */ + 0x18d8 0x4e 0x00 /* RXB_RX_EQU_ADAPTOR_CNTRL3 */ + 0x18dc 0x18 0x00 /* RXB_RX_EQU_ADAPTOR_CNTRL4 */ + 0x18f8 0x77 0x00 /* RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */ + 0x18fc 0x80 0x00 /* RXB_RX_OFFSET_ADAPTOR_CNTRL2 */ + 0x1904 0x03 0x00 /* RXB_SIGDET_CNTRL */ + 0x190c 0x16 0x00 /* RXB_SIGDET_DEGLITCH_CNTRL */ + 0x1964 0x05 0x00 /* RXB_RX_MODE_00 */ + 0x18c0 0x03 0x00 /* RXB_VGA_CAL_CNTRL2 */ + 0x1260 0x10 0x00 /* TXA_HIGHZ_DRVR_EN */ + 0x12a4 0x12 0x00 /* TXA_RCV_DETECT_LVL_2 */ + 0x128c 0x16 0x00 /* TXA_LANE_MODE_1 */ + 0x1248 0x09 0x00 /* TXA_RES_CODE_LANE_OFFSET_RX */ + 0x1244 0x06 0x00 /* TXA_RES_CODE_LANE_OFFSET_TX */ + 0x1660 0x10 0x00 /* TXB_HIGHZ_DRVR_EN */ + 0x16a4 0x12 0x00 /* TXB_RCV_DETECT_LVL_2 */ + 0x168c 0x16 0x00 /* TXB_LANE_MODE_1 */ + 0x1648 0x09 0x00 /* TXB_RES_CODE_LANE_OFFSET_RX */ + 0x1644 0x06 0x00 /* TXB_RES_CODE_LANE_OFFSET_TX */ + 0x1cc8 0x83 0x00 /* PCS_FLL_CNTRL2 */ + 0x1ccc 0x09 0x00 /* PCS_FLL_CNT_VAL_L */ + 0x1cd0 0xa2 0x00 /* PCS_FLL_CNT_VAL_H_TOL */ + 0x1cd4 0x40 0x00 /* PCS_FLL_MAN_CODE */ + 0x1cc4 0x02 0x00 /* PCS_FLL_CNTRL1 */ + 0x1c80 0xd1 0x00 /* PCS_LOCK_DETECT_CONFIG1 */ + 0x1c84 0x1f 0x00 /* PCS_LOCK_DETECT_CONFIG2 */ + 0x1c88 0x47 0x00 /* PCS_LOCK_DETECT_CONFIG3 */ + 0x1c64 0x1b 0x00 /* PCS_POWER_STATE_CONFIG2 */ + 0x1434 0x75 0x00 /* RXA_UCDR_SO_SATURATION */ + 0x1834 0x75 0x00 /* RXB_UCDR_SO_SATURATION */ + 0x1dd8 0xba 0x00 /* PCS_RX_SIGDET_LVL */ + 0x1c0c 0x9f 0x00 /* PCS_TXMGN_V0 */ + 0x1c10 0x9f 0x00 /* PCS_TXMGN_V1 */ + 0x1c14 0xb7 0x00 /* PCS_TXMGN_V2 */ + 0x1c18 0x4e 0x00 /* PCS_TXMGN_V3 */ + 0x1c1c 0x65 0x00 /* PCS_TXMGN_V4 */ + 0x1c20 0x6b 0x00 /* PCS_TXMGN_LS */ + 0x1c24 0x15 0x00 /* PCS_TXDEEMPH_M6DB_V0 */ + 0x1c28 0x0d 0x00 /* PCS_TXDEEMPH_M3P5DB_V0 */ + 0x1c2c 0x15 0x00 /* PCS_TXDEEMPH_M6DB_V1 */ + 0x1c30 0x0d 0x00 /* PCS_TXDEEMPH_M3P5DB_V1 */ + 0x1c34 0x15 0x00 /* PCS_TXDEEMPH_M6DB_V2 */ + 0x1c38 0x0d 0x00 /* PCS_TXDEEMPH_M3P5DB_V2 */ + 0x1c3c 0x15 0x00 /* PCS_TXDEEMPH_M6DB_V3 */ + 0x1c40 0x1d 0x00 /* PCS_TXDEEMPH_M3P5DB_V3 */ + 0x1c44 0x15 0x00 /* PCS_TXDEEMPH_M6DB_V4 */ + 0x1c48 0x0d 0x00 /* PCS_TXDEEMPH_M3P5DB_V4 */ + 0x1c4c 0x15 0x00 /* PCS_TXDEEMPH_M6DB_LS */ + 0x1c50 0x0d 0x00 /* PCS_TXDEEMPH_M3P5DB_LS */ + 0x1e0c 0x21 0x00 /* PCS_REFGEN_REQ_CONFIG1 */ + 0x1e10 0x60 0x00 /* PCS_REFGEN_REQ_CONFIG2 */ + 0x1c5c 0x02 0x00 /* PCS_RATE_SLEW_CNTRL */ + 0x1ca0 0x04 0x00 /* PCS_PWRUP_RESET_DLY_TIME_AUXCLK */ + 0x1c8c 0x44 0x00 /* PCS_TSYNC_RSYNC_TIME */ + 0x1c70 0xe7 0x00 /* PCS_RCVR_DTCT_DLY_P1U2_L */ + 0x1c74 0x03 0x00 /* PCS_RCVR_DTCT_DLY_P1U2_H */ + 0x1c78 0x40 0x00 /* PCS_RCVR_DTCT_DLY_U3_L */ + 0x1c7c 0x00 0x00 /* PCS_RCVR_DTCT_DLY_U3_H */ + 0x1cb8 0x75 0x00 /* PCS_RXEQTRAINING_WAIT_TIME */ + 0x1cb0 0x86 0x00 /* PCS_LFPS_TX_ECSTART_EQTLOCK */ + 0x1cbc 0x13 0x00 /* PCS_RXEQTRAINING_RUN_TIME */ + 0x1cac 0x04 0x00 /* PCS_LFPS_DET_HIGH_COUNT_VAL */ + 0xffffffff 0xffffffff 0x00>; + + qcom,qmp-phy-reg-offset = + <0x1d74 /* USB3_DP_PCS_PCS_STATUS */ + 0x1cd8 /* USB3_DP_PCS_AUTONOMOUS_MODE_CTRL */ + 0x1cdc /* USB3_DP_PCS_LFPS_RXTERM_IRQ_CLEAR */ + 0x1c04 /* USB3_DP_PCS_POWER_DOWN_CONTROL */ + 0x1c00 /* USB3_DP_PCS_SW_RESET */ + 0x1c08 /* USB3_DP_PCS_START_CONTROL */ + 0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */ + 0x2a18 /* USB3_DP_DP_PHY_PD_CTL */ + 0x0008 /* USB3_DP_COM_POWER_DOWN_CTRL */ + 0x0004 /* USB3_DP_COM_SW_RESET */ + 0x001c /* USB3_DP_COM_RESET_OVRD_CTRL */ + 0x0000 /* USB3_DP_COM_PHY_MODE_CTRL */ + 0x0010 /* USB3_DP_COM_TYPEC_CTRL */ + 0x000c /* USB3_DP_COM_SWI_CTRL */ + 0x1a0c>; /* USB3_DP_PCS_MISC_CLAMP_ENABLE */ + + clocks = <&clock_gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk", "cfg_ahb_clk"; + + resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&clock_gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x1b2f 0x0>; + qcom,usb-audio-stream-id = <0xf>; + qcom,usb-audio-intr-num = <2>; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-usbc-idp-overlay.dts b/arch/arm/boot/dts/qcom/sdmmagpie-usbc-idp-overlay.dts new file mode 100644 index 000000000000..fd69d2242a2c --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-usbc-idp-overlay.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include + +#include "sdmmagpie-idp.dtsi" +#include "sdmmagpie-usbc-idp.dtsi" + +/ { + model = "USBC Audio IDP"; + compatible = "qcom,sdmmagpie-idp", "qcom,sdmmagpie", "qcom,idp"; + qcom,msm-id = <365 0x0>; + qcom,board-id = <34 2>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-usbc-idp.dts b/arch/arm/boot/dts/qcom/sdmmagpie-usbc-idp.dts new file mode 100644 index 000000000000..6c86760281e6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-usbc-idp.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdmmagpie.dtsi" +#include "sdmmagpie-idp.dtsi" +#include "sdmmagpie-usbc-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDMMAGPIE PM6150 USBC Audio IDP"; + compatible = "qcom,sdmmagpie-idp", "qcom,sdmmagpie", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-usbc-idp.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-usbc-idp.dtsi new file mode 100644 index 000000000000..f79404f3ddae --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-usbc-idp.dtsi @@ -0,0 +1,19 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdmmagpie-audio-overlay.dtsi" + +&sm6150_snd { + qcom,msm-mbhc-usbc-audio-supported = <1>; + qcom,msm-mbhc-hphl-swh = <0>; + qcom,msm-mbhc-gnd-swh = <0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie-vidc.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie-vidc.dtsi new file mode 100644 index 000000000000..92b370cdc2a1 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie-vidc.dtsi @@ -0,0 +1,219 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&soc { + msm_vidc0: qcom,vidc0 { + compatible = "qcom,msm-vidc", "qcom,sdmmagpie-vidc"; + status = "ok"; + sku-index = <0>; + reg = <0xaa00000 0x200000>; + interrupts = ; + + /* Supply */ + iris-ctl-supply = <&mvsc_gdsc>; + vcodec-supply = <&mvs0_gdsc>; + cvp-supply = <&mvs1_gdsc>; + + /* Clocks */ + clock-names = "video_cc_mvsc_ctl_axi", "video_cc_mvs0_ctl_axi", + "video_cc_mvs1_ctl_axi", "core_clk", "vcodec_clk", + "cvp_clk", "iface_clk"; + clocks = <&clock_videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, + <&clock_videocc VIDEO_CC_MVS0_AXI_CLK>, + <&clock_videocc VIDEO_CC_MVS1_AXI_CLK>, + <&clock_videocc VIDEO_CC_MVSC_CORE_CLK>, + <&clock_videocc VIDEO_CC_MVS0_CORE_CLK>, + <&clock_videocc VIDEO_CC_MVS1_CORE_CLK>, + <&clock_videocc VIDEO_CC_VENUS_AHB_CLK>; + + qcom,proxy-clock-names = "video_cc_mvsc_ctl_axi", + "video_cc_mvs0_ctl_axi", "video_cc_mvs1_ctl_axi", + "core_clk", "vcodec_clk", "cvp_clk", "iface_clk"; + + qcom,clock-configs = <0x0 0x0 0x0 0x1 0x1 0x1 0x0>; + qcom,allowed-clock-rates = <240000000 338000000 365000000>; + + /* Buses */ + bus_cnoc { + compatible = "qcom,msm-vidc,bus"; + label = "cnoc"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 1000>; + }; + + venus_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-ddr"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "msm-vidc-ddr"; + qcom,bus-range-kbps = <1000 6533000>; + }; + arm9_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-arm9-ddr"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 1000>; + }; + + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_ns"; + iommus = <&apps_smmu 0x1080 0x60>; + buffer-types = <0xfff>; + virtual-addr-pool = <0x25800000 0xba800000>; + }; + + secure_non_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_non_pixel"; + iommus = <&apps_smmu 0x1084 0x60>; + buffer-types = <0x480>; + virtual-addr-pool = <0x1000000 0x24800000>; + qcom,secure-context-bank; + }; + + secure_bitstream_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_bitstream"; + iommus = <&apps_smmu 0x1081 0x4>; + buffer-types = <0x241>; + virtual-addr-pool = <0x500000 0xdfb00000>; + qcom,secure-context-bank; + }; + + secure_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_pixel"; + iommus = <&apps_smmu 0x1083 0x20>; + buffer-types = <0x106>; + virtual-addr-pool = <0x500000 0xdfb00000>; + qcom,secure-context-bank; + }; + + /* Memory Heaps */ + qcom,msm-vidc,mem_cdsp { + compatible = "qcom,msm-vidc,mem-cdsp"; + memory-region = <&cdsp_mem>; + }; + }; + + msm_vidc1: qcom,vidc1 { + compatible = "qcom,msm-vidc", "qcom,sdmmagpie-vidc"; + status = "ok"; + sku-index = <1>; + reg = <0xaa00000 0x200000>; + interrupts = ; + + /* Supply */ + iris-ctl-supply = <&mvsc_gdsc>; + vcodec-supply = <&mvs0_gdsc>; + cvp-supply = <&mvs1_gdsc>; + + /* Clocks */ + clock-names = "video_cc_mvsc_ctl_axi", "video_cc_mvs0_ctl_axi", + "video_cc_mvs1_ctl_axi", "core_clk", "vcodec_clk", + "cvp_clk", "iface_clk"; + clocks = <&clock_videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, + <&clock_videocc VIDEO_CC_MVS0_AXI_CLK>, + <&clock_videocc VIDEO_CC_MVS1_AXI_CLK>, + <&clock_videocc VIDEO_CC_MVSC_CORE_CLK>, + <&clock_videocc VIDEO_CC_MVS0_CORE_CLK>, + <&clock_videocc VIDEO_CC_MVS1_CORE_CLK>, + <&clock_videocc VIDEO_CC_VENUS_AHB_CLK>; + + qcom,proxy-clock-names = "video_cc_mvsc_ctl_axi", + "video_cc_mvs0_ctl_axi", "video_cc_mvs1_ctl_axi", + "core_clk", "vcodec_clk", "cvp_clk", "iface_clk"; + + qcom,clock-configs = <0x0 0x0 0x0 0x1 0x1 0x1 0x0>; + qcom,allowed-clock-rates = <200000000>; + + /* Buses */ + bus_cnoc { + compatible = "qcom,msm-vidc,bus"; + label = "cnoc"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 1000>; + }; + + venus_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-ddr"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "msm-vidc-ddr"; + qcom,bus-range-kbps = <1000 6533000>; + }; + arm9_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-arm9-ddr"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 1000>; + }; + + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_ns"; + iommus = <&apps_smmu 0x1080 0x60>; + buffer-types = <0xfff>; + virtual-addr-pool = <0x25800000 0xba800000>; + }; + + secure_non_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_non_pixel"; + iommus = <&apps_smmu 0x1084 0x60>; + buffer-types = <0x480>; + virtual-addr-pool = <0x1000000 0x24800000>; + qcom,secure-context-bank; + }; + + secure_bitstream_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_bitstream"; + iommus = <&apps_smmu 0x1081 0x4>; + buffer-types = <0x241>; + virtual-addr-pool = <0x500000 0xdfb00000>; + qcom,secure-context-bank; + }; + + secure_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_pixel"; + iommus = <&apps_smmu 0x1083 0x20>; + buffer-types = <0x106>; + virtual-addr-pool = <0x500000 0xdfb00000>; + qcom,secure-context-bank; + }; + + /* Memory Heaps */ + qcom,msm-vidc,mem_cdsp { + compatible = "qcom,msm-vidc,mem-cdsp"; + memory-region = <&cdsp_mem>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie.dts b/arch/arm/boot/dts/qcom/sdmmagpie.dts new file mode 100644 index 000000000000..780dbe2503d4 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdmmagpie.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDMMAGPIE SoC"; + compatible = "qcom,sdmmagpie"; + qcom,pmic-name = "PM6150"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpie.dtsi b/arch/arm/boot/dts/qcom/sdmmagpie.dtsi new file mode 100644 index 000000000000..1083bda78f5e --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpie.dtsi @@ -0,0 +1,3472 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "skeleton64.dtsi" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} + +/ { + model = "Qualcomm Technologies, Inc. SDMMAGPIE"; + compatible = "qcom,sdmmagpie"; + qcom,msm-id = <365 0x0>; + qcom,msm-name = "SDMMAGPIE"; + interrupt-parent = <&pdc>; + + aliases { + spi0 = &qupv3_se0_spi; + spi1 = &qupv3_se4_spi; + i2c0 = &qupv3_se2_i2c; + i2c1 = &qupv3_se7_i2c; + i2c2 = &qupv3_se9_i2c; + serial0 = &qupv3_se8_2uart; + hsuart0 = &qupv3_se3_4uart; + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ + sdhc2 = &sdhc_2; /* SDC2 SD Card slot */ + ufshc1 = &ufshc_mem; /* Embedded UFS slot */ + swr0 = &swr0; + swr1 = &swr1; + swr2 = &swr2; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + cache-size = <0x8000>; + next-level-cache = <&L2_0>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-size = <0x100000>; + cache-level = <3>; + }; + }; + + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_0: l2-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + cache-size = <0x8000>; + next-level-cache = <&L2_100>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_100: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_100: l2-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + cache-size = <0x8000>; + next-level-cache = <&L2_200>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_200: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_200: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_200: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_200: l2-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + cache-size = <0x8000>; + next-level-cache = <&L2_300>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_300: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_300: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_300: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_300: l2-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + cache-size = <0x8000>; + next-level-cache = <&L2_400>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_400: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_400: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_400: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_400: l2-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + cache-size = <0x8000>; + next-level-cache = <&L2_500>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_500: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_500: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_500: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_500: l2-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; + cache-size = <0x10000>; + next-level-cache = <&L2_600>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + #cooling-cells = <2>; + L2_600: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + qcom,dump-size = <0x48000>; + }; + + L1_I_600: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x11000>; + }; + + L1_D_600: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + + L1_ITLB_600: l1-itlb { + qcom,dump-size = <0x300>; + }; + + L1_DTLB_600: l1-dtlb { + qcom,dump-size = <0x480>; + }; + + L2_TLB_600: l2-tlb { + qcom,dump-size = <0x7800>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; + cache-size = <0x10000>; + next-level-cache = <&L2_700>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + #cooling-cells = <2>; + L2_700: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + qcom,dump-size = <0x48000>; + }; + + L1_I_700: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x11000>; + }; + + L1_D_700: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + + L1_ITLB_700: l1-itlb { + qcom,dump-size = <0x300>; + }; + + L1_DTLB_700: l1-dtlb { + qcom,dump-size = <0x480>; + }; + + L2_TLB_700: l2-tlb { + qcom,dump-size = <0x7800>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + }; + + cluster1 { + core0 { + cpu = <&CPU6>; + }; + + core1 { + cpu = <&CPU7>; + }; + }; + }; + }; + + energy_costs: energy-costs { + compatible = "sched-energy"; + + CPU_COST_0: core-cost0 { + busy-cost-data = < + 300000 10 + 576000 18 + 768000 23 + 1017600 36 + 1248000 52 + 1324800 67 + 1497600 76 + 1612800 92 + 1708800 113 + 1804800 119 + >; + idle-cost-data = < + 16 12 8 6 + >; + }; + + CPU_COST_1: core-cost1 { + busy-cost-data = < + 300000 166 + 652800 242 + 806400 293 + 979200 424 + 1094400 470 + 1209600 621 + 1324800 676 + 1555200 973 + 1708800 1060 + 1843200 1298 + 1939200 1362 + 2169600 1801 + 2208000 2000 + 2361600 2326 + 2400000 2568 + >; + idle-cost-data = < + 100 80 60 40 + >; + }; + + CLUSTER_COST_0: cluster-cost0 { + busy-cost-data = < + 300000 5 + 576000 5 + 768000 5 + 1017600 7 + 1248000 8 + 1324800 10 + 1497600 10 + 1612800 12 + 1708800 14 + 1804800 14 + >; + idle-cost-data = < + 5 4 3 2 1 + >; + }; + + CLUSTER_COST_1: cluster-cost1 { + busy-cost-data = < + 300000 19 + 652800 21 + 806400 21 + 979200 25 + 1094400 26 + 1209600 32 + 1324800 33 + 1555200 41 + 1708800 43 + 1843200 49 + 1939200 50 + 2169600 60 + 2208000 61 + 2361600 62 + 2400000 63 + >; + idle-cost-data = < + 5 4 3 2 1 + >; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + }; + + soc: soc { }; + + firmware: firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; + }; + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_region: hyp_region@85700000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x85700000 0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_mem@85e00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x85e00000 0x0 0x1ff000>; + }; + + sec_apps_mem: sec_apps_region@85fff000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x85fff000 0x0 0x1000>; + }; + + smem_region: smem@86000000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x86000000 0x0 0x200000>; + }; + + removed_region: removed_region@86200000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x86200000 0 0x2d00000>; + }; + + pil_camera_mem: camera_region@8ab00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x8ab00000 0 0x500000>; + }; + + pil_modem_mem: modem_region@8b000000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x8b000000 0 0x7e00000>; + }; + + pil_video_mem: pil_video_region@92e00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x92e00000 0 0x500000>; + }; + + pil_cdsp_mem: cdsp_regions@93300000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x93300000 0 0x1e00000>; + }; + + pil_adsp_mem: pil_adsp_region@95100000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x95100000 0 0x1e00000>; + }; + + wlan_msa_mem: wlan_msa_region@96f00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x96f00000 0 0x180000>; + }; + + npu_mem: npu_region@97080000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x97080000 0 0x80000>; + }; + + pil_ipa_fw_mem: ips_fw_region@97100000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x97100000 0 0x10000>; + }; + + pil_ipa_gsi_mem: ipa_gsi_region@97110000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x97110000 0 0x5000>; + }; + + pil_gpu_mem: gpu_region@97115000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x97115000 0 0x2000>; + }; + + qseecom_mem: qseecom_region@9e400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x9e400000 0 0x1400000>; + }; + + cdsp_sec_mem: cdsp_sec_regions@0x9f800000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x9f800000 0x0 0x1e00000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0xc00000>; + }; + + cdsp_mem: cdsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x1000000>; + }; + + sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */ + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x5c00000>; + }; + + cont_splash_memory: cont_splash_region@9c000000 { + reg = <0x0 0x9c000000 0x0 0x01800000>; + label = "cont_splash_region"; + }; + + disp_rdump_memory: disp_rdump_region@9c000000 { + reg = <0x0 0x9c000000 0x0 0x01800000>; + label = "disp_rdump_region"; + }; + + dfps_data_memory: dfps_data_region@9e300000 { + reg = <0x0 0x9d700000 0x0 0x0100000>; + label = "dfps_data_region"; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x2400000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x2000000>; + linux,cma-default; + }; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + jtag_mm0: jtagmm@7040000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7040000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU0>; + }; + + jtag_mm1: jtagmm@7140000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7140000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU1>; + }; + + jtag_mm2: jtagmm@7240000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7240000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU2>; + }; + + jtag_mm3: jtagmm@7340000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7340000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU3>; + }; + + jtag_mm4: jtagmm@7440000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7440000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU4>; + }; + + jtag_mm5: jtagmm@7540000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7540000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU5>; + }; + + jtag_mm6: jtagmm@7640000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7640000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU6>; + }; + + jtag_mm7: jtagmm@7740000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7740000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU7>; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17a60000 0x100000>; /* GICR * 8 */ + interrupts = ; + interrupt-parent = <&intc>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,pdc-sdmmagpie"; + reg = <0xb220000 0x400>; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <2>; + label = "modem"; + }; + + mem_client_3_size: qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x500000>; + qcom,client-id = <1>; + qcom,allocate-on-request; + label = "modem"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + timer@0x17c20000{ + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17c20000 0x1000>; + clock-frequency = <19200000>; + + frame@0x17c21000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = ; + reg = <0x17c23000 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = ; + reg = <0x17c25000 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = ; + reg = <0x17c27000 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = ; + reg = <0x17c29000 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = ; + reg = <0x17c2b000 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = ; + reg = <0x17c2d000 0x1000>; + status = "disabled"; + }; + }; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "chip_sleep_clk"; + #clock-cells = <1>; + }; + }; + + clock_rpmh: qcom,rpmh { + compatible = "qcom,rpmh-clk-sdmmagpie"; + mboxes = <&apps_rsc 0>; + mbox-names = "apps"; + #clock-cells = <1>; + }; + + clock_aop: qcom,aopclk { + compatible = "qcom,aop-qmp-clk"; + #clock-cells = <1>; + mboxes = <&qmp_aop 0>; + mbox-names = "qdss_clk"; + }; + + clock_gcc: qcom,gcc@100000 { + compatible = "qcom,gcc-sdmmagpie", "syscon"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; + reg = <0x100000 0x1f0000>; + reg-names = "cc_base"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_camcc: qcom,camcc { + compatible = "qcom,camcc-sdmmagpie", "syscon"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + reg = <0xad00000 0x10000>; + reg-names = "cc_base"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_gpucc: qcom,gpucc { + compatible = "qcom,gpucc-sdmmagpie", "syscon"; + reg = <0x5090000 0x9000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_gfx-supply = <&VDD_GFX_LEVEL>; + qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>; + qcom,gpu_cc_gmu_clk_src-opp-handle = <&gmu>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_videocc: qcom,videocc@ab00000 { + compatible = "qcom,videocc-sdmmagpie", "syscon"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + reg = <0xab00000 0x10000>, + <0x00786018 0x4>; + reg-names = "cc_base", "efuse"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_dispcc: qcom,dispcc@af00000 { + compatible = "qcom,dispcc-sdmmagpie", "syscon"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + reg = <0xaf00000 0x20000>; + reg-names = "cc_base"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_npucc: qcom,npucc { + compatible = "qcom,npucc-sdmmagpie", "syscon"; + reg = <0x9910000 0x10000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + npu_gdsc-supply = <&npu_core_gdsc>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_cpucc: qcom,cpucc@18321000 { + compatible = "qcom,clk-cpu-osm-sdmmagpie"; + reg = <0x18321000 0x1400>, + <0x18323000 0x1400>, + <0x18325800 0x1400>; + reg-names = "osm_l3_base", "osm_pwrcl_base", + "osm_perfcl_base"; + l3-devs = <&cpu0_cpu_l3_lat &cpu6_cpu_l3_lat + &cdsp_cdsp_l3_lat>; + + #clock-cells = <1>; + }; + + cpucc_debug: syscon@182a0018 { + compatible = "syscon"; + reg = <0x182a0018 0x4>; + }; + + mccc_debug: syscon@90b0000 { + compatible = "syscon"; + reg = <0x90b0000 0x1000>; + }; + + clock_debug: qcom,cc-debug { + compatible = "qcom,debugcc-sdmmagpie"; + qcom,cc-count = <8>; + qcom,gcc = <&clock_gcc>; + qcom,videocc = <&clock_videocc>; + qcom,camcc = <&clock_camcc>; + qcom,dispcc = <&clock_dispcc>; + qcom,gpucc = <&clock_gpucc>; + qcom,npucc = <&clock_npucc>; + qcom,cpucc = <&cpucc_debug>; + qcom,mccc = <&mccc_debug>; + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo_clk_src"; + #clock-cells = <1>; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = ; + }; + + dsu_pmu@0 { + compatible = "arm,dsu-pmu"; + interrupts = ; + cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, + <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>; + }; + + qcom,msm-imem@146aa000 { + compatible = "qcom,msm-imem"; + reg = <0x146aa000 0x1000>; + ranges = <0x0 0x146aa000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 32>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 12>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 200>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 200>; + }; + }; + + restart@c264000 { + compatible = "qcom,pshold"; + reg = <0xc264000 0x4>, + <0x1fd3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + qcom,mpm2-sleep-counter@0xc221000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xc221000 0x1000>; + clock-frequency = <32768>; + }; + + aop-msg-client { + compatible = "qcom,debugfs-qmp-client"; + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + gpi_dma0: qcom,gpi-dma@0x800000 { + #dma-cells = <5>; + compatible = "qcom,gpi-dma"; + reg = <0x800000 0x60000>; + reg-names = "gpi-top"; + interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>, + <0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>; + qcom,max-num-gpii = <8>; + qcom,gpii-mask = <0x0f>; + qcom,ev-factor = <2>; + iommus = <&apps_smmu 0x0216 0x0>; + qcom,smmu-cfg = <0x1>; + qcom,iova-range = <0x0 0x100000 0x0 0x100000>; + status = "ok"; + }; + + gpi_dma1: qcom,gpi-dma@0xa00000 { + #dma-cells = <5>; + compatible = "qcom,gpi-dma"; + reg = <0xa00000 0x60000>; + reg-names = "gpi-top"; + interrupts = <0 279 0>, <0 280 0>, <0 281 0>, <0 282 0>, + <0 283 0>, <0 284 0>, <0 293 0>, <0 294 0>; + qcom,max-num-gpii = <8>; + qcom,gpii-mask = <0x0f>; + qcom,ev-factor = <2>; + iommus = <&apps_smmu 0x04d6 0x0>; + qcom,smmu-cfg = <0x1>; + qcom,iova-range = <0x0 0x100000 0x0 0x100000>; + status = "ok"; + }; + + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-io-supply = <&pm6150_l10>; + qca,bt-vdd-core-supply = <&pm6150l_l2>; + qca,bt-vdd-pa-supply = <&pm6150l_l10>; + qca,bt-vdd-xtal-supply = <&pm6150l_l1>; + + qca,bt-vdd-io-voltage-level = <1700000 1900000>; /* IO */ + qca,bt-vdd-core-voltage-level = <1245000 1350000>; /* RFA */ + qca,bt-vdd-pa-voltage-level = <3200000 3400000>; /*chain0 */ + qca,bt-vdd-xtal-voltage-level = <1700000 1900000>; /* XO */ + + qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ + }; + + slim_aud: slim@62dc0000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0x62dc0000 0x2c000>, + <0x62d84000 0x2a000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 163 0>, <0 164 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x7c0000>; + qcom,ea-pc = <0x300>; + status = "disabled"; + qcom,iommu-s1-bypass; + + iommu_slim_aud_ctrl_cb: qcom,iommu_slim_ctrl_cb { + compatible = "qcom,iommu-slim-ctrl-cb"; + iommus = <&apps_smmu 0x1be6 0x8>, + <&apps_smmu 0x1bed 0x2>, + <&apps_smmu 0x1bf0 0x1>; + }; + + }; + + slim_qca: slim@62e40000 { + cell-index = <3>; + compatible = "qcom,slim-ngd"; + reg = <0x62e40000 0x2c000>, + <0x62e04000 0x20000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 291 0>, <0 292 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + status = "ok"; + qcom,iommu-s1-bypass; + + iommu_slim_qca_ctrl_cb: qcom,iommu_slim_ctrl_cb { + compatible = "qcom,iommu-slim-ctrl-cb"; + iommus = <&apps_smmu 0x1bf3 0x0>; + }; + + /* Slimbus Slave DT for WCN3990 */ + btfmslim_codec: wcn3990 { + compatible = "qcom,btfmslim_slave"; + elemental-addr = [00 01 20 02 17 02]; + qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; + qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; + }; + }; + + wdog: qcom,wdt@17c10000{ + compatible = "qcom,msm-watchdog"; + reg = <0x17c10000 0x1000>; + reg-names = "wdt-base"; + interrupts = , + ; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + qcom,scandump-sizes = <0x10100 0x10100 0x10100 0x10100 + 0x10100 0x10100 0x25900 0x25900>; + }; + + eud: qcom,msm-eud@88e0000 { + compatible = "qcom,msm-eud"; + interrupt-names = "eud_irq"; + interrupts = ; + reg = <0x88e0000 0x2000>, + <0x88e4000 0x1000>; + reg-names = "eud_base", "eud_mode_mgr2"; + qcom,secure-eud-en; + qcom,eud-clock-vote-req; + clocks = <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; + clock-names = "eud_ahb2phy_clk"; + status = "ok"; + }; + + qcom,chd_sliver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x18000058 0x18010058 + 0x18020058 0x18030058 + 0x18040058 0x18050058>; + qcom,config-arr = <0x18000060 0x18010060 + 0x18020060 0x18030060 + 0x18040060 0x18050060>; + }; + + qcom,chd_gold { + compatible = "qcom,core-hang-detect"; + label = "gold"; + qcom,threshold-arr = <0x18060058 0x18070058>; + qcom,config-arr = <0x18060060 0x18070060>; + }; + + kryo-erp { + compatible = "arm,arm64-kryo-cpu-erp"; + interrupts = , + ; + + interrupt-names = "l1-l2-faultirq", + "l3-scu-faultirq"; + }; + + qcom,ghd { + compatible = "qcom,gladiator-hang-detect-v3"; + qcom,threshold-arr = <0x17e0041C>; + qcom,config-reg = <0x17e00434>; + }; + + cpuss_dump { + compatible = "qcom,cpuss-dump"; + + qcom,l1_i_cache0 { + qcom,dump-node = <&L1_I_0>; + qcom,dump-id = <0x60>; + }; + + qcom,l1_i_cache100 { + qcom,dump-node = <&L1_I_100>; + qcom,dump-id = <0x61>; + }; + + qcom,l1_i_cache200 { + qcom,dump-node = <&L1_I_200>; + qcom,dump-id = <0x62>; + }; + + qcom,l1_i_cache300 { + qcom,dump-node = <&L1_I_300>; + qcom,dump-id = <0x63>; + }; + + qcom,l1_i_cache400 { + qcom,dump-node = <&L1_I_400>; + qcom,dump-id = <0x64>; + }; + + qcom,l1_i_cache500 { + qcom,dump-node = <&L1_I_500>; + qcom,dump-id = <0x65>; + }; + + qcom,l1_i_cache600 { + qcom,dump-node = <&L1_I_600>; + qcom,dump-id = <0x66>; + }; + + qcom,l1_i_cache700 { + qcom,dump-node = <&L1_I_700>; + qcom,dump-id = <0x67>; + }; + + qcom,l1_d_cache0 { + qcom,dump-node = <&L1_D_0>; + qcom,dump-id = <0x80>; + }; + + qcom,l1_d_cache100 { + qcom,dump-node = <&L1_D_100>; + qcom,dump-id = <0x81>; + }; + + qcom,l1_d_cache200 { + qcom,dump-node = <&L1_D_200>; + qcom,dump-id = <0x82>; + }; + + qcom,l1_d_cache300 { + qcom,dump-node = <&L1_D_300>; + qcom,dump-id = <0x83>; + }; + + qcom,l1_d_cache400 { + qcom,dump-node = <&L1_D_400>; + qcom,dump-id = <0x84>; + }; + + qcom,l1_d_cache500 { + qcom,dump-node = <&L1_D_500>; + qcom,dump-id = <0x85>; + }; + + qcom,l1_d_cache600 { + qcom,dump-node = <&L1_D_600>; + qcom,dump-id = <0x86>; + }; + + qcom,l1_d_cache700 { + qcom,dump-node = <&L1_D_700>; + qcom,dump-id = <0x87>; + }; + + qcom,l1_i_tlb_dump600 { + qcom,dump-node = <&L1_ITLB_600>; + qcom,dump-id = <0x26>; + }; + + qcom,l1_i_tlb_dump700 { + qcom,dump-node = <&L1_ITLB_700>; + qcom,dump-id = <0x27>; + }; + + qcom,l1_d_tlb_dump600 { + qcom,dump-node = <&L1_DTLB_600>; + qcom,dump-id = <0x46>; + }; + + qcom,l1_d_tlb_dump700 { + qcom,dump-node = <&L1_DTLB_700>; + qcom,dump-id = <0x47>; + }; + + qcom,l2_cache_dump600 { + qcom,dump-node = <&L2_600>; + qcom,dump-id = <0xc6>; + }; + + qcom,l2_cache_dump700 { + qcom,dump-node = <&L2_700>; + qcom,dump-id = <0xc7>; + }; + + qcom,l2_tlb_dump0 { + qcom,dump-node = <&L2_TLB_0>; + qcom,dump-id = <0x120>; + }; + + qcom,l2_tlb_dump100 { + qcom,dump-node = <&L2_TLB_100>; + qcom,dump-id = <0x121>; + }; + + qcom,l2_tlb_dump200 { + qcom,dump-node = <&L2_TLB_200>; + qcom,dump-id = <0x122>; + }; + + qcom,l2_tlb_dump300 { + qcom,dump-node = <&L2_TLB_300>; + qcom,dump-id = <0x123>; + }; + + qcom,l2_tlb_dump400 { + qcom,dump-node = <&L2_TLB_400>; + qcom,dump-id = <0x124>; + }; + + qcom,l2_tlb_dump500 { + qcom,dump-node = <&L2_TLB_500>; + qcom,dump-id = <0x125>; + }; + + qcom,l2_tlb_dump600 { + qcom,dump-node = <&L2_TLB_600>; + qcom,dump-id = <0x126>; + }; + + qcom,l2_tlb_dump700 { + qcom,dump-node = <&L2_TLB_700>; + qcom,dump-id = <0x127>; + }; + + qcom,llcc1_d_cache { + qcom,dump-node = <&LLCC_1>; + qcom,dump-id = <0x140>; + }; + + qcom,llcc2_d_cache { + qcom,dump-node = <&LLCC_2>; + qcom,dump-id = <0x141>; + }; + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + rpmh { + qcom,dump-size = <0x2000000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + tmc_etf { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf0>; + }; + + etf_swao { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etf_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x101>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + }; + + thermal_zones: thermal-zones {}; + + tsens0: tsens@c222000 { + compatible = "qcom,tsens24xx"; + reg = <0xc222000 0x8>, + <0xc263000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts = <0 506 0>, <0 508 0>; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: tsens@c223000 { + compatible = "qcom,tsens24xx"; + reg = <0xc223000 0x8>, + <0xc265000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts = <0 507 0>, <0 509 0>; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + #thermal-sensor-cells = <1>; + }; + + dcc: dcc_v2@10a2000 { + compatible = "qcom,dcc-v2"; + reg = <0x10a2000 0x1000>, + <0x10ae000 0x2000>; + reg-names = "dcc-base", "dcc-ram-base"; + + dcc-ram-offset = <0x6000>; + }; + + qcom,llcc@9200000 { + compatible = "qcom,llcc-core", "syscon", "simple-mfd"; + reg = <0x9200000 0x450000>; + reg-names = "llcc_base"; + qcom,llcc-banks-off = <0x0 0x80000>; + qcom,llcc-broadcast-off = <0x400000>; + + llcc: qcom,sdmmagpie-llcc { + compatible = "qcom,sdmmagpie-llcc"; + #cache-cells = <1>; + max-slices = <32>; + cap-based-alloc-and-pwr-collapse; + }; + + qcom,llcc-perfmon { + compatible = "qcom,llcc-perfmon"; + clocks = <&clock_aop QDSS_CLK>; + clock-names = "qdss_clk"; + }; + + qcom,llcc-erp { + compatible = "qcom,llcc-erp"; + }; + + qcom,llcc-amon { + compatible = "qcom,llcc-amon"; + }; + + LLCC_1: llcc_1_dcache { + qcom,dump-size = <0x6c000>; + }; + + LLCC_2: llcc_2_dcache { + qcom,dump-size = <0x6c000>; + }; + }; + + apps_rsc: mailbox@18220000 { + compatible = "qcom,tcs-drv"; + label = "apps_rsc"; + reg = <0x18220000 0x100>, <0x18220d00 0x3000>; + interrupts = <0 5 0>; + #mbox-cells = <1>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + }; + + disp_rsc: mailbox@af20000 { + compatible = "qcom,tcs-drv"; + label = "display_rsc"; + reg = <0xaf20000 0x100>, <0xaf21c00 0x3000>; + interrupts = <0 129 0>; + #mbox-cells = <1>; + qcom,drv-id = <0>; + qcom,tcs-config = , + , + , + ; + }; + + system_pm { + compatible = "qcom,system-pm"; + mboxes = <&apps_rsc 0>; + }; + + cmd_db: qcom,cmd-db@c3f000c { + compatible = "qcom,cmd-db"; + reg = <0xc3f000c 8>; + }; + + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 3>; + }; + + apcs: syscon@17c0000c { + compatible = "syscon"; + reg = <0x17c0000c 0x4>; + }; + + apcs_glb: mailbox@17c00000 { + compatible = "qcom,sm8150-apcs-hmss-global"; + reg = <0x17c00000 0x1000>; + + #mbox-cells = <1>; + }; + + qcom,msm-cdsp-loader { + compatible = "qcom,cdsp-loader"; + qcom,proc-img-to-load = "cdsp"; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + restrict-access; + }; + + qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,rpc-latency-us = <611>; + qcom,adsp-remoteheap-vmid = <22 37>; + qcom,fastrpc-adsp-audio-pdr; + qcom,fastrpc-adsp-sensors-pdr; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1421 0x0>, + <&apps_smmu 0x1441 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1422 0x0>, + <&apps_smmu 0x1442 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1423 0x0>, + <&apps_smmu 0x1443 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1424 0x0>, + <&apps_smmu 0x1444 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1425 0x0>, + <&apps_smmu 0x1445 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1406 0x0060>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb9 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x1409 0x0060>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb10 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1B23 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb11 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1B24 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb12 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1B25 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb13 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1B26 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb14 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1B27 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb15 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1B28 0x0>; + shared-cb = <3>; + dma-coherent; + }; + }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_modem: modem { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&apcs_glb 12>; + mbox-names = "mpss_smem"; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 0x2>; + }; + + qcom,modem_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>, + <&glink_cdsp>; + }; + }; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&apcs_glb 24>; + mbox-names = "adsp_smem"; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,apr_tal_rpmsg { + qcom,glink-channels = "apr_audio_svc"; + qcom,intents = <0x200 20>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,adsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_cdsp>; + }; + }; + + glink_cdsp: cdsp { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&apcs_glb 4>; + mbox-names = "cdsp_smem"; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12>; + + qcom,cdsp-cdsp-l3-gov { + compatible = "qcom,cdsp-l3"; + qcom,target-dev = <&cdsp_cdsp_l3_lat>; + }; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-latency-us = <44>; + qcom,qos-maxhold-ms = <20>; + qcom,compute-cx-limit-en; + qcom,compute-priority-mode = <2>; + #cooling-cells = <2>; + }; + + msm_hvx_rm: qcom,msm_hvx_rm { + compatible = "qcom,msm-hvx-rm"; + #cooling-cells = <2>; + }; + }; + + qcom,cdsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>; + }; + }; + + glink_spi_xprt_wdsp: wdsp { + qcom,remote-pid = <10>; + transport = "spi"; + tx-descriptors = <0x12000 0x12004>; + rx-descriptors = <0x1200c 0x12010>; + + label = "wdsp"; + qcom,glink-label = "wdsp"; + + qcom,wdsp_ctrl { + qcom,glink-channels = "g_glink_ctrl"; + qcom,intents = <0x400 1>; + }; + + qcom,wdsp_ild { + qcom,glink-channels = + "g_glink_persistent_data_ild"; + }; + + qcom,wdsp_nild { + qcom,glink-channels = + "g_glink_persistent_data_nild"; + }; + + qcom,wdsp_data { + qcom,glink-channels = "g_glink_audio_data"; + qcom,intents = <0x1000 2>; + }; + + qcom,diag_data { + qcom,glink-channels = "DIAG_DATA"; + qcom,intents = <0x4000 2>; + }; + + qcom,diag_ctrl { + qcom,glink-channels = "DIAG_CTRL"; + qcom,intents = <0x4000 1>; + }; + + qcom,diag_cmd { + qcom,glink-channels = "DIAG_CMD"; + qcom,intents = <0x4000 1 >; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qmp_npu0: qcom,qmp-npu-low@9818000 { + compatible = "qcom,qmp-mbox"; + reg = <0x9818000 0x8000>, <0x17c00010 0x4>; + reg-names = "msgram", "irq-reg-base"; + qcom,irq-mask = <0x20>; + interrupts = ; + + label = "npu_qmp_low"; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; + + qmp_npu1: qcom,qmp-npu-high@9818000 { + compatible = "qcom,qmp-mbox"; + reg = <0x9818000 0x8000>, <0x17c00010 0x4>; + reg-names = "msgram", "irq-reg-base"; + qcom,irq-mask = <0x40>; + interrupts = ; + + label = "npu_qmp_high"; + priority = <1>; + mbox-desc-offset = <0x2000>; + #mbox-cells = <1>; + }; + + qmp_aop: qcom,qmp-aop@c300000 { + compatible = "qcom,qmp-mbox"; + reg = <0xc300000 0x1000>, <0x17c0000C 0x4>; + reg-names = "msgram", "irq-reg-base"; + qcom,irq-mask = <0x1>; + interrupts = ; + + label = "aop"; + qcom,early-boot; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + interrupt-parent = <&sleepstate_smp2p_in>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + qcom,ipc = <&apcs 0 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = ; + qcom,ipc = <&apcs 0 26>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts = ; + qcom,ipc = <&apcs 0 6>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_qvrexternal5_out: qcom,smp2p-qvrexternal5-out { + qcom,entry-name = "qvrexternal"; + #qcom,smem-state-cells = <1>; + }; + }; + + sdcc1_ice: sdcc1ice@7C8000 { + compatible = "qcom,ice"; + reg = <0x7C8000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ice_core_clk_src", "ice_core_clk", + "bus_clk", "iface_clk"; + clocks = <&clock_gcc GCC_SDCC1_ICE_CORE_CLK_SRC>, + <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>, + <&clock_gcc GCC_SDCC1_AHB_CLK>, + <&clock_gcc GCC_SDCC1_APPS_CLK>; + qcom,op-freq-hz = <300000000>, <0>, <0>, <0>; + qcom,msm-bus,name = "sdcc_ice_noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 757 0 0>, /* No vote */ + <1 757 1000 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "sdcc"; + }; + + sdhc_1: sdhci@7c4000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>; + reg-names = "hc_mem", "cmdq_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + sdhc-msm-crypto = <&sdcc1_ice>; + + qcom,bus-width = <8>; + qcom,large-address-bus; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 + 192000000 384000000>; + qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; + + qcom,devfreq,freq-table = <50000000 200000000>; + + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <9>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <150 512 0 0>, <1 806 0 0>, + /* 400 KB/s*/ + <150 512 1000 2000>, + <1 806 2000 4000>, + /* 20 MB/s */ + <150 512 25000 50000>, + <1 806 20000 40000>, + /* 25 MB/s */ + <150 512 50000 100000>, + <1 806 30000 60000>, + /* 50 MB/s */ + <150 512 80000 150000>, + <1 806 40000 80000>, + /* 100 MB/s */ + <150 512 100000 200000>, + <1 806 50000 100000>, + /* 200 MB/s */ + <150 512 150000 250000>, + <1 806 80000 120000>, + /* 400 MB/s */ + <150 512 261438 2718822>, + <1 806 300000 1359411>, + /* Max. bandwidth */ + <150 512 1338562 4096000>, + <1 806 1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100750000 200000000 400000000 4294967295>; + + /* PM QoS */ + qcom,pm-qos-irq-type = "affine_irq"; + qcom,pm-qos-irq-latency = <67 67>; + qcom,pm-qos-cpu-groups = <0x3f 0xc0>; + qcom,pm-qos-cmdq-latency-us = <67 67>, <67 67>; + qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>; + + clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, + <&clock_gcc GCC_SDCC1_APPS_CLK>, + <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface_clk", "core_clk", "ice_core_clk"; + + qcom,ice-clk-rates = <300000000 75000000>; + + qcom,scaling-lower-bus-speed-mode = "DDR52"; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x000F642C 0x0 0x0 0x00010800 0x80040868>; + + qcom,nonremovable; + status = "disabled"; + }; + + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x8804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <4>; + qcom,large-address-bus; + + qcom,clk-rates = <400000 20000000 25000000 + 50000000 100000000 202000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", + "SDR104"; + + qcom,devfreq,freq-table = <50000000 202000000>; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <81 512 0 0>, <1 608 0 0>, + /* 400 KB/s*/ + <81 512 1000 2000>, + <1 608 1600 20000>, + /* 20 MB/s */ + <81 512 20000 40000>, + <1 608 20000 40000>, + /* 25 MB/s */ + <81 512 40000 80000>, + <1 608 30000 60000>, + /* 50 MB/s */ + <81 512 60000 120000>, + <1 608 40000 80000>, + /* 100 MB/s */ + <81 512 80000 160000>, + <1 608 50000 100000>, + /* 200 MB/s */ + <81 512 100000 200000>, + <1 608 60000 120000>, + /* Max. bandwidth */ + <81 512 1338562 4096000>, + <1 608 1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100750000 200000000 4294967295>; + + /* PM QoS */ + qcom,pm-qos-irq-type = "affine_irq"; + qcom,pm-qos-irq-latency = <67 67>; + qcom,pm-qos-cpu-groups = <0x3f 0xc0>; + qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>; + + clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>, + <&clock_gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface_clk", "core_clk"; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642C 0x0 0x0 0x00010800 0x80040868>; + + status = "disabled"; + }; + + qcom_seecom: qseecom@86d00000 { + compatible = "qcom,qseecom"; + reg = <0x86d00000 0xe00000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,no-clock-support; + qcom,fde-key-size; + qcom,appsbl-qseecom-support; + qcom,commonlib64-loaded-by-uefi; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_smcinvoke: smcinvoke@86d00000 { + compatible = "qcom,smcinvoke"; + reg = <0x86d00000 0xe00000>; + reg-names = "secapp-region"; + }; + + qcom_rng: qrng@793000 { + compatible = "qcom,msm-rng"; + reg = <0x793000 0x1000>; + qcom,msm-rng-iface-clk; + qcom,no-qrng-config; + qcom,msm-bus,name = "msm-rng-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 618 0 0>, /* No vote */ + <1 618 0 300000>; /* 75 MHz */ + clocks = <&clock_gcc GCC_PRNG_AHB_CLK>; + clock-names = "iface_clk"; + }; + + ufs_ice: ufsice@1d90000 { + compatible = "qcom,ice"; + reg = <0x1d90000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk", "bus_clk", + "iface_clk", "ice_core_clk"; + clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>, + <&clock_gcc GCC_UFS_PHY_AHB_CLK>, + <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>; + qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; + vdd-hba-supply = <&ufs_phy_gdsc>; + qcom,msm-bus,name = "ufs_ice_noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 650 0 0>, /* No vote */ + <1 650 1000 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "ufs"; + }; + + ufsphy_mem: ufsphy_mem@1d87000 { + reg = <0x1d87000 0xddc>; /* PHY regs */ + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <1>; + + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>, + <&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x3000>; + interrupts = <0 265 0>; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + ufs-qcom-crypto = <&ufs_ice>; + + lanes-per-direction = <1>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + spm-level = <5>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks = + <&clock_gcc GCC_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_UFS_PHY_AHB_CLK>, + <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + + qcom,msm-bus,name = "ufshc_mem"; + qcom,msm-bus,num-cases = <12>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <123 512 0 0>, <1 757 0 0>, /* No vote */ + <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */ + <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */ + <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */ + <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */ + <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */ + <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */ + <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */ + <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */ + <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */ + <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */ + <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", + "MAX"; + + /* PM QoS */ + qcom,pm-qos-cpu-groups = <0x3f 0xC0>; + qcom,pm-qos-cpu-group-latency-us = <67 67>; + qcom,pm-qos-default-cpu = <0>; + + pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; + pinctrl-0 = <&ufs_dev_reset_assert>; + pinctrl-1 = <&ufs_dev_reset_deassert>; + + resets = <&clock_gcc GCC_UFS_PHY_BCR>; + reset-names = "core_reset"; + non-removable; + + status = "disabled"; + }; + + qcom,lpass@62400000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x62400000 0x00100>; + + vdd_lpi_cx-supply = <&L8A_LEVEL>; + qcom,vdd_cx-uV-uA = ; + vdd_lpi_mx-supply = <&L7A_LEVEL>; + qcom,vdd_mx-uV-uA = ; + qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx"; + + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <1>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,sysmon-id = <1>; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + + /* Inputs from lpass */ + interrupts-extended = <&pdc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,err-ready", + "qcom,proxy-unvote", + "qcom,stop-ack"; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "adsp-pil"; + }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x200000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + qcom,guard-memory; + }; + + qcom_cedev: qcedev@1de0000 { + compatible = "qcom,qcedev"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 272 0>; + qcom,bam-pipe-pair = <3>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,bam-ee = <0>; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <125 512 0 0>, + <125 512 393600 393600>; + qcom,smmu-s1-enable; + qcom,no-clock-support; + iommus = <&apps_smmu 0x0506 0x0011>, + <&apps_smmu 0x0516 0x0011>; + }; + + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; + + qcom_crypto: qcrypto@1de0000 { + compatible = "qcom,qcrypto"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 272 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + qcom,clk-mgmt-sus-res; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <125 512 0 0>, + <125 512 393600 393600>; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-aead-algo; + qcom,use-sw-hmac-algo; + qcom,smmu-s1-enable; + qcom,no-clock-support; + iommus = <&apps_smmu 0x0504 0x0011>, + <&apps_smmu 0x0514 0x0011>; + }; + + qcom_tzlog: tz-log@146aa720 { + compatible = "qcom,tz-log"; + reg = <0x146aa720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + + spmi_bus: qcom,spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0x1100>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>, + <0xe700000 0xa0000>, + <0xc40a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + qcom,turing@8300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x8300000 0x100000>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + vdd_mx-supply = <&VDD_MX_LEVEL>; + qcom,vdd_mx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx", "vdd_mx"; + + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <18>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <601>; + qcom,sysmon-id = <7>; + qcom,ssctl-instance-id = <0x17>; + qcom,firmware-name = "cdsp"; + memory-region = <&pil_cdsp_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + + /* Inputs from turing */ + interrupts-extended = <&pdc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,err-ready", + "qcom,proxy-unvote", + "qcom,stop-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "cdsp-pil"; + }; + + pil_modem: qcom,mss@4080000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x4080000 0x100>; + + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + vdd_mss-supply = <&VDD_MSS_LEVEL>; + qcom,vdd_mss-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx", "vdd_mss"; + + qcom,firmware-name = "modem"; + memory-region = <&pil_modem_mem>; + qcom,proxy-timeout-ms = <10000>; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x12>; + qcom,pas-id = <4>; + qcom,smem-id = <421>; + qcom,signal-aop; + qcom,minidump-id = <3>; + qcom,complete-ramdump; + + /* Inputs from mss */ + interrupts-extended = <&pdc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_NONE>, + <&modem_smp2p_in 1 IRQ_TYPE_NONE>, + <&modem_smp2p_in 2 IRQ_TYPE_NONE>, + <&modem_smp2p_in 3 IRQ_TYPE_NONE>, + <&modem_smp2p_in 7 IRQ_TYPE_NONE>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,err-ready", + "qcom,proxy-unvote", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "mss-pil"; + }; + + qcom,venus@aae0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xaae0000 0x4000>; + + vdd-supply = <&mvsc_gdsc>; + qcom,proxy-reg-names = "vdd"; + + clocks = <&clock_videocc VIDEO_CC_XO_CLK>, + <&clock_videocc VIDEO_CC_MVSC_CORE_CLK>, + <&clock_videocc VIDEO_CC_IRIS_AHB_CLK>; + clock-names = "xo", "core", "ahb"; + qcom,proxy-clock-names = "xo", "core", "ahb"; + + qcom,core-freq = <200000000>; + qcom,ahb-freq = <200000000>; + + qcom,pas-id = <9>; + qcom,msm-bus,name = "pil-venus"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <63 512 0 0>, + <63 512 0 304000>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&pil_video_mem>; + }; + + qcom,npu@0x9800000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x9800000 0x800000>; + + status = "ok"; + qcom,pas-id = <23>; + qcom,firmware-name = "npu"; + memory-region = <&npu_mem>; + }; + + icnss: qcom,icnss@18800000 { + compatible = "qcom,icnss"; + reg = <0x18800000 0x800000>, + <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa"; + iommus = <&apps_smmu 0x0240 0x1>; + interrupts = <0 414 0 /* CE0 */ >, + <0 415 0 /* CE1 */ >, + <0 416 0 /* CE2 */ >, + <0 417 0 /* CE3 */ >, + <0 418 0 /* CE4 */ >, + <0 419 0 /* CE5 */ >, + <0 420 0 /* CE6 */ >, + <0 421 0 /* CE7 */ >, + <0 422 0 /* CE8 */ >, + <0 423 0 /* CE9 */ >, + <0 424 0 /* CE10 */ >, + <0 425 0 /* CE11 */ >; + qcom,smmu-s1-bypass; + qcom,wlan-msa-memory = <0x100000>; + qcom,wlan-msa-fixed-region = <&wlan_msa_mem>; + vdd-cx-mx-supply = <&pm6150_l9>; + vdd-1.8-xo-supply = <&pm6150l_l1>; + vdd-1.3-rfa-supply = <&pm6150l_l2>; + vdd-3.3-ch0-supply = <&pm6150l_l10>; + qcom,vdd-cx-mx-config = <640000 640000>; + qcom,smp2p_map_wlan_1_in { + interrupts-extended = <&smp2p_wlan_1_in 0 0>, + <&smp2p_wlan_1_in 1 0>; + interrupt-names = "qcom,smp2p-force-fatal-error", + "qcom,smp2p-early-crash-ind"; + }; + + }; + + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + qcom,ipa-platform-type-msm; + qcom,ipa-advertise-sg-support; + qcom,ipa-napi-enable; + }; + + ipa_hw: qcom,ipa@1e00000 { + compatible = "qcom,ipa"; + reg = <0x1e00000 0x34000>, + <0x1e04000 0x2c000>; + reg-names = "ipa-base", "gsi-base"; + interrupts = <0 311 0>, <0 432 0>; + interrupt-names = "ipa-irq", "gsi-irq"; + qcom,ipa-hw-ver = <16>; /* IPA core version = IPAv4.2 */ + qcom,ipa-hw-mode = <0>; + qcom,ee = <0>; + qcom,use-ipa-tethering-bridge; + qcom,modem-cfg-emb-pipe-flt; + qcom,ipa-wdi2; + qcom,ipa-wdi2_over_gsi; + qcom,ipa-fltrt-not-hashable; + qcom,use-64-bit-dma-mask; + qcom,arm-smmu; + qcom,smmu-fast-map; + qcom,use-ipa-pm; + qcom,bandwidth-vote-for-ipa; + qcom,ipa-endp-delay-wa; + qcom,msm-bus,name = "ipa"; + qcom,msm-bus,num-cases = <5>; + qcom,msm-bus,num-paths = <4>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + , + , + , + , + /* SVS2 */ + , + , + , + , + /* SVS */ + , + , + , + , + /* NOMINAL */ + , + , + , + , + /* TURBO */ + , + , + , + ; + qcom,bus-vector-names = + "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; + qcom,throughput-threshold = <310 600 1000>; + qcom,scaling-exceptions = <>; + + /* smp2p information */ + qcom,smp2p_map_ipa_1_out { + compatible = "qcom,smp2p-map-ipa-1-out"; + qcom,smem-states = <&smp2p_ipa_1_out 0>; + qcom,smem-state-names = "ipa-smp2p-out"; + }; + + qcom,smp2p_map_ipa_1_in { + compatible = "qcom,smp2p-map-ipa-1-in"; + interrupts-extended = <&smp2p_ipa_1_in 0 0>; + interrupt-names = "ipa-smp2p-in"; + }; + }; + + llcc_pmu: llcc-pmu@90cc000 { + compatible = "qcom,qcom-llcc-pmu"; + reg = <0x090cc000 0x300>; + reg-names = "lagg-base"; + }; + + llcc_bw_opp_table: llcc-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */ + BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */ + BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */ + BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */ + BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */ + }; + + cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6300 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x90b6300 0x300>, <0x90b6200 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_cpu_llcc_bw>; + qcom,count-unit = <0x10000>; + }; + + ddr_bw_opp_table: ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ + BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ + BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ + BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ + BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ + BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ + BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ + BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */ + BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ + BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ + }; + + cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@90cd000 { + compatible = "qcom,bimc-bwmon5"; + reg = <0x90cd000 0x1000>; + reg-names = "base"; + interrupts = ; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_llcc_ddr_bw>; + qcom,count-unit = <0x10000>; + }; + + suspendable_ddr_bw_opp_table: suspendable-ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 0, 4); /* 0 MB/s */ + BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ + BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ + BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ + BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ + BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ + BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ + BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ + BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */ + BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ + BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ + }; + + cdsp_cdsp_l3_lat: qcom,cdsp-cdsp-l3-lat { + compatible = "devfreq-simple-dev"; + clock-names = "devfreq_clk"; + clocks = <&clock_cpucc L3_MISC_VOTE_CLK>; + governor = "powersave"; + }; + + cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { + compatible = "devfreq-simple-dev"; + clock-names = "devfreq_clk"; + clocks = <&clock_cpucc L3_CLUSTER0_VOTE_CLK>; + governor = "performance"; + }; + + cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,target-dev = <&cpu0_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = + < 768000 300000000 >, + < 1017600 556800000 >, + < 1248000 768000000 >, + < 1497000 940800000 >, + < 1804800 1459200000 >; + }; + + cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat { + compatible = "devfreq-simple-dev"; + clock-names = "devfreq_clk"; + clocks = <&clock_cpucc L3_CLUSTER1_VOTE_CLK>; + governor = "performance"; + }; + + cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,target-dev = <&cpu6_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = + < 1094000 556800000 >, + < 1324000 768000000 >, + < 1708800 1190400000 >, + < 1939000 1382400000 >, + < 2438400 1459200000 >; + }; + + cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,target-dev = <&cpu0_cpu_llcc_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,core-dev-table = + < 1324000 MHZ_TO_MBPS(300, 16) >, + < 1497000 MHZ_TO_MBPS(466, 16) >, + < 1804800 MHZ_TO_MBPS(600, 16) >; + }; + + cpu6_cpu_llcc_lat: qcom,cpu6-cpu-llcc-lat { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu6_cpu_llcc_latmon: qcom,cpu6-cpu-llcc-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,target-dev = <&cpu6_cpu_llcc_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,core-dev-table = + < 806000 MHZ_TO_MBPS(300, 16) >, + < 1094000 MHZ_TO_MBPS(466, 16) >, + < 1324000 MHZ_TO_MBPS(600, 16) >, + < 1708800 MHZ_TO_MBPS(806, 16) >, + < 2438400 MHZ_TO_MBPS(933, 16) >; + }; + + cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,target-dev = <&cpu0_llcc_ddr_lat>; + qcom,cachemiss-ev = <0x1000>; + qcom,core-dev-table = + < 768000 MHZ_TO_MBPS( 300, 4) >, + < 1017600 MHZ_TO_MBPS( 451, 4) >, + < 1248000 MHZ_TO_MBPS( 547, 4) >, + < 1497000 MHZ_TO_MBPS( 768, 4) >, + < 1804800 MHZ_TO_MBPS(1017, 4) >; + }; + + cpu6_llcc_ddr_lat: qcom,cpu6-llcc-ddr-lat { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu6_llcc_ddr_latmon: qcom,cpu6-llcc-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,target-dev = <&cpu6_llcc_ddr_lat>; + qcom,cachemiss-ev = <0x1000>; + qcom,core-dev-table = + < 806000 MHZ_TO_MBPS( 451, 4) >, + < 1094000 MHZ_TO_MBPS( 547, 4) >, + < 1324000 MHZ_TO_MBPS(1017, 4) >, + < 1708800 MHZ_TO_MBPS(1555, 4) >, + < 2438400 MHZ_TO_MBPS(1804, 4) >; + }; + + cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_computemon: qcom,cpu0-computemon { + compatible = "qcom,arm-cpu-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 768000 MHZ_TO_MBPS( 300, 4) >, + < 1248000 MHZ_TO_MBPS( 451, 4) >, + < 1497000 MHZ_TO_MBPS( 547, 4) >, + < 1804800 MHZ_TO_MBPS( 768,4) >; + }; + + cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu6_computemon: qcom,cpu6-computemon { + compatible = "qcom,arm-cpu-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,target-dev = <&cpu6_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1094000 MHZ_TO_MBPS( 300, 4) >, + < 1324000 MHZ_TO_MBPS( 547, 4) >, + < 1552200 MHZ_TO_MBPS( 768, 4) >, + < 1708000 MHZ_TO_MBPS(1017, 4) >, + < 2438400 MHZ_TO_MBPS(1804, 4) >; + }; + + npu_npu_ddr_bw: qcom,npu-npu-ddr-bw { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = ; + operating-points-v2 = <&suspendable_ddr_bw_opp_table>; + }; + + npu_npu_ddr_bwmon: qcom,npu-npu-ddr-bwmon@9960300 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x9960300 0x300>, <0x9960200 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&npu_npu_ddr_bw>; + qcom,count-unit = <0x10000>; + }; + + ipa_smmu_ap: ipa_smmu_ap { + compatible = "qcom,ipa-smmu-ap-cb"; + qcom,smmu-s1-bypass; + iommus = <&apps_smmu 0x520 0x0>; + qcom,iova-mapping = <0x20000000 0x40000000>; + /* modem tables in IMEM */ + qcom,additional-mapping = <0x146A8000 0x146A8000 0x2000>; + }; + + ipa_smmu_wlan: ipa_smmu_wlan { + compatible = "qcom,ipa-smmu-wlan-cb"; + qcom,smmu-s1-bypass; + iommus = <&apps_smmu 0x521 0x0>; + /* ipa-uc ram */ + qcom,additional-mapping = <0x1e60000 0x1e60000 0x80000>; + }; + + ipa_smmu_uc: ipa_smmu_uc { + compatible = "qcom,ipa-smmu-uc-cb"; + qcom,smmu-s1-bypass; + iommus = <&apps_smmu 0x522 0x0>; + qcom,iova-mapping = <0x40400000 0x1fc00000>; + }; + + qcom,ipa_fws { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0xf>; + qcom,firmware-name = "ipa_fws"; + qcom,pil-force-shutdown; + memory-region = <&pil_ipa_fw_mem>; + }; + + keepalive_opp_table: keepalive-opp-table { + compatible = "operating-points-v2"; + opp-1 { + opp-hz = /bits/ 64 < 1 >; + }; + }; + + snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <1 627>; + qcom,active-only; + status = "ok"; + operating-points-v2 = <&keepalive_opp_table>; + }; + + bus_proxy_client: qcom,bus_proxy_client { + compatible = "qcom,bus-proxy-client"; + qcom,msm-bus,name = "bus-proxy-client"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + qcom,msm-bus,active-only; + status = "ok"; + }; + + demux { + compatible = "qcom,demux"; + }; + + cx_ipeak_lm: cx_ipeak@01fed000 { + compatible = "qcom,cx-ipeak-v2"; + reg = <0x1fed000 0x8008>; + }; +}; + +#include "sdmmagpie-gdsc.dtsi" +#include "sdmmagpie-bus.dtsi" +#include "sdmmagpie-qupv3.dtsi" +#include "sdmmagpie-vidc.dtsi" +#include "sdmmagpie-sde-pll.dtsi" +#include "sdmmagpie-sde.dtsi" +#include "sdmmagpie-camera.dtsi" +#include "msm-rdbg.dtsi" +#include "msm-qvr-external.dtsi" + +&pcie_0_gdsc { + status = "ok"; +}; + +&usb30_prim_gdsc { + status = "ok"; +}; + +&ufs_phy_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu1_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu2_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc { + status = "ok"; +}; + +&bps_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&ife_0_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + status = "ok"; +}; + +&ife_1_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + status = "ok"; +}; + +&ipe_0_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&ipe_1_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&titan_top_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + status = "ok"; +}; + +&mdss_core_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_DISP_AHB_CLK>; + status = "ok"; +}; + +&gpu_cx_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_gx_gdsc { + clock-names = "core_root_clk"; + clocks = <&clock_gpucc GPU_CC_GX_GFX3D_CLK_SRC>; + qcom,force-enable-root-clk; + parent-supply = <&VDD_GFX_LEVEL>; + qcom,reset-aon-logic; + status = "ok"; +}; + +&mvsc_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; + status = "ok"; +}; + +&mvs0_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&mvs1_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&npu_core_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_NPU_CFG_AHB_CLK>; + status = "ok"; +}; + +#include "sdmmagpie-ion.dtsi" +#include "msm-arm-smmu-sdmmagpie.dtsi" +#include "sdmmagpie-pm.dtsi" +#include "pm6150.dtsi" +#include "pm6150l.dtsi" +#include "sdmmagpie-pinctrl.dtsi" +#include "pm8009.dtsi" +#include "sdmmagpie-regulator.dtsi" +#include "sdmmagpie-camera.dtsi" +#include "sdmmagpie-coresight.dtsi" +#include "sdmmagpie-usb.dtsi" +#include "sdmmagpie-thermal.dtsi" + +&qupv3_se9_i2c { + status = "ok"; + fsa4480: fsa4480@43 { + compatible = "qcom,fsa4480-i2c"; + reg = <0x43>; + pinctrl-names = "default"; + pinctrl-0 = <&fsa_usbc_ana_en>; + }; +}; + +#include "sdmmagpie-audio.dtsi" +#include "sdmmagpie-gpu.dtsi" + +&usb0 { + extcon = <&pm6150_pdphy>, <&pm6150_charger>, <&eud>; +}; + +&pm6150_vadc { + rf_pa0_therm { + reg = ; + label = "rf_pa0_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + rf_pa1_therm { + reg = ; + label = "rf_pa1_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + quiet_therm { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm6150_adc_tm { + io-channels = <&pm6150_vadc ADC_XO_THERM_PU2>, + <&pm6150_vadc ADC_AMUX_THM2_PU2>, + <&pm6150_vadc ADC_AMUX_THM3_PU2>, + <&pm6150_vadc ADC_AMUX_THM4_PU2>; + + /* Channel nodes */ + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + rf_pa0_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + rf_pa1_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + quiet_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm6150l_vadc { + pinctrl-names = "default"; + pinctrl-0 = <&nvm_therm_default>; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + smb_therm { + reg = ; + label = "smb_therm"; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + camera_ftherm { + reg = ; + label = "camera_ftherm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + nvm_therm { + reg = ; + label = "nvm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm6150l_gpios { + nvm_therm { + nvm_therm_default: nvm_therm_default { + pins = "gpio10"; + bias-high-impedance; + }; + }; +}; + +&pm6150l_adc_tm { + io-channels = <&pm6150l_vadc ADC_AMUX_THM1_PU2>, + <&pm6150l_vadc ADC_AMUX_THM3_PU2>, + <&pm6150l_vadc ADC_GPIO4_PU2>; + + /* Channel nodes */ + conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + camera_ftherm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + nvm_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&msm_vidc0 { + qcom,cx-ipeak-data = <&cx_ipeak_lm 5>; + qcom,clock-freq-threshold = <533000000>; +}; + +#include "sdmmagpie-npu.dtsi" diff --git a/arch/arm/boot/dts/qcom/sdmmagpiep-atp-overlay.dts b/arch/arm/boot/dts/qcom/sdmmagpiep-atp-overlay.dts new file mode 100644 index 000000000000..fc84bd38a11c --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpiep-atp-overlay.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "sdmmagpie-atp.dtsi" + +/ { + model = "ATP"; + compatible = "qcom,sdmmagpiep-atp", "qcom,sdmmagpiep", "qcom,atp"; + qcom,msm-id = <366 0x0>; + qcom,board-id = <33 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpiep-atp.dts b/arch/arm/boot/dts/qcom/sdmmagpiep-atp.dts new file mode 100644 index 000000000000..48d4c02b8e85 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpiep-atp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdmmagpiep.dtsi" +#include "sdmmagpie-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDMMAGPIEP PM6150 ATP"; + compatible = "qcom,sdmmagpiep-atp", "qcom,sdmmagpiep", "qcom,atp"; + qcom,board-id = <33 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpiep-idp-overlay.dts b/arch/arm/boot/dts/qcom/sdmmagpiep-idp-overlay.dts new file mode 100644 index 000000000000..f5c3fcddd2b3 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpiep-idp-overlay.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "sdmmagpie-idp.dtsi" + +/ { + model = "IDP"; + compatible = "qcom,sdmmagpiep-idp", "qcom,sdmmagpiep", "qcom,idp"; + qcom,msm-id = <366 0x0>; + qcom,board-id = <34 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpiep-idp.dts b/arch/arm/boot/dts/qcom/sdmmagpiep-idp.dts new file mode 100644 index 000000000000..30bdd6eb4516 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpiep-idp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdmmagpiep.dtsi" +#include "sdmmagpie-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDMMAGPIEP PM6150 IDP"; + compatible = "qcom,sdmmagpiep-idp", "qcom,sdmmagpiep", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpiep-qrd-overlay.dts b/arch/arm/boot/dts/qcom/sdmmagpiep-qrd-overlay.dts new file mode 100644 index 000000000000..2172498a631f --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpiep-qrd-overlay.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include + +#include "sdmmagpie-qrd.dtsi" + +/ { + model = "QRD"; + compatible = "qcom,sdmmagpiep-qrd", "qcom,sdmmagpiep", "qcom,qrd"; + qcom,msm-id = <366 0>; + qcom,board-id = <11 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpiep-qrd.dts b/arch/arm/boot/dts/qcom/sdmmagpiep-qrd.dts new file mode 100644 index 000000000000..77df22dedd4f --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpiep-qrd.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdmmagpiep.dtsi" +#include "sdmmagpie-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDMMAGPIEP PM6150 QRD"; + compatible = "qcom,sdmmagpiep-qrd", "qcom,sdmmagpiep", "qcom,qrd"; + qcom,board-id = <11 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpiep.dts b/arch/arm/boot/dts/qcom/sdmmagpiep.dts new file mode 100644 index 000000000000..9f63a0faaf57 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpiep.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdmmagpiep.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDMMAGPIEP SoC"; + compatible = "qcom,sdmmagpiep"; + qcom,pmic-name = "PM6150"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmmagpiep.dtsi b/arch/arm/boot/dts/qcom/sdmmagpiep.dtsi new file mode 100644 index 000000000000..491e6ebd9af7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmmagpiep.dtsi @@ -0,0 +1,19 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdmmagpie.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDMMAGPIEP"; + qcom,msm-name = "SDMMAGPIEP"; + qcom,msm-id = <366 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/sdmshrike-audio-overlay.dtsi new file mode 100644 index 000000000000..4e0d024e8494 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-audio-overlay.dtsi @@ -0,0 +1,307 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm8150-wcd.dtsi" +#include "msm-wsa881x.dtsi" +#include + +&snd_9360 { + qcom,audio-routing = + "AIF4 VI", "MCLK", + "MADINPUT", "MCLK", + "AMIC3", "MIC BIAS2", + "AMIC4", "MIC BIAS2", + "AMIC5", "MIC BIAS3", + "MIC BIAS3", "Handset Mic", + "AMIC2", "AQT MIC BIAS1", + "AQT MIC BIAS1", "Headset Mic", + "AQT AMIC3", "AQT MIC BIAS1", + "AQT AMIC1", "AQT MIC BIAS1", + "AQT MIC BIAS1", "ANCLeft Headset Mic", + "AQT AMIC2", "AQT MIC BIAS1", + "AQT MIC BIAS1", "ANCRight Headset Mic", + "DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "DMIC4", "MIC BIAS4", + "MIC BIAS4", "Digital Mic4", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT"; + + qcom,pahu-ext-clk-freq = <19200000>; + + asoc-codec = <&stub_codec>, <&ext_disp_audio_codec>; + asoc-codec-names = "msm-stub-codec.1", + "msm-ext-disp-audio-codec-rx"; + + qcom,wsa-max-devs = <2>; + qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>, + <&wsa881x_0213>, <&wsa881x_0214>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", + "SpkrLeft", "SpkrRight"; +}; + +&snd_934x { + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "hifi amp", "LINEOUT1", + "hifi amp", "LINEOUT2", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC3", "MIC BIAS2", + "MIC BIAS2", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2", + "MIC BIAS2", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS3", + "MIC BIAS3", "Handset Mic", + "DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "DMIC4", "MIC BIAS4", + "MIC BIAS4", "Digital Mic4", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT"; + + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,msm-mbhc-hs-mic-max-threshold-mv = <1700>; + qcom,msm-mbhc-hs-mic-min-threshold-mv = <50>; + qcom,hph-en0-gpio = <&tavil_hph_en0>; + qcom,hph-en1-gpio = <&tavil_hph_en1>; + qcom,tavil-mclk-clk-freq = <9600000>; + + asoc-codec = <&stub_codec>, <&ext_disp_audio_codec>; + asoc-codec-names = "msm-stub-codec.1", + "msm-ext-disp-audio-codec-rx"; + + qcom,wsa-max-devs = <2>; + qcom,wsa-devs = <&wsa881x_70211>, <&wsa881x_70212>, + <&wsa881x_70213>, <&wsa881x_70214>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", + "SpkrLeft", "SpkrRight"; +}; + +&soc { + wcd9xxx_intc: wcd9xxx-irq { + status = "ok"; + compatible = "qcom,wcd9xxx-irq"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&tlmm>; + qcom,gpio-connect = <&tlmm 123 0>; + pinctrl-names = "default"; + pinctrl-0 = <&wcd_intr_default>; + }; + + clock_audio: audio_ext_clk { + status = "ok"; + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = <2>; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <278>; + qcom,use-pinctrl = <1>; + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&quin_mi2s_mclk_active>; + pinctrl-1 = <&quin_mi2s_mclk_sleep>; + #clock-cells = <1>; + }; + + wcd_rst_gpio: msm_cdc_pinctrl@143 { + compatible = "qcom,msm-cdc-pinctrl"; + qcom,cdc-rst-n-gpio = <&tlmm 143 0>; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_reset_active>; + pinctrl-1 = <&cdc_reset_sleep>; + }; + + qocm,wcd-dsp-glink { + compatible = "qcom,wcd-dsp-glink"; + qcom,wdsp-channels = "g_glink_ctrl", + "g_glink_persistent_data_nild", + "g_glink_persistent_data_ild", + "g_glink_audio_data"; + }; + + pahu_wdsp: wcd-dsp-mgr@1 { + compatible = "qcom,wcd-dsp-mgr"; + qcom,wdsp-components = <&wcd9360_cdc 0>, + <&wcd_spi_0 1>, + <&glink_spi_xprt_wdsp 2>; + qcom,img-filename = "cpe_9360"; + }; + + tavil_wdsp: wcd-dsp-mgr@2 { + compatible = "qcom,wcd-dsp-mgr"; + qcom,wdsp-components = <&wcd934x_cdc 0>, + <&tavil_spi_0 1>, + <&glink_spi_xprt_wdsp 2>; + qcom,img-filename = "cpe_9340"; + }; + + clock_audio_lnbb: audio_ext_clk_lnbb { + status = "ok"; + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = <1>; + clock-names = "osr_clk"; + clocks = <&clock_rpmh RPMH_LN_BB_CLK2>; + #clock-cells = <1>; + }; +}; + +&slim_aud { + wcd9360_cdc: pahu_codec { + compatible = "qcom,pahu-slim-pgd"; + elemental-addr = [00 01 C0 02 17 02]; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 + 30 31>; + + qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; + + clock-names = "wcd_clk"; + clocks = <&clock_audio 0>; + + cdc-vdd-ldo-rxtx-supply = <&pm8150_1_s5>; + qcom,cdc-vdd-ldo-rxtx-voltage = <2040000 2040000>; + qcom,cdc-vdd-ldo-rxtx-current = <30000>; + + cdc-vdd-buck-sido-supply = <&pm8150_1_s4>; + qcom,cdc-vdd-buck-sido-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-sido-current = <228000>; + + cdc-vdd-px-supply = <&pm8150_1_s4>; + qcom,cdc-vdd-px-voltage = <1800000 1800000>; + qcom,cdc-vdd-px-current = <15000>; + + cdc-vdd-mic-bias-supply = <&pm8150c_bob>; + qcom,cdc-vdd-mic-bias-voltage = <3300000 3300000>; + qcom,cdc-vdd-mic-bias-current = <16800>; + + cdc-vdd-pa-supply = <&pm8150c_bob>; + qcom,cdc-vdd-pa-voltage = <3300000 3300000>; + qcom,cdc-vdd-pa-current = <230000>; + + qcom,cdc-static-supplies = "cdc-vdd-buck-sido", + "cdc-vdd-px", + "cdc-vdd-mic-bias", + "cdc-vdd-pa"; + qcom,cdc-on-demand-supplies = "cdc-vdd-ldo-rxtx"; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; + + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-slim-ifd = "pahu-slim-ifd"; + qcom,cdc-slim-ifd-elemental-addr = [00 00 C0 02 17 02]; + qcom,cdc-dmic-sample-rate = <4800000>; + qcom,cdc-mad-dmic-rate = <600000>; + + qcom,wdsp-cmpnt-dev-name = "pahu_codec"; + + wcd_spi_0: wcd_spi { + compatible = "qcom,wcd-spi-v2"; + qcom,master-bus-num = <0>; + qcom,chip-select = <0>; + qcom,max-frequency = <24000000>; + qcom,mem-base-addr = <0x100000>; + }; + + }; + + wcd934x_cdc: tavil_codec { + compatible = "qcom,tavil-slim-pgd"; + elemental-addr = [00 01 50 02 17 02]; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 + 30 31>; + + qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; + + clock-names = "wcd_clk"; + clocks = <&clock_audio_lnbb 0>; + + cdc-vdd-buck-supply = <&pm8150_1_s4>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <650000>; + + cdc-buck-sido-supply = <&pm8150_1_s4>; + qcom,cdc-buck-sido-voltage = <1800000 1800000>; + qcom,cdc-buck-sido-current = <500000>; + + cdc-vdd-tx-h-supply = <&pm8150_1_s4>; + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-tx-h-current = <25000>; + + cdc-vdd-rx-h-supply = <&pm8150_1_s4>; + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-rx-h-current = <25000>; + + cdc-vddpx-1-supply = <&pm8150_1_s4>; + qcom,cdc-vddpx-1-voltage = <1800000 1800000>; + qcom,cdc-vddpx-1-current = <10000>; + + cdc-vdd-3v3-supply = <&pm8150c_bob>; + qcom,cdc-vdd-3v3-voltage = <3300000 3300000>; + qcom,cdc-vdd-3v3-current = <16800>; + + qcom,cdc-static-supplies = "cdc-vdd-buck", + "cdc-buck-sido", + "cdc-vdd-tx-h", + "cdc-vdd-rx-h", + "cdc-vddpx-1", + "cdc-vdd-3v3"; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; + + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-slim-ifd = "tavil-slim-ifd"; + qcom,cdc-slim-ifd-elemental-addr = [00 00 50 02 17 02]; + qcom,cdc-dmic-sample-rate = <4800000>; + qcom,cdc-mad-dmic-rate = <600000>; + + qcom,wdsp-cmpnt-dev-name = "tavil_codec"; + + tavil_spi_0: wcd_spi { + compatible = "qcom,wcd-spi-v2"; + qcom,master-bus-num = <0>; + qcom,chip-select = <0>; + qcom,max-frequency = <24000000>; + qcom,mem-base-addr = <0x100000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-bus.dtsi b/arch/arm/boot/dts/qcom/sdmshrike-bus.dtsi new file mode 100644 index 000000000000..1996ad1d6c19 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-bus.dtsi @@ -0,0 +1,2148 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + ad_hoc_bus: ad-hoc-bus { + compatible = "qcom,msm-bus-device"; + reg = <0x016E0000 0x40000>, + <0x1700000 0x40000>, + <0x1500000 0x40000>, + <0x9160000 0x40000>, + <0x9680000 0x40000>, + <0x9680000 0x40000>, + <0x1740000 0x40000>, + <0x1620000 0x40000>, + <0x1620000 0x40000>, + <0x1620000 0x40000>, + <0x9800000 0x40000>; + + reg-names = "aggre1_noc-base", "aggre2_noc-base", + "config_noc-base", "dc_noc-base", + "mc_virt-base", "gem_noc-base", + "mmss_noc-base", "system_noc-base", "ipa_virt-base", + "camnoc_virt-base", "compute_noc-base"; + + mbox-names = "apps_rsc", "disp_rsc"; + mboxes = <&apps_rsc 0 &disp_rsc 0>; + + /*RSCs*/ + rsc_apps: rsc-apps { + cell-id = ; + label = "apps_rsc"; + qcom,rsc-dev; + qcom,req_state = <2>; + }; + + rsc_disp: rsc-disp { + cell-id = ; + label = "disp_rsc"; + qcom,rsc-dev; + qcom,req_state = <3>; + }; + + /*BCMs*/ + bcm_acv: bcm-acv { + cell-id = ; + label = "ACV"; + qcom,bcm-name = "ACV"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_alc: bcm-alc { + cell-id = ; + label = "ALC"; + qcom,bcm-name = "ALC"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_mc0: bcm-mc0 { + cell-id = ; + label = "MC0"; + qcom,bcm-name = "MC0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sh0: bcm-sh0 { + cell-id = ; + label = "SH0"; + qcom,bcm-name = "SH0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_mm0: bcm-mm0 { + cell-id = ; + label = "MM0"; + qcom,bcm-name = "MM0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_co0: bcm-co0 { + cell-id = ; + label = "CO0"; + qcom,bcm-name = "CO0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_ce0: bcm-ce0 { + cell-id = ; + label = "CE0"; + qcom,bcm-name = "CE0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_cn0: bcm-cn0 { + cell-id = ; + label = "CN0"; + qcom,bcm-name = "CN0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_mm1: bcm-mm1 { + cell-id = ; + label = "MM1"; + qcom,bcm-name = "MM1"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_qup0: bcm-qup0 { + cell-id = ; + label = "QUP0"; + qcom,bcm-name = "QUP0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sh2: bcm-sh2 { + cell-id = ; + label = "SH2"; + qcom,bcm-name = "SH2"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_mm2: bcm-mm2 { + cell-id = ; + label = "MM2"; + qcom,bcm-name = "MM2"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sh3: bcm-sh3 { + cell-id = ; + label = "SH3"; + qcom,bcm-name = "SH3"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn0: bcm-sn0 { + cell-id = ; + label = "SN0"; + qcom,bcm-name = "SN0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn1: bcm-sn1 { + cell-id = ; + label = "SN1"; + qcom,bcm-name = "SN1"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn2: bcm-sn2 { + cell-id = ; + label = "SN2"; + qcom,bcm-name = "SN2"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_co2: bcm-co2 { + cell-id = ; + label = "CO2"; + qcom,bcm-name = "CO2"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_ip0: bcm-ip0 { + cell-id = ; + label = "IP0"; + qcom,bcm-name = "IP0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn3: bcm-sn3 { + cell-id = ; + label = "SN3"; + qcom,bcm-name = "SN3"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn4: bcm-sn4 { + cell-id = ; + label = "SN4"; + qcom,bcm-name = "SN4"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn8: bcm-sn8 { + cell-id = ; + label = "SN8"; + qcom,bcm-name = "SN8"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn9: bcm-sn9 { + cell-id = ; + label = "SN9"; + qcom,bcm-name = "SN9"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn11: bcm-sn11 { + cell-id = ; + label = "SN11"; + qcom,bcm-name = "SN11"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn14: bcm-sn14 { + cell-id = ; + label = "SN14"; + qcom,bcm-name = "SN14"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn15: bcm-sn15 { + cell-id = ; + label = "SN15"; + qcom,bcm-name = "SN15"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_acv_display: bcm-acv_display { + cell-id = ; + label = "ACV_DISPLAY"; + qcom,bcm-name = "ACV"; + qcom,rscs = <&rsc_disp>; + qcom,bcm-dev; + }; + + bcm_mc0_display: bcm-mc0_display { + cell-id = ; + label = "MC0_DISPLAY"; + qcom,bcm-name = "MC0"; + qcom,rscs = <&rsc_disp>; + qcom,bcm-dev; + }; + + bcm_sh0_display: bcm-sh0_display { + cell-id = ; + label = "SH0_DISPLAY"; + qcom,bcm-name = "SH0"; + qcom,rscs = <&rsc_disp>; + qcom,bcm-dev; + }; + + bcm_mm0_display: bcm-mm0_display { + cell-id = ; + label = "MM0_DISPLAY"; + qcom,bcm-name = "MM0"; + qcom,rscs = <&rsc_disp>; + qcom,bcm-dev; + }; + + bcm_mm1_display: bcm-mm1_display { + cell-id = ; + label = "MM1_DISPLAY"; + qcom,bcm-name = "MM1"; + qcom,rscs = <&rsc_disp>; + qcom,bcm-dev; + }; + + bcm_mm2_display: bcm-mm2_display { + cell-id = ; + label = "MM2_DISPLAY"; + qcom,bcm-name = "MM2"; + qcom,rscs = <&rsc_disp>; + qcom,bcm-dev; + }; + + + /*Buses*/ + fab_aggre1_noc: fab-aggre1_noc{ + cell-id = ; + label = "fab-aggre1_noc"; + qcom,fab-dev; + qcom,base-name = "aggre1_noc-base"; + qcom,qos-off = <4096>; + qcom,base-offset = <12288>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_aggre2_noc: fab-aggre2_noc{ + cell-id = ; + label = "fab-aggre2_noc"; + qcom,fab-dev; + qcom,base-name = "aggre2_noc-base"; + qcom,qos-off = <4096>; + qcom,base-offset = <16384>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_camnoc_virt: fab-camnoc_virt{ + cell-id = ; + label = "fab-camnoc_virt"; + qcom,fab-dev; + qcom,base-name = "camnoc_virt-base"; + qcom,qos-off = <0>; + qcom,base-offset = <0>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + clocks = <>; + }; + + fab_compute_noc: fab-compute_noc{ + cell-id = ; + label = "fab-compute_noc"; + qcom,fab-dev; + qcom,base-name = "compute_noc-base"; + qcom,qos-off = <4096>; + qcom,base-offset = <81920>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_config_noc: fab-config_noc{ + cell-id = ; + label = "fab-config_noc"; + qcom,fab-dev; + qcom,base-name = "config_noc-base"; + qcom,qos-off = <0>; + qcom,base-offset = <0>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_dc_noc: fab-dc_noc{ + cell-id = ; + label = "fab-dc_noc"; + qcom,fab-dev; + qcom,base-name = "dc_noc-base"; + qcom,qos-off = <0>; + qcom,base-offset = <0>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_gem_noc: fab-gem_noc{ + cell-id = ; + label = "fab-gem_noc"; + qcom,fab-dev; + qcom,base-name = "gem_noc-base"; + qcom,qos-off = <128>; + qcom,base-offset = <196608>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_ipa_virt: fab-ipa_virt{ + cell-id = ; + label = "fab-ipa_virt"; + qcom,fab-dev; + qcom,base-name = "ipa_virt-base"; + qcom,qos-off = <0>; + qcom,base-offset = <0>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + clocks = <>; + }; + + fab_mc_virt: fab-mc_virt{ + cell-id = ; + label = "fab-mc_virt"; + qcom,fab-dev; + qcom,base-name = "mc_virt-base"; + qcom,qos-off = <0>; + qcom,base-offset = <0>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + clocks = <>; + }; + + fab_mmss_noc: fab-mmss_noc{ + cell-id = ; + label = "fab-mmss_noc"; + qcom,fab-dev; + qcom,base-name = "mmss_noc-base"; + qcom,qos-off = <4096>; + qcom,base-offset = <36864>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_system_noc: fab-system_noc{ + cell-id = ; + label = "fab-system_noc"; + qcom,fab-dev; + qcom,base-name = "system_noc-base"; + qcom,qos-off = <4096>; + qcom,base-offset = <69632>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_gem_noc_display: fab-gem_noc_display{ + cell-id = ; + label = "fab-gem_noc_display"; + qcom,fab-dev; + qcom,base-name = "gem_noc-base"; + qcom,qos-off = <128>; + qcom,base-offset = <196608>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_mc_virt_display: fab-mc_virt_display{ + cell-id = ; + label = "fab-mc_virt_display"; + qcom,fab-dev; + qcom,base-name = "mc_virt-base"; + qcom,qos-off = <0>; + qcom,base-offset = <0>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + clocks = <>; + }; + + fab_mmss_noc_display: fab-mmss_noc_display{ + cell-id = ; + label = "fab-mmss_noc_display"; + qcom,fab-dev; + qcom,base-name = "mmss_noc-base"; + qcom,qos-off = <4096>; + qcom,base-offset = <36864>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clocks = <>; + }; + + + /*Masters*/ + + mas_qhm_a1noc_cfg: mas-qhm-a1noc-cfg { + cell-id = ; + label = "mas-qhm-a1noc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_srvc_aggre1_noc>; + qcom,bus-dev = <&fab_aggre1_noc>; + }; + + mas_xm_ufs_card: mas-xm-ufs-card { + cell-id = ; + label = "mas-xm-ufs-card"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <3>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_xm_ufs_g4: mas-xm-ufs-g4 { + cell-id = ; + label = "mas-xm-ufs-g4"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <12>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_xm_ufs_mem: mas-xm-ufs-mem { + cell-id = ; + label = "mas-xm-ufs-mem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <0>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_xm_usb3_0: mas-xm-usb3-0 { + cell-id = ; + label = "mas-xm-usb3-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <7>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_xm_usb3_1: mas-xm-usb3-1 { + cell-id = ; + label = "mas-xm-usb3-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <2>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_xm_usb3_2: mas-xm-usb3-2 { + cell-id = ; + label = "mas-xm-usb3-2"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,qport = <6>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qhm_a2noc_cfg: mas-qhm-a2noc-cfg { + cell-id = ; + label = "mas-qhm-a2noc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_srvc_aggre2_noc>; + qcom,bus-dev = <&fab_aggre2_noc>; + }; + + mas_qhm_qdss_bam: mas-qhm-qdss-bam { + cell-id = ; + label = "mas-qhm-qdss-bam"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,qport = <23>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qhm_qspi: mas-qhm-qspi { + cell-id = ; + label = "mas-qhm-qspi"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,qport = <14>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qhm_qspi1: mas-qhm-qspi1 { + cell-id = ; + label = "mas-qhm-qspi1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,qport = <15>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qhm_qup0: mas-qhm-qup0 { + cell-id = ; + label = "mas-qhm-qup0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,qport = <5>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,bcms = <&bcm_qup0>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qhm_qup1: mas-qhm-qup1 { + cell-id = ; + label = "mas-qhm-qup1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,qport = <21>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,bcms = <&bcm_qup0>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qhm_qup2: mas-qhm-qup2 { + cell-id = ; + label = "mas-qhm-qup2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,qport = <22>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,bcms = <&bcm_qup0>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qhm_sensorss_ahb: mas-qhm-sensorss-ahb { + cell-id = ; + label = "mas-qhm-sensorss-ahb"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + }; + + mas_qxm_crypto: mas-qxm-crypto { + cell-id = ; + label = "mas-qxm-crypto"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <3>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,bcms = <&bcm_ce0>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qxm_ipa: mas-qxm-ipa { + cell-id = ; + label = "mas-qxm-ipa"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <4>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_xm_emac: mas-xm-emac { + cell-id = ; + label = "mas-xm-emac"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <12>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_xm_pcie3_0: mas-xm-pcie3-0 { + cell-id = ; + label = "mas-xm-pcie3-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <7>; + qcom,connections = <&slv_qns_pcie_mem_noc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_xm_pcie3_1: mas-xm-pcie3-1 { + cell-id = ; + label = "mas-xm-pcie3-1"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,qport = <0>; + qcom,connections = <&slv_qns_pcie_mem_noc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_xm_pcie3_2: mas-xm-pcie3-2 { + cell-id = ; + label = "mas-xm-pcie3-2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <3>; + qcom,connections = <&slv_qns_pcie_mem_noc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_xm_pcie3_3: mas-xm-pcie3-3 { + cell-id = ; + label = "mas-xm-pcie3-3"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,qport = <4>; + qcom,connections = <&slv_qns_pcie_mem_noc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_xm_qdss_etr: mas-xm-qdss-etr { + cell-id = ; + label = "mas-xm-qdss-etr"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <9>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_xm_sdc2: mas-xm-sdc2 { + cell-id = ; + label = "mas-xm-sdc2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <10>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_xm_sdc4: mas-xm-sdc4 { + cell-id = ; + label = "mas-xm-sdc4"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <11>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qxm_camnoc_hf0_uncomp: mas-qxm-camnoc-hf0-uncomp { + cell-id = ; + label = "mas-qxm-camnoc-hf0-uncomp"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_camnoc_uncomp>; + qcom,bus-dev = <&fab_camnoc_virt>; + qcom,bcms = <&bcm_mm1>; + }; + + mas_qxm_camnoc_hf1_uncomp: mas-qxm-camnoc-hf1-uncomp { + cell-id = ; + label = "mas-qxm-camnoc-hf1-uncomp"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_camnoc_uncomp>; + qcom,bus-dev = <&fab_camnoc_virt>; + qcom,bcms = <&bcm_mm1>; + }; + + mas_qxm_camnoc_sf_uncomp: mas-qxm-camnoc-sf-uncomp { + cell-id = ; + label = "mas-qxm-camnoc-sf-uncomp"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_camnoc_uncomp>; + qcom,bus-dev = <&fab_camnoc_virt>; + qcom,bcms = <&bcm_mm1>; + }; + + mas_qnm_npu: mas-qnm-npu { + cell-id = ; + label = "mas-qnm-npu"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <2>; + qcom,connections = <&slv_qns_cdsp_mem_noc>; + qcom,bus-dev = <&fab_compute_noc>; + qcom,bcms = <&bcm_co2>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qnm_snoc: mas-qnm-snoc { + cell-id = ; + label = "mas-qnm-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qhs_tlmm_south + &slv_qhs_compute_dsp &slv_qhs_spss_cfg + &slv_qhs_camera_cfg &slv_qhs_sdc4 + &slv_qhs_ahb2phy_refgen_center &slv_qhs_sdc2 + &slv_qhs_pcie2_cfg &slv_qhs_mnoc_cfg + &slv_qhs_emac_cfg &slv_qhs_qspi_0 + &slv_qhs_qspi_1 &slv_qhs_tlmm_east + &slv_qhs_snoc_cfg &slv_qhs_ahb2phy_refgen_east + &slv_qhs_glm &slv_qhs_pdm + &slv_qhs_pcie1_cfg &slv_qhs_a2_noc_cfg + &slv_qhs_qdss_cfg &slv_qhs_display_cfg + &slv_qhs_tcsr &slv_qhs_ufs_mem0_cfg + &slv_qhs_ddrss_cfg &slv_qhs_pcie0_cfg + &slv_qhs_qupv3_east0 &slv_qhs_qupv3_east1 + &slv_qhs_npu_cfg &slv_qhs_crypto0_cfg + &slv_qhs_gpuss_cfg &slv_qhs_venus_cfg + &slv_qhs_tsif &slv_qhs_ipa + &slv_qhs_clk_ctl &slv_qhs_security + &slv_qhs_aop &slv_qhs_ahb2phy_refgen_west + &slv_qhs_ahb2phy_south &slv_srvc_cnoc + &slv_qhs_ufs_card_cfg &slv_qhs_usb3_1 + &slv_qhs_usb3_2 &slv_qhs_pcie3_cfg + &slv_qhs_cpr_cx &slv_qhs_tlmm_west + &slv_qhs_a1_noc_cfg &slv_qhs_aoss + &slv_qhs_prng &slv_qhs_vsense_ctrl_cfg + &slv_qhs_qupv3_west &slv_qhs_usb3_0 + &slv_qhs_cpr_mmcx &slv_qhs_pimem_cfg + &slv_qhs_ufs_mem1_cfg &slv_qhs_cpr_mx + &slv_qhs_imem_cfg>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + mas_qhm_cnoc_dc_noc: mas-qhm-cnoc-dc-noc { + cell-id = ; + label = "mas-qhm-cnoc-dc-noc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qhs_llcc &slv_qhs_gemnoc>; + qcom,bus-dev = <&fab_dc_noc>; + }; + + mas_acm_apps: mas-acm-apps { + cell-id = ; + label = "mas-acm-apps"; + qcom,buswidth = <64>; + qcom,agg-ports = <4>; + qcom,qport = <0 1 2 3 4 5 6 7>; + qcom,connections = <&slv_qns_ecc + &slv_qns_llcc &slv_qns_gem_noc_snoc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,bcms = <&bcm_sh3>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_acm_gpu_tcu: mas-acm-gpu-tcu { + cell-id = ; + label = "mas-acm-gpu-tcu"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <8>; + qcom,connections = <&slv_qns_llcc + &slv_qns_gem_noc_snoc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_acm_sys_tcu: mas-acm-sys-tcu { + cell-id = ; + label = "mas-acm-sys-tcu"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <9>; + qcom,connections = <&slv_qns_llcc + &slv_qns_gem_noc_snoc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qhm_gemnoc_cfg: mas-qhm-gemnoc-cfg { + cell-id = ; + label = "mas-qhm-gemnoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_srvc_gemnoc1 + &slv_srvc_gemnoc &slv_qhs_mdsp_ms_mpu_cfg>; + qcom,bus-dev = <&fab_gem_noc>; + }; + + mas_qnm_cmpnoc: mas-qnm-cmpnoc { + cell-id = ; + label = "mas-qnm-cmpnoc"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,qport = <1224 1225>; + qcom,connections = <&slv_qns_ecc + &slv_qns_llcc &slv_qns_gem_noc_snoc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qnm_gpu: mas-qnm-gpu { + cell-id = ; + label = "mas-qnm-gpu"; + qcom,buswidth = <32>; + qcom,agg-ports = <4>; + qcom,qport = <1226 1227 1228 1229>; + qcom,connections = <&slv_qns_llcc + &slv_qns_gem_noc_snoc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qnm_mnoc_hf: mas-qnm-mnoc-hf { + cell-id = ; + label = "mas-qnm-mnoc-hf"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,qport = <1230 1231>; + qcom,connections = <&slv_qns_llcc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qnm_mnoc_sf: mas-qnm-mnoc-sf { + cell-id = ; + label = "mas-qnm-mnoc-sf"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <16>; + qcom,connections = <&slv_qns_llcc + &slv_qns_gem_noc_snoc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qnm_pcie: mas-qnm-pcie { + cell-id = ; + label = "mas-qnm-pcie"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <17>; + qcom,connections = <&slv_qns_llcc + &slv_qns_gem_noc_snoc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qnm_snoc_gc: mas-qnm-snoc-gc { + cell-id = ; + label = "mas-qnm-snoc-gc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <1232>; + qcom,connections = <&slv_qns_llcc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qnm_snoc_sf: mas-qnm-snoc-sf { + cell-id = ; + label = "mas-qnm-snoc-sf"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <19>; + qcom,connections = <&slv_qns_llcc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qxm_ecc: mas-qxm-ecc { + cell-id = ; + label = "mas-qxm-ecc"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,qport = <1556 1557>; + qcom,connections = <&slv_qns_llcc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_ipa_core_master: mas-ipa-core-master { + cell-id = ; + label = "mas-ipa-core-master"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_ipa_core_slave>; + qcom,bus-dev = <&fab_ipa_virt>; + }; + + mas_llcc_mc: mas-llcc-mc { + cell-id = ; + label = "mas-llcc-mc"; + qcom,buswidth = <4>; + qcom,agg-ports = <8>; + qcom,connections = <&slv_ebi>; + qcom,bus-dev = <&fab_mc_virt>; + }; + + mas_qhm_mnoc_cfg: mas-qhm-mnoc-cfg { + cell-id = ; + label = "mas-qhm-mnoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_srvc_mnoc>; + qcom,bus-dev = <&fab_mmss_noc>; + }; + + mas_qxm_camnoc_hf0: mas-qxm-camnoc-hf0 { + cell-id = ; + label = "mas-qxm-camnoc-hf0"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <1>; + qcom,connections = <&slv_qns_mem_noc_hf>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm1>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qxm_camnoc_hf1: mas-qxm-camnoc-hf1 { + cell-id = ; + label = "mas-qxm-camnoc-hf1"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <2>; + qcom,connections = <&slv_qns_mem_noc_hf>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm1>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qxm_camnoc_sf: mas-qxm-camnoc-sf { + cell-id = ; + label = "mas-qxm-camnoc-sf"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <0>; + qcom,connections = <&slv_qns2_mem_noc>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm2>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qxm_mdp0: mas-qxm-mdp0 { + cell-id = ; + label = "mas-qxm-mdp0"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <3>; + qcom,connections = <&slv_qns_mem_noc_hf>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm1>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qxm_mdp1: mas-qxm-mdp1 { + cell-id = ; + label = "mas-qxm-mdp1"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <4>; + qcom,connections = <&slv_qns_mem_noc_hf>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm1>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qxm_rot: mas-qxm-rot { + cell-id = ; + label = "mas-qxm-rot"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <5>; + qcom,connections = <&slv_qns2_mem_noc>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm2>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qxm_venus0: mas-qxm-venus0 { + cell-id = ; + label = "mas-qxm-venus0"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <6>; + qcom,connections = <&slv_qns2_mem_noc>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm2>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qxm_venus1: mas-qxm-venus1 { + cell-id = ; + label = "mas-qxm-venus1"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <7>; + qcom,connections = <&slv_qns2_mem_noc>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm2>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qxm_venus_arm9: mas-qxm-venus-arm9 { + cell-id = ; + label = "mas-qxm-venus-arm9"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <8>; + qcom,connections = <&slv_qns2_mem_noc>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm2>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qhm_snoc_cfg: mas-qhm-snoc-cfg { + cell-id = ; + label = "mas-qhm-snoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_srvc_snoc>; + qcom,bus-dev = <&fab_system_noc>; + }; + + mas_qnm_aggre1_noc: mas-qnm-aggre1-noc { + cell-id = ; + label = "mas-qnm-aggre1-noc"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_gemnoc_sf + &slv_qxs_pimem &slv_qxs_imem + &slv_qhs_apss &slv_qns_cnoc + &slv_xs_qdss_stm>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn9>; + }; + + mas_qnm_aggre2_noc: mas-qnm-aggre2-noc { + cell-id = ; + label = "mas-qnm-aggre2-noc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_gemnoc_sf + &slv_qxs_pimem &slv_xs_pcie_3 + &slv_qxs_imem &slv_qhs_apss + &slv_xs_pcie_2 &slv_qns_cnoc + &slv_xs_pcie_0 &slv_xs_pcie_1 + &slv_xs_sys_tcu_cfg &slv_xs_qdss_stm>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn11>; + }; + + mas_qnm_gemnoc: mas-qnm-gemnoc { + cell-id = ; + label = "mas-qnm-gemnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qxs_pimem + &slv_qxs_imem &slv_qhs_apss + &slv_qns_cnoc &slv_xs_sys_tcu_cfg + &slv_xs_qdss_stm>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn15>; + }; + + mas_qxm_pimem: mas-qxm-pimem { + cell-id = ; + label = "mas-qxm-pimem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <3>; + qcom,connections = <&slv_qns_gemnoc_gc &slv_qxs_imem>; + qcom,bus-dev = <&fab_system_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_xm_gic: mas-xm-gic { + cell-id = ; + label = "mas-xm-gic"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <0>; + qcom,connections = <&slv_qns_gemnoc_gc &slv_qxs_imem>; + qcom,bus-dev = <&fab_system_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qnm_mnoc_hf_display: mas-qnm-mnoc-hf_display { + cell-id = ; + label = "mas-qnm-mnoc-hf_display"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,qport = <1230 1231>; + qcom,connections = <&slv_qns_llcc_display>; + qcom,bus-dev = <&fab_gem_noc_display>; + }; + + mas_qnm_mnoc_sf_display: mas-qnm-mnoc-sf_display { + cell-id = ; + label = "mas-qnm-mnoc-sf_display"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <16>; + qcom,connections = <&slv_qns_llcc_display>; + qcom,bus-dev = <&fab_gem_noc_display>; + }; + + mas_llcc_mc_display: mas-llcc-mc_display { + cell-id = ; + label = "mas-llcc-mc_display"; + qcom,buswidth = <4>; + qcom,agg-ports = <8>; + qcom,connections = <&slv_ebi_display>; + qcom,bus-dev = <&fab_mc_virt_display>; + }; + + mas_qxm_mdp0_display: mas-qxm-mdp0_display { + cell-id = ; + label = "mas-qxm-mdp0_display"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <3>; + qcom,connections = <&slv_qns_mem_noc_hf_display>; + qcom,bus-dev = <&fab_mmss_noc_display>; + qcom,bcms = <&bcm_mm1_display>; + }; + + mas_qxm_mdp1_display: mas-qxm-mdp1_display { + cell-id = ; + label = "mas-qxm-mdp1_display"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <4>; + qcom,connections = <&slv_qns_mem_noc_hf_display>; + qcom,bus-dev = <&fab_mmss_noc_display>; + qcom,bcms = <&bcm_mm1_display>; + }; + + mas_qxm_rot_display: mas-qxm-rot_display { + cell-id = ; + label = "mas-qxm-rot_display"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <5>; + qcom,connections = <&slv_qns2_mem_noc_display>; + qcom,bus-dev = <&fab_mmss_noc_display>; + qcom,bcms = <&bcm_mm2_display>; + }; + + /*Internal nodes*/ + + /*Slaves*/ + + slv_qns_a1noc_snoc:slv-qns-a1noc-snoc { + cell-id = ; + label = "slv-qns-a1noc-snoc"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,connections = <&mas_qnm_aggre1_noc>; + }; + + slv_srvc_aggre1_noc:slv-srvc-aggre1-noc { + cell-id = ; + label = "slv-srvc-aggre1-noc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,bcms = <&bcm_sn3>; + }; + + slv_qns_a2noc_snoc:slv-qns-a2noc-snoc { + cell-id = ; + label = "slv-qns-a2noc-snoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,connections = <&mas_qnm_aggre2_noc>; + }; + + slv_qns_pcie_mem_noc:slv-qns-pcie-mem-noc { + cell-id = ; + label = "slv-qns-pcie-mem-noc"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,connections = <&mas_qnm_pcie>; + qcom,bcms = <&bcm_sn14>; + }; + + slv_srvc_aggre2_noc:slv-srvc-aggre2-noc { + cell-id = ; + label = "slv-srvc-aggre2-noc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_aggre2_noc>; + }; + + slv_qns_camnoc_uncomp:slv-qns-camnoc-uncomp { + cell-id = ; + label = "slv-qns-camnoc-uncomp"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_camnoc_virt>; + }; + + slv_qns_cdsp_mem_noc:slv-qns-cdsp-mem-noc { + cell-id = ; + label = "slv-qns-cdsp-mem-noc"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,bus-dev = <&fab_compute_noc>; + qcom,connections = <&mas_qnm_cmpnoc>; + qcom,bcms = <&bcm_co0>; + }; + + slv_qhs_a1_noc_cfg:slv-qhs-a1-noc-cfg { + cell-id = ; + label = "slv-qhs-a1-noc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,connections = <&mas_qhm_a1noc_cfg>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_a2_noc_cfg:slv-qhs-a2-noc-cfg { + cell-id = ; + label = "slv-qhs-a2-noc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,connections = <&mas_qhm_a2noc_cfg>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_ahb2phy_refgen_center:slv-qhs-ahb2phy-refgen-center { + cell-id = ; + label = "slv-qhs-ahb2phy-refgen-center"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_ahb2phy_refgen_east:slv-qhs-ahb2phy-refgen-east { + cell-id = ; + label = "slv-qhs-ahb2phy-refgen-east"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_ahb2phy_refgen_west:slv-qhs-ahb2phy-refgen-west { + cell-id = ; + label = "slv-qhs-ahb2phy-refgen-west"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_ahb2phy_south:slv-qhs-ahb2phy-south { + cell-id = ; + label = "slv-qhs-ahb2phy-south"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_aop:slv-qhs-aop { + cell-id = ; + label = "slv-qhs-aop"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_aoss:slv-qhs-aoss { + cell-id = ; + label = "slv-qhs-aoss"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_camera_cfg:slv-qhs-camera-cfg { + cell-id = ; + label = "slv-qhs-camera-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_clk_ctl:slv-qhs-clk-ctl { + cell-id = ; + label = "slv-qhs-clk-ctl"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_compute_dsp:slv-qhs-compute-dsp { + cell-id = ; + label = "slv-qhs-compute-dsp"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_cpr_cx:slv-qhs-cpr-cx { + cell-id = ; + label = "slv-qhs-cpr-cx"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_cpr_mmcx:slv-qhs-cpr-mmcx { + cell-id = ; + label = "slv-qhs-cpr-mmcx"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_cpr_mx:slv-qhs-cpr-mx { + cell-id = ; + label = "slv-qhs-cpr-mx"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_crypto0_cfg:slv-qhs-crypto0-cfg { + cell-id = ; + label = "slv-qhs-crypto0-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_ddrss_cfg:slv-qhs-ddrss-cfg { + cell-id = ; + label = "slv-qhs-ddrss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,connections = <&mas_qhm_cnoc_dc_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_display_cfg:slv-qhs-display-cfg { + cell-id = ; + label = "slv-qhs-display-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_emac_cfg:slv-qhs-emac-cfg { + cell-id = ; + label = "slv-qhs-emac-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_glm:slv-qhs-glm { + cell-id = ; + label = "slv-qhs-glm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_gpuss_cfg:slv-qhs-gpuss-cfg { + cell-id = ; + label = "slv-qhs-gpuss-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_imem_cfg:slv-qhs-imem-cfg { + cell-id = ; + label = "slv-qhs-imem-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_ipa:slv-qhs-ipa { + cell-id = ; + label = "slv-qhs-ipa"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_mnoc_cfg:slv-qhs-mnoc-cfg { + cell-id = ; + label = "slv-qhs-mnoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,connections = <&mas_qhm_mnoc_cfg>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_npu_cfg:slv-qhs-npu-cfg { + cell-id = ; + label = "slv-qhs-npu-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_pcie0_cfg:slv-qhs-pcie0-cfg { + cell-id = ; + label = "slv-qhs-pcie0-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_pcie1_cfg:slv-qhs-pcie1-cfg { + cell-id = ; + label = "slv-qhs-pcie1-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_pcie2_cfg:slv-qhs-pcie2-cfg { + cell-id = ; + label = "slv-qhs-pcie2-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_pcie3_cfg:slv-qhs-pcie3-cfg { + cell-id = ; + label = "slv-qhs-pcie3-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_pdm:slv-qhs-pdm { + cell-id = ; + label = "slv-qhs-pdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_pimem_cfg:slv-qhs-pimem-cfg { + cell-id = ; + label = "slv-qhs-pimem-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_prng:slv-qhs-prng { + cell-id = ; + label = "slv-qhs-prng"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_qdss_cfg:slv-qhs-qdss-cfg { + cell-id = ; + label = "slv-qhs-qdss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_qspi_0:slv-qhs-qspi-0 { + cell-id = ; + label = "slv-qhs-qspi-0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_qspi_1:slv-qhs-qspi-1 { + cell-id = ; + label = "slv-qhs-qspi-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_qupv3_east0:slv-qhs-qupv3-east0 { + cell-id = ; + label = "slv-qhs-qupv3-east0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_qupv3_east1:slv-qhs-qupv3-east1 { + cell-id = ; + label = "slv-qhs-qupv3-east1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_qupv3_west:slv-qhs-qupv3-west { + cell-id = ; + label = "slv-qhs-qupv3-west"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_sdc2:slv-qhs-sdc2 { + cell-id = ; + label = "slv-qhs-sdc2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_sdc4:slv-qhs-sdc4 { + cell-id = ; + label = "slv-qhs-sdc4"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_security:slv-qhs-security { + cell-id = ; + label = "slv-qhs-security"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_snoc_cfg:slv-qhs-snoc-cfg { + cell-id = ; + label = "slv-qhs-snoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,connections = <&mas_qhm_snoc_cfg>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_spss_cfg:slv-qhs-spss-cfg { + cell-id = ; + label = "slv-qhs-spss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_tcsr:slv-qhs-tcsr { + cell-id = ; + label = "slv-qhs-tcsr"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_tlmm_east:slv-qhs-tlmm-east { + cell-id = ; + label = "slv-qhs-tlmm-east"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_tlmm_south:slv-qhs-tlmm-south { + cell-id = ; + label = "slv-qhs-tlmm-south"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_tlmm_west:slv-qhs-tlmm-west { + cell-id = ; + label = "slv-qhs-tlmm-west"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_tsif:slv-qhs-tsif { + cell-id = ; + label = "slv-qhs-tsif"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_ufs_card_cfg:slv-qhs-ufs-card-cfg { + cell-id = ; + label = "slv-qhs-ufs-card-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_ufs_mem0_cfg:slv-qhs-ufs-mem0-cfg { + cell-id = ; + label = "slv-qhs-ufs-mem0-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_ufs_mem1_cfg:slv-qhs-ufs-mem1-cfg { + cell-id = ; + label = "slv-qhs-ufs-mem1-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_usb3_0:slv-qhs-usb3-0 { + cell-id = ; + label = "slv-qhs-usb3-0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_usb3_1:slv-qhs-usb3-1 { + cell-id = ; + label = "slv-qhs-usb3-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_usb3_2:slv-qhs-usb3-2 { + cell-id = ; + label = "slv-qhs-usb3-2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_venus_cfg:slv-qhs-venus-cfg { + cell-id = ; + label = "slv-qhs-venus-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_vsense_ctrl_cfg:slv-qhs-vsense-ctrl-cfg { + cell-id = ; + label = "slv-qhs-vsense-ctrl-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_srvc_cnoc:slv-srvc-cnoc { + cell-id = ; + label = "slv-srvc-cnoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_gemnoc:slv-qhs-gemnoc { + cell-id = ; + label = "slv-qhs-gemnoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_dc_noc>; + qcom,connections = <&mas_qhm_gemnoc_cfg>; + }; + + slv_qhs_llcc:slv-qhs-llcc { + cell-id = ; + label = "slv-qhs-llcc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_dc_noc>; + }; + + slv_qhs_mdsp_ms_mpu_cfg:slv-qhs-mdsp-ms-mpu-cfg { + cell-id = ; + label = "slv-qhs-mdsp-ms-mpu-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_gem_noc>; + }; + + slv_qns_ecc:slv-qns-ecc { + cell-id = ; + label = "slv-qns-ecc"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_gem_noc>; + }; + + slv_qns_gem_noc_snoc:slv-qns-gem-noc-snoc { + cell-id = ; + label = "slv-qns-gem-noc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,connections = <&mas_qnm_gemnoc>; + qcom,bcms = <&bcm_sh2>; + }; + + slv_qns_llcc:slv-qns-llcc { + cell-id = ; + label = "slv-qns-llcc"; + qcom,buswidth = <16>; + qcom,agg-ports = <8>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,connections = <&mas_llcc_mc>; + qcom,bcms = <&bcm_sh0>; + }; + + slv_srvc_gemnoc:slv-srvc-gemnoc { + cell-id = ; + label = "slv-srvc-gemnoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_gem_noc>; + }; + + slv_srvc_gemnoc1:slv-srvc-gemnoc1 { + cell-id = ; + label = "slv-srvc-gemnoc1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_gem_noc>; + }; + + slv_ipa_core_slave:slv-ipa-core-slave { + cell-id = ; + label = "slv-ipa-core-slave"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_ipa_virt>; + qcom,bcms = <&bcm_ip0>; + }; + + slv_ebi:slv-ebi { + cell-id = ; + label = "slv-ebi"; + qcom,buswidth = <4>; + qcom,agg-ports = <8>; + qcom,bus-dev = <&fab_mc_virt>; + qcom,bcms = <&bcm_mc0>, <&bcm_acv>; + }; + + slv_qns2_mem_noc:slv-qns2-mem-noc { + cell-id = ; + label = "slv-qns2-mem-noc"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,connections = <&mas_qnm_mnoc_sf>; + qcom,bcms = <&bcm_mm2>; + }; + + slv_qns_mem_noc_hf:slv-qns-mem-noc-hf { + cell-id = ; + label = "slv-qns-mem-noc-hf"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,connections = <&mas_qnm_mnoc_hf>; + qcom,bcms = <&bcm_mm0>; + }; + + slv_srvc_mnoc:slv-srvc-mnoc { + cell-id = ; + label = "slv-srvc-mnoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_mmss_noc>; + }; + + slv_qhs_apss:slv-qhs-apss { + cell-id = ; + label = "slv-qhs-apss"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + }; + + slv_qns_cnoc:slv-qns-cnoc { + cell-id = ; + label = "slv-qns-cnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,connections = <&mas_qnm_snoc>; + qcom,bcms = <&bcm_sn3>; + }; + + slv_qns_gemnoc_gc:slv-qns-gemnoc-gc { + cell-id = ; + label = "slv-qns-gemnoc-gc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,connections = <&mas_qnm_snoc_gc>; + qcom,bcms = <&bcm_sn2>; + }; + + slv_qns_gemnoc_sf:slv-qns-gemnoc-sf { + cell-id = ; + label = "slv-qns-gemnoc-sf"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,connections = <&mas_qnm_snoc_sf>; + qcom,bcms = <&bcm_sn0>; + }; + + slv_qxs_imem:slv-qxs-imem { + cell-id = ; + label = "slv-qxs-imem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn1>; + }; + + slv_qxs_pimem:slv-qxs-pimem { + cell-id = ; + label = "slv-qxs-pimem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn4>; + }; + + slv_srvc_snoc:slv-srvc-snoc { + cell-id = ; + label = "slv-srvc-snoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + }; + + slv_xs_pcie_0:slv-xs-pcie-0 { + cell-id = ; + label = "slv-xs-pcie-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn8>; + }; + + slv_xs_pcie_1:slv-xs-pcie-1 { + cell-id = ; + label = "slv-xs-pcie-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn8>; + }; + + slv_xs_pcie_2:slv-xs-pcie-2 { + cell-id = ; + label = "slv-xs-pcie-2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn8>; + }; + + slv_xs_pcie_3:slv-xs-pcie-3 { + cell-id = ; + label = "slv-xs-pcie-3"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn8>; + }; + + slv_xs_qdss_stm:slv-xs-qdss-stm { + cell-id = ; + label = "slv-xs-qdss-stm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + }; + + slv_xs_sys_tcu_cfg:slv-xs-sys-tcu-cfg { + cell-id = ; + label = "slv-xs-sys-tcu-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + }; + + slv_qns_llcc_display:slv-qns-llcc_display { + cell-id = ; + label = "slv-qns-llcc_display"; + qcom,buswidth = <16>; + qcom,agg-ports = <8>; + qcom,bus-dev = <&fab_gem_noc_display>; + qcom,connections = <&mas_llcc_mc_display>; + qcom,bcms = <&bcm_sh0_display>; + }; + + slv_ebi_display:slv-ebi_display { + cell-id = ; + label = "slv-ebi_display"; + qcom,buswidth = <4>; + qcom,agg-ports = <8>; + qcom,bus-dev = <&fab_mc_virt_display>; + qcom,bcms = <&bcm_mc0_display>, <&bcm_acv_display>; + }; + + slv_qns2_mem_noc_display:slv-qns2-mem-noc_display { + cell-id = ; + label = "slv-qns2-mem-noc_display"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_mmss_noc_display>; + qcom,connections = <&mas_qnm_mnoc_sf_display>; + qcom,bcms = <&bcm_mm2_display>; + }; + + slv_qns_mem_noc_hf_display:slv-qns-mem-noc-hf_display { + cell-id = ; + label = "slv-qns-mem-noc-hf_display"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,bus-dev = <&fab_mmss_noc_display>; + qcom,connections = <&mas_qnm_mnoc_hf_display>; + qcom,bcms = <&bcm_mm0_display>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/qcom/sdmshrike-cdp-overlay.dts b/arch/arm/boot/dts/qcom/sdmshrike-cdp-overlay.dts new file mode 100644 index 000000000000..5c9bb022d0fe --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-cdp-overlay.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +#include "sdmshrike-cdp.dtsi" + +/ { + model = "CDP"; + compatible = "qcom,sdmshrike-cdp", "qcom,sdmshrike", "qcom,cdp"; + qcom,board-id = <1 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-cdp.dts b/arch/arm/boot/dts/qcom/sdmshrike-cdp.dts new file mode 100644 index 000000000000..bbda400d38f3 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-cdp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdmshrike.dtsi" +#include "sdmshrike-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDMSHRIKE CDP"; + compatible = "qcom,sdmshrike-cdp", "qcom,sdmshrike", "qcom,cdp"; + qcom,board-id = <1 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-cdp.dtsi b/arch/arm/boot/dts/qcom/sdmshrike-cdp.dtsi new file mode 100644 index 000000000000..b3bb447678fa --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-cdp.dtsi @@ -0,0 +1,123 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "sdmshrike-sde-display.dtsi" + +#include "sdmshrike-pmic-overlay.dtsi" +#include "sdmshrike-audio-overlay.dtsi" +#include "sdmshrike-thermal-overlay.dtsi" + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_home_default + &key_vol_up_default>; + + home { + label = "home"; + gpios = <&pm8150_1_gpios 1 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + + vol_up { + label = "volume_up"; + gpios = <&pm8150_1_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; + + sound-tavil { + qcom,us-euro-gpios = <&tavil_us_euro_switch>; + }; +}; + +&pm8150l_wled { + qcom,string-cfg= <7>; + status = "ok"; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 6 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 7 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 6 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 7 0>; +}; + +&dsi_sharp_4k_dsc_cmd_display { + qcom,dsi-display-active; +}; + +&pm8150l_lcdb { + status = "ok"; +}; + +&qupv3_se12_2uart { + status = "ok"; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + +&qupv3_se3_spi { + status = "ok"; +}; + +&qupv3_se4_i2c { + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm8150_2_l17>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8150c_l6>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&tlmm 96 1>; + + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-gdsc.dtsi b/arch/arm/boot/dts/qcom/sdmshrike-gdsc.dtsi new file mode 100644 index 000000000000..0546459d9854 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-gdsc.dtsi @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm8150-gdsc.dtsi" + +&soc { + /* GDSCs in Global CC */ + pcie_2_gdsc: qcom,gdsc@19d004 { + compatible = "qcom,gdsc"; + regulator-name = "pcie_2_gdsc"; + reg = <0x19d004 0x4>; + status = "disabled"; + }; + + pcie_3_gdsc: qcom,gdsc@1a3004 { + compatible = "qcom,gdsc"; + regulator-name = "pcie_3_gdsc"; + reg = <0x1a3004 0x4>; + status = "disabled"; + }; + + ufs_card_2_gdsc: qcom,gdsc@1a2004 { + compatible = "qcom,gdsc"; + regulator-name = "ufs_card_2_gdsc"; + reg = <0x1a2004 0x4>; + status = "disabled"; + }; + + usb30_mp_gdsc: qcom,gdsc@1a6004 { + compatible = "qcom,gdsc"; + regulator-name = "usb30_mp_gdsc"; + reg = <0x1a6004 0x4>; + status = "disabled"; + }; + + /* GDSCs in Camera CC */ + ife_2_gdsc: qcom,gdsc@ad0f004 { + compatible = "qcom,gdsc"; + regulator-name = "ife_2_gdsc"; + reg = <0xad0f004 0x4>; + status = "disabled"; + }; + + ife_3_gdsc: qcom,gdsc@ad0f070 { + compatible = "qcom,gdsc"; + regulator-name = "ife_3_gdsc"; + reg = <0xad0f070 0x4>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-gpu.dtsi b/arch/arm/boot/dts/qcom/sdmshrike-gpu.dtsi new file mode 100644 index 000000000000..76a1e5379fc6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-gpu.dtsi @@ -0,0 +1,393 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + pil_gpu: qcom,kgsl-hyp { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <13>; + qcom,firmware-name = "a640_zap"; + }; + + msm_bus: qcom,kgsl-busmon{ + label = "kgsl-busmon"; + compatible = "qcom,kgsl-busmon"; + }; + + gpubw: qcom,gpubw { + compatible = "qcom,devbw"; + governor = "bw_vbif"; + qcom,src-dst-ports = <26 512>; + qcom,bw-tbl = + < 0 /* off */ >, + < 381 /* 100 MHz */ >, + < 572 /* 150 MHz */ >, + < 762 /* 200 MHz */ >, + < 1144 /* 300 MHz */ >, + < 1571 /* 412 MHz */ >, + < 2086 /* 547 MHz */ >, + < 2597 /* 681 MHz */ >, + < 2929 /* 768 MHz */ >, + < 3879 /* 1017 MHz */ >, + < 4943 /* 1296 MHz */ >, + < 5931 /* 1555 MHz */ >, + < 6881 /* 1804 MHz */ >; + }; + + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + opp-microvolt = ; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = ; + }; + + opp-461000000 { + opp-hz = /bits/ 64 <461000000>; + opp-microvolt = ; + }; + + opp-405000000 { + opp-hz = /bits/ 64 <405000000>; + opp-microvolt = ; + }; + + opp-315000000 { + opp-hz = /bits/ 64 <315000000>; + opp-microvolt = ; + }; + + opp-256000000 { + opp-hz = /bits/ 64 <256000000>; + opp-microvolt = ; + }; + + opp-177000000 { + opp-hz = /bits/ 64 <177000000>; + opp-microvolt = ; + }; + }; + + msm_gpu: qcom,kgsl-3d0@2c00000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; + status = "ok"; + reg = <0x2c00000 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <0 300 0>; + interrupt-names = "kgsl_3d0_irq"; + qcom,id = <0>; + + qcom,chipid = <0x6080000>; + + qcom,initial-pwrlevel = <5>; + + qcom,idle-timeout = <80>; /* msecs */ + qcom,no-nap; + + qcom,highest-bank-bit = <16>; + + qcom,min-access-length = <32>; + + qcom,ubwc-mode = <3>; + + qcom,snapshot-size = <1048576>; /* bytes */ + + qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */ + + qcom,tsens-name = "tsens_tz_sensor12"; + #cooling-cells = <2>; + + qcom,pm-qos-active-latency = <460>; + + clocks = <&clock_gpucc GPU_CC_CXO_CLK>, + <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gpucc GPU_CC_CX_GMU_CLK>, + <&clock_gpucc GPU_CC_AHB_CLK>; + + clock-names = "rbbmtimer_clk", "mem_clk", + "mem_iface_clk", "gmu_clk", + "gpu_cc_ahb"; + + qcom,isense-clk-on-level = <1>; + + /* Bus Scale Settings */ + qcom,gpubw-dev = <&gpubw>; + qcom,bus-control; + qcom,msm-bus,name = "grp3d"; + qcom,bus-width = <32>; + qcom,msm-bus,num-cases = <13>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, + <26 512 0 400000>, /* 1 bus=100 */ + <26 512 0 600000>, /* 2 bus=150 */ + <26 512 0 800000>, /* 3 bus=200 */ + <26 512 0 1200000>, /* 4 bus=300 */ + <26 512 0 1648000>, /* 5 bus=412 */ + <26 512 0 2188000>, /* 6 bus=547 */ + <26 512 0 2724000>, /* 7 bus=681 */ + <26 512 0 3072000>, /* 8 bus=768 */ + <26 512 0 4068000>, /* 9 bus=1017 */ + <26 512 0 5184000>, /* 10 bus=1296 */ + <26 512 0 6220000>, /* 11 bus=1555 */ + <26 512 0 7216000>; /* 12 bus=1804 */ + + /* GDSC regulator names */ + regulator-names = "vddcx", "vdd"; + /* GDSC oxili regulators */ + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + + /* GPU OPP data */ + operating-points-v2 = <&gpu_opp_table>; + + /* GPU related llc slices */ + cache-slice-names = "gpu", "gpuhtw"; + cache-slices = <&llcc 12>, <&llcc 11>; + + /* GPU Mempools */ + qcom,gpu-mempools { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-reserved = <2048>; + qcom,mempool-allocate; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-reserved = <1024>; + qcom,mempool-allocate; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; + + /* Power levels */ + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <514000000>; + qcom,bus-freq = <12>; + qcom,bus-min = <11>; + qcom,bus-max = <12>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <500000000>; + qcom,bus-freq = <12>; + qcom,bus-min = <10>; + qcom,bus-max = <12>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <461000000>; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <405000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <315000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <256000000>; + qcom,bus-freq = <5>; + qcom,bus-min = <5>; + qcom,bus-max = <7>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <177000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + }; + + kgsl_msm_iommu: qcom,kgsl-iommu@2ca0000 { + compatible = "qcom,kgsl-smmu-v2"; + + reg = <0x2ca0000 0x10000>; + /* CB5(ATOS) & CB5/6/7 are protected by HYP */ + qcom,protect = <0x40000 0xc000>; + qcom,micro-mmu-control = <0x6000>; + + clocks =<&clock_gcc GCC_GPU_CFG_AHB_CLK>, + <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>; + + clock-names = "iface_clk", "mem_clk", "mem_iface_clk"; + + qcom,secure_align_mask = <0xfff>; + qcom,global_pt; + qcom,retention; + qcom,hyp_secure_alloc; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + label = "gfx3d_user"; + iommus = <&kgsl_smmu 0x0 0xC01>; + qcom,gpu-offset = <0x48000>; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + label = "gfx3d_secure"; + iommus = <&kgsl_smmu 0x2 0xC00>; + }; + }; + + gmu_opp_table: gmu-opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = ; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = ; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = ; + }; + }; + + gmu: qcom,gmu@2c6a000 { + label = "kgsl-gmu"; + compatible = "qcom,gpu-gmu"; + + reg = <0x2c6a000 0x30000>, <0xb200000 0x300000>; + reg-names = "kgsl_gmu_reg", "kgsl_gmu_pdc_reg"; + + interrupts = <0 304 0>, <0 305 0>; + interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq"; + + qcom,msm-bus,name = "cnoc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 10036 0 0>, /* CNOC off */ + <26 10036 0 100>; /* CNOC on */ + + regulator-names = "vddcx", "vdd"; + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + + /* GMU OPP data */ + operating-points-v2 = <&gmu_opp_table>; + + clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>, + <&clock_gpucc GPU_CC_CXO_CLK>, + <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gpucc GPU_CC_AHB_CLK>; + + clock-names = "gmu_clk", "cxo_clk", "axi_clk", + "memnoc_clk", "gpu_cc_ahb"; + + qcom,gmu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gmu-pwrlevels"; + + /* GMU power levels must go from lowest to highest */ + qcom,gmu-pwrlevel@0 { + reg = <0>; + qcom,gmu-freq = <0>; + }; + + qcom,gmu-pwrlevel@1 { + reg = <1>; + qcom,gmu-freq = <200000000>; + }; + + qcom,gmu-pwrlevel@2 { + reg = <2>; + qcom,gmu-freq = <400000000>; + }; + + qcom,gmu-pwrlevel@3 { + reg = <3>; + qcom,gmu-freq = <500000000>; + }; + }; + + gmu_user: gmu_user { + compatible = "qcom,smmu-gmu-user-cb"; + iommus = <&kgsl_smmu 0x4 0xC00>; + }; + + gmu_kernel: gmu_kernel { + compatible = "qcom,smmu-gmu-kernel-cb"; + iommus = <&kgsl_smmu 0x5 0xC00>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-ion.dtsi b/arch/arm/boot/dts/qcom/sdmshrike-ion.dtsi new file mode 100644 index 000000000000..72006a4945d1 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-ion.dtsi @@ -0,0 +1,65 @@ +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = <25>; + qcom,ion-heap-type = "SYSTEM"; + }; + + qcom,ion-heap@22 { /* ADSP HEAP */ + reg = <22>; + memory-region = <&adsp_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@26 { /* USER CONTIG HEAP */ + reg = <26>; + memory-region = <&user_contig_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = <27>; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@19 { /* QSEECOM TA HEAP */ + reg = <19>; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@13 { /* SPSS HEAP */ + reg = <13>; + memory-region = <&sp_mem>; + qcom,ion-heap-type = "HYP_CMA"; + }; + + qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ + reg = <10>; + memory-region = <&secure_display_memory>; + qcom,ion-heap-type = "HYP_CMA"; + }; + + qcom,ion-heap@9 { + reg = <9>; + qcom,ion-heap-type = "SYSTEM_SECURE"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-mtp-overlay.dts b/arch/arm/boot/dts/qcom/sdmshrike-mtp-overlay.dts new file mode 100644 index 000000000000..77e99892a90c --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-mtp-overlay.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +#include "sdmshrike-mtp.dtsi" + +/ { + model = "MTP"; + compatible = "qcom,sdmshrike-mtp", "qcom,sdmshrike", "qcom,mtp"; + qcom,board-id = <8 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-mtp.dts b/arch/arm/boot/dts/qcom/sdmshrike-mtp.dts new file mode 100644 index 000000000000..ae4d575c902c --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-mtp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdmshrike.dtsi" +#include "sdmshrike-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDMSHRIKE MTP"; + compatible = "qcom,sdmshrike-mtp", "qcom,sdmshrike", "qcom,mtp"; + qcom,board-id = <8 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-mtp.dtsi b/arch/arm/boot/dts/qcom/sdmshrike-mtp.dtsi new file mode 100644 index 000000000000..0988d0e1a7c0 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-mtp.dtsi @@ -0,0 +1,156 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "sdmshrike-sde-display.dtsi" + +#include "sdmshrike-pmic-overlay.dtsi" +#include "sdmshrike-audio-overlay.dtsi" +#include "sdmshrike-thermal-overlay.dtsi" + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_home_default + &key_vol_up_default>; + + home { + label = "home"; + gpios = <&pm8150_1_gpios 1 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + + vol_up { + label = "volume_up"; + gpios = <&pm8150_1_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&pm8150l_wled { + qcom,string-cfg= <7>; + status = "ok"; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 6 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 7 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 6 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 7 0>; +}; + +&dsi_sharp_4k_dsc_cmd_display { + qcom,dsi-display-active; +}; + +&pm8150l_lcdb { + status = "ok"; +}; + +&qupv3_se12_2uart { + status = "ok"; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + +&qupv3_se3_spi { + status = "ok"; +}; + +&qupv3_se4_i2c { + status = "ok"; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4"; + vdda-phy-supply = <&pm8150_2_l5>; + vdda-pll-supply = <&pm8150c_l3>; + vdda-phy-max-microamp = <138000>; + vdda-pll-max-microamp = <65100>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8150_2_l10>; + vcc-voltage-level = <2504000 2960000>; + vcc-low-voltage-sup; + vccq-supply = <&pm8150_1_l6>; + vccq2-supply = <&pm8150_2_l7>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <750000>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&pm8150c_l2>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status= "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm8150_2_l17>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8150c_l6>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&tlmm 96 1>; + + status = "ok"; +}; + +&usb2_phy1 { + status = "ok"; +}; + +&usb1 { + qcom,default-mode-host; + status ="ok"; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-pinctrl.dtsi b/arch/arm/boot/dts/qcom/sdmshrike-pinctrl.dtsi new file mode 100644 index 000000000000..36a98fc4fbc0 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-pinctrl.dtsi @@ -0,0 +1,4246 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tlmm: pinctrl@3000000 { + compatible = "qcom,sdmshrike-pinctrl"; + reg = <0x03000000 0xdd2000>, <0x17c000f0 0x60>; + reg-names = "pinctrl", "spi_cfg"; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + ufs_dev_reset_assert: ufs_dev_reset_assert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * UFS_RESET driver strengths are having + * different values/steps compared to typical + * GPIO drive strengths. + * + * Following table clarifies: + * + * HDRV value | UFS_RESET | Typical GPIO + * (dec) | (mA) | (mA) + * 0 | 0.8 | 2 + * 1 | 1.55 | 4 + * 2 | 2.35 | 6 + * 3 | 3.1 | 8 + * 4 | 3.9 | 10 + * 5 | 4.65 | 12 + * 6 | 5.4 | 14 + * 7 | 6.15 | 16 + * + * POR value for UFS_RESET HDRV is 3 which means + * 3.1mA and we want to use that. Hence just + * specify 8mA to "drive-strength" binding and + * that should result into writing 3 to HDRV + * field. + */ + drive-strength = <8>; /* default: 3.1 mA */ + output-low; /* active low reset */ + }; + }; + + ufs_dev_reset_deassert: ufs_dev_reset_deassert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * default: 3.1 mA + * check comments under ufs_dev_reset_assert + */ + drive-strength = <8>; + output-high; /* active low reset */ + }; + }; + + aqt_intr { + aqt_intr_default: aqt_intr_default { + mux { + pins = "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio125"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + wcd9xxx_intr { + wcd_intr_default: wcd_intr_default { + mux { + pins = "gpio123"; + function = "gpio"; + }; + + config { + pins = "gpio123"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + cdc_reset_ctrl { + cdc_reset_sleep: cdc_reset_sleep { + mux { + pins = "gpio143"; + function = "gpio"; + }; + config { + pins = "gpio143"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_reset_active:cdc_reset_active { + mux { + pins = "gpio143"; + function = "gpio"; + }; + config { + pins = "gpio143"; + drive-strength = <8>; + bias-pull-down; + output-high; + }; + }; + }; + + sec_aux_pcm { + sec_aux_pcm_sleep: sec_aux_pcm_sleep { + mux { + pins = "gpio126", "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_active: sec_aux_pcm_active { + mux { + pins = "gpio126", "gpio127"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_aux_pcm_din { + sec_aux_pcm_din_sleep: sec_aux_pcm_din_sleep { + mux { + pins = "gpio128"; + function = "gpio"; + }; + + config { + pins = "gpio128"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_din_active: sec_aux_pcm_din_active { + mux { + pins = "gpio128"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio128"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_aux_pcm_dout { + sec_aux_pcm_dout_sleep: sec_aux_pcm_dout_sleep { + mux { + pins = "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio129"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_dout_active: sec_aux_pcm_dout_active { + mux { + pins = "gpio129"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio129"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_aux_pcm { + tert_aux_pcm_sleep: tert_aux_pcm_sleep { + mux { + pins = "gpio133", "gpio134"; + function = "gpio"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_active: tert_aux_pcm_active { + mux { + pins = "gpio133", "gpio134"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_aux_pcm_din { + tert_aux_pcm_din_sleep: tert_aux_pcm_din_sleep { + mux { + pins = "gpio135"; + function = "gpio"; + }; + + config { + pins = "gpio135"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_din_active: tert_aux_pcm_din_active { + mux { + pins = "gpio135"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio135"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_aux_pcm_dout { + tert_aux_pcm_dout_sleep: tert_aux_pcm_dout_sleep { + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_dout_active: tert_aux_pcm_dout_active { + mux { + pins = "gpio131"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio131"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_aux_pcm { + quat_aux_pcm_sleep: quat_aux_pcm_sleep { + mux { + pins = "gpio137", "gpio138"; + function = "gpio"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_pcm_active: quat_aux_pcm_active { + mux { + pins = "gpio137", "gpio138"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_aux_pcm_din { + quat_aux_pcm_din_sleep: quat_aux_pcm_din_sleep { + mux { + pins = "gpio139"; + function = "gpio"; + }; + + config { + pins = "gpio139"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_pcm_din_active: quat_aux_pcm_din_active { + mux { + pins = "gpio139"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio139"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_aux_pcm_dout { + quat_aux_pcm_dout_sleep: quat_aux_pcm_dout_sleep { + mux { + pins = "gpio140"; + function = "gpio"; + }; + + config { + pins = "gpio140"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_pcm_dout_active: quat_aux_pcm_dout_active { + mux { + pins = "gpio140"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio140"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_aux_pcm_clk { + pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep { + mux { + pins = "gpio144"; + function = "gpio"; + }; + + config { + pins = "gpio144"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_clk_active: pri_aux_pcm_clk_active { + mux { + pins = "gpio144"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio144"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_aux_pcm_sync { + pri_aux_pcm_sync_sleep: pri_aux_pcm_sync_sleep { + mux { + pins = "gpio145"; + function = "gpio"; + }; + + config { + pins = "gpio145"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_sync_active: pri_aux_pcm_sync_active { + mux { + pins = "gpio145"; + function = "pri_mi2s_ws"; + }; + + config { + pins = "gpio145"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_aux_pcm_din { + pri_aux_pcm_din_sleep: pri_aux_pcm_din_sleep { + mux { + pins = "gpio146"; + function = "gpio"; + }; + + config { + pins = "gpio146"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_din_active: pri_aux_pcm_din_active { + mux { + pins = "gpio146"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio146"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_aux_pcm_dout { + pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep { + mux { + pins = "gpio147"; + function = "gpio"; + }; + + config { + pins = "gpio147"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_dout_active: pri_aux_pcm_dout_active { + mux { + pins = "gpio147"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio147"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_aux_pcm { + quin_aux_pcm_sleep: quin_aux_pcm_sleep { + mux { + pins = "gpio149", "gpio151"; + function = "gpio"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_aux_pcm_active: quin_aux_pcm_active { + mux { + pins = "gpio149", "gpio151"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quin_aux_pcm_din { + quin_aux_pcm_din_sleep: quin_aux_pcm_din_sleep { + mux { + pins = "gpio150"; + function = "gpio"; + }; + + config { + pins = "gpio150"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_aux_pcm_din_active: quin_aux_pcm_din_active { + mux { + pins = "gpio150"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio150"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_aux_pcm_dout { + quin_aux_pcm_dout_sleep: quin_aux_pcm_dout_sleep { + mux { + pins = "gpio152"; + function = "gpio"; + }; + + config { + pins = "gpio152"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_aux_pcm_dout_active: quin_aux_pcm_dout_active { + mux { + pins = "gpio152"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio152"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio8"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio8"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + sec_tdm { + sec_tdm_sleep: sec_tdm_sleep { + mux { + pins = "gpio126", "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_active: sec_tdm_active { + mux { + pins = "gpio126", "gpio127"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_tdm_din { + sec_tdm_din_sleep: sec_tdm_din_sleep { + mux { + pins = "gpio128"; + function = "gpio"; + }; + + config { + pins = "gpio128"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_din_active: sec_tdm_din_active { + mux { + pins = "gpio128"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio128"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_tdm_dout { + sec_tdm_dout_sleep: sec_tdm_dout_sleep { + mux { + pins = "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio129"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_dout_active: sec_tdm_dout_active { + mux { + pins = "gpio129"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio129"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_tdm { + tert_tdm_sleep: tert_tdm_sleep { + mux { + pins = "gpio133", "gpio134"; + function = "gpio"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_active: tert_tdm_active { + mux { + pins = "gpio133", "gpio134"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_tdm_din { + tert_tdm_din_sleep: tert_tdm_din_sleep { + mux { + pins = "gpio135"; + function = "gpio"; + }; + + config { + pins = "gpio135"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_din_active: tert_tdm_din_active { + mux { + pins = "gpio135"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio135"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_tdm_dout { + tert_tdm_dout_sleep: tert_tdm_dout_sleep { + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_dout_active: tert_tdm_dout_active { + mux { + pins = "gpio131"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio131"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_tdm { + quat_tdm_sleep: quat_tdm_sleep { + mux { + pins = "gpio137", "gpio138"; + function = "gpio"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_active: quat_tdm_active { + mux { + pins = "gpio137", "gpio138"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_tdm_din { + quat_tdm_din_sleep: quat_tdm_din_sleep { + mux { + pins = "gpio139"; + function = "gpio"; + }; + + config { + pins = "gpio139"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_din_active: quat_tdm_din_active { + mux { + pins = "gpio139"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio139"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_tdm_dout { + quat_tdm_dout_sleep: quat_tdm_dout_sleep { + mux { + pins = "gpio140"; + function = "gpio"; + }; + + config { + pins = "gpio140"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_dout_active: quat_tdm_dout_active { + mux { + pins = "gpio140"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio140"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_tdm_clk { + pri_tdm_clk_sleep: pri_tdm_clk_sleep { + mux { + pins = "gpio144"; + function = "gpio"; + }; + + config { + pins = "gpio144"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_clk_active: pri_tdm_clk_active { + mux { + pins = "gpio144"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio144"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_tdm_sync { + pri_tdm_sync_sleep: pri_tdm_sync_sleep { + mux { + pins = "gpio145"; + function = "gpio"; + }; + + config { + pins = "gpio145"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_sync_active: pri_tdm_sync_active { + mux { + pins = "gpio145"; + function = "pri_mi2s_ws"; + }; + + config { + pins = "gpio145"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_tdm_din { + pri_tdm_din_sleep: pri_tdm_din_sleep { + mux { + pins = "gpio146"; + function = "gpio"; + }; + + config { + pins = "gpio146"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_din_active: pri_tdm_din_active { + mux { + pins = "gpio146"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio146"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_tdm_dout { + pri_tdm_dout_sleep: pri_tdm_dout_sleep { + mux { + pins = "gpio147"; + function = "gpio"; + }; + + config { + pins = "gpio147"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_dout_active: pri_tdm_dout_active { + mux { + pins = "gpio147"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio147"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_tdm { + quin_tdm_sleep: quin_tdm_sleep { + mux { + pins = "gpio149", "gpio151"; + function = "gpio"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_tdm_active: quin_tdm_active { + mux { + pins = "gpio149", "gpio151"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quin_tdm_din { + quin_tdm_din_sleep: quin_tdm_din_sleep { + mux { + pins = "gpio150"; + function = "gpio"; + }; + + config { + pins = "gpio150"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_tdm_din_active: quin_tdm_din_active { + mux { + pins = "gpio150"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio150"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_tdm_dout { + quin_tdm_dout_sleep: quin_tdm_dout_sleep { + mux { + pins = "gpio152"; + function = "gpio"; + }; + + config { + pins = "gpio152"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_tdm_dout_active: quin_tdm_dout_active { + mux { + pins = "gpio152"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio152"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_mclk { + sec_mi2s_mclk_sleep: sec_mi2s_mclk_sleep { + mux { + pins = "gpio130"; + function = "gpio"; + }; + + config { + pins = "gpio130"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_mclk_active: sec_mi2s_mclk_active { + mux { + pins = "gpio130"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio130"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s { + sec_mi2s_sleep: sec_mi2s_sleep { + mux { + pins = "gpio126", "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO PULL */ + input-enable; + }; + }; + + sec_mi2s_active: sec_mi2s_active { + mux { + pins = "gpio126", "gpio127"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_sd0 { + sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep { + mux { + pins = "gpio128"; + function = "gpio"; + }; + + config { + pins = "gpio128"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sd0_active: sec_mi2s_sd0_active { + mux { + pins = "gpio128"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio128"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_sd1 { + sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep { + mux { + pins = "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio129"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sd1_active: sec_mi2s_sd1_active { + mux { + pins = "gpio129"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio129"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s_mclk { + tert_mi2s_mclk_sleep: tert_mi2s_mclk_sleep { + mux { + pins = "gpio132"; + function = "gpio"; + }; + + config { + pins = "gpio132"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_mclk_active: tert_mi2s_mclk_active { + mux { + pins = "gpio132"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio132"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s { + tert_mi2s_sleep: tert_mi2s_sleep { + mux { + pins = "gpio133", "gpio134"; + function = "gpio"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_active: tert_mi2s_active { + mux { + pins = "gpio133", "gpio134"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_mi2s_sd0 { + tert_mi2s_sd0_sleep: tert_mi2s_sd0_sleep { + mux { + pins = "gpio135"; + function = "gpio"; + }; + + config { + pins = "gpio135"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_sd0_active: tert_mi2s_sd0_active { + mux { + pins = "gpio135"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio135"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s_sd1 { + tert_mi2s_sd1_sleep: tert_mi2s_sd1_sleep { + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_sd1_active: tert_mi2s_sd1_active { + mux { + pins = "gpio131"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio131"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_mclk { + quat_mi2s_mclk_sleep: quat_mi2s_mclk_sleep { + mux { + pins = "gpio136"; + function = "gpio"; + }; + + config { + pins = "gpio136"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_mclk_active: quat_mi2s_mclk_active { + mux { + pins = "gpio136"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio136"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s { + quat_mi2s_sleep: quat_mi2s_sleep { + mux { + pins = "gpio137", "gpio138"; + function = "gpio"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_active: quat_mi2s_active { + mux { + pins = "gpio137", "gpio138"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_mi2s_sd0 { + quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { + mux { + pins = "gpio139"; + function = "gpio"; + }; + + config { + pins = "gpio139"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd0_active: quat_mi2s_sd0_active { + mux { + pins = "gpio139"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio139"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_sd1 { + quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { + mux { + pins = "gpio140"; + function = "gpio"; + }; + + config { + pins = "gpio140"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd1_active: quat_mi2s_sd1_active { + mux { + pins = "gpio140"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio140"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_sd2 { + quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { + mux { + pins = "gpio141"; + function = "gpio"; + }; + + config { + pins = "gpio141"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd2_active: quat_mi2s_sd2_active { + mux { + pins = "gpio141"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio141"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_sd3 { + quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { + mux { + pins = "gpio142"; + function = "gpio"; + }; + + config { + pins = "gpio142"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd3_active: quat_mi2s_sd3_active { + mux { + pins = "gpio142"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio142"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_mi2s_mclk { + pri_mi2s_mclk_sleep: pri_mi2s_mclk_sleep { + mux { + pins = "gpio143"; + function = "gpio"; + }; + + config { + pins = "gpio143"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_mclk_active: pri_mi2s_mclk_active { + mux { + pins = "gpio143"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio143"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sck { + pri_mi2s_sck_sleep: pri_mi2s_sck_sleep { + mux { + pins = "gpio144"; + function = "gpio"; + }; + + config { + pins = "gpio144"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sck_active: pri_mi2s_sck_active { + mux { + pins = "gpio144"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio144"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_ws { + pri_mi2s_ws_sleep: pri_mi2s_ws_sleep { + mux { + pins = "gpio145"; + function = "gpio"; + }; + + config { + pins = "gpio145"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_ws_active: pri_mi2s_ws_active { + mux { + pins = "gpio145"; + function = "pri_mi2s_ws"; + }; + + config { + pins = "gpio145"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sd0 { + pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep { + mux { + pins = "gpio146"; + function = "gpio"; + }; + + config { + pins = "gpio146"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd0_active: pri_mi2s_sd0_active { + mux { + pins = "gpio146"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio146"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_mi2s_sd1 { + pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep { + mux { + pins = "gpio147"; + function = "gpio"; + }; + + config { + pins = "gpio147"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd1_active: pri_mi2s_sd1_active { + mux { + pins = "gpio147"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio147"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_mi2s_mclk { + quin_mi2s_mclk_sleep: quin_mi2s_mclk_sleep { + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + quin_mi2s_mclk_active: quin_mi2s_mclk_active { + mux { + pins = "gpio148"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio148"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_mi2s { + quin_mi2s_sleep: quin_mi2s_sleep { + mux { + pins = "gpio149", "gpio151"; + function = "gpio"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_mi2s_active: quin_mi2s_active { + mux { + pins = "gpio149", "gpio151"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quin_mi2s_sd0 { + quin_mi2s_sd0_sleep: quin_mi2s_sd0_sleep { + mux { + pins = "gpio150"; + function = "gpio"; + }; + + config { + pins = "gpio150"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_mi2s_sd0_active: quin_mi2s_sd0_active { + mux { + pins = "gpio150"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio150"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_mi2s_sd1 { + quin_mi2s_sd1_sleep: quin_mi2s_sd1_sleep { + mux { + pins = "gpio152"; + function = "gpio"; + }; + + config { + pins = "gpio152"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_mi2s_sd1_active: quin_mi2s_sd1_active { + mux { + pins = "gpio152"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio152"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + /* add pins for DisplayPort */ + sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + bias-disable; + drive-strength = <16>; + }; + }; + + sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_eldo2_default: cam_sensor_eldo2_default { + /* AVDD ELDO2 */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* NO PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + camera_vaf_en_default: camera_vaf_en_default { + /* VAF ELDO1 */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + camera_vana_en_default: camera_vana_en_default { + /* VANA ELDO2 */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rear: cam_sensor_active_rear { + /* RESET REAR2 */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rear: cam_sensor_suspend_rear { + /* RESET REAR2 */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rear_aux: cam_sensor_active_rear_aux { + /* RESET REARAUX */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rear_aux: cam_sensor_suspend_rear_aux { + /* RESET REARAUX */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_front: cam_sensor_active_front { + /* RESET FRONT */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_front: cam_sensor_suspend_front { + /* RESET FRONT */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_iris: cam_sensor_active_iris { + /* RESET IRIS */ + mux { + pins = "gpio23", "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_iris: cam_sensor_suspend_iris { + /* RESET IRIS */ + mux { + pins = "gpio23", "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio26"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_triple_rear: cam_sensor_active_triple_rear { + mux { + pins = "gpio30", "gpio157", "gpio158"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio157", "gpio158"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_triple_rear: cam_sensor_suspend_triple_rear { + mux { + pins = "gpio30", "gpio157", "gpio158"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio157", "gpio158"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_triple_rear_aux: + cam_sensor_active_triple_rear_aux { + mux { + pins = "gpio23", "gpio159", "gpio160"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio159", "gpio160"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_triple_rear_aux: + cam_sensor_suspend_triple_rear_aux { + mux { + pins = "gpio23", "gpio159", "gpio160"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio159", "gpio160"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_triple_rear_aux2: + cam_sensor_active_triple_rear_aux2 { + mux { + pins = "gpio28", "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio24", "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_triple_rear_aux2: + cam_sensor_suspend_triple_rear_aux2 { + mux { + pins = "gpio28", "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio24", "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cci0_active: cci0_active { + mux { + /* CLK, DATA */ + pins = "gpio17","gpio18"; // Only 2 + function = "cci_i2c"; + }; + + config { + pins = "gpio17","gpio18"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio17","gpio18"; + function = "cci_i2c"; + }; + + config { + pins = "gpio17","gpio18"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA */ + pins = "gpio19","gpio20"; + function = "cci_i2c"; + }; + + config { + pins = "gpio19","gpio20"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio19","gpio20"; + function = "cci_i2c"; + }; + + config { + pins = "gpio19","gpio20"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_active: cci2_active { + mux { + /* CLK, DATA */ + pins = "gpio31","gpio32"; + function = "cci_i2c"; + }; + + config { + pins = "gpio31","gpio32"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_suspend: cci2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio31","gpio32"; + function = "cci_i2c"; + }; + + config { + pins = "gpio31","gpio32"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_active: cci3_active { + mux { + /* CLK, DATA */ + pins = "gpio33","gpio34"; + function = "cci_i2c"; + }; + + config { + pins = "gpio33","gpio34"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_suspend: cci3_suspend { + mux { + /* CLK, DATA */ + pins = "gpio33","gpio34"; + function = "cci_i2c"; + }; + + config { + pins = "gpio33","gpio34"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + fsa_usbc_ana_en_n@100 { + fsa_usbc_ana_en: fsa_usbc_ana_en { + mux { + pins = "gpio100"; + function = "gpio"; + }; + + config { + pins = "gpio100"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + }; + + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_on: cd_on { + mux { + pins = "gpio96"; /* sdcard_det */ + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_cd_off: cd_off { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie0 { + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio36"; + function = "pci_e0"; + }; + + config { + pins = "gpio36"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie1 { + pcie1_clkreq_default: pcie1_clkreq_default { + mux { + pins = "gpio103"; + function = "pci_e1"; + }; + + config { + pins = "gpio103"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_perst_default: pcie1_perst_default { + mux { + pins = "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio102"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie1_wake_default: pcie1_wake_default { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie_ep { + pcie_ep_clkreq_default: pcie_ep_clkreq_default { + mux { + pins = "gpio103"; + function = "pci_e1"; + }; + config { + pins = "gpio103"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio102"; + function = "gpio"; + }; + config { + pins = "gpio102"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio104"; + function = "gpio"; + }; + config { + pins = "gpio104"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + emac { + emac_mdc: emac_mdc { + mux { + pins = "gpio7"; + function = "rgmii_mdc"; + }; + + config { + pins = "gpio7"; + bias-pull-up; + }; + }; + emac_mdio: emac_mdio { + mux { + pins = "gpio59"; + function = "rgmii_mdio"; + }; + + config { + pins = "gpio59"; + bias-pull-up; + }; + }; + + emac_rgmii_txd0: emac_rgmii_txd0 { + mux { + pins = "gpio122"; + function = "rgmii_txd0"; + }; + + config { + pins = "gpio122"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txd1: emac_rgmii_txd1 { + mux { + pins = "gpio4"; + function = "rgmii_txd1"; + }; + + config { + pins = "gpio4"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txd2: emac_rgmii_txd2 { + mux { + pins = "gpio5"; + function = "rgmii_txd2"; + }; + + config { + pins = "gpio5"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txd3: emac_rgmii_txd3 { + mux { + pins = "gpio6"; + function = "rgmii_txd3"; + }; + + config { + pins = "gpio6"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txc: emac_rgmii_txc { + mux { + pins = "gpio114"; + function = "rgmii_txc"; + }; + + config { + pins = "gpio114"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_tx_ctl: emac_rgmii_tx_ctl { + mux { + pins = "gpio121"; + function = "rgmii_tx"; + }; + + config { + pins = "gpio121"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_rxd0: emac_rgmii_rxd0 { + mux { + pins = "gpio117"; + function = "rgmii_rxd0"; + }; + + config { + pins = "gpio117"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2MA */ + }; + }; + + emac_rgmii_rxd1: emac_rgmii_rxd1 { + mux { + pins = "gpio118"; + function = "rgmii_rxd1"; + }; + + config { + pins = "gpio118"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_rgmii_rxd2: emac_rgmii_rxd2 { + mux { + pins = "gpio119"; + function = "rgmii_rxd2"; + }; + + config { + pins = "gpio119"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_rgmii_rxd3: emac_rgmii_rxd3 { + mux { + pins = "gpio120"; + function = "rgmii_rxd3"; + }; + + config { + pins = "gpio120"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_rgmii_rxc: emac_rgmii_rxc { + mux { + pins = "gpio115"; + function = "rgmii_rxc"; + }; + + config { + pins = "gpio115"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_rgmii_rx_ctl: emac_rgmii_rx_ctl { + mux { + pins = "gpio116"; + function = "rgmii_rx"; + }; + + config { + pins = "gpio116"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_phy_intr: emac_phy_intr { + mux { + pins = "gpio124"; + function = "emac_phy"; + }; + config { + pins = "gpio124"; + bias-disable; /* NO pull */ + drive-strength = <8>; + }; + }; + + emac_phy_reset_state: emac_phy_reset_state { + mux { + pins = "gpio79"; + function = "gpio"; + }; + config { + pins = "gpio79"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_pin_pps_0: emac_pin_pps_0 { + mux { + pins = "gpio81"; + function = "emac_pps"; + }; + + config { + pins = "gpio81"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + }; + + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio169"; + function = "gpio"; + }; + + config { + pins = "gpio169"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio169"; + function = "gpio"; + }; + + config { + pins = "gpio169"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + }; + + usb2phy_ac_en1_default: usb2phy_ac_en1_default { + mux { + pins = "gpio113"; + function = "usb2phy_ac"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; + bias-disable; + }; + }; + + usb2phy_ac_en2_default: usb2phy_ac_en2_default { + mux { + pins = "gpio123"; + function = "usb2phy_ac"; + }; + + config { + pins = "gpio123"; + drive-strength = <2>; + bias-disable; + }; + }; + + audio_ioexp_reset_active: audio_ioexp_reset_active { + mux { + pins = "gpio166"; + function = "gpio"; + }; + config { + pins = "gpio166"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + tsif0_signals_active: tsif0_signals_active { + tsif1_clk { + pins = "gpio88"; /* TSIF0 CLK */ + function = "tsif1_clk"; + }; + tsif1_en { + pins = "gpio89"; /* TSIF0 Enable */ + function = "tsif1_en"; + }; + tsif1_data { + pins = "gpio90"; /* TSIF0 DATA */ + function = "tsif1_data"; + }; + signals_cfg { + pins = "gpio88", "gpio89", "gpio90"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + /* sync signal is only used if configured to mode-2 */ + tsif0_sync_active: tsif0_sync_active { + tsif1_sync { + pins = "gpio91"; /* TSIF0 SYNC */ + function = "tsif1_sync"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + tsif1_signals_active: tsif1_signals_active { + tsif2_clk { + pins = "gpio92"; /* TSIF1 CLK */ + function = "tsif2_clk"; + }; + tsif2_en { + pins = "gpio93"; /* TSIF1 Enable */ + function = "tsif2_en"; + }; + tsif2_data { + pins = "gpio94"; /* TSIF1 DATA */ + function = "tsif2_data"; + }; + signals_cfg { + pins = "gpio92", "gpio93", "gpio94"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + /* sync signal is only used if configured to mode-2 */ + tsif1_sync_active: tsif1_sync_active { + tsif2_sync { + pins = "gpio95"; /* TSIF1 SYNC */ + function = "tsif2_sync"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + conn_power_1p8_active: conn_power_1p8_active { + mux { + pins = "gpio173"; + function = "gpio"; + }; + + config { + pins = "gpio173"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + conn_power_pa_active: conn_power_pa_active { + mux { + pins = "gpio174"; + function = "gpio"; + }; + + config { + pins = "gpio174"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + bt_en_active: bt_en_active { + mux { + pins = "gpio172"; + function = "gpio"; + }; + + config { + pins = "gpio172"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + /* SE0 pin mappings */ + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_active: qupv3_se0_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "qup0"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_active: qupv3_se0_spi_active { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "qup0"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 1 pin mappings */ + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_active: qupv3_se1_i2c_active { + mux { + pins = "gpio114", "gpio115"; + function = "qup1"; + }; + + config { + pins = "gpio114", "gpio115"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio114", "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio114", "gpio115"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_active: qupv3_se1_spi_active { + mux { + pins = "gpio114", "gpio115", "gpio116", + "gpio117"; + function = "qup1"; + }; + + config { + pins = "gpio114", "gpio115", "gpio116", + "gpio117"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio114", "gpio115", "gpio116", + "gpio117"; + function = "gpio"; + }; + + config { + pins = "gpio114", "gpio115", "gpio116", + "gpio117"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 2 pin mappings */ + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio126", "gpio127"; + function = "qup2"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio126", "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_active: qupv3_se2_spi_active { + mux { + pins = "gpio126", "gpio127", "gpio128", + "gpio129"; + function = "qup2"; + }; + + config { + pins = "gpio126", "gpio127", "gpio128", + "gpio129"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio126", "gpio127", "gpio128", + "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio126", "gpio127", "gpio128", + "gpio129"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 3 pin mappings */ + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_active: qupv3_se3_i2c_active { + mux { + pins = "gpio144", "gpio145"; + function = "qup3"; + }; + + config { + pins = "gpio144", "gpio145"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio144", "gpio145"; + function = "gpio"; + }; + + config { + pins = "gpio144", "gpio145"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se3_spi_pins: qupv3_se3_spi_pins { + qupv3_se3_spi_active: qupv3_se3_spi_active { + mux { + pins = "gpio144", "gpio145", "gpio146", + "gpio147"; + function = "qup3"; + }; + + config { + pins = "gpio144", "gpio145", "gpio146", + "gpio147"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { + mux { + pins = "gpio144", "gpio145", "gpio146", + "gpio147"; + function = "qup3"; + }; + + config { + pins = "gpio144", "gpio145", "gpio146", + "gpio147"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 4 pin mappings */ + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_active: qupv3_se4_i2c_active { + mux { + pins = "gpio51", "gpio52"; + function = "qup4"; + }; + + config { + pins = "gpio51", "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio51", "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio51", "gpio52"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se4_spi_pins: qupv3_se4_spi_pins { + qupv3_se4_spi_active: qupv3_se4_spi_active { + mux { + pins = "gpio51", "gpio52", "gpio53", + "gpio54"; + function = "qup4"; + }; + + config { + pins = "gpio51", "gpio52", "gpio53", + "gpio54"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { + mux { + pins = "gpio51", "gpio52", "gpio53", + "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio51", "gpio52", "gpio53", + "gpio54"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 5 pin mappings */ + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_active: qupv3_se5_i2c_active { + mux { + pins = "gpio121", "gpio122"; + function = "qup5"; + }; + + config { + pins = "gpio121", "gpio122"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio121", "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio121", "gpio122"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se5_spi_pins: qupv3_se5_spi_pins { + qupv3_se5_spi_active: qupv3_se5_spi_active { + mux { + pins = "gpio119", "gpio120", "gpio121", + "gpio122"; + function = "qup5"; + }; + + config { + pins = "gpio119", "gpio120", "gpio121", + "gpio122"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { + mux { + pins = "gpio119", "gpio120", "gpio121", + "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio119", "gpio120", "gpio121", + "gpio122"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 6 pin mappings */ + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_active: qupv3_se6_i2c_active { + mux { + pins = "gpio6", "gpio7"; + function = "qup6"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_active: qupv3_se6_spi_active { + mux { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + function = "qup6"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 7 pin mappings */ + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_active: qupv3_se7_i2c_active { + mux { + pins = "gpio98", "gpio99"; + function = "qup7"; + }; + + config { + pins = "gpio98", "gpio99"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio98", "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio98", "gpio99"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se7_spi_pins: qupv3_se7_spi_pins { + qupv3_se7_spi_active: qupv3_se7_spi_active { + mux { + pins = "gpio98", "gpio99", "gpio100", + "gpio101"; + function = "qup7"; + }; + + config { + pins = "gpio98", "gpio99", "gpio100", + "gpio101"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_sleep: qupv3_se7_spi_sleep { + mux { + pins = "gpio98", "gpio99", "gpio100", + "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio98", "gpio99", "gpio100", + "gpio101"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* QUPv3 East instances */ + /* SE 8 pin mappings */ + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_active: qupv3_se8_i2c_active { + mux { + pins = "gpio88", "gpio89"; + function = "qup8"; + }; + + config { + pins = "gpio88", "gpio89"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio88", "gpio89"; + function = "gpio"; + }; + + config { + pins = "gpio88", "gpio89"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se8_spi_pins: qupv3_se8_spi_pins { + qupv3_se8_spi_active: qupv3_se8_spi_active { + mux { + pins = "gpio88", "gpio89", "gpio90", + "gpio91"; + function = "qup8"; + }; + + config { + pins = "gpio88", "gpio89", "gpio90", + "gpio91"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { + mux { + pins = "gpio88", "gpio89", "gpio90", + "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio88", "gpio89", "gpio90", + "gpio91"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 9 pin mappings */ + qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { + qupv3_se9_i2c_active: qupv3_se9_i2c_active { + mux { + pins = "gpio39", "gpio40"; + function = "qup9"; + }; + + config { + pins = "gpio39", "gpio40"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { + mux { + pins = "gpio39", "gpio40"; + function = "gpio"; + }; + + config { + pins = "gpio39", "gpio40"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se9_spi_pins: qupv3_se9_spi_pins { + qupv3_se9_spi_active: qupv3_se9_spi_active { + mux { + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; + function = "qup9"; + }; + + config { + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { + mux { + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; + function = "gpio"; + }; + + config { + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 10 pin mappings */ + qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { + qupv3_se10_i2c_active: qupv3_se10_i2c_active { + mux { + pins = "gpio9", "gpio10"; + function = "qup10"; + }; + + config { + pins = "gpio9", "gpio10"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { + mux { + pins = "gpio9", "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio9", "gpio10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se10_spi_pins: qupv3_se10_spi_pins { + qupv3_se10_spi_active: qupv3_se10_spi_active { + mux { + pins = "gpio9", "gpio10", "gpio11", + "gpio12"; + function = "qup10"; + }; + + config { + pins = "gpio9", "gpio10", "gpio11", + "gpio12"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { + mux { + pins = "gpio9", "gpio10", "gpio11", + "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio9", "gpio10", "gpio11", + "gpio12"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 11 pin mappings */ + qupv3_se11_i2c_pins: qupv3_se11_i2c_pins { + qupv3_se11_i2c_active: qupv3_se11_i2c_active { + mux { + pins = "gpio94", "gpio95"; + function = "qup11"; + }; + + config { + pins = "gpio94", "gpio95"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep { + mux { + pins = "gpio94", "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio94", "gpio95"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se11_spi_pins: qupv3_se11_spi_pins { + qupv3_se11_spi_active: qupv3_se11_spi_active { + mux { + pins = "gpio92", "gpio93", "gpio94", + "gpio95"; + function = "qup11"; + }; + + config { + pins = "gpio92", "gpio93", "gpio94", + "gpio95"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_sleep: qupv3_se11_spi_sleep { + mux { + pins = "gpio92", "gpio93", "gpio94", + "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio92", "gpio93", "gpio94", + "gpio95"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 12 pin mappings */ + qupv3_se12_i2c_pins: qupv3_se12_i2c_pins { + qupv3_se12_i2c_active: qupv3_se12_i2c_active { + mux { + pins = "gpio83", "gpio84"; + function = "qup12"; + }; + + config { + pins = "gpio83", "gpio84"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep { + mux { + pins = "gpio83", "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio83", "gpio84"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se12_spi_pins: qupv3_se12_spi_pins { + qupv3_se12_spi_active: qupv3_se12_spi_active { + mux { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + function = "qup12"; + }; + + config { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_sleep: qupv3_se12_spi_sleep { + mux { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 13 pin mappings */ + qupv3_se13_i2c_pins: qupv3_se13_i2c_pins { + qupv3_se13_i2c_active: qupv3_se13_i2c_active { + mux { + pins = "gpio43", "gpio44"; + function = "qup13"; + }; + + config { + pins = "gpio43", "gpio44"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep { + mux { + pins = "gpio43", "gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio43", "gpio44"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se13_spi_pins: qupv3_se13_spi_pins { + qupv3_se13_spi_active: qupv3_se13_spi_active { + mux { + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; + function = "qup13"; + }; + + config { + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se13_spi_sleep: qupv3_se13_spi_sleep { + mux { + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; + function = "gpio"; + }; + + config { + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + + /* SE 14 pin mappings */ + qupv3_se14_i2c_pins: qupv3_se14_i2c_pins { + qupv3_se14_i2c_active: qupv3_se14_i2c_active { + mux { + pins = "gpio47", "gpio48"; + function = "qup14"; + }; + + config { + pins = "gpio47", "gpio48"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep { + mux { + pins = "gpio47", "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio47", "gpio48"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se14_spi_pins: qupv3_se14_spi_pins { + qupv3_se14_spi_active: qupv3_se14_spi_active { + mux { + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; + function = "qup14"; + }; + + config { + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se14_spi_sleep: qupv3_se14_spi_sleep { + mux { + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 15 pin mappings */ + qupv3_se15_i2c_pins: qupv3_se15_i2c_pins { + qupv3_se15_i2c_active: qupv3_se15_i2c_active { + mux { + pins = "gpio27", "gpio28"; + function = "qup15"; + }; + + config { + pins = "gpio27", "gpio28"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep { + mux { + pins = "gpio27", "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio27", "gpio28"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se15_spi_pins: qupv3_se15_spi_pins { + qupv3_se15_spi_active: qupv3_se15_spi_active { + mux { + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; + function = "qup15"; + }; + + config { + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_sleep: qupv3_se15_spi_sleep { + mux { + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 16 pin mappings */ + qupv3_se16_i2c_pins: qupv3_se16_i2c_pins { + qupv3_se16_i2c_active: qupv3_se16_i2c_active { + mux { + pins = "gpio86", "gpio85"; + function = "qup16"; + }; + + config { + pins = "gpio86", "gpio85"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se16_i2c_sleep: qupv3_se16_i2c_sleep { + mux { + pins = "gpio86", "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio86", "gpio85"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se16_spi_pins: qupv3_se16_spi_pins { + qupv3_se16_spi_active: qupv3_se16_spi_active { + mux { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + function = "qup16"; + }; + + config { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se16_spi_sleep: qupv3_se16_spi_sleep { + mux { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 17 pin mappings */ + qupv3_se17_i2c_pins: qupv3_se17_i2c_pins { + qupv3_se17_i2c_active: qupv3_se17_i2c_active { + mux { + pins = "gpio55", "gpio56"; + function = "qup17"; + }; + + config { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se17_i2c_sleep: qupv3_se17_i2c_sleep { + mux { + pins = "gpio55", "gpio56"; + function = "gpio"; + }; + + config { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se17_spi_pins: qupv3_se17_spi_pins { + qupv3_se17_spi_active: qupv3_se17_spi_active { + mux { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + function = "qup17"; + }; + + config { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se17_spi_sleep: qupv3_se17_spi_sleep { + mux { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + function = "gpio"; + }; + + config { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 18 pin mappings */ + qupv3_se18_i2c_pins: qupv3_se18_i2c_pins { + qupv3_se18_i2c_active: qupv3_se18_i2c_active { + mux { + pins = "gpio23", "gpio24"; + function = "qup18"; + }; + + config { + pins = "gpio23", "gpio24"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se18_i2c_sleep: qupv3_se18_i2c_sleep { + mux { + pins = "gpio23", "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio24"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se18_spi_pins: qupv3_se18_spi_pins { + qupv3_se18_spi_active: qupv3_se18_spi_active { + mux { + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; + function = "qup18"; + }; + + config { + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se18_spi_sleep: qupv3_se18_spi_sleep { + mux { + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 19 pin mappings */ + qupv3_se19_i2c_pins: qupv3_se19_i2c_pins { + qupv3_se19_i2c_active: qupv3_se19_i2c_active { + mux { + pins = "gpio181", "gpio182"; + function = "qup19"; + }; + + config { + pins = "gpio181", "gpio182"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se19_i2c_sleep: qupv3_se19_i2c_sleep { + mux { + pins = "gpio181", "gpio182"; + function = "gpio"; + }; + + config { + pins = "gpio181", "gpio182"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se19_spi_pins: qupv3_se19_spi_pins { + qupv3_se19_spi_active: qupv3_se19_spi_active { + mux { + pins = "gpio181", "gpio182", "gpio183", + "gpio184"; + function = "qup19"; + }; + + config { + pins = "gpio181", "gpio182", "gpio183", + "gpio184"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se19_spi_sleep: qupv3_se19_spi_sleep { + mux { + pins = "gpio181", "gpio182", "gpio183", + "gpio184"; + function = "gpio"; + }; + + config { + pins = "gpio181", "gpio182", "gpio183", + "gpio184"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + + /* SE12 UART-2wire pin mappings */ + qupv3_se12_2uart_pins: qupv3_se12_2uart_pins { + qupv3_se12_2uart_active: qupv3_se12_2uart_active { + mux { + pins = "gpio85", "gpio86"; + function = "qup12"; + }; + + config { + pins = "gpio85", "gpio86"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se12_2uart_sleep: qupv3_se12_2uart_sleep { + mux { + pins = "gpio85", "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio85", "gpio86"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + trigout_a: trigout_a { + mux { + pins = "gpio141"; + function = "qdss_cti"; + }; + config { + pins = "gpio141"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* SE 10 pin mappings */ + qupv3_se10_2uart_pins: qupv3_se10_2uart_pins { + qupv3_se10_2uart_active: qupv3_se10_2uart_active { + mux { + pins = "gpio11", "gpio12"; + function = "qup10"; + }; + + config { + pins = "gpio11", "gpio12"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se10_2uart_sleep: qupv3_se10_2uart_sleep { + mux { + pins = "gpio11", "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio11", "gpio12"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + /* SE 13 UART 4-Wire pin mappings */ + qupv3_se13_4uart_pins: qupv3_se13_4uart_pins { + qupv3_se13_default_ctsrtsrx: + qupv3_se13_default_ctsrtsrx { + mux { + pins = "gpio43", "gpio44", "gpio46"; + function = "gpio"; + }; + + config { + pins = "gpio43", "gpio44", "gpio46"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se13_default_tx: qupv3_se13_default_tx { + mux { + pins = "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio45"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se13_ctsrx: qupv3_se13_ctsrx { + mux { + pins = "gpio43", "gpio46"; + function = "qup13"; + }; + + config { + pins = "gpio43", "gpio46"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se13_rts: qupv3_se13_rts { + mux { + pins = "gpio44"; + function = "qup13"; + }; + + config { + pins = "gpio44"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se13_tx: qupv3_se13_tx { + mux { + pins = "gpio45"; + function = "qup13"; + }; + + config { + pins = "gpio45"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-pmic-overlay.dtsi b/arch/arm/boot/dts/qcom/sdmshrike-pmic-overlay.dtsi new file mode 100644 index 000000000000..f8eb68fe164a --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-pmic-overlay.dtsi @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "pm8150.dtsi" +#include "pm8150l.dtsi" + +pm8150_1_gpios: &pm8150_gpios { + interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>, + <0x0 0xc2 0 IRQ_TYPE_NONE>, + <0x0 0xc3 0 IRQ_TYPE_NONE>, + <0x0 0xc5 0 IRQ_TYPE_NONE>, + <0x0 0xc8 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8150_1_gpio1", "pm8150_1_gpio3", + "pm8150_1_gpio4", "pm8150_1_gpio6", + "pm8150_1_gpio9"; + qcom,gpios-disallowed = <2 5 7 8 10>; +}; + +/* PM8150_2: */ +&spmi_bus { + qcom,pm8150@8 { + compatible = "qcom,spmi-pmic"; + reg = <0x8 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + + pm8150_2_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0xa00>; + interrupts = <0x8 0xc0 0 IRQ_TYPE_NONE>, + <0x8 0xc2 0 IRQ_TYPE_NONE>, + <0x8 0xc3 0 IRQ_TYPE_NONE>, + <0x8 0xc5 0 IRQ_TYPE_NONE>, + <0x8 0xc8 0 IRQ_TYPE_NONE>, + <0x8 0xc9 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8150_2_gpio1", "pm8150_2_gpio3", + "pm8150_2_gpio4", "pm8150_2_gpio6", + "pm8150_2_gpio9", "pm8150_2_gpio10"; + gpio-controller; + #gpio-cells = <2>; + qcom,gpios-disallowed = <2 5 7 8>; + }; + }; + + qcom,pm8150@9 { + compatible ="qcom,spmi-pmic"; + reg = <0x9 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +/* PMK8002: */ +&spmi_bus { + qcom,pm8150@6 { + compatible = "qcom,spmi-pmic"; + reg = <0x6 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + + pmk8002_clkdiv: clock-controller@5b00 { + compatible = "qcom,spmi-clkdiv"; + reg = <0x5b00 0x100>; + #clock-cells = <1>; + qcom,num-clkdivs = <1>; + clock-output-names = "pmk8002_div_clk1"; + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + }; + }; + + qcom,pm8150@7 { + compatible ="qcom,spmi-pmic"; + reg = <0x7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +/* PMIC GPIO pin control configurations: */ +&pm8150_1_gpios { + key_home { + key_home_default: key_home_default { + pins = "gpio1"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; + + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-qupv3.dtsi b/arch/arm/boot/dts/qcom/sdmshrike-qupv3.dtsi new file mode 100644 index 000000000000..b26cb64f139f --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-qupv3.dtsi @@ -0,0 +1,989 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + /* QUPv3 West Instances + * West 0 : SE 0 + * West 1 : SE 1 + * West 2 : SE 2 + * West 3 : SE 3 + * West 4 : SE 4 + * West 5 : SE 5 + * West 6 : SE 6 + * West 7 : SE 7 + */ + qupv3_0: qcom,qupv3_0_geni_se@8c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x8c0000 0x6000>; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; + qcom,iommu-s1-bypass; + + iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0x4c3 0x0>; + }; + }; + + /* I2C */ + qupv3_se0_i2c: i2c@880000 { + compatible = "qcom,i2c-geni"; + reg = <0x880000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@884000 { + compatible = "qcom,i2c-geni"; + reg = <0x884000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@888000 { + compatible = "qcom,i2c-geni"; + reg = <0x888000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@88c000 { + compatible = "qcom,i2c-geni"; + reg = <0x88c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@890000 { + compatible = "qcom,i2c-geni"; + reg = <0x890000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@894000 { + compatible = "qcom,i2c-geni"; + reg = <0x894000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@898000 { + compatible = "qcom,i2c-geni"; + reg = <0x898000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se7_i2c: i2c@89c000 { + compatible = "qcom,i2c-geni"; + reg = <0x89c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se0_spi: spi@880000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x880000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_spi: spi@884000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x884000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_spi: spi@888000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x888000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se3_spi: spi@88c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x88c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se4_spi: spi@890000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x890000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se5_spi: spi@894000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x894000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se6_spi: spi@898000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x898000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se7_spi: spi@89c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x89c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_active>; + pinctrl-1 = <&qupv3_se7_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* QUPv3 East0 and East1 Instances + * East1 0 : SE 8 + * East1 1 : SE 9 + * East1 2 : SE 10 + * East1 3 : SE 11 + * East1 4 : SE 12 + * East1 5 : SE 16 + * East1 0 : SE 17 + * East0 1 : SE 18 + * East0 2 : SE 19 + * East0 3 : SE 13 + * East0 4 : SE 14 + * East0 5 : SE 15 + */ + + /* QUPv3 East1 Instances */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0xac0000 0x6000>; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; + qcom,iommu-s1-bypass; + + iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0x603 0x0>; + }; + }; + + /* 2-wire UART */ + + /* Debug UART Instance for CDP/MTP platform */ + qupv3_se12_2uart: qcom,qup_uart@a90000 { + compatible = "qcom,msm-geni-console", "qcom,msm-geni-uart"; + reg = <0xa90000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_2uart_active>; + pinctrl-1 = <&qupv3_se12_2uart_sleep>; + interrupts = ; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* Debug UART Instance for RUMI platform */ + qupv3_se10_2uart: qcom,qup_uart@a88000 { + compatible = "qcom,msm-geni-console", "qcom,msm-geni-uart"; + reg = <0xa88000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_2uart_active>; + pinctrl-1 = <&qupv3_se10_2uart_sleep>; + interrupts = ; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* I2C */ + qupv3_se8_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se10_i2c: i2c@a88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_i2c_active>; + pinctrl-1 = <&qupv3_se10_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se11_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_i2c_active>; + pinctrl-1 = <&qupv3_se11_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se12_i2c: i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_i2c_active>; + pinctrl-1 = <&qupv3_se12_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se13_i2c: i2c@c8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xc8c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_i2c_active>; + pinctrl-1 = <&qupv3_se13_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se8_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa80000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_spi_active>; + pinctrl-1 = <&qupv3_se8_spi_active>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se9_spi: spi@a84000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa84000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se10_spi: spi@a88000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa88000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_spi_active>; + pinctrl-1 = <&qupv3_se10_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se11_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_spi_active>; + pinctrl-1 = <&qupv3_se11_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se12_spi: spi@a90000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa90000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_spi_active>; + pinctrl-1 = <&qupv3_se12_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se13_spi: spi@c8c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_spi_active>; + pinctrl-1 = <&qupv3_se13_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + /* QUPv3 East0 Instances */ + qupv3_2: qcom,qupv3_2_geni_se@cc0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0xcc0000 0x6000>; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; + qcom,iommu-s1-bypass; + + iommu_qupv3_2_geni_se_cb: qcom,iommu_qupv3_2_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0x7a3 0x0>; + }; + }; + + /* 4-wire UART */ + qupv3_se13_4uart: qcom,qup_uart@c8c000 { + compatible = "qcom,msm-geni-serial-hs", "qcom,msm-geni-uart"; + reg = <0xc8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_default_ctsrtsrx>, + <&qupv3_se13_default_tx>; + pinctrl-1 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>, + <&qupv3_se13_tx>; + pinctrl-2 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>, + <&qupv3_se13_tx>; + interrupts-extended = <&pdc GIC_SPI 585 0>, + <&tlmm 46 0>; + qcom,wrapper-core = <&qupv3_2>; + qcom,wakeup-byte = <0xFD>; + status = "disabled"; + }; + + /* I2C */ + qupv3_se14_i2c: i2c@0xc90000 { + compatible = "qcom,i2c-geni"; + reg = <0xc90000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_i2c_active>; + pinctrl-1 = <&qupv3_se14_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se15_i2c: i2c@0xc94000 { + compatible = "qcom,i2c-geni"; + reg = <0xc94000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S5_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_i2c_active>; + pinctrl-1 = <&qupv3_se15_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se16_i2c: i2c@0xa94000 { + compatible = "qcom,i2c-geni"; + reg = <0xa94000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se16_i2c_active>; + pinctrl-1 = <&qupv3_se16_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se17_i2c: i2c@0xc80000 { + compatible = "qcom,i2c-geni"; + reg = <0xc80000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se17_i2c_active>; + pinctrl-1 = <&qupv3_se17_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se18_i2c: i2c@0xc84000 { + compatible = "qcom,i2c-geni"; + reg = <0xc84000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S1_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se18_i2c_active>; + pinctrl-1 = <&qupv3_se18_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se19_i2c: i2c@0xc88000 { + compatible = "qcom,i2c-geni"; + reg = <0xc88000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se19_i2c_active>; + pinctrl-1 = <&qupv3_se19_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se14_spi: spi@c90000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc90000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_spi_active>; + pinctrl-1 = <&qupv3_se14_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se15_spi: spi@c94000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc94000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S5_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_spi_active>; + pinctrl-1 = <&qupv3_se15_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se16_spi: spi@a94000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa94000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se16_spi_active>; + pinctrl-1 = <&qupv3_se16_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se17_spi: spi@c80000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc80000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se17_spi_active>; + pinctrl-1 = <&qupv3_se17_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se18_spi: spi@c84000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc84000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S1_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se18_spi_active>; + pinctrl-1 = <&qupv3_se18_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se19_spi: spi@c88000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc88000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se19_spi_active>; + pinctrl-1 = <&qupv3_se19_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + /* QUPv3 SSC Instances */ + qupv3_3: qcom,qupv3_3_geni_se@26c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x26c0000 0x6000>; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; + qcom,iommu-s1-bypass; + + iommu_qupv3_3_geni_se_cb: qcom,iommu_qupv3_3_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0x4e3 0x0>; + }; + }; + + /* I2C */ + qupv3_se20_i2c: i2c@2680000 { + compatible = "qcom,i2c-geni"; + reg = <0x2680000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_scc SCC_QUPV3_SE0_CLK>, + <&clock_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se20_i2c_active>; + pinctrl-1 = <&qupv3_se20_i2c_sleep>; + qcom,wrapper-core = <&qupv3_3>; + status = "disabled"; + }; + + qupv3_se21_i2c: i2c@2684000 { + compatible = "qcom,i2c-geni"; + reg = <0x2684000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_scc SCC_QUPV3_SE1_CLK>, + <&clock_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se21_i2c_active>; + pinctrl-1 = <&qupv3_se21_i2c_sleep>; + qcom,wrapper-core = <&qupv3_3>; + status = "disabled"; + }; + + qupv3_se22_i2c: i2c@2688000 { + compatible = "qcom,i2c-geni"; + reg = <0x2688000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_scc SCC_QUPV3_SE2_CLK>, + <&clock_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se22_i2c_active>; + pinctrl-1 = <&qupv3_se22_i2c_sleep>; + qcom,wrapper-core = <&qupv3_3>; + status = "disabled"; + }; + + qupv3_se23_i2c: i2c@268c000 { + compatible = "qcom,i2c-geni"; + reg = <0x268c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_scc SCC_QUPV3_SE3_CLK>, + <&clock_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se23_i2c_active>; + pinctrl-1 = <&qupv3_se23_i2c_sleep>; + qcom,wrapper-core = <&qupv3_3>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se21_spi: spi@2684000 { + compatible = "qcom,spi-geni"; + reg = <0x2684000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_scc SCC_QUPV3_SE1_CLK>, + <&clock_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se21_spi_active>; + pinctrl-1 = <&qupv3_se21_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_3>; + status = "disabled"; + }; + + qupv3_se22_spi: spi@2688000 { + compatible = "qcom,spi-geni"; + reg = <0x2688000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_scc SCC_QUPV3_SE2_CLK>, + <&clock_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se22_spi_active>; + pinctrl-1 = <&qupv3_se22_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_3>; + qcom,disable-dma; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-regulators.dtsi b/arch/arm/boot/dts/qcom/sdmshrike-regulators.dtsi new file mode 100644 index 000000000000..51e4f9916842 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-regulators.dtsi @@ -0,0 +1,971 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + /* Stub regulators */ + + /* + * RPMh does not provide support for PM8150_1 S4. Therefore, + * use a stub regulator for S4. + */ + S4A: pm8150_1_s4: regulator-pm8150_1-s4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_1_s4"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&soc { + + /* PM8150_1 regulators */ + + rpmh-regulator-smpa5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpa5"; + S5A: pm8150_1_s5: regulator-pm8150_1-s5 { + regulator-name = "pm8150_1_s5"; + qcom,set = ; + regulator-min-microvolt = <1824000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1824000>; + }; + }; + + /* PM8150_1 S10 + S9 + S8 + S7 + S6 = VDD_GFX */ + rpmh-regulator-gfxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "gfx.lvl"; + S10A_LEVEL: pm8150_1_s10_level: regulator-pm8150_1-s10-level { + regulator-name = "pm8150_1_s10_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + rpmh-regulator-ldoa3 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L3A: pm8150_1_l3: regulator-pm8150_1-l3 { + regulator-name = "pm8150_1_l3"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L5A: pm8150_1_l5: regulator-pm8150_1-l5 { + regulator-name = "pm8150_1_l5"; + qcom,set = ; + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <932000>; + qcom,init-voltage = <480000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa6 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L6A: pm8150_1_l6: regulator-pm8150_1-l6 { + regulator-name = "pm8150_1_l6"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa7 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L7A: pm8150_1_l7: regulator-pm8150_1-l7 { + regulator-name = "pm8150_1_l7"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa9 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L9A: pm8150_1_l9: regulator-pm8150_1-l9 { + regulator-name = "pm8150_1_l9"; + qcom,set = ; + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1304000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa11 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L11A: pm8150_1_l11: regulator-pm8150_1-l11 { + regulator-name = "pm8150_1_l11"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa12 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L12A: pm8150_1_l12: regulator-pm8150_1-l12 { + regulator-name = "pm8150_1_l12"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + + L12A_AO: pm8150_1_l12_ao: regulator-pm8150_1-l12-ao { + regulator-name = "pm8150_1_l12_ao"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + + regulator-pm8150_1-l12-so { + regulator-name = "pm8150_1_l12_so"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + qcom,init-enable = <0>; + }; + + }; + + rpmh-regulator-ldoa13 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L13A: pm8150_1_l13: regulator-pm8150_1-l13 { + regulator-name = "pm8150_1_l13"; + qcom,set = ; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + qcom,init-voltage = <2704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa15 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa15"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L15A: pm8150_1_l15: regulator-pm8150_1-l15 { + regulator-name = "pm8150_1_l15"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1704000>; + qcom,init-voltage = <1704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa16 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L16A: pm8150_1_l16: regulator-pm8150_1-l16 { + regulator-name = "pm8150_1_l16"; + qcom,set = ; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <2704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa18 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa18"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L18A: pm8150_1_l18: regulator-pm8150_1-l18 { + regulator-name = "pm8150_1_l18"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + }; + + /* PM8150_2 regulators */ + + /* PM8150_2 S3 + S2 + S1 = VDD_CX supply */ + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "cx.lvl"; + pm8150_2_s3_level-parent-supply = <&VDD_MX_LEVEL>; + pm8150_2_s3_level_ao-parent-supply = <&VDD_MX_LEVEL_AO>; + + VDD_CX_LEVEL: S3E_LEVEL: + pm8150_2_s3_level: regulator-pm8150_2-s3-level { + regulator-name = "pm8150_2_s3_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + + VDD_CX_LEVEL_AO: S3E_LEVEL_AO: + pm8150_2_s3_level_ao: regulator-pm8150_2-s3-level-ao { + regulator-name = "pm8150_2_s3_level_ao"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + cx_cdev: regulator-cdev { + compatible = "qcom,rpmh-reg-cdev"; + mboxes = <&qmp_aop 0>; + qcom,reg-resource-name = "cx"; + #cooling-cells = <2>; + }; + }; + + rpmh-regulator-smpe4 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpe4"; + S4E: pm8150_2_s4: regulator-pm8150_2-s4 { + regulator-name = "pm8150_2_s4"; + qcom,set = ; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <1128000>; + qcom,init-voltage = <752000>; + }; + }; + + rpmh-regulator-smpe5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpe5"; + S5E: pm8150_2_s5: regulator-pm8150_2-s5 { + regulator-name = "pm8150_2_s5"; + qcom,set = ; + regulator-min-microvolt = <1824000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1824000>; + }; + }; + + rpmh-regulator-ldoe1 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L1E: pm8150_2_l1: regulator-pm8150_2-l1 { + regulator-name = "pm8150_2_l1"; + qcom,set = ; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + qcom,init-voltage = <752000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe2 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L2E: pm8150_2_l2: regulator-pm8150_2-l2 { + regulator-name = "pm8150_2_l2"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + qcom,init-voltage = <1704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-lmxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "lmx.lvl"; + L4E_LEVEL: pm8150_2_l4_level: regulator-pm8150_2-l4-level { + regulator-name = "pm8150_2_l4_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ldoe5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L5E: pm8150_2_l5: regulator-pm8150_2-l5 { + regulator-name = "pm8150_2_l5"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + + L5E_AO: pm8150_2_l5_ao: regulator-pm8150_2-l5-ao { + regulator-name = "pm8150_2_l5_ao"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + + regulator-pm8150_2-l5-so { + regulator-name = "pm8150_2_l5_so"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + qcom,init-enable = <0>; + }; + + }; + + rpmh-regulator-ldoe7 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L7E: pm8150_2_l7: regulator-pm8150_2-l7 { + regulator-name = "pm8150_2_l7"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-lcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "lcx.lvl"; + L8E_LEVEL: pm8150_2_l8_level: regulator-pm8150_2-l8-level { + regulator-name = "pm8150_2_l8_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + rpmh-regulator-ldoe10 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L10E: pm8150_2_l10: regulator-pm8150_2-l10 { + regulator-name = "pm8150_2_l10"; + qcom,set = ; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <2504000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe13 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L13E: pm8150_2_l13: regulator-pm8150_2-l13 { + regulator-name = "pm8150_2_l13"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + qcom,init-voltage = <1704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe14 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe14"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L14E: pm8150_2_l14: regulator-pm8150_2-l14 { + regulator-name = "pm8150_2_l14"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe15 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe15"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L15E: pm8150_2_l15: regulator-pm8150_2-l15 { + regulator-name = "pm8150_2_l15"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe16 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L16E: pm8150_2_l16: regulator-pm8150_2-l16 { + regulator-name = "pm8150_2_l16"; + qcom,set = ; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + qcom,init-voltage = <3072000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe17 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L17E: pm8150_2_l17: regulator-pm8150_2-l17 { + regulator-name = "pm8150_2_l17"; + qcom,set = ; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <2960000>; + qcom,init-mode = ; + }; + }; + + /* PM8150C regulators */ + + /* PM8150C S1 = VDD_MMCX supply */ + rpmh-regulator-mmcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "mmcx.lvl"; + + VDD_MMCX_LEVEL: + S1C_LEVEL: pm8150c_s1_level: regulator-pm8150c-s1-level { + regulator-name = "pm8150c_s1_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + VDD_MMCX_LEVEL_AO: S1C_LEVEL_AO: + pm8150c_s1_level_ao: regulator-pm8150c-s1-level-ao { + regulator-name = "pm8150c_s1_level_ao"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + mm_cx_cdev: mm-cx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&VDD_MMCX_LEVEL_AO>; + regulator-levels = ; + #cooling-cells = <2>; + }; + }; + + /* PM8150C S2 = VDD_MODEM supply */ + rpmh-regulator-msslvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "mss.lvl"; + S2C_LEVEL: pm8150c_s2_level: regulator-pm8150c-s2-level { + regulator-name = "pm8150c_s2_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + /* PM8150C S3 + S4 = VDD_MX supply */ + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "mx.lvl"; + + VDD_MX_LEVEL: S3C_LEVEL: + pm8150c_s3_level: regulator-pm8150c-s3-level { + regulator-name = "pm8150c_s3_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + VDD_MX_LEVEL_AO: S3C_LEVEL_AO: + pm8150c_s3_level_ao: regulator-pm8150c-s3-level-ao { + regulator-name = "pm8150c_s3_level_ao"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + mx_cdev: mx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&VDD_MX_LEVEL>; + regulator-levels = ; + #cooling-cells = <2>; + }; + }; + + /* PM8150C S5 = VDDA_EBI supply */ + rpmh-regulator-ebilvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ebi.lvl"; + S5C_LEVEL: pm8150c_s5_level: regulator-pm8150c-s5-level { + regulator-name = "pm8150c_s5_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + ebi_cdev: regulator-cdev { + compatible = "qcom,rpmh-reg-cdev"; + mboxes = <&qmp_aop 0>; + qcom,reg-resource-name = "ebi"; + #cooling-cells = <2>; + }; + }; + + rpmh-regulator-smpc6 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpc6"; + S6C: pm8150c_s6: regulator-pm8150c-s6 { + regulator-name = "pm8150c-s6"; + qcom,set = ; + regulator-min-microvolt = <1260000>; + regulator-max-microvolt = <1396000>; + qcom,init-voltage = <1260000>; + }; + }; + + rpmh-regulator-smpc7 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpc7"; + S7C: pm8150c_s7: regulator-pm8150c-s7 { + regulator-name = "pm8150c-s7"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1128000>; + qcom,init-voltage = <800000>; + }; + }; + + rpmh-regulator-smpc8 { + compatible = "qcom,rpmh-xob-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpc8"; + S8C: pm8150c_s8: regulator-pm8150c-s8 { + regulator-name = "pm8150c_s8"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + rpmh-regulator-ldoc1 { + compatible = "qcom,rpmh-xob-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc1"; + L1C: pm8150c_l1: regulator-pm8150c-l1 { + regulator-name = "pm8150c_l1"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + rpmh-regulator-ldoc2 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L2C: pm8150c_l2: regulator-pm8150c-l2 { + regulator-name = "pm8150c_l2"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc3 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L3C: pm8150c_l3: regulator-pm8150c-l3 { + regulator-name = "pm8150c_l3"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc4 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L4C: pm8150c_l4: regulator-pm8150c-l4 { + regulator-name = "pm8150c_l4"; + qcom,set = ; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + qcom,init-voltage = <2856000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc6 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L6C: pm8150c_l6: regulator-pm8150c-l6 { + regulator-name = "pm8150c_l6"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc7 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L7C: pm8150c_l7: regulator-pm8150c-l7 { + regulator-name = "pm8150c_l7"; + qcom,set = ; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + qcom,init-voltage = <2856000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc8 { + compatible = "qcom,rpmh-xob-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc8"; + L8C: pm8150c_l8: regulator-pm8150c-l8 { + regulator-name = "pm8150c_l8"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + rpmh-regulator-ldoc9 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L9C: pm8150c_l9: regulator-pm8150c-l9 { + regulator-name = "pm8150c_l9"; + qcom,set = ; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <2504000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc10 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L10C: pm8150c_l10: regulator-pm8150c-l10 { + regulator-name = "pm8150c_l10"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc11 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L11C: pm8150c_l11: regulator-pm8150c-l11 { + regulator-name = "pm8150c_l11"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-bobc1 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "bobc1"; + qcom,regulator-type = "pmic5-bob"; + qcom,send-defaults; + + BOB: pm8150c_bob: regulator-pm8150c-bob { + regulator-name = "pm8150c_bob"; + qcom,set = ; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + qcom,init-voltage = <3296000>; + qcom,init-mode = ; + }; + BOB_AO: pm8150c_bob_ao: regulator-pm8150c-bob-ao { + regulator-name = "pm8150c_bob_ao"; + qcom,set = ; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + qcom,init-voltage = <3296000>; + qcom,init-mode = ; + }; + }; + + refgen: refgen-regulator@88e7000 { + compatible = "qcom,refgen-regulator"; + reg = <0x88e7000 0x60>; + regulator-name = "refgen"; + regulator-enable-ramp-delay = <5>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-rumi.dts b/arch/arm/boot/dts/qcom/sdmshrike-rumi.dts new file mode 100644 index 000000000000..7425fea214ab --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-rumi.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/memreserve/ 0x90000000 0x00000100; + +#include "sdmshrike.dtsi" +#include "sdmshrike-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDMSHRIKE RUMI"; + compatible = "qcom,sdmshrike-rumi", "qcom,sdmshrike", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-rumi.dtsi b/arch/arm/boot/dts/qcom/sdmshrike-rumi.dtsi new file mode 100644 index 000000000000..0549be8ff8cb --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-rumi.dtsi @@ -0,0 +1,73 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdmshrike-pmic-overlay.dtsi" + +&soc { + usb_emu_phy: usb_emu_phy@a720000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x0a720000 0x9500>, + <0x0a6f8800 0x100>; + reg-names = "base", "qcratch_base"; + + qcom,emu-init-seq = <0xfff0 0x4 + 0xfff3 0x4 + 0x40 0x4 + 0xfff3 0x4 + 0xfff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x1a0 0x20 + 0x100000 0x3c + 0x0 0x3c + 0x10060 0x3c + 0x0 0x4>; + }; +}; + +&usb0 { + dwc3@a600000 { + usb-phy = <&usb_emu_phy>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + }; +}; + +&usb2_phy0 { + status = "disabled"; +}; + +&sdhc_2 { + vdd-supply = <&pm8150_2_l17>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8150c_l6>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50"; + + /delete-property/qcom,devfreq,freq-table; + + cd-gpios = <&tlmm 96 0x1>; + + status = "ok"; +}; + +&qupv3_se10_2uart { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-sde-display.dtsi b/arch/arm/boot/dts/qcom/sdmshrike-sde-display.dtsi new file mode 100644 index 000000000000..4687aa1a5dc6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-sde-display.dtsi @@ -0,0 +1,615 @@ +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-sim-cmd.dtsi" +#include "dsi-panel-sim-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-video.dtsi" +#include "dsi-panel-sim-dualmipi-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" +#include "dsi-panel-sharp-dsc-4k-video.dtsi" +#include "dsi-panel-sharp-dsc-4k-cmd.dtsi" +#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi" +#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi" +#include "dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi" +#include "dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi" +#include "dsi-panel-nt35695b-truly-fhd-video.dtsi" +#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi" +#include "dsi-panel-sharp-1080p-cmd.dtsi" +#include "dsi-panel-sharp-dualmipi-1080p-120hz.dtsi" +#include "dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi" +#include "dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi" +#include + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_vdd_no_labibb: dsi_panel_pwr_supply_vdd_no_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <857000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + }; + + dsi_sharp_4k_dsc_video_display: qcom,dsi-display@0 { + label = "dsi_sharp_4k_dsc_video_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sharp_4k_dsc_video>; + }; + + dsi_sharp_4k_dsc_cmd_display: qcom,dsi-display@1 { + label = "dsi_sharp_4k_dsc_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sharp_4k_dsc_cmd>; + }; + + dsi_sharp_1080_cmd_display: qcom,dsi-display@2 { + label = "dsi_sharp_1080_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sharp_1080_cmd>; + }; + + dsi_dual_sharp_1080_120hz_cmd_display: qcom,dsi-display@3 { + label = "dsi_dual_sharp_1080_120hz_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_dual_sharp_1080_120hz_cmd>; + }; + + dsi_dual_nt35597_truly_video_display: qcom,dsi-display@4 { + label = "dsi_dual_nt35597_truly_video_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_dual_nt35597_truly_video>; + }; + + dsi_dual_nt35597_truly_cmd_display: qcom,dsi-display@5 { + label = "dsi_dual_nt35597_truly_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_dual_nt35597_truly_cmd>; + }; + + dsi_nt35597_truly_dsc_cmd_display: qcom,dsi-display@6 { + label = "dsi_nt35597_truly_dsc_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <1>; + qcom,dsi-phy-num = <1>; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,dsi-panel = <&dsi_nt35597_truly_dsc_cmd>; + }; + + dsi_nt35597_truly_dsc_video_display: qcom,dsi-display@7 { + label = "dsi_nt35597_truly_dsc_video_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <1>; + qcom,dsi-phy-num = <1>; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,dsi-panel = <&dsi_nt35597_truly_dsc_video>; + }; + + dsi_sim_vid_display: qcom,dsi-display@8 { + label = "dsi_sim_vid_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sim_vid>; + }; + + dsi_dual_sim_vid_display: qcom,dsi-display@9 { + label = "dsi_dual_sim_vid_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_dual_sim_vid>; + }; + + dsi_sim_cmd_display: qcom,dsi-display@10 { + label = "dsi_sim_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sim_cmd>; + }; + + dsi_dual_sim_cmd_display: qcom,dsi-display@11 { + label = "dsi_dual_sim_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_dual_sim_cmd>; + }; + + dsi_sim_dsc_375_cmd_display: qcom,dsi-display@12 { + label = "dsi_sim_dsc_375_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sim_dsc_375_cmd>; + }; + + dsi_dual_sim_dsc_375_cmd_display: qcom,dsi-display@13 { + label = "dsi_dual_sim_dsc_375_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_dual_sim_dsc_375_cmd>; + }; + + dsi_sw43404_amoled_cmd_display: qcom,dsi-display@14 { + label = "dsi_sw43404_amoled_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sw43404_amoled_cmd>; + }; + + dsi_nt35695b_truly_fhd_cmd_display: qcom,dsi-display@15 { + label = "dsi_nt35695b_truly_fhd_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_cmd>; + + }; + + dsi_nt35695b_truly_fhd_video_display: qcom,dsi-display@16 { + label = "dsi_nt35695b_truly_fhd_video_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_video>; + }; + + sde_dsi: qcom,dsi-display { + compatible = "qcom,dsi-display"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, + <&mdss_dsi0_pll PCLK_MUX_0_CLK>, + <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, + <&mdss_dsi1_pll PCLK_MUX_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 8 0>; + + vddio-supply = <&pm8150c_l1>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + + qcom,dsi-display-list = + <&dsi_sharp_4k_dsc_video_display + &dsi_sharp_4k_dsc_cmd_display + &dsi_sharp_1080_cmd_display + &dsi_dual_sharp_1080_120hz_cmd_display + &dsi_dual_nt35597_truly_video_display + &dsi_dual_nt35597_truly_cmd_display + &dsi_nt35597_truly_dsc_cmd_display + &dsi_nt35597_truly_dsc_video_display + &dsi_sim_vid_display + &dsi_dual_sim_vid_display + &dsi_sim_cmd_display + &dsi_dual_sim_cmd_display + &dsi_sim_dsc_375_cmd_display + &dsi_dual_sim_dsc_375_cmd_display + &dsi_sw43404_amoled_cmd_display + &dsi_nt35695b_truly_fhd_cmd_display + &dsi_nt35695b_truly_fhd_video_display>; + }; + + sde_wb: qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display"; + }; + + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; +}; + +&mdss_mdp { + connectors = <&sde_wb &sde_dsi>; +}; + +/* PHY TIMINGS REVISION P */ +&dsi_dual_nt35597_truly_video { + qcom,mdss-dsi-t-clk-post = <0x17>; + qcom,mdss-dsi-t-clk-pre = <0x18>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 03 04 00 18 17]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,mdss-dsi-t-clk-post = <0x17>; + qcom,mdss-dsi-t-clk-pre = <0x18>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 03 04 00 18 17]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt35597_truly_dsc_cmd { + qcom,mdss-dsi-t-clk-post = <0x15>; + qcom,mdss-dsi-t-clk-pre = <0x12>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05 + 05 03 03 04 00 12 15]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + }; +}; + +&dsi_nt35597_truly_dsc_video { + qcom,mdss-dsi-t-clk-post = <0x15>; + qcom,mdss-dsi-t-clk-pre = <0x12>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05 + 05 03 03 04 00 12 15]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + }; +}; + +&dsi_sharp_4k_dsc_video { + qcom,mdss-dsi-t-clk-post = <0x18>; + qcom,mdss-dsi-t-clk-pre = <0x19>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 03 04 00 19 18]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,mdss-dsi-t-clk-post = <0x18>; + qcom,mdss-dsi-t-clk-pre = <0x19>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 03 04 00 19 18]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt35695b_truly_fhd_video { + qcom,mdss-dsi-t-clk-post = <0x17>; + qcom,mdss-dsi-t-clk-pre = <0x19>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 + 08 08 05 03 04 00 19 17]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,mdss-dsi-t-clk-post = <0x17>; + qcom,mdss-dsi-t-clk-pre = <0x19>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 + 08 08 05 03 04 00 19 17]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sharp_1080_120hz_cmd { + qcom,mdss-dsi-t-clk-post = <0x0f>; + qcom,mdss-dsi-t-clk-pre = <0x36>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09 + 09 06 03 04 00]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_1080_cmd { + qcom,mdss-dsi-t-clk-post = <0x0c>; + qcom,mdss-dsi-t-clk-pre = <0x29>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07 + 07 04 03 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [01 03 01 00 01 01 01 + 01 00 03 04 00 03 04]; + qcom,display-topology = <1 0 1>, + <2 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_vid { + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 13 03 03 05 06 03 + 03 02 03 04 00 10 06]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 03 01 00 01 01 02 + 01 00 03 04 00 03 04]; + qcom,display-topology = <1 0 1>, + <2 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 13 03 03 05 06 03 + 03 02 03 04 00 10 06]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + timing@1{ + qcom,mdss-dsi-panel-phy-timings = [00 13 03 03 05 06 03 + 03 02 03 04 00 10 06]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + timing@2{ + qcom,mdss-dsi-panel-phy-timings = [00 13 03 03 05 06 03 + 03 02 03 04 00 10 06]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,mdss-dsi-display-timings { + timing@0 { /* 1080p */ + qcom,mdss-dsi-panel-phy-timings = [00 12 03 04 07 07 04 + 04 03 03 04 00 13 07]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + timing@1 { /* qhd */ + qcom,mdss-dsi-panel-phy-timings = [00 12 03 04 07 07 04 + 04 03 03 04 00 13 07]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,mdss-dsi-display-timings { + timing@0 { /* qhd */ + qcom,mdss-dsi-panel-phy-timings = [00 13 03 03 05 06 03 + 03 02 03 04 00 10 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + timing@1 { /* 4k */ + qcom,mdss-dsi-panel-phy-timings = [00 13 03 03 05 06 03 + 03 02 03 04 00 10 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sw43404_amoled_cmd { + qcom,mdss-dsi-t-clk-post = <0x16>; + qcom,mdss-dsi-t-clk-pre = <0x16>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 22 21 07 + 07 04 03 04 00 16 16]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-sde-pll.dtsi b/arch/arm/boot/dts/qcom/sdmshrike-sde-pll.dtsi new file mode 100644 index 000000000000..943f295bb301 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-sde-pll.dtsi @@ -0,0 +1,92 @@ +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + mdss_dsi0_pll: qcom,mdss_dsi_pll@ae94900 { + compatible = "qcom,mdss_dsi_pll_7nm"; + label = "MDSS DSI 0 PLL"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae94900 0x260>, + <0xae94400 0x800>, + <0xaf03000 0x8>; + reg-names = "pll_base", "phy_base", "gdsc_base"; + clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + clock-rate = <0>; + gdsc-supply = <&mdss_core_gdsc>; + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1_pll: qcom,mdss_dsi_pll@ae96900 { + compatible = "qcom,mdss_dsi_pll_7nm"; + label = "MDSS DSI 1 PLL"; + cell-index = <1>; + #clock-cells = <1>; + reg = <0xae96900 0x260>, + <0xae96400 0x800>, + <0xaf03000 0x8>; + reg-names = "pll_base", "phy_base", "gdsc_base"; + clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + clock-rate = <0>; + gdsc-supply = <&mdss_core_gdsc>; + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dp_pll: qcom,mdss_dp_pll@88ea000 { + compatible = "qcom,mdss_dp_pll_7nm"; + label = "MDSS DP PLL"; + cell-index = <0>; + #clock-cells = <1>; + + reg = <0x88ea000 0x200>, + <0x88eaa00 0x200>, + <0x88ea200 0x200>, + <0x88ea600 0x200>, + <0xaf03000 0x8>; + reg-names = "pll_base", "phy_base", "ln_tx0_base", + "ln_tx1_base", "gdsc_base"; + + clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_DISP_AHB_CLK>, + <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "iface_clk", "ref_clk_src", "gcc_iface", + "ref_clk", "pipe_clk"; + clock-rate = <0>; + }; + +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-sde.dtsi b/arch/arm/boot/dts/qcom/sdmshrike-sde.dtsi new file mode 100644 index 000000000000..c6717c6de5d5 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-sde.dtsi @@ -0,0 +1,717 @@ +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + compatible = "qcom,sde-kms"; + reg = <0xae00000 0x84208>, + <0xaeb0000 0x2008>, + <0xaeac000 0x214>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys"; + + clocks = + <&clock_gcc GCC_DISP_AHB_CLK>, + <&clock_gcc GCC_DISP_HF_AXI_CLK>, + <&clock_gcc GCC_DISP_SF_AXI_CLK>, + <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, + <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk", "rot_clk"; + clock-rate = <0 0 0 0 300000000 19200000 300000000 19200000>; + clock-max-rate = <0 0 0 0 460000000 19200000 460000000 + 460000000>; + + sde-vdd-supply = <&mdss_core_gdsc>; + + /* interrupt config */ + interrupts = <0 83 0>; + interrupt-controller; + #interrupt-cells = <1>; + iommus = <&apps_smmu 0x800 0x420>, + <&apps_smmu 0x820 0x420>; + + #address-cells = <1>; + #size-cells = <0>; + + #power-domain-cells = <0>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x45c>; + + qcom,sde-ctl-off = <0x2000 0x2200 0x2400 + 0x2600 0x2800 0x2a00>; + qcom,sde-ctl-size = <0x1e0>; + qcom,sde-ctl-display-pref = "primary", "primary", "none", + "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 + 0x48000 0x49000 0x4a000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none", "none", "none"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dest-scaler-top-off = <0x00061000>; + qcom,sde-dest-scaler-top-size = <0x1c>; + qcom,sde-dest-scaler-off = <0x800 0x1000>; + qcom,sde-dest-scaler-size = <0x800>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x3b8 24>; + + qcom,sde-intf-off = <0x6b000 0x6b800 + 0x6c000 0x6c800>; + qcom,sde-intf-size = <0x280>; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + + qcom,sde-pp-off = <0x71000 0x71800 + 0x72000 0x72800 0x73000 0x73800>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0>; + qcom,sde-pp-size = <0xd4>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2>; + + qcom,sde-merge-3d-off = <0x84000 0x84100 0x84200>; + qcom,sde-merge-3d-size = <0x100>; + + qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0 0x0 0x0>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + qcom,sde-dsc-off = <0x81000 0x81400 0x81800 0x81c00>; + qcom,sde-dsc-size = <0x140>; + + qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 + 0x30e0 0x30e0 0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "vig", "vig", "vig", + "dma", "dma", "dma", "dma"; + + qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 + 0x25000 0x27000 0x29000 0x2b000>; + qcom,sde-sspp-src-size = <0x1f0>; + + qcom,sde-sspp-xin-id = <0 4 8 12 + 1 5 9 13>; + qcom,sde-sspp-excl-rect = <1 1 1 1 + 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3 6 5>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>, + <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-type = "qseedv3"; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <4096>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-mixer-blendstages = <0xb>; + qcom,sde-highest-bank-bit = <0x2>; + qcom,sde-ubwc-version = <0x300>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-idle-pc; + qcom,sde-has-dest-scaler; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-max-bw-low-kbps = <9600000>; + qcom,sde-max-bw-high-kbps = <9600000>; + qcom,sde-min-core-ib-kbps = <2400000>; + qcom,sde-min-llcc-ib-kbps = <800000>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + qcom,sde-dspp-ad-version = <0x00040000>; + qcom,sde-dspp-ad-off = <0x28000 0x27000>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1040>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + + qcom,sde-danger-lut = <0x0000000f 0x0000ffff 0x00000000 + 0x00000000>; + qcom,sde-safe-lut-linear = + <4 0xfff8>, + <0 0xfff0>; + qcom,sde-safe-lut-macrotile = + <10 0xfe00>, + <11 0xfc00>, + <12 0xf800>, + <0 0xf000>; + qcom,sde-safe-lut-nrt = + <0 0xffff>; + qcom,sde-safe-lut-cwb = + <0 0xffff>; + qcom,sde-qos-lut-linear = + <4 0x00000000 0x00000357>, + <5 0x00000000 0x00003357>, + <6 0x00000000 0x00023357>, + <7 0x00000000 0x00223357>, + <8 0x00000000 0x02223357>, + <9 0x00000000 0x22223357>, + <10 0x00000002 0x22223357>, + <11 0x00000022 0x22223357>, + <12 0x00000222 0x22223357>, + <13 0x00002222 0x22223357>, + <14 0x00012222 0x22223357>, + <0 0x00112222 0x22223357>; + qcom,sde-qos-lut-macrotile = + <10 0x00000003 0x44556677>, + <11 0x00000033 0x44556677>, + <12 0x00000233 0x44556677>, + <13 0x00002233 0x44556677>, + <14 0x00012233 0x44556677>, + <0 0x00112233 0x44556677>; + qcom,sde-qos-lut-nrt = + <0 0x00000000 0x00000000>; + qcom,sde-qos-lut-cwb = + <0 0x75300000 0x00000000>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + + qcom,sde-reg-dma-off = <0>; + qcom,sde-reg-dma-version = <0x00010001>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + + qcom,sde-secure-sid-mask = <0x4200801>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + qcom,sde-vig-gamut = <0x1d00 0x00050000>; + qcom,sde-vig-igc = <0x1d00 0x00050000>; + qcom,sde-vig-inverse-pma; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + qcom,sde-dma-igc = <0x400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x200>; + }; + dgm@1 { + qcom,sde-dma-igc = <0x1400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1200>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040001>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + }; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "sde-vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x801 0x420>, + <&apps_smmu 0x821 0x420>; + }; + + /* data and reg bus scale settings */ + qcom,sde-data-bus { + qcom,msm-bus,name = "mdss_sde_mnoc"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <22 773 0 0>, <23 773 0 0>, + <22 773 0 6400000>, <23 773 0 6400000>, + <22 773 0 6400000>, <23 773 0 6400000>; + }; + + qcom,sde-llcc-bus { + qcom,msm-bus,name = "mdss_sde_llcc"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <132 770 0 0>, + <132 770 0 6400000>, + <132 770 0 6400000>; + }; + + qcom,sde-ebi-bus { + qcom,msm-bus,name = "mdss_sde_ebi"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <129 512 0 0>, + <129 512 0 6400000>, + <129 512 0 6400000>; + }; + + qcom,sde-reg-bus { + qcom,msm-bus,name = "mdss_reg"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,active-only; + qcom,msm-bus,vectors-KBps = + <1 590 0 0>, + <1 590 0 76800>, + <1 590 0 150000>, + <1 590 0 300000>; + }; + }; + + sde_rscc: qcom,sde_rscc@af20000 { + cell-index = <0>; + compatible = "qcom,sde-rsc"; + reg = <0xaf20000 0x1c44>, + <0xaf30000 0x3fd4>; + reg-names = "drv", "wrapper"; + qcom,sde-rsc-version = <2>; + status = "disabled"; + + vdd-supply = <&mdss_core_gdsc>; + clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, + <&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; + clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; + clock-rate = <0 0 0>; + + qcom,sde-dram-channels = <2>; + + mboxes = <&disp_rsc 0>; + mbox-names = "disp_rsc"; + + /* data and reg bus scale settings */ + qcom,sde-data-bus { + qcom,msm-bus,name = "disp_rsc_mnoc"; + qcom,msm-bus,active-only; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <20003 20515 0 0>, <20004 20515 0 0>, + <20003 20515 0 6400000>, <20004 20515 0 6400000>, + <20003 20515 0 6400000>, <20004 20515 0 6400000>; + }; + + qcom,sde-llcc-bus { + qcom,msm-bus,name = "disp_rsc_llcc"; + qcom,msm-bus,active-only; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <20001 20513 0 0>, + <20001 20513 0 6400000>, + <20001 20513 0 6400000>; + }; + + qcom,sde-ebi-bus { + qcom,msm-bus,name = "disp_rsc_ebi"; + qcom,msm-bus,active-only; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <20000 20512 0 0>, + <20000 20512 0 6400000>, + <20000 20512 0 6400000>; + }; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "mmcx"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_rotator: qcom,mdss_rotator@ae00000 { + compatible = "qcom,sde_rotator"; + reg = <0xae00000 0xac000>, + <0xaeb8000 0x3000>; + reg-names = "mdp_phys", + "rot_vbif_phys"; + + #list-cells = <1>; + + qcom,mdss-rot-mode = <1>; + qcom,mdss-highest-bank-bit = <0x2>; + + /* Bus Scale Settings */ + qcom,msm-bus,name = "mdss_rotator"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <25 512 0 0>, + <25 512 0 6400000>, + <25 512 0 6400000>; + + rot-vdd-supply = <&mdss_core_gdsc>; + qcom,supply-names = "rot-vdd"; + + clocks = + <&clock_gcc GCC_DISP_AHB_CLK>, + <&clock_gcc GCC_DISP_SF_AXI_CLK>, + <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", + "iface_clk", "rot_clk"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <2 0>; + + power-domains = <&mdss_mdp>; + + /* Offline rotator QoS setting */ + qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>; + qcom,mdss-rot-vbif-memtype = <3 3>; + qcom,mdss-rot-cdp-setting = <1 1>; + qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>; + qcom,mdss-rot-danger-lut = <0x0 0x0>; + qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>; + + /* Inline rotator QoS Setting */ + /* setting default register values for RD - qos/danger/safe */ + qcom,mdss-inline-rot-qos-lut = <0x44556677 0x00112233 + 0x44556677 0x00112233>; + qcom,mdss-inline-rot-danger-lut = <0x0055aaff 0x0000ffff>; + qcom,mdss-inline-rot-safe-lut = <0x0000f000 0x0000ff00>; + + qcom,mdss-default-ot-rd-limit = <32>; + qcom,mdss-default-ot-wr-limit = <32>; + + qcom,mdss-sbuf-headroom = <20>; + + cache-slice-names = "rotator"; + cache-slices = <&llcc 4>; + + /* reg bus scale settings */ + rot_reg: qcom,rot-reg-bus { + qcom,msm-bus,name = "mdss_rot_reg"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,active-only; + qcom,msm-bus,vectors-KBps = + <1 590 0 0>, + <1 590 0 76800>; + }; + + smmu_rot_unsec: qcom,smmu_rot_unsec_cb { + compatible = "qcom,smmu_sde_rot_unsec"; + iommus = <&apps_smmu 0x2040 0x0>; + }; + + smmu_rot_sec: qcom,smmu_rot_sec_cb { + compatible = "qcom,smmu_sde_rot_sec"; + iommus = <&apps_smmu 0x2041 0x0>; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.3"; + label = "dsi-ctrl-0"; + cell-index = <0>; + reg = <0xae94000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + vdda-1p2-supply = <&pm8150c_l3>; + clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", + "esc_clk"; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <4>; + }; + }; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.3"; + label = "dsi-ctrl-1"; + cell-index = <1>; + reg = <0xae96000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <5 0>; + vdda-1p2-supply = <&pm8150c_l3>; + clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <4>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 { + compatible = "qcom,dsi-phy-v4.0"; + label = "dsi-phy-0"; + cell-index = <0>; + reg = <0xae94400 0x7c0>; + reg-names = "dsi_phy"; + vdda-0p9-supply = <&pm8150_2_l5>; + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <36000>; + qcom,supply-disable-load = <32>; + }; + }; + }; + + mdss_dsi_phy1: qcom,mdss_dsi_phy0@ae96400 { + compatible = "qcom,dsi-phy-v4.0"; + label = "dsi-phy-1"; + cell-index = <1>; + reg = <0xae96400 0x7c0>; + reg-names = "dsi_phy"; + vdda-0p9-supply = <&pm8150_2_l5>; + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <36000>; + qcom,supply-disable-load = <32>; + }; + }; + }; + + sde_dp: qcom,dp_display@0{ + cell-index = <0>; + compatible = "qcom,dp-display"; + + reg = <0xae90000 0x0dc>, + <0xae90200 0x0c0>, + <0xae90400 0x508>, + <0xae90a00 0x094>, + <0x88eaa00 0x200>, + <0x88ea200 0x200>, + <0x88ea600 0x200>, + <0xaf02000 0x1a0>, + <0x780000 0x621c>, + <0x88ea040 0x10>, + <0x88e8000 0x20>, + <0xaee1000 0x034>, + <0xae91000 0x094>; + /* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */ + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_mmss_cc", "qfprom_physical", "dp_pll", + "usb3_dp_com", "hdcp_physical", "dp_p1"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, + <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + clock-names = "core_aux_clk", "core_usb_ref_clk_src", + "core_usb_ref_clk", "core_usb_pipe_clk", + "link_clk", "link_iface_clk", + "crypto_clk", "pixel_clk_rcg", "pixel_parent", + "pixel1_clk_rcg", "pixel1_parent", + "strm0_pixel_clk", "strm1_pixel_clk"; + + qcom,phy-version = <0x420>; + qcom,aux-cfg0-settings = [20 00]; + qcom,aux-cfg1-settings = [24 13]; + qcom,aux-cfg2-settings = [28 24]; + qcom,aux-cfg3-settings = [2c 00]; + qcom,aux-cfg4-settings = [30 0a]; + qcom,aux-cfg5-settings = [34 26]; + qcom,aux-cfg6-settings = [38 0a]; + qcom,aux-cfg7-settings = [3c 03]; + qcom,aux-cfg8-settings = [40 b7]; + qcom,aux-cfg9-settings = [44 03]; + + qcom,max-pclk-frequency-khz = <675000>; + + qcom,mst-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; + qcom,max-dp-dsc-blks = <2>; + qcom,max-dp-dsc-input-width-pixs = <2048>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <36000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-smp2p.dtsi b/arch/arm/boot/dts/qcom/sdmshrike-smp2p.dtsi new file mode 100644 index 000000000000..5e42f0056eec --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-smp2p.dtsi @@ -0,0 +1,96 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + qcom,ipc = <&apcs 0 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = ; + qcom,ipc = <&apcs 0 10>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-dsps { + compatible = "qcom,smp2p"; + qcom,smem = <481>, <430>; + interrupts = ; + qcom,ipc = <&apcs 0 26>; + qcom,local-pid = <0>; + qcom,remote-pid = <3>; + + dsps_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + dsps_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts = ; + qcom,ipc = <&apcs 0 6>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-thermal-overlay.dtsi b/arch/arm/boot/dts/qcom/sdmshrike-thermal-overlay.dtsi new file mode 100644 index 000000000000..74b28c7262eb --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-thermal-overlay.dtsi @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include + +&thermal_zones { + pm8150_tz { + cooling-maps { + trip0_cpu0 { + trip = <&pm8150_trip0>; + cooling-device = + <&CPU0 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu1 { + trip = <&pm8150_trip0>; + cooling-device = + <&CPU1 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu2 { + trip = <&pm8150_trip0>; + cooling-device = + <&CPU2 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu3 { + trip = <&pm8150_trip0>; + cooling-device = + <&CPU3 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu4 { + trip = <&pm8150_trip0>; + cooling-device = + <&CPU4 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu5 { + trip = <&pm8150_trip0>; + cooling-device = + <&CPU5 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu6 { + trip = <&pm8150_trip0>; + cooling-device = + <&CPU6 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu7 { + trip = <&pm8150_trip0>; + cooling-device = + <&CPU7 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip1_cpu1 { + trip = <&pm8150_trip1>; + cooling-device = + <&CPU1 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu2 { + trip = <&pm8150_trip1>; + cooling-device = + <&CPU2 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu3 { + trip = <&pm8150_trip1>; + cooling-device = + <&CPU3 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu4 { + trip = <&pm8150_trip1>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu5 { + trip = <&pm8150_trip1>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu6 { + trip = <&pm8150_trip1>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu7 { + trip = <&pm8150_trip1>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm8150l-vph-lvl0 { + cooling-maps { + vph_cpu4 { + trip = <&vph_lvl0>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + vph_cpu5 { + trip = <&vph_lvl0>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + vph_gpu0 { + trip = <&vph_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm8150l-vph-lvl1 { + cooling-maps { + vph_cpu6 { + trip = <&vph_lvl1>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + vph_cpu7 { + trip = <&vph_lvl1>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + vph_gpu1 { + trip = <&vph_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + }; + }; + + pm8150l-vph-lvl2 { + cooling-maps { + vph_gpu2 { + trip = <&vph_lvl2>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; +}; + +&mdss_mdp { + #cooling-cells = <2>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-thermal.dtsi b/arch/arm/boot/dts/qcom/sdmshrike-thermal.dtsi new file mode 100644 index 000000000000..79a2b169d659 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-thermal.dtsi @@ -0,0 +1,1367 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&clock_cpucc { + #address-cells = <1>; + #size-cells = <1>; + lmh_dcvs0: qcom,limits-dcvs@18358800 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + qcom,affinity = <0>; + reg = <0x18358800 0x1000>, + <0x18323000 0x1000>; + #thermal-sensor-cells = <0>; + }; + + lmh_dcvs1: qcom,limits-dcvs@18350800 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + qcom,affinity = <1>; + reg = <0x18350800 0x1000>, + <0x18325800 0x1000>; + #thermal-sensor-cells = <0>; + isens_vref_0p8-supply = <&pm8150_2_l5_ao>; + isens-vref-0p8-settings = <880000 880000 20000>; + isens_vref_1p8-supply = <&pm8150_1_l12_ao>; + isens-vref-1p8-settings = <1800000 1800000 20000>; + }; +}; + +&soc { + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + adsp { + qcom,instance-id = <0x1>; + + adsp_vdd: adsp_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + + cdsp { + qcom,instance-id = <0x43>; + + cdsp_vdd: cdsp_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + + slpi { + qcom,instance-id = <0x53>; + + slpi_vdd: slpi_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + }; +}; + +&thermal_zones { + aoss0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 0>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 1>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 3>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-0-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-4-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-5-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-6-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-7-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 15>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 0>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cwlan-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 1>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + video-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 2>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + ddr-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + q6-hvx-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 5>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cmpss-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 6>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-core-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 7>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + npu-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-vec-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 9>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-scl-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 10>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 11>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 12>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 13>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + ddrss-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 14>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + pcie-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 15>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + lmh-dcvs-01 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&lmh_dcvs1>; + wake-capable-sensor; + + trips { + active-config { + temperature = <85000>; + hysteresis = <25000>; + type = "passive"; + }; + }; + }; + + lmh-dcvs-00 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&lmh_dcvs0>; + wake-capable-sensor; + + trips { + active-config { + temperature = <85000>; + hysteresis = <25000>; + type = "passive"; + }; + }; + }; + + quad-gpuss-max-step { + polling-delay-passive = <10>; + polling-delay = <100>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + gpu_trip0: gpu-trip0 { + temperature = <85000>; + hysteresis = <0>; + type = "passive"; + }; + }; + cooling-maps { + gpu_cdev { + trip = <&gpu_trip0>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + apc-0-max-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + silver-trip { + temperature = <120000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + apc-1-max-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + gold-trip { + temperature = <120000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + + cpu-0-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 1>; + wake-capable-sensor; + trips { + cpu00_config: cpu00-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu00_cdev { + trip = <&cpu00_config>; + cooling-device = + <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-0-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 2>; + wake-capable-sensor; + trips { + cpu01_config: cpu01-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu01_cdev { + trip = <&cpu01_config>; + cooling-device = + <&CPU1 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-0-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 3>; + wake-capable-sensor; + trips { + cpu02_config: cpu02-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu02_cdev { + trip = <&cpu02_config>; + cooling-device = + <&CPU2 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-0-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu03_config: cpu03-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu03_cdev { + trip = <&cpu03_config>; + cooling-device = + <&CPU3 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu10_config: cpu10-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu10_cdev { + trip = <&cpu10_config>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu11_config: cpu11-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu11_cdev { + trip = <&cpu11_config>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu12_config: cpu12-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu12_cdev { + trip = <&cpu12_config>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu13_config: cpu13-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu13_cdev { + trip = <&cpu13_config>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-4-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu14_config: cpu14-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu14_cdev { + trip = <&cpu14_config>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-5-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu15_config: cpu15-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu15_cdev { + trip = <&cpu15_config>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-6-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu16_config: cpu16-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu16_cdev { + trip = <&cpu16_config>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-7-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu17_config: cpu17-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu17_cdev { + trip = <&cpu17_config>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-7-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + thermal-governor = "low_limits_floor"; + wake-capable-sensor; + tracks-low; + trips { + cpu17_trip: cpu17-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&cpu17_trip>; + cooling-device = <&CPU0 1 1>; + }; + cpu1_cdev { + trip = <&cpu17_trip>; + cooling-device = <&CPU4 5 5>; + }; + cx_vdd_cdev { + trip = <&cpu17_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&cpu17_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + ebi_vdd_cdev { + trip = <&cpu17_trip>; + cooling-device = <&ebi_cdev 0 0>; + }; + mmcx_vdd_cdev { + trip = <&cpu17_trip>; + cooling-device = <&mm_cx_cdev 0 0>; + }; + adsp_vdd_cdev { + trip = <&cpu17_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&cpu17_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + slpi_vdd_cdev { + trip = <&cpu17_trip>; + cooling-device = <&slpi_vdd 0 0>; + }; + gpu_vdd_cdev { + trip = <&cpu17_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + }; + }; + + gpuss-0-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 15>; + thermal-governor = "low_limits_floor"; + wake-capable-sensor; + tracks-low; + trips { + gpuss0_trip: gpuss0-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&gpuss0_trip>; + cooling-device = <&CPU0 1 1>; + }; + cpu1_cdev { + trip = <&gpuss0_trip>; + cooling-device = <&CPU4 5 5>; + }; + cx_vdd_cdev { + trip = <&gpuss0_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&gpuss0_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + ebi_vdd_cdev { + trip = <&gpuss0_trip>; + cooling-device = <&ebi_cdev 0 0>; + }; + mmcx_vdd_cdev { + trip = <&gpuss0_trip>; + cooling-device = <&mm_cx_cdev 0 0>; + }; + adsp_vdd_cdev { + trip = <&gpuss0_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&gpuss0_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + slpi_vdd_cdev { + trip = <&gpuss0_trip>; + cooling-device = <&slpi_vdd 0 0>; + }; + gpu_vdd_cdev { + trip = <&gpuss0_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + }; + }; + + camera-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 5>; + thermal-governor = "low_limits_floor"; + wake-capable-sensor; + tracks-low; + trips { + camera_trip: camera-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&camera_trip>; + cooling-device = <&CPU0 1 1>; + }; + cpu1_cdev { + trip = <&camera_trip>; + cooling-device = <&CPU4 5 5>; + }; + cx_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + ebi_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&ebi_cdev 0 0>; + }; + mmcx_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&mm_cx_cdev 0 0>; + }; + adsp_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + slpi_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&slpi_vdd 0 0>; + }; + gpu_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + }; + }; + + mdm-scl-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 10>; + thermal-governor = "low_limits_floor"; + wake-capable-sensor; + tracks-low; + trips { + mdms_trip: mdms-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&mdms_trip>; + cooling-device = <&CPU0 1 1>; + }; + cpu1_cdev { + trip = <&mdms_trip>; + cooling-device = <&CPU4 5 5>; + }; + cx_vdd_cdev { + trip = <&mdms_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&mdms_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + ebi_vdd_cdev { + trip = <&mdms_trip>; + cooling-device = <&ebi_cdev 0 0>; + }; + mmcx_vdd_cdev { + trip = <&mdms_trip>; + cooling-device = <&mm_cx_cdev 0 0>; + }; + adsp_vdd_cdev { + trip = <&mdms_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&mdms_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + slpi_vdd_cdev { + trip = <&mdms_trip>; + cooling-device = <&slpi_vdd 0 0>; + }; + gpu_vdd_cdev { + trip = <&mdms_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + }; + }; + + pcie-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 15>; + thermal-governor = "low_limits_floor"; + wake-capable-sensor; + tracks-low; + trips { + pcie_trip: pcie-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&pcie_trip>; + cooling-device = <&CPU0 1 1>; + }; + cpu1_cdev { + trip = <&pcie_trip>; + cooling-device = <&CPU4 5 5>; + }; + cx_vdd_cdev { + trip = <&pcie_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&pcie_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + ebi_vdd_cdev { + trip = <&pcie_trip>; + cooling-device = <&ebi_cdev 0 0>; + }; + mmcx_vdd_cdev { + trip = <&pcie_trip>; + cooling-device = <&mm_cx_cdev 0 0>; + }; + adsp_vdd_cdev { + trip = <&pcie_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&pcie_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + slpi_vdd_cdev { + trip = <&pcie_trip>; + cooling-device = <&slpi_vdd 0 0>; + }; + gpu_vdd_cdev { + trip = <&pcie_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8195-vm-usb.dtsi b/arch/arm/boot/dts/qcom/sdmshrike-usb.dtsi similarity index 68% rename from arch/arm64/boot/dts/qcom/sa8195-vm-usb.dtsi rename to arch/arm/boot/dts/qcom/sdmshrike-usb.dtsi index 1035d25de40b..9362ddd57f99 100644 --- a/arch/arm64/boot/dts/qcom/sa8195-vm-usb.dtsi +++ b/arch/arm/boot/dts/qcom/sdmshrike-usb.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -10,7 +10,6 @@ * GNU General Public License for more details. */ -#include #include #include @@ -33,16 +32,16 @@ qcom,use-pdc-interrupts; USB3_GDSC-supply = <&usb30_prim_gdsc>; - clocks = <&clock_virt GCC_USB30_PRIM_MASTER_CLK>, - <&clock_virt GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&clock_virt GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&clock_virt GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&clock_virt GCC_USB30_PRIM_SLEEP_CLK>, - <&clock_virt GCC_USB3_PRIM_CLKREF_CLK>; + clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>, + <&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&clock_rpmh RPMH_CXO_CLK>; clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk", "sleep_clk", "xo"; - resets = <&clock_virt GCC_USB30_PRIM_BCR>; + resets = <&clock_gcc GCC_USB30_PRIM_BCR>; reset-names = "core_reset"; qcom,core-clk-rate = <200000000>; @@ -57,7 +56,17 @@ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <27696>; - status = "disabled"; + qcom,msm-bus,name = "usb0"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <3>; + qcom,msm-bus,vectors-KBps = + , + , + , + , + , + ; dwc3@a600000 { compatible = "snps,dwc3"; @@ -68,15 +77,14 @@ snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; - snps,ssp-u3-u0-quirk; - snps,usb3-u1u2-disable; + snps,usb3_lpm_capable; usb-core-id = <0>; tx-fifo-resize; maximum-speed = "high-speed"; dr_mode = "otg"; }; - usbbam: qcom,usbbam@a704000 { + qcom,usbbam@a704000 { compatible = "qcom,usb-bam-msm"; reg = <0xa704000 0x17000>; interrupts = <0 132 0>; @@ -89,8 +97,6 @@ qcom,usb-bam-max-mbps-superspeed = <3600>; qcom,reset-bam-on-connect; - status = "disabled"; - qcom,pipe0 { label = "ssusb-qdss-in-0"; qcom,usb-bam-mem-type = <2>; @@ -114,19 +120,17 @@ reg = <0x88e2000 0x110>; reg-names = "hsusb_phy_base"; - vdd-supply = <&pm8195_3_l5>; - vdda18-supply = <&pm8195_1_l12>; - vdda33-supply = <&pm8195_3_l16>; + vdd-supply = <&pm8150_2_l5>; + vdda18-supply = <&pm8150_1_l12>; + vdda33-supply = <&pm8150_2_l16>; qcom,vdd-voltage-level = <0 880000 880000>; - clocks = <&clock_gcc RPMH_CXO_CLK>; + clocks = <&clock_rpmh RPMH_CXO_CLK>; clock-names = "ref_clk_src"; - resets = <&clock_virt GCC_QUSB2PHY_PRIM_BCR>; + resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>; reset-names = "phy_reset"; qcom,param-override-seq = <0x43 0x70>; - - status = "disabled"; }; usb_nop_phy: usb_nop_phy { @@ -151,16 +155,16 @@ qcom,use-pdc-interrupts; USB3_GDSC-supply = <&usb30_sec_gdsc>; - clocks = <&clock_virt GCC_USB30_SEC_MASTER_CLK>, - <&clock_virt GCC_CFG_NOC_USB3_SEC_AXI_CLK>, - <&clock_virt GCC_AGGRE_USB3_SEC_AXI_CLK>, - <&clock_virt GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&clock_virt GCC_USB30_SEC_SLEEP_CLK>, - <&clock_virt GCC_USB3_SEC_CLKREF_CLK>; + clocks = <&clock_gcc GCC_USB30_SEC_MASTER_CLK>, + <&clock_gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&clock_gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&clock_gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&clock_gcc GCC_USB30_SEC_SLEEP_CLK>, + <&clock_rpmh RPMH_CXO_CLK>; clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk", "sleep_clk", "xo"; - resets = <&clock_virt GCC_USB30_SEC_BCR>; + resets = <&clock_gcc GCC_USB30_SEC_BCR>; reset-names = "core_reset"; qcom,core-clk-rate = <200000000>; @@ -176,6 +180,27 @@ qcom,dwc-usb3-msm-tx-fifo-size = <27696>; qcom,charging-disabled; + qcom,msm-bus,name = "usb1"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <3>; + qcom,msm-bus,vectors-KBps = + /* suspend vote */ + , + , + , + + /* nominal vote */ + , + , + , + + /* svs vote */ + , + , + ; + status = "disabled"; dwc3@a800000 { @@ -201,15 +226,15 @@ reg = <0x88e3000 0x110>; reg-names = "hsusb_phy_base"; - vdd-supply = <&pm8195_3_l5>; - vdda18-supply = <&pm8195_1_l12>; - vdda33-supply = <&pm8195_3_l16>; + vdd-supply = <&pm8150_2_l5>; + vdda18-supply = <&pm8150_1_l12>; + vdda33-supply = <&pm8150_2_l16>; qcom,vdd-voltage-level = <0 880000 880000>; - clocks = <&clock_gcc RPMH_CXO_CLK>; + clocks = <&clock_rpmh RPMH_CXO_CLK>; clock-names = "ref_clk_src"; - resets = <&clock_virt GCC_QUSB2PHY_SEC_BCR>; + resets = <&clock_gcc GCC_QUSB2PHY_SEC_BCR>; reset-names = "phy_reset"; status = "disabled"; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-v2-mtp.dts b/arch/arm/boot/dts/qcom/sdmshrike-v2-mtp.dts new file mode 100644 index 000000000000..55d1e7f015f9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-v2-mtp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdmshrike-v2.dtsi" +#include "sdmshrike-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDMSHRIKE V2 MTP"; + compatible = "qcom,sdmshrike-mtp", "qcom,sdmshrike", "qcom,mtp"; + qcom,board-id = <8 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-v2.dts b/arch/arm/boot/dts/qcom/sdmshrike-v2.dts new file mode 100644 index 000000000000..4d269441a095 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-v2.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdmshrike-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDMSHRIKE v2 SoC"; + compatible = "qcom,sdmshrike"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike-v2.dtsi b/arch/arm/boot/dts/qcom/sdmshrike-v2.dtsi new file mode 100644 index 000000000000..13c41d54eb87 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike-v2.dtsi @@ -0,0 +1,262 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdmshrike.dtsi" +/ { + model = "Qualcomm Technologies, Inc. SDMSHRIKE V2"; + qcom,msm-name = "SDMSHRIKE V2"; + qcom,msm-id = <340 0x20000>; +}; + +&soc { + gpu_opp_table_v2: gpu_opp_table_v2 { + compatible = "operating-points-v2"; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = ; + }; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; + opp-microvolt = ; + }; + opp-585000000 { + opp-hz = /bits/ 64 <585000000>; + opp-microvolt = ; + }; + + opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + opp-microvolt = ; + }; + + opp-427000000 { + opp-hz = /bits/ 64 <427000000>; + opp-microvolt = ; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + opp-microvolt = ; + }; + + opp-257000000 { + opp-hz = /bits/ 64 <257000000>; + opp-microvolt = ; + }; + }; +}; +/* GPU overrides */ +&msm_gpu { + /* Updated chip ID */ + qcom,chipid = <0x6080001>; + + /* Power level to start throttling */ + qcom,throttle-pwrlevel = <3>; + + /* Updated Bus Scale Settings */ + qcom,msm-bus,num-cases = <12>; + + /* + * Value for vote is: (DDR freq) * 4 - 5 + * The 5 value is to ensure that there is no rounding errors + * where the total request doesn't divide evenly by the BCM + * DDR bandwidth unit (note, 5 is greater than this unit). + */ + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, // 0 bus=0 + <26 512 0 795000>, // 1 bus=200 + <26 512 0 1195000>, // 2 bus=300 + <26 512 0 1799000>, // 3 bus=451 + <26 512 0 2183000>, // 4 bus=547 + <26 512 0 2719000>, // 5 bus=681 + <26 512 0 3067000>, // 6 bus=768 + <26 512 0 4063000>, // 7 bus=1017 + <26 512 0 5407000>, // 8 bus=1353 + <26 512 0 6215000>, // 9 bus=1555 + <26 512 0 7211000>, // 10 bus=1804 + <26 512 0 8363000>; // 11 bus=2092 + + qcom,initial-pwrlevel = <4>; + + operating-points-v2 = <&gpu_opp_table_v2>; + + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <700000000>; + qcom,bus-freq = <10>; + qcom,bus-min = <8>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <675000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <585000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <427000000>; + qcom,bus-freq = <6>; + qcom,bus-min = <5>; + qcom,bus-max = <9>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <345000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <3>; + qcom,bus-max = <8>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <257000000>; + qcom,bus-freq = <2>; + qcom,bus-min = <1>; + qcom,bus-max = <8>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + + }; + + qcom,l3-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,l3-pwrlevels"; + + qcom,l3-pwrlevel@0 { + reg = <0>; + qcom,l3-freq = <0>; + }; + + qcom,l3-pwrlevel@1 { + reg = <1>; + qcom,l3-freq = <1344000000>; + }; + + qcom,l3-pwrlevel@2 { + reg = <2>; + qcom,l3-freq = <1612800000>; + }; + }; +}; + +&gmu { + reg = <0x2c6a000 0x30000>, + <0xb290000 0x10000>, + <0xb490000 0x10000>; + reg-names = "kgsl_gmu_reg", + "kgsl_gmu_pdc_cfg", + "kgsl_gmu_pdc_seq"; + + qcom,gpu-acd-table { + /* Corresponds to levels in the GPU perf table */ + qcom,acd-enable-by-level = <0x7e>; + qcom,acd-stride = <0x2>; + qcom,acd-num-levels = <0x6>; + + /* ACDCR, ACDTD */ + qcom,acd-data = <0xa02d5ffd 0x00007611 /* LowSVS */ + 0xa02d5ffd 0x00006911 /* SVS */ + 0xa02d5ffd 0x00006111 /* SVS_L1 */ + 0xa02d5ffd 0x00006011 /* SVS_L2 */ + 0x802d5ffd 0x00005411 /* NOM */ + 0x802d5ffd 0x00005411>; /* NOM_L1 */ + }; +}; +&mdss_mdp { + qcom,fullsize-va-map; + qcom,sde-min-core-ib-kbps = <0>; + qcom,sde-min-llcc-ib-kbps = <0>; +}; + +&clock_npucc { + compatible = "qcom,npucc-sm8150-v2", "syscon"; +}; + +&clock_dispcc { + compatible = "qcom,dispcc-sdmshrike-v2", "syscon"; +}; + +&mdss_dsi0_pll { + compatible = "qcom,mdss_dsi_pll_7nm_v2"; +}; + +&mdss_dsi1_pll { + compatible = "qcom,mdss_dsi_pll_7nm_v2"; +}; + +&msm_fastrpc { + qcom,msm_fastrpc_compute_cb1 { + iommus = <&apps_smmu 0x1001 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb2 { + iommus = <&apps_smmu 0x1002 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb3 { + iommus = <&apps_smmu 0x1003 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb4 { + iommus = <&apps_smmu 0x1004 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb5 { + iommus = <&apps_smmu 0x1005 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb6 { + iommus = <&apps_smmu 0x1006 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb7 { + iommus = <&apps_smmu 0x1007 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb8 { + iommus = <&apps_smmu 0x1008 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb9 { + iommus = <&apps_smmu 0x1009 0x0460>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike.dts b/arch/arm/boot/dts/qcom/sdmshrike.dts new file mode 100644 index 000000000000..2fe29fa84aa5 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdmshrike.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDMSHRIKE SoC"; + compatible = "qcom,sdmshrike"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdmshrike.dtsi b/arch/arm/boot/dts/qcom/sdmshrike.dtsi new file mode 100644 index 000000000000..50372a88962a --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdmshrike.dtsi @@ -0,0 +1,2513 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "skeleton64.dtsi" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} + +/ { + model = "Qualcomm Technologies, Inc. SDMSHRIKE"; + compatible = "qcom,sdmshrike"; + qcom,msm-name = "SDMSHRIKE"; + qcom,msm-id = <340 0x10000>; + interrupt-parent = <&pdc>; + + aliases { + ufshc1 = &ufshc_mem; /* Embedded UFS slot */ + sdhc2 = &sdhc_2; /* SDC2 SD Card slot */ + serial0 = &qupv3_se12_2uart; + hsuart0 = &qupv3_se13_4uart; + spi0 = &qupv3_se3_spi; + i2c0 = &qupv3_se4_i2c; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cache-size = <0x8000>; + next-level-cache = <&L2_0>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-size = <0x400000>; + cache-level = <3>; + }; + }; + + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cache-size = <0x8000>; + next-level-cache = <&L2_1>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cache-size = <0x8000>; + next-level-cache = <&L2_2>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_2: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_200: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + + L1_D_200: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cache-size = <0x8000>; + next-level-cache = <&L2_3>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_3: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_300: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + + L1_D_300: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + cache-size = <0x20000>; + next-level-cache = <&L2_4>; + sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + #cooling-cells = <2>; + L2_4: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x80000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_400: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + + L1_D_400: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + cache-size = <0x20000>; + next-level-cache = <&L2_5>; + sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + #cooling-cells = <2>; + L2_5: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x80000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_500: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + + L1_D_500: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + cache-size = <0x20000>; + next-level-cache = <&L2_6>; + sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + #cooling-cells = <2>; + L2_6: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x80000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_600: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + + L1_D_600: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + cache-size = <0x20000>; + next-level-cache = <&L2_7>; + sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + #cooling-cells = <2>; + L2_7: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x80000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_700: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + + L1_D_700: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + energy_costs: energy-costs { + compatible = "sched-energy"; + + CPU_COST_0: core-cost0 { + busy-cost-data = < + 300000 24 + 403200 25 + 499200 27 + 576000 29 + 672000 33 + 768000 37 + 844800 42 + 940800 47 + 1036800 54 + 1113600 59 + 1209600 66 + 1305600 73 + 1382400 79 + 1478400 88 + 1555200 96 + 1632000 105 + 1708800 115 + 1785600 128 + >; + idle-cost-data = < + 18 14 12 + >; + }; + + CPU_COST_1: core-cost1 { + busy-cost-data = < + 825600 227 + 940800 262 + 1056000 302 + 1171200 348 + 1286400 398 + 1401600 451 + 1497600 498 + 1612800 556 + 1708800 606 + 1804800 655 + 1920000 716 + 2016000 766 + 2131200 826 + 2227200 878 + 2323200 933 + 2419200 992 + 2534400 1075 + 2649600 1179 + 2745600 1288 + 2841600 1427 + 2956800 1670 + >; + idle-cost-data = < + 110 90 70 + >; + }; + + CLUSTER_COST_0: cluster-cost0 { + busy-cost-data = < + 300000 3 + 403200 4 + 499200 4 + 576000 4 + 672000 5 + 768000 5 + 844800 6 + 940800 7 + 1036800 8 + 1113600 9 + 1209600 10 + 1305600 11 + 1382400 12 + 1478400 13 + 1555200 14 + 1632000 15 + 1708800 16 + 1785600 17 + >; + idle-cost-data = < + 3 2 1 + >; + }; + + CLUSTER_COST_1: cluster-cost1 { + busy-cost-data = < + 825600 30 + 940800 33 + 1056000 36 + 1171200 39 + 1286400 42 + 1401600 46 + 1497600 49 + 1612800 55 + 1708800 67 + 1804800 77 + 1920000 87 + 2016000 100 + 2131200 110 + 2227200 120 + 2323200 128 + 2419200 135 + 2534400 140 + 2649600 147 + 2745600 160 + 2841600 180 + 2956800 197 + >; + idle-cost-data = < + 3 2 1 + >; + }; + }; /* energy-costs */ + + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 cgroup.memory=nokmem,nosocket"; + }; + + cpuss_dump { + compatible = "qcom,cpuss-dump"; + + qcom,l1_i_cache0 { + qcom,dump-node = <&L1_I_0>; + qcom,dump-id = <0x60>; + }; + + qcom,l1_i_cache1 { + qcom,dump-node = <&L1_I_100>; + qcom,dump-id = <0x61>; + }; + + qcom,l1_i_cache2 { + qcom,dump-node = <&L1_I_200>; + qcom,dump-id = <0x62>; + }; + + qcom,l1_i_cache3 { + qcom,dump-node = <&L1_I_300>; + qcom,dump-id = <0x63>; + }; + + qcom,l1_i_cache100 { + qcom,dump-node = <&L1_I_400>; + qcom,dump-id = <0x64>; + }; + + qcom,l1_i_cache101 { + qcom,dump-node = <&L1_I_500>; + qcom,dump-id = <0x65>; + }; + + qcom,l1_i_cache102 { + qcom,dump-node = <&L1_I_600>; + qcom,dump-id = <0x66>; + }; + + qcom,l1_i_cache103 { + qcom,dump-node = <&L1_I_700>; + qcom,dump-id = <0x67>; + }; + + qcom,l1_d_cache0 { + qcom,dump-node = <&L1_D_0>; + qcom,dump-id = <0x80>; + }; + + qcom,l1_d_cache1 { + qcom,dump-node = <&L1_D_100>; + qcom,dump-id = <0x81>; + }; + + qcom,l1_d_cache2 { + qcom,dump-node = <&L1_D_200>; + qcom,dump-id = <0x82>; + }; + + qcom,l1_d_cache3 { + qcom,dump-node = <&L1_D_300>; + qcom,dump-id = <0x83>; + }; + + qcom,l1_d_cache100 { + qcom,dump-node = <&L1_D_400>; + qcom,dump-id = <0x84>; + }; + + qcom,l1_d_cache101 { + qcom,dump-node = <&L1_D_500>; + qcom,dump-id = <0x85>; + }; + + qcom,l1_d_cache102 { + qcom,dump-node = <&L1_D_600>; + qcom,dump-id = <0x86>; + }; + + qcom,l1_d_cache103 { + qcom,dump-node = <&L1_D_700>; + qcom,dump-id = <0x87>; + }; + }; + + firmware: firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; + }; + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/8804000.sdhci/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp_mem@85700000 { + no-map; + reg = <0x0 0x85700000 0x0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_mem@85e00000 { + no-map; + reg = <0x0 0x85e00000 0x0 0x140000>; + }; + + flex_sec_apps_mem: flex_sec_apps_regions@85ffd000 { + no-map; + reg = <0x0 0x85ffd000 0x0 0x3000>; + }; + + smem_region: smem@86000000 { + no-map; + reg = <0x0 0x86000000 0x0 0x200000>; + }; + + removed_regions: removed_regions@86200000 { + no-map; + reg = <0x0 0x86200000 0x0 0x5500000>; + }; + + pil_camera_mem: camera_region@8b700000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x8b700000 0x0 0x500000>; + }; + + pil_wlan_fw_mem: pil_wlan_fw_region@8bc00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x8bc00000 0x0 0x180000>; + }; + + pil_npu_mem: pil_npu_region@0x8bd80000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x8bd80000 0x0 0x80000>; + }; + + pil_adsp_mem: pil_adsp_region@0x8be00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x8be00000 0x0 0x1a00000>; + }; + + pil_modem_mem: modem_region@0x8d800000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x8d800000 0x0 0x9600000>; + }; + + pil_video_mem: pil_video_region@0x96e00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x96e00000 0x0 0x500000>; + }; + + pil_slpi_mem: pil_slpi_region@0x97300000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x97300000 0x0 0x1400000>; + }; + + pil_ipa_fw_mem: pil_ipa_fw_region@0x98700000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x98700000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: pil_ipa_gsi_region@0x98710000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x98710000 0x0 0x5000>; + }; + + pil_gpu_mem: pil_gpu_region@0x98715000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x98715000 0x0 0x2000>; + }; + + pil_spss_mem: pil_spss_region@0x98800000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x98800000 0x0 0x100000>; + }; + + pil_cdsp_mem: cdsp_regions@0x98900000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x98900000 0x0 0x1400000>; + }; + + qseecom_mem: qseecom_region@0x9e400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0x0 0x9e400000 0x0 0x1400000>; + }; + + + cont_splash_memory: cont_splash_region@0x9c000000 { + reg = <0x0 0x9c000000 0x0 0x02400000>; + label = "cont_splash_region"; + }; + + disp_rdump_memory: disp_rdump_region@0x9c000000 { + reg = <0x0 0x9c000000 0x0 0x02400000>; + label = "disp_rdump_region"; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + cdsp_mem: cdsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x400000>; + }; + + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; + }; + + secure_display_memory: secure_display_region { /* Secure UI */ + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xA000000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x2400000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2800000>; + linux,cma-default; + }; + }; + + vendor: vendor { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + }; + + soc: soc { }; + +}; + +#include "sdmshrike-gdsc.dtsi" +#include "sdmshrike-sde-pll.dtsi" +#include "sdmshrike-sde.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17a60000 0x100000>; /* GICR * 8 */ + interrupts = <1 9 4>; + interrupt-parent = <&intc>; + }; + + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x8804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = <0 204 0>, <0 222 0>; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <4>; + qcom,large-address-bus; + + qcom,clk-rates = <400000 20000000 25000000 + 50000000 100000000 200000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", + "SDR104"; + + qcom,devfreq,freq-table = <50000000 200000000>; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <81 512 0 0>, <1 608 0 0>, + /* 400 KB/s*/ + <81 512 1046 1600>, + <1 608 1600 1600>, + /* 20 MB/s */ + <81 512 52286 80000>, + <1 608 80000 80000>, + /* 25 MB/s */ + <81 512 65360 100000>, + <1 608 100000 100000>, + /* 50 MB/s */ + <81 512 130718 200000>, + <1 608 100000 100000>, + /* 100 MB/s */ + <81 512 261438 200000>, + <1 608 130000 130000>, + /* 200 MB/s */ + <81 512 261438 400000>, + <1 608 300000 300000>, + /* Max. bandwidth */ + <81 512 1338562 4096000>, + <1 608 1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100000000 200000000 4294967295>; + + qcom,restore-after-cx-collapse; + + /* PM QoS */ + qcom,pm-qos-irq-type = "affine_irq"; + qcom,pm-qos-irq-latency = <70 70>; + qcom,pm-qos-cpu-groups = <0x0f 0xf0>; + qcom,pm-qos-legacy-latency-us = <70 70>, <70 70>; + + clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>, + <&clock_gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface_clk", "core_clk"; + + status = "disabled"; + }; + + pdc: interrupt-controller@0xb220000{ + compatible = "qcom,pdc-sm8150"; + reg = <0xb220000 0x400>; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 1 0xf08>, + <1 2 0xf08>, + <1 3 0xf08>, + <1 0 0xf08>; + clock-frequency = <19200000>; + }; + + timer@0x17c20000{ + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17c20000 0x1000>; + clock-frequency = <19200000>; + + frame@0x17c21000 { + frame-number = <0>; + interrupts = <0 7 0x4>, + <0 6 0x4>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = <0 8 0x4>; + reg = <0x17c23000 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = <0 9 0x4>; + reg = <0x17c25000 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = <0 10 0x4>; + reg = <0x17c26000 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = <0 11 0x4>; + reg = <0x17c29000 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = <0 12 0x4>; + reg = <0x17c2b000 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = <0 13 0x4>; + reg = <0x17c2d000 0x1000>; + status = "disabled"; + }; + }; + + llcc_pmu: llcc-pmu@90cc000 { + compatible = "qcom,qcom-llcc-pmu"; + reg = <0x090cc000 0x300>, <0x09648000 0x200>; + reg-names = "lagg-base", "beac-base"; + }; + + llcc_bw_opp_table: llcc-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ + BW_OPP_ENTRY( 200, 16); /* 3051 MB/s */ + BW_OPP_ENTRY( 403, 16); /* 6149 MB/s */ + BW_OPP_ENTRY( 533, 16); /* 8132 MB/s */ + BW_OPP_ENTRY( 666, 16); /* 10162 MB/s */ + BW_OPP_ENTRY( 777, 16); /* 11856 MB/s */ + }; + + cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x90b6400 0x300>, <0x90b6300 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_cpu_llcc_bw>; + qcom,count-unit = <0x10000>; + }; + + ddr_bw_opp_table: ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ + BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ + BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ + BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ + BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ + BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ + BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ + BW_OPP_ENTRY(1296, 4); /* 4943 MB/s */ + BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ + BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ + BW_OPP_ENTRY(2092, 4); /* 7980 MB/s */ + }; + + cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@90cd000 { + compatible = "qcom,bimc-bwmon5"; + reg = <0x90cd000 0x1000>; + reg-names = "base"; + interrupts = ; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_llcc_ddr_bw>; + qcom,count-unit = <0x10000>; + }; + + cdsp_cdsp_l3_lat: qcom,cdsp-cdsp-l3-lat { + compatible = "devfreq-simple-dev"; + clock-names = "devfreq_clk"; + clocks = <&clock_cpucc L3_MISC_VOTE_CLK>; + governor = "powersave"; + }; + + cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { + compatible = "devfreq-simple-dev"; + clock-names = "devfreq_clk"; + clocks = <&clock_cpucc L3_CLUSTER0_VOTE_CLK>; + governor = "performance"; + }; + + cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = + < 300000 300000000 >, + < 576000 576000000 >, + < 672000 768000000 >, + < 864000 960000000 >, + < 1171200 1228800000 >, + < 1267200 1344000000 >; + }; + + cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat { + compatible = "devfreq-simple-dev"; + clock-names = "devfreq_clk"; + clocks = <&clock_cpucc L3_CLUSTER1_VOTE_CLK>; + governor = "performance"; + }; + + cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&cpu4_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = + < 300000 300000000 >, + < 576000 576000000 >, + < 768000 768000000 >, + < 960000 960000000 >, + < 1248000 1228800000 >, + < 1593600 1344000000 >; + }; + + cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_cpu_llcc_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS(150, 16) >, + < 576000 MHZ_TO_MBPS(200, 16) >, + < 672000 MHZ_TO_MBPS(403, 16) >, + < 864000 MHZ_TO_MBPS(533, 16) >, + < 1171200 MHZ_TO_MBPS(666, 16) >, + < 1267200 MHZ_TO_MBPS(777, 16) >; + }; + + cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu4_cpu_llcc_latmon: qcom,cpu4-cpu-llcc-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&cpu4_cpu_llcc_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS(150, 16) >, + < 576000 MHZ_TO_MBPS(200, 16) >, + < 768000 MHZ_TO_MBPS(403, 16) >, + < 960000 MHZ_TO_MBPS(533, 16) >, + < 1248000 MHZ_TO_MBPS(666, 16) >, + < 1593600 MHZ_TO_MBPS(777, 16) >; + }; + + cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_llcc_ddr_lat>; + qcom,cachemiss-ev = <0x1000>; + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS( 200, 4) >, + < 576000 MHZ_TO_MBPS( 451, 4) >, + < 672000 MHZ_TO_MBPS( 768, 4) >, + < 864000 MHZ_TO_MBPS(1017, 4) >, + < 1171200 MHZ_TO_MBPS(1555, 4) >, + < 1267200 MHZ_TO_MBPS(1804, 4) >; + }; + + cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&cpu4_llcc_ddr_lat>; + qcom,cachemiss-ev = <0x1000>; + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS( 200, 4) >, + < 576000 MHZ_TO_MBPS( 451, 4) >, + < 768000 MHZ_TO_MBPS( 768, 4) >, + < 960000 MHZ_TO_MBPS(1017, 4) >, + < 1248000 MHZ_TO_MBPS(1555, 4) >, + < 1593600 MHZ_TO_MBPS(1804, 4) >, + < 1689600 MHZ_TO_MBPS(2092, 4) >; + }; + + cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu4_computemon: qcom,cpu4-computemon { + compatible = "qcom,arm-cpu-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&cpu4_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1593600 MHZ_TO_MBPS( 200, 4) >, + < 2016000 MHZ_TO_MBPS(1017, 4) >, + < 2054400 MHZ_TO_MBPS(2092, 4) >; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = <1 5 4>; + }; + + qcom,chd_silver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x18000058 0x18010058 + 0x18020058 0x18030058>; + qcom,config-arr = <0x18000060 0x18010060 + 0x18020060 0x18030060>; + }; + + qcom,chd_gold { + compatible = "qcom,core-hang-detect"; + label = "gold"; + qcom,threshold-arr = <0x18040058 0x18050058 + 0x18060058 0x18070058>; + qcom,config-arr = <0x18040060 0x18050060 + 0x18060060 0x18070060>; + }; + + qcom,ghd { + compatible = "qcom,gladiator-hang-detect-v3"; + qcom,threshold-arr = <0x17e0041C>; + qcom,config-reg = <0x17e00434>; + }; + + kryo-erp { + compatible = "arm,arm64-kryo-cpu-erp"; + interrupts = <1 6 4>, + <1 7 4>, + <0 34 4>, + <0 35 4>; + + interrupt-names = "l1-l2-faultirq", + "l1-l2-errirq", + "l3-scu-errirq", + "l3-scu-faultirq"; + }; + + qcom,llcc@9200000 { + compatible = "qcom,llcc-core", "syscon", "simple-mfd"; + reg = <0x9200000 0x450000>; + reg-names = "llcc_base"; + qcom,llcc-banks-off = <0x0 0x80000 0x100000 0x180000 + 0x200000 0x280000 0x300000 0x380000>; + qcom,llcc-broadcast-off = <0x400000>; + + llcc: qcom,sdmshrike-llcc { + compatible = "qcom,sdmshrike-llcc"; + #cache-cells = <1>; + max-slices = <32>; + }; + + qcom,llcc-erp { + compatible = "qcom,llcc-erp"; + }; + + qcom,llcc-amon { + compatible = "qcom,llcc-amon"; + }; + }; + + qmp_aop: qcom,qmp-aop@c300000 { + compatible = "qcom,qmp-mbox"; + reg = <0xc300000 0x1000>, <0x17c0000C 0x4>; + reg-names = "msgram", "irq-reg-base"; + qcom,irq-mask = <0x1>; + interrupts = ; + + label = "aop"; + qcom,early-boot; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; + + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: qcom,hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 3>; + }; + + apcs: syscon@17c0000c { + compatible = "syscon"; + reg = <0x17c0000c 0x4>; + }; + + apcs_glb: mailbox@17c00000 { + compatible = "qcom,sm8150-apcs-hmss-global"; + reg = <0x17c00000 0x1000>; + + #mbox-cells = <1>; + }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_modem: modem { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&apcs_glb 12>; + mbox-names = "mpss_smem"; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + }; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&apcs_glb 8>; + mbox-names = "adsp_smem"; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,apr_tal_rpmsg { + qcom,glink-channels = "apr_audio_svc"; + qcom,intents = <0x200 20>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + }; + + glink_slpi: dsps { + qcom,remote-pid = <3>; + transport = "smem"; + mboxes = <&apcs_glb 24>; + mbox-names = "dsps_smem"; + interrupts = ; + + label = "slpi"; + qcom,glink-label = "dsps"; + + qcom,slpi_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + }; + + glink_cdsp: cdsp { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&apcs_glb 4>; + mbox-names = "cdsp_smem"; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + }; + + glink_spi_xprt_wdsp: wdsp { + qcom,remote-pid = <10>; + transport = "spi"; + tx-descriptors = <0x12000 0x12004>; + rx-descriptors = <0x1200c 0x12010>; + + label = "wdsp"; + qcom,glink-label = "wdsp"; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + slim_aud: slim@171c0000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0x171c0000 0x2c000>, + <0x17184000 0x2c000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 163 0>, <0 164 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x780000>; + qcom,ea-pc = <0x2b0>; + qcom,iommu-s1-bypass; + + iommu_slim_aud_ctrl_cb: qcom,iommu_slim_ctrl_cb { + compatible = "qcom,iommu-slim-ctrl-cb"; + iommus = <&apps_smmu 0x1b46 0x8>, + <&apps_smmu 0x1b4d 0x2>, + <&apps_smmu 0x1b50 0x1>; + }; + }; + + spmi_bus: qcom,spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0x1100>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>, + <0xe700000 0xa0000>, + <0xc40a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + thermal_zones: thermal-zones { + }; + + cmd_db: qcom,cmd-db@c3f000c { + compatible = "qcom,cmd-db"; + reg = <0xc3f000c 8>; + }; + + apps_rsc: mailbox@18220000 { + compatible = "qcom,tcs-drv"; + label = "apps_rsc"; + reg = <0x18220000 0x100>, <0x18220d00 0x3000>; + interrupts = ; + #mbox-cells = <1>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + }; + + disp_rsc: mailbox@af20000 { + status = "disabled"; + compatible = "qcom,tcs-drv"; + label = "display_rsc"; + reg = <0xaf20000 0x100>, <0xaf21c00 0x3000>; + interrupts = ; + #mbox-cells = <1>; + qcom,drv-id = <0>; + qcom,tcs-config = , + , + , + ; + }; + + keepalive_opp_table: keepalive-opp-table { + compatible = "operating-points-v2"; + opp-1 { + opp-hz = /bits/ 64 < 1 >; + }; + }; + + snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <1 627>; + qcom,active-only; + status = "ok"; + operating-points-v2 = <&keepalive_opp_table>; + }; + + cdsp_keepalive: qcom,cdsp_keepalive { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <154 10070>; + qcom,active-only; + status = "ok"; + operating-points-v2 = <&keepalive_opp_table>; + }; + + clock_rpmh: qcom,rpmhclk { + compatible = "qcom,rpmh-clk-sdmshrike"; + mboxes = <&apps_rsc 0>; + mbox-names = "apps"; + #clock-cells = <1>; + }; + + clock_gcc: qcom,gcc@100000 { + compatible = "qcom,gcc-sdmshrike", "syscon"; + reg = <0x100000 0x1f0000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_videocc: qcom,videocc@ab00000 { + compatible = "qcom,videocc-sm8150-v2", "syscon"; + reg = <0xab00000 0x10000>; + reg-names = "cc_base"; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + clock-names = "cfg_ahb_clk"; + clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_npucc: qcom,npucc@9910000 { + compatible = "qcom,npucc-sm8150"; + reg = <0x9910000 0x10000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_gdsc-supply = <&npu_core_gdsc>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_dispcc: qcom,dispcc@af00000 { + compatible = "qcom,dispcc-sm8150"; + reg = <0xaf00000 0x20000>; + reg-names = "cc_base"; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + clock-names = "cfg_ahb_clk"; + clocks = <&clock_gcc GCC_DISP_AHB_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_camcc: qcom,camcc@ad00000 { + compatible = "qcom,camcc-sdmshrike", "syscon"; + reg = <0xad00000 0x20000>; + reg-names = "cc_base"; + vdd_mx-supply = <&pm8150c_s3_level>; + vdd_mm-supply = <&pm8150c_s1_level>; + clock-names = "cfg_ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + #clock-cells = <1>; + }; + + clock_cpucc: qcom,cpucc@18321000 { + compatible = "qcom,clk-cpu-osm-sdmshrike"; + reg = <0x18321000 0x1400>, + <0x18323000 0x1400>, + <0x18325800 0x1400>; + reg-names = "osm_l3_base", "osm_pwrcl_base", + "osm_perfcl_base"; + l3-devs = <&cpu0_cpu_l3_lat &cpu4_cpu_l3_lat &cdsp_cdsp_l3_lat>; + #clock-cells = <1>; + }; + + clock_gpucc: qcom,gpucc@2c90000 { + compatible = "qcom,gpucc-sdmshrike", "syscon"; + reg = <0x2c90000 0x9000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_scc: qcom,scc@2b10000 { + compatible = "qcom,scc-sm8150-v2"; + reg = <0x2b10000 0x30000>; + #clock-cells = <1>; + status = "disabled"; + }; + + cpucc_debug: syscon@182a0018 { + compatible = "syscon"; + reg = <0x182a0018 0x4>; + }; + + tsens0: tsens@c222000 { + compatible = "qcom,tsens24xx"; + reg = <0xc222000 0x4>, + <0xc263000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts = <0 506 0>, <0 508 0>; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: tsens@c223000 { + compatible = "qcom,tsens24xx"; + reg = <0xc223000 0x4>, + <0xc265000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts = <0 507 0>, <0 509 0>; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + #thermal-sensor-cells = <1>; + }; + + clock_aop: qcom,aopclk { + compatible = "qcom,aop-qmp-clk"; + mboxes = <&qmp_aop 0>; + mbox-names = "qdss_clk"; + #clock-cells = <1>; + }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x200000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + }; + + pil_lpass: qcom,lpass@17300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x17300000 0x00100>; + + vdd_cx-supply = <&pm8150_2_s3_level>; + qcom,proxy-reg-names = "vdd_cx"; + + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <1>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,sysmon-id = <1>; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + + /* Inputs from lpass */ + interrupts-extended = <&pdc 0 162 1>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "adsp-pil"; + }; + + pil_ssc: qcom,ssc@5c00000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x5c00000 0x4000>; + + vdd_cx-supply = <&L8E_LEVEL>; + vdd_mx-supply = <&L4E_LEVEL>; + + qcom,proxy-reg-names = "vdd_cx", "vdd_mx"; + qcom,keep-proxy-regs-on; + + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <12>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <424>; + qcom,sysmon-id = <3>; + qcom,ssctl-instance-id = <0x16>; + qcom,firmware-name = "slpi"; + status = "ok"; + memory-region = <&pil_slpi_mem>; + + /* Inputs from ssc */ + interrupts-extended = <&pdc 0 494 1>, + <&dsps_smp2p_in 0 0>, + <&dsps_smp2p_in 2 0>, + <&dsps_smp2p_in 1 0>, + <&dsps_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to ssc */ + qcom,smem-states = <&dsps_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "slpi-pil"; + }; + + pil_spss: qcom,spss@1880000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x188101c 0x4>, + <0x1881024 0x4>, + <0x1881028 0x4>, + <0x188103c 0x4>, + <0x1882014 0x4>; + reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", + "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2"; + interrupts = <0 352 1>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,proxy-reg-names = "vdd_cx"; + vdd_mx-supply = <&VDD_MX_LEVEL>; + + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + qcom,pil-generic-irq-handler; + status = "ok"; + qcom,signal-aop; + qcom,complete-ramdump; + + qcom,pas-id = <14>; + qcom,proxy-timeout-ms = <10000>; + qcom,firmware-name = "spss"; + memory-region = <&pil_spss_mem>; + qcom,spss-scsr-bits = <24 25>; + + mboxes = <&qmp_aop 0>; + mbox-names = "spss-pil"; + }; + + pil_npu: qcom,npu@0x9800000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x9800000 0x800000>; + + status = "ok"; + qcom,pas-id = <23>; + qcom,firmware-name = "npu"; + + memory-region = <&pil_npu_mem>; + }; + + pil_turing: qcom,turing@8300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x8300000 0x100000>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,proxy-reg-names = "vdd_cx"; + + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <18>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <601>; + qcom,sysmon-id = <7>; + qcom,ssctl-instance-id = <0x17>; + qcom,firmware-name = "cdsp"; + memory-region = <&pil_cdsp_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + + qcom,msm-bus,name = "pil-cdsp"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <154 10070 0 0>, + <154 10070 0 1>; + + /* Inputs from turing */ + interrupts-extended = <&pdc 0 578 1>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "cdsp-pil"; + }; + + pil_venus: qcom,venus@aae0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xaae0000 0x4000>; + + vdd-supply = <&mvsc_gdsc>; + qcom,proxy-reg-names = "vdd"; + qcom,complete-ramdump; + + clocks = <&clock_videocc VIDEO_CC_XO_CLK>, + <&clock_videocc VIDEO_CC_MVSC_CORE_CLK>, + <&clock_videocc VIDEO_CC_IRIS_AHB_CLK>; + clock-names = "xo", "core", "ahb"; + qcom,proxy-clock-names = "xo", "core", "ahb"; + + qcom,core-freq = <200000000>; + qcom,ahb-freq = <200000000>; + + qcom,pas-id = <9>; + qcom,msm-bus,name = "pil-venus"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <63 512 0 0>, + <63 512 0 304000>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&pil_video_mem>; + }; + + ssc_sensors: qcom,msm-ssc-sensors { + compatible = "qcom,msm-ssc-sensors"; + qcom,firmware-name = "slpi"; + status = "disabled"; + }; + + wdog: qcom,wdt@17c10000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17c10000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 0 0>, <0 1 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; + + qcom,msm-imem@146bf000 { + compatible = "qcom,msm-imem"; + reg = <0x146bf000 0x1000>; + ranges = <0x0 0x146bf000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 32>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 12>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 200>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 200>; + }; + }; + + restart@c264000 { + compatible = "qcom,pshold"; + reg = <0xc264000 0x4>, + <0x1fd3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + qcom,mpm2-sleep-counter@c221000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xc221000 0x1000>; + clock-frequency = <32768>; + }; + + ufs_ice: ufsice@1d90000 { + compatible = "qcom,ice"; + reg = <0x1d90000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk", + "iface_clk", "ice_core_clk"; + clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_UFS_PHY_AHB_CLK>, + <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>; + qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; + vdd-hba-supply = <&ufs_phy_gdsc>; + qcom,msm-bus,name = "ufs_ice_noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 650 0 0>, /* No vote */ + <1 650 1000 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "ufs"; + }; + + ufsphy_mem: ufsphy_mem@1d87000 { + reg = <0x1d87000 0xda8>; /* PHY regs */ + reg-names = "phy_mem"; + #phy-cells = <0>; + ufs-qcom-crypto = <&ufs_ice>; + + lanes-per-direction = <2>; + + clock-names = "ref_clk_src", + "ref_aux_clk"; + clocks = <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x2500>; + interrupts = <0 265 0>; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + ufs-qcom-crypto = <&ufs_ice>; + qcom,disable-lpm; + + lanes-per-direction = <2>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&clock_gcc GCC_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_UFS_PHY_AHB_CLK>, + <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <37500000 300000000>, + <0 0>, + <0 0>, + <37500000 300000000>, + <37500000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + qcom,msm-bus,name = "ufshc_mem"; + qcom,msm-bus,num-cases = <26>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <123 512 0 0>, <1 797 0 0>, /* No vote */ + <123 512 922 0>, <1 797 1000 0>, /* PWM G1 */ + <123 512 1844 0>, <1 797 1000 0>, /* PWM G2 */ + <123 512 3688 0>, <1 797 1000 0>, /* PWM G3 */ + <123 512 7376 0>, <1 797 1000 0>, /* PWM G4 */ + <123 512 1844 0>, <1 797 1000 0>, /* PWM G1 L2 */ + <123 512 3688 0>, <1 797 1000 0>, /* PWM G2 L2 */ + <123 512 7376 0>, <1 797 1000 0>, /* PWM G3 L2 */ + <123 512 14752 0>, <1 797 1000 0>, /* PWM G4 L2 */ + <123 512 127796 0>, <1 797 1000 0>, /* HS G1 RA */ + <123 512 255591 0>, <1 797 1000 0>, /* HS G2 RA */ + <123 512 2097152 0>, <1 797 102400 0>, /* HS G3 RA */ + <123 512 4194304 0>, <1 797 204800 0>, /* HS G4 RA */ + <123 512 255591 0>, <1 797 1000 0>, /* HS G1 RA L2 */ + <123 512 511181 0>, <1 797 1000 0>, /* HS G2 RA L2 */ + <123 512 4194304 0>, <1 797 204800 0>, /* HS G3 RA L2 */ + <123 512 8388608 0>, <1 797 409600 0>, /* HS G4 RA L2 */ + <123 512 149422 0>, <1 797 1000 0>, /* HS G1 RB */ + <123 512 298189 0>, <1 797 1000 0>, /* HS G2 RB */ + <123 512 2097152 0>, <1 797 102400 0>, /* HS G3 RB */ + <123 512 4194304 0>, <1 797 204800 0>, /* HS G4 RB */ + <123 512 298189 0>, <1 797 1000 0>, /* HS G1 RB L2 */ + <123 512 596378 0>, <1 797 1000 0>, /* HS G2 RB L2 */ + /* As UFS working in HS G3 RB L2 mode, aggregated + * bandwidth (AB) should take care of providing + * optimum throughput requested. However, as tested, + * in order to scale up CNOC clock, instantaneous + * bindwidth (IB) needs to be given a proper value too. + */ + <123 512 4194304 0>, <1 797 204800 409600>, /* HS G3 RB L2 */ + <123 512 8388608 0>, <1 797 409600 409600>, /* HS G4 RB L2 */ + <123 512 7643136 0>, <1 797 307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", + "MAX"; + + /* PM QoS */ + qcom,pm-qos-cpu-groups = <0x0f 0xf0>; + qcom,pm-qos-cpu-group-latency-us = <44 44>; + qcom,pm-qos-default-cpu = <0>; + + pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; + pinctrl-0 = <&ufs_dev_reset_assert>; + pinctrl-1 = <&ufs_dev_reset_deassert>; + + resets = <&clock_gcc GCC_UFS_PHY_BCR>; + reset-names = "core_reset"; + + status = "disabled"; + }; + + qcom,msm-cdsp-loader { + compatible = "qcom,cdsp-loader"; + qcom,proc-img-to-load = "cdsp"; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + }; + + msm_fastrpc: qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,fastrpc-adsp-audio-pdr; + qcom,rpc-latency-us = <235>; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1401 0x2040>, + <&apps_smmu 0x1421 0x0>, + <&apps_smmu 0x2001 0x420>, + <&apps_smmu 0x2041 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x4 0x3440>, + <&apps_smmu 0x24 0x3400>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x5 0x3440>, + <&apps_smmu 0x25 0x3400>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x6 0x3460>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb7 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x7 0x3460>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb8 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x8 0x3460>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x2 0x3440>, + <&apps_smmu 0x22 0x3400>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x3 0x3440>, + <&apps_smmu 0x1423 0x0>, + <&apps_smmu 0x2023 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb9 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x9 0x3460>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb10 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1b23 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb11 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1b24 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb12 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1b25 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb13 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "sdsprpc-smd"; + iommus = <&apps_smmu 0x5a1 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb14 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "sdsprpc-smd"; + iommus = <&apps_smmu 0x5a2 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb15 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "sdsprpc-smd"; + iommus = <&apps_smmu 0x5a3 0x0>; + shared-cb = <4>; + dma-coherent; + }; + }; + + system_pm { + compatible = "qcom,system-pm"; + mboxes = <&apps_rsc 0>; + }; + + qcom_seecom: qseecom@87900000 { + compatible = "qcom,qseecom"; + reg = <0x87900000 0x2200000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,no-clock-support; + qcom,fde-key-size; + qcom,appsbl-qseecom-support; + qcom,commonlib64-loaded-by-uefi; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_smcinvoke: smcinvoke@87900000 { + compatible = "qcom,smcinvoke"; + reg = <0x87900000 0x2200000>; + reg-names = "secapp-region"; + }; + + qcom_rng: qrng@793000 { + compatible = "qcom,msm-rng"; + reg = <0x793000 0x1000>; + qcom,msm-rng-iface-clk; + qcom,no-qrng-config; + qcom,msm-bus,name = "msm-rng-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 618 0 0>, /* No vote */ + <1 618 0 300000>; /* 75 MHz */ + clocks = <&clock_gcc GCC_PRNG_AHB_CLK>; + clock-names = "iface_clk"; + }; + + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + rpmh { + qcom,dump-size = <0x2000000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + tmc_etf { + qcom,dump-size = <0x8000>; + qcom,dump-id = <0xf0>; + }; + + etf_swao { + qcom,dump-size = <0x8000>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etf_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x101>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + }; + +}; + +&emac_gdsc { + status = "ok"; +}; + +&pcie_0_gdsc { + status = "ok"; +}; + +&pcie_1_gdsc { + status = "ok"; +}; + +&pcie_2_gdsc { + status = "ok"; +}; + +&pcie_3_gdsc { + status = "ok"; +}; + +&ufs_card_gdsc { + status = "ok"; +}; + +&ufs_card_2_gdsc { + status = "ok"; +}; + +&ufs_phy_gdsc { + status = "ok"; +}; + +&usb30_prim_gdsc { + status = "ok"; +}; + +&usb30_sec_gdsc { + status = "ok"; +}; + +&usb30_mp_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu1_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu2_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu0_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu1_gdsc { + status = "ok"; +}; + +&bps_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&ipe_0_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&ipe_1_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&ife_0_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&ife_1_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&ife_2_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&ife_3_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&titan_top_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&mdss_core_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_DISP_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; + qcom,msm-bus,name = "mdss_core_gdsc_ahb"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + status = "ok"; +}; + +&gpu_cx_gdsc { + status = "ok"; +}; + +&gpu_gx_gdsc { + parent-supply = <&pm8150_1_s10_level>; + vdd_parent-supply = <&pm8150_1_s10_level>; + status = "ok"; +}; + +&mvsc_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&mvs0_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&mvs1_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&npu_core_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_NPU_CFG_AHB_CLK>; + status = "ok"; +}; + +#include "sdmshrike-smp2p.dtsi" +#include "sdmshrike-pinctrl.dtsi" +#include "sm8150-slpi-pinctrl.dtsi" +#include "sdmshrike-regulators.dtsi" +#include "sdmshrike-ion.dtsi" +#include "sdmshrike-bus.dtsi" +#include "msm-arm-smmu-sdmshrike.dtsi" +#include "sdmshrike-usb.dtsi" +#include "sdmshrike-qupv3.dtsi" +#include "sm8150-audio.dtsi" +#include "sm8150-pm.dtsi" +#include "sdmshrike-gpu.dtsi" +#include "sdmshrike-thermal.dtsi" diff --git a/arch/arm/boot/dts/qcom/sdx-audio-lpass.dtsi b/arch/arm/boot/dts/qcom/sdx-audio-lpass.dtsi new file mode 100644 index 000000000000..2c2319f7c886 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdx-audio-lpass.dtsi @@ -0,0 +1,345 @@ +/* + * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,msm-adsp-loader { + compatible = "qcom,adsp-loader"; + qcom,adsp-state = <0>; + qcom,proc-img-to-load = "modem"; + }; + + qcom,msm-audio-ion { + compatible = "qcom,msm-audio-ion"; + qcom,scm-mp-enabled; + memory-region = <&audio_mem>; + }; + + pcm0: qcom,msm-pcm { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <0>; + }; + + routing: qcom,msm-pcm-routing { + compatible = "qcom,msm-pcm-routing"; + }; + + pcm1: qcom,msm-pcm-low-latency { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <1>; + qcom,msm-pcm-low-latency; + qcom,latency-level = "ultra"; + }; + + qcom,msm-compr-dsp { + compatible = "qcom,msm-compr-dsp"; + }; + + voip: qcom,msm-voip-dsp { + compatible = "qcom,msm-voip-dsp"; + }; + + voice: qcom,msm-pcm-voice { + compatible = "qcom,msm-pcm-voice"; + qcom,destroy-cvd; + }; + + stub_codec: qcom,msm-stub-codec { + compatible = "qcom,msm-stub-codec"; + }; + + qcom,msm-dai-fe { + compatible = "qcom,msm-dai-fe"; + }; + + afe: qcom,msm-pcm-afe { + compatible = "qcom,msm-pcm-afe"; + }; + + hostless: qcom,msm-pcm-hostless { + compatible = "qcom,msm-pcm-hostless"; + }; + + audio_apr: qcom,msm-audio-apr { + compatible = "qcom,msm-audio-apr"; + qcom,subsys-name = "apr_modem"; + }; + + host_pcm: qcom,msm-voice-host-pcm { + compatible = "qcom,msm-voice-host-pcm"; + }; + + loopback: qcom,msm-pcm-loopback { + compatible = "qcom,msm-pcm-loopback"; + }; + + compress: qcom,msm-compress-dsp { + compatible = "qcom,msm-compress-dsp"; + qcom,adsp-version = "MDSP 1.2"; + }; + + qcom,msm-dai-stub { + compatible = "qcom,msm-dai-stub"; + dtmf_tx: qcom,msm-dai-stub-dtmf-tx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <4>; + }; + + rx_capture_tx: qcom,msm-dai-stub-host-rx-capture-tx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <5>; + }; + + rx_playback_rx: qcom,msm-dai-stub-host-rx-playback-rx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <6>; + }; + + tx_capture_tx: qcom,msm-dai-stub-host-tx-capture-tx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <7>; + }; + + tx_playback_rx: qcom,msm-dai-stub-host-tx-playback-rx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <8>; + }; + }; + + qcom,msm-dai-q6 { + compatible = "qcom,msm-dai-q6"; + afe_pcm_rx: qcom,msm-dai-q6-be-afe-pcm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <224>; + }; + + afe_pcm_tx: qcom,msm-dai-q6-be-afe-pcm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <225>; + }; + + afe_proxy_rx: qcom,msm-dai-q6-afe-proxy-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <241>; + }; + + afe_proxy_tx: qcom,msm-dai-q6-afe-proxy-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <240>; + }; + + incall_record_rx: qcom,msm-dai-q6-incall-record-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32771>; + }; + + incall_record_tx: qcom,msm-dai-q6-incall-record-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32772>; + }; + + incall_music_rx: qcom,msm-dai-q6-incall-music-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32773>; + }; + }; + + pcm_dtmf: qcom,msm-pcm-dtmf { + compatible = "qcom,msm-pcm-dtmf"; + }; + + cpu-pmu { + compatible = "arm,cortex-a7-pmu"; + qcom,irq-is-percpu; + interrupts = <1 8 0x100>; + }; + + dai_pri_auxpcm: qcom,msm-pri-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "primary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + dai_sec_auxpcm: qcom,msm-sec-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "secondary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + qcom,msm-dai-tdm-pri-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37120>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36864>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <0>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <1>; + qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>; + dai_pri_tdm_rx_0: qcom,msm-dai-q6-tdm-pri-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36864>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + }; + + qcom,msm-dai-tdm-pri-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37121>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36865>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <0>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <1>; + qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>; + dai_pri_tdm_tx_0: qcom,msm-dai-q6-tdm-pri-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36865>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-sec-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37136>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36880>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sec_tdm_rx_0: qcom,msm-dai-q6-tdm-sec-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36880>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-sec-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37137>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36881>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sec_tdm_tx_0: qcom,msm-dai-q6-tdm-sec-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36881>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-mi2s { + compatible = "qcom,msm-dai-mi2s"; + mi2s_prim: qcom,msm-dai-q6-mi2s-prim { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <0>; + qcom,msm-mi2s-rx-lines = <2>; + qcom,msm-mi2s-tx-lines = <1>; + }; + mi2s_sec: qcom,msm-dai-q6-mi2s-sec { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <1>; + qcom,msm-mi2s-rx-lines = <2>; + qcom,msm-mi2s-tx-lines = <1>; + }; + + }; + + prim_master: prim_master_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&pri_ws_active_master + &pri_sck_active_master + &pri_dout_active + &pri_din_active>; + pinctrl-1 = <&pri_ws_sleep + &pri_sck_sleep + &pri_dout_sleep + &pri_din_sleep>; + qcom,mi2s-auxpcm-cdc-gpios; + }; + + prim_slave: prim_slave_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&pri_ws_active_slave + &pri_sck_active_slave + &pri_dout_active + &pri_din_active>; + pinctrl-1 = <&pri_ws_sleep + &pri_sck_sleep + &pri_dout_sleep + &pri_din_sleep>; + qcom,mi2s-auxpcm-cdc-gpios; + }; + + sec_master: sec_master_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&sec_ws_active_master + &sec_sck_active_master + &sec_dout_active + &sec_din_active>; + pinctrl-1 = <&sec_ws_sleep + &sec_sck_sleep + &sec_dout_sleep + &sec_din_sleep>; + qcom,mi2s-auxpcm-cdc-gpios; + }; + + sec_slave: sec_slave_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&sec_ws_active_slave + &sec_sck_active_slave + &sec_dout_active + &sec_din_active>; + pinctrl-1 = <&sec_ws_sleep + &sec_sck_sleep + &sec_dout_sleep + &sec_din_sleep>; + qcom,mi2s-auxpcm-cdc-gpios; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdx-wsa881x.dtsi b/arch/arm/boot/dts/qcom/sdx-wsa881x.dtsi new file mode 100644 index 000000000000..3d4e90a260e5 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdx-wsa881x.dtsi @@ -0,0 +1,45 @@ +/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&i2c_3 { + tavil_codec { + swr_master { + compatible = "qcom,swr-wcd"; + #address-cells = <2>; + #size-cells = <0>; + + wsa881x_0211: wsa881x@20170211 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170211>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>; + }; + + wsa881x_0212: wsa881x@20170212 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170212>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>; + }; + + wsa881x_0213: wsa881x@21170213 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170213>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>; + }; + + wsa881x_0214: wsa881x@21170214 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170214>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdx5xm-external-soc.dtsi b/arch/arm/boot/dts/qcom/sdx5xm-external-soc.dtsi new file mode 100644 index 000000000000..0d0af328d788 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdx5xm-external-soc.dtsi @@ -0,0 +1,59 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + mdm3: qcom,mdm3 { + cell-index = <0>; + #address-cells = <0>; + interrupt-parent = <&mdm3>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-names = + "err_fatal_irq", + "status_irq", + "mdm2ap_vddmin_irq"; + /* modem attributes */ + qcom,ramdump-delay-ms = <3000>; + qcom,ramdump-timeout-ms = <120000>; + qcom,vddmin-modes = "normal"; + qcom,vddmin-drive-strength = <8>; + qcom,sfr-query; + qcom,sysmon-id = <20>; + qcom,ssctl-instance-id = <0x10>; + qcom,support-shutdown; + qcom,pil-force-shutdown; + pinctrl-names = "default", "mdm_active", "mdm_suspend"; + pinctrl-0 = <&ap2mdm_pon_reset_default>; + pinctrl-1 = <&ap2mdm_active &mdm2ap_active>; + pinctrl-2 = <&ap2mdm_sleep &mdm2ap_sleep>; + interrupt-map = <0 &tlmm 53 0x3 + 1 &tlmm 135 0x3>; + qcom,mdm2ap-errfatal-gpio = <&tlmm 53 0x00>; + qcom,ap2mdm-errfatal-gpio = <&tlmm 141 0x00>; + qcom,mdm2ap-status-gpio = <&tlmm 142 0x00>; + qcom,ap2mdm-status-gpio = <&tlmm 135 0x00>; + qcom,ap2mdm-soft-reset-gpio = <&pm8150l_gpios 9 0>; + qcom,esoc-skip-restart-for-mdm-crash; + status = "ok"; + }; +}; + +&pm8150l_gpios { + ap2mdm_pon_reset { + ap2mdm_pon_reset_default: ap2mdm_pon_reset_default { + /* MDM PON conrol*/ + pins = "gpio9"; + function = "normal"; + power-source = <1>; /* 1.8V */ + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-aqc.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-aqc.dtsi new file mode 100644 index 000000000000..ff0802a715b8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-aqc.dtsi @@ -0,0 +1,95 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&pcie0_rp { + aqc_x4: aquantia,aqc107@pcie0_rp { + reg = <0 0 0 0 0>; + + compatible = "aquantia,aqc-107"; + + pci-ids = + "1d6a:0001", + "1d6a:d107", + "1d6a:07b1", + "1d6a:87b1", + "1d6a:d108", + "1d6a:08b1", + "1d6a:88b1", + "1d6a:d109", + "1d6a:09b1", + "1d6a:89b1", + "1d6a:d100", + "1d6a:00b1", + "1d6a:80b1", + "1d6a:11b1", + "1d6a:91b1", + "1d6a:51b1", + "1d6a:12b1", + "1d6a:92b1", + "1d6a:52b1"; + + qcom,smmu; + + /* IOVA range is restricted to avoid conflicts with PCI BAR + * space and IOVA spaces used by peripherals that are currently + * attached to IPA. + */ + qcom,smmu-iova-base = /bits/ 64 <0x80000000>; + qcom,smmu-iova-size = /bits/ 64 <0x10000000>; + + qcom,smmu-attr-atomic; + qcom,smmu-attr-fastmap; + + /* AQC IPA offload driver */ + + qcom,rx-proxy = <&atd_proxy_host>, + <&atd_proxy_uc>; + qcom,rx-proxy-mode = "counter"; + + qcom,rx-ring-size = <4096>; + qcom,rx-buff-size = <2048>; + qcom,rx-int-mod-usecs = <64>; + + qcom,rx-gsi-mod-pc = <10>; + qcom,rx-gsi-mod-timer = <32>; + + qcom,tx-ring-size = <4096>; + qcom,tx-buff-size = <2048>; + qcom,tx-wrb-mod-pc = <25>; + + qcom,tx-gsi-mod-pc = <10>; + qcom,tx-gsi-mod-timer = <32>; + + qcom,use-pci-direct; + + #address-cells = <1>; + #size-cells = <1>; + + atd_proxy_host: host_proxy@17a00040 { + reg = <0x17800200 0>; + reg-names = "intc-ispendr-n"; + + interrupt-parent = <&intc>; + interrupts = ; + + qcom,proxy-agent = "host"; + qcom,proxy-method = "msi"; + }; + + atd_proxy_uc: uc_proxy@1ec2080 { + qcom,proxy-agent = "uc"; + qcom,proxy-method = "msi"; + qcom,proxy-msi-addr = /bits/ 64 <0x01ec2080>; + qcom,proxy-msi-data = /bits/ 32 <0x636f6d6d>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-audio-overlay.dtsi new file mode 100644 index 000000000000..f4d43970d8b2 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-audio-overlay.dtsi @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdxprairie-wcd.dtsi" +#include "sdx-wsa881x.dtsi" +#include + +&snd_934x { + qcom,audio-routing = + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC3", "MIC BIAS2", + "MIC BIAS2", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2", + "MIC BIAS2", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS3", + "MIC BIAS3", "Handset Mic", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "DMIC4", "MIC BIAS4", + "MIC BIAS4", "Digital Mic4", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "SpkrRight IN", "SPK2 OUT"; + + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,msm-mbhc-hs-mic-max-threshold-mv = <1700>; + qcom,msm-mbhc-hs-mic-min-threshold-mv = <50>; + qcom,cdc-ext-clk-rate = <19200000>; + qcom,tavil-mclk-clk-freq = <9600000>; + + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + + qcom,wsa-max-devs = <2>; + qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>, + <&wsa881x_0213>, <&wsa881x_0214>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", + "SpkrLeft", "SpkrRight"; +}; + +&soc { + wcd9xxx_intc: wcd9xxx-irq { + status = "ok"; + compatible = "qcom,wcd9xxx-irq"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&tlmm>; + qcom,gpio-connect = <&tlmm 96 0>; + pinctrl-names = "default"; + pinctrl-0 = <&wcd_intr_default>; + }; + + clock_audio_up: audio_ext_clk_up { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-clk-id = <770>; + qcom,codec-lpass-ext-clk-freq = <9600000>; + qcom,use-pinctrl = <1>; + pinctrl-names = "sleep", "active"; + pinctrl-0 = <&i2s_mclk_sleep>; + pinctrl-1 = <&i2s_mclk_active>; + #clock-cells = <1>; + }; + + wcd_rst_gpio: msm_cdc_pinctrl@92 { + compatible = "qcom,msm-cdc-pinctrl"; + qcom,cdc-rst-n-gpio = <&tlmm 92 0>; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_reset_active>; + pinctrl-1 = <&cdc_reset_sleep>; + }; +}; + +&i2c_3 { + wcd934x_cdc: tavil_codec { + compatible = "qcom,tavil-i2c"; + reg = <0x0d>; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 + 30 31>; + + qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; + + clock-names = "wcd_clk"; + clocks = <&clock_audio_up 0>; + + cdc-vdd-buck-supply = <&pmxprairie_l6>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <650000>; + + cdc-buck-sido-supply = <&pmxprairie_l6>; + qcom,cdc-buck-sido-voltage = <1800000 1800000>; + qcom,cdc-buck-sido-current = <250000>; + + cdc-vdd-tx-h-supply = <&pmxprairie_l6>; + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-tx-h-current = <25000>; + + cdc-vdd-rx-h-supply = <&pmxprairie_l6>; + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-rx-h-current = <25000>; + + cdc-vddpx-1-supply = <&pmxprairie_l6>; + qcom,cdc-vddpx-1-voltage = <1800000 1800000>; + qcom,cdc-vddpx-1-current = <10000>; + + qcom,cdc-static-supplies = "cdc-vdd-buck", + "cdc-buck-sido", + "cdc-vdd-tx-h", + "cdc-vdd-rx-h", + "cdc-vddpx-1"; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; + + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-dmic-sample-rate = <4800000>; + + qcom,wdsp-cmpnt-dev-name = "tavil_codec"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-audio.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-audio.dtsi new file mode 100644 index 000000000000..b45f8372189a --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-audio.dtsi @@ -0,0 +1,55 @@ +/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdx-audio-lpass.dtsi" + +&soc { + snd_934x: sound-tavil { + compatible = "qcom,sdx-asoc-snd-tavil"; + qcom,model = "sdx-tavil-i2s-snd-card"; + qcom,prim_mi2s_aux_master = <&prim_master>; + qcom,prim_mi2s_aux_slave = <&prim_slave>; + qcom,sec_mi2s_aux_master = <&sec_master>; + qcom,sec_mi2s_aux_slave = <&sec_slave>; + + asoc-platform = <&pcm0>, <&pcm1>, <&voip>, <&voice>, + <&loopback>, <&hostless>, <&afe>, <&routing>, + <&pcm_dtmf>, <&host_pcm>, <&compress>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-voip-dsp", "msm-pcm-voice", + "msm-pcm-loopback", "msm-pcm-hostless", + "msm-pcm-afe", "msm-pcm-routing", + "msm-pcm-dtmf", "msm-voice-host-pcm", + "msm-compress-dsp"; + asoc-cpu = <&dai_pri_auxpcm>, <&mi2s_prim>, <&mi2s_sec>, + <&dtmf_tx>, + <&rx_capture_tx>, <&rx_playback_rx>, + <&tx_capture_tx>, <&tx_playback_rx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_sec_auxpcm>; + asoc-cpu-names = "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-stub-dev.4", "msm-dai-stub-dev.5", + "msm-dai-stub-dev.6", "msm-dai-stub-dev.7", + "msm-dai-stub-dev.8", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-auxpcm.2"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-blsp.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-blsp.dtsi new file mode 100644 index 000000000000..9c1070bbbcc8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-blsp.dtsi @@ -0,0 +1,572 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "sdxprairie-pinctrl.dtsi" + +/ { + aliases { + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + i2c5 = &i2c_5; + i2c6 = &i2c_6; + i2c7 = &i2c_7; + spi1 = &spi_1; + spi2 = &spi_2; + spi3 = &spi_3; + spi4 = &spi_4; + }; +}; + + +&soc { + dma_blsp1: qcom,sps-dma@804000 { /* BLSP1 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0x804000 0x23000>; + interrupts = <0 58 0>; + qcom,summing-threshold = <0x10>; + }; + + i2c_1: i2c@835000 { /* BLSP1 QUP1: GPIO: 2,3 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x835000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 31 0>; + dmas = <&dma_blsp1 8 64 0x20000020 0x20>, + <&dma_blsp1 9 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_1_active>; + pinctrl-1 = <&i2c_1_sleep>; + status = "disabled"; + }; + + i2c_2: i2c@836000 { /* BLSP1 QUP2: GPIO: 6,7 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x836000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 32 0>; + dmas = <&dma_blsp1 10 64 0x20000020 0x20>, + <&dma_blsp1 11 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_2_active>; + pinctrl-1 = <&i2c_2_sleep>; + status = "disabled"; + }; + + i2c_3: i2c@837000 { /* BLSP1 QUP3: GPIO: 10,11 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x837000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 33 0>; + dmas = <&dma_blsp1 12 64 0x20000020 0x20>, + <&dma_blsp1 13 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_3_active>; + pinctrl-1 = <&i2c_3_sleep>; + }; + + i2c_4: i2c@838000 { /* BLSP1 QUP4: GPIO: 78,79 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x838000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 34 0>; + dmas = <&dma_blsp1 14 64 0x20000020 0x20>, + <&dma_blsp1 15 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_4_active>; + pinctrl-1 = <&i2c_4_sleep>; + status = "disabled"; + }; + + i2c_5: i2c@835000 { /* BLSP1 QUP1: GPIO: 82,83 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x835000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 31 0>; + dmas = <&dma_blsp1 8 64 0x20000020 0x20>, + <&dma_blsp1 9 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_5_active>; + pinctrl-1 = <&i2c_5_sleep>; + status = "disabled"; + }; + + i2c_6: i2c@836000 { /* BLSP1 QUP2: GPIO: 65,66 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x836000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 32 0>; + dmas = <&dma_blsp1 10 64 0x20000020 0x20>, + <&dma_blsp1 11 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_6_active>; + pinctrl-1 = <&i2c_6_sleep>; + status = "disabled"; + }; + + i2c_7: i2c@838000 { /* BLSP1 QUP4: GPIO: 18,19 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x838000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 34 0>; + dmas = <&dma_blsp1 14 64 0x20000020 0x20>, + <&dma_blsp1 15 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_7_active>; + pinctrl-1 = <&i2c_7_sleep>; + status = "disabled"; + }; + + spi_1: spi@835000 { /* BLSP1 QUP1: GPIO: 80,81,82,83 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x835000 0x600>, + <0x804000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 31 0>, <0 58 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <8>; + qcom,bam-producer-pipe-index = <9>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_1_active>; + pinctrl-1 = <&spi_1_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_2: spi@836000 { /* BLSP1 QUP2: GPIO: 4,5,6,7 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x836000 0x600>, + <0x804000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 32 0>, <0 58 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <10>; + qcom,bam-producer-pipe-index = <11>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_2_active>; + pinctrl-1 = <&spi_2_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_3: spi@837000 { /* BLSP1 QUP3: GPIO: 8,9,10,11 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x837000 0x600>, + <0x804000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 33 0>, <0 58 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <12>; + qcom,bam-producer-pipe-index = <13>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_3_active>; + pinctrl-1 = <&spi_3_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_4: spi@838000 { /* BLSP1 QUP4: GPIO: 16,17,18,19 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x838000 0x600>, + <0x804000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 34 0>, <0 58 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <14>; + qcom,bam-producer-pipe-index = <15>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_4_active>; + pinctrl-1 = <&spi_4_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; + status = "disabled"; + }; + + blsp1_uart1a_hs: uarta@82f000 { /* BLSP1 UART1: GPIO: 0,1,2,3 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x82f000 0x200>, + <0x804000 0x23000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart1a_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 24 0 + 1 &intc 0 58 0 + 2 &tlmm 1 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc GCC_BLSP1_UART1_APPS_CLK>, + <&clock_gcc GCC_BLSP1_AHB_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart1a_tx_sleep>, + <&blsp1_uart1a_rxcts_sleep>, <&blsp1_uart1a_rfr_sleep>; + pinctrl-1 = <&blsp1_uart1a_tx_active>, + <&blsp1_uart1a_rxcts_active>, <&blsp1_uart1a_rfr_active>; + + qcom,msm-bus,name = "buart1a"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp1_uart1b_hs: uartb@82f000 { /* BLSP1 UART1: GPIO: 20,21,22,23 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x82f000 0x200>, + <0x804000 0x23000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart1b_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 24 0 + 1 &intc 0 58 0 + 2 &tlmm 21 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc GCC_BLSP1_UART1_APPS_CLK>, + <&clock_gcc GCC_BLSP1_AHB_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart1b_tx_sleep>, + <&blsp1_uart1b_rxcts_sleep>, <&blsp1_uart1b_rfr_sleep>; + pinctrl-1 = <&blsp1_uart1b_tx_active>, + <&blsp1_uart1b_rxcts_active>, <&blsp1_uart1b_rfr_active>; + + qcom,msm-bus,name = "buart1b"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp1_uart2a_hs: uarta@830000 { /* BLSP1 UART2 : GPIO: 4,5,6,7 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x830000 0x200>, + <0x804000 0x23000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart2a_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 25 0 + 1 &intc 0 58 0 + 2 &tlmm 5 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <2>; + qcom,bam-rx-ep-pipe-index = <3>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, + <&clock_gcc GCC_BLSP1_AHB_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart2a_tx_sleep>, + <&blsp1_uart2a_rxcts_sleep>, <&blsp1_uart2a_rfr_sleep>; + pinctrl-1 = <&blsp1_uart2b_tx_active>, + <&blsp1_uart2b_rxcts_active>, <&blsp1_uart2b_rfr_active>; + + qcom,msm-bus,name = "buart2a"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp1_uart2b_hs: uartb@830000 { /* BLSP1 UART2 : GPIO: 63,64,65,66 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x830000 0x200>, + <0x804000 0x23000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart2b_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 25 0 + 1 &intc 0 58 0 + 2 &tlmm 64 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <2>; + qcom,bam-rx-ep-pipe-index = <3>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, + <&clock_gcc GCC_BLSP1_AHB_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart2b_tx_sleep>, + <&blsp1_uart2b_rxcts_sleep>, <&blsp1_uart2b_rfr_sleep>; + pinctrl-1 = <&blsp1_uart2b_tx_active>, + <&blsp1_uart2b_rxcts_active>, <&blsp1_uart2b_rfr_active>; + + qcom,msm-bus,name = "buart2b"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp1_uart3_hs: uart@831000 { /* BLSP1 UART3: GPIO: 8,9,10,11 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x831000 0x200>, + <0x804000 0x23000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart3_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 26 0 + 1 &intc 0 58 0 + 2 &tlmm 9 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <4>; + qcom,bam-rx-ep-pipe-index = <5>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc GCC_BLSP1_UART3_APPS_CLK>, + <&clock_gcc GCC_BLSP1_AHB_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart3_tx_sleep>, + <&blsp1_uart3_rxcts_sleep>, <&blsp1_uart3_rfr_sleep>; + pinctrl-1 = <&blsp1_uart3_tx_active>, + <&blsp1_uart3_rxcts_active>, <&blsp1_uart3_rfr_active>; + + qcom,msm-bus,name = "buart3"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp1_uart4a_hs: uarta@832000 { /* BLSP1 UART4 : GPIO: 20,21,22,23 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x832000 0x200>, + <0x804000 0x23000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart4a_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 27 0 + 1 &intc 0 58 0 + 2 &tlmm 21 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <6>; + qcom,bam-rx-ep-pipe-index = <7>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc GCC_BLSP1_UART4_APPS_CLK>, + <&clock_gcc GCC_BLSP1_AHB_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart4a_tx_active>, + <&blsp1_uart4a_rxcts_sleep>, <&blsp1_uart4a_rfr_sleep>; + pinctrl-1 = <&blsp1_uart4a_tx_active>, + <&blsp1_uart4a_rxcts_active>, <&blsp1_uart4a_rfr_active>; + + qcom,msm-bus,name = "buart4a"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp1_uart4b_hs: uartb@832000 { /* BLSP1 UART4 : GPIO: 16,17,18,19 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0x832000 0x200>, + <0x804000 0x23000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart4b_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 27 0 + 1 &intc 0 58 0 + 2 &tlmm 17 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <6>; + qcom,bam-rx-ep-pipe-index = <7>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc GCC_BLSP1_UART4_APPS_CLK>, + <&clock_gcc GCC_BLSP1_AHB_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart4b_tx_sleep>, + <&blsp1_uart4b_rxcts_sleep>, <&blsp1_uart4b_rfr_sleep>; + pinctrl-1 = <&blsp1_uart4b_tx_active>, + <&blsp1_uart4b_rxcts_active>, <&blsp1_uart4b_rfr_active>; + + qcom,msm-bus,name = "buart4b"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-bus.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-bus.dtsi new file mode 100644 index 000000000000..5f4308c0e216 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-bus.dtsi @@ -0,0 +1,958 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + ad_hoc_bus: ad-hoc-bus { + compatible = "qcom,msm-bus-device"; + reg = <0x1100000 0x400000>, + <0x1100000 0x400000>, + <0x1620000 0x400000>, + <0x1620000 0x400000>; + + reg-names = "mc_virt-base", "mem_noc-base", + "system_noc-base", "ipa_virt-base"; + + mbox-names = "apps_rsc"; + mboxes = <&apps_rsc 0>; + + /*RSCs*/ + rsc_apps: rsc-apps { + cell-id = ; + label = "apps_rsc"; + qcom,rsc-dev; + qcom,req-state = <2>; + }; + + /*BCMs*/ + bcm_mc0: bcm-mc0 { + cell-id = ; + label = "MC0"; + qcom,bcm-name = "MC0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sh0: bcm-sh0 { + cell-id = ; + label = "SH0"; + qcom,bcm-name = "SH0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_ce0: bcm-ce0 { + cell-id = ; + label = "CE0"; + qcom,bcm-name = "CE0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_ip0: bcm-ip0 { + cell-id = ; + label = "IP0"; + qcom,bcm-name = "IP0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_pn0: bcm-pn0 { + cell-id = ; + label = "PN0"; + qcom,bcm-name = "PN0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_qp0: bcm-qp0 { + cell-id = ; + label = "QP0"; + qcom,bcm-name = "QP0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sh3: bcm-sh3 { + cell-id = ; + label = "SH3"; + qcom,bcm-name = "SH3"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sh4: bcm-sh4 { + cell-id = ; + label = "SH4"; + qcom,bcm-name = "SH4"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn0: bcm-sn0 { + cell-id = ; + label = "SN0"; + qcom,bcm-name = "SN0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn1: bcm-sn1 { + cell-id = ; + label = "SN1"; + qcom,bcm-name = "SN1"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_pn1: bcm-pn1 { + cell-id = ; + label = "PN1"; + qcom,bcm-name = "PN1"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_pn2: bcm-pn2 { + cell-id = ; + label = "PN2"; + qcom,bcm-name = "PN2"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn3: bcm-sn3 { + cell-id = ; + label = "SN3"; + qcom,bcm-name = "SN3"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_pn3: bcm-pn3 { + cell-id = ; + label = "PN3"; + qcom,bcm-name = "PN3"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn4: bcm-sn4 { + cell-id = ; + label = "SN4"; + qcom,bcm-name = "SN4"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_pn5: bcm-pn5 { + cell-id = ; + label = "PN5"; + qcom,bcm-name = "PN5"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn6: bcm-sn6 { + cell-id = ; + label = "SN6"; + qcom,bcm-name = "SN6"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn7: bcm-sn7 { + cell-id = ; + label = "SN7"; + qcom,bcm-name = "SN7"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn8: bcm-sn8 { + cell-id = ; + label = "SN8"; + qcom,bcm-name = "SN8"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn9: bcm-sn9 { + cell-id = ; + label = "SN9"; + qcom,bcm-name = "SN9"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn10: bcm-sn10 { + cell-id = ; + label = "SN10"; + qcom,bcm-name = "SN10"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn11: bcm-sn11 { + cell-id = ; + label = "SN11"; + qcom,bcm-name = "SN11"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + + /*Buses*/ + fab_ipa_virt: fab-ipa_virt{ + cell-id = ; + label = "fab-ipa_virt"; + qcom,fab-dev; + qcom,base-name = "ipa_virt-base"; + qcom,qos-off = <0>; + qcom,base-offset = <0>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + clocks = <>; + }; + + fab_mc_virt: fab-mc_virt{ + cell-id = ; + label = "fab-mc_virt"; + qcom,fab-dev; + qcom,base-name = "mc_virt-base"; + qcom,qos-off = <0>; + qcom,base-offset = <0>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + clocks = <>; + }; + + fab_mem_noc: fab-mem_noc{ + cell-id = ; + label = "fab-mem_noc"; + qcom,fab-dev; + qcom,base-name = "mem_noc-base"; + qcom,qos-off = <4096>; + qcom,base-offset = <65536>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_system_noc: fab-system_noc{ + cell-id = ; + label = "fab-system_noc"; + qcom,fab-dev; + qcom,base-name = "system_noc-base"; + qcom,qos-off = <4096>; + qcom,base-offset = <49152>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clocks = <>; + }; + + + /*Masters*/ + + mas_ipa_core_master: mas-ipa-core-master { + cell-id = ; + label = "mas-ipa-core-master"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_ipa_core_slave>; + qcom,bus-dev = <&fab_ipa_virt>; + }; + + mas_llcc_mc: mas-llcc-mc { + cell-id = ; + label = "mas-llcc-mc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_ebi>; + qcom,bus-dev = <&fab_mc_virt>; + }; + + mas_acm_tcu: mas-acm-tcu { + cell-id = ; + label = "mas-acm-tcu"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <0>; + qcom,connections = <&slv_qns_llcc + &slv_qns_memnoc_snoc &slv_qns_sys_pcie>; + qcom,bus-dev = <&fab_mem_noc>; + qcom,ap-owned; + qcom,prio = <6>; + }; + + mas_qnm_snoc_gc: mas-qnm-snoc-gc { + cell-id = ; + label = "mas-qnm-snoc-gc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <8>; + qcom,connections = <&slv_qns_llcc>; + qcom,bus-dev = <&fab_mem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + }; + + mas_xm_apps_rdwr: mas-xm-apps-rdwr { + cell-id = ; + label = "mas-xm-apps-rdwr"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,qport = <3>; + qcom,connections = <&slv_qns_llcc + &slv_qns_memnoc_snoc &slv_qns_sys_pcie>; + qcom,bus-dev = <&fab_mem_noc>; + qcom,bcms = <&bcm_sh3>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qhm_audio: mas-qhm-audio { + cell-id = ; + label = "mas-qhm-audio"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_aggre_noc>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn2>; + }; + + mas_qhm_blsp1: mas-qhm-blsp1 { + cell-id = ; + label = "mas-qhm-blsp1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_aggre_noc>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn3>; + }; + + mas_qhm_qdss_bam: mas-qhm-qdss-bam { + cell-id = ; + label = "mas-qhm-qdss-bam"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,qport = <11>; + qcom,connections = <&slv_qhs_snoc_cfg + &slv_qhs_emac_cfg &slv_qhs_usb3 + &slv_qhs_tlmm &slv_qhs_spmi_fetcher + &slv_qhs_qdss_cfg &slv_qhs_pdm + &slv_qns_snoc_memnoc &slv_qhs_tcsr + &slv_qhs_ddrss_cfg &slv_qhs_spmi_vgi_coex + &slv_qhs_qpic &slv_qxs_imem + &slv_qhs_ipa &slv_qhs_usb3_phy + &slv_qhs_aop &slv_qhs_blsp1 + &slv_qhs_sdc1 &slv_qhs_mss_cfg + &slv_qhs_pcie_parf &slv_qhs_ecc_cfg + &slv_qhs_audio &slv_qhs_aoss + &slv_qhs_prng &slv_qhs_crypto0_cfg + &slv_xs_sys_tcu_cfg &slv_qhs_clk_ctl + &slv_qhs_imem_cfg>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn8>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qhm_qpic: mas-qhm-qpic { + cell-id = ; + label = "mas-qhm-qpic"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qhs_aoss + &slv_qhs_ipa &slv_qns_aggre_noc + &slv_qhs_aop &slv_qhs_audio>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn3>; + }; + + mas_qhm_snoc_cfg: mas-qhm-snoc-cfg { + cell-id = ; + label = "mas-qhm-snoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_srvc_snoc>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + mas_qhm_spmi_fetcher1: mas-qhm-spmi-fetcher1 { + cell-id = ; + label = "mas-qhm-spmi-fetcher1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qhs_aoss + &slv_qns_aggre_noc &slv_qhs_aop>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn2>; + }; + + mas_qnm_aggre_noc: mas-qnm-aggre-noc { + cell-id = ; + label = "mas-qnm-aggre-noc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <12>; + qcom,connections = <&slv_xs_pcie + &slv_qhs_snoc_cfg &slv_qhs_sdc1 + &slv_qhs_tlmm &slv_qhs_spmi_fetcher + &slv_qhs_qdss_cfg &slv_qhs_pdm + &slv_qns_snoc_memnoc &slv_qhs_tcsr + &slv_qhs_ddrss_cfg &slv_qhs_spmi_vgi_coex + &slv_xs_qdss_stm &slv_qhs_qpic + &slv_qxs_imem &slv_qhs_ipa + &slv_qhs_usb3_phy &slv_qhs_aop + &slv_qhs_blsp1 &slv_qhs_usb3 + &slv_qhs_mss_cfg &slv_qhs_pcie_parf + &slv_qhs_ecc_cfg &slv_qhs_apss + &slv_qhs_audio &slv_qhs_aoss + &slv_qhs_prng &slv_qhs_crypto0_cfg + &slv_xs_sys_tcu_cfg &slv_qhs_clk_ctl + &slv_qhs_imem_cfg>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn7>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + }; + + mas_qnm_ipa: mas-qnm-ipa { + cell-id = ; + label = "mas-qnm-ipa"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <5>; + qcom,connections = <&slv_qhs_snoc_cfg + &slv_qhs_emac_cfg &slv_qhs_usb3 + &slv_qhs_aoss &slv_qhs_spmi_fetcher + &slv_qhs_qdss_cfg &slv_qhs_pdm + &slv_qns_snoc_memnoc &slv_qhs_tcsr + &slv_qhs_ddrss_cfg &slv_xs_qdss_stm + &slv_qhs_qpic &slv_qxs_imem + &slv_qhs_ipa &slv_qhs_usb3_phy + &slv_qhs_aop &slv_qhs_blsp1 + &slv_qhs_sdc1 &slv_qhs_mss_cfg + &slv_qhs_pcie_parf &slv_qhs_ecc_cfg + &slv_qhs_audio &slv_qhs_tlmm + &slv_qhs_prng &slv_qhs_crypto0_cfg + &slv_qhs_clk_ctl &slv_qhs_imem_cfg>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn11>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qnm_memnoc: mas-qnm-memnoc { + cell-id = ; + label = "mas-qnm-memnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qhs_snoc_cfg + &slv_qhs_emac_cfg &slv_qhs_usb3 + &slv_qhs_tlmm &slv_qhs_spmi_fetcher + &slv_qhs_qdss_cfg &slv_qhs_pdm + &slv_qhs_tcsr &slv_qhs_ddrss_cfg + &slv_qhs_spmi_vgi_coex &slv_xs_qdss_stm + &slv_qhs_qpic &slv_qxs_imem + &slv_qhs_ipa &slv_qhs_usb3_phy + &slv_qhs_aop &slv_qhs_blsp1 + &slv_qhs_sdc1 &slv_qhs_mss_cfg + &slv_qhs_pcie_parf &slv_qhs_ecc_cfg + &slv_qhs_apss &slv_qhs_audio + &slv_qhs_aoss &slv_qhs_prng + &slv_qhs_crypto0_cfg &slv_xs_sys_tcu_cfg + &slv_qhs_clk_ctl &slv_qhs_imem_cfg>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn9>; + }; + + mas_qnm_memnoc_pcie: mas-qnm-memnoc-pcie { + cell-id = ; + label = "mas-qnm-memnoc-pcie"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_xs_pcie>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn10>; + }; + + mas_qxm_crypto: mas-qxm-crypto { + cell-id = ; + label = "mas-qxm-crypto"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <1>; + qcom,connections = <&slv_qhs_aoss + &slv_qns_aggre_noc &slv_qhs_aop>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_ce0>, <&bcm_pn5>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_xm_emac: mas-xm-emac { + cell-id = ; + label = "mas-xm-emac"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <7>; + qcom,connections = <&slv_qns_aggre_noc>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn7>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_xm_ipa2pcie_slv: mas-xm-ipa2pcie-slv { + cell-id = ; + label = "mas-xm-ipa2pcie-slv"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <6>; + qcom,connections = <&slv_xs_pcie>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn11>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_xm_pcie: mas-xm-pcie { + cell-id = ; + label = "mas-xm-pcie"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <2>; + qcom,connections = <&slv_qns_aggre_noc>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn7>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + }; + + mas_xm_qdss_etr: mas-xm-qdss-etr { + cell-id = ; + label = "mas-xm-qdss-etr"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <3>; + qcom,connections = <&slv_qhs_snoc_cfg + &slv_qhs_emac_cfg &slv_qhs_usb3 + &slv_qhs_tlmm &slv_qhs_spmi_fetcher + &slv_qhs_qdss_cfg &slv_qhs_pdm + &slv_qns_snoc_memnoc &slv_qhs_tcsr + &slv_qhs_ddrss_cfg &slv_qhs_spmi_vgi_coex + &slv_qhs_qpic &slv_qxs_imem + &slv_qhs_ipa &slv_qhs_usb3_phy + &slv_qhs_aop &slv_qhs_blsp1 + &slv_qhs_sdc1 &slv_qhs_mss_cfg + &slv_qhs_pcie_parf &slv_qhs_ecc_cfg + &slv_qhs_audio &slv_qhs_aoss + &slv_qhs_prng &slv_qhs_crypto0_cfg + &slv_xs_sys_tcu_cfg &slv_qhs_clk_ctl + &slv_qhs_imem_cfg>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn8>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_xm_sdc1: mas-xm-sdc1 { + cell-id = ; + label = "mas-xm-sdc1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <8>; + qcom,connections = <&slv_qhs_aoss + &slv_qhs_ipa &slv_qns_aggre_noc + &slv_qhs_aop &slv_qhs_audio>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn1>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_xm_usb3: mas-xm-usb3 { + cell-id = ; + label = "mas-xm-usb3"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <4>; + qcom,connections = <&slv_qns_aggre_noc>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn7>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + /*Internal nodes*/ + + /*Slaves*/ + + slv_ipa_core_slave:slv-ipa-core-slave { + cell-id = ; + label = "slv-ipa-core-slave"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_ipa_virt>; + qcom,bcms = <&bcm_ip0>; + }; + + slv_ebi:slv-ebi { + cell-id = ; + label = "slv-ebi"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_mc_virt>; + qcom,bcms = <&bcm_mc0>; + }; + + slv_qns_llcc:slv-qns-llcc { + cell-id = ; + label = "slv-qns-llcc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_mem_noc>; + qcom,connections = <&mas_llcc_mc>; + qcom,bcms = <&bcm_sh0>; + }; + + slv_qns_memnoc_snoc:slv-qns-memnoc-snoc { + cell-id = ; + label = "slv-qns-memnoc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_mem_noc>; + qcom,connections = <&mas_qnm_memnoc>; + qcom,bcms = <&bcm_sh4>; + }; + + slv_qns_sys_pcie:slv-qns-sys-pcie { + cell-id = ; + label = "slv-qns-sys-pcie"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_mem_noc>; + qcom,connections = <&mas_qnm_memnoc_pcie>; + qcom,bcms = <&bcm_sh4>; + }; + + slv_qhs_aop:slv-qhs-aop { + cell-id = ; + label = "slv-qhs-aop"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_aoss:slv-qhs-aoss { + cell-id = ; + label = "slv-qhs-aoss"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_apss:slv-qhs-apss { + cell-id = ; + label = "slv-qhs-apss"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_audio:slv-qhs-audio { + cell-id = ; + label = "slv-qhs-audio"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_blsp1:slv-qhs-blsp1 { + cell-id = ; + label = "slv-qhs-blsp1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_clk_ctl:slv-qhs-clk-ctl { + cell-id = ; + label = "slv-qhs-clk-ctl"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_crypto0_cfg:slv-qhs-crypto0-cfg { + cell-id = ; + label = "slv-qhs-crypto0-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_ddrss_cfg:slv-qhs-ddrss-cfg { + cell-id = ; + label = "slv-qhs-ddrss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_ecc_cfg:slv-qhs-ecc-cfg { + cell-id = ; + label = "slv-qhs-ecc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_emac_cfg:slv-qhs-emac-cfg { + cell-id = ; + label = "slv-qhs-emac-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_imem_cfg:slv-qhs-imem-cfg { + cell-id = ; + label = "slv-qhs-imem-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_ipa:slv-qhs-ipa { + cell-id = ; + label = "slv-qhs-ipa"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_mss_cfg:slv-qhs-mss-cfg { + cell-id = ; + label = "slv-qhs-mss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_pcie_parf:slv-qhs-pcie-parf { + cell-id = ; + label = "slv-qhs-pcie-parf"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_pdm:slv-qhs-pdm { + cell-id = ; + label = "slv-qhs-pdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_prng:slv-qhs-prng { + cell-id = ; + label = "slv-qhs-prng"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_qdss_cfg:slv-qhs-qdss-cfg { + cell-id = ; + label = "slv-qhs-qdss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_qpic:slv-qhs-qpic { + cell-id = ; + label = "slv-qhs-qpic"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_sdc1:slv-qhs-sdc1 { + cell-id = ; + label = "slv-qhs-sdc1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_snoc_cfg:slv-qhs-snoc-cfg { + cell-id = ; + label = "slv-qhs-snoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,connections = <&mas_qhm_snoc_cfg>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_spmi_fetcher:slv-qhs-spmi-fetcher { + cell-id = ; + label = "slv-qhs-spmi-fetcher"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_spmi_vgi_coex:slv-qhs-spmi-vgi-coex { + cell-id = ; + label = "slv-qhs-spmi-vgi-coex"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_tcsr:slv-qhs-tcsr { + cell-id = ; + label = "slv-qhs-tcsr"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_tlmm:slv-qhs-tlmm { + cell-id = ; + label = "slv-qhs-tlmm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_usb3:slv-qhs-usb3 { + cell-id = ; + label = "slv-qhs-usb3"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qhs_usb3_phy:slv-qhs-usb3-phy { + cell-id = ; + label = "slv-qhs-usb3-phy"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_qns_aggre_noc:slv-qns-aggre-noc { + cell-id = ; + label = "slv-qns-aggre-noc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,connections = <&mas_qnm_aggre_noc>; + qcom,bcms = <&bcm_sn7>; + }; + + slv_qns_snoc_memnoc:slv-qns-snoc-memnoc { + cell-id = ; + label = "slv-qns-snoc-memnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,connections = <&mas_qnm_snoc_gc>; + qcom,bcms = <&bcm_sn0>; + }; + + slv_qxs_imem:slv-qxs-imem { + cell-id = ; + label = "slv-qxs-imem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn1>; + }; + + slv_srvc_snoc:slv-srvc-snoc { + cell-id = ; + label = "slv-srvc-snoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_pn0>; + }; + + slv_xs_pcie:slv-xs-pcie { + cell-id = ; + label = "slv-xs-pcie"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn6>; + }; + + slv_xs_qdss_stm:slv-xs-qdss-stm { + cell-id = ; + label = "slv-xs-qdss-stm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn3>; + }; + + slv_xs_sys_tcu_cfg:slv-xs-sys-tcu-cfg { + cell-id = ; + label = "slv-xs-sys-tcu-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn4>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/qcom/sdxprairie-cdp-256.dts b/arch/arm/boot/dts/qcom/sdxprairie-cdp-256.dts new file mode 100644 index 000000000000..56030239dbd6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-cdp-256.dts @@ -0,0 +1,31 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdxprairie.dtsi" +#include "sdxprairie-cdp-256.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXPRAIRIE CDP(256MB)"; + compatible = "qcom,sdxprairie-cdp", + "qcom,sdxprairie", "qcom,cdp"; + qcom,board-id = <0x10001 0x0>; +}; + +&qnand_1 { + status = "ok"; +}; + +&blsp1_uart2b_hs { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-cdp-256.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-cdp-256.dtsi new file mode 100644 index 000000000000..8b9bd064b91b --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-cdp-256.dtsi @@ -0,0 +1,182 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdxprairie-pmic-overlay.dtsi" +#include "sdxprairie-cdp-audio-overlay.dtsi" + +&pmxprairie_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm1 { + reg = ; + label = "pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm2 { + reg = ; + label = "pa_therm2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + sdx_case_therm { + reg = ; + label = "sdx_case_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + ambient_therm { + reg = ; + label = "ambient_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pmxprairie_adc_tm_iio { + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm2 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + sdx_case_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + ambient_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150b_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + chg_sbux { + reg = ; + label = "chg_sbux"; + qcom,pre-scaling = <1 3>; + }; + + mid_chg_div6 { + reg = ; + label = "chg_mid"; + qcom,pre-scaling = <1 6>; + }; + + usb_in_i_uv { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + usb_in_v_div_16 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; +}; + +&pm8150b_adc_tm { + status = "disabled"; +}; + +&thermal_zones { + xo-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmxprairie_adc_tm_iio ADC_XO_THERM_PU2>; + thermal-governor = "user_space"; + }; + + pa-therm1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmxprairie_adc_tm_iio ADC_AMUX_THM1_PU2>; + thermal-governor = "user_space"; + }; + + pa-therm2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmxprairie_adc_tm_iio ADC_AMUX_THM2_PU2>; + thermal-governor = "user_space"; + }; + + sdx-case-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmxprairie_adc_tm_iio ADC_AMUX_THM3_PU2>; + thermal-governor = "user_space"; + }; + + ambient-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmxprairie_adc_tm_iio ADC_GPIO1_PU2>; + thermal-governor = "user_space"; + }; +}; + +&soc { + bluetooth: bt_qca6390 { + compatible = "qca,qca6390"; + qca,bt-reset-gpio = <&pmxprairie_gpios 6 0>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-cdp-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-cdp-audio-overlay.dtsi new file mode 100644 index 000000000000..21156fb4759f --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-cdp-audio-overlay.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdxprairie-audio-overlay.dtsi" + +&soc { + sound-tavil { + qcom,wsa-max-devs = <1>; + qcom,wsa-devs = <&wsa881x_0214>; + qcom,wsa-aux-dev-prefix = "SpkrRight"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-cdp-cpe.dts b/arch/arm/boot/dts/qcom/sdxprairie-cdp-cpe.dts new file mode 100644 index 000000000000..3db0c8850552 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-cdp-cpe.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdxprairie-cdp-cpe.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXPRAIRIE CDP (CPE)"; + compatible = "qcom,sdxprairie-cdp", + "qcom,sdxprairie", "qcom,cdp"; + qcom,board-id = <0x5010001 0x0>; +}; + + diff --git a/arch/arm/boot/dts/qcom/sdxprairie-cdp-cpe.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-cdp-cpe.dtsi new file mode 100644 index 000000000000..2a33ad562530 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-cdp-cpe.dtsi @@ -0,0 +1,22 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdxprairie.dtsi" +#include "sdxprairie-cdp.dtsi" + +&qnand_1 { + status = "ok"; +}; + +&wsa881x_0214 { + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs404-iot-sku6.dts b/arch/arm/boot/dts/qcom/sdxprairie-cdp.dts similarity index 60% rename from arch/arm64/boot/dts/qcom/qcs404-iot-sku6.dts rename to arch/arm/boot/dts/qcom/sdxprairie-cdp.dts index 6aa3024878b9..795a7f2ec99c 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-iot-sku6.dts +++ b/arch/arm/boot/dts/qcom/sdxprairie-cdp.dts @@ -1,5 +1,4 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -13,17 +12,20 @@ /dts-v1/; -#include "qcs404.dtsi" -#include "qcs404-csra1-audio-overlay.dtsi" -#include "qcs405-circular-pca9956.dtsi" +#include "sdxprairie.dtsi" +#include "sdxprairie-cdp.dtsi" / { - model = "Qualcomm Technologies, Inc. QCS404 QCS404 1 CSRA"; - compatible = "qcom,qcs404-iot", "qcom,qcs404", "qcom,iot"; - qcom,board-id = <0x020020 0x4>; - + model = "Qualcomm Technologies, Inc. SDXPRAIRIE CDP"; + compatible = "qcom,sdxprairie-cdp", + "qcom,sdxprairie", "qcom,cdp"; + qcom,board-id = <0x4010001 0x0>; }; &qnand_1 { status = "ok"; }; + +&blsp1_uart2b_hs { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-cdp.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-cdp.dtsi new file mode 100644 index 000000000000..21ea5898bc58 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-cdp.dtsi @@ -0,0 +1,213 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdxprairie-pmic-overlay.dtsi" +#include "sdxprairie-cdp-audio-overlay.dtsi" + +&pmxprairie_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm1 { + reg = ; + label = "pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm2 { + reg = ; + label = "pa_therm2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + sdx_case_therm { + reg = ; + label = "sdx_case_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + ambient_therm { + reg = ; + label = "ambient_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pmxprairie_adc_tm_iio { + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm2 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + sdx_case_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + ambient_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150b_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + chg_sbux { + reg = ; + label = "chg_sbux"; + qcom,pre-scaling = <1 3>; + }; + + mid_chg_div6 { + reg = ; + label = "chg_mid"; + qcom,pre-scaling = <1 6>; + }; + + usb_in_i_uv { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + usb_in_v_div_16 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; +}; + +&pm8150b_adc_tm { + status = "disabled"; +}; + +&thermal_zones { + xo-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmxprairie_adc_tm_iio ADC_XO_THERM_PU2>; + thermal-governor = "user_space"; + }; + + pa-therm1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmxprairie_adc_tm_iio ADC_AMUX_THM1_PU2>; + thermal-governor = "user_space"; + }; + + pa-therm2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmxprairie_adc_tm_iio ADC_AMUX_THM2_PU2>; + thermal-governor = "user_space"; + }; + + sdx-case-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmxprairie_adc_tm_iio ADC_AMUX_THM3_PU2>; + thermal-governor = "user_space"; + }; + + ambient-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmxprairie_adc_tm_iio ADC_GPIO1_PU2>; + thermal-governor = "user_space"; + }; +}; + +&soc { + bluetooth: bt_qca6390 { + compatible = "qca,qca6390"; + qca,bt-reset-gpio = <&pmxprairie_gpios 6 0>; + }; +}; + +&pm8150b_charger { + qcom,batteryless-platform; + io-channels = <&pm8150b_vadc ADC_USB_IN_V_16>, + <&pm8150b_vadc ADC_USB_IN_I>, + <&pm8150b_vadc ADC_CHG_TEMP>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp"; +}; + +&sdhc_1 { + vdd-supply = <&vreg_sd_vdd>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&vreg_vddpx_2>; + qcom,vdd-io-voltage-level = <1800000 2850000>; + qcom,vdd-io-current-level = <0 10000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_cd_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_cd_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 + 200000000>; + qcom,devfreq,freq-table = <50000000 200000000>; + + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-coresight.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-coresight.dtsi new file mode 100644 index 000000000000..049fad807e9c --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-coresight.dtsi @@ -0,0 +1,1283 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + csr: csr@6001000 { + compatible = "qcom,coresight-csr"; + reg = <0x6001000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-csr"; + qcom,usb-bam-support; + qcom,hwctrl-set-support; + qcom,set-byte-cntr-support; + + qcom,blk-size = <1>; + }; + + replicator_qdss: replicator@6046000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b909>; + + reg = <0x6046000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-qdss"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_qdss_out_tmc_etr: endpoint { + remote-endpoint= + <&tmc_etr_in_replicator_qdss>; + }; + }; + + port@1 { + reg = <1>; + replicator_qdss_out_tpiu: endpoint { + remote-endpoint= + <&tpiu_in_replicator_qdss>; + }; + }; + + port@2 { + reg = <0>; + replicator_qdss_in_replicator_swao: endpoint { + slave-mode; + remote-endpoint= + <&replicator_swao_out_replicator_qdss>; + }; + }; + }; + }; + + replicator_swao: replicator@6b0a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b909>; + + reg = <0x6b0a000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-swao"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_swao_out_replicator_qdss: endpoint { + remote-endpoint = + <&replicator_qdss_in_replicator_swao>; + }; + }; + + /* Always have EUD before funnel leading to ETR. If both + * sink are active we need to give preference to EUD + * over ETR + */ + port@1 { + reg = <1>; + replicator_swao_out_eud: endpoint { + remote-endpoint = + <&eud_in_replicator_swao>; + }; + }; + + port@2 { + reg = <0>; + replicator_swao_in_tmc_etf: endpoint { + slave-mode; + remote-endpoint = + <&tmc_etf_out_replicator_swao>; + }; + }; + + }; + }; + + tmc_etf: tmc@6b09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb961>; + + reg = <0x6b09000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etf"; + coresight-csr = <&swao_csr>; + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tmc_etf_out_replicator_swao: endpoint { + remote-endpoint= + <&replicator_swao_in_tmc_etf>; + }; + }; + + port@1 { + reg = <0>; + tmc_etf_in_funnel_swao: endpoint { + slave-mode; + remote-endpoint= + <&funnel_swao_out_tmc_etf>; + }; + }; + }; + }; + + tmc_etr: tmc@6048000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + + reg = <0x6048000 0x1000>, + <0x6064000 0x15000>; + reg-names = "tmc-base", "bam-base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + arm,buffer-size = <0x400000>; + + coresight-name = "coresight-tmc-etr"; + coresight-ctis = <&cti0 &cti0>; + coresight-csr = <&csr>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + port { + tmc_etr_in_replicator_qdss: endpoint { + slave-mode; + remote-endpoint = + <&replicator_qdss_out_tmc_etr>; + }; + }; + }; + + funnel_merg: funnel@6045000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6045000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-merg"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_merg_out_funnel_swao: endpoint { + remote-endpoint = + <&funnel_swao_in_funnel_merg>; + }; + }; + + port@1 { + reg = <0>; + funnel_merg_in_funnel_in0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in0_out_funnel_merg>; + }; + }; + + port@2 { + reg = <1>; + funnel_merg_in_funnel_in1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in1_out_funnel_merg>; + }; + }; + }; + }; + + funnel_swao: funnel@6b08000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6b08000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-swao"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_swao_out_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_in_funnel_swao>; + }; + }; + + port@1 { + reg = <6>; + funnel_swao_in_tpda_swao: endpoint { + slave-mode; + remote-endpoint = + <&tpda_swao_out_funnel_swao>; + }; + }; + port@2 { + reg = <7>; + funnel_swao_in_funnel_merg: endpoint { + slave-mode; + remote-endpoint = + <&funnel_merg_out_funnel_swao>; + }; + }; + }; + }; + + funnel_qdss_qatb: funnel@6005000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6005000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-qdss-qatb"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_qdss_qatb_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_qdss_qatb>; + }; + }; + + port@1 { + reg = <0>; + funnel_qdss_qatb_in_tpda_qdss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_qdss_out_funnel_qdss_qatb>; + }; + }; + }; + }; + + tpda_qdss: tpda@6004000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6004000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-qdss"; + + qcom,tpda-atid = <65>; + qcom,dsb-elem-size = <14 32>; + qcom,cmb-elem-size = <0 64>, + <12 32>, + <13 32>, + <14 32>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_qdss_out_funnel_qdss_qatb: endpoint { + remote-endpoint = + <&funnel_qdss_qatb_in_tpda_qdss>; + }; + + }; + + port@1 { + reg = <0>; + tpda_qdss_in_funnel_ddr_qatb: endpoint { + slave-mode; + remote-endpoint = + <&funnel_ddr_qatb_out_tpda_qdss>; + }; + }; + + port@2 { + reg = <12>; + tpda_qdss_in_tpdm_vsense: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_vsense_out_tpda_qdss>; + }; + }; + + port@3 { + reg = <13>; + tpda_qdss_in_tpdm_dcc: endpoint { + slave-mode; + emote-endpoint = + <&tpdm_dcc_out_tpda_qdss>; + }; + }; + + port@4 { + reg = <14>; + tpda_qdss_in_tpdm_top: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_top_out_tpda_qdss>; + }; + }; + }; + }; + + stm: stm@6002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b962>; + + reg = <0x6002000 0x1000>, + <0x16280000 0x180000>, + <0x7820f0 0x4>; + reg-names = "stm-base", "stm-stimulus-base", "stm-debug-status"; + + coresight-name = "coresight-stm"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + stm_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_stm>; + }; + }; + + }; + + swao_csr: csr@6b0e000 { + compatible = "qcom,coresight-csr"; + reg = <0x6b0e000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-swao-csr"; + qcom,timestamp-support; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,blk-size = <1>; + }; + + funnel_in0: funnel@6041000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6041000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in0_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in0>; + }; + }; + + port@1 { + reg = <6>; + funnel_in0_in_funnel_qdss_qatb: endpoint { + slave-mode; + remote-endpoint = + <&funnel_qdss_qatb_out_funnel_in0>; + }; + }; + + port@2 { + reg = <7>; + funnel_in0_in_stm: endpoint { + slave-mode; + remote-endpoint = + <&stm_out_funnel_in0>; + }; + }; + }; + }; + + funnel_in1: funnel@6042000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6042000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in1_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in1>; + }; + }; + port@1 { + reg = <0>; + funnel_in1_in_etm0: endpoint { + slave-mode; + remote-endpoint = + <&etm0_out_funnel_in1>; + }; + }; + port@2 { + reg = <2>; + funnel_in1_in_funnel_modem_dl: endpoint { + slave-mode; + remote-endpoint = + <&funnel_modem_dl_out_funnel_in1>; + }; + }; + }; + }; + + funnel_modem_dl: funnel@6804000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6804000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-modem-dl"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_modem_dl_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_modem_dl>; + }; + }; + port@1 { + reg = <0>; + funnel_modem_dl_in_tpda_modem: endpoint { + slave-mode; + remote-endpoint = + <&tpda_modem_out_funnel_modem_dl>; + }; + }; + port@2 { + reg = <1>; + funnel_modem_dl_in_modem_etm1: endpoint { + slave-mode; + remote-endpoint = + <&modem_etm1_out_funnel_modem_dl>; + }; + }; + port@3 { + reg = <3>; + funnel_modem_dl_in_funnel_scal_dup: endpoint { + slave-mode; + remote-endpoint = + <&funnel_scal_dup_out_funnel_modem_dl>; + }; + }; + }; + }; + + funnel_scal: funnel@680c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x680c000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-modem-q6"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_scal_out_funnel_scal_dup: endpoint { + remote-endpoint = + <&funnel_scal_dup_in_funnel_scal>; + }; + }; + port@1 { + reg = <0>; + funnel_scal_in_modem_etm0: endpoint { + slave-mode; + remote-endpoint = + <&modem_etm0_out_funnel_scal>; + }; + }; + }; + }; + + funnel_scal_dup: funnel@680a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x680a000 0x1>, + <0x680c000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + + coresight-name = "coresight-funnel-modem-duplicate"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + qcom,duplicate-funnel; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_scal_dup_out_funnel_modem_dl: endpoint { + remote-endpoint = + <&funnel_modem_dl_in_funnel_scal_dup>; + }; + }; + port@1 { + reg = <1>; + funnel_scal_dup_in_funnel_scal: endpoint { + slave-mode; + remote-endpoint = + <&funnel_scal_out_funnel_scal_dup>; + }; + }; + }; + }; + + + funnel_ddr_qatb: funnel@69e2000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x69e2000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-ddr-qatb"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ddr_qatb_out_tpda_qdss: endpoint { + remote-endpoint = + <&tpda_qdss_in_funnel_ddr_qatb>; + }; + }; + port@1 { + reg = <0>; + funnel_ddr_qatb_in_tpdm_ddr: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_ddr_out_funnel_ddr_qatb>; + }; + }; + }; + }; + + tpda_swao: tpda@6b01000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6b01000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-swao"; + + qcom,tpda-atid = <71>; + qcom,dsb-elem-size = <1 32>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_swao_out_funnel_swao: endpoint { + remote-endpoint = + <&funnel_swao_in_tpda_swao>; + }; + }; + + port@1 { + reg = <0>; + tpda_swao_in_tpdm_swao0: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_swao0_out_tpda_swao>; + }; + }; + port@2 { + reg = <1>; + tpda_swao_in_tpdm_swao1: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_swao1_out_tpda_swao>; + }; + }; + }; + }; + + tpda_modem: tpda@6803000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6803000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-modem"; + + qcom,tpda-atid = <67>; + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_modem_out_funnel_modem_dl: endpoint { + remote-endpoint = + <&funnel_modem_dl_in_tpda_modem>; + }; + }; + + port@1 { + reg = <0>; + tpda_modem_in_tpdm_modem_0: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_modem_0_out_tpda_modem>; + }; + }; + }; + }; + + tpdm_modem_0: tpdm@6800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6800000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-modem-0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_modem_0_out_tpda_modem: endpoint { + remote-endpoint = <&tpda_modem_in_tpdm_modem_0>; + }; + }; + }; + + tpdm_swao0: tpdm@6b02000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + + reg = <0x6b02000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_swao0_out_tpda_swao: endpoint { + remote-endpoint = <&tpda_swao_in_tpdm_swao0>; + }; + }; + }; + + tpdm_swao1: tpdm@6b03000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6b03000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name="coresight-tpdm-swao-1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_swao1_out_tpda_swao: endpoint { + remote-endpoint = <&tpda_swao_in_tpdm_swao1>; + }; + }; + }; + + tpdm_ddr: tpdm@69e0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x069e0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_ddr_out_funnel_ddr_qatb: endpoint { + remote-endpoint = + <&funnel_ddr_qatb_in_tpdm_ddr>; + }; + }; + }; + + tpdm_vsense: tpdm@6840000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6840000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-vsense"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port{ + tpdm_vsense_out_tpda_qdss: endpoint { + remote-endpoint = <&tpda_qdss_in_tpdm_vsense>; + }; + }; + }; + + + tpdm_dcc: tpdm@6870000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6870000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dcc"; + qcom,hw-enable-check; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port{ + tpdm_dcc_out_tpda_qdss: endpoint { + remote-endpoint = <&tpda_qdss_in_tpdm_dcc>; + }; + }; + }; + + + tpdm_top: tpdm@6c28000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6c28000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-top"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port{ + tpdm_top_out_tpda_qdss: endpoint { + remote-endpoint = <&tpda_qdss_in_tpdm_top>; + }; + }; + }; + + etm0: etm@7002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b956>; + + reg = <0x7002000 0x1000>; + cpu = <&CPU0>; + + coresight-name = "coresight-etm0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm0_out_funnel_in1: endpoint { + remote-endpoint = <&funnel_in1_in_etm0>; + }; + }; + }; + + cti0_ddr0: cti@69e1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x69e1000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_0_cti_0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_ddr1: cti@69e4000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x69e4000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_1_cti_0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_ddr1: cti@69e5000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x69e5000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_1_cti_1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti2_ddr1: cti@69e6000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x69e6000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_1_cti_2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0: cti@6010000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6010000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti1: cti@6011000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6011000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti2: cti@6012000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6012000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti3: cti@6013000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6013000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti3"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti4: cti@6014000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6014000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti4"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti5: cti@6015000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6015000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti5"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti6: cti@6016000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6016000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti6"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti7: cti@6017000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6017000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti7"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti8: cti@6018000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6018000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti8"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti9: cti@6019000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6019000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti9"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti10: cti@601a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti10"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti11: cti@601b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti11"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti12: cti@601c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti12"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti13: cti@601d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601d000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti13"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti14: cti@601e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601e000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti14"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti15: cti@601f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601f000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti15"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti_cpu0: cti@7003000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7003000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu0"; + cpu = <&CPU0>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + ipcb_tgu: tgu@6b0c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb999>; + reg = <0x06b0c000 0x1000>; + reg-names = "tgu-base"; + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <4>; + tgu-timer-counters = <8>; + + coresight-name = "coresight-tgu-ipcb"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_swao:cti@6b04000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b04000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_swao:cti@6b05000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b05000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti2_swao:cti@6b06000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b06000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti3_swao:cti@6b07000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b07000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti3"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + dummy_eud: dummy_sink { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-eud"; + + qcom,dummy-sink; + port { + eud_in_replicator_swao: endpoint { + slave-mode; + remote-endpoint = + <&replicator_swao_out_eud>; + }; + }; + }; + + dummy_tpiu: dummy_sink { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-tpiu"; + + qcom,dummy-sink; + port { + tpiu_in_replicator_qdss: endpoint { + slave-mode; + remote-endpoint = + <&replicator_qdss_out_tpiu>; + }; + }; + }; + + modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem-etm0"; + qcom,inst-id = <2>; + + port { + modem_etm0_out_funnel_scal: endpoint { + remote-endpoint = + <&funnel_scal_in_modem_etm0>; + }; + }; + }; + + + modem_etm1 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem-etm1"; + qcom,inst-id = <2>; + + port { + modem_etm1_out_funnel_modem_dl: endpoint { + remote-endpoint = + <&funnel_modem_dl_in_modem_etm1>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-dsda-cdp.dts b/arch/arm/boot/dts/qcom/sdxprairie-dsda-cdp.dts new file mode 100644 index 000000000000..cdb3f1b638e0 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-dsda-cdp.dts @@ -0,0 +1,56 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdxprairie.dtsi" +#include "sdxprairie-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXPRAIRIE CDP"; + compatible = "qcom,sdxprairie-cdp", + "qcom,sdxprairie", "qcom,cdp"; + qcom,board-id = <0x6010001 0x0>; +}; + +/* delete pm8150b nodes */ +&soc { + /delete-node/ thermal-zones; +}; + +&usb { + extcon = <&vbus_detect>; +}; + +&spmi_bus { + /delete-node/ qpnp,fg; + /delete-node/ bcl@1d00; + /delete-node/ qcom,usb-pdphy@1700; + /delete-node/ qcom,qpnp-smb5; + /delete-node/ adc_tm@3500; + /delete-node/ vadc@3100; + /delete-node/ qcom,pm8150b@2; + /delete-node/ qcom,pm8150b@3; +}; + +&qnand_1 { + status = "ok"; +}; + +&blsp1_uart2b_hs { + status = "okay"; +}; + +&vbus_detect { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/qcom/sdxprairie-dsda-mtp.dts b/arch/arm/boot/dts/qcom/sdxprairie-dsda-mtp.dts new file mode 100644 index 000000000000..5470356cfbe8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-dsda-mtp.dts @@ -0,0 +1,56 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdxprairie.dtsi" +#include "sdxprairie-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXPRAIRIE MTP(DSDA)"; + compatible = "qcom,sdxprairie-mtp", + "qcom,sdxprairie", "qcom,mtp"; + qcom,board-id = <8 8>, <8 0x108>; +}; + +/* delete pm8150b nodes */ +&soc { + /delete-node/ thermal-zones; +}; + +&usb { + extcon = <&vbus_detect>; +}; + +&spmi_bus { + /delete-node/ qpnp,fg; + /delete-node/ bcl@1d00; + /delete-node/ qcom,usb-pdphy@1700; + /delete-node/ qcom,qpnp-smb5; + /delete-node/ adc_tm@3500; + /delete-node/ vadc@3100; + /delete-node/ qcom,pm8150b@2; + /delete-node/ qcom,pm8150b@3; +}; + +&qnand_1 { + status = "ok"; +}; + +&blsp1_uart2b_hs { + status = "okay"; +}; + +&vbus_detect { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/qcom/sdxprairie-gdsc.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-gdsc.dtsi new file mode 100644 index 000000000000..d4f00fd03ae9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-gdsc.dtsi @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + /* GDSCs in Global CC */ + gdsc_usb30: qcom,gdsc@10b004 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_usb30"; + reg = <0x10b004 0x4>; + status = "disabled"; + }; + + gdsc_emac: qcom,gdsc@147004 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_emac"; + reg = <0x147004 0x4>; + status = "disabled"; + }; + + gdsc_pcie: qcom,gdsc@137004 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_pcie"; + reg = <0x137004 0x4>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-ion.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-ion.dtsi new file mode 100644 index 000000000000..89b2c452bc38 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-ion.dtsi @@ -0,0 +1,41 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = <25>; + qcom,ion-heap-type = "SYSTEM"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = <27>; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@19 { /* QSEECOM TA HEAP */ + reg = <19>; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@28 { /* AUDIO HEAP */ + reg = <28>; + memory-region = <&audio_mem>; + qcom,ion-heap-type = "DMA"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-mtp-256.dts b/arch/arm/boot/dts/qcom/sdxprairie-mtp-256.dts new file mode 100644 index 000000000000..c679f5cc27f2 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-mtp-256.dts @@ -0,0 +1,31 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdxprairie.dtsi" +#include "sdxprairie-mtp-256.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXPRAIRIE MTP(256MB)"; + compatible = "qcom,sdxprairie-mtp", + "qcom,sdxprairie", "qcom,mtp"; + qcom,board-id = <0x10008 0x0>; +}; + +&qnand_1 { + status = "ok"; +}; + +&blsp1_uart2b_hs { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-mtp-256.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-mtp-256.dtsi new file mode 100644 index 000000000000..858051621fe3 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-mtp-256.dtsi @@ -0,0 +1,224 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdxprairie-pmic-overlay.dtsi" +#include "sdxprairie-mtp-audio-overlay.dtsi" + +&pmxprairie_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm1 { + reg = ; + label = "pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm2 { + reg = ; + label = "pa_therm2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + sdx_case_therm { + reg = ; + label = "sdx_case_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + ambient_therm { + reg = ; + label = "ambient_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pmxprairie_adc_tm_iio { + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm2 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + sdx_case_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + ambient_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150b_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + chg_sbux { + reg = ; + label = "chg_sbux"; + qcom,pre-scaling = <1 3>; + }; + + mid_chg_div6 { + reg = ; + label = "chg_mid"; + qcom,pre-scaling = <1 6>; + }; + + usb_in_i_uv { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + usb_in_v_div_16 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; +}; + +&pm8150b_adc_tm { + status = "disabled"; +}; + +&thermal_zones { + xo-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmxprairie_adc_tm_iio ADC_XO_THERM_PU2>; + thermal-governor = "user_space"; + }; + + pa-therm1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmxprairie_adc_tm_iio ADC_AMUX_THM1_PU2>; + thermal-governor = "user_space"; + }; + + pa-therm2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmxprairie_adc_tm_iio ADC_AMUX_THM2_PU2>; + thermal-governor = "user_space"; + }; + + sdx-case-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmxprairie_adc_tm_iio ADC_AMUX_THM3_PU2>; + thermal-governor = "user_space"; + }; + + ambient-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmxprairie_adc_tm_iio ADC_GPIO1_PU2>; + thermal-governor = "user_space"; + }; +}; + +&soc { + sdxprairie_mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "fg-gen4-batterydata-alium-3600mah.dtsi" + }; +}; + +&soc { + bluetooth: bt_qca6390 { + compatible = "qca,qca6390"; + qca,bt-reset-gpio = <&pmxprairie_gpios 6 0>; + }; +}; + +&pm8150b_charger { + qcom,sec-charger-config = <0>; + qcom,auto-recharge-soc = <98>; + io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>, + <&pm8150b_vadc ADC_USB_IN_I>, + <&pm8150b_vadc ADC_SBUx>, + <&pm8150b_vadc ADC_VPH_PWR>, + <&pm8150b_vadc ADC_CHG_TEMP>, + <&pm8150b_vadc ADC_USB_IN_V_16>; + io-channel-names = "mid_voltage", + "usb_in_current", + "sbux_res", + "vph_voltage", + "chg_temp", + "usb_in_voltage"; + qcom,battery-data = <&sdxprairie_mtp_batterydata>; + qcom,step-charging-enable; + qcom,wd-bark-time-secs = <16>; + qcom,suspend-input-on-debug-batt; +}; + +&pm8150b_fg { + qcom,battery-data = <&sdxprairie_mtp_batterydata>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,five-pin-battery; + /* ESR fast calibration */ + qcom,fg-esr-timer-chg-fast = <0 7>; + qcom,fg-esr-timer-dischg-fast = <0 7>; + qcom,fg-esr-timer-chg-slow = <0 96>; + qcom,fg-esr-timer-dischg-slow = <0 96>; + qcom,fg-esr-cal-soc-thresh = <26 230>; + qcom,fg-esr-cal-temp-thresh = <10 40>; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-mtp-aqc.dts b/arch/arm/boot/dts/qcom/sdxprairie-mtp-aqc.dts new file mode 100644 index 000000000000..5faa08d48608 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-mtp-aqc.dts @@ -0,0 +1,31 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdxprairie.dtsi" +#include "sdxprairie-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXPRAIRIE MTP(AQC)"; + compatible = "qcom,sdxprairie-mtp", + "qcom,sdxprairie", "qcom,mtp"; + qcom,board-id = <0x1010008 0x0>; +}; + +&qnand_1 { + status = "ok"; +}; + +&blsp1_uart2b_hs { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-mtp-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-mtp-audio-overlay.dtsi new file mode 100644 index 000000000000..72eeea9b4696 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-mtp-audio-overlay.dtsi @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdxprairie-audio-overlay.dtsi" + +&soc { + sound-tavil { + qcom,wsa-max-devs = <1>; + qcom,wsa-devs = <&wsa881x_0214>; + qcom,wsa-aux-dev-prefix = "SpkrRight"; + }; +}; + diff --git a/arch/arm/boot/dts/qcom/sdxprairie-mtp-cpe.dts b/arch/arm/boot/dts/qcom/sdxprairie-mtp-cpe.dts new file mode 100644 index 000000000000..94f1729753eb --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-mtp-cpe.dts @@ -0,0 +1,55 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdxprairie-mtp-cpe.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXPRAIRIE MTP (CPE)"; + compatible = "qcom,sdxprairie-mtp", + "qcom,sdxprairie", "qcom,mtp"; + qcom,board-id = <0x7010008 0x0>; +}; + +/* delete pm8150b nodes */ +&soc { + /delete-node/ thermal-zones; +}; + +&usb { + extcon = <&vbus_detect>; +}; + +&spmi_bus { + /delete-node/ qpnp,fg; + /delete-node/ bcl@1d00; + /delete-node/ qcom,usb-pdphy@1700; + /delete-node/ qcom,qpnp-smb5; + /delete-node/ adc_tm@3500; + /delete-node/ vadc@3100; + /delete-node/ qcom,pm8150b@2; + /delete-node/ qcom,pm8150b@3; +}; + +&qnand_1 { + status = "ok"; +}; + +&blsp1_uart2b_hs { + status = "okay"; +}; + +&vbus_detect { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/qcom/sdxprairie-mtp-cpe.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-mtp-cpe.dtsi new file mode 100644 index 000000000000..007fd6c7faee --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-mtp-cpe.dtsi @@ -0,0 +1,18 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdxprairie.dtsi" +#include "sdxprairie-mtp.dtsi" + +&qnand_1 { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-mtp.dts b/arch/arm/boot/dts/qcom/sdxprairie-mtp.dts new file mode 100644 index 000000000000..9c2a429c2775 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-mtp.dts @@ -0,0 +1,31 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdxprairie.dtsi" +#include "sdxprairie-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXPRAIRIE MTP"; + compatible = "qcom,sdxprairie-mtp", + "qcom,sdxprairie", "qcom,mtp"; + qcom,board-id = <0x5010008 0x0>; +}; + +&qnand_1 { + status = "ok"; +}; + +&blsp1_uart2b_hs { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-mtp.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-mtp.dtsi new file mode 100644 index 000000000000..ea15b58ac8ca --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-mtp.dtsi @@ -0,0 +1,245 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdxprairie-pmic-overlay.dtsi" +#include "sdxprairie-mtp-audio-overlay.dtsi" + +&pmxprairie_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm1 { + reg = ; + label = "pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm2 { + reg = ; + label = "pa_therm2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + sdx_case_therm { + reg = ; + label = "sdx_case_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + ambient_therm { + reg = ; + label = "ambient_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pmxprairie_adc_tm_iio { + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm2 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + sdx_case_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + ambient_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150b_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + chg_sbux { + reg = ; + label = "chg_sbux"; + qcom,pre-scaling = <1 3>; + }; + + mid_chg_div6 { + reg = ; + label = "chg_mid"; + qcom,pre-scaling = <1 6>; + }; + + usb_in_i_uv { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + usb_in_v_div_16 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; +}; + +&pm8150b_adc_tm { + status = "disabled"; +}; + +&thermal_zones { + xo-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmxprairie_adc_tm_iio ADC_XO_THERM_PU2>; + thermal-governor = "user_space"; + }; + + pa-therm1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmxprairie_adc_tm_iio ADC_AMUX_THM1_PU2>; + thermal-governor = "user_space"; + }; + + pa-therm2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmxprairie_adc_tm_iio ADC_AMUX_THM2_PU2>; + thermal-governor = "user_space"; + }; + + sdx-case-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmxprairie_adc_tm_iio ADC_AMUX_THM3_PU2>; + thermal-governor = "user_space"; + }; + + ambient-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmxprairie_adc_tm_iio ADC_GPIO1_PU2>; + thermal-governor = "user_space"; + }; +}; + +&soc { + sdxprairie_mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "fg-gen4-batterydata-alium-3600mah.dtsi" + }; +}; + +&soc { + bluetooth: bt_qca6390 { + compatible = "qca,qca6390"; + qca,bt-reset-gpio = <&pmxprairie_gpios 6 0>; + }; +}; + +&pm8150b_charger { + qcom,sec-charger-config = <0>; + qcom,auto-recharge-soc = <98>; + io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>, + <&pm8150b_vadc ADC_USB_IN_I>, + <&pm8150b_vadc ADC_SBUx>, + <&pm8150b_vadc ADC_VPH_PWR>, + <&pm8150b_vadc ADC_CHG_TEMP>, + <&pm8150b_vadc ADC_USB_IN_V_16>; + io-channel-names = "mid_voltage", + "usb_in_current", + "sbux_res", + "vph_voltage", + "chg_temp", + "usb_in_voltage"; + qcom,battery-data = <&sdxprairie_mtp_batterydata>; + qcom,step-charging-enable; + qcom,wd-bark-time-secs = <16>; + qcom,suspend-input-on-debug-batt; +}; + +&pm8150b_fg { + qcom,battery-data = <&sdxprairie_mtp_batterydata>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,five-pin-battery; + /* ESR fast calibration */ + qcom,fg-esr-timer-chg-fast = <0 7>; + qcom,fg-esr-timer-dischg-fast = <0 7>; + qcom,fg-esr-timer-chg-slow = <0 96>; + qcom,fg-esr-timer-dischg-slow = <0 96>; + qcom,fg-esr-cal-soc-thresh = <26 230>; + qcom,fg-esr-cal-temp-thresh = <10 40>; +}; + +&sdhc_1 { + vdd-supply = <&vreg_sd_vdd>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&vreg_vddpx_2>; + qcom,vdd-io-voltage-level = <1800000 2850000>; + qcom,vdd-io-current-level = <0 10000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_cd_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_cd_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 + 200000000>; + qcom,devfreq,freq-table = <50000000 200000000>; + + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dts b/arch/arm/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dts new file mode 100644 index 000000000000..8071be5a1df1 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdxprairie-pcie-ep-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXPRAIRIE PCIE-EP MTP"; + compatible = "qcom,sdxprairie-mtp", + "qcom,sdxprairie", "qcom,mtp"; + qcom,board-id = <0x6010008 0x0>; +}; + + diff --git a/arch/arm/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dtsi new file mode 100644 index 000000000000..f0dfb1eb9a01 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dtsi @@ -0,0 +1,42 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdxprairie.dtsi" +#include "sdxprairie-mtp.dtsi" + +&qnand_1 { + status = "ok"; +}; + +&restart_pshold { + qcom,force-warm-reboot; +}; + +&cnss_qca6390 { + status = "disabled"; +}; + +&ipa_hw { + qcom,use-ipa-in-mhi-mode; +}; + +&pcie0 { + status = "disabled"; +}; + +&pcie_ep { + status = "ok"; +}; + +&mhi_device { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-pcie.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-pcie.dtsi new file mode 100644 index 000000000000..cbf9791f1011 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-pcie.dtsi @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + pcie0: qcom,pcie@1c00000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x1c00000 0x4000>, + <0x1c06000 0x2000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>; + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc 0 140 0 + 0 0 0 1 &intc 0 141 0 + 0 0 0 2 &intc 0 142 0 + 0 0 0 3 &intc 0 143 0 + 0 0 0 4 &intc 0 144 0>; + + qcom,phy-sequence = <0x1240 0x03 0x0 + 0x1010 0x00 0x0 + 0x101c 0x31 0x0 + 0x1020 0x01 0x0 + 0x1024 0xce 0x0 + 0x1028 0x0b 0x0 + 0x1030 0x97 0x0 + 0x1034 0x0c 0x0 + 0x1044 0x18 0x0 + 0x1048 0x90 0x0 + 0x1058 0x0f 0x0 + 0x1074 0x06 0x0 + 0x1078 0x06 0x0 + 0x107c 0x16 0x0 + 0x1080 0x16 0x0 + 0x1084 0x36 0x0 + 0x1088 0x36 0x0 + 0x1094 0x08 0x0 + 0x10a4 0x46 0x0 + 0x10a8 0x04 0x0 + 0x10ac 0x04 0x0 + 0x10b0 0x0d 0x0 + 0x10b4 0x0a 0x0 + 0x10b8 0x1a 0x0 + 0x10bc 0xc3 0x0 + 0x10c4 0xd0 0x0 + 0x10d4 0x05 0x0 + 0x10d8 0x55 0x0 + 0x10dc 0x55 0x0 + 0x10e0 0x05 0x0 + 0x110c 0x02 0x0 + 0x1154 0x34 0x0 + 0x1158 0x12 0x0 + 0x115c 0x00 0x0 + 0x1168 0x05 0x0 + 0x116c 0x04 0x0 + 0x119c 0x88 0x0 + 0x11a0 0x03 0x0 + 0x11ac 0xca 0x0 + 0x11b0 0x1e 0x0 + 0x11b4 0xd8 0x0 + 0x11b8 0x20 0x0 + 0x11bc 0x22 0x0 + 0x106c 0x0a 0x0 + 0x1070 0x10 0x0 + 0x11a4 0x05 0x0 + 0x11a8 0x0f 0x0 + 0x008c 0x06 0x0 + 0x00e0 0x01 0x0 + 0x00c4 0x01 0x0 + 0x0258 0x16 0x0 + 0x0378 0x83 0x0 + 0x0360 0xe2 0x0 + 0x0364 0x04 0x0 + 0x0368 0x30 0x0 + 0x0370 0xff 0x0 + 0x03cc 0x42 0x0 + 0x03d0 0x0d 0x0 + 0x03d4 0x77 0x0 + 0x03d8 0x2d 0x0 + 0x03dc 0x39 0x0 + 0x03e0 0x9f 0x0 + 0x03e4 0x0f 0x0 + 0x03e8 0x63 0x0 + 0x03ec 0xbf 0x0 + 0x03f0 0x79 0x0 + 0x03f4 0x4f 0x0 + 0x03f8 0x0f 0x0 + 0x03fc 0xd5 0x0 + 0x02ac 0x7f 0x0 + 0x0310 0x55 0x0 + 0x0334 0x0c 0x0 + 0x0338 0x00 0x0 + 0x0350 0x0f 0x0 + 0x088c 0x06 0x0 + 0x08e0 0x01 0x0 + 0x08c4 0x01 0x0 + 0x0a58 0x16 0x0 + 0x0b78 0x83 0x0 + 0x0b60 0xe2 0x0 + 0x0b64 0x04 0x0 + 0x0b68 0x30 0x0 + 0x0b70 0xff 0x0 + 0x0bcc 0x42 0x0 + 0x0bd0 0x0d 0x0 + 0x0bd4 0x77 0x0 + 0x0bd8 0x2d 0x0 + 0x0bdc 0x39 0x0 + 0x0be0 0x9f 0x0 + 0x0be4 0x0f 0x0 + 0x0be8 0x63 0x0 + 0x0bec 0xbf 0x0 + 0x0bf0 0x79 0x0 + 0x0bf4 0x4f 0x0 + 0x0bf8 0x0f 0x0 + 0x0bfc 0xd5 0x0 + 0x0aac 0x7f 0x0 + 0x0b10 0x55 0x0 + 0x0b34 0x0c 0x0 + 0x0b38 0x00 0x0 + 0x0b50 0x0f 0x0 + 0x161c 0xc1 0x0 + 0x1690 0x00 0x0 + 0x13e4 0x03 0x0 + 0x1708 0x03 0x0 + 0x16a0 0x16 0x0 + 0x13e0 0x16 0x0 + 0x13d8 0x01 0x0 + 0x16fc 0x01 0x0 + 0x13dc 0x00 0x0 + 0x1700 0x00 0x0 + 0x1828 0x50 0x0 + 0x1c28 0x50 0x0 + 0x1200 0x00 0x0 + 0x1244 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + + perst-gpio = <&tlmm 57 0>; + wake-gpio = <&tlmm 53 0>; + + gdsc-vdd-supply = <&gdsc_pcie>; + vreg-1.8-supply = <&pmxprairie_l1>; + vreg-0.9-supply = <&pmxprairie_l4>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1.8-voltage-level = <1200000 1200000 15000>; + qcom,vreg-0.9-voltage-level = <872000 872000 47900>; + qcom,vreg-cx-voltage-level = ; + + msi-parent = <&pcie0_msi>; + + qcom,no-l0s-supported; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x40000000>; + + qcom,pcie-phy-ver = <0x1096>; + qcom,use-19p2mhz-aux-clk; + qcom,phy-status-offset = <0x1214>; + qcom,phy-status-bit = <7>; + qcom,phy-power-down-offset = <0x1240>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <0>; + + qcom,smmu-sid-base = <0x0200>; + iommu-map = <0x0 &apps_smmu 0x0200 0x1>, + <0x100 &apps_smmu 0x0201 0x1>; + + qcom,msm-bus,name = "pcie0"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 500 800>; + + clocks = <&clock_gcc GCC_PCIE_PIPE_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_PCIE_AUX_CLK>, + <&clock_gcc GCC_PCIE_CFG_AHB_CLK>, + <&clock_gcc GCC_PCIE_MSTR_AXI_CLK>, + <&clock_gcc GCC_PCIE_SLV_AXI_CLK>, + <&clock_gcc GCC_PCIE_0_CLKREF_CLK>, + <&clock_gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&clock_gcc GCC_PCIE_SLEEP_CLK>, + <&clock_gcc GCC_PCIE_RCHNG_PHY_CLK>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", + "pcie_0_sleep_clk", "pcie_phy_refgen_clk"; + + max-clock-frequency-hz = <0>, <0>, <0>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>; + + resets = <&clock_gcc GCC_PCIE_BCR>, + <&clock_gcc GCC_PCIE_PHY_BCR>; + + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + pcie0_rp: pcie0_rp { + reg = <0 0 0 0 0>; + pci-ids = "17cb:010c"; + }; + }; + + pcie0_msi: qcom,pcie0_msi@a0000000 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0xa0000000 0x0>; + interrupt-parent = <&intc>; + interrupts = ; + qcom,snps; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-pinctrl.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-pinctrl.dtsi new file mode 100644 index 000000000000..841e1675dc7a --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-pinctrl.dtsi @@ -0,0 +1,1477 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tlmm: pinctrl@f100000 { + compatible = "qcom,sdxprairie-pinctrl"; + reg = <0xf100000 0x300000>, + <0xb204900 0x280>; + reg-names = "pinctrl", "pdc"; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + interrupt-parent = <&pdc>; + #interrupt-cells = <2>; + + uart3_console_active: uart3_console_active { + mux { + pins = "gpio8", "gpio9"; + function = "blsp_uart3"; + }; + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + + uart3_console_sleep: uart3_console_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "blsp_uart3"; + }; + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* I2C CONFIGURATION */ + i2c_1 { + i2c_1_active: i2c_1_active { + mux { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_1_sleep: i2c_1_sleep { + mux { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_2 { + i2c_2_active: i2c_2_active { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_2_sleep: i2c_2_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_3 { + i2c_3_active: i2c_3_active { + mux { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_3_sleep: i2c_3_sleep { + mux { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_4 { + i2c_4_active: i2c_4_active { + mux { + pins = "gpio78", "gpio79"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio78", "gpio79"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_4_sleep: i2c_4_sleep { + mux { + pins = "gpio78", "gpio79"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio78", "gpio79"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_5 { + i2c_5_active: i2c_5_active { + mux { + pins = "gpio82", "gpio83"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio82", "gpio83"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_5_sleep: i2c_5_sleep { + mux { + pins = "gpio82", "gpio83"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio82", "gpio83"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_6 { + i2c_6_active: i2c_6_active { + mux { + pins = "gpio65", "gpio66"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio65", "gpio66"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_6_sleep: i2c_6_sleep { + mux { + pins = "gpio65", "gpio66"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio65", "gpio66"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_7 { + i2c_7_active: i2c_7_active { + mux { + pins = "gpio18", "gpio19"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_7_sleep: i2c_7_sleep { + mux { + pins = "gpio18", "gpio19"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + /*SPI Configuration*/ + spi_1 { + spi_1_active: spi_1_active { + mux { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + function = "blsp_spi1"; + }; + + config { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_1_sleep: spi_1_sleep { + mux { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + function = "blsp_spi1"; + }; + + config { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_2 { + spi_2_active: spi_2_active { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_2_sleep: spi_2_sleep { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_3 { + spi_3_active: spi_3_active { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_3_sleep: spi_3_sleep { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_4 { + spi_4_active: spi_4_active { + mux { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_4_sleep: spi_4_sleep { + mux { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + wcd9xxx_intr { + wcd_intr_default: wcd_intr_default{ + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + cdc_reset_ctrl { + cdc_reset_sleep: cdc_reset_sleep { + mux { + pins = "gpio92"; + function = "gpio"; + }; + config { + pins = "gpio92"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_reset_active:cdc_reset_active { + mux { + pins = "gpio92"; + function = "gpio"; + }; + config { + pins = "gpio92"; + drive-strength = <8>; + bias-pull-down; + output-high; + }; + }; + }; + + i2s_mclk { + i2s_mclk_sleep: i2s_mclk_sleep { + mux { + pins = "gpio62"; + function = "i2s_mclk"; + }; + + config { + pins = "gpio62"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + i2s_mclk_active: i2s_mclk_active { + mux { + pins = "gpio62"; + function = "i2s_mclk"; + }; + + config { + pins = "gpio62"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + }; + + pmx_pri_mi2s_aux { + pri_ws_sleep: pri_ws_sleep { + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_sck_sleep: pri_sck_sleep { + mux { + pins = "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio15"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_dout_sleep: pri_dout_sleep { + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_ws_active_master: pri_ws_active_master { + mux { + pins = "gpio12"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + pri_sck_active_master: pri_sck_active_master { + mux { + pins = "gpio15"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio15"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + pri_ws_active_slave: pri_ws_active_slave { + mux { + pins = "gpio12"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + pri_sck_active_slave: pri_sck_active_slave { + mux { + pins = "gpio15"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio15"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + pri_dout_active: pri_dout_active { + mux { + pins = "gpio14"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio14"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + }; + + pmx_pri_mi2s_aux_din { + pri_din_sleep: pri_din_sleep { + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_din_active: pri_din_active { + mux { + pins = "gpio13"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio13"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pmx_sec_mi2s_aux { + sec_ws_sleep: sec_ws_sleep { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_sck_sleep: sec_sck_sleep { + mux { + pins = "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_dout_sleep: sec_dout_sleep { + mux { + pins = "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_ws_active_master: sec_ws_active_master { + mux { + pins = "gpio16"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio16"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + sec_sck_active_master: sec_sck_active_master { + mux { + pins = "gpio19"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio19"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + sec_ws_active_slave: sec_ws_active_slave { + mux { + pins = "gpio16"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio16"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + sec_sck_active_slave: sec_sck_active_slave { + mux { + pins = "gpio19"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio19"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + sec_dout_active: sec_dout_active { + mux { + pins = "gpio18"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio18"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + }; + pmx_sec_mi2s_aux_din { + sec_din_sleep: sec_din_sleep { + mux { + pins = "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_din_active: sec_din_active { + mux { + pins = "gpio17"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio17"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + /* HS UART CONFIGURATION */ + + blsp1_uart1a: blsp1_uart1a { + blsp1_uart1a_tx_active: blsp1_uart1a_tx_active { + mux { + pins = "gpio0"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1a_tx_sleep: blsp1_uart1a_tx_sleep { + mux { + pins = "gpio0"; + function = "gpio"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart1a_rxcts_active: blsp1_uart1a_rxcts_active { + mux { + pins = "gpio1", "gpio2"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio1", "gpio2"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1a_rxcts_sleep: blsp1_uart1a_rxcts_sleep { + mux { + pins = "gpio1", "gpio2"; + function = "gpio"; + }; + + config { + pins = "gpio1", "gpio2"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + blsp1_uart1a_rfr_active: blsp1_uart1a_rfr_active { + mux { + pins = "gpio3"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1a_rfr_sleep: blsp1_uart1a_rfr_sleep { + mux { + pins = "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + blsp1_uart1b: blsp1_uart1b { + blsp1_uart1b_tx_active: blsp1_uart1b_tx_active { + mux { + pins = "gpio20"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1b_tx_sleep: blsp1_uart1b_tx_sleep { + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart1b_rxcts_active: blsp1_uart1b_rxcts_active { + mux { + pins = "gpio21", "gpio22"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio21", "gpio22"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1b_rxcts_sleep: blsp1_uart1b_rxcts_sleep { + mux { + pins = "gpio21", "gpio22"; + function = "gpio"; + }; + + config { + pins = "gpio21", "gpio22"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + blsp1_uart1b_rfr_active: blsp1_uart1b_rfr_active { + mux { + pins = "gpio23"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1b_rfr_sleep: blsp1_uart1b_rfr_sleep { + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + blsp1_uart2a: blsp1_uart2a { + blsp1_uart2a_tx_active: blsp1_uart2a_tx_active { + mux { + pins = "gpio4"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2a_tx_sleep: blsp1_uart2a_tx_sleep { + mux { + pins = "gpio4"; + function = "gpio"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart2a_rxcts_active: blsp1_uart2a_rxcts_active { + mux { + pins = "gpio5", "gpio6"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio5", "gpio6"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2a_rxcts_sleep: blsp1_uart2a_rxcts_sleep { + mux { + pins = "gpio5", "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio1", "gpio2"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + blsp1_uart2a_rfr_active: blsp1_uart2a_rfr_active { + mux { + pins = "gpio7"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2a_rfr_sleep: blsp1_uart2a_rfr_sleep { + mux { + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + blsp1_uart2b: blsp1_uart2b { + blsp1_uart2b_tx_active: blsp1_uart2b_tx_active { + mux { + pins = "gpio63"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio63"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2b_tx_sleep: blsp1_uart2b_tx_sleep { + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart2b_rxcts_active: blsp1_uart2b_rxcts_active { + mux { + pins = "gpio64", "gpio65"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio64", "gpio65"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2b_rxcts_sleep: blsp1_uart2b_rxcts_sleep { + mux { + pins = "gpio64", "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio64", "gpio65"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + blsp1_uart2b_rfr_active: blsp1_uart2b_rfr_active { + mux { + pins = "gpio66"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio66"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2b_rfr_sleep: blsp1_uart2b_rfr_sleep { + mux { + pins = "gpio66"; + function = "gpio"; + }; + + config { + pins = "gpio66"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + blsp1_uart3: blsp1_uart3 { + blsp1_uart3_tx_active: blsp1_uart3_tx_active { + mux { + pins = "gpio8"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_tx_sleep: blsp1_uart3_tx_sleep { + mux { + pins = "gpio8"; + function = "gpio"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart3_rxcts_active: blsp1_uart3_rxcts_active { + mux { + pins = "gpio9", "gpio10"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio9", "gpio10"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_rxcts_sleep: blsp1_uart3_rxcts_sleep { + mux { + pins = "gpio9", "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio9", "gpio10"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + blsp1_uart3_rfr_active: blsp1_uart3_rfr_active { + mux { + pins = "gpio11"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_rfr_sleep: blsp1_uart3_rfr_sleep { + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + blsp1_uart4a: blsp1_uart4a { + blsp1_uart4a_tx_active: blsp1_uart4a_tx_active { + mux { + pins = "gpio20"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4a_tx_sleep: blsp1_uart4a_tx_sleep { + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart4a_rxcts_active: blsp1_uart4a_rxcts_active { + mux { + pins = "gpio21", "gpio22"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio21", "gpio22"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4a_rxcts_sleep: blsp1_uart4a_rxcts_sleep { + mux { + pins = "gpio21", "gpio22"; + function = "gpio"; + }; + + config { + pins = "gpio21", "gpio22"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + blsp1_uart4a_rfr_active: blsp1_uart4a_rfr_active { + mux { + pins = "gpio23"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4a_rfr_sleep: blsp1_uart4a_rfr_sleep { + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + blsp1_uart4b: blsp1_uart4b { + blsp1_uart4b_tx_active: blsp1_uart4b_tx_active { + mux { + pins = "gpio16"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4b_tx_sleep: blsp1_uart4b_tx_sleep { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart4b_rxcts_active: blsp1_uart4b_rxcts_active { + mux { + pins = "gpio17", "gpio18"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio17", "gpio18"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4b_rxcts_sleep: blsp1_uart4b_rxcts_sleep { + mux { + pins = "gpio17", "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio17", "gpio18"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + blsp1_uart4b_rfr_active: blsp1_uart4b_rfr_active { + mux { + pins = "gpio19"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4b_rfr_sleep: blsp1_uart4b_rfr_sleep { + mux { + pins = "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + pcie0 { + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio56"; + function = "pcie_clkreq"; + }; + + config { + pins = "gpio56"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio57"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie_ep { + pcie_ep_clkreq_default: pcie_ep_clkreq_default { + mux { + pins = "gpio56"; + function = "pcie_clkreq"; + }; + config { + pins = "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio57"; + function = "gpio"; + }; + config { + pins = "gpio57"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio53"; + function = "gpio"; + }; + config { + pins = "gpio53"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio52"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio52"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + }; + + /* SDC pin type */ + sdc1_clk_on: sdc1_clk_on { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc1_clk_off: sdc1_clk_off { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_cmd_on: sdc1_cmd_on { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_cmd_off: sdc1_cmd_off { + config { + pins = "sdc1_cmd"; + num-grp-pins = <1>; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_data_on: sdc1_data_on { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_data_off: sdc1_data_off { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_cd_on: cd_on { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc1_cd_off: cd_off { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; + bias-disable; + }; + }; + + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-pm.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-pm.dtsi new file mode 100644 index 000000000000..6302cd66ec1d --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-pm.dtsi @@ -0,0 +1,102 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include + +&soc { + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm-cluster@0{ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + label = "system"; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0 { + reg = <0>; + label = "cx_active"; + qcom,psci-mode = <0x0>; + qcom,entry-latency-us = <120>; + qcom,exit-latency-us = <150>; + qcom,min-residency-us = <6488>; + }; + + qcom,pm-cluster-level@1 { + reg = <1>; + label = "cx_min"; + qcom,psci-mode = <0x4>; + qcom,entry-latency-us = <140>; + qcom,exit-latency-us = <200>; + qcom,min-residency-us = <8000>; + qcom,min-child-idx = <2>; + qcom,notify-rpm; + qcom,is-reset; + }; + + qcom,pm-cpu@0 { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,cpu = <&CPU0>; + + qcom,pm-cpu-level@0{ + reg = <0>; + label = "wfi"; + qcom,psci-cpu-mode = <0x1>; + qcom,latency-us = <1>; + qcom,entry-latency-us = <57>; + qcom,exit-latency-us = <43>; + qcom,min-residency-us = <83>; + }; + + qcom,pm-cpu-level@1 { + reg = <1>; + label ="standalone_pc"; + qcom,psci-cpu-mode = <0x4>; + qcom,entry-latency-us = <120>; + qcom,exit-latency-us = <120>; + qcom,min-residency-us = <4488>; + qcom,use-broadcast-timer; + qcom,is-reset; + }; + + qcom,pm-cpu-level@2 { + reg = <2>; + label = "system-pc"; + qcom,psci-cpu-mode = <0x4>; + qcom,entry-latency-us = <120>; + qcom,exit-latency-us = <150>; + qcom,min-residency-us = <6488>; + qcom,use-broadcast-timer; + qcom,is-reset; + }; + }; + }; + }; + + qcom,rpm-stats@c300000 { + compatible = "qcom,rpm-stats"; + reg = <0xC300000 0x1000>, <0xC370004 0x4>; + reg-names = "phys_addr_base", "offset_addr"; + qcom,num-records = <3>; + }; + + qcom,rpmh-master-stats@b211200 { + compatible = "qcom,rpmh-master-stats-v1"; + reg = <0xb211200 0x60>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-pmic-overlay.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-pmic-overlay.dtsi new file mode 100644 index 000000000000..fc9bb5b6f7f3 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-pmic-overlay.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "pmxprairie.dtsi" +#include "pm8150b.dtsi" +#include + +&pm8150b_charger { + dpdm-supply = <&usb2_phy>; + + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; + + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; +}; + +/delete-node/ &pm8150b_hr_led; + +&pm8150b_pdphy { + vdd-pdphy-supply = <&L10E>; + vbus-supply = <&smb5_vbus>; + vconn-supply = <&smb5_vconn>; +}; + +&usb { + extcon = <&pm8150b_pdphy>; +}; + +&pmxprairie_gpios { + vreg_rgmii_off { + vreg_rgmii_off_default: vreg_rgmii_off_default { + pins = "gpio9"; + bias-pull-down; + output-disable; + input-enable; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-regulator.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-regulator.dtsi new file mode 100644 index 000000000000..817bef3db90a --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-regulator.dtsi @@ -0,0 +1,511 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&soc { + /* RPMh regulators */ + + /* PMXPRAIRIE S1 + S6 = VDD_MODEM supply */ + rpmh-regulator-msslvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "mss.lvl"; + VDD_MODEM_LEVEL: S1E_LEVEL: + pmxprairie_s1_level: regulator-pmxprairie-s1-level { + regulator-name = "pmxprairie_s1_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-smpe2 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpe2"; + S2E: pmxprairie_s2: regulator-pmxprairie-s2 { + regulator-name = "pmxprairie_s2"; + qcom,set = ; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1400000>; + qcom,init-voltage = <1224000>; + }; + }; + + rpmh-regulator-smpe3 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpe3"; + S3E: pmxprairie_s3: regulator-pmxprairie-s3 { + regulator-name = "pmxprairie_s3"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + qcom,init-voltage = <800000>; + }; + }; + + rpmh-regulator-smpe4 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpe4"; + S4E: pmxprairie_s4: regulator-pmxprairie-s4 { + regulator-name = "pmxprairie_s4"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1960000>; + qcom,init-voltage = <1800000>; + }; + }; + + /* PMXPRAIRIE S7 = VDD_MX supply */ + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "mx.lvl"; + + VDD_MX_LEVEL: S7E_LEVEL: + pmxprairie_s7_level: regulator-pmxprairie-s7-level { + regulator-name = "pmxprairie_s7_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + + VDD_MX_LEVEL_AO: S7E_LEVEL_AO: pmxprairie_s7_level_ao: + regulator-pmxprairie-s7-level-ao { + regulator-name = "pmxprairie_s7_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + + mx_cdev: mx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&VDD_MX_LEVEL>; + regulator-levels = ; + #cooling-cells = <2>; + }; + }; + + /* PMXPRAIRIE S5 = VDD_CX supply */ + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "cx.lvl"; + pmxprairie_s5_level-parent-supply = <&VDD_MX_LEVEL>; + pmxprairie_s5_level_ao-parent-supply = <&VDD_MX_LEVEL_AO>; + + VDD_CX_LEVEL: S5E_LEVEL: pmxprairie_s5_level: + regulator-pmxprairie-s5-level { + regulator-name = "pmxprairie_s5_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + + VDD_CX_LEVEL_AO: S5E_LEVEL_AO: pmxprairie_s5_level_ao: + regulator-pmxprairie-s5-level-ao { + regulator-name = "pmxprairie_s5_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + + cx_cdev: regulator-cdev { + compatible = "qcom,rpmh-reg-cdev"; + mboxes = <&qmp_aop 0>; + qcom,reg-resource-name = "cx"; + #cooling-cells = <2>; + }; + }; + + rpmh-regulator-ldoe1 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L1E: pmxprairie_l1: regulator-pmxprairie-l1 { + regulator-name = "pmxprairie_l1"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe2 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L2E: pmxprairie_l2: regulator-pmxprairie-l2 { + regulator-name = "pmxprairie_l2"; + qcom,set = ; + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + qcom,init-voltage = <1128000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe3 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L3E: pmxprairie_l3: regulator-pmxprairie-l3 { + regulator-name = "pmxprairie_l3"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe4 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L4E: pmxprairie_l4: regulator-pmxprairie-l4 { + regulator-name = "pmxprairie_l4"; + qcom,set = ; + regulator-min-microvolt = <872000>; + regulator-max-microvolt = <872000>; + qcom,init-voltage = <872000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L5E: pmxprairie_l5: regulator-pmxprairie-l5 { + regulator-name = "pmxprairie_l5"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe6 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L6E: pmxprairie_l6: regulator-pmxprairie-l6 { + regulator-name = "pmxprairie_l6"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe7 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L7E: pmxprairie_l7: regulator-pmxprairie-l7 { + regulator-name = "pmxprairie_l7"; + qcom,set = ; + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <900000>; + qcom,init-voltage = <480000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe8 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe8"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L8E: pmxprairie_l8: regulator-pmxprairie-l8 { + regulator-name = "pmxprairie_l8"; + qcom,set = ; + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <900000>; + qcom,init-voltage = <480000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe9 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L9E: pmxprairie_l9: regulator-pmxprairie-l9 { + regulator-name = "pmxprairie_l9"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe10 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L10E: pmxprairie_l10: regulator-pmxprairie-l10 { + regulator-name = "pmxprairie_l10"; + qcom,set = ; + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + qcom,init-voltage = <3088000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe11 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L11E: pmxprairie_l11: regulator-pmxprairie-l11 { + regulator-name = "pmxprairie_l11"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + qcom,init-voltage = <1704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe12 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L12E: pmxprairie_l12: regulator-pmxprairie-l12 { + regulator-name = "pmxprairie_l12"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe13 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L13E: pmxprairie_l13: regulator-pmxprairie-l13 { + regulator-name = "pmxprairie_l13"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + qcom,init-voltage = <1704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe14 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe14"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L14E: pmxprairie_l14: regulator-pmxprairie-l14 { + regulator-name = "pmxprairie_l14"; + qcom,set = ; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <600000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe15 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe15"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L15E: pmxprairie_l15: regulator-pmxprairie-l15 { + regulator-name = "pmxprairie_l15"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoe16 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoe16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L16E: pmxprairie_l16: regulator-pmxprairie-l16 { + regulator-name = "pmxprairie_l16"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + qcom,init-voltage = <1704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-vrefe2 { + compatible = "qcom,rpmh-xob-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "vrefe2"; + pmxprairie_vref_rgmii: regulator-pmxprairie-rgmii { + regulator-name = "pmxprairie_vref_rgmii"; + qcom,set = ; + }; + }; + + vreg_vddpx_2: vddpx2-gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "vddpx_2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2850000>; + enable-gpio = <&tlmm 98 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + states = <1800000 0>, + <2850000 1>; + startup-delay-us = <200000>; + enable-active-high; + }; + + vreg_sd_vdd: sd-vdd-fixed-regulator { + compatible = "qcom,stub-regulator"; + regulator-name = "sd_vdd"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + parent-supply = <&vreg_vddpx_2>; + }; + + vreg_emac_phy: emac_phy_regulator { + compatible = "regulator-fixed"; + regulator-name = "emac_phy"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <100>; + gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vreg_rgmii_io_pads: rgmii_io_pads_regulator { + compatible = "regulator-fixed"; + regulator-name = "rgmii_io_pads"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-enable-ramp-delay = <100>; + gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-rumi.dts b/arch/arm/boot/dts/qcom/sdxprairie-rumi.dts new file mode 100644 index 000000000000..b944d1950bdb --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-rumi.dts @@ -0,0 +1,31 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdxprairie.dtsi" +#include "sdxprairie-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXPRAIRIE RUMI"; + compatible = "qcom,sdxprairie-rumi", + "qcom,sdxprairie", "qcom,rumi"; + qcom,board-id = <15 0>; +}; + +&qnand_1 { + status = "ok"; +}; + +&blsp1_uart2b_hs { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-rumi.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-rumi.dtsi new file mode 100644 index 000000000000..49158a894440 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-rumi.dtsi @@ -0,0 +1,91 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdxprairie-pmic-overlay.dtsi" + +&soc { + timer { + clock-frequency = <48000>; + }; + + timer@17820000 { + clock-frequency = <48000>; + }; + + usb_emu_phy: usb_emu_phy@a720000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x0a720000 0x9500>, + <0x0a6f8800 0x100>; + reg-names = "base", "qcratch_base"; + + qcom,emu-init-seq = <0xfff0 0x4 + 0xfff3 0x4 + 0x40 0x4 + 0xfff3 0x4 + 0xfff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x1a0 0x20 + 0x100000 0x3c + 0x0 0x3c + 0x10060 0x3c + 0x0 0x4>; + }; +}; + +&clock_rpmh { + compatible = "qcom,dummycc"; + clock-output-names = "rpmh_clocks"; +}; + +&clock_aop { + compatible = "qcom,dummycc"; + clock-output-names = "aop_clocks"; +}; + +&clock_gcc { + compatible = "qcom,dummycc"; + clock-output-names = "gcc_clocks"; +}; + +&clock_debugcc { + compatible = "qcom,dummycc"; + clock-output-names = "dummy_clocks"; +}; + +&ipa_hw { + qcom,ipa-hw-mode = <1>; /* IPA hw type = Virtual */ +}; + +&usb { + /delete-property/ iommus; + /delete-property/ extcon; + dwc3@a600000 { + usb-phy = <&usb_emu_phy>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + }; +}; + +&usb_qmp_phy { + status = "disabled"; +}; + +&usb2_phy { + status = "disabled"; +}; + +&soc { + bluetooth: bt_qca6390 { + compatible = "qca,qca6390"; + qca,bt-reset-gpio = <&pmxprairie_gpios 6 0>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-thermal.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-thermal.dtsi new file mode 100644 index 000000000000..8cee48986a78 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-thermal.dtsi @@ -0,0 +1,428 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + modem { + qcom,instance-id = <0x0>; + + modem_pa: modem_pa { + qcom,qmi-dev-name = "pa"; + #cooling-cells = <2>; + }; + + modem_proc: modem_proc { + qcom,qmi-dev-name = "modem"; + #cooling-cells = <2>; + }; + + modem_current: modem_current { + qcom,qmi-dev-name = "modem_current"; + #cooling-cells = <2>; + }; + + modem_skin: modem_skin { + qcom,qmi-dev-name = "modem_skin"; + #cooling-cells = <2>; + }; + + modem_vdd: modem_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + + }; + + qmi_sensor: qmi-ts-sensors { + compatible = "qcom,qmi-sensors"; + #thermal-sensor-cells = <1>; + + modem { + qcom,instance-id = <0x0>; + qcom,qmi-sensor-names = "pa", + "pa_1", + "qfe_pa0", + "qfe_wtr0"; + }; + }; +}; + +&thermal_zones { + aoss0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 0>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + active-config1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-q6-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 1>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + active-config1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + ipa-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + active-config1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu0-a7-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 3>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + active-config1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-5g-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + active-config1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-vpe-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + active-config1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-core-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + thermal-governor = "user_space"; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + active-config1 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss0-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 0>; + tracks-low; + trips { + aoss0_trip: active-config0 { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&aoss0_trip>; + cooling-device = <&CPU0 1 1>; + }; + modem_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + cx_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + }; + }; + + mdm-q6-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 1>; + tracks-low; + trips { + mdm_q6_trip: active-config0 { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&mdm_q6_trip>; + cooling-device = <&CPU0 1 1>; + }; + modem_vdd_cdev { + trip = <&mdm_q6_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + cx_vdd_cdev { + trip = <&mdm_q6_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&mdm_q6_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + }; + }; + + ipa-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 2>; + tracks-low; + trips { + ipa_trip: active-config0 { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&ipa_trip>; + cooling-device = <&CPU0 1 1>; + }; + modem_vdd_cdev { + trip = <&ipa_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + cx_vdd_cdev { + trip = <&ipa_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&ipa_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + }; + }; + + cpu0-a7-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 3>; + tracks-low; + trips { + cpu0_trip: active-config0 { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&cpu0_trip>; + cooling-device = <&CPU0 1 1>; + }; + modem_vdd_cdev { + trip = <&cpu0_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + cx_vdd_cdev { + trip = <&cpu0_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&cpu0_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + }; + }; + + mdm-5g-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + thermal-governor = "low_limits_floor"; + tracks-low; + trips { + mdm_5g_trip: active-config0 { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&mdm_5g_trip>; + cooling-device = <&CPU0 1 1>; + }; + modem_vdd_cdev { + trip = <&mdm_5g_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + cx_vdd_cdev { + trip = <&mdm_5g_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&mdm_5g_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + }; + }; + + mdm-vpe-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + thermal-governor = "low_limits_floor"; + tracks-low; + trips { + mdm_vpe_trip: active-config0 { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&mdm_vpe_trip>; + cooling-device = <&CPU0 1 1>; + }; + modem_vdd_cdev { + trip = <&mdm_vpe_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + cx_vdd_cdev { + trip = <&mdm_vpe_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&mdm_vpe_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + }; + }; + + mdm-core-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + thermal-governor = "low_limits_floor"; + tracks-low; + trips { + mdm_core_trip: active-config0 { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&CPU0 1 1>; + }; + modem_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + cx_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-usb.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-usb.dtsi new file mode 100644 index 000000000000..a250c6c4fb74 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-usb.dtsi @@ -0,0 +1,285 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&soc { + usb: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a600000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x1a0 0x0>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <0 157 0>, <0 130 0>, <0 158 0>, <0 198 0>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&gdsc_usb30>; + dpdm-supply = <&usb2_phy>; + clocks = <&clock_gcc GCC_USB30_MASTER_CLK>, + <&clock_gcc GCC_USB30_SLV_AHB_CLK>, + <&clock_gcc GCC_USB30_MSTR_AXI_CLK>, + <&clock_gcc GCC_USB30_MOCK_UTMI_CLK>, + <&clock_gcc GCC_USB30_SLEEP_CLK>, + <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&clock_gcc GCC_USB30_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x208 /* GSI_DBL_ADDR_L */ + 0x224 /* GSI_DBL_ADDR_H */ + 0x240 /* GSI_RING_BASE_ADDR_L */ + 0x25c /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + + qcom,msm-bus,name = "usb"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <3>; + qcom,msm-bus,vectors-KBps = + /* suspend vote */ + , + , + , + + /* nominal vote */ + , + , + , + + /* svs vote */ + , + , + ; + + qcom,default-bus-vote = <2>; /* use svs bus voting */ + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0x0a600000 0xcd00>; + interrupts = <0 133 0>; + usb-phy = <&usb2_phy>, <&usb_qmp_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,ssp-u3-u0-quirk; + snps,usb3-u1u2-disable; + snps,bus-suspend-enable; + usb-core-id = <0>; + tx-fifo-resize; + maximum-speed = "super-speed-plus"; + dr_mode = "otg"; + }; + + qcom,usbbam@a704000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa704000 0x17000>; + interrupts = <0 132 0>; + + qcom,usb-bam-fifo-baseaddr = <0x1468b000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + usb2_phy: hsphy@ff4000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0xff4000 0x114>; + reg-names = "hsusb_phy_base"; + + vdd-supply = <&pmxprairie_l4>; + qcom,vdd-voltage-level = <0 872000 872000>; + vdda18-supply = <&pmxprairie_l5>; + vdda33-supply = <&pmxprairie_l10>; + + clocks = <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; + clock-names = "ref_clk_src", "cfg_ahb_clk"; + + resets = <&clock_gcc GCC_QUSB2PHY_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70>; + qcom,no-rext-present; + }; + + usb_qmp_phy: ssphy@ff6000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0xff6000 0x1000>, + <0xff688c 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&pmxprairie_l4>; + qcom,vdd-voltage-level = <0 872000 872000>; + qcom,vdd-max-load-uA = <47900>; + core-supply = <&pmxprairie_l1>; + qcom,core-max-load-uA = <15000>; + qcom,vbus-valid-override; + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + + clocks = <&clock_gcc GCC_USB3_PHY_AUX_CLK>, + <&clock_gcc GCC_USB3_PHY_PIPE_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "cfg_ahb_clk"; + + resets = <&clock_gcc GCC_USB3_PHY_BCR>, + <&clock_gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-v2-cdp.dts b/arch/arm/boot/dts/qcom/sdxprairie-v2-cdp.dts new file mode 100644 index 000000000000..240bd302dff2 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-v2-cdp.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdxprairie-v2.dtsi" +#include "sdxprairie-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXPRAIRIE CDP V2"; + compatible = "qcom,sdxprairie-cdp", + "qcom,sdxprairie", "qcom,cdp"; + qcom,board-id = <0x4010001 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-v2-mtp.dts b/arch/arm/boot/dts/qcom/sdxprairie-v2-mtp.dts new file mode 100644 index 000000000000..1078d3d2b24c --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-v2-mtp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sdxprairie-v2.dtsi" +#include "sdxprairie-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXPRAIRIE MTP V2"; + compatible = "qcom,sdxprairie-mtp", + "qcom,sdxprairie", "qcom,mtp"; + qcom,board-id = <0x5010008 0x0>; +}; + + diff --git a/arch/arm/boot/dts/qcom/sdxprairie-v2.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-v2.dtsi new file mode 100644 index 000000000000..a58b88f7b13d --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-v2.dtsi @@ -0,0 +1,31 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdxprairie.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXPRAIRIE V2"; + compatible = "qcom,sdxprairie"; + qcom,msm-id = <357 0x20000>, <368 0x20000>, <418 0x20000>; +}; + +&qnand_1 { + status = "ok"; +}; + +&blsp1_uart2b_hs { + status = "okay"; +}; + +&clock_gcc { + compatible = "qcom,gcc-sdxprairie-v2", "syscon"; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie-wcd.dtsi b/arch/arm/boot/dts/qcom/sdxprairie-wcd.dtsi new file mode 100644 index 000000000000..5484f9339c0d --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie-wcd.dtsi @@ -0,0 +1,80 @@ +/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&i2c_3 { + tavil_codec { + wcd: wcd_pinctrl@5 { + compatible = "qcom,wcd-pinctrl"; + qcom,num-gpios = <5>; + gpio-controller; + #gpio-cells = <2>; + + spkr_1_wcd_en_active: spkr_1_wcd_en_active { + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + output-high; + }; + }; + + spkr_1_wcd_en_sleep: spkr_1_wcd_en_sleep { + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + input-enable; + }; + }; + + spkr_2_wcd_en_active: spkr_2_sd_n_active { + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + output-high; + }; + }; + + spkr_2_wcd_en_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + input-enable; + }; + }; + }; + + wsa_spkr_wcd_sd1: msm_cdc_pinctrll { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_wcd_en_active>; + pinctrl-1 = <&spkr_1_wcd_en_sleep>; + }; + + wsa_spkr_wcd_sd2: msm_cdc_pinctrlr { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_2_wcd_en_active>; + pinctrl-1 = <&spkr_2_wcd_en_sleep>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdxprairie.dtsi b/arch/arm/boot/dts/qcom/sdxprairie.dtsi new file mode 100644 index 000000000000..9ca2c95b20c8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdxprairie.dtsi @@ -0,0 +1,1519 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include "skeleton.dtsi" +#include +#include +#include +#include +#include +#include +#include +#include + +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} + +/ { + model = "Qualcomm Technologies, Inc. SDXPRAIRIE"; + compatible = "qcom,sdxprairie"; + qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>; + interrupt-parent = <&pdc>; + + aliases { + pci-domain0 = &pcie0; /* PCIe0 domain */ + sdhc1 = &sdhc_1; /* SDC1 eMMC/SD/SDIO slot */ + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mpss_adsp_mem: mpss_adsp_region@90c00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x90c00000 0xd400000>; + label = "mpss_adsp_mem"; + }; + + tz_apps_mem: tz_apps_region@0x90000000 { + no-map; + reg = <0x90000000 0xc00000>; + label = "tz_apps_mem"; + }; + + tz_mem: tz_region@8ff00000 { + no-map; + reg = <0x8ff00000 0x100000>; + label = "tz_mem"; + }; + + smem_mem: smem_region@8fe40000 { + no-map; + reg = <0x8fe40000 0xc0000>; + label = "smem_mem"; + }; + + peripheral2_mem: peripheral2_region@8fd00000 { + no-map; + reg = <0x8fd00000 0x140000>; + label = "peripheral2_mem"; + }; + + secdata_mem: secdata_region@8fcfd000 { + no-map; + reg = <0x8fcfd000 0x1000>; + label = "secdata_mem"; + }; + + ac_db_mem: ac_db_region@8fc80000 { + no-map; + reg = <0x8fc80000 0x40000>; + label = "ac_db_mem"; + }; + + hyp_mem: hyp_region@8fc00000 { + no-map; + reg = <0x8fc00000 0x80000>; + label = "hyp_mem"; + }; + + mpss_debug_mem: mpss_debug_region@8ef00000 { + no-map; + reg = <0x8ef00000 0x800000>; + label = "mpss_debug_mem"; + }; + + qseecom_mem: qseecom_region@0 { + compatible = "shared-dma-pool"; + reusable; + alignment = <0x400000>; + size = <0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region@0 { + compatible = "shared-dma-pool"; + reusable; + alignment = <0x400000>; + size = <0x1000000>; + }; + + audio_mem: audio_region@0 { + compatible = "shared-dma-pool"; + no-map; + size = <0x400000>; + }; + + cnss_wlan_mem: cnss_wlan_region@0 { + compatible = "shared-dma-pool"; + reusable; + size = <0x1400000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x400000>; + }; + }; + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + enable-method = "psci"; + #cooling-cells = <2>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc: soc { }; +}; + +#include "sdxprairie-regulator.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + thermal_zones: thermal-zones { + }; + + intc: interrupt-controller@17800000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <3>; + reg = <0x17800000 0x1000>, + <0x17802000 0x1000>; + }; + + pdc: interrupt-controller@b210000{ + compatible = "qcom,pdc-sdxprairie"; + reg = <0xb210000 0x30000>; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 12 0xf08>, + <1 10 0xf08>, + <1 11 0xf08>; + clock-frequency = <19200000>; + }; + + timer@17820000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17820000 0x1000>; + clock-frequency = <19200000>; + + frame@17821000 { + frame-number = <0>; + interrupts = <0 7 0x4>, + <0 6 0x4>; + reg = <0x17821000 0x1000>, + <0x17822000 0x1000>; + }; + + frame@17823000 { + frame-number = <1>; + interrupts = <0 8 0x4>; + reg = <0x17823000 0x1000>; + status = "disabled"; + }; + + frame@17824000 { + frame-number = <2>; + interrupts = <0 9 0x4>; + reg = <0x17824000 0x1000>; + status = "disabled"; + }; + + frame@17825000 { + frame-number = <3>; + interrupts = <0 10 0x4>; + reg = <0x17825000 0x1000>; + status = "disabled"; + }; + + frame@17826000 { + frame-number = <4>; + interrupts = <0 11 0x4>; + reg = <0x17826000 0x1000>; + status = "disabled"; + }; + + frame@17827000 { + frame-number = <5>; + interrupts = <0 12 0x4>; + reg = <0x17827000 0x1000>; + status = "disabled"; + }; + + frame@17828000 { + frame-number = <6>; + interrupts = <0 13 0x4>; + reg = <0x17828000 0x1000>; + status = "disabled"; + }; + + frame@17829000 { + frame-number = <7>; + interrupts = <0 14 0x4>; + reg = <0x17829000 0x1000>; + status = "disabled"; + }; + }; + + qcom,mpm2-sleep-counter@c221000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xc221000 0x1000>; + clock-frequency = <32768>; + }; + + restart_pshold: restart@c264000 { + compatible = "qcom,pshold"; + reg = <0xc264000 0x4>, + <0x1fd3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + qcom,wdt@17817000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17817000 0x1000>; + reg-names = "wdt-base"; + interrupts = <1 3 0>, <1 2 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + qcom,wakeup-enable; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + keepalive_opp_table: keepalive-opp-table { + compatible = "operating-points-v2"; + opp-1 { + opp-hz = /bits/ 64 < 1 >; + }; + }; + + snoc_pcnoc_keepalive: qcom,snoc_pcnoc_keepalive { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <1 627>; + qcom,active-only; + status = "ok"; + operating-points-v2 = <&keepalive_opp_table>; + }; + + ddr_keepalive: qcom,ddr_keepalive { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <1 512>; + qcom,active-only; + status = "ok"; + operating-points-v2 = <&keepalive_opp_table>; + }; + + clock_rpmh: qcom,rpmh { + compatible = "qcom,rpmh-clk-sdxprairie"; + mboxes = <&apps_rsc 0>; + mbox-names = "apps"; + #clock-cells = <1>; + }; + + clock_aop: qcom,aop { + compatible = "qcom,aop-qmp-clk"; + mboxes = <&qmp_aop 0>; + mbox-names = "qdss_clk"; + #clock-cells = <1>; + }; + + clock_gcc: qcom,gcc@100000 { + compatible = "qcom,gcc-sdxprairie", "syscon"; + reg = <0x100000 0x1f0000>; + reg-names = "cc_base"; + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_debugcc: qcom,cc-debug { + compatible = "qcom,debugcc-sdxprairie"; + qcom,gcc = <&clock_gcc>; + qcom,cpucc = <&cpucc_debug>; + qcom,mccc = <&mccc_debug>; + clock-names = "xo_clk_src"; + clocks = <&clock_rpmh RPMH_CXO_CLK>; + #clock-cells = <1>; + }; + + clock_cpu: qcom,clock-cpu@17808100 { + compatible = "qcom,cpu-sdxprairie"; + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + reg = <0x17810008 0x8>, + <0x17808100 0x44>; + reg-names = "apcs_cmd" , "apcs_pll"; + vdd-lucid-pll-supply = <&VDD_CX_LEVEL_AO>; + cpu-vdd-supply = <&VDD_CX_LEVEL_AO>; + qcom,speed0-bin-v0 = + < 0 RPMH_REGULATOR_LEVEL_OFF>, + < 345600000 RPMH_REGULATOR_LEVEL_LOW_SVS>, + < 576000000 RPMH_REGULATOR_LEVEL_SVS>, + < 1094400000 RPMH_REGULATOR_LEVEL_NOM>, + < 1555200000 RPMH_REGULATOR_LEVEL_TURBO>; + #clock-cells = <1>; + }; + + cpucc_debug: syscon@1781101c { + compatible = "syscon"; + reg = <0x1781101c 0x4>; + }; + + mccc_debug: syscon@90b0000 { + compatible = "syscon"; + reg = <0x90b0000 0x800>; + }; + + spmi_bus: qcom,spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0xd00>, + <0xc600000 0xff0110>, + <0xe600000 0x7fa0>, + <0xe700000 0x40>, + <0xc40a000 0xb00>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + serial_uart: serial@831000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x831000 0x200>; + interrupts = <0 26 0>; + clocks = <&clock_gcc GCC_BLSP1_UART3_APPS_CLK>, + <&clock_gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&uart3_console_active>; + pinctrl-1 = <&uart3_console_sleep>; + status = "ok"; + }; + + qcom,msm-imem@1468F000 { + compatible = "qcom,msm-imem"; + reg = <0x1468F000 0x1000>; /* Address and size of IMEM */ + ranges = <0x0 0x1468F000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 32>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 200>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 200>; + }; + }; + + eud: qcom,msm-eud@ff0000 { + compatible = "qcom,msm-eud"; + interrupt-names = "eud_irq"; + interrupts = ; + reg = <0xff0000 0x2000>, + <0xff2000 0x1000>; + reg-names = "eud_base", "eud_mode_mgr2"; + qcom,secure-eud-en; + qcom,eud-clock-vote-req; + clocks = <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; + clock-names = "eud_ahb2phy_clk"; + status = "ok"; + }; + + pil_modem: qcom,mss@4080000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x4080000 0x100>; + + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + vdd_mss-supply = <&VDD_MODEM_LEVEL>; + qcom,vdd_mss-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx", "vdd_mss"; + + qcom,firmware-name = "modem"; + memory-region = <&mpss_adsp_mem>; + qcom,pas-id = <4>; + qcom,smem-id = <421>; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x12>; + + interrupts-extended = <&intc 0 250 1>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + status = "ok"; + }; + + qcom,llcc@9200000 { + compatible = "qcom,llcc-core", "syscon", "simple-mfd"; + reg = <0x9200000 0x50000>; + reg-names = "llcc_base"; + qcom,llcc-banks-off = <0x0>; + qcom,llcc-broadcast-off = <0x0>; + + llcc: qcom,sdxprairie-llcc { + compatible = "qcom,sdxprairie-llcc"; + #cache-cells = <1>; + max-slices = <32>; + cap-based-alloc-and-pwr-collapse; + }; + }; + + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + }; + + dcc: dcc_v2@10a2000 { + compatible = "qcom,dcc-v2"; + reg = <0x10a2000 0x1000>, + <0x10ae800 0x1800>; + reg-names = "dcc-base", "dcc-ram-base"; + + dcc-ram-offset = <0x800>; + }; + + qcom,ipa_fws { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0xf>; + qcom,firmware-name = "ipa_fws"; + qcom,pil-force-shutdown; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + + ipa_hw: qcom,ipa@01e00000 { + compatible = "qcom,ipa"; + mboxes = <&qmp_aop 0>; + reg = <0x1e00000 0x84000>, + <0x1e04000 0x23000>; + reg-names = "ipa-base", "gsi-base"; + interrupts = + <0 241 IRQ_TYPE_NONE>, + <0 47 IRQ_TYPE_NONE>; + interrupt-names = "ipa-irq", "gsi-irq"; + qcom,ipa-hw-ver = <17>; /* IPA core version = IPAv4.5 */ + qcom,ipa-hw-mode = <0>; + qcom,ee = <0>; + qcom,use-ipa-tethering-bridge; + qcom,mhi-event-ring-id-limits = <9 11>; /* start and end */ + qcom,modem-cfg-emb-pipe-flt; + qcom,use-ipa-pm; + qcom,arm-smmu; + qcom,smmu-fast-map; + qcom,wlan-ce-db-over-pcie; + qcom,bandwidth-vote-for-ipa; + qcom,msm-bus,name = "ipa"; + qcom,ipa-wdi3-over-gsi; + qcom,ipa-endp-delay-wa; + qcom,msm-bus,num-cases = <5>; + qcom,msm-bus,num-paths = <5>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + , + , + , + , + , + + /* SVS2 */ + , + , + , + , + , + + /* SVS */ + , + , + , + , + , + + /* NOMINAL */ + , + , + , + , + , + + /* TURBO */ + , + , + , + , + ; + + qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", + "TURBO"; + qcom,throughput-threshold = <600 2500 5000>; + qcom,scaling-exceptions = <>; + + /* ipa tz unlock registers */ + qcom,ipa-tz-unlock-reg = + <0x4043583c 0x1000>; /* 32-bit reg addr and size*/ + + ipa_smmu_ap: ipa_smmu_ap { + compatible = "qcom,ipa-smmu-ap-cb"; + iommus = <&apps_smmu 0x5E0 0x0>; + qcom,iova-mapping = <0x20000000 0x40000000>; + qcom,additional-mapping = + /* modem tables in IMEM */ + <0x14688000 0x14688000 0x3000>; + qcom,ipa-q6-smem-size = <26624>; + }; + + ipa_smmu_wlan: ipa_smmu_wlan { + compatible = "qcom,ipa-smmu-wlan-cb"; + iommus = <&apps_smmu 0x5E1 0x0>; + }; + + ipa_smmu_uc: ipa_smmu_uc { + compatible = "qcom,ipa-smmu-uc-cb"; + iommus = <&apps_smmu 0x5E2 0x0>; + qcom,iova-mapping = <0x40000000 0x20000000>; + }; + + /* smp2p information */ + qcom,smp2p_map_ipa_1_out { + compatible = "qcom,smp2p-map-ipa-1-out"; + qcom,smem-states = <&smp2p_ipa_1_out 0>; + qcom,smem-state-names = "ipa-smp2p-out"; + }; + + qcom,smp2p_map_ipa_1_in { + compatible = "qcom,smp2p-map-ipa-1-in"; + interrupts-extended = <&smp2p_ipa_1_in 0 0>; + interrupt-names = "ipa-smp2p-in"; + }; + }; + + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + apcs_glb: mailbox@0x17811000 { + compatible = "qcom,sdxprairie-apcs-gcc"; + reg = <0x17811000 0xb9>; + #mbox-cells = <1>; + }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_modem: modem { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&apcs_glb 15>; + mbox-names = "mpss_smem"; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,apr_tal_rpmsg { + qcom,glink-channels = "apr_audio_svc"; + qcom,intents = <0x200 20>; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-data5-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA5_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl0"; + }; + + qcom,glinkpkt-data6-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA6_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl1"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + + qcom,glinkpkt-data21 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA21"; + qcom,glinkpkt-dev-name = "smd21"; + }; + + qcom,glinkpkt-data22 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA22"; + qcom,glinkpkt-dev-name = "smd22"; + }; + }; + + qmp_aop: qcom,qmp-aop@c300000 { + compatible = "qcom,qmp-mbox"; + reg = <0xc310000 0x1000>, <0x17811008 0x4>; + reg-names = "msgram", "irq-reg-base"; + qcom,irq-mask = <0x1>; + interrupts = ; + + label = "aop"; + qcom,early-boot; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; + + aop-msg-client { + compatible = "qcom,debugfs-qmp-client"; + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + }; + + apps_rsc: mailbox@17840000 { + compatible = "qcom,tcs-drv"; + label = "apps_rsc"; + reg = <0x17840000 0x100>, <0x17840d00 0x3000>; + interrupts = <0 17 0>; + #mbox-cells = <1>; + qcom,drv-id = <1>; + qcom,tcs-config = , + , + , + ; + }; + + cmd_db: qcom,cmd-db@c37000c { + compatible = "qcom,cmd-db"; + reg = <0xc37000c 8>; + }; + + system_pm { + compatible = "qcom,system-pm"; + mboxes = <&apps_rsc 0>; + }; + + qcom,smp2p-modem@1799000c { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + mboxes = <&apcs_glb 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom_cedev: qcedev@1de0000 { + compatible = "qcom,qcedev"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 252 0>; + qcom,bam-pipe-pair = <3>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <125 512 0 0>, + <125 512 393600 393600>; + qcom,no-clock-support; + qcom,smmu-s1-enable; + iommus = <&apps_smmu 0x0066 0x0011>, + <&apps_smmu 0x0076 0x0011>; + }; + + qcom_crypto: qcrypto@1de0000 { + compatible = "qcom,qcrypto"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 252 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <125 512 0 0>, + <125 512 393600 393600>; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-aead-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-hmac-algo; + qcom,no-clock-support; + qcom,smmu-s1-enable; + iommus = <&apps_smmu 0x0064 0x0011>, + <&apps_smmu 0x0074 0x0011>; + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + rpmh { + qcom,dump-size = <0x200000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x80000>; + qcom,dump-id = <0xe4>; + }; + + + tmc_etf { + qcom,dump-size = <0x4000>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etf_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + }; + + qcom_tzlog: tz-log@0x1468f720 { + compatible = "qcom,tz-log"; + reg = <0x1468f720 0x2000>; + }; + + qcom_rng: qrng@793000{ + compatible = "qcom,msm-rng"; + reg = <0x793000 0x1000>; + qcom,no-qrng-config; + qcom,msm-bus,name = "msm-rng-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 618 0 0>, /* No vote */ + <1 618 0 300000>; /* 75 MHz */ + qcom,no-clock-support; + }; + + qcom_seecom: qseecom@90000000{ + compatible = "qcom,qseecom"; + reg = <0x90000000 0xc00000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,no-clock-support; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <125 512 0 0>, + <125 512 20000 40000>, + <125 512 30000 80000>, + <125 512 40000 100000>; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_smcinvoke: smcinvoke@90000000{ + compatible = "qcom,smcinvoke"; + reg = <0x90000000 0xc00000>; + reg-names = "secapp-region"; + }; + + qnand_1: nand@1b00000 { + compatible = "qcom,msm-nand"; + reg = <0x01b00000 0x1000>, + <0x01b04000 0x1c000>; + reg-names = "nand_phys", + "bam_phys"; + qcom,reg-adjustment-offset = <0x4000>; + + interrupts = <0 135 0>; + interrupt-names = "bam_irq"; + + qcom,msm-bus,name = "qpic_nand"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <91 512 0 0>, + /* Voting for max b/w on PNOC bus for now */ + <91 512 400000 400000>; + + clock-names = "core_clk"; + clocks = <&clock_rpmh RPMH_QPIC_CLK>; + + status = "disabled"; + }; + + tsens0: tsens@c222000 { + compatible = "qcom,tsens24xx"; + reg = <0xc222000 0x4>, + <0xc263000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts = <0 163 0>, <0 165 0>; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + #thermal-sensor-cells = <1>; + }; + + msm_cpufreq: qcom,msm-cpufreq { + compatible = "qcom,msm-cpufreq"; + clocks = <&clock_cpu APCS_MUX_CLK>; + clock-names = "cpu0_clk"; + + qcom,cpufreq-table-0 = + < 153600 >, + < 300000 >, + < 345600 >, + < 576000 >, + < 1094400 >, + < 1555200 >; + }; + + ddr_bw_opp_table: ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 100, 4); /* 381 MB/s */ + BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ + BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ + BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ + BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ + BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ + BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ + BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ + BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */ + BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ + BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ + }; + + cpubw: qcom,cpubw { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = <1 512>; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + devfreq_compute: qcom,devfreq-compute { + compatible = "qcom,arm-cpu-mon"; + qcom,cpulist = <&CPU0>; + qcom,target-dev = <&cpubw>; + qcom,core-dev-table = + < 153600 MHZ_TO_MBPS( 300, 4) >, + < 576000 MHZ_TO_MBPS(1017, 4) >, + < 1497600 MHZ_TO_MBPS(1804, 4)>; + }; + + cnss_qca6390: qcom,cnss-qca6390@a0000000 { + compatible = "qcom,cnss-qca6390"; + reg = <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + wlan-en-gpio = <&tlmm 52 0>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + qcom,wlan-rc-num = <0>; + qcom,wlan-ramdump-dynamic = <0x400000>; + pcie-disable-l1; + pcie-disable-l1ss; + qcom,smmu-s1-enable; + + mhi,max-channels = <30>; + mhi,timeout = <10000>; + + mhi_channels { + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + + mhi_devices { + }; + + }; + + pcie_ep: qcom,pcie@40002000 { + compatible = "qcom,pcie-ep"; + + reg = <0x40002000 0x1000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40002000 0x2000>, + <0x01c00000 0x3000>, + <0x01c06000 0x2000>, + <0x01c03000 0x1000>, + <0x01fcb000 0x1000>; + reg-names = "msi", "dm_core", "elbi", "iatu", "edma", "parf", + "phy", "mmio", "tcsr_pcie_perst_en"; + + #address-cells = <0>; + interrupt-parent = <&pcie_ep>; + interrupts = <0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 140 0>; + interrupt-names = "int_global"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default + &pcie_ep_wake_default>; + + clkreq-gpio = <&tlmm 56 0>; + perst-gpio = <&tlmm 57 0>; + wake-gpio = <&tlmm 53 0>; + + gdsc-vdd-supply = <&gdsc_pcie>; + vreg-1.8-supply = <&pmxprairie_l1>; + vreg-0.9-supply = <&pmxprairie_l4>; + + qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0.9-voltage-level = <872000 872000 24000>; + + clocks = <&clock_gcc GCC_PCIE_PIPE_CLK>, + <&clock_gcc GCC_PCIE_CFG_AHB_CLK>, + <&clock_gcc GCC_PCIE_MSTR_AXI_CLK>, + <&clock_gcc GCC_PCIE_SLV_AXI_CLK>, + <&clock_gcc GCC_PCIE_AUX_CLK>, + <&clock_gcc GCC_PCIE_0_CLKREF_CLK>, + <&clock_gcc GCC_PCIE_SLEEP_CLK>, + <&clock_gcc GCC_PCIE_SLV_Q2A_AXI_CLK>; + + clock-names = "pcie_pipe_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_aux_clk", "pcie_ldo", + "pcie_sleep_clk", + "pcie_slv_q2a_axi_clk"; + + resets = <&clock_gcc GCC_PCIE_BCR>, + <&clock_gcc GCC_PCIE_PHY_BCR>; + + reset-names = "pcie_core_reset", + "pcie_phy_reset"; + + qcom,msm-bus,name = "pcie-ep"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 500 800>; + + qcom,pcie-vendor-id = /bits/ 16 <0x17cb>; + qcom,pcie-device-id = /bits/ 16 <0x0306>; + qcom,pcie-link-speed = <3>; + qcom,pcie-phy-ver = <6>; + qcom,pcie-active-config; + qcom,pcie-aggregated-irq; + qcom,pcie-mhi-a7-irq; + qcom,phy-status-reg = <0x814>; + + qcom,phy-init = <0x1240 0x001 0x0 0x1 + 0x100c 0x002 0x0 0x1 + 0x1044 0x018 0x0 0x1 + 0x104c 0x007 0x0 0x1 + 0x1058 0x00f 0x0 0x1 + 0x1074 0x009 0x0 0x1 + 0x1078 0x00a 0x0 0x1 + 0x107c 0x018 0x0 0x1 + 0x1080 0x019 0x0 0x1 + 0x1084 0x006 0x0 0x1 + 0x1088 0x003 0x0 0x1 + 0x1094 0x000 0x0 0x1 + 0x10a4 0x046 0x0 0x1 + 0x10a8 0x004 0x0 0x1 + 0x10ac 0x07f 0x0 0x1 + 0x10b0 0x002 0x0 0x1 + 0x10b4 0x0ff 0x0 0x1 + 0x10b8 0x004 0x0 0x1 + 0x10bc 0x025 0x0 0x1 + 0x10c4 0x028 0x0 0x1 + 0x10d4 0x008 0x0 0x1 + 0x10f4 0x0fb 0x0 0x1 + 0x10f8 0x001 0x0 0x1 + 0x110c 0x002 0x0 0x1 + 0x1158 0x012 0x0 0x1 + 0x115c 0x000 0x0 0x1 + 0x1168 0x005 0x0 0x1 + 0x116c 0x004 0x0 0x1 + 0x119c 0x088 0x0 0x1 + 0x11a0 0x003 0x0 0x1 + 0x11ac 0x056 0x0 0x1 + 0x11b0 0x01d 0x0 0x1 + 0x11b4 0x04b 0x0 0x1 + 0x11b8 0x01f 0x0 0x1 + 0x11bc 0x022 0x0 0x1 + 0x11a4 0x015 0x0 0x1 + 0x11a8 0x00f 0x0 0x1 + 0x008c 0x006 0x0 0x1 + 0x00e0 0x001 0x0 0x1 + 0x00c4 0x001 0x0 0x1 + 0x0258 0x016 0x0 0x1 + 0x0378 0x083 0x0 0x1 + 0x0360 0x0e2 0x0 0x1 + 0x0364 0x004 0x0 0x1 + 0x0368 0x030 0x0 0x1 + 0x0370 0x0ff 0x0 0x1 + 0x03cc 0x042 0x0 0x1 + 0x03d0 0x00d 0x0 0x1 + 0x03d4 0x077 0x0 0x1 + 0x03d8 0x02d 0x0 0x1 + 0x03dc 0x039 0x0 0x1 + 0x03e0 0x09f 0x0 0x1 + 0x03e4 0x00f 0x0 0x1 + 0x03e8 0x063 0x0 0x1 + 0x03ec 0x0bf 0x0 0x1 + 0x03f0 0x079 0x0 0x1 + 0x03f4 0x04f 0x0 0x1 + 0x03f8 0x00f 0x0 0x1 + 0x03fc 0x0d5 0x0 0x1 + 0x02ac 0x075 0x0 0x1 + 0x0310 0x055 0x0 0x1 + 0x0334 0x00c 0x0 0x1 + 0x0338 0x000 0x0 0x1 + 0x0350 0x00f 0x0 0x1 + 0x088c 0x006 0x0 0x1 + 0x08e0 0x001 0x0 0x1 + 0x08c4 0x001 0x0 0x1 + 0x0a58 0x016 0x0 0x1 + 0x0b78 0x083 0x0 0x1 + 0x0b60 0x0e2 0x0 0x1 + 0x0b64 0x004 0x0 0x1 + 0x0b68 0x030 0x0 0x1 + 0x0b70 0x0ff 0x0 0x1 + 0x0bcc 0x042 0x0 0x1 + 0x0bd0 0x00d 0x0 0x1 + 0x0bd4 0x077 0x0 0x1 + 0x0bd8 0x02d 0x0 0x1 + 0x0bdc 0x039 0x0 0x1 + 0x0be0 0x09f 0x0 0x1 + 0x0be4 0x00f 0x0 0x1 + 0x0be8 0x063 0x0 0x1 + 0x0bec 0x0bf 0x0 0x1 + 0x0bf0 0x079 0x0 0x1 + 0x0bf4 0x04f 0x0 0x1 + 0x0bf8 0x00f 0x0 0x1 + 0x0bfc 0x0d5 0x0 0x1 + 0x0aac 0x07f 0x0 0x1 + 0x0b10 0x055 0x0 0x1 + 0x0b34 0x00c 0x0 0x1 + 0x0b38 0x000 0x0 0x1 + 0x0b50 0x00f 0x0 0x1 + 0x13e4 0x003 0x0 0x1 + 0x1708 0x003 0x0 0x1 + 0x16a0 0x016 0x0 0x1 + 0x13e0 0x016 0x0 0x1 + 0x13d8 0x001 0x0 0x1 + 0x16fc 0x001 0x0 0x1 + 0x13dc 0x000 0x0 0x1 + 0x1700 0x000 0x0 0x1 + 0x1828 0x050 0x0 0x1 + 0x1c28 0x050 0x0 0x1 + 0x1200 0x000 0x0 0x1 + 0x1244 0x003 0x0 0x1>; + + status = "disabled"; + }; + + mhi_device: mhi_dev@1c03000 { + compatible = "qcom,msm-mhi-dev"; + reg = <0x1c03000 0x1000>, + <0x1e15000 0x4>, + <0x1e15148 0x4>; + reg-names = "mhi_mmio_base", "ipa_uc_mbox_crdb", + "ipa_uc_mbox_erdb"; + qcom,mhi-ep-msi = <0>; + qcom,mhi-version = <0x1000000>; + qcom,use-ipa-software-channel; + interrupts = <0 145 0>; + interrupt-names = "mhi-device-inta"; + qcom,mhi-ifc-id = <0x030617cb>; + qcom,mhi-interrupt; + status = "disabled"; + }; + + sdhc_1: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x8804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <4>; + + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ + <78 512 1600 3200>, /* 400 KB/s*/ + <78 512 80000 160000>, /* 20 MB/s */ + <78 512 100000 200000>, /* 25 MB/s */ + <78 512 200000 400000>, /* 50 MB/s */ + <78 512 400000 800000>, /* 100 MB/s */ + <78 512 400000 800000>, /* 200 MB/s */ + <78 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100000000 200000000 4294967295>; + + /* PM QoS */ + qcom,pm-qos-cpu-groups = <0x0>; + qcom,pm-qos-legacy-latency-us = <70 70>; + qcom,pm-qos-irq-type = "affine_cores"; + qcom,pm-qos-irq-cpu = <0>; + qcom,pm-qos-irq-latency = <70 70>; + + clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, + <&clock_gcc GCC_SDCC1_APPS_CLK>; + clock-names = "iface_clk", "core_clk"; + + qcom,restore-after-cx-collapse; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0xa800 0x10 + 0x2c010800 0x80040868>; + + status = "disabled"; + }; + + emac_hw: qcom,emac@00020000 { + compatible = "qcom,emac-dwc-eqos"; + qcom,arm-smmu; + reg = <0x20000 0x10000>, + <0x36000 0x100>, + <0x3900000 0x300000>; + reg-names = "emac-base", "rgmii-base", "tlmm-central-base"; + interrupts-extended = <&pdc 0 62 4>, <&pdc 0 60 4>, + <&tlmm 90 2>, <&pdc 0 49 4>, + <&pdc 0 50 4>, <&pdc 0 51 4>, + <&pdc 0 52 4>, <&pdc 0 53 4>, + <&pdc 0 54 4>, <&pdc 0 55 4>, + <&pdc 0 56 4>, <&pdc 0 57 4>, + <&pdc 0 290 1>, <&pdc 0 291 1>; + interrupt-names = "sbd-intr", "lpi-intr", + "phy-intr", "tx-ch0-intr", + "tx-ch1-intr", "tx-ch2-intr", + "tx-ch3-intr", "tx-ch4-intr", + "rx-ch0-intr", "rx-ch1-intr", + "rx-ch2-intr", "rx-ch3-intr", + "ptp_pps_irq_0", "ptp_pps_irq_1"; + qcom,msm-bus,name = "emac"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <98 512 0 0>, <1 781 0 0>, /* No vote */ + <98 512 2500 0>, <1 781 0 40000>, /* 10Mbps vote */ + <98 512 25000 0>, <1 781 0 40000>, /* 100Mbps vote */ + <98 512 250000 0>, <1 781 0 40000>; /* 1000Mbps vote */ + qcom,bus-vector-names = "0", "10", "100", "1000"; + clocks = <&clock_gcc GCC_ETH_AXI_CLK>, + <&clock_gcc GCC_ETH_PTP_CLK>, + <&clock_gcc GCC_ETH_RGMII_CLK>, + <&clock_gcc GCC_ETH_SLAVE_AHB_CLK>; + clock-names = "eth_axi_clk", + "eth_ptp_clk", + "eth_rgmii_clk", "eth_slave_ahb_clk"; + qcom,phy-intr-redirect = <&tlmm 90 GPIO_ACTIVE_LOW>; + qcom,phy-reset = <&tlmm 91 GPIO_ACTIVE_LOW>; + qcom,emac-pps0-test-intr = <&tlmm 31 GPIO_ACTIVE_LOW>; + vreg_rgmii-supply = <&pmxprairie_vref_rgmii>; + vreg_emac_phy-supply = <&vreg_emac_phy>; + vreg_rgmii_io_pads-supply = <&vreg_rgmii_io_pads>; + gdsc_emac-supply = <&gdsc_emac>; + mboxes = <&qmp_aop 0>; + mbox-names = "emac_aop"; + + io-macro-info { + io-macro-bypass-mode = <0>; + io-interface = "rgmii"; + }; + + emac_emb_smmu: emac_emb_smmu { + compatible = "qcom,emac-smmu-embedded"; + iommus = <&apps_smmu 0x1c0 0xf>; + qcom,iova-mapping = <0x80000000 0x40000000>; + }; + }; +}; + +#include "sdxprairie-pm.dtsi" +#include "sdxprairie-pinctrl.dtsi" +#include "sdxprairie-ion.dtsi" +#include "sdxprairie-bus.dtsi" +#include "msm-arm-smmu-sdxprairie.dtsi" +#include "sdxprairie-gdsc.dtsi" +#include "sdxprairie-usb.dtsi" +#include "sdxprairie-blsp.dtsi" +#include "sdxprairie-audio.dtsi" +#include "sdxprairie-pcie.dtsi" +#include "sdxprairie-coresight.dtsi" +#include "sdxprairie-aqc.dtsi" +#include "sdxprairie-thermal.dtsi" + +&gdsc_usb30 { + status = "ok"; +}; + +&gdsc_emac { + status = "ok"; +}; + +&gdsc_pcie { + status = "ok"; +}; + +&pcie0_rp { + cnss: qcom,qca6390@0 { + reg = <0 0 0 0 0>; + pci-ids = "17cb:1101"; + + memory-region = <&cnss_wlan_mem>; + }; +}; + +&soc { + ess-instance { + num_devices = <0x1>; + ess-switch@0 { + compatible = "qcom,ess-switch-qca83xx"; + qcom,switch-access-mode = "mdio"; + qcom,ar8327-initvals = < + 0x00004 0x4200000 /* PAD0_MODE */ + 0x00008 0x0 /* PAD5_MODE */ + 0x000e4 0xaa545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + qcom,link-intr-gpio = <90>; + qcom,switch-cpu-bmp = <0x01>; /* cpu port bitmap */ + qcom,switch-lan-bmp = <0x3e>; /* lan port bitmap */ + qcom,switch-wan-bmp = <0x0>; /* wan port bitmap */ + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/skeleton.dtsi b/arch/arm/boot/dts/qcom/skeleton.dtsi new file mode 100644 index 000000000000..34eda68d9ea2 --- /dev/null +++ b/arch/arm/boot/dts/qcom/skeleton.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * This file is deprecated, and will be removed once existing users have been + * updated. New dts{,i} files should *not* include skeleton.dtsi, and should + * instead explicitly provide the below nodes only as required. + * + * Skeleton device tree; the bare minimum needed to boot; just include and + * add a compatible value. The bootloader will typically populate the memory + * node. + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0>; }; +}; diff --git a/arch/arm/boot/dts/qcom/skeleton64.dtsi b/arch/arm/boot/dts/qcom/skeleton64.dtsi new file mode 100644 index 000000000000..1f8ba28132c4 --- /dev/null +++ b/arch/arm/boot/dts/qcom/skeleton64.dtsi @@ -0,0 +1,15 @@ +/* + * Skeleton device tree in the 64 bits version; the bare minimum + * needed to boot; just include and add a compatible value. The + * bootloader will typically populate the memory node. + */ + +/ { + #address-cells = <2>; + #size-cells = <2>; + cpus { }; + soc { }; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0 0 0>; }; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/sm6150-audio-overlay.dtsi similarity index 60% rename from arch/arm64/boot/dts/qcom/atoll-audio-overlay.dtsi rename to arch/arm/boot/dts/qcom/sm6150-audio-overlay.dtsi index 95e339b86454..4316c8b35d56 100644 --- a/arch/arm64/boot/dts/qcom/atoll-audio-overlay.dtsi +++ b/arch/arm/boot/dts/qcom/sm6150-audio-overlay.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -11,31 +11,20 @@ * GNU General Public License for more details. */ -#include "atoll-lpi.dtsi" -#include +#include "sm6150-lpi.dtsi" +#include #include -#include &bolero { qcom,num-macros = <4>; - bolero-clk-rsc-mngr { - compatible = "qcom,bolero-clk-rsc-mngr"; - qcom,fs-gen-sequence = <0x3000 0x1>, <0x3004 0x1>, <0x3080 0x2>; - qcom,rx_mclk_mode_muxsel = <0x627240D8>; - qcom,wsa_mclk_mode_muxsel = <0x627220D8>; - qcom,va_mclk_mode_muxsel = <0x627A0000>; - - clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk", - "wsa_core_clk", "wsa_npl_clk", "va_core_clk"; - clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>, - <&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>, - <&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>, - <&clock_audio_va 0>; - }; - - tx_macro: tx-macro@62620000 { + qcom,va-without-decimation; + slew_rate_reg1 = <0x62B6F000 0x0>; + slew_rate_reg2 = <0x62B6F004 0x0>; + slew_rate_val1 = <0x3333 0x0>; + slew_rate_val2 = <0xF 0x0>; + tx_macro: tx-macro@62ec0000 { compatible = "qcom,tx-macro"; - reg = <0x62620000 0x0>; + reg = <0x62ec0000 0x0>; clock-names = "tx_core_clk", "tx_npl_clk"; clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>; @@ -45,16 +34,11 @@ compatible = "qcom,swr-mstr"; #address-cells = <2>; #size-cells = <0>; - clock-names = "lpass_core_hw_vote", - "lpass_audio_hw_vote"; - clocks = <&lpass_core_hw_vote 0>, - <&lpass_audio_hw_vote 0>; qcom,swr_master_id = <3>; - swrm-io-base = <0x62630000 0x0>; - qcom,mipi-sdw-block-packing-mode = <1>; - interrupts = <0 296 0>, <0 555 0>; + swrm-io-base = <0x62ed0000 0x0>; + interrupts = <0 137 0>, <0 623 0>; interrupt-names = "swr_master_irq", "swr_wake_irq"; - qcom,swr-wakeup-required = <0>; + qcom,swr-wakeup-required = <1>; qcom,swr-num-ports = <5>; qcom,swr-port-mapping = <1 PCM_OUT1 0xF>, <2 ADC1 0x1>, <2 ADC2 0x2>, @@ -66,39 +50,29 @@ qcom,swr-num-dev = <1>; qcom,swr-clock-stop-mode0 = <1>; qcom,swr-mstr-irq-wakeup-capable = <1>; - wcd938x_tx_slave: wcd938x-tx-slave { - compatible = "qcom,wcd938x-slave"; - reg = <0x0 0x01170223>; - }; wcd937x_tx_slave: wcd937x-tx-slave { - status = "disabled"; compatible = "qcom,wcd937x-slave"; reg = <0x0 0x01170223>; }; }; }; - rx_macro: rx-macro@62600000 { + rx_macro: rx-macro@62ee0000 { compatible = "qcom,rx-macro"; - reg = <0x62600000 0x0>; + reg = <0x62ee0000 0x0>; clock-names = "rx_core_clk", "rx_npl_clk"; clocks = <&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>; qcom,rx-swr-gpios = <&rx_swr_gpios>; - qcom,rx_mclk_mode_muxsel = <0x627240D8>; + qcom,rx_mclk_mode_muxsel = <0x62c25020>; qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>; - qcom,default-clk-id = ; swr1: rx_swr_master { compatible = "qcom,swr-mstr"; #address-cells = <2>; #size-cells = <0>; - clock-names = "lpass_core_hw_vote", - "lpass_audio_hw_vote"; - clocks = <&lpass_core_hw_vote 0>, - <&lpass_audio_hw_vote 0>; qcom,swr_master_id = <2>; - swrm-io-base = <0x62610000 0x0>; - interrupts = <0 297 0>; + swrm-io-base = <0x62ef0000 0x0>; + interrupts = <0 138 0>; interrupt-names = "swr_master_irq"; qcom,swr-num-ports = <5>; qcom,swr-port-mapping = <1 HPH_L 0x1>, @@ -108,40 +82,28 @@ <5 DSD_R 0x2>; qcom,swr-num-dev = <1>; qcom,swr-clock-stop-mode0 = <1>; - wcd938x_rx_slave: wcd938x-rx-slave { - compatible = "qcom,wcd938x-slave"; - reg = <0x0 0x01170224>; - }; wcd937x_rx_slave: wcd937x-rx-slave { - status = "disabled"; compatible = "qcom,wcd937x-slave"; reg = <0x0 0x01170224>; }; }; }; - wsa_macro: wsa-macro@62640000 { + wsa_macro: wsa-macro@62f00000 { compatible = "qcom,wsa-macro"; - reg = <0x62640000 0x0>; + reg = <0x62f00000 0x0>; clock-names = "wsa_core_clk", "wsa_npl_clk"; clocks = <&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>; qcom,wsa-swr-gpios = <&wsa_swr_gpios>; - qcom,wsa_mclk_mode_muxsel = <0x627220D8>; qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>; - qcom,default-clk-id = ; swr0: wsa_swr_master { compatible = "qcom,swr-mstr"; #address-cells = <2>; #size-cells = <0>; qcom,swr_master_id = <1>; - clock-names = "lpass_core_hw_vote", - "lpass_audio_hw_vote"; - clocks = <&lpass_core_hw_vote 0>, - <&lpass_audio_hw_vote 0>; - swrm-io-base = <0x62650000 0x0>; - qcom,mipi-sdw-block-packing-mode = <0>; - interrupts = <0 295 0>; + swrm-io-base = <0x62f10000 0x0>; + interrupts = <0 136 0>; interrupt-names = "swr_master_irq"; qcom,swr-num-ports = <8>; qcom,swr-port-mapping = <1 SPKR_L 0x1>, @@ -177,67 +139,15 @@ }; - va_macro: va-macro@62770000 { + va_macro: va-macro@62f20000 { compatible = "qcom,va-macro"; - reg = <0x62770000 0x0>; - clock-names = "lpass_audio_hw_vote"; - clocks = <&lpass_audio_hw_vote 0>; - qcom,va-clk-mux-select = <1>; - qcom,va-island-mode-muxsel = <0x627A0000>; - qcom,va-dmic-sample-rate = <600000>; - qcom,default-clk-id = ; - }; - - wcd938x_codec: wcd938x-codec { - compatible = "qcom,wcd938x-codec"; - qcom,split-codec = <1>; - qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>, - <0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>, - <2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>, - <3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>, - <4 DSD_R 0x2 0 DSD_R>; - qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>, - <0 ADC2 0x2 0 ADC2>, <1 ADC3 0x1 0 ADC3>, - <1 ADC4 0x2 0 ADC4>, <2 DMIC0 0x1 0 DMIC0>, - <2 DMIC1 0x2 0 DMIC1>, <2 MBHC 0x4 0 DMIC2>, - <2 DMIC2 0x4 0 DMIC2>, <2 DMIC3 0x8 0 DMIC3>, - <3 DMIC4 0x1 0 DMIC4>, <3 DMIC5 0x2 0 DMIC5>, - <3 DMIC6 0x4 0 DMIC6>, <3 DMIC7 0x8 0 DMIC7>; - - qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; - qcom,rx-slave = <&wcd938x_rx_slave>; - qcom,tx-slave = <&wcd938x_tx_slave>; - - cdc-vdd-rxtx-supply = <&L10A>; - qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>; - qcom,cdc-vdd-rxtx-current = <30000>; - - cdc-vddio-supply = <&L10A>; - qcom,cdc-vddio-voltage = <1800000 1800000>; - qcom,cdc-vddio-current = <30000>; - - cdc-vdd-buck-supply = <&L15A>; - qcom,cdc-vdd-buck-voltage = <1800000 1800000>; - qcom,cdc-vdd-buck-current = <650000>; - - cdc-vdd-mic-bias-supply = <&BOB>; - qcom,cdc-vdd-mic-bias-voltage = <3300000 3300000>; - qcom,cdc-vdd-mic-bias-current = <30000>; - - qcom,cdc-micbias1-mv = <1800>; - qcom,cdc-micbias2-mv = <1800>; - qcom,cdc-micbias3-mv = <1800>; - - qcom,cdc-static-supplies = "cdc-vdd-rxtx", - "cdc-vddio", - "cdc-vdd-buck", - "cdc-vdd-mic-bias"; + reg = <0x62f20000 0x0>; + clock-names = "va_core_clk"; + clocks = <&clock_audio_va 0>; }; wcd937x_codec: wcd937x-codec { - status = "disabled"; compatible = "qcom,wcd937x-codec"; - qcom,split-codec = <1>; qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>, <0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>, <2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>, @@ -250,7 +160,7 @@ <3 DMIC3 0x2 0 DMIC5>, <3 DMIC4 0x4 0 DMIC6>, <3 DMIC5 0x8 0 DMIC7>; - qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; + qcom,wcd-rst-gpio-node = <&wcd937x_rst_gpio>; qcom,rx-slave = <&wcd937x_rx_slave>; qcom,tx-slave = <&wcd937x_tx_slave>; @@ -267,8 +177,8 @@ qcom,cdc-vdd-buck-current = <650000>; cdc-vdd-mic-bias-supply = <&BOB>; - qcom,cdc-vdd-mic-bias-voltage = <3300000 3300000>; - qcom,cdc-vdd-mic-bias-current = <30000>; + qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>; + qcom,cdc-vdd-mic-bias-current = <25000>; qcom,cdc-micbias1-mv = <1800>; qcom,cdc-micbias2-mv = <1800>; @@ -279,21 +189,16 @@ "cdc-vdd-mic-bias"; qcom,cdc-on-demand-supplies = "cdc-vdd-buck"; }; + }; -&atoll_snd { - qcom,model = "atoll-idp-snd-card"; +&sm6150_snd { + qcom,model = "sm6150-idp-snd-card"; qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; - qcom,ext-disp-audio-rx = <0>; + qcom,ext-disp-audio-rx = <1>; qcom,audio-routing = - "AMIC1", "MIC BIAS1", - "MIC BIAS1", "Analog Mic1", "AMIC2", "MIC BIAS2", "MIC BIAS2", "Analog Mic2", - "AMIC3", "MIC BIAS3", - "MIC BIAS3", "Analog Mic3", - "AMIC4", "MIC BIAS4", - "MIC BIAS4", "Analog Mic4", "TX DMIC0", "MIC BIAS1", "MIC BIAS1", "Digital Mic0", "TX DMIC1", "MIC BIAS1", @@ -302,23 +207,20 @@ "MIC BIAS3", "Digital Mic2", "TX DMIC3", "MIC BIAS3", "MIC BIAS3", "Digital Mic3", - "TX DMIC4", "MIC BIAS4", - "MIC BIAS4", "Digital Mic4", + "TX_AIF1 CAP", "VA_MCLK", + "TX_AIF2 CAP", "VA_MCLK", + "RX AIF1 PB", "VA_MCLK", + "RX AIF2 PB", "VA_MCLK", + "RX AIF3 PB", "VA_MCLK", + "RX AIF4 PB", "VA_MCLK", + "HPHL_OUT", "VA_MCLK", + "HPHR_OUT", "VA_MCLK", + "AUX_OUT", "VA_MCLK", "IN1_HPHL", "HPHL_OUT", "IN2_HPHR", "HPHR_OUT", "IN3_AUX", "AUX_OUT", "TX SWR_ADC0", "ADC1_OUTPUT", - "TX SWR_ADC1", "ADC2_OUTPUT", - "TX SWR_ADC2", "ADC3_OUTPUT", - "TX SWR_ADC3", "ADC4_OUTPUT", - "TX SWR_DMIC0", "DMIC1_OUTPUT", - "TX SWR_DMIC1", "DMIC2_OUTPUT", - "TX SWR_DMIC2", "DMIC3_OUTPUT", - "TX SWR_DMIC3", "DMIC4_OUTPUT", - "TX SWR_DMIC4", "DMIC5_OUTPUT", - "TX SWR_DMIC5", "DMIC6_OUTPUT", - "TX SWR_DMIC6", "DMIC7_OUTPUT", - "TX SWR_DMIC7", "DMIC8_OUTPUT", + "TX SWR_ADC2", "ADC2_OUTPUT", "WSA SRC0_INP", "SRC0", "WSA_TX DEC0_INP", "TX DEC0 MUX", "WSA_TX DEC1_INP", "TX DEC1 MUX", @@ -328,56 +230,22 @@ "RX_TX DEC3_INP", "TX DEC3 MUX", "SpkrLeft IN", "WSA_SPK1 OUT", "SpkrRight IN", "WSA_SPK2 OUT", - "VA MIC BIAS3", "Digital Mic0", - "VA MIC BIAS3", "Digital Mic1", - "VA MIC BIAS1", "Digital Mic2", - "VA MIC BIAS1", "Digital Mic3", - "VA MIC BIAS4", "Digital Mic4", - "VA MIC BIAS4", "Digital Mic5", - "VA DMIC0", "VA MIC BIAS3", - "VA DMIC1", "VA MIC BIAS3", - "VA DMIC2", "VA MIC BIAS1", - "VA DMIC3", "VA MIC BIAS1", - "VA DMIC4", "VA MIC BIAS4", - "VA DMIC5", "VA MIC BIAS4", - "VA SWR_ADC0", "VA_SWR_CLK", - "VA SWR_ADC1", "VA_SWR_CLK", - "VA SWR_ADC2", "VA_SWR_CLK", - "VA SWR_ADC3", "VA_SWR_CLK", - "VA SWR_MIC0", "VA_SWR_CLK", - "VA SWR_MIC1", "VA_SWR_CLK", - "VA SWR_MIC2", "VA_SWR_CLK", - "VA SWR_MIC3", "VA_SWR_CLK", - "VA SWR_MIC4", "VA_SWR_CLK", - "VA SWR_MIC5", "VA_SWR_CLK", - "VA SWR_MIC6", "VA_SWR_CLK", - "VA SWR_MIC7", "VA_SWR_CLK", - "VA SWR_ADC0", "ADC1_OUTPUT", - "VA SWR_ADC1", "ADC2_OUTPUT", - "VA SWR_ADC2", "ADC3_OUTPUT", - "VA SWR_ADC3", "ADC4_OUTPUT", - "VA SWR_MIC0", "DMIC1_OUTPUT", - "VA SWR_MIC1", "DMIC2_OUTPUT", - "VA SWR_MIC2", "DMIC3_OUTPUT", - "VA SWR_MIC3", "DMIC4_OUTPUT", - "VA SWR_MIC4", "DMIC5_OUTPUT", - "VA SWR_MIC5", "DMIC6_OUTPUT", - "VA SWR_MIC6", "DMIC7_OUTPUT", - "VA SWR_MIC7", "DMIC8_OUTPUT"; + "WSA_SPK1 OUT", "VA_MCLK", + "WSA_SPK2 OUT", "VA_MCLK"; qcom,msm-mbhc-hphl-swh = <1>; qcom,msm-mbhc-gnd-swh = <1>; qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; - qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>; - asoc-codec = <&stub_codec>, <&bolero>; - asoc-codec-names = "msm-stub-codec.1", "bolero_codec"; + asoc-codec = <&stub_codec>, <&bolero>, <&ext_disp_audio_codec>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec", + "msm-ext-disp-audio-codec-rx"; qcom,wsa-max-devs = <2>; qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>, <&wsa881x_0213>, <&wsa881x_0214>; qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", "SpkrLeft", "SpkrRight"; qcom,codec-max-aux-devs = <1>; - qcom,codec-aux-devs = <&wcd938x_codec>; + qcom,codec-aux-devs = <&wcd937x_codec>; qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>, <&bolero>; }; @@ -399,20 +267,11 @@ qcom,lpi-gpios; }; - cdc_dmic45_gpios: cdc_dmic45_pinctrl { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>; - pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>; - qcom,lpi-gpios; - }; - wsa_swr_gpios: wsa_swr_clk_data_pinctrl { compatible = "qcom,msm-cdc-pinctrl"; pinctrl-names = "aud_active", "aud_sleep"; pinctrl-0 = <&wsa_swr_clk_active &wsa_swr_data_active>; pinctrl-1 = <&wsa_swr_clk_sleep &wsa_swr_data_sleep>; - qcom,lpi-gpios; }; rx_swr_gpios: rx_swr_clk_data_pinctrl { @@ -426,10 +285,10 @@ tx_swr_gpios: tx_swr_clk_data_pinctrl { compatible = "qcom,msm-cdc-pinctrl"; pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&tx_swr_clk_active - &tx_swr_data1_active &tx_swr_data2_active>; - pinctrl-1 = <&tx_swr_clk_sleep - &tx_swr_data1_sleep &tx_swr_data2_sleep>; + pinctrl-0 = <&tx_swr_clk_active &tx_swr_data1_active + &tx_swr_data2_active>; + pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data1_sleep + &tx_swr_data2_sleep>; qcom,lpi-gpios; }; @@ -447,11 +306,51 @@ pinctrl-1 = <&spkr_2_sd_n_sleep>; }; - wcd_rst_gpio: msm_cdc_pinctrl@58 { + wcd9xxx_intc: wcd9xxx-irq { + status = "disabled"; + compatible = "qcom,wcd9xxx-irq"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&tlmm>; + qcom,gpio-connect = <&tlmm 122 0>; + pinctrl-names = "default"; + pinctrl-0 = <&wcd_intr_default>; + }; + + + wcd934x_rst_gpio: msm_cdc_pinctrl@29 { + status = "disabled"; compatible = "qcom,msm-cdc-pinctrl"; pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&wcd_reset_active>; - pinctrl-1 = <&wcd_reset_sleep>; + pinctrl-0 = <&lpi_wcd934x_reset_active>; + pinctrl-1 = <&lpi_wcd934x_reset_sleep>; + qcom,lpi-gpios; + }; + + wcd937x_rst_gpio: msm_cdc_pinctrl@24 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&lpi_wcd937x_reset_active>; + pinctrl-1 = <&lpi_wcd937x_reset_sleep>; + qcom,lpi-gpios; + }; + + tavil_glink: qcom,wcd-dsp-glink { + status = "disabled"; + compatible = "qcom,wcd-dsp-glink"; + qcom,wdsp-channels = "g_glink_ctrl", + "g_glink_persistent_data_nild", + "g_glink_persistent_data_ild", + "g_glink_audio_data"; + }; + + tavil_wdsp: wcd-dsp-mgr@2 { + status = "disabled"; + compatible = "qcom,wcd-dsp-mgr"; + qcom,wdsp-components = <&wcd934x_cdc 0>, + <&tavil_spi_0 1>, + <&glink_spi_xprt_wdsp 2>; + qcom,img-filename = "cpe_9340"; }; clock_audio_wsa_1: wsa_core_clk { @@ -510,4 +409,97 @@ #clock-cells = <1>; }; + clock_audio: audio_ext_clk { + status = "disabled"; + qcom,codec-ext-clk-src = <0>; + compatible = "qcom,audio-ref-clk"; + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&wcd934x_mclk_default>; + pinctrl-1 = <&wcd934x_mclk_default>; + qcom,use-pinctrl = <1>; + qcom,audio-ref-clk-gpio = <&pm6150_gpios 8 0>; + clock-names = "osr_clk"; + clocks = <&pm6150_clkdiv>; + qcom,node_has_rpm_clock; + pmic-clock-names = "pm6150_div_clk1"; + #clock-cells = <1>; + }; + + dbu1: dbu1 { + compatible = "regulator-fixed"; + regulator-name = "dbu1"; + startup-delay-us = <0>; + enable-active-high; + }; +}; + +&slim_aud { + wcd934x_cdc: tavil_codec { + status = "disabled"; + compatible = "qcom,tavil-slim-pgd"; + elemental-addr = [00 01 50 02 17 02]; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 + 30 31>; + + qcom,wcd-rst-gpio-node = <&wcd934x_rst_gpio>; + + clock-names = "wcd_clk"; + clocks = <&clock_audio 0>; + + cdc-vdd-buck-supply = <&dbu1>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <594000>; + + cdc-buck-sido-supply = <&dbu1>; + qcom,cdc-buck-sido-voltage = <1800000 1800000>; + qcom,cdc-buck-sido-current = <500000>; + + cdc-vdd-tx-h-supply = <&dbu1>; + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-tx-h-current = <25000>; + + cdc-vdd-rx-h-supply = <&dbu1>; + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-rx-h-current = <25000>; + + cdc-vddpx-1-supply = <&dbu1>; + qcom,cdc-vddpx-1-voltage = <1800000 1800000>; + qcom,cdc-vddpx-1-current = <10000>; + + cdc-vdd-mic-bias-supply = <&BOB>; + qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>; + qcom,cdc-vdd-mic-bias-current = <30400 1000001>; + + qcom,cdc-static-supplies = "cdc-vdd-buck", + "cdc-buck-sido", + "cdc-vdd-tx-h", + "cdc-vdd-rx-h", + "cdc-vddpx-1"; + qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias"; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; + + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-slim-ifd = "tavil-slim-ifd"; + qcom,cdc-slim-ifd-elemental-addr = [00 00 50 02 17 02]; + qcom,cdc-dmic-sample-rate = <4800000>; + qcom,cdc-mad-dmic-rate = <600000>; + + qcom,wdsp-cmpnt-dev-name = "tavil_codec"; + qcom,vreg-micb-supply = <&BOB>; + + tavil_spi_0: wcd_spi { + compatible = "qcom,wcd-spi-v2"; + qcom,master-bus-num = <0>; + qcom,chip-select = <0>; + qcom,max-frequency = <24000000>; + qcom,mem-base-addr = <0x100000>; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom/sm6150-audio.dtsi b/arch/arm/boot/dts/qcom/sm6150-audio.dtsi new file mode 100644 index 000000000000..6dcc4d2842bd --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-audio.dtsi @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msm-audio-lpass.dtsi" +#include "dt-bindings/clock/qcom,audio-ext-clk.h" + +&msm_audio_ion { + iommus = <&apps_smmu 0x1721 0x0>; + qcom,smmu-sid-mask = /bits/ 64 <0xf>; +}; + +&soc { + qcom,avtimer@62CF7000 { + compatible = "qcom,avtimer"; + reg = <0x62CF700C 0x4>, + <0x62CF7010 0x4>; + reg-names = "avtimer_lsb_addr", "avtimer_msb_addr"; + qcom,clk-div = <192>; + qcom,clk-mult = <10>; + }; + + lpass_core_hw_vote: lpass_core_hw_vote { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + #clock-cells = <1>; + }; +}; + +&audio_apr { + q6core: qcom,q6core-audio { + compatible = "qcom,q6core-audio"; + bolero: bolero-cdc { + compatible = "qcom,bolero-codec"; + tx_macro: tx-macro@62ec0000 { + swr2: tx_swr_master { + }; + }; + + rx_macro: rx-macro@62ee0000 { + swr1: rx_swr_master { + }; + }; + wsa_macro: wsa-macro@62f00000 { + swr0: wsa_swr_master { + }; + }; + }; + }; +}; + +&q6core { + sm6150_snd: sound { + compatible = "qcom,sm6150-asoc-snd"; + qcom,mi2s-audio-intf = <1>; + qcom,auxpcm-audio-intf = <1>; + qcom,wcn-btfm = <1>; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq"; + asoc-cpu = <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, + <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, <&sb_8_rx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, + <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, + <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>, + <&wsa_cdc_dma_0_rx>, <&wsa_cdc_dma_0_tx>, + <&wsa_cdc_dma_1_rx>, <&wsa_cdc_dma_1_tx>, + <&wsa_cdc_dma_2_tx>, + <&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>, + <&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>, + <&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>, + <&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>, + <&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>, + <&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>, + <&rx_cdc_dma_6_rx>, <&rx_cdc_dma_7_rx>; + asoc-cpu-names = "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", + "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16398", + "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", + "msm-dai-q6-dev.16400", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", + "msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36929", + "msm-dai-cdc-dma-dev.45056", + "msm-dai-cdc-dma-dev.45057", + "msm-dai-cdc-dma-dev.45058", + "msm-dai-cdc-dma-dev.45059", + "msm-dai-cdc-dma-dev.45061", + "msm-dai-cdc-dma-dev.45104", + "msm-dai-cdc-dma-dev.45105", + "msm-dai-cdc-dma-dev.45106", + "msm-dai-cdc-dma-dev.45107", + "msm-dai-cdc-dma-dev.45108", + "msm-dai-cdc-dma-dev.45109", + "msm-dai-cdc-dma-dev.45110", + "msm-dai-cdc-dma-dev.45111", + "msm-dai-cdc-dma-dev.45112", + "msm-dai-cdc-dma-dev.45113", + "msm-dai-cdc-dma-dev.45114", + "msm-dai-cdc-dma-dev.45115", + "msm-dai-cdc-dma-dev.45116", + "msm-dai-cdc-dma-dev.45118"; + fsa4480-i2c-handle = <&fsa4480>; + }; +}; + +&slim_aud { + status = "disabled"; + dai_slim: msm_dai_slim { + status = "disabled"; + compatible = "qcom,msm-dai-slim"; + elemental-addr = [ff ff ff fe 17 02]; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-bus.dtsi b/arch/arm/boot/dts/qcom/sm6150-bus.dtsi new file mode 100644 index 000000000000..cc73771442d1 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-bus.dtsi @@ -0,0 +1,1850 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&soc { + ad_hoc_bus: ad-hoc-bus { + compatible = "qcom,msm-bus-device"; + reg = <0x1700000 0x40000>, + <0x1500000 0x40000>, + <0x9160000 0x40000>, + <0x9680000 0x60000>, + <0x1380000 0x40000>, + <0x1740000 0x40000>, + <0x1620000 0x40000>, + <0x1620000 0x40000>, + <0x1620000 0x40000>; + + reg-names = "aggre1_noc-base", "config_noc-base", + "dc_noc-base", "gem_noc-base", + "mc_virt-base", "mmss_noc-base", + "system_noc-base", "ipa_virt-base", + "camnoc_virt-base"; + + mbox-names = "apps_rsc", "disp_rsc"; + mboxes = <&apps_rsc 0 &disp_rsc 0>; + + /*RSCs*/ + rsc_apps: rsc-apps { + cell-id = ; + label = "apps_rsc"; + qcom,rsc-dev; + qcom,req_state = <2>; + }; + + rsc_disp: rsc-disp { + cell-id = ; + label = "disp_rsc"; + qcom,rsc-dev; + qcom,req_state = <2>; + }; + + /*BCMs*/ + bcm_acv: bcm-acv { + cell-id = ; + label = "ACV"; + qcom,bcm-name = "ACV"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_alc: bcm-alc { + cell-id = ; + label = "ALC"; + qcom,bcm-name = "ALC"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_mc0: bcm-mc0 { + cell-id = ; + label = "MC0"; + qcom,bcm-name = "MC0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sh0: bcm-sh0 { + cell-id = ; + label = "SH0"; + qcom,bcm-name = "SH0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_mm0: bcm-mm0 { + cell-id = ; + label = "MM0"; + qcom,bcm-name = "MM0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_mm1: bcm-mm1 { + cell-id = ; + label = "MM1"; + qcom,bcm-name = "MM1"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sh2: bcm-sh2 { + cell-id = ; + label = "SH2"; + qcom,bcm-name = "SH2"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_mm2: bcm-mm2 { + cell-id = ; + label = "MM2"; + qcom,bcm-name = "MM2"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sh3: bcm-sh3 { + cell-id = ; + label = "SH3"; + qcom,bcm-name = "SH3"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_mm3: bcm-mm3 { + cell-id = ; + label = "MM3"; + qcom,bcm-name = "MM3"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn0: bcm-sn0 { + cell-id = ; + label = "SN0"; + qcom,bcm-name = "SN0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_ce0: bcm-ce0 { + cell-id = ; + label = "CE0"; + qcom,bcm-name = "CE0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_ip0: bcm-ip0 { + cell-id = ; + label = "IP0"; + qcom,bcm-name = "IP0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_cn0: bcm-cn0 { + cell-id = ; + label = "CN0"; + qcom,bcm-name = "CN0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_qup0: bcm-qup0 { + cell-id = ; + label = "QUP0"; + qcom,bcm-name = "QUP0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn1: bcm-sn1 { + cell-id = ; + label = "SN1"; + qcom,bcm-name = "SN1"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_cn1: bcm-cn1 { + cell-id = ; + label = "CN1"; + qcom,bcm-name = "CN1"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn2: bcm-sn2 { + cell-id = ; + label = "SN2"; + qcom,bcm-name = "SN2"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn3: bcm-sn3 { + cell-id = ; + label = "SN3"; + qcom,bcm-name = "SN3"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn4: bcm-sn4 { + cell-id = ; + label = "SN4"; + qcom,bcm-name = "SN4"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn5: bcm-sn5 { + cell-id = ; + label = "SN5"; + qcom,bcm-name = "SN5"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn8: bcm-sn8 { + cell-id = ; + label = "SN8"; + qcom,bcm-name = "SN8"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn9: bcm-sn9 { + cell-id = ; + label = "SN9"; + qcom,bcm-name = "SN9"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn12: bcm-sn12 { + cell-id = ; + label = "SN12"; + qcom,bcm-name = "SN12"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn13: bcm-sn13 { + cell-id = ; + label = "SN13"; + qcom,bcm-name = "SN13"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn14: bcm-sn14 { + cell-id = ; + label = "SN14"; + qcom,bcm-name = "SN14"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn15: bcm-sn15 { + cell-id = ; + label = "SN15"; + qcom,bcm-name = "SN15"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_mc0_display: bcm-mc0_display { + cell-id = ; + label = "MC0_DISPLAY"; + qcom,bcm-name = "MC0"; + qcom,rscs = <&rsc_disp>; + qcom,bcm-dev; + }; + + bcm_sh0_display: bcm-sh0_display { + cell-id = ; + label = "SH0_DISPLAY"; + qcom,bcm-name = "SH0"; + qcom,rscs = <&rsc_disp>; + qcom,bcm-dev; + }; + + bcm_mm0_display: bcm-mm0_display { + cell-id = ; + label = "MM0_DISPLAY"; + qcom,bcm-name = "MM0"; + qcom,rscs = <&rsc_disp>; + qcom,bcm-dev; + }; + + bcm_mm1_display: bcm-mm1_display { + cell-id = ; + label = "MM1_DISPLAY"; + qcom,bcm-name = "MM1"; + qcom,rscs = <&rsc_disp>; + qcom,bcm-dev; + }; + + bcm_mm2_display: bcm-mm2_display { + cell-id = ; + label = "MM2_DISPLAY"; + qcom,bcm-name = "MM2"; + qcom,rscs = <&rsc_disp>; + qcom,bcm-dev; + }; + + /*Buses*/ + fab_aggre1_noc: fab-aggre1_noc { + cell-id = ; + label = "fab-aggre1_noc"; + qcom,fab-dev; + qcom,base-name = "aggre1_noc-base"; + qcom,qos-off = <4096>; + qcom,base-offset = <16384>; + qcom,sbm-offset = <0>; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_camnoc_virt: fab-camnoc_virt { + cell-id = ; + label = "fab-camnoc_virt"; + qcom,fab-dev; + qcom,base-name = "camnoc_virt-base"; + qcom,qos-off = <0>; + qcom,base-offset = <0>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + clocks = <>; + }; + + fab_config_noc: fab-config_noc { + cell-id = ; + label = "fab-config_noc"; + qcom,fab-dev; + qcom,base-name = "config_noc-base"; + qcom,qos-off = <0>; + qcom,base-offset = <0>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_dc_noc: fab-dc_noc { + cell-id = ; + label = "fab-dc_noc"; + qcom,fab-dev; + qcom,base-name = "dc_noc-base"; + qcom,qos-off = <0>; + qcom,base-offset = <0>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_gem_noc: fab-gem_noc { + cell-id = ; + label = "fab-gem_noc"; + qcom,fab-dev; + qcom,base-name = "gem_noc-base"; + qcom,qos-off = <128>; + qcom,base-offset = <176128>; + qcom,sbm-offset = <0>; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_ipa_virt: fab-ipa_virt { + cell-id = ; + label = "fab-ipa_virt"; + qcom,fab-dev; + qcom,base-name = "ipa_virt-base"; + qcom,qos-off = <0>; + qcom,base-offset = <0>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + clocks = <>; + }; + + fab_mc_virt: fab-mc_virt { + cell-id = ; + label = "fab-mc_virt"; + qcom,fab-dev; + qcom,base-name = "mc_virt-base"; + qcom,qos-off = <0>; + qcom,base-offset = <0>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + clocks = <>; + }; + + fab_mmss_noc: fab-mmss_noc { + cell-id = ; + label = "fab-mmss_noc"; + qcom,fab-dev; + qcom,base-name = "mmss_noc-base"; + qcom,qos-off = <4096>; + qcom,base-offset = <36864>; + qcom,sbm-offset = <0>; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_system_noc: fab-system_noc { + cell-id = ; + label = "fab-system_noc"; + qcom,fab-dev; + qcom,base-name = "system_noc-base"; + qcom,qos-off = <4096>; + qcom,base-offset = <45056>; + qcom,sbm-offset = <0>; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_gem_noc_display: fab-gem_noc_display { + cell-id = ; + label = "fab-gem_noc_display"; + qcom,fab-dev; + qcom,base-name = "gem_noc-base"; + qcom,qos-off = <128>; + qcom,base-offset = <176128>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_mc_virt_display: fab-mc_virt_display { + cell-id = ; + label = "fab-mc_virt_display"; + qcom,fab-dev; + qcom,base-name = "mc_virt-base"; + qcom,qos-off = <0>; + qcom,base-offset = <0>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + clocks = <>; + }; + + fab_mmss_noc_display: fab-mmss_noc_display { + cell-id = ; + label = "fab-mmss_noc_display"; + qcom,fab-dev; + qcom,base-name = "mmss_noc-base"; + qcom,qos-off = <4096>; + qcom,base-offset = <36864>; + qcom,sbm-offset = <0>; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clocks = <>; + }; + + /*Masters*/ + + mas_qhm_a1noc_cfg: mas-qhm-a1noc-cfg { + cell-id = ; + label = "mas-qhm-a1noc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_srvc_aggre2_noc>; + qcom,bus-dev = <&fab_aggre1_noc>; + }; + + mas_qhm_qdss_bam: mas-qhm-qdss-bam { + cell-id = ; + label = "mas-qhm-qdss-bam"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,qport = <8>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,ap-owned; + qcom,prio = <2>; + }; + + mas_qhm_qspi: mas-qhm-qspi { + cell-id = ; + label = "mas-qhm-qspi"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,qport = <18>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,bcms = <&bcm_cn1>; + qcom,ap-owned; + qcom,prio = <2>; + }; + + mas_qhm_qup0: mas-qhm-qup0 { + cell-id = ; + label = "mas-qhm-qup0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,qport = <12>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,bcms = <&bcm_qup0>; + qcom,ap-owned; + qcom,prio = <2>; + }; + + mas_qhm_qup1: mas-qhm-qup1 { + cell-id = ; + label = "mas-qhm-qup1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,qport = <14>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,bcms = <&bcm_qup0>; + qcom,ap-owned; + qcom,prio = <2>; + }; + + mas_qnm_cnoc: mas-qnm-cnoc { + cell-id = ; + label = "mas-qnm-cnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <0>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,ap-owned; + qcom,prio = <2>; + qcom,forwarding; + }; + + mas_qxm_crypto: mas-qxm-crypto { + cell-id = ; + label = "mas-qxm-crypto"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <1>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,bcms = <&bcm_ce0>; + qcom,ap-owned; + qcom,prio = <2>; + qcom,forwarding; + }; + + mas_qxm_ipa: mas-qxm-ipa { + cell-id = ; + label = "mas-qxm-ipa"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <2>; + qcom,connections = <&slv_qns_lpass_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,ap-owned; + qcom,prio = <2>; + qcom,forwarding; + qcom,defer-init-qos; + qcom,node-qos-bcms = <7035 0 1>; + }; + + mas_xm_emac_avb: mas-xm-emac-avb { + cell-id = ; + label = "mas-xm-emac-avb"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <6>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,ap-owned; + qcom,prio = <2>; + }; + + mas_xm_pcie: mas-xm-pcie { + cell-id = ; + label = "mas-xm-pcie"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <15>; + qcom,connections = <&slv_qns_pcie_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_xm_qdss_etr: mas-xm-qdss-etr { + cell-id = ; + label = "mas-xm-qdss-etr"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <7>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,ap-owned; + qcom,prio = <2>; + }; + + mas_xm_sdc1: mas-xm-sdc1 { + cell-id = ; + label = "mas-xm-sdc1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <10>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,bcms = <&bcm_cn1>; + qcom,ap-owned; + qcom,prio = <2>; + }; + + mas_xm_sdc2: mas-xm-sdc2 { + cell-id = ; + label = "mas-xm-sdc2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <18>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,bcms = <&bcm_cn1>; + qcom,ap-owned; + qcom,prio = <2>; + }; + + mas_xm_ufs_mem: mas-xm-ufs-mem { + cell-id = ; + label = "mas-xm-ufs-mem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <13>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,ap-owned; + qcom,prio = <2>; + qcom,node-qos-clks { + clocks = + <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; + clock-names = + "clk-aggre-ufs-phy-axi-no-rate"; + }; + }; + + mas_xm_usb2: mas-xm-usb2 { + cell-id = ; + label = "mas-xm-usb2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <17>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,ap-owned; + qcom,prio = <2>; + qcom,node-qos-clks { + clocks = + <&clock_gcc GCC_AGGRE_USB2_SEC_AXI_CLK>; + clock-names = + "clk-aggre-usb2-sec-axi-no-rate"; + }; + }; + + mas_xm_usb3_0: mas-xm-usb3-0 { + cell-id = ; + label = "mas-xm-usb3-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <9>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,ap-owned; + qcom,prio = <2>; + qcom,node-qos-clks { + clocks = + <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + clock-names = + "clk-aggre-usb3-prim-axi-no-rate"; + }; + }; + + mas_qxm_camnoc_hf0_uncomp: mas-qxm-camnoc-hf0-uncomp { + cell-id = ; + label = "mas-qxm-camnoc-hf0-uncomp"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_camnoc_uncomp>; + qcom,bus-dev = <&fab_camnoc_virt>; + qcom,bcms = <&bcm_mm1>; + }; + + mas_qxm_camnoc_hf1_uncomp: mas-qxm-camnoc-hf1-uncomp { + cell-id = ; + label = "mas-qxm-camnoc-hf1-uncomp"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_camnoc_uncomp>; + qcom,bus-dev = <&fab_camnoc_virt>; + qcom,bcms = <&bcm_mm1>; + }; + + mas_qxm_camnoc_sf_uncomp: mas-qxm-camnoc-sf-uncomp { + cell-id = ; + label = "mas-qxm-camnoc-sf-uncomp"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_camnoc_uncomp>; + qcom,bus-dev = <&fab_camnoc_virt>; + qcom,bcms = <&bcm_mm1>; + }; + + mas_qhm_spdm: mas-qhm-spdm { + cell-id = ; + label = "mas-qhm-spdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_cnoc_a2noc>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + mas_qnm_snoc: mas-qnm-snoc { + cell-id = ; + label = "mas-qnm-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qhs_tlmm_south + &slv_qhs_camera_cfg &slv_qhs_sdc2 + &slv_qhs_mnoc_cfg &slv_qhs_sdc1 + &slv_qhs_ufs_mem_cfg &slv_qhs_tlmm_east + &slv_qhs_emac_avb_cfg &slv_qhs_pcie_config + &slv_qhs_glm &slv_qhs_ahb2phy_east + &slv_qhs_tlmm_west &slv_qhs_qdss_cfg + &slv_qhs_display_cfg &slv_qhs_tcsr + &slv_qhs_ddrss_cfg &slv_qhs_snoc_cfg + &slv_qhs_gpuss_cfg &slv_qhs_venus_cfg + &slv_qhs_ipa &slv_qhs_clk_ctl + &slv_qhs_aop &slv_qhs_usb3 + &slv_srvc_cnoc &slv_qhs_ahb2phy_west + &slv_qhs_cpr_cx &slv_qhs_a1_noc_cfg + &slv_qhs_aoss &slv_qhs_prng + &slv_qhs_vsense_ctrl_cfg &slv_qhs_qspi + &slv_qhs_spdm &slv_qhs_crypto0_cfg + &slv_qhs_pimem_cfg &slv_qhs_cpr_mx + &slv_qhs_qup0 &slv_qhs_qup1 + &slv_qhs_usb2 &slv_qhs_imem_cfg>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + mas_xm_qdss_dap: mas-xm-qdss-dap { + cell-id = ; + label = "mas-xm-qdss-dap"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qhs_tlmm_south + &slv_qhs_camera_cfg &slv_qhs_sdc2 + &slv_qhs_mnoc_cfg &slv_qhs_sdc1 + &slv_qhs_ufs_mem_cfg &slv_qhs_tlmm_east + &slv_qhs_emac_avb_cfg &slv_qhs_pcie_config + &slv_qhs_glm &slv_qhs_ahb2phy_east + &slv_qhs_tlmm_west &slv_qhs_qdss_cfg + &slv_qhs_display_cfg &slv_qhs_tcsr + &slv_qhs_ddrss_cfg &slv_qns_cnoc_a2noc + &slv_qhs_snoc_cfg &slv_qhs_gpuss_cfg + &slv_qhs_venus_cfg &slv_qhs_ipa + &slv_qhs_clk_ctl &slv_qhs_aop + &slv_qhs_usb3 &slv_srvc_cnoc + &slv_qhs_ahb2phy_west &slv_qhs_cpr_cx + &slv_qhs_a1_noc_cfg &slv_qhs_aoss + &slv_qhs_prng &slv_qhs_vsense_ctrl_cfg + &slv_qhs_qspi &slv_qhs_spdm + &slv_qhs_crypto0_cfg &slv_qhs_pimem_cfg + &slv_qhs_cpr_mx &slv_qhs_qup0 + &slv_qhs_qup1 &slv_qhs_usb2 + &slv_qhs_imem_cfg>; + qcom,bus-dev = <&fab_config_noc>; + }; + + mas_qhm_cnoc: mas-qhm-cnoc { + cell-id = ; + label = "mas-qhm-cnoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qhs_llcc + &slv_qhs_dc_noc_gemnoc>; + qcom,bus-dev = <&fab_dc_noc>; + }; + + mas_acm_apps: mas-acm-apps { + cell-id = ; + label = "mas-acm-apps"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,qport = <96 98>; + qcom,connections = <&slv_qns_llcc &slv_qns_gem_noc_snoc + &slv_qns_sys_pcie>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,bcms = <&bcm_sh2>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + }; + + mas_acm_gpu_tcu: mas-acm-gpu-tcu { + cell-id = ; + label = "mas-acm-gpu-tcu"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <352>; + qcom,connections = <&slv_qns_llcc + &slv_qns_gem_noc_snoc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <6>; + }; + + mas_acm_sys_tcu: mas-acm-sys-tcu { + cell-id = ; + label = "mas-acm-sys-tcu"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <384>; + qcom,connections = <&slv_qns_llcc + &slv_qns_gem_noc_snoc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <6>; + }; + + mas_qhm_gemnoc_cfg: mas-qhm-gemnoc-cfg { + cell-id = ; + label = "mas-qhm-gemnoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_srvc_gemnoc + &slv_qhs_mdsp_ms_mpu_cfg>; + qcom,bus-dev = <&fab_gem_noc>; + }; + + mas_qnm_gpu: mas-qnm-gpu { + cell-id = ; + label = "mas-qnm-gpu"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,qport = <288 289>; + qcom,connections = <&slv_qns_llcc + &slv_qns_gem_noc_snoc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + }; + + mas_qnm_mnoc_hf: mas-qnm-mnoc-hf { + cell-id = ; + label = "mas-qnm-mnoc-hf"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <128>; + qcom,connections = <&slv_qns_llcc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + qcom,node-qos-bcms = <7012 0 1>; + }; + + mas_qnm_mnoc_sf: mas-qnm-mnoc-sf { + cell-id = ; + label = "mas-qnm-mnoc-sf"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <320>; + qcom,connections = <&slv_qns_llcc + &slv_qns_gem_noc_snoc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + qcom,node-qos-bcms = <7012 0 1>; + }; + + mas_qnm_snoc_gc: mas-qnm-snoc-gc { + cell-id = ; + label = "mas-qnm-snoc-gc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <192>; + qcom,connections = <&slv_qns_llcc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + }; + + mas_qnm_snoc_sf: mas-qnm-snoc-sf { + cell-id = ; + label = "mas-qnm-snoc-sf"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,qport = <160>; + qcom,connections = <&slv_qns_llcc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + }; + + mas_ipa_core_master: mas-ipa-core-master { + cell-id = ; + label = "mas-ipa-core-master"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_ipa_core_slave>; + qcom,bus-dev = <&fab_ipa_virt>; + }; + + mas_llcc_mc: mas-llcc-mc { + cell-id = ; + label = "mas-llcc-mc"; + qcom,buswidth = <4>; + qcom,agg-ports = <2>; + qcom,connections = <&slv_ebi>; + qcom,bus-dev = <&fab_mc_virt>; + }; + + mas_qhm_mnoc_cfg: mas-qhm-mnoc-cfg { + cell-id = ; + label = "mas-qhm-mnoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_srvc_mnoc>; + qcom,bus-dev = <&fab_mmss_noc>; + }; + + mas_qxm_camnoc_hf0: mas-qxm-camnoc-hf0 { + cell-id = ; + label = "mas-qxm-camnoc-hf0"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <1>; + qcom,connections = <&slv_qns_mem_noc_hf>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm1>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + qcom,node-qos-bcms = <7012 0 1>; + }; + + mas_qxm_camnoc_hf1: mas-qxm-camnoc-hf1 { + cell-id = ; + label = "mas-qxm-camnoc-hf1"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <2>; + qcom,connections = <&slv_qns_mem_noc_hf>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm1>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + qcom,node-qos-bcms = <7012 0 1>; + }; + + mas_qxm_camnoc_sf: mas-qxm-camnoc-sf { + cell-id = ; + label = "mas-qxm-camnoc-sf"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <0>; + qcom,connections = <&slv_qns2_mem_noc>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm2>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + qcom,node-qos-bcms = <7012 0 1>; + }; + + mas_qxm_mdp0: mas-qxm-mdp0 { + cell-id = ; + label = "mas-qxm-mdp0"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <3>; + qcom,connections = <&slv_qns_mem_noc_hf>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm1>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + qcom,node-qos-bcms = <7012 0 1>; + }; + + mas_qxm_rot: mas-qxm-rot { + cell-id = ; + label = "mas-qxm-rot"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <5>; + qcom,connections = <&slv_qns2_mem_noc>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm1>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + qcom,node-qos-bcms = <7012 0 1>; + }; + + mas_qxm_venus0: mas-qxm-venus0 { + cell-id = ; + label = "mas-qxm-venus0"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <6>; + qcom,connections = <&slv_qns2_mem_noc>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm3>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + qcom,node-qos-bcms = <7012 0 1>; + }; + + mas_qxm_venus_arm9: mas-qxm-venus-arm9 { + cell-id = ; + label = "mas-qxm-venus-arm9"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <8>; + qcom,connections = <&slv_qns2_mem_noc>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm3>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + qcom,node-qos-bcms = <7012 0 1>; + }; + + mas_qhm_snoc_cfg: mas-qhm-snoc-cfg { + cell-id = ; + label = "mas-qhm-snoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_srvc_snoc>; + qcom,bus-dev = <&fab_system_noc>; + }; + + mas_qnm_aggre1_noc: mas-qnm-aggre1-noc { + cell-id = ; + label = "mas-qnm-aggre1-noc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_gemnoc_sf &slv_qxs_pimem + &slv_xs_pcie &slv_qxs_imem + &slv_qhs_apss &slv_qns_cnoc + &slv_xs_sys_tcu_cfg &slv_xs_qdss_stm>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn9>; + }; + + mas_qnm_gemnoc: mas-qnm-gemnoc { + cell-id = ; + label = "mas-qnm-gemnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qxs_pimem &slv_qxs_imem + &slv_qhs_apss &slv_qns_cnoc + &slv_xs_sys_tcu_cfg &slv_xs_qdss_stm>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn15>; + }; + + mas_qnm_gemnoc_pcie: mas-qnm-gemnoc-pcie { + cell-id = ; + label = "mas-qnm-gemnoc-pcie"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_xs_pcie>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn8>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + }; + + mas_qnm_lpass_anoc: mas-qnm-lpass-anoc { + cell-id = ; + label = "mas-qnm-lpass-anoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_gemnoc_sf + &slv_qxs_pimem &slv_xs_pcie + &slv_qxs_imem &slv_qhs_apss + &slv_qns_cnoc &slv_xs_qdss_stm>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn13>; + }; + + mas_qnm_pcie_anoc: mas-qnm-pcie-anoc { + cell-id = ; + label = "mas-qnm-pcie-anoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_gemnoc_sf &slv_qxs_imem + &slv_qhs_apss &slv_qns_cnoc + &slv_xs_qdss_stm>; + qcom,bus-dev = <&fab_system_noc>; + }; + + mas_qxm_pimem: mas-qxm-pimem { + cell-id = ; + label = "mas-qxm-pimem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <1>; + qcom,connections = <&slv_qxs_imem &slv_qns_memnoc_gc>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn12>; + qcom,ap-owned; + qcom,prio = <2>; + qcom,forwarding; + }; + + mas_xm_gic: mas-xm-gic { + cell-id = ; + label = "mas-xm-gic"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <2>; + qcom,connections = <&slv_qxs_imem &slv_qns_memnoc_gc>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn12>; + qcom,ap-owned; + qcom,prio = <2>; + qcom,forwarding; + }; + + mas_alc: mas-alc { + cell-id = ; + label = "mas-alc"; + qcom,buswidth = <1>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_mc_virt>; + qcom,bcms = <&bcm_alc>; + }; + + mas_qnm_mnoc_hf_display: mas-qnm-mnoc-hf_display { + cell-id = ; + label = "mas-qnm-mnoc-hf_display"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <128>; + qcom,connections = <&slv_qns_llcc_display>; + qcom,bus-dev = <&fab_gem_noc_display>; + }; + + mas_qnm_mnoc_sf_display: mas-qnm-mnoc-sf_display { + cell-id = ; + label = "mas-qnm-mnoc-sf_display"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <320>; + qcom,connections = <&slv_qns_llcc_display>; + qcom,bus-dev = <&fab_gem_noc_display>; + }; + + mas_llcc_mc_display: mas-llcc-mc_display { + cell-id = ; + label = "mas-llcc-mc_display"; + qcom,buswidth = <4>; + qcom,agg-ports = <2>; + qcom,connections = <&slv_ebi_display>; + qcom,bus-dev = <&fab_mc_virt_display>; + }; + + mas_qxm_mdp0_display: mas-qxm-mdp0_display { + cell-id = ; + label = "mas-qxm-mdp0_display"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <3>; + qcom,connections = <&slv_qns_mem_noc_hf_display>; + qcom,bus-dev = <&fab_mmss_noc_display>; + qcom,bcms = <&bcm_mm1_display>; + }; + + mas_qxm_rot_display: mas-qxm-rot_display { + cell-id = ; + label = "mas-qxm-rot_display"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <5>; + qcom,connections = <&slv_qns2_mem_noc_display>; + qcom,bus-dev = <&fab_mmss_noc_display>; + qcom,bcms = <&bcm_mm1_display>; + }; + + /*Internal nodes*/ + + /*Slaves*/ + + slv_qns_a1noc_snoc:slv-qns-a1noc-snoc { + cell-id = ; + label = "slv-qns-a1noc-snoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,connections = <&mas_qnm_aggre1_noc>; + }; + + slv_qns_lpass_snoc:slv-qns-lpass-snoc { + cell-id = ; + label = "slv-qns-lpass-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,connections = <&mas_qnm_lpass_anoc>; + }; + + slv_qns_pcie_snoc:slv-qns-pcie-snoc { + cell-id = ; + label = "slv-qns-pcie-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,connections = <&mas_qnm_pcie_anoc>; + qcom,bcms = <&bcm_sn14>; + }; + + slv_srvc_aggre2_noc:slv-srvc-aggre2-noc { + cell-id = ; + label = "slv-srvc-aggre2-noc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,bcms = <&bcm_sn3>; + }; + + slv_qns_camnoc_uncomp:slv-qns-camnoc-uncomp { + cell-id = ; + label = "slv-qns-camnoc-uncomp"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_camnoc_virt>; + }; + + slv_qhs_a1_noc_cfg:slv-qhs-a1-noc-cfg { + cell-id = ; + label = "slv-qhs-a1-noc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,connections = <&mas_qhm_a1noc_cfg>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_ahb2phy_east:slv-qhs-ahb2phy-east { + cell-id = ; + label = "slv-qhs-ahb2phy-east"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn1>; + }; + + slv_qhs_ahb2phy_west:slv-qhs-ahb2phy-west { + cell-id = ; + label = "slv-qhs-ahb2phy-west"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn1>; + }; + + slv_qhs_aop:slv-qhs-aop { + cell-id = ; + label = "slv-qhs-aop"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_aoss:slv-qhs-aoss { + cell-id = ; + label = "slv-qhs-aoss"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_camera_cfg:slv-qhs-camera-cfg { + cell-id = ; + label = "slv-qhs-camera-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_clk_ctl:slv-qhs-clk-ctl { + cell-id = ; + label = "slv-qhs-clk-ctl"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_cpr_cx:slv-qhs-cpr-cx { + cell-id = ; + label = "slv-qhs-cpr-cx"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_cpr_mx:slv-qhs-cpr-mx { + cell-id = ; + label = "slv-qhs-cpr-mx"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_crypto0_cfg:slv-qhs-crypto0-cfg { + cell-id = ; + label = "slv-qhs-crypto0-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_ddrss_cfg:slv-qhs-ddrss-cfg { + cell-id = ; + label = "slv-qhs-ddrss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,connections = <&mas_qhm_cnoc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_display_cfg:slv-qhs-display-cfg { + cell-id = ; + label = "slv-qhs-display-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_emac_avb_cfg:slv-qhs-emac-avb-cfg { + cell-id = ; + label = "slv-qhs-emac-avb-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_glm:slv-qhs-glm { + cell-id = ; + label = "slv-qhs-glm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_gpuss_cfg:slv-qhs-gpuss-cfg { + cell-id = ; + label = "slv-qhs-gpuss-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_imem_cfg:slv-qhs-imem-cfg { + cell-id = ; + label = "slv-qhs-imem-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_ipa:slv-qhs-ipa { + cell-id = ; + label = "slv-qhs-ipa"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_mnoc_cfg:slv-qhs-mnoc-cfg { + cell-id = ; + label = "slv-qhs-mnoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,connections = <&mas_qhm_mnoc_cfg>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_pcie_config:slv-qhs-pcie-config { + cell-id = ; + label = "slv-qhs-pcie-config"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_pimem_cfg:slv-qhs-pimem-cfg { + cell-id = ; + label = "slv-qhs-pimem-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_prng:slv-qhs-prng { + cell-id = ; + label = "slv-qhs-prng"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_qdss_cfg:slv-qhs-qdss-cfg { + cell-id = ; + label = "slv-qhs-qdss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_qspi:slv-qhs-qspi { + cell-id = ; + label = "slv-qhs-qspi"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn1>; + }; + + slv_qhs_qup0:slv-qhs-qup0 { + cell-id = ; + label = "slv-qhs-qup0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_qup1:slv-qhs-qup1 { + cell-id = ; + label = "slv-qhs-qup1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_sdc1:slv-qhs-sdc1 { + cell-id = ; + label = "slv-qhs-sdc1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn1>; + }; + + slv_qhs_sdc2:slv-qhs-sdc2 { + cell-id = ; + label = "slv-qhs-sdc2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn1>; + }; + + slv_qhs_snoc_cfg:slv-qhs-snoc-cfg { + cell-id = ; + label = "slv-qhs-snoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,connections = <&mas_qhm_snoc_cfg>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_spdm:slv-qhs-spdm { + cell-id = ; + label = "slv-qhs-spdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_tcsr:slv-qhs-tcsr { + cell-id = ; + label = "slv-qhs-tcsr"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_tlmm_east:slv-qhs-tlmm-east { + cell-id = ; + label = "slv-qhs-tlmm-east"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_tlmm_south:slv-qhs-tlmm-south { + cell-id = ; + label = "slv-qhs-tlmm-south"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_tlmm_west:slv-qhs-tlmm-west { + cell-id = ; + label = "slv-qhs-tlmm-west"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_ufs_mem_cfg:slv-qhs-ufs-mem-cfg { + cell-id = ; + label = "slv-qhs-ufs-mem-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_usb2:slv-qhs-usb2 { + cell-id = ; + label = "slv-qhs-usb2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_usb3:slv-qhs-usb3 { + cell-id = ; + label = "slv-qhs-usb3"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_venus_cfg:slv-qhs-venus-cfg { + cell-id = ; + label = "slv-qhs-venus-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_vsense_ctrl_cfg:slv-qhs-vsense-ctrl-cfg { + cell-id = ; + label = "slv-qhs-vsense-ctrl-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qns_cnoc_a2noc:slv-qns-cnoc-a2noc { + cell-id = ; + label = "slv-qns-cnoc-a2noc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,connections = <&mas_qnm_cnoc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_srvc_cnoc:slv-srvc-cnoc { + cell-id = ; + label = "slv-srvc-cnoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_dc_noc_gemnoc:slv-qhs-dc-noc-gemnoc { + cell-id = ; + label = "slv-qhs-dc-noc-gemnoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_dc_noc>; + qcom,connections = <&mas_qhm_gemnoc_cfg>; + }; + + slv_qhs_llcc:slv-qhs-llcc { + cell-id = ; + label = "slv-qhs-llcc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_dc_noc>; + }; + + slv_qhs_mdsp_ms_mpu_cfg:slv-qhs-mdsp-ms-mpu-cfg { + cell-id = ; + label = "slv-qhs-mdsp-ms-mpu-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_gem_noc>; + }; + + slv_qns_gem_noc_snoc:slv-qns-gem-noc-snoc { + cell-id = ; + label = "slv-qns-gem-noc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,connections = <&mas_qnm_gemnoc>; + qcom,bcms = <&bcm_sh3>; + }; + + slv_qns_llcc:slv-qns-llcc { + cell-id = ; + label = "slv-qns-llcc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,connections = <&mas_llcc_mc>; + qcom,bcms = <&bcm_sh0>; + }; + + slv_qns_sys_pcie:slv-qns-sys-pcie { + cell-id = ; + label = "slv-qns-sys-pcie"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,connections = <&mas_qnm_gemnoc_pcie>; + }; + + slv_srvc_gemnoc:slv-srvc-gemnoc { + cell-id = ; + label = "slv-srvc-gemnoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_gem_noc>; + }; + + slv_ipa_core_slave:slv-ipa-core-slave { + cell-id = ; + label = "slv-ipa-core-slave"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_ipa_virt>; + qcom,bcms = <&bcm_ip0>; + }; + + slv_ebi:slv-ebi { + cell-id = ; + label = "slv-ebi"; + qcom,buswidth = <4>; + qcom,agg-ports = <2>; + qcom,bus-dev = <&fab_mc_virt>; + qcom,bcms = <&bcm_mc0>, <&bcm_acv>; + }; + + slv_qns2_mem_noc:slv-qns2-mem-noc { + cell-id = ; + label = "slv-qns2-mem-noc"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,connections = <&mas_qnm_mnoc_sf>; + qcom,bcms = <&bcm_mm2>; + }; + + slv_qns_mem_noc_hf:slv-qns-mem-noc-hf { + cell-id = ; + label = "slv-qns-mem-noc-hf"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,connections = <&mas_qnm_mnoc_hf>; + qcom,bcms = <&bcm_mm0>; + }; + + slv_srvc_mnoc:slv-srvc-mnoc { + cell-id = ; + label = "slv-srvc-mnoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_mmss_noc>; + }; + + slv_qhs_apss:slv-qhs-apss { + cell-id = ; + label = "slv-qhs-apss"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + }; + + slv_qns_cnoc:slv-qns-cnoc { + cell-id = ; + label = "slv-qns-cnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,connections = <&mas_qnm_snoc>; + qcom,bcms = <&bcm_sn3>; + }; + + slv_qns_gemnoc_sf:slv-qns-gemnoc-sf { + cell-id = ; + label = "slv-qns-gemnoc-sf"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,connections = <&mas_qnm_snoc_sf>; + qcom,bcms = <&bcm_sn0>; + }; + + slv_qns_memnoc_gc:slv-qns-memnoc-gc { + cell-id = ; + label = "slv-qns-memnoc-gc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,connections = <&mas_qnm_snoc_gc>; + qcom,bcms = <&bcm_sn2>; + }; + + slv_qxs_imem:slv-qxs-imem { + cell-id = ; + label = "slv-qxs-imem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn1>; + }; + + slv_qxs_pimem:slv-qxs-pimem { + cell-id = ; + label = "slv-qxs-pimem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn4>; + }; + + slv_srvc_snoc:slv-srvc-snoc { + cell-id = ; + label = "slv-srvc-snoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + }; + + slv_xs_pcie:slv-xs-pcie { + cell-id = ; + label = "slv-xs-pcie"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn8>; + }; + + slv_xs_qdss_stm:slv-xs-qdss-stm { + cell-id = ; + label = "slv-xs-qdss-stm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn5>; + }; + + slv_xs_sys_tcu_cfg:slv-xs-sys-tcu-cfg { + cell-id = ; + label = "slv-xs-sys-tcu-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + }; + + slv_qns_llcc_display:slv-qns-llcc_display { + cell-id = ; + label = "slv-qns-llcc_display"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_gem_noc_display>; + qcom,connections = <&mas_llcc_mc_display>; + qcom,bcms = <&bcm_sh0_display>; + }; + + slv_ebi_display:slv-ebi_display { + cell-id = ; + label = "slv-ebi_display"; + qcom,buswidth = <4>; + qcom,agg-ports = <2>; + qcom,bus-dev = <&fab_mc_virt_display>; + qcom,bcms = <&bcm_mc0_display>; + }; + + slv_qns2_mem_noc_display:slv-qns2-mem-noc_display { + cell-id = ; + label = "slv-qns2-mem-noc_display"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_mmss_noc_display>; + qcom,connections = <&mas_qnm_mnoc_sf_display>; + qcom,bcms = <&bcm_mm2_display>; + }; + + slv_qns_mem_noc_hf_display:slv-qns-mem-noc-hf_display { + cell-id = ; + label = "slv-qns-mem-noc-hf_display"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_mmss_noc_display>; + qcom,connections = <&mas_qnm_mnoc_hf_display>; + qcom,bcms = <&bcm_mm0_display>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/qcom/sm6150-camera-sensor-adp.dtsi b/arch/arm/boot/dts/qcom/sm6150-camera-sensor-adp.dtsi new file mode 100644 index 000000000000..30153ed84ec4 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-camera-sensor-adp.dtsi @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&cam_cci { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + + + cam_vio-supply = <&pm6155_1_s4>; + cam_vana-supply = <&pm6155_1_s4>; + cam_vdig-supply = <&pm6155_1_s4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + + gpios = <&tlmm 43 0>, + <&tlmm 28 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + + cam_vio-supply = <&pm6155_1_s4>; + cam_vana-supply = <&pm6155_1_s4>; + cam_vdig-supply = <&pm6155_1_s4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + + gpios = <&tlmm 31 0>, + <&tlmm 29 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + + cam_vio-supply = <&pm6155_1_s4>; + cam_vana-supply = <&pm6155_1_s4>; + cam_vdig-supply = <&pm6155_1_s4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + gpios = <&tlmm 31 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-camera-sensor-idp.dtsi b/arch/arm/boot/dts/qcom/sm6150-camera-sensor-idp.dtsi new file mode 100644 index 000000000000..c29345c7cbcb --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-camera-sensor-idp.dtsi @@ -0,0 +1,624 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2 &pm6150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2 &pm6150l_switch2>; + status = "ok"; + }; + + led_flash_front: qcom,camera-flash@2 { + cell-index = <2>; + reg = <0x02 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash2>; + torch-source = <&pm6150l_torch2>; + switch-source = <&pm6150l_switch2>; + status = "ok"; + enable-active-high; + gpio = <&tlmm 38 0>; + pinctrl-names = "default"; + pinctrl-0 = <&flash_led3_front_en>; + }; + + led_flash_rear_aux2: qcom,camera-flash@3 { + cell-index = <3>; + reg = <0x03 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2 &pm6150l_switch2>; + status = "ok"; + }; + + camera_ldo: gpio-regulator@0 { + compatible = "regulator-fixed"; + reg = <0x00 0x00>; + regulator-name = "camera_ldo"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&pm6150l_gpios 3 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_sensor_dvdd_en>; + vin-supply = <&pm6150l_s8>; + }; + + camera_vana0_ldo: gpio-regulator@1 { + compatible = "regulator-fixed"; + reg = <0x01 0x00>; + regulator-name = "camera_vana0_ldo"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-enable-ramp-delay = <233>; + enable-active-high; + gpio = <&pm6150l_gpios 9 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_sensor_0_vana>; + vin-supply = <&pm6150l_bob>; + }; + + camera_vana1_2_ldo: gpio-regulator@2 { + compatible = "regulator-fixed"; + reg = <0x02 0x00>; + regulator-name = "camera_vana1_2_ldo"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-enable-ramp-delay = <233>; + enable-active-high; + gpio = <&pm6150l_gpios 4 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_sensor_1_2_vana>; + vin-supply = <&pm6150l_bob>; + }; +}; + +&cam_cci { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; + + actuator_rear: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm6150_l19>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + }; + + actuator_rear_aux: qcom,actuator@1 { + cell-index = <1>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm6150_l19>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + }; + + actuator_front: qcom,actuator@2 { + cell-index = <2>; + reg = <0x1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm6150_l19>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + }; + + actuator_triple_tele: qcom,actuator@3 { + cell-index = <3>; + reg = <0x3>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm6150_l19>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + }; + + ois_rear: qcom,ois@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,ois"; + cci-master = <0>; + cam_vaf-supply = <&pm6150_l19>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "disabled"; + }; + + eeprom_rear: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm6150_l13>; + cam_vana-supply = <&camera_vana0_ldo>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm6150_l19>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2850000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 2850000 1200000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 28 0>, + <&tlmm 47 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm6150_l13>; + cam_vana-supply = <&camera_vana1_2_ldo>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm6150_l19>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2850000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 2850000 1200000 0 2800000>; + rgltr-load-current = <105000 0 80000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 29 0>, + <&tlmm 45 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm6150_l13>; + cam_vana-supply = <&camera_vana1_2_ldo>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm6150_l19>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2850000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 2850000 1200000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 30 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear_aux: qcom,eeprom@3 { + cell-index = <3>; + reg = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm6150_l13>; + cam_vana-supply = <&camera_vana0_ldo>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm6150_l19>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2850000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 2850000 1200000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 28 0>, + <&tlmm 47 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear>; + ois-src = <&ois_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&pm6150_l13>; + cam_vana-supply = <&camera_vana0_ldo>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2850000 1200000 0>; + rgltr-max-voltage = <1800000 2850000 1200000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 28 0>, + <&tlmm 47 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux>; + actuator-src = <&actuator_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&pm6150_l13>; + cam_vana-supply = <&camera_vana1_2_ldo>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2850000 1200000 0>; + rgltr-max-voltage = <1800000 2850000 1200000 0>; + rgltr-load-current = <105000 0 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 29 0>, + <&tlmm 45 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + actuator-src = <&actuator_front>; + led-flash-src = <&led_flash_front>; + cam_vio-supply = <&pm6150_l13>; + cam_vana-supply = <&camera_vana1_2_ldo>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2850000 1200000 0>; + rgltr-max-voltage = <1800000 2850000 1200000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 30 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x3>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux>; + actuator-src = <&actuator_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&pm6150_l13>; + cam_vana-supply = <&camera_vana0_ldo>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2850000 1200000 0>; + rgltr-max-voltage = <1800000 2850000 1200000 0>; + rgltr-load-current = <105000 0 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 29 0>, + <&tlmm 45 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + reg = <0x4>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&pm6150_l13>; + cam_vana-supply = <&camera_vana0_ldo>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2850000 1200000 0>; + rgltr-max-voltage = <1800000 2850000 1200000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 28 0>, + <&tlmm 47 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + reg = <0x5>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux>; + actuator-src = <&actuator_triple_tele>; + eeprom-src = <&eeprom_triple_rear_aux>; + cam_vio-supply = <&pm6150_l13>; + cam_vana-supply = <&camera_vana1_2_ldo>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2850000 1200000 0>; + rgltr-max-voltage = <1800000 2850000 1200000 0>; + rgltr-load-current = <105000 0 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 29 0>, + <&tlmm 45 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@6 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + reg = <0x6>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_front>; + actuator-src = <&actuator_front>; + led-flash-src = <&led_flash_rear_aux2>; + cam_vio-supply = <&pm6150_l13>; + cam_vana-supply = <&camera_vana1_2_ldo>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2850000 1200000 0>; + rgltr-max-voltage = <1800000 2850000 1200000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 30 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-camera-sensor-qrd.dtsi b/arch/arm/boot/dts/qcom/sm6150-camera-sensor-qrd.dtsi new file mode 100644 index 000000000000..c3b5b219a615 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-camera-sensor-qrd.dtsi @@ -0,0 +1,364 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2 &pm6150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2 &pm6150l_switch2>; + status = "ok"; + }; + + led_flash_front: qcom,camera-flash@2 { + cell-index = <2>; + reg = <0x02 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash2>; + torch-source = <&pm6150l_torch2>; + switch-source = <&pm6150l_switch2>; + status = "ok"; + enable-active-high; + gpio = <&tlmm 38 0>; + pinctrl-names = "default"; + pinctrl-0 = <&flash_led3_front_en>; + }; + + camera_ldo: gpio-regulator@0 { + compatible = "regulator-fixed"; + reg = <0x00 0x00>; + regulator-name = "camera_ldo"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&pm6150l_gpios 3 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_sensor_dvdd_en>; + vin-supply = <&pm6150l_s8>; + }; + + camera_vana0_ldo: gpio-regulator@1 { + compatible = "regulator-fixed"; + reg = <0x01 0x00>; + regulator-name = "camera_vana0_ldo"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-enable-ramp-delay = <233>; + enable-active-high; + gpio = <&pm6150l_gpios 9 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_sensor_0_vana>; + vin-supply = <&pm6150l_bob>; + }; + + camera_vana1_2_ldo: gpio-regulator@2 { + compatible = "regulator-fixed"; + reg = <0x02 0x00>; + regulator-name = "camera_vana1_2_ldo"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-enable-ramp-delay = <233>; + enable-active-high; + gpio = <&pm6150l_gpios 4 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_sensor_1_2_vana>; + vin-supply = <&pm6150l_bob>; + }; +}; + +&cam_cci { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; + + actuator_rear: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm6150_l19>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + }; + + actuator_front: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm6150_l19>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + }; + + eeprom_rear: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm6150_l13>; + cam_vana-supply = <&camera_vana0_ldo>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm6150_l19>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2850000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 2850000 1200000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 28 0>, + <&tlmm 47 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm6150_l13>; + cam_vana-supply = <&camera_vana1_2_ldo>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm6150_l19>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2850000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 2850000 1200000 0 2800000>; + rgltr-load-current = <105000 0 80000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 29 0>, + <&tlmm 45 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm6150_l13>; + cam_vana-supply = <&camera_vana1_2_ldo>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm6150_l19>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2850000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 2850000 1200000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 30 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear>; + led-flash-src = <&led_flash_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&pm6150_l13>; + cam_vana-supply = <&camera_vana0_ldo>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2850000 1200000 0>; + rgltr-max-voltage = <1800000 2850000 1200000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 28 0>, + <&tlmm 47 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + cam_vio-supply = <&pm6150_l13>; + cam_vana-supply = <&camera_vana1_2_ldo>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2850000 1200000 0>; + rgltr-max-voltage = <1800000 2850000 1200000 0>; + rgltr-load-current = <105000 0 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 29 0>, + <&tlmm 45 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + actuator-src = <&actuator_front>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&pm6150_l13>; + cam_vana-supply = <&camera_vana1_2_ldo>; + cam_vdig-supply = <&camera_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2850000 1200000 0>; + rgltr-max-voltage = <1800000 2850000 1200000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 30 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll-camera.dtsi b/arch/arm/boot/dts/qcom/sm6150-camera.dtsi similarity index 76% rename from arch/arm64/boot/dts/qcom/atoll-camera.dtsi rename to arch/arm/boot/dts/qcom/sm6150-camera.dtsi index 020032d19482..dee2b7f4a71f 100644 --- a/arch/arm64/boot/dts/qcom/atoll-camera.dtsi +++ b/arch/arm/boot/dts/qcom/sm6150-camera.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -19,22 +19,16 @@ cam_csiphy0: qcom,csiphy@ac65000 { cell-index = <0>; - compatible = "qcom,csiphy-v1.2.2", "qcom,csiphy"; + compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; reg = <0x0ac65000 0x1000>; reg-names = "csiphy"; reg-cam-base = <0x65000>; interrupts = <0 477 0>; interrupt-names = "csiphy"; - regulator-names = "gdscr", "refgen", - "mipi-csi-vdd1", "mipi-csi-vdd2"; + regulator-names = "gdscr"; gdscr-supply = <&titan_top_gdsc>; - refgen-supply = <&refgen>; - mipi-csi-vdd1-supply = <&L4A>; - mipi-csi-vdd2-supply = <&L3C>; - rgltr-cntrl-support; - rgltr-min-voltage = <0 0 900000 1200000>; - rgltr-max-voltage = <0 0 900000 1200000>; - rgltr-load-current = <0 0 80000 80000>; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&pm6150l_l3>; clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, <&clock_camcc CAM_CC_SOC_AHB_CLK>, <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, @@ -52,32 +46,25 @@ "csi0phytimer_clk_src", "csi0phytimer_clk"; src-clock-name = "csi0phytimer_clk_src"; - clock-cntl-level = "svs", "svs_l1", "turbo"; + clock-cntl-level = "svs_l1", "turbo"; clock-rates = - <0 0 0 0 270000000 0 300000000 0>, - <0 0 0 0 360000000 0 300000000 0>, - <0 0 0 0 360000000 0 300000000 0>; + <0 0 0 0 269333333 0 269333333 0>, + <0 0 0 0 384000000 0 269333333 0>; status = "ok"; }; cam_csiphy1: qcom,csiphy@ac66000{ cell-index = <1>; - compatible = "qcom,csiphy-v1.2.2", "qcom,csiphy"; + compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; reg = <0xac66000 0x1000>; reg-names = "csiphy"; reg-cam-base = <0x66000>; interrupts = <0 478 0>; interrupt-names = "csiphy"; - regulator-names = "gdscr", "refgen", - "mipi-csi-vdd1", "mipi-csi-vdd2"; + regulator-names = "gdscr"; gdscr-supply = <&titan_top_gdsc>; - refgen-supply = <&refgen>; - mipi-csi-vdd1-supply = <&L4A>; - mipi-csi-vdd2-supply = <&L3C>; - rgltr-cntrl-support; - rgltr-min-voltage = <0 0 900000 1200000>; - rgltr-max-voltage = <0 0 900000 1200000>; - rgltr-load-current = <0 0 80000 80000>; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&pm6150l_l3>; clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, <&clock_camcc CAM_CC_SOC_AHB_CLK>, <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, @@ -95,32 +82,26 @@ "csi1phytimer_clk_src", "csi1phytimer_clk"; src-clock-name = "csi1phytimer_clk_src"; - clock-cntl-level = "svs", "svs_l1", "turbo"; + clock-cntl-level = "svs_l1", "turbo"; clock-rates = - <0 0 0 0 270000000 0 300000000 0>, - <0 0 0 0 360000000 0 300000000 0>, - <0 0 0 0 360000000 0 300000000 0>; + <0 0 0 0 269333333 0 269333333 0>, + <0 0 0 0 384000000 0 269333333 0>; + status = "ok"; }; cam_csiphy2: qcom,csiphy@ac67000 { cell-index = <2>; - compatible = "qcom,csiphy-v1.2.2", "qcom,csiphy"; + compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; reg = <0xac67000 0x1000>; reg-names = "csiphy"; reg-cam-base = <0x67000>; interrupts = <0 479 0>; interrupt-names = "csiphy"; - regulator-names = "gdscr", "refgen", - "mipi-csi-vdd1", "mipi-csi-vdd2"; + regulator-names = "gdscr"; gdscr-supply = <&titan_top_gdsc>; - refgen-supply = <&refgen>; - mipi-csi-vdd1-supply = <&L4A>; - mipi-csi-vdd2-supply = <&L3C>; - rgltr-cntrl-support; - rgltr-min-voltage = <0 0 900000 1200000>; - rgltr-max-voltage = <0 0 900000 1200000>; - rgltr-load-current = <0 0 80000 80000>; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&pm6150l_l3>; clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, <&clock_camcc CAM_CC_SOC_AHB_CLK>, <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, @@ -138,65 +119,23 @@ "csi2phytimer_clk_src", "csi2phytimer_clk"; src-clock-name = "csi2phytimer_clk_src"; - clock-cntl-level = "svs", "svs_l1", "turbo"; - clock-rates = - <0 0 0 0 270000000 0 300000000 0>, - <0 0 0 0 360000000 0 300000000 0>, - <0 0 0 0 360000000 0 300000000 0>; - status = "ok"; - }; - - cam_csiphy3: qcom,csiphy@ac68000 { - cell-index = <2>; - compatible = "qcom,csiphy-v1.2.2", "qcom,csiphy"; - reg = <0xac68000 0x1000>; - reg-names = "csiphy"; - reg-cam-base = <0x68000>; - interrupts = <0 461 0>; - interrupt-names = "csiphy"; - regulator-names = "gdscr", "refgen", - "mipi-csi-vdd1", "mipi-csi-vdd2"; - gdscr-supply = <&titan_top_gdsc>; - refgen-supply = <&refgen>; - mipi-csi-vdd1-supply = <&L4A>; - mipi-csi-vdd2-supply = <&L3C>; - rgltr-cntrl-support; - rgltr-min-voltage = <0 0 900000 1200000>; - rgltr-max-voltage = <0 0 900000 1200000>; - rgltr-load-current = <0 0 80000 80000>; - clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, - <&clock_camcc CAM_CC_SOC_AHB_CLK>, - <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, - <&clock_camcc CAM_CC_CPAS_AHB_CLK>, - <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, - <&clock_camcc CAM_CC_CSIPHY3_CLK>, - <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, - <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>; - clock-names = "camnoc_axi_clk", - "soc_ahb_clk", - "slow_ahb_src_clk", - "cpas_ahb_clk", - "cphy_rx_clk_src", - "csiphy3_clk", - "csi3phytimer_clk_src", - "csi3phytimer_clk"; - src-clock-name = "csi3phytimer_clk_src"; - clock-cntl-level = "svs", "svs_l1", "turbo"; + clock-cntl-level = "svs_l1", "turbo"; clock-rates = - <0 0 0 0 270000000 0 300000000 0>, - <0 0 0 0 360000000 0 300000000 0>, - <0 0 0 0 360000000 0 300000000 0>; + <0 0 0 0 269333333 0 269333333 0>, + <0 0 0 0 384000000 0 269333333 0>; status = "ok"; }; - cam_cci0: qcom,cci@ac4a000 { + cam_cci: qcom,cci@ac4a000 { cell-index = <0>; compatible = "qcom,cci"; - reg = <0xac4a000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xac4a000 0x4000>; reg-names = "cci"; reg-cam-base = <0x4a000>; interrupt-names = "cci"; - interrupts = <0 468 0>; + interrupts = <0 460 0>; status = "ok"; gdscr-supply = <&titan_top_gdsc>; regulator-names = "gdscr"; @@ -204,8 +143,8 @@ <&clock_camcc CAM_CC_SOC_AHB_CLK>, <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, <&clock_camcc CAM_CC_CPAS_AHB_CLK>, - <&clock_camcc CAM_CC_CCI_0_CLK>, - <&clock_camcc CAM_CC_CCI_0_CLK_SRC>; + <&clock_camcc CAM_CC_CCI_CLK>, + <&clock_camcc CAM_CC_CCI_CLK_SRC>; clock-names = "camnoc_axi_clk", "soc_ahb_clk", "slow_ahb_src_clk", @@ -218,10 +157,10 @@ pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cci0_active &cci1_active>; pinctrl-1 = <&cci0_suspend &cci1_suspend>; - gpios = <&tlmm 17 0>, - <&tlmm 18 0>, - <&tlmm 19 0>, - <&tlmm 20 0>; + gpios = <&tlmm 32 0>, + <&tlmm 33 0>, + <&tlmm 34 0>, + <&tlmm 35 0>; gpio-req-tbl-num = <0 1 2 3>; gpio-req-tbl-flags = <1 1 1 1>; gpio-req-tbl-label = "CCI_I2C_DATA0", @@ -290,105 +229,6 @@ }; }; - cam_cci1: qcom,cci@ac4b000 { - cell-index = <1>; - compatible = "qcom,cci"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xac4b000 0x1000>; - reg-names = "cci"; - reg-cam-base = <0x4b000>; - interrupt-names = "cci"; - interrupts = <0 462 0>; - status = "ok"; - gdscr-supply = <&titan_top_gdsc>; - regulator-names = "gdscr"; - clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, - <&clock_camcc CAM_CC_SOC_AHB_CLK>, - <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, - <&clock_camcc CAM_CC_CPAS_AHB_CLK>, - <&clock_camcc CAM_CC_CCI_1_CLK>, - <&clock_camcc CAM_CC_CCI_1_CLK_SRC>; - clock-names = "camnoc_axi_clk", - "soc_ahb_clk", - "slow_ahb_src_clk", - "cpas_ahb_clk", - "cci_clk", - "cci_clk_src"; - src-clock-name = "cci_clk_src"; - clock-cntl-level = "lowsvs"; - clock-rates = <0 0 0 0 0 37500000>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cci2_active>; - pinctrl-1 = <&cci2_suspend>; - gpios = <&tlmm 27 0>, - <&tlmm 28 0>; - gpio-req-tbl-num = <0 1>; - gpio-req-tbl-flags = <1 1>; - gpio-req-tbl-label = "CCI_I2C_DATA2", - "CCI_I2C_CLK2"; - - i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { - hw-thigh = <201>; - hw-tlow = <174>; - hw-tsu-sto = <204>; - hw-tsu-sta = <231>; - hw-thd-dat = <22>; - hw-thd-sta = <162>; - hw-tbuf = <227>; - hw-scl-stretch-en = <0>; - hw-trdhld = <6>; - hw-tsp = <3>; - cci-clk-src = <37500000>; - status = "ok"; - }; - - i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { - hw-thigh = <38>; - hw-tlow = <56>; - hw-tsu-sto = <40>; - hw-tsu-sta = <40>; - hw-thd-dat = <22>; - hw-thd-sta = <35>; - hw-tbuf = <62>; - hw-scl-stretch-en = <0>; - hw-trdhld = <6>; - hw-tsp = <3>; - cci-clk-src = <37500000>; - status = "ok"; - }; - - i2c_freq_custom_cci1: qcom,i2c_custom_mode { - hw-thigh = <38>; - hw-tlow = <56>; - hw-tsu-sto = <40>; - hw-tsu-sta = <40>; - hw-thd-dat = <22>; - hw-thd-sta = <35>; - hw-tbuf = <62>; - hw-scl-stretch-en = <1>; - hw-trdhld = <6>; - hw-tsp = <3>; - cci-clk-src = <37500000>; - status = "ok"; - }; - - i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { - hw-thigh = <16>; - hw-tlow = <22>; - hw-tsu-sto = <17>; - hw-tsu-sta = <18>; - hw-thd-dat = <16>; - hw-thd-sta = <15>; - hw-tbuf = <24>; - hw-scl-stretch-en = <0>; - hw-trdhld = <3>; - hw-tsp = <3>; - cci-clk-src = <37500000>; - status = "ok"; - }; - }; - qcom,cam_smmu { compatible = "qcom,msm-cam-smmu"; status = "ok"; @@ -461,7 +301,7 @@ msm_cam_smmu_icp { compatible = "qcom,msm-cam-smmu-cb"; - iommus = <&apps_smmu 0x0ce2 0x0>, + iommus = <&apps_smmu 0x0de2 0x0>, <&apps_smmu 0x0c80 0x0>, <&apps_smmu 0x0ca0 0x0>, <&apps_smmu 0x0d00 0x0>, @@ -519,8 +359,8 @@ msm_cam_smmu_cpas_cdm { compatible = "qcom,msm-cam-smmu-cb"; - iommus = <&apps_smmu 0x0d60 0x0>, - <&apps_smmu 0x0d61 0x0>; + iommus = <&apps_smmu 0x0c00 0x0>, + <&apps_smmu 0x0c01 0x0>; label = "cpas-cdm0"; cpas_cdm_iova_mem_map: iova-mem-map { iova-mem-region-io { @@ -553,7 +393,7 @@ reg-cam-base = <0x40000 0x42000>; interrupt-names = "cpas_camnoc"; interrupts = <0 459 0>; - qcom,cpas-hw-ver = <0x150110>; /* Titan v150 v1.1.0 */ + qcom,cpas-hw-ver = <0x150100>; /* Titan v150 v1.0.0 */ camnoc-axi-min-ib-bw = <3000000000>; regulator-names = "camss-vdd"; camss-vdd-supply = <&titan_top_gdsc>; @@ -575,26 +415,29 @@ <0 0 0 80000000 0 0>, <0 0 0 80000000 0 0>, <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>, <0 0 0 80000000 0 0>; - clock-cntl-level = "suspend", "lowsvs", "svs", + clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", "svs_l1", "nominal", "turbo"; - //qcom,cam-cx-ipeak = <&cx_ipeak_lm 2>; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 2>; qcom,msm-bus,name = "cam_ahb"; - qcom,msm-bus,num-cases = <6>; + qcom,msm-bus,num-cases = <7>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = , , + MSM_BUS_SLAVE_CAMERA_CFG 0 76500>, + , , + MSM_BUS_SLAVE_CAMERA_CFG 0 150000>, , + MSM_BUS_SLAVE_CAMERA_CFG 0 150000>, , + MSM_BUS_SLAVE_CAMERA_CFG 0 300000>, ; + MSM_BUS_SLAVE_CAMERA_CFG 0 300000>; vdd-corners = ; vdd-corner-ahb-mapping = "suspend", "suspend", - "lowsvs", "lowsvs", "svs", "svs_l1", + "minsvs", "lowsvs", "svs", "svs_l1", "nominal", "nominal", "nominal", "turbo", "turbo"; client-id-based; client-names = - "csiphy0", "csiphy1", "csiphy2", "csiphy3", - "csid0", "csid1", "csid2", "cci0", + "csiphy0", "csiphy1", "csiphy2", "cci0", + "csid0", "csid1", "csid2", "ife0", "ife1", "ife2", "ipe0", "ipe1", "cam-cdm-intf0", "cpas-cdm0", "bps0", "icp0", "jpeg-dma0", "jpeg-enc0", "lrmecpas0"; - client-axi-port-names = - "cam_hf_1", "cam_hf_2", "cam_hf_2", "cam_hf_2", + client-axi-port-names = "cam_hf_1", "cam_hf_2", "cam_hf_2", "cam_sf_1", + "cam_hf_1", "cam_hf_2", "cam_hf_2", "cam_hf_1", "cam_hf_2", "cam_hf_2", "cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1"; @@ -703,117 +546,6 @@ }; }; - - qcom,cam-icp { - compatible = "qcom,cam-icp"; - compat-hw-name = "qcom,a5", - "qcom,ipe0", - "qcom,bps"; - num-a5 = <1>; - num-ipe = <1>; - num-bps = <1>; - icp_pc_en; - status = "ok"; - }; - - cam_a5: qcom,a5@ac00000 { - cell-index = <0>; - compatible = "qcom,cam-a5"; - reg = <0xac00000 0x6000>, - <0xac10000 0x8000>, - <0xac18000 0x3000>; - reg-names = "a5_qgic", "a5_sierra", "a5_csr"; - reg-cam-base = <0x00000 0x10000 0x18000>; - interrupts = <0 463 0>; - interrupt-names = "a5"; - regulator-names = "camss-vdd"; - camss-vdd-supply = <&titan_top_gdsc>; - clock-names = "gcc_cam_ahb_clk", - "gcc_cam_axi_clk", - "soc_fast_ahb", - "soc_ahb_clk", - "cpas_ahb_clk", - "camnoc_axi_clk", - "icp_clk", - "icp_clk_src"; - clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, - <&clock_gcc GCC_CAMERA_HF_AXI_CLK>, - <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, - <&clock_camcc CAM_CC_SOC_AHB_CLK>, - <&clock_camcc CAM_CC_CPAS_AHB_CLK>, - <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, - <&clock_camcc CAM_CC_ICP_CLK>, - <&clock_camcc CAM_CC_ICP_CLK_SRC>; - - clock-rates = - <0 0 200000000 0 0 0 0 360000000>, - <0 0 200000000 0 0 0 0 600000000>; - clock-cntl-level = "svs", "turbo"; - fw_name = "CAMERA_ICP.elf"; - ubwc-cfg = <0x73 0x1CF>; - status = "ok"; - }; - - cam_ipe0: qcom,ipe0 { - cell-index = <0>; - compatible = "qcom,cam-ipe"; - reg = <0xac87000 0x3000>; - reg-names = "ipe0_top"; - reg-cam-base = <0x87000>; - regulator-names = "ipe0-vdd"; - ipe0-vdd-supply = <&ipe_0_gdsc>; - clock-names = "ipe_0_ahb_clk", - "ipe_0_areg_clk", - "ipe_0_axi_clk", - "ipe_0_clk", - "ipe_0_clk_src"; - src-clock-name = "ipe_0_clk_src"; - clocks = <&clock_camcc CAM_CC_IPE_0_AHB_CLK>, - <&clock_camcc CAM_CC_IPE_0_AREG_CLK>, - <&clock_camcc CAM_CC_IPE_0_AXI_CLK>, - <&clock_camcc CAM_CC_IPE_0_CLK>, - <&clock_camcc CAM_CC_IPE_0_CLK_SRC>; - - clock-rates = - <0 0 0 0 360000000>, - <0 0 0 0 432000000>, - <0 0 0 0 540000000>, - <0 0 0 0 600000000>; - clock-cntl-level = "svs", - "svs_l1", "nominal", "turbo"; - status = "ok"; - }; - - cam_bps: qcom,bps { - cell-index = <0>; - compatible = "qcom,cam-bps"; - reg = <0xac6f000 0x3000>; - reg-names = "bps_top"; - reg-cam-base = <0x6f000>; - regulator-names = "bps-vdd"; - bps-vdd-supply = <&bps_gdsc>; - clock-names = "bps_ahb_clk", - "bps_areg_clk", - "bps_axi_clk", - "bps_clk", - "bps_clk_src"; - src-clock-name = "bps_clk_src"; - clocks = <&clock_camcc CAM_CC_BPS_AHB_CLK>, - <&clock_camcc CAM_CC_BPS_AREG_CLK>, - <&clock_camcc CAM_CC_BPS_AXI_CLK>, - <&clock_camcc CAM_CC_BPS_CLK>, - <&clock_camcc CAM_CC_BPS_CLK_SRC>; - - clock-rates = - <0 0 0 0 360000000>, - <0 0 0 0 432000000>, - <0 0 0 0 480000000>, - <0 0 0 0 600000000>; - clock-cntl-level = "svs", - "svs_l1", "nominal", "turbo"; - status = "ok"; - }; - qcom,cam-cdm-intf { compatible = "qcom,cam-cdm-intf"; cell-index = <0>; @@ -833,7 +565,7 @@ reg = <0xac48000 0x1000>; reg-names = "cpas-cdm"; reg-cam-base = <0x48000>; - interrupts = <0 469 0>; + interrupts = <0 461 0>; interrupt-names = "cpas-cdm"; regulator-names = "camss"; camss-supply = <&titan_top_gdsc>; @@ -897,11 +629,10 @@ <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; clock-rates = - <0 0 0 0 0 0 270000000 0 0 0 360000000 0 0>, - <0 0 0 0 0 0 480000000 0 0 0 600000000 0 0>; - clock-cntl-level = "svs", "turbo"; + <0 0 0 0 0 0 320000000 0 0 0 432000000 0 0>, + <0 0 0 0 0 0 540000000 0 0 0 600000000 0 0>; + clock-cntl-level = "svs_l1", "turbo"; src-clock-name = "ife_csid_clk_src"; - ppi-enable; status = "ok"; }; @@ -938,12 +669,14 @@ clock-rates = <0 0 0 0 0 0 360000000 0 0>, <0 0 0 0 0 0 432000000 0 0>, + <0 0 0 0 0 0 540000000 0 0>, <0 0 0 0 0 0 600000000 0 0>; - clock-cntl-level = "svs", "svs_l1", "turbo"; + clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_clk_src"; clock-names-option = "ife_dsp_clk"; clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>; clock-rates-option = <600000000>; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 2>; status = "ok"; }; @@ -985,11 +718,10 @@ <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; clock-rates = - <0 0 0 0 0 0 270000000 0 0 0 360000000 0 0>, - <0 0 0 0 0 0 480000000 0 0 0 600000000 0 0>; - clock-cntl-level = "svs", "turbo"; + <0 0 0 0 0 0 320000000 0 0 0 432000000 0 0>, + <0 0 0 0 0 0 540000000 0 0 0 600000000 0 0>; + clock-cntl-level = "svs_l1", "turbo"; src-clock-name = "ife_csid_clk_src"; - ppi-enable; status = "ok"; }; @@ -1026,12 +758,14 @@ clock-rates = <0 0 0 0 0 0 360000000 0 0>, <0 0 0 0 0 0 432000000 0 0>, + <0 0 0 0 0 0 540000000 0 0>, <0 0 0 0 0 0 600000000 0 0>; - clock-cntl-level = "svs", "svs_l1", "turbo"; + clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_clk_src"; clock-names-option = "ife_dsp_clk"; clocks-option = <&clock_camcc CAM_CC_IFE_1_DSP_CLK>; clock-rates-option = <600000000>; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 2>; status = "ok"; }; @@ -1042,7 +776,7 @@ reg = <0xacc8000 0x1000>; reg-cam-base = <0xc8000>; interrupt-names = "csid-lite"; - interrupts = <0 473 0>; + interrupts = <0 468 0>; regulator-names = "camss"; camss-supply = <&titan_top_gdsc>; clock-names = "camera_ahb", @@ -1070,11 +804,10 @@ <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; clock-rates = - <0 0 0 0 0 0 270000000 0 0 0 360000000 0>, - <0 0 0 0 0 0 480000000 0 0 0 600000000 0>; - clock-cntl-level = "svs", "turbo"; + <0 0 0 0 0 0 320000000 0 0 0 432000000 0>, + <0 0 0 0 0 0 540000000 0 0 0 600000000 0>; + clock-cntl-level = "svs_l1", "turbo"; src-clock-name = "ife_csid_clk_src"; - ppi-enable; status = "ok"; }; @@ -1085,7 +818,7 @@ reg = <0xacc4000 0x4000>; reg-cam-base = <0xc4000>; interrupt-names = "ife-lite"; - interrupts = <0 472 0>; + interrupts = <0 469 0>; regulator-names = "camss"; camss-supply = <&titan_top_gdsc>; clock-names = "camera_ahb", @@ -1107,12 +840,127 @@ clock-rates = <0 0 0 0 0 0 360000000 0>, <0 0 0 0 0 0 432000000 0>, + <0 0 0 0 0 0 540000000 0>, <0 0 0 0 0 0 600000000 0>; - clock-cntl-level = "svs", "svs_l1", "turbo"; + clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ife_clk_src"; status = "ok"; }; + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,a5", + "qcom,ipe0", + "qcom,bps"; + num-a5 = <1>; + num-ipe = <1>; + num-bps = <1>; + icp_pc_en; + status = "ok"; + }; + + cam_a5: qcom,a5@ac00000 { + cell-index = <0>; + compatible = "qcom,cam-a5"; + reg = <0xac00000 0x6000>, + <0xac10000 0x8000>, + <0xac18000 0x3000>; + reg-names = "a5_qgic", "a5_sierra", "a5_csr"; + reg-cam-base = <0x00000 0x10000 0x18000>; + interrupts = <0 463 0>; + interrupt-names = "a5"; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = "gcc_cam_ahb_clk", + "gcc_cam_axi_clk", + "soc_fast_ahb", + "soc_ahb_clk", + "cpas_ahb_clk", + "camnoc_axi_clk", + "icp_clk", + "icp_clk_src"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_HF_AXI_CLK>, + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_ICP_CLK>, + <&clock_camcc CAM_CC_ICP_CLK_SRC>; + + clock-rates = + <0 0 200000000 0 0 0 0 360000000>, + <0 0 200000000 0 0 0 0 600000000>; + clock-cntl-level = "svs", "turbo"; + fw_name = "CAMERA_ICP.elf"; + ubwc-cfg = <0x73 0x1CF>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0 { + cell-index = <0>; + compatible = "qcom,cam-ipe"; + reg = <0xac87000 0x3000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x87000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&ipe_0_gdsc>; + clock-names = "ipe_0_ahb_clk", + "ipe_0_areg_clk", + "ipe_0_axi_clk", + "ipe_0_clk", + "ipe_0_clk_src"; + src-clock-name = "ipe_0_clk_src"; + clocks = <&clock_camcc CAM_CC_IPE_0_AHB_CLK>, + <&clock_camcc CAM_CC_IPE_0_AREG_CLK>, + <&clock_camcc CAM_CC_IPE_0_AXI_CLK>, + <&clock_camcc CAM_CC_IPE_0_CLK>, + <&clock_camcc CAM_CC_IPE_0_CLK_SRC>; + + clock-rates = + <0 0 0 0 360000000>, + <0 0 0 0 432000000>, + <0 0 0 0 480000000>, + <0 0 0 0 540000000>, + <0 0 0 0 600000000>; + clock-cntl-level = "svs", + "svs_l1", "nominal", "nominal_l1", "turbo"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 2>; + status = "ok"; + }; + + cam_bps: qcom,bps { + cell-index = <0>; + compatible = "qcom,cam-bps"; + reg = <0xac6f000 0x3000>; + reg-names = "bps_top"; + reg-cam-base = <0x6f000>; + regulator-names = "bps-vdd"; + bps-vdd-supply = <&bps_gdsc>; + clock-names = "bps_ahb_clk", + "bps_areg_clk", + "bps_axi_clk", + "bps_clk", + "bps_clk_src"; + src-clock-name = "bps_clk_src"; + clocks = <&clock_camcc CAM_CC_BPS_AHB_CLK>, + <&clock_camcc CAM_CC_BPS_AREG_CLK>, + <&clock_camcc CAM_CC_BPS_AXI_CLK>, + <&clock_camcc CAM_CC_BPS_CLK>, + <&clock_camcc CAM_CC_BPS_CLK_SRC>; + + clock-rates = + <0 0 0 0 360000000>, + <0 0 0 0 432000000>, + <0 0 0 0 480000000>, + <0 0 0 0 540000000>, + <0 0 0 0 600000000>; + clock-cntl-level = "svs", + "svs_l1", "nominal", "nominal_l1", "turbo"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 2>; + status = "ok"; + }; + qcom,cam-jpeg { compatible = "qcom,cam-jpeg"; compat-hw-name = "qcom,jpegenc", @@ -1153,7 +1001,7 @@ status = "ok"; }; - cam_jpeg_dma: qcom,jpegdma@ac52000 { + cam_jpeg_dma: qcom,jpegdma@ac52000{ cell-index = <0>; compatible = "qcom,cam_jpeg_dma"; reg-names = "jpegdma_hw"; @@ -1184,63 +1032,45 @@ status = "ok"; }; - cam_ppi0: qcom,ppi0@ace0000 { - cell-index = <0>; - compatible = "qcom,ppi170"; - reg-names = "ppi"; - reg = <0xace0000 0x200>; - reg-cam-base = <0xe0000>; - interrupt-names = "ppi"; - interrupts = <0 170 0>; - clocks = <&clock_camcc CAM_CC_CSIPHY0_CLK>; - clock-names = "csiphy0_clk"; - clock-cntl-level = "svs"; - clock-rates = <0>; + qcom,cam-lrme { + compatible = "qcom,cam-lrme"; + arch-compat = "lrme"; status = "ok"; }; - cam_ppi1: qcom,ppi0@ace0200 { - cell-index = <1>; - compatible = "qcom,ppi170"; - reg-names = "ppi"; - reg = <0xace0200 0x200>; - reg-cam-base = <0xe0200>; - interrupt-names = "ppi"; - interrupts = <0 171 0>; - clocks = <&clock_camcc CAM_CC_CSIPHY1_CLK>; - clock-names = "csiphy1_clk"; - clock-cntl-level = "svs"; - clock-rates = <0>; - status = "ok"; - }; - - cam_ppi2: qcom,ppi0@ace0400 { - cell-index = <2>; - compatible = "qcom,ppi170"; - reg-names = "ppi"; - reg = <0xace0400 0x200>; - reg-cam-base = <0xe0400>; - interrupt-names = "ppi"; - interrupts = <0 172 0>; - clocks = <&clock_camcc CAM_CC_CSIPHY2_CLK>; - clock-names = "csiphy2_clk"; - clock-cntl-level = "svs"; - clock-rates = <0>; - status = "ok"; - }; - - cam_ppi3: qcom,ppi0@ace0600 { - cell-index = <3>; - compatible = "qcom,ppi170"; - reg-names = "ppi"; - reg = <0xace0600 0x200>; - reg-cam-base = <0xe00600>; - interrupt-names = "ppi"; - interrupts = <0 173 0>; - clocks = <&clock_camcc CAM_CC_CSIPHY3_CLK>; - clock-names = "csiphy3_clk"; - clock-cntl-level = "svs"; - clock-rates = <0>; + cam_lrme: qcom,lrme@ac6b000 { + cell-index = <0>; + compatible = "qcom,lrme"; + reg-names = "lrme"; + reg = <0xac6b000 0xa00>; + reg-cam-base = <0x6b000>; + interrupt-names = "lrme"; + interrupts = <0 476 0>; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = "camera_ahb", + "camera_axi", + "soc_ahb_clk", + "cpas_ahb_clk", + "camnoc_axi_clk", + "lrme_clk_src", + "lrme_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_HF_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_LRME_CLK_SRC>, + <&clock_camcc CAM_CC_LRME_CLK>; + clock-rates = <0 0 0 0 0 200000000 200000000>, + <0 0 0 0 0 216000000 216000000>, + <0 0 0 0 0 300000000 300000000>, + <0 0 0 0 0 404000000 404000000>, + <0 0 0 0 0 404000000 404000000>, + <0 0 0 0 0 404000000 404000000>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "nominal_l1", "turbo"; + src-clock-name = "lrme_clk_src"; status = "ok"; }; }; diff --git a/arch/arm/boot/dts/qcom/sm6150-cmd-mode-display-idp-overlay.dts b/arch/arm/boot/dts/qcom/sm6150-cmd-mode-display-idp-overlay.dts new file mode 100644 index 000000000000..8ac43d86f11f --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-cmd-mode-display-idp-overlay.dts @@ -0,0 +1,62 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "sm6150-idp.dtsi" +#include "sm6150-audio-overlay.dtsi" + +/ { + model = "Command mode display IDP"; + compatible = "qcom,sm6150-idp", "qcom,sm6150", "qcom,idp"; + qcom,msm-id = <355 0x0>; + qcom,board-id = <34 3>; +}; + +&qupv3_se1_i2c { + synaptics_dsx@20 { + compatible = "synaptics,dsx-i2c"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <89 0x2008>; + vdd-supply = <&pm6150_l10>; + avdd-supply = <&pm6150l_l7>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + synaptics,pwr-reg-name = "avdd"; + synaptics,bus-reg-name = "vdd"; + synaptics,ub-i2c-addr = <0x20>; + synaptics,max-y-for-2d = <2159>; + synaptics,irq-gpio = <&tlmm 89 0x2008>; + synaptics,reset-gpio = <&tlmm 88 0x0>; + synaptics,irq-on-state = <0>; + synaptics,power-delay-ms = <200>; + synaptics,reset-delay-ms = <200>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + }; + + himax_ts@48 { + status = "disabled"; + }; +}; + +&dsi_td4328_truly_cmd_display { + qcom,dsi-display-active; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-cmd-mode-display-idp.dts b/arch/arm/boot/dts/qcom/sm6150-cmd-mode-display-idp.dts new file mode 100644 index 000000000000..3cc83ced91fb --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-cmd-mode-display-idp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm6150.dtsi" +#include "sm6150-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM6150 PM6150 Command mode display IDP"; + compatible = "qcom,sm6150-idp", "qcom,sm6150", "qcom,idp"; + qcom,board-id = <34 3>; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-coresight.dtsi b/arch/arm/boot/dts/qcom/sm6150-coresight.dtsi new file mode 100644 index 000000000000..0ff0dcc8dd69 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-coresight.dtsi @@ -0,0 +1,2774 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + csr: csr@6001000 { + compatible = "qcom,coresight-csr"; + reg = <0x6001000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-csr"; + qcom,usb-bam-support; + qcom,hwctrl-set-support; + qcom,set-byte-cntr-support; + + qcom,blk-size = <1>; + }; + + replicator_qdss: replicator@6046000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b909>; + + reg = <0x6046000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-qdss"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator0_out_tmc_etr: endpoint { + remote-endpoint= + <&tmc_etr_in_replicator0>; + }; + }; + + port@1 { + reg = <1>; + replicator0_out_replicator1_in: endpoint { + remote-endpoint= + <&replicator1_in_replicator0_out>; + }; + }; + + port@2 { + reg = <0>; + replicator0_in_tmc_etf: endpoint { + slave-mode; + remote-endpoint= + <&tmc_etf_out_replicator0>; + }; + }; + }; + }; + + replicator_qdss1: replicator@604a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b909>; + + reg = <0x604a000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-qdss1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <1>; + replicator1_out_funnel_swao: endpoint { + remote-endpoint= + <&funnel_swao_in_replicator1_out>; + }; + }; + + port@1 { + reg = <1>; + replicator1_in_replicator0_out: endpoint { + slave-mode; + remote-endpoint= + <&replicator0_out_replicator1_in>; + }; + }; + }; + }; + + tmc_etr: tmc@6048000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + reg = <0x6048000 0x1000>, + <0x6064000 0x15000>; + reg-names = "tmc-base", "bam-base"; + + qcom,smmu-s1-bypass; + iommus = <&apps_smmu 0x01e0 0>, + <&apps_smmu 0x00a0 0>; + arm,buffer-size = <0x400000>; + + coresight-name = "coresight-tmc-etr"; + coresight-ctis = <&cti0>; + coresight-csr = <&csr>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + port { + tmc_etr_in_replicator0: endpoint { + slave-mode; + remote-endpoint = <&replicator0_out_tmc_etr>; + }; + }; + }; + + tmc_etf: tmc@6047000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + + reg = <0x6047000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etf"; + coresight-ctis = <&cti0>; + coresight-csr = <&csr>; + arm,default-sink; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tmc_etf_out_replicator0: endpoint { + remote-endpoint = + <&replicator0_in_tmc_etf>; + }; + }; + + port@1 { + reg = <0>; + tmc_etf_in_funnel_merg: endpoint { + slave-mode; + remote-endpoint = + <&funnel_merg_out_tmc_etf>; + }; + }; + }; + + }; + + funnel_merg: funnel@6045000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6045000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-merg"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_merg_out_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_in_funnel_merg>; + }; + }; + + port@1 { + reg = <0>; + funnel_merg_in_funnel_in0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in0_out_funnel_merg>; + }; + }; + + port@2 { + reg = <1>; + funnel_merg_in_funnel_in1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in1_out_funnel_merg>; + }; + }; + }; + }; + + funnel_in0: funnel@6041000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6041000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in0_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in0>; + }; + }; + + port@1 { + reg = <6>; + funnel_in0_in_funnel_qatb: endpoint { + slave-mode; + remote-endpoint = + <&funnel_qatb_out_funnel_in0>; + }; + }; + + port@2 { + reg = <7>; + funnel_in0_in_stm: endpoint { + slave-mode; + remote-endpoint = <&stm_out_funnel_in0>; + }; + }; + }; + }; + + funnel_qatb: funnel@6005000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6005000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-qatb"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_qatb_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_qatb>; + }; + }; + + port@1 { + reg = <0>; + funnel_qatb_in_tpda: endpoint { + slave-mode; + remote-endpoint = + <&tpda_out_funnel_qatb>; + }; + }; + + port@2 { + reg = <5>; + funnel_qatb_in_funnel_monaq_1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_monaq_1_out_funnel_qatb>; + }; + }; + + port@3 { + reg = <7>; + funnel_qatb_in_funnel_turing_1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_turing_1_out_funnel_qatb>; + }; + }; + }; + }; + + tpda: tpda@6004000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6004000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda"; + + qcom,tpda-atid = <65>; + qcom,bc-elem-size = <10 32>, + <13 32>; + qcom,tc-elem-size = <13 32>; + qcom,dsb-elem-size = <0 32>, + <2 32>, + <3 32>, + <5 32>, + <6 32>, + <10 32>, + <11 32>, + <13 32>; + qcom,cmb-elem-size = <3 64>, + <7 64>, + <13 64>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_tpda>; + }; + + }; + + port@1 { + reg = <0>; + tpda_in_tpdm_center: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_center_out_tpda>; + }; + }; + + port@2 { + reg = <4>; + tpda_in_funnel_monaq: endpoint { + slave-mode; + remote-endpoint = + <&funnel_monaq_out_tpda>; + }; + }; + + port@3 { + reg = <5>; + tpda_in_funnel_ddr_0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_ddr_0_out_tpda>; + }; + }; + + port@4 { + reg = <6>; + tpda_in_funnel_turing: endpoint { + slave-mode; + remote-endpoint = + <&funnel_turing_out_tpda>; + }; + }; + + port@5 { + reg = <7>; + tpda_in_tpdm_vsense: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_vsense_out_tpda>; + }; + }; + + port@6 { + reg = <8>; + tpda_in_tpdm_dcc: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dcc_out_tpda>; + }; + }; + + port@7 { + reg = <9>; + tpda_in_tpdm_prng: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_prng_out_tpda>; + }; + }; + + port@8 { + reg = <11>; + tpda_in_tpdm_qm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_qm_out_tpda>; + }; + }; + + port@9 { + reg = <14>; + tpda_in_tpdm_pimem: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_pimem_out_tpda>; + }; + }; + + port@10 { + reg = <12>; + tpda_in_tpdm_west: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_west_out_tpda>; + }; + }; + }; + }; + + tpdm_wcss: tpdm@699c000 { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-tpdm-wcss"; + qcom,dummy-source; + + port { + tpdm_wcss_out_funnel_in1: endpoint { + remote-endpoint = <&funnel_in1_in_tpdm_wcss>; + }; + }; + }; + + tpdm_west: tpdm@6b48000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6b48000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-west"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_west_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_west>; + }; + }; + }; + + tpdm_center: tpdm@6c28000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6c28000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-center"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_center_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_center>; + }; + }; + }; + + funnel_monaq: funnel@69c3000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x69c3000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-monaq"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_monaq_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_funnel_monaq>; + }; + }; + + port@1 { + reg = <0>; + funnel_monaq_in_tpdm_monaq: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_monaq_out_funnel_monaq>; + }; + }; + }; + }; + + funnel_monaq1: funnel_1@69c3000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x69c1000 0x1>, + <0x69c3000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + + coresight-name = "coresight-funnel-monaq1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + qcom,duplicate-funnel; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_monaq_1_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_funnel_monaq_1>; + }; + }; + + port@1 { + reg = <1>; + funnel_monaq_1_in_audio_etm0: endpoint { + slave-mode; + remote-endpoint = + <&audio_etm0_out_funnel_monaq_1>; + }; + }; + + port@2 { + reg = <7>; + funnel_monaq_1_in_funnel_modem: endpoint { + slave-mode; + remote-endpoint = + <&funnel_modem_out_funnel_monaq_1>; + }; + }; + + port@3 { + reg = <6>; + funnel_monaq_1_in_modem_etm0: endpoint { + slave-mode; + remote-endpoint = + <&modem_etm0_out_funnel_monaq_1>; + }; + }; + }; + }; + + funnel_modem: funnel@6832000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6832000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-modem"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_modem_out_funnel_monaq_1: endpoint { + remote-endpoint = + <&funnel_monaq_1_in_funnel_modem>; + }; + }; + + port@1 { + reg = <0>; + funnel_modem_in_tpda_modem: endpoint { + slave-mode; + remote-endpoint = + <&tpda_modem_out_funnel_modem>; + }; + }; + }; + }; + + tpda_modem: tpda@6831000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6831000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-modem"; + + qcom,tpda-atid = <67>; + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_modem_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_tpda_modem>; + }; + }; + + port@1 { + reg = <0>; + tpda_modem_in_tpdm_modem: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_modem_out_tpda_modem>; + }; + }; + }; + }; + + tpdm_modem: tpdm@6830000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6830000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-modem"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_modem_out_tpda_modem: endpoint { + remote-endpoint = + <&tpda_modem_in_tpdm_modem>; + }; + }; + }; + + modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem-etm0"; + qcom,inst-id = <2>; + + port { + modem_etm0_out_funnel_monaq_1: endpoint { + remote-endpoint = + <&funnel_monaq_1_in_modem_etm0>; + }; + }; + }; + + audio_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-audio-etm0"; + qcom,inst-id = <5>; + + port { + audio_etm0_out_funnel_monaq_1: endpoint { + remote-endpoint = + <&funnel_monaq_1_in_audio_etm0>; + }; + }; + }; + + tpdm_monaq: tpdm@69c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x69c0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-monaq"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_monaq_out_funnel_monaq: endpoint { + remote-endpoint = + <&funnel_monaq_in_tpdm_monaq>; + }; + }; + }; + + funnel_ddr_0: funnel@6a05000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6a05000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-ddr-0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ddr_0_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_funnel_ddr_0>; + }; + }; + + port@1 { + reg = <0>; + funnel_ddr_0_in_tpdm_ddr: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_ddr_out_funnel_ddr_0>; + }; + }; + }; + }; + + tpdm_ddr: tpdm@6a00000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6a00000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_ddr_out_funnel_ddr_0: endpoint { + remote-endpoint = <&funnel_ddr_0_in_tpdm_ddr>; + }; + }; + }; + + funnel_turing: funnel@6861000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6861000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-turing"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_turing_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_funnel_turing>; + }; + }; + + port@1 { + reg = <0>; + funnel_turing_in_tpdm_turing: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_turing_out_funnel_turing>; + }; + }; + }; + }; + + funnel_turing1: funnel_1@6861000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6867010 0x10>, + <0x6861000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + + coresight-name = "coresight-funnel-turing1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + qcom,duplicate-funnel; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_turing_1_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_funnel_turing_1>; + }; + }; + + port@1 { + reg = <1>; + funnel_turing_1_in_turing_etm0: endpoint { + slave-mode; + remote-endpoint = + <&turing_etm0_out_funnel_turing_1>; + }; + }; + }; + }; + + turing_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-turing-etm0"; + qcom,inst-id = <13>; + + port{ + turing_etm0_out_funnel_turing_1: endpoint { + remote-endpoint = + <&funnel_turing_1_in_turing_etm0>; + }; + }; + }; + + tpdm_turing: tpdm@6860000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6860000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-turing"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_turing_out_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_in_tpdm_turing>; + }; + }; + }; + + tpdm_vsense: tpdm@6840000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6840000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-vsense"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port{ + tpdm_vsense_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_vsense>; + }; + }; + }; + + tpdm_dcc: tpdm@6870000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6870000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dcc"; + + status = "disabled"; + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port{ + tpdm_dcc_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_dcc>; + }; + }; + }; + + tpdm_prng: tpdm@684c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x684c000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-prng"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port{ + tpdm_prng_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_prng>; + }; + }; + }; + + tpdm_qm: tpdm@69d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x69d0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-qm"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_qm_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_qm>; + }; + }; + }; + + tpdm_pimem: tpdm@6850000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6850000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-pimem"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_pimem_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_pimem>; + }; + }; + }; + + stm: stm@6002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b962>; + + reg = <0x6002000 0x1000>, + <0x16280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + coresight-name = "coresight-stm"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + stm_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_stm>; + }; + }; + + }; + + funnel_in1: funnel@6042000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6042000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in1_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in1>; + }; + }; + + port@1 { + reg = <3>; + funnel_in1_in_replicator_swao: endpoint { + slave-mode; + remote-endpoint = + <&replicator_swao_out_funnel_in1>; + }; + }; + + port@2 { + reg = <4>; + funnel_in1_in_tpdm_wcss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_wcss_out_funnel_in1>; + }; + }; + + port@3 { + reg = <7>; + funnel_in1_in_funnel_apss_merg: endpoint { + slave-mode; + remote-endpoint = + <&funnel_apss_merg_out_funnel_in1>; + }; + }; + }; + }; + + replicator_swao: replicator@6b0a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b909>; + + reg = <0x6b0a000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-swao"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* Always have EUD before funnel leading to ETR. If both + * sink are active we need to give preference to EUD + * over ETR + */ + port@0 { + reg = <1>; + replicator_swao_out_eud: endpoint { + remote-endpoint = + <&eud_in_replicator_swao>; + }; + }; + + port@1 { + reg = <0>; + replicator_swao_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_replicator_swao>; + }; + }; + + port@2 { + reg = <0>; + replicator_swao_in_tmc_etf_swao: endpoint { + slave-mode; + remote-endpoint = + <&tmc_etf_swao_out_replicator_swao>; + }; + }; + + }; + }; + + tmc_etf_swao: tmc@6b09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + + reg = <0x6b09000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etf-swao"; + coresight-csr = <&csr>; + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tmc_etf_swao_out_replicator_swao: endpoint { + remote-endpoint= + <&replicator_swao_in_tmc_etf_swao>; + }; + }; + + port@1 { + reg = <0>; + tmc_etf_swao_in_funnel_swao: endpoint { + slave-mode; + remote-endpoint= + <&funnel_swao_out_tmc_etf_swao>; + }; + }; + }; + + }; + + swao_csr: csr@6b0e000 { + compatible = "qcom,coresight-csr"; + reg = <0x6b0e000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-swao-csr"; + qcom,timestamp-support; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,blk-size = <1>; + }; + + funnel_swao:funnel@6b08000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6b08000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-swao"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_swao_out_tmc_etf_swao: endpoint { + remote-endpoint = + <&tmc_etf_swao_in_funnel_swao>; + }; + }; + + port@1 { + reg = <6>; + funnel_swao_in_replicator1_out: endpoint { + slave-mode; + remote-endpoint= + <&replicator1_out_funnel_swao>; + }; + }; + + port@2 { + reg = <7>; + funnel_swao_in_tpda_swao: endpoint { + slave-mode; + remote-endpoint= + <&tpda_swao_out_funnel_swao>; + }; + }; + }; + }; + + tpda_swao: tpda@6b01000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6b01000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-swao"; + + qcom,tpda-atid = <71>; + qcom,dsb-elem-size = <1 32>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_swao_out_funnel_swao: endpoint { + remote-endpoint = + <&funnel_swao_in_tpda_swao>; + }; + + }; + + port@1 { + reg = <0>; + tpda_swao_in_tpdm_swao0: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_swao0_out_tpda_swao>; + }; + }; + + port@2 { + reg = <1>; + tpda_swao_in_tpdm_swao1: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_swao1_out_tpda_swao>; + }; + + }; + }; + }; + + tpdm_swao0: tpdm@6b02000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + + reg = <0x6b02000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_swao0_out_tpda_swao: endpoint { + remote-endpoint = <&tpda_swao_in_tpdm_swao0>; + }; + }; + }; + + tpdm_swao1: tpdm@6b03000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6b03000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name="coresight-tpdm-swao-1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_swao1_out_tpda_swao: endpoint { + remote-endpoint = <&tpda_swao_in_tpdm_swao1>; + }; + }; + }; + + dummy_eud: dummy_sink { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-eud"; + + qcom,dummy-sink; + port { + eud_in_replicator_swao: endpoint { + slave-mode; + remote-endpoint = + <&replicator_swao_out_eud>; + }; + }; + }; + + cti0_dlct: cti@6c29000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6c29000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct_cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_dlct: cti@6c2a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6c2a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct_cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_ddr0: cti@6a02000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6a02000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_0_cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_ddr0: cti@6a03000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6a03000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_0_cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_ddr1: cti@6a10000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6a10000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_1_cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_ddr1: cti@6a11000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6a11000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_1_cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_mss_q6: cti@683b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x683b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-mss-q6"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_turing: cti@6867000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6867000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-turing"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti2_ssc_sdc: cti@6b10000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b10000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ssc_sdc_cti2"; + status = "disabled"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_ssc: cti@6b11000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b11000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ssc_cti1"; + status = "disabled"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_ssc_q6: cti@6b1b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b1b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ssc_q6_cti0"; + status = "disabled"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_ssc_noc: cti@6b1e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b1e000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ssc_noc"; + status = "disabled"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti6_ssc_noc: cti@6b1f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b1f000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ssc_noc_cti6"; + status = "disabled"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_swao: cti@6b04000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b04000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_swao: cti@6b05000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b05000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti2_swao: cti@6b06000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b06000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti3_swao: cti@6b07000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b07000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti3"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_aop_m3: cti@6b21000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b21000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-aop-m3"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_titan: cti@6c13000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6c13000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-titan"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_venus_arm9: cti@6c20000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6c20000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-venus-arm9"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_apss: cti@78e0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x78e0000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss_cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_apss: cti@78f0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x78f0000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss_cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti2_apss: cti@7900000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7900000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss_cti2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0: cti@6010000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6010000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti1: cti@6011000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6011000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti2: cti@6012000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6012000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti3: cti@6013000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6013000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti3"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti4: cti@6014000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6014000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti4"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti5: cti@6015000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6015000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti5"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti6: cti@6016000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6016000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti6"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti7: cti@6017000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6017000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti7"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti8: cti@6018000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6018000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti8"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti9: cti@6019000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6019000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti9"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti10: cti@601a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti10"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti11: cti@601b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti11"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti12: cti@601c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti12"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti13: cti@601d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601d000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti13"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti14: cti@601e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601e000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti14"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti15: cti@601f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601f000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti15"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti_cpu0: cti@7020000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7020000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu0"; + cpu = <&CPU0>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti_cpu1: cti@7120000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7120000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu1"; + cpu = <&CPU1>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu2: cti@7220000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7220000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu2"; + cpu = <&CPU2>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu3: cti@7320000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7320000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu3"; + cpu = <&CPU3>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu4: cti@7420000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7420000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu4"; + cpu = <&CPU4>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu5: cti@7520000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7520000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu5"; + cpu = <&CPU5>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu6: cti@7620000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7620000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu6"; + cpu = <&CPU6>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu7: cti@7720000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7720000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu7"; + cpu = <&CPU7>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + etm0: etm@7040000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7040000 0x1000>; + cpu = <&CPU0>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm0_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm0>; + }; + }; + }; + + etm1: etm@7140000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7140000 0x1000>; + cpu = <&CPU1>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm1_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm1>; + }; + }; + }; + + etm2: etm@7240000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7240000 0x1000>; + cpu = <&CPU2>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm2_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm2>; + }; + }; + }; + + etm3: etm@7340000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7340000 0x1000>; + cpu = <&CPU3>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm3"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm3_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm3>; + }; + }; + }; + + etm4: etm@7440000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7440000 0x1000>; + cpu = <&CPU4>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm4"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm4_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm4>; + }; + }; + }; + + etm5: etm@7540000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7540000 0x1000>; + cpu = <&CPU5>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm5"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm5_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm5>; + }; + }; + }; + + etm6: etm@7640000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7640000 0x1000>; + cpu = <&CPU6>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm6"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm6_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm6>; + }; + }; + }; + + etm7: etm@7740000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7740000 0x1000>; + cpu = <&CPU7>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm7"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm7_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm7>; + }; + }; + }; + + funnel_apss_merg: funnel@7810000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x7810000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss-merg"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss_merg_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_apss_merg>; + }; + }; + + port@1 { + reg = <0>; + funnel_apss_merg_in_funnel_apss: endpoint { + slave-mode; + remote-endpoint = + <&funnel_apss_out_funnel_apss_merg>; + }; + }; + + port@2 { + reg = <2>; + funnel_apss_merg_in_tpda_olc: endpoint { + slave-mode; + remote-endpoint = + <&tpda_olc_out_funnel_apss_merg>; + }; + }; + + port@3 { + reg = <3>; + funnel_apss_merg_in_tpda_llm_silver: endpoint { + slave-mode; + remote-endpoint = + <&tpda_llm_silver_out_funnel_apss_merg>; + }; + }; + + port@4 { + reg = <4>; + funnel_apss_merg_in_tpda_llm_gold: endpoint { + slave-mode; + remote-endpoint = + <&tpda_llm_gold_out_funnel_apss_merg>; + }; + }; + + port@5 { + reg = <5>; + funnel_apss_merg_in_tpda_apss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_apss_out_funnel_apss_merg>; + }; + }; + }; + }; + + tpda_olc: tpda@7832000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x7832000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-olc"; + + qcom,tpda-atid = <69>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_olc_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_tpda_olc>; + }; + }; + port@1 { + reg = <0>; + tpda_olc_in_tpdm_olc: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_olc_out_tpda_olc>; + }; + }; + }; + }; + + tpdm_olc: tpdm@7830000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x7830000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-olc"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port{ + tpdm_olc_out_tpda_olc: endpoint { + remote-endpoint = <&tpda_olc_in_tpdm_olc>; + }; + }; + }; + + tpda_apss: tpda@7862000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x7862000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-apss"; + + qcom,tpda-atid = <66>; + qcom,dsb-elem-size = <0 32>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_apss_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_tpda_apss>; + }; + }; + + port@1 { + reg = <0>; + tpda_apss_in_tpdm_apss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_apss_out_tpda_apss>; + }; + }; + }; + }; + + tpdm_apss: tpdm@7860000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x7860000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-apss"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_apss_out_tpda_apss: endpoint { + remote-endpoint = <&tpda_apss_in_tpdm_apss>; + }; + }; + }; + + tpda_llm_silver: tpda@78c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x78c0000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-llm-silver"; + + qcom,tpda-atid = <72>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_llm_silver_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_tpda_llm_silver>; + }; + }; + + port@1 { + reg = <0>; + tpda_llm_silver_in_tpdm_llm_silver: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_llm_silver_out_tpda_llm_silver>; + }; + }; + }; + }; + + tpdm_llm_silver: tpdm@78a0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x78a0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-llm-silver"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_llm_silver_out_tpda_llm_silver: endpoint { + remote-endpoint = + <&tpda_llm_silver_in_tpdm_llm_silver>; + }; + }; + }; + + tpda_llm_gold: tpda@78d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x78d0000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-llm-gold"; + + qcom,tpda-atid = <73>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_llm_gold_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_tpda_llm_gold>; + }; + }; + + port@1 { + reg = <0>; + tpda_llm_gold_in_tpdm_llm_gold: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_llm_gold_out_tpda_llm_gold>; + }; + }; + }; + }; + + tpdm_llm_gold: tpdm@78b0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x78b0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-llm-gold"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_llm_gold_out_tpda_llm_gold: endpoint { + remote-endpoint = + <&tpda_llm_gold_in_tpdm_llm_gold>; + }; + }; + }; + + funnel_apss: funnel@7800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x7800000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_funnel_apss>; + }; + }; + port@1 { + reg = <0>; + funnel_apss_in_etm0: endpoint { + slave-mode; + remote-endpoint = + <&etm0_out_funnel_apss>; + }; + }; + + port@2 { + reg = <1>; + funnel_apss_in_etm1: endpoint { + slave-mode; + remote-endpoint = + <&etm1_out_funnel_apss>; + }; + }; + + port@3 { + reg = <2>; + funnel_apss_in_etm2: endpoint { + slave-mode; + remote-endpoint = + <&etm2_out_funnel_apss>; + }; + }; + + port@4 { + reg = <3>; + funnel_apss_in_etm3: endpoint { + slave-mode; + remote-endpoint = + <&etm3_out_funnel_apss>; + }; + }; + + port@5 { + reg = <4>; + funnel_apss_in_etm4: endpoint { + slave-mode; + remote-endpoint = + <&etm4_out_funnel_apss>; + }; + }; + + port@6 { + reg = <5>; + funnel_apss_in_etm5: endpoint { + slave-mode; + remote-endpoint = + <&etm5_out_funnel_apss>; + }; + }; + + port@7 { + reg = <6>; + funnel_apss_in_etm6: endpoint { + slave-mode; + remote-endpoint = + <&etm6_out_funnel_apss>; + }; + }; + + port@8 { + reg = <7>; + funnel_apss_in_etm7: endpoint { + slave-mode; + remote-endpoint = + <&etm7_out_funnel_apss>; + }; + }; + }; + }; + + cti1: cti@6011000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6011000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti2: cti@6012000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6012000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti3: cti@6013000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6013000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti3"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti4: cti@6014000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6014000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti4"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti5: cti@6015000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6015000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti5"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti6: cti@6016000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6016000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti6"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti7: cti@6017000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6017000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti7"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti8: cti@6018000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6018000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti8"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti9: cti@6019000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6019000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti9"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti10: cti@601a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti10"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti11: cti@601b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti11"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti12: cti@601c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti12"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti13: cti@601d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601d000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti13"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti14: cti@601e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601e000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti14"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti15: cti@601f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601f000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti15"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti_cpu0: cti@7020000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7020000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu0"; + cpu = <&CPU0>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti_cpu1: cti@7120000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7120000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu1"; + cpu = <&CPU1>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu2: cti@7220000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7220000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu2"; + cpu = <&CPU2>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu3: cti@7320000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7320000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu3"; + cpu = <&CPU3>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu4: cti@7420000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7420000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu4"; + cpu = <&CPU4>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu5: cti@7520000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7520000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu5"; + cpu = <&CPU5>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu6: cti@7620000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7620000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu6"; + cpu = <&CPU6>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu7: cti@7720000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7720000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu7"; + cpu = <&CPU7>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + hwevent: hwevent@91866f0 { + compatible = "qcom,coresight-hwevent"; + reg = <0x091866f0 0x4>, + <0x91966f0 0x4>, + <0x9186038 0x4>, + <0x9196038 0x4>, + <0x17e00034 0x4>, + <0x18200050 0x80>, + <0x02c8d050 0x80>, + <0x0af20050 0x80>; + reg-names = "ddr-ch0-cfg", "ddr-ch23-cfg", "ddr-ch0-ctrl", + "ddr-ch23-ctrl", "apss-testbus-mux-cfg", + "apss-rsc-hwevent-mux0-select", + "gpu-rsc-hwevent-mux0-select", + "sde-rsc-hwevent-mux0-select"; + + coresight-name = "coresight-hwevent"; + coresight-csr = <&csr>; + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + ipcb_tgu: tgu@6b0c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b999>; + reg = <0x06b0c000 0x1000>; + reg-names = "tgu-base"; + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <4>; + tgu-timer-counters = <8>; + + coresight-name = "coresight-tgu-ipcb"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-ext-codec-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/sm6150-ext-codec-audio-overlay.dtsi new file mode 100644 index 000000000000..fddfc562d0e0 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-ext-codec-audio-overlay.dtsi @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "sm6150-audio-overlay.dtsi" + +&bolero { + status = "disabled"; +}; + +&wcd937x_codec { + status = "disabled"; +}; + +&wcd937x_rst_gpio { + status = "disabled"; +}; + +&cdc_dmic01_gpios { + status = "disabled"; +}; + +&cdc_dmic23_gpios { + status = "disabled"; +}; + +&wsa_swr_gpios { + status = "disabled"; +}; + +&rx_swr_gpios { + status = "disabled"; +}; + +&tx_swr_gpios { + status = "disabled"; +}; + +&wsa_spkr_en1 { + status = "disabled"; +}; + +&wsa_spkr_en2 { + status = "disabled"; +}; + +&wcd9xxx_intc { + status = "okay"; +}; + +&qupv3_se4_spi { + status = "okay"; +}; + +&tavil_wdsp { + status = "okay"; +}; + +&tavil_glink { + status = "okay"; +}; + +&slim_aud { + status = "okay"; +}; + +&dai_slim { + status = "okay"; +}; + +&wcd934x_cdc { + status = "okay"; +}; + +&clock_audio { + status = "okay"; +}; + +&wcd934x_rst_gpio { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-external-codec-idp-overlay.dts b/arch/arm/boot/dts/qcom/sm6150-external-codec-idp-overlay.dts new file mode 100644 index 000000000000..473c59fdefe8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-external-codec-idp-overlay.dts @@ -0,0 +1,32 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "sm6150-idp.dtsi" +#include "sm6150-ext-codec-audio-overlay.dtsi" +#include "sm6150-external-codec.dtsi" + +/ { + model = "External Audio Codec IDP"; + compatible = "qcom,sm6150-idp", "qcom,sm6150", "qcom,idp"; + qcom,msm-id = <355 0x0>; + qcom,board-id = <34 1>; +}; + +&dsi_hx83112a_truly_vid_display { + qcom,dsi-display-active; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-external-codec-idp.dts b/arch/arm/boot/dts/qcom/sm6150-external-codec-idp.dts new file mode 100644 index 000000000000..47cef042e62c --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-external-codec-idp.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm6150.dtsi" +#include "sm6150-idp.dtsi" +#include "sm6150-ext-codec-audio-overlay.dtsi" +#include "sm6150-external-codec.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM6150 PM6150 External Audio Codec IDP"; + compatible = "qcom,sm6150-idp", "qcom,sm6150", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-external-codec.dtsi b/arch/arm/boot/dts/qcom/sm6150-external-codec.dtsi new file mode 100644 index 000000000000..04b1fdd55ec4 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-external-codec.dtsi @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "sm6150-wcd.dtsi" + +&sm6150_snd { + qcom,model = "sm6150-tavil-snd-card"; + qcom,tavil_codec = <1>; + qcom,ext-disp-audio-rx = <1>; + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "hifi amp", "LINEOUT1", + "hifi amp", "LINEOUT2", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC3", "MIC BIAS2", + "MIC BIAS2", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2", + "MIC BIAS2", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS3", + "MIC BIAS3", "Handset Mic", + "DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "DMIC4", "MIC BIAS4", + "MIC BIAS4", "Digital Mic4", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT"; + asoc-cpu = <&dai_dp>, <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, <&dai_mi2s4>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, + <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, + <&dai_quin_auxpcm>, + <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, + <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, + <&sb_4_rx>, <&sb_4_tx>, <&sb_5_rx>, <&sb_5_tx>, + <&sb_6_rx>, <&sb_7_rx>, <&sb_7_tx>, + <&sb_8_rx>, <&sb_8_tx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, + <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, + <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>; + asoc-cpu-names = "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", + "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", + "msm-dai-q6-auxpcm.5", + "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", + "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", + "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", + "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", + "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", + "msm-dai-q6-dev.16394", "msm-dai-q6-dev.16395", + "msm-dai-q6-dev.16396", + "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", + "msm-dai-q6-dev.16400", "msm-dai-q6-dev.16401", + "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", + "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", + "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", + "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", + "msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36929"; + asoc-codec = <&stub_codec>, <&ext_disp_audio_codec>; + asoc-codec-names = "msm-stub-codec.1", "msm-ext-disp-audio-codec-rx"; + qcom,hph-en0-gpio = <&tavil_hph_en0>; + qcom,hph-en1-gpio = <&tavil_hph_en1>; + qcom,wsa-max-devs = <2>; + qcom,wsa-devs = <&wsa881x_11>, <&wsa881x_12>, + <&wsa881x_13>, <&wsa881x_14>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", + "SpkrLeft", "SpkrRight"; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&wcd934x_cdc>, + <&q6core>, <&lpi_tlmm>; +}; + +&slim_aud { + status = "okay"; + tavil_codec { + swr3: swr_master { + compatible = "qcom,swr-mstr"; + #address-cells = <2>; + #size-cells = <0>; + qcom,swr-num-ports = <8>; + qcom,swr-port-mapping = <1 SPKR_L 0x1>, + <2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>, + <4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>, + <6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>, + <8 SPKR_R_VI 0x3>; + qcom,swr_master_id = <1>; + wsa881x_11: wsa881x@11 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170211>; + qcom,spkr-sd-n-node = <&wsa_spk_wcd_sd1>; + }; + + wsa881x_12: wsa881x@12 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170212>; + qcom,spkr-sd-n-node = <&wsa_spk_wcd_sd2>; + }; + + wsa881x_13: wsa881x@13 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170213>; + qcom,spkr-sd-n-node = <&wsa_spk_wcd_sd1>; + }; + + wsa881x_14: wsa881x@14 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170214>; + qcom,spkr-sd-n-node = <&wsa_spk_wcd_sd2>; + }; + }; + }; +}; + +&dai_slim { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-gdsc.dtsi b/arch/arm/boot/dts/qcom/sm6150-gdsc.dtsi new file mode 100644 index 000000000000..eb907b496720 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-gdsc.dtsi @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + /* GDSCs in Global CC */ + emac_gdsc: qcom,gdsc@106004 { + compatible = "qcom,gdsc"; + regulator-name = "emac_gdsc"; + reg = <0x106004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + pcie_0_gdsc: qcom,gdsc@16b004 { + compatible = "qcom,gdsc"; + regulator-name = "pcie_0_gdsc"; + reg = <0x16b004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + ufs_phy_gdsc: qcom,gdsc@177004 { + compatible = "qcom,gdsc"; + regulator-name = "ufs_phy_gdsc"; + reg = <0x177004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + usb20_sec_gdsc: qcom,gdsc@1a6004 { + compatible = "qcom,gdsc"; + regulator-name = "usb20_sec_gdsc"; + reg = <0x1a6004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + usb30_prim_gdsc: qcom,gdsc@10f004 { + compatible = "qcom,gdsc"; + regulator-name = "usb30_prim_gdsc"; + reg = <0x10f004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc: qcom,gdsc@17d040 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc"; + reg = <0x17d040 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_tbu1_gdsc: qcom,gdsc@17d044 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc"; + reg = <0x17d044 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_tbu2_gdsc: qcom,gdsc@17d048 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc"; + reg = <0x17d048 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc: qcom,gdsc@17d04c { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc"; + reg = <0x17d04c 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; + reg = <0x17d050 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@17d054 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc"; + reg = <0x17d054 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc"; + reg = <0x17d058 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + /* GDSCs in Camera CC */ + bps_gdsc: qcom,gdsc@ad06004 { + compatible = "qcom,gdsc"; + regulator-name = "bps_gdsc"; + reg = <0xad06004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + ife_0_gdsc: qcom,gdsc@ad09004 { + compatible = "qcom,gdsc"; + regulator-name = "ife_0_gdsc"; + reg = <0xad09004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + ife_1_gdsc: qcom,gdsc@ad0a004 { + compatible = "qcom,gdsc"; + regulator-name = "ife_1_gdsc"; + reg = <0xad0a004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + ipe_0_gdsc: qcom,gdsc@ad07004 { + compatible = "qcom,gdsc"; + regulator-name = "ipe_0_gdsc"; + reg = <0xad07004 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + titan_top_gdsc: qcom,gdsc@ad0b134 { + compatible = "qcom,gdsc"; + regulator-name = "titan_top_gdsc"; + reg = <0xad0b134 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + /* GDSCs in Display CC */ + mdss_core_gdsc: qcom,gdsc@af03000 { + compatible = "qcom,gdsc"; + regulator-name = "mdss_core_gdsc"; + reg = <0xaf03000 0x4>; + qcom,poll-cfg-gdscr; + qcom,support-hw-trigger; + status = "disabled"; + proxy-supply = <&mdss_core_gdsc>; + qcom,proxy-consumer-enable; + }; + + /* GDSCs in Graphics CC */ + gpu_cx_hw_ctrl: syscon@5091540 { + compatible = "syscon"; + reg = <0x5091540 0x4>; + }; + + gpu_cx_gdsc: qcom,gdsc@509106c { + compatible = "qcom,gdsc"; + regulator-name = "gpu_cx_gdsc"; + reg = <0x509106c 0x4>; + hw-ctrl-addr = <&gpu_cx_hw_ctrl>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + qcom,clk-dis-wait-val = <8>; + status = "disabled"; + }; + + gpu_gx_gdsc: qcom,gdsc@509100c { + compatible = "qcom,gdsc"; + regulator-name = "gpu_gx_gdsc"; + reg = <0x509100c 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + /* GDSCs in Video CC */ + vcodec0_gdsc: qcom,gdsc@ab00874 { + compatible = "qcom,gdsc"; + regulator-name = "vcodec0_gdsc"; + reg = <0xab00874 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; + + venus_gdsc: qcom,gdsc@ab00814 { + compatible = "qcom,gdsc"; + regulator-name = "venus_gdsc"; + reg = <0xab00814 0x4>; + qcom,poll-cfg-gdscr; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-gpu.dtsi b/arch/arm/boot/dts/qcom/sm6150-gpu.dtsi new file mode 100644 index 000000000000..70a44811ea63 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-gpu.dtsi @@ -0,0 +1,651 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + pil_gpu: qcom,kgsl-hyp { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <13>; + qcom,firmware-name = "a612_zap"; + }; + + msm_bus: qcom,kgsl-busmon { + label = "kgsl-busmon"; + compatible = "qcom,kgsl-busmon"; + }; + + gpubw: qcom,gpubw { + compatible = "qcom,devbw"; + governor = "bw_vbif"; + qcom,src-dst-ports = <26 512>; + operating-points-v2 = <&suspendable_ddr_bw_opp_table>; + }; + + msm_gpu: qcom,kgsl-3d0@5000000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; + status = "ok"; + reg = <0x5000000 0x90000>, + <0x780000 0x6fff>; + reg-names = "kgsl_3d0_reg_memory", + "qfprom_memory"; + interrupts = <0 300 0>; + interrupt-names = "kgsl_3d0_irq"; + qcom,id = <0>; + + qcom,chipid = <0x06010200>; + + qcom,initial-pwrlevel = <5>; + + /* */ + qcom,idle-timeout = <80>; + qcom,no-nap; + + qcom,highest-bank-bit = <14>; + qcom,ubwc-mode = <2>; + qcom,min-access-length = <32>; + + /* size in bytes */ + qcom,snapshot-size = <1048576>; + + /* base addr, size */ + qcom,gpu-qdss-stm = <0x161c0000 0x40000>; + #cooling-cells = <2>; + + clocks = <&clock_gpucc GPU_CC_GX_GFX3D_CLK>, + <&clock_gpucc GPU_CC_CXO_CLK>, + <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, + <&clock_gpucc GPU_CC_AHB_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&clock_gpucc GPU_CC_CX_GMU_CLK>; + + clock-names = "core_clk", "rbbmtimer_clk", "mem_clk", + "iface_clk", "mem_iface_clk", + "smmu_vote", "gmu_clk"; + + /* Bus Scale Settings */ + qcom,gpubw-dev = <&gpubw>; + qcom,bus-control; + qcom,msm-bus,name = "grp3d"; + qcom,bus-width = <32>; + qcom,msm-bus,num-cases = <12>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, + <26 512 0 400000>, /* 1 bus=100 (Low SVS) */ + <26 512 0 800000>, /* 2 bus=200 (Low SVS) */ + <26 512 0 1200000>, /* 3 bus=300 (Low SVS) */ + <26 512 0 1804000>, /* 4 bus=451.2 (Low SVS) */ + <26 512 0 2188000>, /* 5 bus=547.2 (Low SVS) */ + <26 512 0 2726000>, /* 6 bus=681.6 (SVS) */ + <26 512 0 3072000>, /* 7 bus=768 (SVS) */ + <26 512 0 4070000>, /* 8 bus=1017.6 (SVS L1) */ + <26 512 0 5414000>, /* 9 bus=1353.6 (NOM) */ + <26 512 0 6220000>, /* 10 bus=1555.2 (NOM) */ + <26 512 0 7219000>; /* 11 bus=1804.8 (TURBO) */ + + /* GDSC regulator names */ + regulator-names = "vddcx", "vdd"; + /* GDSC oxili regulators */ + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + /* Cx ipeak limit supprt */ + qcom,gpu-cx-ipeak = <&cx_ipeak_lm 1>; + + /* GPU related llc slices */ + cache-slice-names = "gpu", "gpuhtw"; + cache-slices = <&llcc 12>, <&llcc 11>; + + /* CPU latency parameter */ + qcom,pm-qos-active-latency = <67>; + qcom,pm-qos-wakeup-latency = <67>; + + /* Enable context aware freq. scaling */ + qcom,enable-ca-jump; + /* Context aware jump busy penalty in us */ + qcom,ca-busy-penalty = <12000>; + /* Context aware jump target power level */ + qcom,ca-target-pwrlevel = <3>; + + qcom,gpu-speed-bin = <0x6004 0x1fe00000 21>; + + /* GPU Mempools */ + qcom,gpu-mempools { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-allocate; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-allocate; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; + + /* + * Speed-bin zero is default speed bin. + * For rest of the speed bins, speed-bin value + * is calulated as FMAX/4.8 MHz round up to zero + * decimal places. + */ + qcom,gpu-pwrlevel-bins { + #address-cells = <1>; + #size-cells = <0>; + + compatible="qcom,gpu-pwrlevel-bins"; + + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <0>; + + qcom,initial-pwrlevel = <5>; + qcom,ca-target-pwrlevel = <3>; + + /* TURBO */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <845000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <745000000>; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <700000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <550000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <435000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <290000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <177>; + + qcom,initial-pwrlevel = <5>; + qcom,ca-target-pwrlevel = <3>; + + /* TURBO */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <845000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <745000000>; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <700000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <550000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <435000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <290000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-2 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <187>; + + qcom,initial-pwrlevel = <6>; + qcom,ca-target-pwrlevel = <4>; + + /* TURBO L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <895000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + /* TURBO */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <845000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <745000000>; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <700000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <550000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <435000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <290000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-3 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <156>; + + qcom,initial-pwrlevel = <4>; + qcom,ca-target-pwrlevel = <2>; + + /* NOM L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <745000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <700000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <550000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <435000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <290000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-4 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <136>; + + qcom,initial-pwrlevel = <3>; + qcom,ca-target-pwrlevel = <1>; + + /* NOM */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <650000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS L1 */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <550000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <435000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <290000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-5 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <105>; + + qcom,initial-pwrlevel = <1>; + qcom,ca-target-pwrlevel = <2>; + + /* SVS L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <500000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <435000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <290000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + + qcom,gpu-pwrlevels-6 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <73>; + + qcom,initial-pwrlevel = <1>; + qcom,ca-target-pwrlevel = <0>; + + /* SVS */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <350000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <290000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <4>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + }; + }; + + kgsl_msm_iommu: qcom,kgsl-iommu@0x050a0000 { + compatible = "qcom,kgsl-smmu-v2"; + + reg = <0x050a0000 0x10000>; + qcom,protect = <0xa0000 0x10000>; + + clocks =<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + + clock-names = "mem_clk", "mem_iface_clk", "smmu_vote"; + + qcom,secure_align_mask = <0xfff>; + qcom,retention; + qcom,hyp_secure_alloc; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + label = "gfx3d_user"; + iommus = <&kgsl_smmu 0x0 0x401>; + qcom,gpu-offset = <0xa8000>; + }; + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + label = "gfx3d_secure"; + iommus = <&kgsl_smmu 0x2 0x400>; + }; + }; + + rgmu: qcom,rgmu@0x0506d000 { + label = "kgsl-rgmu"; + compatible = "qcom,gpu-rgmu"; + + reg = <0x506d000 0x31000>; + reg-names = "kgsl_rgmu"; + + interrupts = <0 304 0>, <0 305 0>; + interrupt-names = "kgsl_oob", "kgsl_rgmu"; + + regulator-names = "vddcx", "vdd"; + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + + clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>, + <&clock_gpucc GPU_CC_CXO_CLK>, + <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, + <&clock_gpucc GPU_CC_AHB_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&clock_gpucc GPU_CC_GX_GFX3D_CLK>; + + clock-names = "gmu", "rbbmtimer", "mem", + "iface", "mem_iface", + "smmu_vote", "core"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-idp-overlay.dts b/arch/arm/boot/dts/qcom/sm6150-idp-overlay.dts new file mode 100644 index 000000000000..d8bb219b60ed --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-idp-overlay.dts @@ -0,0 +1,31 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "sm6150-idp.dtsi" +#include "sm6150-audio-overlay.dtsi" + +/ { + model = "IDP"; + compatible = "qcom,sm6150-idp", "qcom,sm6150", "qcom,idp"; + qcom,msm-id = <355 0x0>; + qcom,board-id = <34 0>; +}; + +&dsi_hx83112a_truly_vid_display { + qcom,dsi-display-active; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-idp.dts b/arch/arm/boot/dts/qcom/sm6150-idp.dts new file mode 100644 index 000000000000..0b32f1756855 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-idp.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm6150.dtsi" +#include "sm6150-idp.dtsi" +#include "sm6150-audio-overlay.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM6150 PM6150 IDP"; + compatible = "qcom,sm6150-idp", "qcom,sm6150", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-idp.dtsi b/arch/arm/boot/dts/qcom/sm6150-idp.dtsi new file mode 100644 index 000000000000..82ef40d8a8d0 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-idp.dtsi @@ -0,0 +1,403 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm6150-thermal-overlay.dtsi" +#include "sm6150-camera-sensor-idp.dtsi" +#include +#include +#include +#include "sm6150-sde-display.dtsi" +#include + +&qupv3_se3_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + #include "smb1390.dtsi" + #include "smb1355.dtsi" +}; + +&pm6150l_gpios { + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio2"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm6150l_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + linux,can-disable; + debounce-interval = <15>; + gpio-key,wakeup; + }; + }; + + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + #include "qg-batterydata-mlp356477-2800mah.dtsi" + }; + emac_hw: qcom,emac@20000 { + compatible = "qcom,emac-dwc-eqos"; + qcom,arm-smmu; + reg = <0x20000 0x10000>, + <0x36000 0x100>; + reg-names = "emac-base", "rgmii-base"; + dma-bit-mask = <32>; + emac-core-version = <7>; + interrupts-extended = <&pdc 0 660 4>, <&pdc 0 661 4>, + <&tlmm 121 2>, <&pdc 0 651 4>, + <&pdc 0 652 4>, <&pdc 0 653 4>, + <&pdc 0 654 4>, <&pdc 0 655 4>, + <&pdc 0 656 4>, <&pdc 0 657 4>, + <&pdc 0 658 4>, <&pdc 0 659 4>, + <&pdc 0 668 4>, <&pdc 0 669 4>; + interrupt-names = "sbd-intr", "lpi-intr", + "phy-intr", "tx-ch0-intr", + "tx-ch1-intr", "tx-ch2-intr", + "tx-ch3-intr", "tx-ch4-intr", + "rx-ch0-intr", "rx-ch1-intr", + "rx-ch2-intr", "rx-ch3-intr", + "ptp_pps_irq_0","ptp_pps_irq_1"; + qcom,msm-bus,name = "emac"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <98 512 0 0>, <1 781 0 0>, /* No vote */ + <98 512 1250 0>, <1 781 0 40000>, /* 10Mbps vote */ + <98 512 12500 0>, <1 781 0 40000>, /* 100Mbps vote */ + <98 512 125000 0>, <1 781 0 40000>; /* 1000Mbps vote */ + qcom,bus-vector-names = "0", "10", "100", "1000"; + clocks = <&clock_gcc GCC_EMAC_AXI_CLK>, + <&clock_gcc GCC_EMAC_PTP_CLK>, + <&clock_gcc GCC_EMAC_RGMII_CLK>, + <&clock_gcc GCC_EMAC_SLV_AHB_CLK>; + clock-names = "eth_axi_clk", "eth_ptp_clk", + "eth_rgmii_clk", "eth_slave_ahb_clk"; + qcom,phy-reset = <&tlmm 104 GPIO_ACTIVE_HIGH>; + qcom,phy-intr-redirect = <&tlmm 121 GPIO_ACTIVE_LOW>; + gdsc_emac-supply = <&emac_gdsc>; + pinctrl-names = "dev-emac-mdc", "dev-emac-mdio", + "dev-emac-rgmii_txd0_state", "dev-emac-rgmii_txd1_state", + "dev-emac-rgmii_txd2_state", "dev-emac-rgmii_txd3_state", + "dev-emac-rgmii_txc_state", "dev-emac-rgmii_tx_ctl_state", + "dev-emac-rgmii_rxd0_state", "dev-emac-rgmii_rxd1_state", + "dev-emac-rgmii_rxd2_state", "dev-emac-rgmii_rxd3_state", + "dev-emac-rgmii_rxc_state", "dev-emac-rgmii_rx_ctl_state", + "dev-emac-phy_intr", "dev-emac-phy_reset_state", + "dev-emac_pin_pps_0"; + + pinctrl-0 = <&emac_mdc>; + pinctrl-1 = <&emac_mdio>; + pinctrl-2 = <&emac_rgmii_txd0>; + pinctrl-3 = <&emac_rgmii_txd1>; + pinctrl-4 = <&emac_rgmii_txd2>; + pinctrl-5 = <&emac_rgmii_txd3>; + pinctrl-6 = <&emac_rgmii_txc>; + pinctrl-7 = <&emac_rgmii_tx_ctl>; + pinctrl-8 = <&emac_rgmii_rxd0>; + pinctrl-9 = <&emac_rgmii_rxd1>; + pinctrl-10 = <&emac_rgmii_rxd2>; + pinctrl-11 = <&emac_rgmii_rxd3>; + pinctrl-12 = <&emac_rgmii_rxc>; + pinctrl-13 = <&emac_rgmii_rx_ctl>; + pinctrl-14 = <&emac_phy_intr>; + pinctrl-15 = <&emac_phy_reset_state>; + pinctrl-16 = <&emac_pin_pps_0>; + + io-macro-info { + io-macro-bypass-mode = <0>; + io-interface = "rgmii"; + }; + emac_emb_smmu: emac_emb_smmu { + compatible = "qcom,emac-smmu-embedded"; + iommus = <&apps_smmu 0x1C0 0x0>; + qcom,iova-mapping = <0x80000000 0x40000000>; + }; + }; +}; + +&qupv3_se0_2uart { + status = "ok"; +}; + +&qupv3_se7_4uart { + status = "ok"; +}; + +&pm6150l_wled { + qcom,string-cfg= <3>; + qcom,leds-per-string = <7>; + status = "ok"; +}; + +&pm6150l_lcdb { + status = "ok"; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v3-660"; + + vdda-phy-supply = <&pm6150_l4>; /* 0.9v */ + vdda-phy-always-on; + vdda-pll-supply = <&pm6150_l11>; + vdda-phy-max-microamp = <30000>; + vdda-pll-max-microamp = <12000>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm6150l_l11>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm6150_l12>; + vcc-max-microamp = <600000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm6150l_l3>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vddp-ref-clk-min-uV = <1232000>; + qcom,vddp-ref-clk-max-uV = <1260000>; + + status = "ok"; +}; + +&qupv3_se1_i2c { + status = "okay"; + himax_ts@48 { + compatible = "himax,hxcommon"; + reg = <0x48>; + interrupt-parent = <&tlmm>; + interrupts = <89 0x2008>; + vdd-supply = <&pm6150_l10>; + avdd-supply = <&pm6150l_l7>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + himax,panel-coords = <0 1080 0 2160>; + himax,display-coords = <0 1080 0 2160>; + himax,irq-gpio = <&tlmm 89 0x00>; + himax,rst-gpio = <&tlmm 88 0x00>; + report_type = <1>; + }; +}; + +&qupv3_se5_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + + #address-cells = <1>; + #size-cells = <0>; + + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 86 0x00>; + qcom,nq-ven = <&tlmm 84 0x00>; + qcom,nq-firm = <&tlmm 85 0x00>; + qcom,nq-clkreq = <&tlmm 50 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <86 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active + &nfc_clk_req_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend + &nfc_clk_req_suspend>; + }; +}; + +&sdhc_1 { + vdd-supply = <&pm6150l_l11>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&pm6150_l12>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm6150l_l9>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&pm6150l_l6>; + qcom,vdd-io-voltage-level = <1800000 3100000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&tlmm 99 1>; + + status = "ok"; +}; + +&pm6150_qg { + qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <100>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; +}; + +&pm6150_charger { + io-channels = <&pm6150_vadc ADC_USB_IN_V_16>, + <&pm6150_vadc ADC_USB_IN_I>, + <&pm6150_vadc ADC_CHG_TEMP>, + <&pm6150_vadc ADC_DIE_TEMP>, + <&pm6150_vadc ADC_AMUX_THM4_PU2>, + <&pm6150_vadc ADC_SBUx>, + <&pm6150_vadc ADC_VPH_PWR>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage"; + qcom,battery-data = <&mtp_batterydata>; + qcom,auto-recharge-soc = <98>; + qcom,step-charging-enable; + qcom,sw-jeita-enable; + qcom,fcc-stepping-enable; + qcom,suspend-input-on-debug-batt; + qcom,sec-charger-config = <3>; + qcom,thermal-mitigation = <4200000 3500000 3000000 + 2500000 2000000 1500000 1000000 500000>; + dpdm-supply = <&qusb_phy0>; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; +}; + +&smb1390 { + /delete-property/ interrupts; + interrupts = <0x0 0xc2 0x0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1390_charger { + /delete-property/ compatible; + compatible = "qcom,smb1390-charger-psy"; + io-channels = <&pm6150_vadc ADC_AMUX_THM3>; + io-channel-names = "cp_die_temp"; + status = "ok"; +}; + +&smb1355 { + /delete-property/ interrupts; + interrupts = <0x0 0xc2 0x0 IRQ_TYPE_LEVEL_LOW>; + status = "ok"; +}; + +&smb1355_charger { + status = "ok"; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 91 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 91 0>; +}; + +&dsi_hx83112a_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 90 0>; + qcom,platform-reset-gpio = <&tlmm 91 0>; +}; + +&dsi_td4328_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 90 0>; + qcom,platform-reset-gpio = <&tlmm 91 0>; +}; + +&dsi_td4328_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 90 0>; + qcom,platform-reset-gpio = <&tlmm 91 0>; +}; + +&dsi_rm69298_truly_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 90 0>; + qcom,platform-reset-gpio = <&tlmm 91 0>; +}; + +&dsi_rm69298_truly_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 90 0>; + qcom,platform-reset-gpio = <&tlmm 91 0>; +}; + +&dsi_sharp_split_link_wuxga_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 90 0>; + qcom,platform-reset-gpio = <&tlmm 91 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-interposer-trinket-idp-overlay.dts b/arch/arm/boot/dts/qcom/sm6150-interposer-trinket-idp-overlay.dts new file mode 100644 index 000000000000..04867e47a3fe --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-interposer-trinket-idp-overlay.dts @@ -0,0 +1,29 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "sm6150-interposer-trinket-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM6150 Interposer TRINKET IDP"; + compatible = "qcom,sm6150-idp", "qcom,sm6150", "qcom,idp"; + qcom,msm-id = <355 0x0>; + qcom,board-id = <34 0>; +}; + +&dsi_td4330_truly_vid_display { + qcom,dsi-display-active; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-interposer-trinket-idp.dts b/arch/arm/boot/dts/qcom/sm6150-interposer-trinket-idp.dts new file mode 100644 index 000000000000..7b799fe780ee --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-interposer-trinket-idp.dts @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm6150-interposer-trinket.dtsi" +#include "sm6150-interposer-trinket-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM SM6150 Interposer TRINKET IDP"; + compatible = "qcom,sm6150-idp", "qcom,sm6150", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-interposer-trinket-idp.dtsi b/arch/arm/boot/dts/qcom/sm6150-interposer-trinket-idp.dtsi new file mode 100644 index 000000000000..3c66e63dc021 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-interposer-trinket-idp.dtsi @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "sm6150-sde-display.dtsi" +#include + +&pm6125_gpios { + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio5"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; +}; + +&pm6125_vadc { + rf_pa1_therm { + reg = ; + label = "rf_pa1_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm6125_adc_tm { + io-channels = <&pm6125_vadc ADC_AMUX_THM1_PU2>, + <&pm6125_vadc ADC_AMUX_THM2_PU2>, + <&pm6125_vadc ADC_XO_THERM_PU2>, + <&pm6125_vadc ADC_GPIO4_PU2>; + + rf_pa1_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + rf-pa1-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm ADC_GPIO4_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + linux,can-disable; + debounce-interval = <15>; + gpio-key,wakeup; + }; + }; +}; + +&sde_dp { + /delete-property/ qcom,dp-usbpd-detection; + status = "disabled"; +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&L18A>; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&L4A>; +}; + +&sde_dsi { + vddio-supply = <&L9A>; +}; + +&mdss_mdp { + connectors = <&sde_rscc &sde_wb &sde_dsi>; +}; + +&dsi_td4330_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 91 0>; + qcom,platform-en-gpio = <&pm6125_gpios 8 0>; + qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>; +}; + +&dsi_td4330_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 90 0>; + qcom,platform-reset-gpio = <&tlmm 91 0>; + qcom,platform-en-gpio = <&pm6125_gpios 8 0>; + qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-interposer-trinket-qrd-overlay.dts b/arch/arm/boot/dts/qcom/sm6150-interposer-trinket-qrd-overlay.dts new file mode 100644 index 000000000000..42e7b664b3bd --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-interposer-trinket-qrd-overlay.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include "sm6150-interposer-trinket-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM6150 Interposer TRINKET QRD"; + compatible = "qcom,sm6150-qrd", "qcom,sm6150", "qcom,qrd"; + qcom,msm-id = <355 0x0>; + qcom,board-id = <11 0x80>; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-interposer-trinket-qrd.dts b/arch/arm/boot/dts/qcom/sm6150-interposer-trinket-qrd.dts new file mode 100644 index 000000000000..9f161c64d003 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-interposer-trinket-qrd.dts @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm6150-interposer-trinket.dtsi" +#include "sm6150-interposer-trinket-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM SM6150 Interposer TRINKET QRD"; + compatible = "qcom,sm6150-qrd", "qcom,sm6150", "qcom,qrd"; + qcom,board-id = <11 0x80>; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi b/arch/arm/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi new file mode 100644 index 000000000000..25541325a9d1 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-interposer-trinket-qrd.dtsi @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&pm6125_gpios { + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio5"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; +}; + +&pmi632_gpios { + smb_en { + smb_en_default: smb_en_default { + pins = "gpio2"; + function = "func1"; + output-enable; + }; + }; + + pmi632_sense { + /* GPIO 7 and 8 are external-sense pins for PMI632 */ + pmi632_sense_default: pmi632_sense_default { + pins = "gpio7", "gpio8"; + bias-high-impedance; /* disable the GPIO */ + bias-disable; /* no-pull */ + }; + }; + + pmi632_ctm { + /* Disable GPIO1 for h/w base mitigation */ + pmi632_ctm_default: pmi632_ctm_default { + pins = "gpio1"; + bias-high-impedance; /* disable the GPIO */ + bias-disable; /* no-pull */ + }; + }; +}; + +&tlmm { + smb_int_default: smb_int_default { + mux { + pins = "gpio21"; + function = "gpio"; + }; + config { + pins = "gpio21"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + linux,can-disable; + debounce-interval = <15>; + gpio-key,wakeup; + }; + }; + + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-ascent-3450mah.dtsi" + #include "qg-batterydata-mlp356477-2800mah.dtsi" + }; +}; + +&qupv3_se1_i2c { + status = "ok"; + #include "smb1355.dtsi" +}; + +&smb1355 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_int_default>; + interrupt-parent = <&tlmm>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + status = "ok"; +}; + +&smb1355_charger { + pinctrl-names = "default"; + pinctrl-0 = <&smb_en_default &pmi632_sense_default &pmi632_ctm_default>; + qcom,parallel-mode = <1>; + qcom,disable-ctm; + qcom,hw-die-temp-mitigation; + status = "ok"; +}; + +&pmi632_qg { + qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <100>; + qcom,hold-soc-while-full; + qcom,linearize-soc; +}; + +&pmi632_charger { + qcom,battery-data = <&mtp_batterydata>; + qcom,suspend-input-on-debug-batt; + qcom,sw-jeita-enable; + /* SMB1355 only */ + qcom,sec-charger-config = <2>; + dpdm-supply = <&qusb_phy0>; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,auto-recharge-soc = <98>; + qcom,flash-disable-soc = <10>; + qcom,hw-die-temp-mitigation; + qcom,hw-connector-mitigation; + qcom,connector-internal-pull-kohm = <100>; + qcom,thermal-mitigation = <3000000 2500000 + 2000000 1500000 1000000 500000>; +}; + +&qupv3_se1_i2c { + status = "ok"; + synaptics_tcm@20 { + compatible = "synaptics,tcm-i2c"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <89 0x2008>; + synaptics,bus-reg-name = "vdd"; + synaptics,pwr-reg-name = "avdd"; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + synaptics,irq-gpio = <&tlmm 89 0x2008>; + synaptics,irq-on-state = <0>; + synaptics,reset-gpio = <&tlmm 88 0x00>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + synaptics,reset-delay-ms = <200>; + synaptics,power-delay-ms = <200>; + synaptics,ubl-i2c-addr = <0x20>; + synaptics,y-flip; + }; +}; + +&pmi632_vadc { + bat_therm { + qcom,lut-index = <0>; + }; + + bat_therm_30k { + qcom,lut-index = <0>; + }; + + bat_therm_400k { + qcom,lut-index = <0>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-interposer-trinket.dts b/arch/arm/boot/dts/qcom/sm6150-interposer-trinket.dts new file mode 100644 index 000000000000..9db4001e9bdf --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-interposer-trinket.dts @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm6150-interposer-trinket.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM6150 Interposer TRINKET"; + compatible = "qcom,sm6150"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-interposer-trinket.dtsi b/arch/arm/boot/dts/qcom/sm6150-interposer-trinket.dtsi new file mode 100644 index 000000000000..fa03d63835c9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-interposer-trinket.dtsi @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm6150.dtsi" +#include + +/ { + model = "Qualcomm Technologies, Inc. SM6150 Interposer TRINKET"; + compatible = "qcom,sm6150"; + qcom,msm-id = <355 0>; +}; + +&soc { + clock_rpmcc: qcom,rpmcc { + }; + + qcom,icnss@18800000 { + /delete-property/ vdd-cx-mx-supply; + /delete-property/ vdd-1.8-xo-supply; + /delete-property/ vdd-1.3-rfa-supply; + /delete-property/ vdd-3.3-ch0-supply; + }; +}; + +#include "sm6150-pm6125-interposer-trinket.dtsi" + +&qusb_phy0 { + vdd-supply = <&L7A>; + vdda18-supply = <&L10A>; + vdda33-supply = <&L15A>; +}; + +&usb_qmp_phy { + vdd-supply = <&L7A>; + core-supply = <&L10A>; +}; + +&usb0 { + extcon = <&pmi632_charger>; +}; + +&qupv3_se0_2uart { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-ion.dtsi b/arch/arm/boot/dts/qcom/sm6150-ion.dtsi new file mode 100644 index 000000000000..a9010fdb6b0d --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-ion.dtsi @@ -0,0 +1,68 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = <25>; + qcom,ion-heap-type = "SYSTEM"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = <27>; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@19 { /* QSEECOM TA HEAP */ + reg = <19>; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@13 { /* SPSS HEAP */ + reg = <13>; + memory-region = <&sp_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ + reg = <10>; + memory-region = <&secure_display_memory>; + qcom,ion-heap-type = "HYP_CMA"; + }; + + qcom,ion-heap@14 { /* SECURE CARVEOUT HEAP */ + reg = <14>; + qcom,ion-heap-type = "SECURE_CARVEOUT"; + cdsp { + memory-region = <&cdsp_sec_mem>; + token = <0x20000000>; + }; + }; + + qcom,ion-heap@9 { + reg = <9>; + qcom,ion-heap-type = "SYSTEM_SECURE"; + }; + + qcom,ion-heap@22 { /* ADSP HEAP */ + reg = <22>; + memory-region = <&sdsp_mem>; + qcom,ion-heap-type = "DMA"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll-lpi.dtsi b/arch/arm/boot/dts/qcom/sm6150-lpi.dtsi similarity index 53% rename from arch/arm64/boot/dts/qcom/atoll-lpi.dtsi rename to arch/arm/boot/dts/qcom/sm6150-lpi.dtsi index f7c7c018de20..0ba90fc4450f 100644 --- a/arch/arm64/boot/dts/qcom/atoll-lpi.dtsi +++ b/arch/arm/boot/dts/qcom/sm6150-lpi.dtsi @@ -12,13 +12,12 @@ */ &soc { - lpi_tlmm: lpi_pinctrl@627C0000 { + lpi_tlmm: lpi_pinctrl@62b40000 { compatible = "qcom,lpi-pinctrl"; - reg = <0x627C0000 0x0>; - qcom,num-gpios = <15>; + reg = <0x62b40000 0x0>; + qcom,num-gpios = <32>; gpio-controller; #gpio-cells = <2>; - qcom,slew-reg = <0x6295A000 0x0>; qcom,lpi-offset-tbl = <0x00000000>, <0x00001000>, <0x00002000>, <0x00003000>, <0x00004000>, <0x00005000>, @@ -26,176 +25,173 @@ <0x00008000>, <0x00009000>, <0x0000A000>, <0x0000B000>, <0x0000C000>, <0x0000D000>, - <0x0000E000>; - - qcom,lpi-slew-offset-tbl = <0x00000000>, <0x00000002>, - <0x00000004>, <0x00000008>, - <0x0000000A>, <0x0000000C>, - <0x00000000>, <0x00000000>, - <0x00000000>, <0x00000000>, - <0x00000010>, <0x00000012>, - <0x00000000>, <0x00000000>, - <0x00000000>; + <0x0000E000>, <0x0000F000>, + <0x00010000>, <0x00011000>, + <0x00012000>, <0x00013000>, + <0x00014000>, <0x00015000>, + <0x00016000>, <0x00017000>, + <0x00018000>, <0x00019000>, + <0x0001A000>, <0x0001B000>, + <0x0001C000>, <0x0001D000>, + <0x0001E000>, <0x0001F000>; clock-names = "lpass_core_hw_vote"; clocks = <&lpass_core_hw_vote 0>; - cdc_dmic01_clk_active: dmic01_clk_active { + lpi_wcd934x_reset_active: lpi_wcd934x_reset_active { mux { - pins = "gpio6"; - function = "func1"; + pins = "gpio29"; + function = "func2"; }; - config { - pins = "gpio6"; - drive-strength = <8>; + pins = "gpio29"; + drive-strength = <16>; output-high; }; }; - cdc_dmic01_clk_sleep: dmic01_clk_sleep { + lpi_wcd934x_reset_sleep: lpi_wcd934x_reset_sleep { mux { - pins = "gpio6"; - function = "func1"; + pins = "gpio29"; + function = "func2"; }; config { - pins = "gpio6"; - drive-strength = <2>; + pins = "gpio29"; + drive-strength = <16>; bias-disable; output-low; }; }; - cdc_dmic01_data_active: dmic01_data_active { + lpi_wcd937x_reset_active: lpi_wcd937x_reset_active { mux { - pins = "gpio7"; - function = "func1"; + pins = "gpio24"; + function = "func2"; }; - config { - pins = "gpio7"; - drive-strength = <8>; - input-enable; + pins = "gpio24"; + drive-strength = <16>; + output-high; }; }; - cdc_dmic01_data_sleep: dmic01_data_sleep { + lpi_wcd937x_reset_sleep: lpi_wcd937x_reset_sleep { mux { - pins = "gpio7"; - function = "func1"; + pins = "gpio24"; + function = "func2"; }; config { - pins = "gpio7"; - drive-strength = <2>; - pull-down; - input-enable; + pins = "gpio24"; + drive-strength = <16>; + bias-disable; + output-low; }; }; - cdc_dmic23_clk_active: dmic23_clk_active { + cdc_dmic01_clk_active: dmic01_clk_active { mux { - pins = "gpio8"; + pins = "gpio26"; function = "func1"; }; config { - pins = "gpio8"; + pins = "gpio26"; drive-strength = <8>; output-high; }; }; - cdc_dmic23_clk_sleep: dmic23_clk_sleep { + cdc_dmic01_clk_sleep: dmic01_clk_sleep { mux { - pins = "gpio8"; + pins = "gpio26"; function = "func1"; }; config { - pins = "gpio8"; + pins = "gpio26"; drive-strength = <2>; bias-disable; output-low; }; }; - cdc_dmic23_data_active: dmic23_data_active { + cdc_dmic01_data_active: dmic01_data_active { mux { - pins = "gpio9"; + pins = "gpio27"; function = "func1"; }; config { - pins = "gpio9"; + pins = "gpio27"; drive-strength = <8>; input-enable; }; }; - cdc_dmic23_data_sleep: dmic23_data_sleep { + cdc_dmic01_data_sleep: dmic01_data_sleep { mux { - pins = "gpio9"; + pins = "gpio27"; function = "func1"; }; config { - pins = "gpio9"; + pins = "gpio27"; drive-strength = <2>; pull-down; input-enable; }; }; - cdc_dmic45_clk_active: dmic45_clk_active { + cdc_dmic23_clk_active: dmic23_clk_active { mux { - pins = "gpio12"; + pins = "gpio28"; function = "func1"; }; config { - pins = "gpio12"; + pins = "gpio28"; drive-strength = <8>; output-high; }; }; - cdc_dmic45_clk_sleep: dmic45_clk_sleep { + cdc_dmic23_clk_sleep: dmic23_clk_sleep { mux { - pins = "gpio12"; + pins = "gpio28"; function = "func1"; }; config { - pins = "gpio12"; + pins = "gpio28"; drive-strength = <2>; bias-disable; output-low; }; }; - cdc_dmic45_data_active: dmic45_data_active { + cdc_dmic23_data_active: dmic23_data_active { mux { - pins = "gpio13"; + pins = "gpio29"; function = "func1"; }; config { - pins = "gpio13"; + pins = "gpio29"; drive-strength = <8>; input-enable; }; }; - cdc_dmic45_data_sleep: dmic45_data_sleep { + cdc_dmic23_data_sleep: dmic23_data_sleep { mux { - pins = "gpio13"; + pins = "gpio29"; function = "func1"; }; config { - pins = "gpio13"; + pins = "gpio29"; drive-strength = <2>; pull-down; input-enable; @@ -204,12 +200,12 @@ tx_swr_clk_sleep: tx_swr_clk_sleep { mux { - pins = "gpio0"; - function = "func1"; + pins = "gpio18"; + function = "func2"; }; config { - pins = "gpio0"; + pins = "gpio18"; drive-strength = <2>; bias-bus-hold; }; @@ -217,90 +213,12 @@ tx_swr_clk_active: tx_swr_clk_active { mux { - pins = "gpio0"; - function = "func1"; + pins = "gpio18"; + function = "func2"; }; config { - pins = "gpio0"; - drive-strength = <8>; - bias-bus-hold; - }; - }; - - tx_swr_data0_sleep: tx_swr_data0_sleep { - mux { - pins = "gpio1"; - function = "func1"; - }; - - config { - pins = "gpio1"; - drive-strength = <2>; - bias-bus-hold; - }; - }; - - tx_swr_data0_active: tx_swr_data0_active { - mux { - pins = "gpio1"; - function = "func1"; - }; - - config { - pins = "gpio1"; - drive-strength = <8>; - bias-bus-hold; - }; - }; - - wsa_swr_clk_sleep: wsa_swr_clk_sleep { - mux { - pins = "gpio10"; - function = "func1"; - }; - - config { - pins = "gpio10"; - drive-strength = <2>; - bias-bus-hold; - }; - }; - - wsa_swr_clk_active: wsa_swr_clk_active { - mux { - pins = "gpio10"; - function = "func1"; - }; - - config { - pins = "gpio10"; - drive-strength = <8>; - bias-bus-hold; - }; - }; - - wsa_swr_data_sleep: wsa_swr_data_sleep { - mux { - pins = "gpio11"; - function = "func1"; - }; - - config { - pins = "gpio11"; - drive-strength = <2>; - bias-bus-hold; - }; - }; - - wsa_swr_data_active: wsa_swr_data_active { - mux { - pins = "gpio11"; - function = "func1"; - }; - - config { - pins = "gpio11"; + pins = "gpio18"; drive-strength = <8>; bias-bus-hold; }; @@ -308,12 +226,12 @@ tx_swr_data1_sleep: tx_swr_data1_sleep { mux { - pins = "gpio2"; - function = "func1"; + pins = "gpio19"; + function = "func3"; }; config { - pins = "gpio2"; + pins = "gpio19"; drive-strength = <2>; bias-bus-hold; }; @@ -321,12 +239,12 @@ tx_swr_data1_active: tx_swr_data1_active { mux { - pins = "gpio2"; - function = "func1"; + pins = "gpio19"; + function = "func3"; }; config { - pins = "gpio2"; + pins = "gpio19"; drive-strength = <8>; bias-bus-hold; }; @@ -334,12 +252,12 @@ tx_swr_data2_sleep: tx_swr_data2_sleep { mux { - pins = "gpio14"; - function = "func1"; + pins = "gpio20"; + function = "func2"; }; config { - pins = "gpio14"; + pins = "gpio20"; drive-strength = <2>; bias-bus-hold; }; @@ -347,12 +265,12 @@ tx_swr_data2_active: tx_swr_data2_active { mux { - pins = "gpio14"; - function = "func1"; + pins = "gpio20"; + function = "func2"; }; config { - pins = "gpio14"; + pins = "gpio20"; drive-strength = <8>; bias-bus-hold; }; @@ -360,12 +278,12 @@ rx_swr_clk_sleep: rx_swr_clk_sleep { mux { - pins = "gpio3"; - function = "func1"; + pins = "gpio21"; + function = "func2"; }; config { - pins = "gpio3"; + pins = "gpio21"; drive-strength = <2>; bias-bus-hold; }; @@ -373,12 +291,12 @@ rx_swr_clk_active: rx_swr_clk_active { mux { - pins = "gpio3"; - function = "func1"; + pins = "gpio21"; + function = "func2"; }; config { - pins = "gpio3"; + pins = "gpio21"; drive-strength = <8>; bias-bus-hold; }; @@ -386,12 +304,12 @@ rx_swr_data_sleep: rx_swr_data_sleep { mux { - pins = "gpio4", "gpio5"; - function = "func1"; + pins = "gpio22", "gpio23"; + function = "func2"; }; config { - pins = "gpio4", "gpio5"; + pins = "gpio22", "gpio23"; drive-strength = <2>; bias-bus-hold; }; @@ -399,12 +317,12 @@ rx_swr_data_active: rx_swr_data_active { mux { - pins = "gpio4", "gpio5"; - function = "func1"; + pins = "gpio22", "gpio23"; + function = "func2"; }; config { - pins = "gpio4", "gpio5"; + pins = "gpio22", "gpio23"; drive-strength = <8>; bias-bus-hold; }; diff --git a/arch/arm/boot/dts/qcom/sm6150-pinctrl.dtsi b/arch/arm/boot/dts/qcom/sm6150-pinctrl.dtsi new file mode 100644 index 000000000000..df5960c939e9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-pinctrl.dtsi @@ -0,0 +1,2263 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + tlmm: pinctrl@03000000 { + compatible = "qcom,sm6150-pinctrl"; + reg = <0x03000000 0xdc2000>, <0x17c000f0 0x60>; + reg-names = "pinctrl", "spi_cfg"; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + ufs_dev_reset_assert: ufs_dev_reset_assert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * UFS_RESET driver strengths are having + * different values/steps compared to typical + * GPIO drive strengths. + * + * Following table clarifies: + * + * HDRV value | UFS_RESET | Typical GPIO + * (dec) | (mA) | (mA) + * 0 | 0.8 | 2 + * 1 | 1.55 | 4 + * 2 | 2.35 | 6 + * 3 | 3.1 | 8 + * 4 | 3.9 | 10 + * 5 | 4.65 | 12 + * 6 | 5.4 | 14 + * 7 | 6.15 | 16 + * + * POR value for UFS_RESET HDRV is 3 which means + * 3.1mA and we want to use that. Hence just + * specify 8mA to "drive-strength" binding and + * that should result into writing 3 to HDRV + * field. + */ + drive-strength = <8>; /* default: 3.1 mA */ + output-low; /* active low reset */ + }; + }; + + ufs_dev_reset_deassert: ufs_dev_reset_deassert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * default: 3.1 mA + * check comments under ufs_dev_reset_assert + */ + drive-strength = <8>; + output-high; /* active low reset */ + }; + }; + + /* QUPv3_0 South SE mappings */ + /* SE 0 pin mappings */ + qupv3_se0_2uart_pins: qupv3_se0_2uart_pins { + qupv3_se0_2uart_active: qupv3_se0_2uart_active { + mux { + pins = "gpio16", "gpio17"; + function = "qup00"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se0_2uart_sleep: qupv3_se0_2uart_sleep { + mux { + pins = "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + /* SE 1 pin mappings */ + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_active: qupv3_se1_i2c_active { + mux { + pins = "gpio4", "gpio5"; + function = "qup01"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-no-pull; + }; + }; + }; + + /* SE 2 pin mappings */ + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "qup02"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_active: qupv3_se2_spi_active { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "qup02"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + fpc_reset_int { + fpc_reset_low: reset_low { + mux { + pins = "gpio101"; + function = "gpio"; + }; + config { + pins = "gpio101"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + fpc_reset_high: reset_high { + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + fpc_int_low: int_low { + mux { + pins = "gpio93"; + function = "gpio"; + }; + config { + pins = "gpio93"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + }; + + /* SE 3 pin mappings */ + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_active: qupv3_se3_i2c_active { + mux { + pins = "gpio18", "gpio19"; + function = "qup03"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + ss5_pwr_ctrl_pins: ss5_pwr_ctrl_pins { + ss5_pwr_ctrl_rst_on: ss5_pwr_ctrl_rst_on { + mux { + pins = "gpio87", "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio87", "gpio18"; + drive-strength = <16>; /* 16 mA */ + bias-pull-up; + output-high; + }; + }; + + ss5_pwr_ctrl_rst_off: ss5_pwr_ctrl_off { + mux { + pins = "gpio87", "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio87", "gpio18"; + drive-strength = <16>; /* 16 mA */ + bias-pull-up; + output-high; + }; + }; + }; + + /* QUPv3_1 North instances */ + /* SE 4 pin mappings */ + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_active: qupv3_se4_i2c_active { + mux { + pins = "gpio20", "gpio21"; + function = "qup10"; + }; + + config { + pins = "gpio20", "gpio21"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio20", "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se4_spi_pins: qupv3_se4_spi_pins { + qupv3_se4_spi_active: qupv3_se4_spi_active { + mux { + pins = "gpio20", "gpio21", "gpio22", + "gpio23"; + function = "qup10"; + }; + + config { + pins = "gpio20", "gpio21", "gpio22", + "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { + mux { + pins = "gpio20", "gpio21", "gpio22", + "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio20", "gpio21", "gpio22", + "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + qupv3_se4_2uart_pins: qupv3_se4_2uart_pins { + qupv3_se4_2uart_active: qupv3_se4_2uart_active { + mux { + pins = "gpio22", "gpio23"; + function = "qup10"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <16>; + bias-disable; + }; + }; + + qupv3_se4_2uart_sleep: qupv3_se4_2uart_sleep { + mux { + pins = "gpio22", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <16>; + bias-disable; + }; + }; + }; + + /* SE 5 pin mappings */ + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_active: qupv3_se5_i2c_active { + mux { + pins = "gpio14", "gpio15"; + function = "qup11"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 86 NFC Read Interrupt */ + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 86 NFC Read Interrupt */ + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_active: nfc_enable_active { + /* active state */ + mux { + /* 84: Enable 85: Firmware */ + pins = "gpio84", "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio84", "gpio85"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + /* sleep state */ + mux { + /* 84: Enable 85: Firmware */ + pins = "gpio84", "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio84", "gpio85"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_clk_req_active: nfc_clk_req_active { + /* active state */ + mux { + /* GPIO 50: NFC CLOCK REQUEST */ + pins = "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio50"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_clk_req_suspend: nfc_clk_req_suspend { + /* sleep state */ + mux { + /* GPIO 50: NFC CLOCK REQUEST */ + pins = "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio50"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + + /* SE 6 pin mappings */ + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_active: qupv3_se6_i2c_active { + mux { + pins = "gpio6", "gpio7"; + function = "qup12"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_active: qupv3_se6_spi_active { + mux { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + function = "qup12"; + }; + + config { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 7 pin mappings */ + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_active: qupv3_se7_i2c_active { + mux { + pins = "gpio10", "gpio11"; + function = "qup13"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se7_spi_pins: qupv3_se7_spi_pins { + qupv3_se7_spi_active: qupv3_se7_spi_active { + mux { + pins = "gpio10", "gpio11", "gpio12", + "gpio13"; + function = "qup13"; + }; + + config { + pins = "gpio10", "gpio11", "gpio12", + "gpio13"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_sleep: qupv3_se7_spi_sleep { + mux { + pins = "gpio10", "gpio11", "gpio12", + "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio10", "gpio11", "gpio12", + "gpio13"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se7_4uart_pins: qupv3_se7_4uart_pins { + qupv3_se7_ctsrx: qupv3_se7_ctsrx { + mux { + pins = "gpio10", "gpio13"; + function = "qup13"; + }; + + config { + pins = "gpio10", "gpio13"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_rts: qupv3_se7_rts { + mux { + pins = "gpio11"; + function = "qup13"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se7_tx: qupv3_se7_tx { + mux { + pins = "gpio12"; + function = "qup13"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + lt9611_pins: lt9611_pins { + mux { + pins = "gpio26", "gpio20", "gpio79"; + function = "gpio"; + }; + + config { + pins = "gpio26", "gpio20", "gpio79"; + drive-strength = <8>; + bias-disable = <0>; /* no pull */ + }; + }; + + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio91"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio91"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + fsa_usbc_ana_en_n@114 { + fsa_usbc_ana_en: fsa_usbc_ana_en { + mux { + pins = "gpio114"; + function = "gpio"; + }; + + config { + pins = "gpio114"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + }; + + pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio90"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio90"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + bias-disable; + drive-strength = <16>; + }; + }; + + sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + sde_dp_switch_active: sde_dp_switch_active { + mux { + pins = "gpio49"; + function = "gpio"; + }; + + config { + pins = "gpio49"; + bias-pull-up; /* pull up */ + output-high; + drive-strength = <2>; + }; + }; + + sde_dp_switch_suspend: sde_dp_switch_suspend { + mux { + pins = "gpio49"; + function = "gpio"; + }; + + config { + pins = "gpio49"; + bias-pull-down; + output-low; + drive-strength = <2>; + }; + }; + + sde_dp_connector_enable: sde_dp_connector_enable { + mux { + pins = "gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio44"; + bias-pull-up; + output-high; + drive-strength = <2>; + }; + }; + + sde_dp_hotplug_ctrl: sde_dp_hotplug_ctrl { + mux { + pins = "gpio103"; + function = "debug_hot"; + }; + + config { + pins = "gpio103"; + bias-disable; + input-enable; + drive-strength = <2>; + }; + }; + + sde_dp_hotplug_tlmm: sde_dp_hotplug_tlmm { + mux { + pins = "gpio103"; + function = "gpio"; + }; + + config { + pins = "gpio103"; + bias-disable; + input-enable; + drive-strength = <2>; + }; + }; + + + + /* SDC pin type */ + sdc1_clk_on: sdc1_clk_on { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc1_clk_off: sdc1_clk_off { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_cmd_on: sdc1_cmd_on { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_cmd_off: sdc1_cmd_off { + config { + pins = "sdc1_cmd"; + num-grp-pins = <1>; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_data_on: sdc1_data_on { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_data_off: sdc1_data_off { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_rclk_on: sdc1_rclk_on { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc1_rclk_off: sdc1_rclk_off { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_on: cd_on { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_cd_off: cd_off { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; + bias-disable; + }; + }; + + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio98"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio98"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + }; + + wsa_swr_clk_pin { + wsa_swr_clk_sleep: wsa_swr_clk_sleep { + mux { + pins = "gpio111"; + function = "WSA_CLK"; + }; + + config { + pins = "gpio111"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + wsa_swr_clk_active: wsa_swr_clk_active { + mux { + pins = "gpio111"; + function = "WSA_CLK"; + }; + + config { + pins = "gpio111"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + }; + + wsa_swr_data_pin { + wsa_swr_data_sleep: wsa_swr_data_sleep { + mux { + pins = "gpio110"; + function = "WSA_DATA"; + }; + + config { + pins = "gpio110"; + drive-strength = <4>; + bias-bus-hold; + }; + }; + + wsa_swr_data_active: wsa_swr_data_active { + mux { + pins = "gpio110"; + function = "WSA_DATA"; + }; + + config { + pins = "gpio110"; + drive-strength = <4>; + bias-bus-hold; + }; + }; + }; + + /* WSA speaker reset pins */ + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio108"; + function = "gpio"; + }; + + config { + pins = "gpio108"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio108"; + function = "gpio"; + }; + + config { + pins = "gpio108"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + spkr_2_sd_n { + spkr_2_sd_n_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio109"; + function = "gpio"; + }; + + config { + pins = "gpio109"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_2_sd_n_active: spkr_2_sd_n_active { + mux { + pins = "gpio109"; + function = "gpio"; + }; + + config { + pins = "gpio109"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + wcd9xxx_intr { + wcd_intr_default: wcd_intr_default{ + mux { + pins = "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio122"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + ter_i2s_sck_ws { + ter_i2s_sck_sleep: ter_i2s_sck_sleep { + mux { + pins = "gpio115", "gpio116"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio115", "gpio116"; + drive-strength = <2>; /* 2 mA */ + bias-disable; + }; + }; + + ter_i2s_sck_active: ter_i2s_sck_active { + mux { + pins = "gpio115", "gpio116"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio115", "gpio116"; + drive-strength = <8>; /* 8 mA */ + input-enable; + bias-disable; + }; + }; + }; + + ter_i2s_data0 { + ter_i2s_data0_sleep: ter_i2s_data0_sleep { + mux { + pins = "gpio117"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio117"; + drive-strength = <2>; /* 2 mA */ + bias-pull-up; + }; + }; + + ter_i2s_data0_active: ter_i2s_data0_active { + mux { + pins = "gpio117"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio117"; + drive-strength = <2>; /* 8 mA */ + input-enable; + bias-disable; + }; + }; + }; + + ter_i2s_data1 { + ter_i2s_data1_sleep: ter_i2s_data1_sleep { + mux { + pins = "gpio118"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio118"; + drive-strength = <2>; /* 2 mA */ + bias-disable; + }; + }; + + ter_i2s_data1_active: ter_i2s_data1_active { + mux { + pins = "gpio118"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio118"; + drive-strength = <8>; /* 8 mA */ + output-high; + bias-disable; + }; + }; + }; + + pcie0 { + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio90"; + function = "pcie_clk"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio100"; + function = "gpio"; + }; + + config { + pins = "gpio100"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pri_aux_pcm_sck { + pri_aux_pcm_sck_sleep: pri_aux_pcm_sck_sleep { + mux { + pins = "gpio108"; + function = "mi2s_1"; + }; + + config { + pins = "gpio108"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + pri_aux_pcm_sck_active: pri_aux_pcm_sck_active { + mux { + pins = "gpio108"; + function = "mi2s_1"; + }; + + config { + pins = "gpio108"; + drive-strength = <8>; /* 8 mA */ + input-enable; + }; + }; + }; + + pri_aux_pcm_ws { + pri_aux_pcm_ws_sleep: pri_aux_pcm_ws_sleep { + mux { + pins = "gpio109"; + function = "mi2s_1"; + }; + + config { + pins = "gpio109"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + pri_aux_pcm_ws_active: pri_aux_pcm_ws_active { + mux { + pins = "gpio109"; + function = "mi2s_1"; + }; + + config { + pins = "gpio109"; + drive-strength = <8>; /* 8 mA */ + input-enable; + }; + }; + }; + + pri_aux_pcm_data0 { + pri_aux_pcm_data0_sleep: pri_aux_pcm_data0_sleep { + mux { + pins = "gpio110"; + function = "mi2s_1"; + }; + + config { + pins = "gpio110"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + pri_aux_pcm_data0_active: pri_aux_pcm_data0_active { + mux { + pins = "gpio110"; + function = "mi2s_1"; + }; + + config { + pins = "gpio110"; + drive-strength = <8>; /* 8 mA */ + input-enable; + }; + }; + }; + + pri_aux_pcm_data1 { + pri_aux_pcm_data1_sleep: pri_aux_pcm_data1_sleep { + mux { + pins = "gpio111"; + function = "mi2s_1"; + }; + + config { + pins = "gpio111"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + pri_aux_pcm_data1_active: pri_aux_pcm_data1_active { + mux { + pins = "gpio111"; + function = "mi2s_1"; + }; + + config { + pins = "gpio111"; + drive-strength = <8>; /* 8 mA */ + output-high; + }; + }; + }; + + pmx_ts_int_active { + ts_int_active: ts_int_active { + mux { + pins = "gpio89"; + function = "gpio"; + }; + + config { + pins = "gpio89"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio89"; + function = "gpio"; + }; + + config { + pins = "gpio89"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_reset_active { + ts_reset_active: ts_reset_active { + mux { + pins = "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio88"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + ts_release: ts_release { + mux { + pins = "gpio89", "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio89", "gpio88"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + cci0_active: cci0_active { + mux { + /* CLK, DATA */ + pins = "gpio32", "gpio33"; + function = "cci_i2c"; + }; + + config { + pins = "gpio32", "gpio33"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio32", "gpio33"; + function = "cci_i2c"; + }; + + config { + pins = "gpio32", "gpio33"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA */ + pins = "gpio34", "gpio35"; + function = "cci_i2c"; + }; + + config { + pins = "gpio34", "gpio35"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio34", "gpio35"; + function = "cci_i2c"; + }; + + config { + pins = "gpio34", "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio28"; + function = "cam_mclk"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio28"; + function = "cam_mclk"; + }; + + config { + pins = "gpio28"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_active: cam_sensor_rear_active { + /* RESET */ + mux { + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_suspend: cam_sensor_rear_suspend { + /* RESET */ + mux { + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_front_active: cam_sensor_front_active { + /* RESET */ + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_suspend: cam_sensor_front_suspend { + /* RESET */ + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_rear2_active: cam_sensor_rear2_active { + /* RESET */ + mux { + pins = "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio45"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear2_suspend: cam_sensor_rear2_suspend { + /* RESET */ + mux { + pins = "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio45"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio29"; + function = "cam_mclk"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio29"; + function = "cam_mclk"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio30"; + function = "cam_mclk"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio30"; + function = "cam_mclk"; + }; + + config { + pins = "gpio30"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio31"; + function = "cam_mclk"; + }; + + config { + pins = "gpio31"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio31"; + function = "cam_mclk"; + }; + + config { + pins = "gpio31"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + flash_led3_front { + flash_led3_front_en: flash_led3_front_en { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + drive_strength = <2>; + output-high; + bias-disable; + }; + }; + + flash_led3_front_dis: flash_led3_front_dis { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + drive_strength = <2>; + output-low; + bias-disable; + }; + }; + }; + + cam_sensor_ir_cut_on: cam_sensor_ir_led_on { + /*IR_LED*/ + mux { + pins = "gpio73", "gpio74"; + function = "gpio"; + }; + + config { + pins = "gpio73", "gpio74"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_ir_cut_off: cam_sensor_ir_led_off { + /*IR_LED*/ + mux { + pins = "gpio73", "gpio74"; + function = "gpio"; + }; + + config { + pins = "gpio73", "gpio74"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + hs0_i2s_sck_ws { + hs0_i2s_sck_sleep: hs0_i2s_sck_sleep { + mux { + pins = "gpio36", "gpio37"; + function = "hs0_mi2s"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + hs0_i2s_sck_active: hs0_i2s_sck_active { + mux { + pins = "gpio36", "gpio37"; + function = "hs0_mi2s"; + }; + + config { + pins = "gpio36", "gpio37"; + drive-strength = <4>; /* 4 mA */ + bias-no-pull; + input-enable; + }; + }; + }; + + hs0_i2s_data0 { + hs0_i2s_data0_sleep: hs0_i2s_data0_sleep { + mux { + pins = "gpio38"; + function = "hs0_mi2s"; + }; + + config { + pins = "gpio38"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + hs0_i2s_data0_active: hs0_i2s_data0_active { + mux { + pins = "gpio38"; + function = "hs0_mi2s"; + }; + + config { + pins = "gpio38"; + drive-strength = <4>; /* 4 mA */ + bias-no-pull; + input-enable; + }; + }; + }; + + hs0_i2s_data1 { + hs0_i2s_data1_sleep: hs0_i2s_data1_sleep { + mux { + pins = "gpio39"; + function = "hs0_mi2s"; + }; + + config { + pins = "gpio39"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + hs0_i2s_data1_active: hs0_i2s_data1_active { + mux { + pins = "gpio39"; + function = "hs0_mi2s"; + }; + + config { + pins = "gpio39"; + drive-strength = <4>; /* 4 mA */ + bias-no-pull; + output-high; + }; + }; + }; + + hs1_i2s_sck_ws { + hs1_i2s_sck_sleep: hs1_i2s_sck_sleep { + mux { + pins = "gpio24", "gpio25"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + hs1_i2s_sck_active: hs1_i2s_sck_active { + mux { + pins = "gpio24", "gpio25"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio24", "gpio25"; + drive-strength = <4>; /* 4 mA */ + bias-no-pull; + input-enable; + }; + }; + }; + + hs1_i2s_data0 { + hs1_i2s_data0_sleep: hs1_i2s_data0_sleep { + mux { + pins = "gpio26"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio26"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + hs1_i2s_data0_active: hs1_i2s_data0_active { + mux { + pins = "gpio26"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio26"; + drive-strength = <4>; /* 4 mA */ + bias-no-pull; + input-enable; + }; + }; + }; + + hs1_i2s_data1 { + hs1_i2s_data1_sleep: hs1_i2s_data1_sleep { + mux { + pins = "gpio27"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio27"; + drive-strength = <2>; /* 2 mA */ + }; + }; + + hs1_i2s_data1_active: hs1_i2s_data1_active { + mux { + pins = "gpio27"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio27"; + drive-strength = <4>; /* 4 mA */ + bias-no-pull; + output-high; + }; + }; + }; + + emac { + emac_mdc: emac_mdc { + mux { + pins = "gpio113"; + function = "rgmii_mdc"; + }; + + config { + pins = "gpio113"; + bias-pull-up; + }; + }; + emac_mdio: emac_mdio { + mux { + pins = "gpio114"; + function = "rgmii_mdio"; + }; + + config { + pins = "gpio114"; + bias-pull-up; + }; + }; + + emac_rgmii_txd0: emac_rgmii_txd0 { + mux { + pins = "gpio96"; + function = "rgmii_txd0"; + }; + + config { + pins = "gpio96"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txd1: emac_rgmii_txd1 { + mux { + pins = "gpio95"; + function = "rgmii_txd1"; + }; + + config { + pins = "gpio95"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txd2: emac_rgmii_txd2 { + mux { + pins = "gpio94"; + function = "rgmii_txd2"; + }; + + config { + pins = "gpio94"; + bias-pull-up; + drive-strength = <16>; + }; + }; + emac_rgmii_txd3: emac_rgmii_txd3 { + mux { + pins = "gpio93"; + function = "rgmii_txd3"; + }; + + config { + pins = "gpio93"; + bias-pull-up; + drive-strength = <16>; + }; + }; + emac_rgmii_txc: emac_rgmii_txc { + mux { + pins = "gpio92"; + function = "rgmii_txc"; + }; + + config { + pins = "gpio92"; + bias-pull-up; + drive-strength = <16>; + }; + }; + emac_rgmii_tx_ctl: emac_rgmii_tx_ctl { + mux { + pins = "gpio97"; + function = "rgmii_tx"; + }; + + config { + pins = "gpio97"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + + emac_rgmii_rxd0: emac_rgmii_rxd0 { + mux { + pins = "gpio83"; + function = "rgmii_rxd0"; + }; + + config { + pins = "gpio83"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2MA */ + }; + }; + + emac_rgmii_rxd1: emac_rgmii_rxd1 { + mux { + pins = "gpio82"; + function = "rgmii_rxd1"; + }; + + config { + pins = "gpio82"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_rgmii_rxd2: emac_rgmii_rxd2 { + mux { + pins = "gpio81"; + function = "rgmii_rxd2"; + }; + + config { + pins = "gpio81"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + emac_rgmii_rxd3: emac_rgmii_rxd3 { + mux { + pins = "gpio103"; + function = "rgmii_rxd3"; + }; + + config { + pins = "gpio103"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + emac_rgmii_rxc: emac_rgmii_rxc { + mux { + pins = "gpio102"; + function = "rgmii_rxc"; + }; + + config { + pins = "gpio102"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + emac_rgmii_rxc_suspend: emac_rgmii_rxc_suspend { + mux { + pins = "gpio102"; + function = "rgmii_rxc"; + }; + + config { + pins = "gpio102"; + input-disable; + }; + }; + emac_rgmii_rxc_resume: emac_rgmii_rxc_resume { + mux { + pins = "gpio102"; + function = "rgmii_rxc"; + }; + + config { + pins = "gpio102"; + input-enable; + bias-disable;/* NO pull */ + }; + }; + emac_rgmii_rx_ctl: emac_rgmii_rx_ctl { + mux { + pins = "gpio112"; + function = "rgmii_rx"; + }; + + config { + pins = "gpio112"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + emac_phy_intr: emac_phy_intr { + mux { + pins = "gpio121"; + function = "emac_phy"; + }; + + config { + pins = "gpio121"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + emac_phy_reset_state: emac_phy_reset_state { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + bias-pull-up; + drive-strength = <16>; + }; + }; + emac_pin_pps_0: emac_pin_pps_0 { + mux { + pins = "gpio91"; + function = "rgmii_sync"; + }; + + config { + pins = "gpio91"; + bias-pull-up; + drive-strength = <16>; + }; + }; + }; + + bt_en_active: bt_en_active { + mux { + pins = "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio85"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + usb0_hs_ac_en_default: usb0_hs_ac_en_default { + mux { + pins = "gpio88"; + function = "usb0_hs_ac"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; + bias-disable; + }; + }; + + usb1_hs_ac_en_default: usb1_hs_ac_en_default { + mux { + pins = "gpio89"; + function = "usb1_hs_ac"; + }; + + config { + pins = "gpio89"; + drive-strength = <2>; + bias-disable; + }; + }; + }; +}; + + +&pm6150_gpios { + wcd934x_mclk { + wcd934x_mclk_default: wcd934x_mclk_default{ + pins = "gpio8"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <0>; + bias-disable; + output-low; + }; + }; + + smb_stat { + smb_stat_default: smb_stat_default { + pins = "gpio3"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = <0>; + }; + }; +}; + +&pm6150l_gpios { + cam_sensor_dvdd_en: cam_sensor_dvdd_en { + pins = "gpio3"; + function = "normal"; + power-source = <0>; + output-low; + }; + cam_sensor_0_vana: cam_sensor_0_vana { + pins = "gpio9"; + function = "normal"; + power-source = <0>; + output-low; + }; + cam_sensor_1_2_vana: cam_sensor_1_2_vana { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + + }; +}; + diff --git a/arch/arm/boot/dts/qcom/sm6150-pm.dtsi b/arch/arm/boot/dts/qcom/sm6150-pm.dtsi new file mode 100644 index 000000000000..ca97a23d825c --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-pm.dtsi @@ -0,0 +1,163 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm-cluster@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + label = "L3"; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xfff>; + + qcom,pm-cluster-level@0 { /* D1 */ + reg = <0>; + label = "l3-wfi"; + qcom,psci-mode = <0x1>; + qcom,entry-latency-us = <660>; + qcom,exit-latency-us = <600>; + qcom,min-residency-us = <1260>; + }; + + qcom,pm-cluster-level@1 { /* D4 */ + reg = <1>; + label = "l3-pc"; + qcom,psci-mode = <0x4>; + qcom,entry-latency-us = <2752>; + qcom,exit-latency-us = <3048>; + qcom,min-residency-us = <6118>; + qcom,min-child-idx = <2>; + qcom,is-reset; + }; + + qcom,pm-cluster-level@2 { /* Cx Ret */ + reg = <2>; + label = "cx-ret"; + qcom,psci-mode = <0x124>; + qcom,entry-latency-us = <3638>; + qcom,exit-latency-us = <4562>; + qcom,min-residency-us = <8467>; + qcom,min-child-idx = <2>; + qcom,is-reset; + qcom,notify-rpm; + }; + + qcom,pm-cluster-level@3 { /* LLCC off, AOSS sleep */ + reg = <3>; + label = "llcc-off"; + qcom,psci-mode = <0xB24>; + qcom,entry-latency-us = <3263>; + qcom,exit-latency-us = <6562>; + qcom,min-residency-us = <9826>; + qcom,min-child-idx = <2>; + qcom,is-reset; + qcom,notify-rpm; + }; + + qcom,pm-cpu@0 { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 + &CPU5>; + + qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + label = "wfi"; + qcom,psci-cpu-mode = <0x1>; + qcom,entry-latency-us = <61>; + qcom,exit-latency-us = <60>; + qcom,min-residency-us = <121>; + }; + + qcom,pm-cpu-level@1 { /* C3 */ + reg = <1>; + label = "pc"; + qcom,psci-cpu-mode = <0x3>; + qcom,entry-latency-us = <549>; + qcom,exit-latency-us = <901>; + qcom,min-residency-us = <1774>; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + + qcom,pm-cpu-level@2 { /* C4 */ + reg = <2>; + label = "rail-pc"; + qcom,psci-cpu-mode = <0x4>; + qcom,entry-latency-us = <702>; + qcom,exit-latency-us = <915>; + qcom,min-residency-us = <4001>; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + + qcom,pm-cpu@1 { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,cpu = <&CPU6 &CPU7>; + + qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + label = "wfi"; + qcom,psci-cpu-mode = <0x1>; + qcom,entry-latency-us = <55>; + qcom,exit-latency-us = <66>; + qcom,min-residency-us = <121>; + }; + + qcom,pm-cpu-level@1 { /* C3 */ + reg = <1>; + label = "pc"; + qcom,psci-cpu-mode = <0x3>; + qcom,entry-latency-us = <523>; + qcom,exit-latency-us = <1244>; + qcom,min-residency-us = <2207>; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + + qcom,pm-cpu-level@2 { /* C4 */ + reg = <2>; + label = "rail-pc"; + qcom,psci-cpu-mode = <0x4>; + qcom,entry-latency-us = <526>; + qcom,exit-latency-us = <1854>; + qcom,min-residency-us = <5555>; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + }; + }; + + qcom,rpm-stats@c300000 { + compatible = "qcom,rpm-stats"; + reg = <0xc300000 0x1000>, <0xc3f0004 0x4>; + reg-names = "phys_addr_base", "offset_addr"; + qcom,num-records = <3>; + }; + + qcom,rpmh-master-stats@b221200 { + compatible = "qcom,rpmh-master-stats-v1"; + reg = <0xb221200 0x60>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-pm6125-interposer-trinket.dtsi b/arch/arm/boot/dts/qcom/sm6150-pm6125-interposer-trinket.dtsi new file mode 100644 index 000000000000..f4b7508aa8ac --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-pm6125-interposer-trinket.dtsi @@ -0,0 +1,721 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include + +&spmi_bus { + /delete-node/ qcom,pm6150@0; + /delete-node/ qcom,pm6150@1; + /delete-node/ qcom,pm6150l@4; + /delete-node/ qcom,pm6150l@5; +}; + +&thermal_zones { + pm6150-tz { + /delete-property/ thermal-sensors; + }; + + pm6150-ibat-lvl0 { + /delete-property/ thermal-sensors; + }; + + pm6150-ibat-lvl1 { + /delete-property/ thermal-sensors; + + }; + + pm6150-vbat-lvl0 { + /delete-property/ thermal-sensors; + }; + + pm6150-vbat-lvl1 { + /delete-property/ thermal-sensors; + }; + + pm6150-vbat-lvl2 { + /delete-property/ thermal-sensors; + }; + + pm6150l-tz { + /delete-property/ thermal-sensors; + }; + + pm6150l-vph-lvl0 { + /delete-property/ thermal-sensors; + }; + + pm6150l-vph-lvl1 { + /delete-property/ thermal-sensors; + }; + + pm6150l-vph-lvl2 { + /delete-property/ thermal-sensors; + }; + + xo-therm { + /delete-property/ thermal-sensors; + }; + + sdm-therm { + /delete-property/ thermal-sensors; + }; + + conn-therm { + /delete-property/ thermal-sensors; + }; + + emmc_ufs-therm { + /delete-property/ thermal-sensors; + }; + + rf_pa0_therm-therm { + /delete-property/ thermal-sensors; + }; + + camera_flash-therm { + /delete-property/ thermal-sensors; + }; + + quiet-therm { + /delete-property/ thermal-sensors; + }; + + quiet-therm-step { + /delete-property/ thermal-sensors; + }; + + soc { + /delete-property/ thermal-sensors; + }; + + quiet-therm-step { + cooling-maps { + battery_lvl0 { + /delete-property/ cooling-device; + }; + + battery_lvl1 { + /delete-property/ cooling-device; + }; + + battery_lvl2 { + /delete-property/ cooling-device; + }; + + battery_lvl3 { + /delete-property/ cooling-device; + }; + }; + }; +}; + +&usb0 { + /delete-property/ extcon; +}; + +&soc { + qcom,lpass@62400000 { + /delete-property/ vdd_cx-supply; + }; + + /* Regulators */ + /delete-node/ rpmh-regulator-modemlvl; + /delete-node/ rpmh-regulator-lmxlvl; + /delete-node/ rpmh-regulator-lcxlvl; + + rpmh-regulator-mxlvl { + /delete-node/ regulator-pm6150-s3; + /delete-node/ regulator-pm6150-s3-level-ao; + + VDD_MX_LEVEL: + S5A_LEVEL: pm6150_s5_level: regulator-pm6150-s5 { + regulator-name = "pm6150_s5_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + + VDD_MX_LEVEL_AO: + S5A_LEVEL_AO: pm6150_s5_level_ao: regulator-pm6150-s5-level-ao { + regulator-name = "pm6150_s5_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-cxlvl { + /delete-property/ pm6150_s1_level-parent-supply; + /delete-property/ pm6150_s1_level_ao-parent-supply; + /delete-node/ regulator-pm6150-s1; + /delete-node/ regulator-pm6150-s1-level-ao; + VDD_CX_LEVEL: + VDD_MSS_LEVEL: + S3A_LEVEL: pm6150_s3_level: regulator-pm6150-s3 { + regulator-name = "pm6150_s3_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + + VDD_CX_LEVEL_AO: + S3A_LEVEL_AO: pm6150_s3_level_ao: regulator-pm6150-s3-level-ao { + qcom,set = ; + regulator-name = "pm6150_s3_level_ao"; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + }; + + rpmh-regulator-ldoa5 { + L5A: pm6150_l5: regulator-pm6150-l5 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3100000>; + qcom,init-voltage = <1650000>; + }; + }; + + rpmh-regulator-ldoa6 { + L6A: pm6150_l6: regulator-pm6150-l6 { + regulator-min-microvolt = <568000>; + regulator-max-microvolt = <650000>; + qcom,init-voltage = <568000>; + }; + }; + + rpmh-regulator-ldoa7 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L7A: pm6150_l7: regulator-pm6150-l7 { + regulator-name = "pm6150_l7"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <975000>; + qcom,init-voltage = <800000>; + qcom,init-mode = ; + }; + }; + + /* pm6125 L8 - WCSS_CX supply */ + rpmh-regulator-ldoa8 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa8"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L8A: pm6150_l8: regulator-pm6150-l8 { + regulator-name = "pm6150_l8"; + qcom,set = ; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + qcom,init-voltage = <400000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa9 { + L9A: pm6150_l9: regulator-pm6150-l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1829000>; + qcom,init-voltage = <1800000>; + }; + }; + + rpmh-regulator-ldoa10 { + L10A: pm6150_l10: regulator-pm6150-l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1890000>; + qcom,init-voltage = <1800000>; + }; + }; + + rpmh-regulator-ldoa11 { + L11A: pm6150_l11: regulator-pm6150-l11 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <1984000>; + qcom,init-voltage = <1624000>; + }; + }; + + rpmh-regulator-ldoa12 { + L12A: pm6150_l12: regulator-pm6150-l12 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <1904000>; + qcom,init-voltage = <1648000>; + }; + }; + + rpmh-regulator-ldoa13 { + L13A: pm6150_l13: regulator-pm6150-l13 { + regulator-min-microvolt = <1720000>; + regulator-max-microvolt = <1824000>; + qcom,init-voltage = <1720000>; + }; + }; + + rpmh-regulator-ldoa14 { + L14A: pm6150_l14: regulator-pm6150-l14 { + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <1904000>; + qcom,init-voltage = <1696000>; + }; + }; + + rpmh-regulator-ldoa15 { + L15A: pm6150_l15: regulator-pm6150-l15 { + regulator-min-microvolt = <2928000>; + regulator-max-microvolt = <3230000>; + qcom,init-voltage = <2928000>; + }; + }; + + rpmh-regulator-ldoa16 { + L16A: pm6150_l16: regulator-pm6150-l16 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1648000>; + }; + }; + + rpmh-regulator-ldoa17 { + L17A: pm6150_l17: regulator-pm6150-l17 { + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1144000>; + }; + }; + + rpmh-regulator-ldoa18 { + L18A: pm6150_l18: regulator-pm6150-l18 { + regulator-min-microvolt = <1136000>; + regulator-max-microvolt = <1260000>; + qcom,init-voltage = <1136000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa19 { + L19A: pm6150_l19: regulator-pm6150-l19 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <1650000>; + }; + }; + + rpmh-regulator-ldoa20 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa20"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L20A: pm6150_l20: regulator-pm6150-l20 { + regulator-name = "pm6150_l20"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa21 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa21"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L21A: pm6150_l21: regulator-pm6150-l21 { + regulator-name = "pm6150_l21"; + qcom,set = ; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2856000>; + qcom,init-voltage = <2600000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa22 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa22"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L22A: pm6150_l22: regulator-pm6150-l22 { + regulator-name = "pm6150_l22"; + qcom,set = ; + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <3304000>; + qcom,init-voltage = <2944000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa23 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa23"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L23A: pm6150_l23: regulator-pm6150-l23 { + regulator-name = "pm6150_l23"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3400000>; + qcom,init-voltage = <2700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa24 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa24"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L24A: pm6150_l24: regulator-pm6150-l24 { + regulator-name = "pm6150_l24"; + qcom,set = ; + regulator-min-microvolt = <1696000>; + regulator-max-microvolt = <3304000>; + qcom,init-voltage = <1696000>; + qcom,init-mode = ; + }; + }; +}; + +#include "pm6125.dtsi" +#include "pmi632.dtsi" + +&pm6125_clkdiv { + /delete-property/ clocks; + clocks = <&clock_rpmh RPMH_CXO_CLK>; +}; + +&pm6125_vadc { + pinctrl-names = "default"; + pinctrl-0 = <&camera_therm_default &emmc_therm_default>; + + rf_pa0_therm { + reg = ; + label = "rf_pa0_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + quiet_therm { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + camera_flash_therm { + reg = ; + label = "camera_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + emmc_ufs_therm { + reg = ; + label = "emmc_ufs_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm6125_gpios { + camera_therm { + camera_therm_default: camera_therm_default { + pins = "gpio3"; + bias-high-impedance; + }; + }; + + emmc_therm { + emmc_therm_default: emmc_therm_default { + pins = "gpio6"; + bias-high-impedance; + }; + }; +}; + +&spmi_bus { + qcom,pm6125@0 { + pm6125_adc_tm_iio: adc_tm@3400 { + compatible = "qcom,adc-tm5-iio"; + reg = <0x3400 0x100>; + #thermal-sensor-cells = <1>; + io-channels = <&pm6125_vadc ADC_GPIO1_PU2>, + <&pm6125_vadc ADC_GPIO3_PU2>; + + emmc_ufs_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + camera_flash_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + }; + }; +}; + +&pm6125_adc_tm { + io-channels = <&pm6125_vadc ADC_AMUX_THM1_PU2>, + <&pm6125_vadc ADC_AMUX_THM2_PU2>, + <&pm6125_vadc ADC_XO_THERM_PU2>; + + /* Channel nodes */ + rf_pa0_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + quiet_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pmi632_vadc { + pinctrl-names = "default"; + pinctrl-0 = <&conn_therm_default &skin_therm_default>; + + xo_therm { + status = "disabled"; + }; + + bat_therm { + qcom,lut-index = <1>; + }; + + bat_therm_30k { + qcom,lut-index = <1>; + }; + + bat_therm_400k { + qcom,lut-index = <1>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_therm { + reg = ; + label = "skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pmi632_gpios { + conn_therm { + conn_therm_default: conn_therm_default { + pins = "gpio1"; + bias-high-impedance; + }; + }; + + skin_therm { + skin_therm_default: skin_therm_default { + pins = "gpio3"; + bias-high-impedance; + }; + }; +}; + +&pmi632_adc_tm { + io-channels = <&pmi632_vadc ADC_GPIO1_PU2>, + <&pmi632_vadc ADC_VBAT_SNS>, + <&pmi632_vadc ADC_GPIO2_PU2>; + + /* Channel nodes */ + conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + vbat_sns { + reg = ; + qcom,kernel-client; + qcom,scale-type = <0>; + qcom,prescaling = <3>; + }; + + skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + + /delete-node/ sdm-therm; + /delete-node/ conn-therm; + /delete-node/ xo-therm; + /delete-node/ emmc_ufs-therm; + /delete-node/ rf_pa0_therm-therm; + /delete-node/ camera_flash-therm; + /delete-node/ quiet-therm; + + rf-pa0-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm ADC_XO_THERM_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmi632_adc_tm ADC_GPIO1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmi632_adc_tm ADC_GPIO2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + emmc-ufs-therm-adc { + polling-delay-passive = <0>; + polling-delay = <5000>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm_iio ADC_GPIO1_PU2>; + }; + + camera-ftherm-adc { + polling-delay-passive = <0>; + polling-delay = <5000>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm_iio ADC_GPIO3_PU2>; + }; + +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-qrd-overlay.dts b/arch/arm/boot/dts/qcom/sm6150-qrd-overlay.dts new file mode 100644 index 000000000000..174fd45a709f --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-qrd-overlay.dts @@ -0,0 +1,67 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "sm6150-audio-overlay.dtsi" +#include "sm6150-qrd.dtsi" + +/ { + model = "QRD"; + compatible = "qcom,sm6150-qrd", "qcom,sm6150", "qcom,qrd"; + qcom,board-id = <11 0>; +}; + +&dsi_hx83112a_truly_vid_display { + qcom,dsi-display-active; +}; + +&sm6150_snd { + qcom,model = "sm6150-qrd-snd-card"; + qcom,audio-routing = + "AMIC1", "MIC BIAS1", + "MIC BIAS1", "Analog Mic1", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Analog Mic2", + "AMIC3", "MIC BIAS3", + "MIC BIAS3", "Analog Mic3", + "TX_AIF1 CAP", "VA_MCLK", + "TX_AIF2 CAP", "VA_MCLK", + "RX AIF1 PB", "VA_MCLK", + "RX AIF2 PB", "VA_MCLK", + "RX AIF3 PB", "VA_MCLK", + "RX AIF4 PB", "VA_MCLK", + "HPHL_OUT", "VA_MCLK", + "HPHR_OUT", "VA_MCLK", + "AUX_OUT", "VA_MCLK", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "IN3_AUX", "AUX_OUT", + "TX SWR_ADC0", "ADC1_OUTPUT", + "TX SWR_ADC2", "ADC2_OUTPUT", + "WSA SRC0_INP", "SRC0", + "WSA_TX DEC0_INP", "TX DEC0 MUX", + "WSA_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "SpkrLeft IN", "WSA_SPK1 OUT", + "WSA_SPK1 OUT", "VA_MCLK"; + qcom,wsa-max-devs = <1>; + qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0213>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrLeft"; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-qrd.dts b/arch/arm/boot/dts/qcom/sm6150-qrd.dts new file mode 100644 index 000000000000..2be0c3b8ed40 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-qrd.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm6150.dtsi" +#include "sm6150-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM6150 PM6150 QRD"; + compatible = "qcom,sm6150-qrd", "qcom,sm6150", "qcom,qrd"; + qcom,board-id = <11 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-qrd.dtsi b/arch/arm/boot/dts/qcom/sm6150-qrd.dtsi new file mode 100644 index 000000000000..8035667588db --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-qrd.dtsi @@ -0,0 +1,291 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm6150-thermal-overlay.dtsi" +#include +#include +#include +#include "sm6150-sde-display.dtsi" +#include "sm6150-camera-sensor-qrd.dtsi" + +&qupv3_se3_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + #include "smb1390.dtsi" + #include "smb1355.dtsi" +}; + +&pm6150l_gpios { + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio2"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm6150l_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + linux,can-disable; + debounce-interval = <15>; + gpio-key,wakeup; + }; + }; + + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + #include "qg-batterydata-mlp356477-2800mah.dtsi" + }; +}; + +&qupv3_se7_4uart { + status = "ok"; +}; + +&pm6150l_wled { + qcom,string-cfg= <3>; + qcom,leds-per-string = <7>; + status = "ok"; +}; + +&pm6150l_lcdb { + status = "ok"; +}; + +&qupv3_se0_2uart { + status = "ok"; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v3-660"; + + vdda-phy-supply = <&pm6150_l4>; /* 0.9v */ + vdda-phy-always-on; + vdda-pll-supply = <&pm6150_l11>; + vdda-phy-max-microamp = <30000>; + vdda-pll-max-microamp = <12000>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm6150l_l11>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm6150_l12>; + vcc-max-microamp = <600000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm6150l_l3>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vddp-ref-clk-min-uV = <1232000>; + qcom,vddp-ref-clk-max-uV = <1260000>; + + status = "ok"; +}; + +&pm6150_qg { + qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <100>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; +}; + +&pm6150_charger { + io-channels = <&pm6150_vadc ADC_USB_IN_V_16>, + <&pm6150_vadc ADC_USB_IN_I>, + <&pm6150_vadc ADC_CHG_TEMP>, + <&pm6150_vadc ADC_DIE_TEMP>, + <&pm6150_vadc ADC_AMUX_THM4_PU2>, + <&pm6150_vadc ADC_SBUx>, + <&pm6150_vadc ADC_VPH_PWR>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp", + "die_temp", + "conn_temp", + "sbux_res", + "vph_voltage"; + qcom,battery-data = <&mtp_batterydata>; + qcom,auto-recharge-soc = <98>; + qcom,sw-jeita-enable; + qcom,fcc-stepping-enable; + qcom,suspend-input-on-debug-batt; + qcom,sec-charger-config = <1>; + qcom,thermal-mitigation = <4200000 3500000 3000000 + 2500000 2000000 1500000 1000000 500000>; + dpdm-supply = <&qusb_phy0>; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; +}; + +&smb1390 { + /delete-property/ interrupts; + interrupts = <0x0 0xc2 0x0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1390_charger { + /delete-property/ compatible; + compatible = "qcom,smb1390-charger-psy"; + io-channels = <&pm6150_vadc ADC_AMUX_THM3>; + io-channel-names = "cp_die_temp"; + status = "ok"; +}; + +&qupv3_se1_i2c { + status = "okay"; + himax_ts@48 { + compatible = "himax,hxcommon"; + reg = <0x48>; + interrupt-parent = <&tlmm>; + interrupts = <125 0x2008>; + vdd-supply = <&pm6150_l10>; + avdd-supply = <&pm6150l_l7>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + himax,panel-coords = <0 1080 0 2160>; + himax,display-coords = <0 1080 0 2160>; + himax,irq-gpio = <&tlmm 89 0x00>; + himax,rst-gpio = <&tlmm 88 0x00>; + report_type = <1>; + }; +}; + +&qupv3_se5_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + + #address-cells = <1>; + #size-cells = <0>; + + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 86 0x00>; + qcom,nq-ven = <&tlmm 84 0x00>; + qcom,nq-firm = <&tlmm 85 0x00>; + qcom,nq-clkreq = <&tlmm 50 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <86 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active + &nfc_clk_req_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend + &nfc_clk_req_suspend>; + }; +}; + +&dsi_hx83112a_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 90 0>; + qcom,platform-reset-gpio = <&tlmm 91 0>; +}; + +&sdhc_1 { + vdd-supply = <&pm6150l_l11>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&pm6150_l12>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm6150l_l9>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&pm6150l_l6>; + qcom,vdd-io-voltage-level = <1800000 3100000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&tlmm 99 0>; + + status = "ok"; +}; + +&soc { + fpc1020 { + compatible = "fpc,fpc1020"; + interrupt-parent = <&tlmm>; + interrupts = <93 0>; + fpc,gpio_rst = <&tlmm 101 0x0>; + fpc,gpio_irq = <&tlmm 93 0>; + vcc_spi-supply = <&pm6150_l10>; + vdd_io-supply = <&pm6150_l10>; + vdd_ana-supply = <&pm6150_l10>; + fpc,enable-on-boot; + pinctrl-names = "fpc1020_reset_reset", + "fpc1020_reset_active", + "fpc1020_irq_active"; + pinctrl-0 = <&fpc_reset_low>; + pinctrl-1 = <&fpc_reset_high>; + pinctrl-2 = <&fpc_int_low>; + }; + +}; + +/* Primary USB port related High Speed PHY */ +&qusb_phy0 { + qcom,qusb-phy-init-seq = <0xc8 0x80 + 0xb3 0x84 + 0x83 0x88 + 0x07 0x8c + 0x30 0x08 + 0x79 0x0c + 0x21 0x10 + 0x14 0x9c + 0x9f 0x1c + 0x00 0x18>; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-qupv3.dtsi b/arch/arm/boot/dts/qcom/sm6150-qupv3.dtsi new file mode 100644 index 000000000000..cc6dd19ab227 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-qupv3.dtsi @@ -0,0 +1,503 @@ +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + /* + * QUPv3 North & South Instances + * North 0 : SE 4 + * North 1 : SE 5 + * North 2 : SE 6 + * North 3 : SE 7 + * South 0 : SE 0 + * South 1 : SE 1 + * South 2 : SE 2 + * South 3 : SE 3 + */ + + /* QUPv3 South Instances */ + qupv3_0: qcom,qupv3_0_geni_se@8c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x8c0000 0x6000>; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; + qcom,iommu-s1-bypass; + + iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0xc3 0x0>; + }; + }; + + /* Debug UART Instance for CDP/MTP platform */ + qupv3_se0_2uart: qcom,qup_uart@0x880000 { + compatible = "qcom,msm-geni-console"; + reg = <0x880000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_2uart_active>; + pinctrl-1 = <&qupv3_se0_2uart_sleep>; + interrupts = ; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* I2C */ + qupv3_se1_i2c: i2c@884000 { + compatible = "qcom,i2c-geni"; + reg = <0x884000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + dmas = <&gpi_dma0 0 1 3 64 0>, + <&gpi_dma0 1 1 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@888000 { + compatible = "qcom,i2c-geni"; + reg = <0x888000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + dmas = <&gpi_dma0 0 2 3 64 0>, + <&gpi_dma0 1 2 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@88c000 { + compatible = "qcom,i2c-geni"; + reg = <0x88c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + dmas = <&gpi_dma0 0 3 3 64 0>, + <&gpi_dma0 1 3 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se2_spi: spi@888000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x888000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + dmas = <&gpi_dma0 0 2 1 64 0>, + <&gpi_dma0 1 2 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + /* QUPv3 North instances */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0xac0000 0x6000>; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; + qcom,iommu-s1-bypass; + + iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0x363 0x0>; + }; + }; + + /* GNSS UART Instance for CDP/MTP platform */ + qupv3_se4_2uart: qcom,qup_uart@0xa80000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa80000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_2uart_active>; + pinctrl-1 = <&qupv3_se4_2uart_sleep>; + interrupts = ; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* I2C */ + qupv3_se4_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + dmas = <&gpi_dma1 0 0 3 64 0>, + <&gpi_dma1 1 0 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + dmas = <&gpi_dma1 0 1 3 64 0>, + <&gpi_dma1 1 1 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@a88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + dmas = <&gpi_dma1 0 2 3 64 0>, + <&gpi_dma1 1 2 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se7_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + dmas = <&gpi_dma1 0 3 3 64 0>, + <&gpi_dma1 1 3 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se4_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa80000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + dmas = <&gpi_dma1 0 0 1 64 0>, + <&gpi_dma1 1 0 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se6_spi: spi@a88000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa88000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + dmas = <&gpi_dma1 0 2 1 64 0>, + <&gpi_dma1 1 2 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se7_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_active>; + pinctrl-1 = <&qupv3_se7_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + dmas = <&gpi_dma1 0 3 1 64 0>, + <&gpi_dma1 1 3 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + /* + * HS UART instances. HS UART usecases can be supported on these + * instances only. + */ + qupv3_se7_4uart: qcom,qup_uart@0xa8c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xa8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>, + <&qupv3_se7_tx>; + pinctrl-1 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>, + <&qupv3_se7_tx>; + interrupts-extended = <&pdc GIC_SPI 356 0>, + <&tlmm 13 0>; + status = "disabled"; + qcom,wakeup-byte = <0xFD>; + qcom,wrapper-core = <&qupv3_1>; + }; + + /* QUPv3 SSC Instances */ + qupv3_2: qcom,qupv3_2_geni_se@626c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x626c0000 0x6000>; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; + qcom,iommu-s1-bypass; + + iommu_qupv3_2_geni_se_cb: qcom,iommu_qupv3_2_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0x1783 0x0>; + }; + }; + + /* I2C */ + qupv3_se8_i2c: i2c@62680000 { + compatible = "qcom,i2c-geni"; + reg = <0x62680000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_scc SCC_QUPV3_SE0_CLK>, + <&clock_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@62684000 { + compatible = "qcom,i2c-geni"; + reg = <0x62684000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_scc SCC_QUPV3_SE1_CLK>, + <&clock_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se10_i2c: i2c@62688000 { + compatible = "qcom,i2c-geni"; + reg = <0x62688000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_scc SCC_QUPV3_SE2_CLK>, + <&clock_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_i2c_active>; + pinctrl-1 = <&qupv3_se10_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se11_i2c: i2c@6268c000 { + compatible = "qcom,i2c-geni"; + reg = <0x6268c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_scc SCC_QUPV3_SE3_CLK>, + <&clock_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_i2c_active>; + pinctrl-1 = <&qupv3_se11_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se12_i2c: i2c@62690000 { + compatible = "qcom,i2c-geni"; + reg = <0x62690000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_scc SCC_QUPV3_SE4_CLK>, + <&clock_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_i2c_active>; + pinctrl-1 = <&qupv3_se12_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se13_i2c: i2c@62694000 { + compatible = "qcom,i2c-geni"; + reg = <0x62694000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_scc SCC_QUPV3_SE5_CLK>, + <&clock_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_i2c_active>; + pinctrl-1 = <&qupv3_se13_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se9_spi: spi@62684000 { + compatible = "qcom,spi-geni"; + reg = <0x62684000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_scc SCC_QUPV3_SE1_CLK>, + <&clock_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + qcom,disable-dma; + status = "disabled"; + }; + + qupv3_se10_spi: spi@62688000 { + compatible = "qcom,spi-geni"; + reg = <0x62688000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_scc SCC_QUPV3_SE2_CLK>, + <&clock_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_spi_active>; + pinctrl-1 = <&qupv3_se10_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + qcom,disable-dma; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-regulator.dtsi b/arch/arm/boot/dts/qcom/sm6150-regulator.dtsi new file mode 100644 index 000000000000..4450b713c7c2 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-regulator.dtsi @@ -0,0 +1,762 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + /* RPMh regulators */ + /* pm6150 S3 - VDD_MX supply */ + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "mx.lvl"; + + VDD_MX_LEVEL: + S3A_LEVEL: pm6150_s3_level: regulator-pm6150-s3 { + regulator-name = "pm6150_s3_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + + VDD_MX_LEVEL_AO: + S3A_LEVEL_AO: pm6150_s3_level_ao: regulator-pm6150-s3-level-ao { + regulator-name = "pm6150_s3_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + + mx_cdev: mx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&VDD_MX_LEVEL>; + regulator-levels = ; + #cooling-cells = <2>; + }; + }; + + /* pm6150 S1 - VDD_CX supply */ + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "cx.lvl"; + pm6150_s1_level-parent-supply = <&VDD_MX_LEVEL>; + pm6150_s1_level_ao-parent-supply = <&VDD_MX_LEVEL_AO>; + + VDD_CX_LEVEL: + S1A_LEVEL: pm6150_s1_level: regulator-pm6150-s1 { + regulator-name = "pm6150_s1_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + + VDD_CX_LEVEL_AO: + S1A_LEVEL_AO: pm6150_s1_level_ao: regulator-pm6150-s1-level-ao { + qcom,set = ; + regulator-name = "pm6150_s1_level_ao"; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + + cx_cdev: regulator-cdev { + compatible = "qcom,rpmh-reg-cdev"; + mboxes = <&qmp_aop 0>; + qcom,reg-resource-name = "cx"; + #cooling-cells = <2>; + }; + }; + + + rpmh-regulator-smpc1 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpc1"; + S1C: pm6150l_s1: regulator-pm6150l-s1 { + regulator-name = "pm6150l_s1"; + qcom,set = ; + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + qcom,init-voltage = <1128000>; + }; + }; + + rpmh-regulator-smpc2 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpc2"; + S2C: pm6150l_s2: regulator-pm6150l-s2 { + regulator-name = "pm6150l_s2"; + qcom,set = ; + regulator-min-microvolt = <348000>; + regulator-max-microvolt = <648000>; + qcom,init-voltage = <348000>; + }; + }; + + /* pm6150l S7 - VDD_MSS supply */ + rpmh-regulator-modemlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "mss.lvl"; + + VDD_MSS_LEVEL: + S7C_LEVEL: pm6150l_s7_level: regulator-pm6150l-s7 { + regulator-name = "pm6150l_s7_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-smpc8 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpc8"; + S8C: pm6150l_s8: regulator-pm6150l-s8 { + regulator-name = "pm6150l_s8"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + qcom,init-voltage = <1200000>; + }; + }; + + rpmh-regulator-ldoa1 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L1A: pm6150_l1: regulator-pm6150-l1 { + regulator-name = "pm6150_l1"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1252000>; + qcom,init-voltage = <1200000>; + }; + }; + + rpmh-regulator-ldoa2 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L2A: pm6150_l2: regulator-pm6150-l2 { + regulator-name = "pm6150_l2"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1050000>; + qcom,init-voltage = <1000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa3 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L3A: pm6150_l3: regulator-pm6150-l3 { + regulator-name = "pm6150_l3"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1060000>; + qcom,init-voltage = <1000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa4 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + proxy-supply = <&pm6150_l4>; + L4A: pm6150_l4: regulator-pm6150-l4 { + regulator-name = "pm6150_l4"; + qcom,set = ; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + qcom,init-voltage = <875000>; + qcom,init-mode = ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <23800>; + }; + }; + + rpmh-regulator-ldoa5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L5A: pm6150_l5: regulator-pm6150-l5 { + regulator-name = "pm6150_l5"; + qcom,set = ; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2970000>; + qcom,init-voltage = <2500000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa6 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L6A: pm6150_l6: regulator-pm6150-l6 { + regulator-name = "pm6150_l6"; + qcom,set = ; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <650000>; + qcom,init-voltage = <600000>; + qcom,init-mode = ; + }; + }; + + /* pm6150 L7 - LPI_MX supply */ + rpmh-regulator-lmxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "lmx.lvl"; + L7A_LEVEL: pm6150_l7_level: regulator-pm6150-l7 { + regulator-name = "pm6150_l7_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + /* pm6150 L8 - LPI_CX supply */ + rpmh-regulator-lcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "lcx.lvl"; + L8A_LEVEL: pm6150_l8_level: regulator-pm6150-l8 { + regulator-name = "pm6150_l8_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + /* pm6150 L9 - WCSS_CX supply */ + rpmh-regulator-ldoa9 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L9A: pm6150_l9: regulator-pm6150-l9 { + regulator-name = "pm6150_l9"; + qcom,set = ; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + qcom,init-voltage = <400000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa10 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L10A: pm6150_l10: regulator-pm6150-l10 { + regulator-name = "pm6150_l10"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1829000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa11 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L11A: pm6150_l11: regulator-pm6150-l11 { + regulator-name = "pm6150_l11"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1890000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa12 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L12A: pm6150_l12: regulator-pm6150-l12 { + regulator-name = "pm6150_l12"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa13 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + proxy-supply = <&pm6150_l13>; + L13A: pm6150_l13: regulator-pm6150-l13 { + regulator-name = "pm6150_l13"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <115000>; + }; + }; + + rpmh-regulator-ldoa14 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa14"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L14A: pm6150_l14: regulator-pm6150-l14 { + regulator-name = "pm6150_l14"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1850000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa15 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa15"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L15A: pm6150_l15: regulator-pm6150-l15 { + regulator-name = "pm6150_l15"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa16 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L16A: pm6150_l16: regulator-pm6150-l16 { + regulator-name = "pm6150_l16"; + qcom,set = ; + regulator-min-microvolt = <2430000>; + regulator-max-microvolt = <2970000>; + qcom,init-voltage = <2430000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa17 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L17A: pm6150_l17: regulator-pm6150-l17 { + regulator-name = "pm6150_l17"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3230000>; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa18 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa18"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L18A: pm6150_l18: regulator-pm6150-l18 { + regulator-name = "pm6150_l18"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3008000>; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa19 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa19"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L19A: pm6150_l19: regulator-pm6150-l19 { + regulator-name = "pm6150_l19"; + qcom,set = ; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3008000>; + qcom,init-voltage = <2700000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc1 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L1C: pm6150l_l1: regulator-pm6150l-l1 { + regulator-name = "pm6150l_l1"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc2 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L2C: pm6150l_l2: regulator-pm6150l-l2 { + regulator-name = "pm6150l_l2"; + qcom,set = ; + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1304000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc3 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + proxy-supply = <&pm6150l_l3>; + L3C: pm6150l_l3: regulator-pm6150l-l3 { + regulator-name = "pm6150l_l3"; + qcom,set = ; + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1260000>; + qcom,init-voltage = <1232000>; + qcom,init-mode = ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <51800>; + }; + }; + + rpmh-regulator-ldoc4 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L4C: pm6150l_l4: regulator-pm6150l-l4 { + regulator-name = "pm6150l_l4"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L5C: pm6150l_l5: regulator-pm6150l-l5 { + regulator-name = "pm6150l_l5"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc6 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L6C: pm6150l_l6: regulator-pm6150l-l6 { + regulator-name = "pm6150l_l6"; + qcom,set = ; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3100000>; + qcom,init-voltage = <1650000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc7 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L7C: pm6150l_l7: regulator-pm6150l-l7 { + regulator-name = "pm6150l_l7"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc8 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc8"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L8C: pm6150l_l8: regulator-pm6150l-l8 { + regulator-name = "pm6150l_l8"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc9 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L9C: pm6150l_l9: regulator-pm6150l-l9 { + regulator-name = "pm6150l_l9"; + qcom,set = ; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <2950000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc10 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L10C: pm6150l_l10: regulator-pm6150l-l10 { + regulator-name = "pm6150l_l10"; + qcom,set = ; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <3200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc11 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L11C: pm6150l_l11: regulator-pm6150l-l11 { + regulator-name = "pm6150l_l11"; + qcom,set = ; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <2950000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-bobc1 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "bobc1"; + qcom,regulator-type = "pmic5-bob"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1000000 2000000>; + qcom,send-defaults; + + BOB: pm6150l_bob: regulator-pm6150l-bob { + regulator-name = "pm6150l_bob"; + qcom,set = ; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + qcom,init-voltage = <3296000>; + qcom,init-mode = ; + }; + + BOB_AO: pm6150l_bob_ao: regulator-pm6150l-bob-ao { + regulator-name = "pm6150l_bob_ao"; + qcom,set = ; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + qcom,init-voltage = <3296000>; + qcom,init-mode = ; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-rumi-overlay.dts b/arch/arm/boot/dts/qcom/sm6150-rumi-overlay.dts new file mode 100644 index 000000000000..cafec923b098 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-rumi-overlay.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "sm6150-rumi.dtsi" + +/ { + model = "RUMI"; + compatible = "qcom,sm6150-rumi", "qcom,sm6150", "qcom,rumi"; + qcom,msm-id = <355 0x0>; + qcom,board-id = <15 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-rumi.dts b/arch/arm/boot/dts/qcom/sm6150-rumi.dts new file mode 100644 index 000000000000..7ba8c195075a --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-rumi.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/memreserve/ 0x90000000 0x00000100; + +#include "sm6150.dtsi" +#include "sm6150-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM6150 PM6150 RUMI"; + compatible = "qcom,sm6150-rumi", "qcom,sm6150", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-rumi.dtsi b/arch/arm/boot/dts/qcom/sm6150-rumi.dtsi new file mode 100644 index 000000000000..34ff3eb557eb --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-rumi.dtsi @@ -0,0 +1,206 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + usb_emu_phy: usb_emu_phy@a720000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x0a720000 0x9500>, + <0x0a6f8800 0x100>; + reg-names = "base", "qcratch_base"; + + qcom,emu-init-seq = <0xfff0 0x4 + 0xfff3 0x4 + 0x40 0x4 + 0xfff3 0x4 + 0xfff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x1a0 0x20 + 0x100000 0x3c + 0x0 0x3c + 0x10060 0x3c + 0x0 0x4>; + }; + + timer { + clock-frequency = <1000000>; + }; + + timer@0x17c00000 { + clock-frequency = <1000000>; + }; + + wdog: qcom,wdt@17c10000{ + status = "disabled"; + }; +}; + +&qupv3_se0_2uart { + status = "ok"; +}; + +&sdhc_1 { + vdd-supply = <&pm6150l_l11>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <200 570000>; + + vdd-io-supply = <&pm6150_l12>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <200 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000>; + qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; + + /delete-property/qcom,devfreq,freq-table; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm6150l_l9>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm6150l_l6>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50"; + + /delete-property/qcom,devfreq,freq-table; + + status = "disabled"; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qrbtc-sdm845"; + + vdda-phy-supply = <&pm6150_l4>; /* 0.88v */ + vdda-pll-supply = <&pm6150_l11>; /* 1.2v */ + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14200>; + + status = "ok"; +}; + +&ufshc_mem { + limit-tx-hs-gear = <1>; + limit-rx-hs-gear = <1>; + scsi-cmd-timeout = <300000>; + + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm6150l_l11>; + vccq2-supply = <&pm6150_l12>; + vcc-max-microamp = <600000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm6150l_l3>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vddp-ref-clk-min-uV = <1232000>; + qcom,vddp-ref-clk-max-uV = <1260000>; + + qcom,disable-lpm; + rpm-level = <0>; + spm-level = <0>; + status = "ok"; +}; + +&spmi_bus { + status = "disabled"; +}; + +&soc { + /delete-node/ rpmh-regulator-mxlvl; + /delete-node/ rpmh-regulator-cxlvl; + /delete-node/ rpmh-regulator-smpc1; + /delete-node/ rpmh-regulator-smpc2; + /delete-node/ rpmh-regulator-modemlvl; + /delete-node/ rpmh-regulator-smpc8; + /delete-node/ rpmh-regulator-ldoa1; + /delete-node/ rpmh-regulator-ldoa2; + /delete-node/ rpmh-regulator-ldoa3; + /delete-node/ rpmh-regulator-ldoa4; + /delete-node/ rpmh-regulator-ldoa5; + /delete-node/ rpmh-regulator-ldoa6; + /delete-node/ rpmh-regulator-lmxlvl; + /delete-node/ rpmh-regulator-lcxlvl; + /delete-node/ rpmh-regulator-ldoa9; + /delete-node/ rpmh-regulator-ldoa10; + /delete-node/ rpmh-regulator-ldoa11; + /delete-node/ rpmh-regulator-ldoa12; + /delete-node/ rpmh-regulator-ldoa13; + /delete-node/ rpmh-regulator-ldoa14; + /delete-node/ rpmh-regulator-ldoa15; + /delete-node/ rpmh-regulator-ldoa16; + /delete-node/ rpmh-regulator-ldoa17; + /delete-node/ rpmh-regulator-ldoa18; + /delete-node/ rpmh-regulator-ldoa19; + /delete-node/ rpmh-regulator-ldoc1; + /delete-node/ rpmh-regulator-ldoc2; + /delete-node/ rpmh-regulator-ldoc3; + /delete-node/ rpmh-regulator-ldoc4; + /delete-node/ rpmh-regulator-ldoc5; + /delete-node/ rpmh-regulator-ldoc6; + /delete-node/ rpmh-regulator-ldoc7; + /delete-node/ rpmh-regulator-ldoc8; + /delete-node/ rpmh-regulator-ldoc9; + /delete-node/ rpmh-regulator-ldoc10; + /delete-node/ rpmh-regulator-ldoc11; + /delete-node/ rpmh-regulator-bobc1; +}; + +&thermal_zones { + /delete-node/ aoss-lowf; + /delete-node/ cpuss-0-lowf; + /delete-node/ cpuss-1-lowf; + /delete-node/ cpuss-2-lowf; + /delete-node/ cpuss-3-lowf; + /delete-node/ cpu-1-0-lowf; + /delete-node/ cpu-1-1-lowf; + /delete-node/ cpu-1-2-lowf; + /delete-node/ cpu-1-3-lowf; + /delete-node/ gpu-lowf; + /delete-node/ q6-hvx-lowf; + /delete-node/ mdm-core-lowf; + /delete-node/ camera-lowf; + /delete-node/ wlan-lowf; + /delete-node/ display-lowf; + /delete-node/ video-lowf; +}; + +&usb0 { + /delete-property/ extcon; + dwc3@a600000 { + usb-phy = <&usb_emu_phy>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; +}; + +&usb_qmp_phy { + status = "disabled"; +}; + +#include "sm6150-stub-regulator.dtsi" diff --git a/arch/arm/boot/dts/qcom/sm6150-sde-display.dtsi b/arch/arm/boot/dts/qcom/sm6150-sde-display.dtsi new file mode 100644 index 000000000000..077a3155addb --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-sde-display.dtsi @@ -0,0 +1,548 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-sim-cmd.dtsi" +#include "dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi" +#include "dsi-panel-td4328-1080p-video.dtsi" +#include "dsi-panel-td4328-1080p-cmd.dtsi" +#include "dsi-panel-rm69298-truly-amoled-fhd-plus-video.dtsi" +#include "dsi-panel-rm69298-truly-amoled-fhd-plus-cmd.dtsi" +#include "dsi-panel-td4330-truly-singlemipi-fhd-cmd.dtsi" +#include "dsi-panel-td4330-truly-singlemipi-fhd-video.dtsi" +#include "dsi-panel-sharp-split-link-wuxga-video.dtsi" +#include "dsi-panel-ext-bridge-hdmi-1080p.dtsi" +#include + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdda-3p3"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <13200>; + qcom,supply-disable-load = <80>; + }; + }; + + dsi_sim_vid_display: qcom,dsi-display@0 { + label = "dsi_sim_vid_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sim_vid>; + }; + + dsi_sim_cmd_display: qcom,dsi-display@1 { + label = "dsi_sim_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sim_cmd>; + }; + + dsi_hx83112a_truly_vid_display: qcom,dsi-display@2 { + label = "dsi_hx83112a_truly_vid_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + + qcom,dsi-panel = <&dsi_hx83112a_truly_video>; + }; + + dsi_td4328_truly_vid_display: qcom,dsi-display@3 { + label = "dsi_td4328_truly_vid_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_td4328_truly_video>; + }; + + dsi_td4328_truly_cmd_display: qcom,dsi-display@4 { + label = "dsi_td4328_truly_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_td4328_truly_cmd>; + }; + + dsi_rm69298_truly_amoled_vid_display: qcom,dsi-display@5 { + label = "dsi_rm69298_truly_amoled_vid_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_rm69298_truly_amoled_video>; + }; + + dsi_rm69298_truly_amoled_cmd_display: qcom,dsi-display@6 { + label = "dsi_rm69298_truly_amoled_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_rm69298_truly_amoled_cmd>; + }; + + dsi_td4330_truly_vid_display: qcom,dsi-display@7 { + label = "dsi_td4330_truly_vid_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_td4330_truly_video>; + }; + + dsi_td4330_truly_cmd_display: qcom,dsi-display@8 { + label = "dsi_td4330_truly_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_td4330_truly_cmd>; + }; + + dsi_sharp_split_link_wuxga_vid_display: qcom,dsi-display@9 { + label = "dsi_sharp_split_link_wuxga_vid_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sharp_split_link_wuxga_video>; + }; + + sde_dsi: qcom,dsi-display { + compatible = "qcom,dsi-display"; + + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + + clocks = <&mdss_dsi0_pll BYTE0_MUX_CLK>, + <&mdss_dsi0_pll PIX0_MUX_CLK>, + <&mdss_dsi0_pll BYTE0_SRC_CLK>, + <&mdss_dsi0_pll PIX0_SRC_CLK>, + <&mdss_dsi0_pll SHADOW_BYTE0_SRC_CLK>, + <&mdss_dsi0_pll SHADOW_PIX0_SRC_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 90 0>; + + vddio-supply = <&pm6150_l13>; + vdda-3p3-supply = <&pm6150_l18>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + + qcom,dsi-display-list = + <&dsi_sim_vid_display + &dsi_sim_cmd_display + &dsi_hx83112a_truly_vid_display + &dsi_td4328_truly_vid_display + &dsi_td4328_truly_cmd_display + &dsi_rm69298_truly_amoled_vid_display + &dsi_rm69298_truly_amoled_cmd_display + &dsi_td4330_truly_vid_display + &dsi_td4330_truly_cmd_display + &dsi_sharp_split_link_wuxga_vid_display>; + }; + + sde_wb: qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display"; + }; + +}; + +&sde_dp { + qcom,dp-usbpd-detection = <&pm6150_pdphy>; + hpd-pwr-supply = <&pm6150_l17>; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <975000>; + qcom,supply-enable-load = <36000>; + qcom,supply-disable-load = <0>; + }; + qcom,phy-supply-entry@1 { + reg = <1>; + qcom,supply-name = "hpd-pwr"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3230000>; + qcom,supply-enable-load = <30000>; + qcom,supply-disable-load = <0>; + }; + }; +}; + +&mdss_mdp { + connectors = <&sde_rscc &sde_wb &sde_dp &sde_dsi>; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-display-timings { + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x31>; + timing@0{ + qcom,mdss-dsi-panel-phy-timings = + [24 1f 08 09 05 02 04 a0 + 24 1f 08 09 05 02 04 a0 + 24 1f 08 09 05 02 04 a0 + 24 1f 08 09 05 02 04 a0 + 24 1c 08 09 05 02 04 a0]; + + qcom,display-topology = <1 0 1>, + <2 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-display-timings { + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x31>; + timing@0{ + qcom,mdss-dsi-panel-phy-timings = + [24 1f 08 09 05 02 04 a0 + 24 1f 08 09 05 02 04 a0 + 24 1f 08 09 05 02 04 a0 + 24 1f 08 09 05 02 04 a0 + 24 1c 08 09 05 02 04 a0]; + + qcom,display-topology = <1 0 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@1{ + qcom,mdss-dsi-panel-phy-timings = + [24 1f 08 09 05 02 04 a0 + 24 1f 08 09 05 02 04 a0 + 24 1f 08 09 05 02 04 a0 + 24 1f 08 09 05 02 04 a0 + 24 1c 08 09 05 02 04 a0]; + qcom,display-topology = <1 0 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <540 40 540 40 540 40>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@2{ + qcom,mdss-dsi-panel-phy-timings = + [24 1f 08 09 05 02 04 a0 + 24 1f 08 09 05 02 04 a0 + 24 1f 08 09 05 02 04 a0 + 24 1f 08 09 05 02 04 a0 + 24 1c 08 09 05 02 04 a0]; + qcom,display-topology = <1 0 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <360 40 360 40 360 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; + +&dsi_hx83112a_truly_video { + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x31>; + qcom,dsi-supported-dfps-list = <60 55 53 43>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = + "dfps_immediate_porch_mode_vfp"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>; + qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>; + qcom,mdss-dsi-panel-status-read-length = <4>; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = + <924736320 909324048 913177120 917030184 920883256 928589392>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = + [24 1f 08 09 05 02 04 a0 + 24 1f 08 09 05 02 04 a0 + 24 1f 08 09 05 02 04 a0 + 24 1f 08 09 05 02 04 a0 + 24 1c 08 09 05 02 04 a0]; + + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_td4328_truly_video { + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x32>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-on-check-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = + [24 20 08 09 05 02 04 a0 + 24 20 08 09 05 02 04 a0 + 24 20 08 09 05 02 04 a0 + 24 20 08 09 05 02 04 a0 + 24 1d 08 09 05 02 04 a0]; + + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_td4328_truly_cmd { + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x32>; + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-on-check-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = + [24 20 08 09 05 02 04 a0 + 24 20 08 09 05 02 04 a0 + 24 20 08 09 05 02 04 a0 + 24 20 08 09 05 02 04 a0 + 24 1d 08 09 05 02 04 a0]; + + qcom,mdss-mdp-transfer-time-us = <14500>; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <16 16 8 2 16 16>; + }; + }; +}; + +&dsi_rm69298_truly_amoled_video { + qcom,mdss-dsi-t-clk-post = <0x0D>; + qcom,mdss-dsi-t-clk-pre = <0x2D>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = + [23 1E 07 08 05 02 04 a0 + 23 1E 07 08 05 02 04 a0 + 23 1E 07 08 05 02 04 a0 + 23 1E 07 08 05 02 04 a0 + 23 19 07 08 05 02 04 a0]; + + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_rm69298_truly_amoled_cmd { + qcom,mdss-dsi-t-clk-post = <0x0D>; + qcom,mdss-dsi-t-clk-pre = <0x2D>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = + [23 1E 07 08 05 02 04 a0 + 23 1E 07 08 05 02 04 a0 + 23 1E 07 08 05 02 04 a0 + 23 1E 07 08 05 02 04 a0 + 23 19 07 08 05 02 04 a0]; + + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_td4330_truly_cmd { + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x36>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = + [26 20 09 0B 06 02 04 a0 + 26 20 09 0B 06 02 04 a0 + 26 20 09 0B 06 02 04 a0 + 26 20 09 0B 06 02 04 a0 + 26 1F 09 0B 06 02 04 a0]; + + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_td4330_truly_video { + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x36>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = + [26 20 09 0B 06 02 04 a0 + 26 20 09 0B 06 02 04 a0 + 26 20 09 0B 06 02 04 a0 + 26 20 09 0B 06 02 04 a0 + 26 1F 09 0B 06 02 04 a0]; + + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_split_link_wuxga_video { + qcom,mdss-dsi-t-clk-post = <0x0E>; + qcom,mdss-dsi-t-clk-pre = <0x35>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = + [25 1f 09 0a 06 03 04 a0 + 25 1f 09 0a 06 03 04 a0 + 25 1f 09 0a 06 03 04 a0 + 25 1f 09 0a 06 03 04 a0 + 25 1f 08 0a 06 03 04 a0]; + + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_ext_bridge_hdmi_1080p { + qcom,mdss-dsi-t-clk-post = <0x0D>; + qcom,mdss-dsi-t-clk-pre = <0x30>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = + [24 1f 08 09 05 03 04 a0 + 24 1f 08 09 05 03 04 a0 + 24 1f 08 09 05 03 04 a0 + 24 1f 08 09 05 03 04 a0 + 24 1b 08 09 05 03 04 a0]; + + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-sde-pll.dtsi b/arch/arm/boot/dts/qcom/sm6150-sde-pll.dtsi new file mode 100644 index 000000000000..87b524fefc91 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-sde-pll.dtsi @@ -0,0 +1,83 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + mdss_dsi0_pll: qcom,mdss_dsi_pll@ae94400 { + compatible = "qcom,mdss_dsi_pll_14nm"; + label = "MDSS DSI 0 PLL"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae94400 0x588>, + <0xaf03000 0x8>, + <0xae94200 0x100>; + reg-names = "pll_base", "gdsc_base", + "dynamic_pll_base"; + clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + clock-rate = <0>; + memory-region = <&dfps_data_memory>; + gdsc-supply = <&mdss_core_gdsc>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dp_pll: qcom,mdss_dp_pll@88e9000 { + compatible = "qcom,mdss_dp_pll_14nm"; + label = "MDSS DP PLL"; + cell-index = <0>; + #clock-cells = <1>; + + reg = <0x088e9c00 0x200>, + <0x088e9000 0x200>, + <0x088e9400 0x200>, + <0x088e9800 0x200>, + <0xaf03000 0x8>; + reg-names = "pll_base", "phy_base", "ln_tx0_base", + "ln_tx1_base", "gdsc_base"; + + clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_AHB2PHY_WEST_CLK>, + <&clock_gcc GCC_DISP_AHB_CLK>, + <&clock_gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names = "iface_clk", "ref_clk_src", "cfg_ahb_clk", + "gcc_iface", "ref_clk"; + clock-rate = <0>; + + gdsc-supply = <&mdss_core_gdsc>; + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll-sde.dtsi b/arch/arm/boot/dts/qcom/sm6150-sde.dtsi similarity index 61% rename from arch/arm64/boot/dts/qcom/atoll-sde.dtsi rename to arch/arm/boot/dts/qcom/sm6150-sde.dtsi index 8a01f196c5e7..6e8bb0925c29 100644 --- a/arch/arm64/boot/dts/qcom/atoll-sde.dtsi +++ b/arch/arm/boot/dts/qcom/sm6150-sde.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -10,19 +10,17 @@ * GNU General Public License for more details. */ -#include +#include &soc { mdss_mdp: qcom,mdss_mdp@ae00000 { compatible = "qcom,sde-kms"; - reg = <0xae00000 0x84208>, - <0xaeb0000 0x2008>, - <0xaeac000 0x214>, - <0xae8f000 0x02c>; + reg = <0x0ae00000 0x84208>, + <0x0aeb0000 0x2008>, + <0x0aeac000 0x214>; reg-names = "mdp_phys", "vbif_phys", - "regdma_phys", - "sid_phys"; + "regdma_phys"; clocks = <&clock_gcc GCC_DISP_AHB_CLK>, @@ -32,21 +30,18 @@ <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>, <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>, <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; - clock-names = "gcc_iface", "gcc_bus", "iface_clk", - "core_clk", "vsync_clk", + clock-names = "gcc_iface", "gcc_bus", + "iface_clk", "core_clk", "vsync_clk", "lut_clk", "rot_clk"; - clock-rate = <0 0 0 300000000 19200000 200000000 - 200000000>; - clock-max-rate = <0 0 0 460000000 19200000 460000000 - 460000000>; - - sde-vdd-supply = <&mdss_core_gdsc>; + clock-rate = <0 0 0 256000000 19200000 192000000>; + clock-max-rate = <0 0 0 307000000 19200000 307000000>; + qcom,dss-cx-ipeak = <&cx_ipeak_lm 3>; /* interrupt config */ - interrupts = ; + interrupts = <0 83 0>; interrupt-controller; #interrupt-cells = <1>; - iommus = <&apps_smmu 0x800 0x2>; + iommus = <&apps_smmu 0x800 0x0>; #address-cells = <1>; #size-cells = <0>; @@ -55,104 +50,106 @@ /* hw blocks */ qcom,sde-off = <0x1000>; - qcom,sde-len = <0x494>; + qcom,sde-len = <0x45c>; - qcom,sde-ctl-off = <0x2000 0x2200 0x2400>; - qcom,sde-ctl-size = <0x1dc>; - qcom,sde-ctl-display-pref = "primary", "none", "none"; + qcom,sde-ctl-off = <0x2000 0x2200 0x2400 + 0x2600 0x2800 0x2a00>; + qcom,sde-ctl-size = <0x1e0>; + qcom,sde-ctl-display-pref = "primary", "none", "none", + "none", "none"; - qcom,sde-mixer-off = <0x45000 0x46000>; + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 + 0x0 0x0 0x0>; qcom,sde-mixer-size = <0x320>; - qcom,sde-mixer-display-pref = "primary", "none"; + qcom,sde-mixer-display-pref = "primary", "none", "none", + "none", "none", "none"; - qcom,sde-mixer-cwb-pref = "none", "cwb"; + qcom,sde-mixer-cwb-pref = "none", "none", "cwb", + "none", "none", "none"; qcom,sde-dspp-top-off = <0x1300>; qcom,sde-dspp-top-size = <0x80>; qcom,sde-dspp-off = <0x55000>; qcom,sde-dspp-size = <0x1800>; + qcom,sde-wb-off = <0x66000>; qcom,sde-wb-size = <0x2c8>; qcom,sde-wb-xin-id = <6>; qcom,sde-wb-id = <2>; qcom,sde-wb-clk-ctrl = <0x3b8 24>; - qcom,sde-intf-off = <0x6b000 0x6b800>; + qcom,sde-intf-off = <0x6b000 0x6b800 0x6c000 + 0x6c800>; + qcom,sde-intf-size = <0x2b8>; - qcom,sde-intf-type = "dp", "dsi"; + qcom,sde-intf-type = "dp", "dsi","none", "dp"; - qcom,sde-pp-off = <0x71000 0x71800>; - qcom,sde-pp-slave = <0x0 0x0>; + qcom,sde-pp-off = <0x71000 0x71800 + 0x72000>; + qcom,sde-pp-slave = <0x0 0x0 0x0>; qcom,sde-pp-size = <0xd4>; - qcom,sde-pp-merge-3d-id = <0x0 0x0>; - qcom,sde-merge-3d-off = <0x84000>; - qcom,sde-merge-3d-size = <0x100>; - qcom,sde-te2-off = <0x2000 0x2000>; + qcom,sde-te2-off = <0x2000 0x2000 0x0>; qcom,sde-cdm-off = <0x7a200>; qcom,sde-cdm-size = <0x224>; - qcom,sde-dither-off = <0x30e0 0x30e0>; + + qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 0x30e0>; qcom,sde-dither-version = <0x00010000>; qcom,sde-dither-size = <0x20>; - qcom,sde-sspp-type = "vig", "dma", "dma", "dma"; + qcom,sde-sspp-type = "vig", "dma", "dma", "dma", "dma"; - qcom,sde-sspp-off = <0x5000 0x25000 0x27000 0x29000>; - qcom,sde-sspp-src-size = <0x1f8>; + qcom,sde-sspp-off = <0x5000 0x25000 0x27000 0x29000 + 0x2b000>; + qcom,sde-sspp-src-size = <0x1f0>; - qcom,sde-sspp-xin-id = <0 1 5 9 >; - qcom,sde-sspp-excl-rect = <1 1 1 1>; - qcom,sde-sspp-smart-dma-priority = <4 1 2 3>; + qcom,sde-sspp-xin-id = <0 1 5 9 13>; + qcom,sde-sspp-excl-rect = <1 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <5 1 2 3 4>; qcom,sde-smart-dma-rev = "smart_dma_v2p5"; - qcom,sde-mixer-pair-mask = <2 1>; + qcom,sde-mixer-pair-mask = <3 0 1 0 0 0>; qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 0xb0 0xc8 0xe0 0xf8 0x110>; - qcom,sde-max-per-pipe-bw-kbps = <2600000 2600000 - 2600000 2600000>; - - qcom,sde-max-per-pipe-bw-high-kbps = <2600000 2600000 - 2600000 2600000>; + qcom,sde-max-per-pipe-bw-kbps = <4500000 + 4500000 4500000 + 4500000 4500000>; /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-sspp-clk-ctrl = - <0x2ac 0>, <0x2b4 8>, - <0x2ac 8>, <0x2c4 8>; + <0x2ac 0>, <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, + <0x2c4 8>; qcom,sde-sspp-csc-off = <0x1a00>; qcom,sde-csc-type = "csc-10bit"; qcom,sde-qseed-type = "qseedv3lite"; qcom,sde-sspp-qseed-off = <0xa00>; qcom,sde-mixer-linewidth = <2560>; qcom,sde-sspp-linewidth = <2160>; - qcom,sde-vig-sspp-linewidth = <4096>; - qcom,sde-wb-linewidth = <1080>; - qcom,sde-mixer-blendstages = <0x7>; + qcom,sde-wb-linewidth = <2160>; + qcom,sde-mixer-blendstages = <0x9>; qcom,sde-highest-bank-bit = <0x1>; qcom,sde-ubwc-version = <0x200>; - qcom,sde-ubwc-bw-calc-version = <0x1>; - qcom,sde-ubwc-static = <0x18>; qcom,sde-panic-per-pipe; - qcom,sde-smart-panel-align-mode = <0xc>; qcom,sde-has-cdp; - qcom,sde-has-src-split; - qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; qcom,sde-has-idle-pc; - qcom,sde-max-bw-low-kbps = <3900000>; - qcom,sde-max-bw-high-kbps = <5500000>; + qcom,sde-max-bw-low-kbps = <4800000>; + qcom,sde-max-bw-high-kbps = <4800000>; qcom,sde-min-core-ib-kbps = <2400000>; qcom,sde-min-llcc-ib-kbps = <800000>; qcom,sde-min-dram-ib-kbps = <800000>; qcom,sde-dram-channels = <2>; qcom,sde-num-nrt-paths = <0>; + qcom,sde-vbif-off = <0>; qcom,sde-vbif-size = <0x1040>; qcom,sde-vbif-id = <0>; @@ -161,25 +158,23 @@ qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>; - qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>; /* macrotile & macrotile-qseed has the same configs */ - qcom,sde-danger-lut = <0x000000ff 0x0000ffff + qcom,sde-danger-lut = <0x0000000f 0x0000ffff 0x00000000 0x00000000 0x0000ffff>; - qcom,sde-safe-lut-linear = <0 0xfff0>; - qcom,sde-safe-lut-macrotile = <0 0xff00>; + qcom,sde-safe-lut-linear = <0 0xfff8>; + qcom,sde-safe-lut-macrotile = <0 0xf000>; /* same as safe-lut-macrotile */ - qcom,sde-safe-lut-macrotile-qseed = <0 0xff00>; + qcom,sde-safe-lut-macrotile-qseed = <0 0xf000>; qcom,sde-safe-lut-nrt = <0 0xffff>; - qcom,sde-safe-lut-cwb = <0 0x3ff>; + qcom,sde-safe-lut-cwb = <0 0xffff>; - qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>; + qcom,sde-qos-lut-linear = <0 0x00112222 0x22223357>; qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>; qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>; qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>; - qcom,sde-qos-lut-cwb = <0 0x66666541 0x00000000>; + qcom,sde-qos-lut-cwb = <0 0x75300000 0x00000000>; qcom,sde-cdp-setting = <1 1>, <1 0>; @@ -189,37 +184,18 @@ /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-reg-dma-off = <0>; - qcom,sde-reg-dma-version = <0x00010002>; + qcom,sde-reg-dma-version = <0x00010001>; qcom,sde-reg-dma-trigger-off = <0x119c>; - qcom,sde-reg-dma-xin-id = <7>; - qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; - qcom,sde-secure-sid-mask = <0x801>; + qcom,sde-secure-sid-mask = <0x0000801>; qcom,sde-sspp-vig-blocks { qcom,sde-vig-csc-off = <0x1a00>; qcom,sde-vig-qseed-off = <0xa00>; qcom,sde-vig-qseed-size = <0xa0>; - qcom,sde-vig-gamut = <0x1d00 0x00060000>; - qcom,sde-vig-igc = <0x1d00 0x00060000>; qcom,sde-vig-inverse-pma; }; - qcom,sde-sspp-dma-blocks { - dgm@0 { - qcom,sde-dma-igc = <0x400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x200>; - }; - - dgm@1 { - qcom,sde-dma-igc = <0x1400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x1200>; - }; - }; qcom,sde-dspp-blocks { qcom,sde-dspp-igc = <0x0 0x00030001>; @@ -228,26 +204,12 @@ qcom,sde-dspp-hist = <0x800 0x00010007>; qcom,sde-dspp-sixzone= <0x900 0x00010007>; qcom,sde-dspp-vlut = <0xa00 0x00010008>; - qcom,sde-dspp-gamut = <0x1000 0x00040002>; + qcom,sde-dspp-gamut = <0x1000 0x00040001>; qcom,sde-dspp-pcc = <0x1700 0x00040000>; qcom,sde-dspp-gc = <0x17c0 0x00010008>; qcom,sde-dspp-dither = <0x82c 0x00010007>; }; - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "sde-vdd"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - smmu_sde_sec: qcom,smmu_sde_sec_cb { compatible = "qcom,smmu_sde_sec"; iommus = <&apps_smmu 0x801 0x0>; @@ -260,8 +222,8 @@ qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <22 512 0 0>, - <22 512 0 6400000>, - <22 512 0 6400000>; + <22 512 0 4800000>, + <22 512 0 4800000>; }; qcom,sde-reg-bus { @@ -279,22 +241,22 @@ sde_rscc: qcom,sde_rscc@af20000 { cell-index = <0>; compatible = "qcom,sde-rsc"; - reg = <0xaf20000 0x3c50>, + reg = <0xaf20000 0x1c44>, <0xaf30000 0x3fd4>; reg-names = "drv", "wrapper"; - qcom,sde-rsc-version = <3>; - status = "disabled"; - - qcom,sde-dram-channels = <2>; - - mboxes = <&disp_rsc 0>; - mbox-names = "disp_rsc"; + qcom,sde-rsc-version = <2>; vdd-supply = <&mdss_core_gdsc>; clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, <&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>, <&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; + clock-rate = <0 0 0>; + + qcom,sde-dram-channels = <2>; + + mboxes = <&disp_rsc 0>; + mbox-names = "disp_rsc"; /* data and reg bus scale settings */ qcom,sde-data-bus { @@ -304,8 +266,8 @@ qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <20003 20515 0 0>, - <20003 20515 0 6400000>, - <20003 20515 0 6400000>; + <20003 20515 0 4800000>, + <20003 20515 0 4800000>; }; qcom,sde-llcc-bus { @@ -331,10 +293,10 @@ }; }; - mdss_rotator: qcom,mdss_rotator@aea8800 { + mdss_rotator: qcom,mdss_rotator@ae00000 { compatible = "qcom,sde_rotator"; - reg = <0xae00000 0xac000>, - <0xaeb8000 0x3000>; + reg = <0x0ae00000 0xac000>, + <0x0aeb8000 0x3000>; reg-names = "mdp_phys", "rot_vbif_phys"; @@ -359,7 +321,8 @@ <&clock_gcc GCC_DISP_AHB_CLK>, <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; - clock-names = "gcc_iface", "iface_clk", "rot_clk"; + clock-names = "gcc_iface", + "iface_clk", "rot_clk"; interrupt-parent = <&mdss_mdp>; interrupts = <2 0>; @@ -374,11 +337,17 @@ qcom,mdss-rot-danger-lut = <0x0 0x0>; qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>; + qcom,mdss-rot-qos-cpu-mask = <0xf>; + qcom,mdss-rot-qos-cpu-dma-latency = <75>; + qcom,mdss-default-ot-rd-limit = <32>; qcom,mdss-default-ot-wr-limit = <32>; qcom,mdss-sbuf-headroom = <20>; + cache-slice-names = "rotator"; + cache-slices = <&llcc 4>; + /* reg bus scale settings */ rot_reg: qcom,rot-reg-bus { qcom,msm-bus,name = "mdss_rot_reg"; @@ -391,26 +360,25 @@ smmu_rot_unsec: qcom,smmu_rot_unsec_cb { compatible = "qcom,smmu_sde_rot_unsec"; - iommus = <&apps_smmu 0xC1C 0x0>; + iommus = <&apps_smmu 0xc40 0x0>; }; smmu_rot_sec: qcom,smmu_rot_sec_cb { compatible = "qcom,smmu_sde_rot_sec"; - iommus = <&apps_smmu 0xC1D 0x0>; + iommus = <&apps_smmu 0xc41 0x0>; }; }; mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { - compatible = "qcom,dsi-ctrl-hw-v2.4"; + compatible = "qcom,dsi-ctrl-hw-v2.3"; label = "dsi-ctrl-0"; cell-index = <0>; - reg = <0xae94000 0x400>, + reg = <0xae94000 0x400>, <0xaf08000 0x4>; reg-names = "dsi_ctrl", "disp_cc_base"; interrupt-parent = <&mdss_mdp>; interrupts = <4 0>; - vdda-1p2-supply = <&L3C>; - refgen-supply = <&refgen>; + vdda-1p2-supply = <&pm6150l_l3>; clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>, <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, @@ -418,8 +386,9 @@ <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", - "esc_clk"; + "pixel_clk", "pixel_clk_rcg", + "esc_clk"; + qcom,split-link-supported; qcom,ctrl-supply-entries { #address-cells = <1>; @@ -428,13 +397,12 @@ qcom,ctrl-supply-entry@0 { reg = <0>; qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; + qcom,supply-min-voltage = <1232000>; + qcom,supply-max-voltage = <1232000>; qcom,supply-enable-load = <21800>; qcom,supply-disable-load = <0>; }; }; - qcom,core-supply-entries { #address-cells = <1>; #size-cells = <0>; @@ -451,83 +419,134 @@ }; mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 { - compatible = "qcom,dsi-phy-v3.0"; + compatible = "qcom,dsi-phy-v2.0"; label = "dsi-phy-0"; cell-index = <0>; - reg = <0xae94400 0x7c0>, + reg = <0xae94400 0x588>, + <0xae01400 0x100>, <0xae94200 0x100>; - reg-names = "dsi_phy", "dyn_refresh_base"; - vdda-0p9-supply = <&S3A_LEVEL>; - qcom,platform-strength-ctrl = [55 03 - 55 03 - 55 03 - 55 03 - 55 00]; - qcom,platform-lane-config = [00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 80]; + reg-names = "dsi_phy", "phy_clamp_base", + "dyn_refresh_base"; + vdda-0p9-supply = <&pm6150_l4>; + qcom,platform-strength-ctrl = [ff 06 + ff 06 + ff 06 + ff 06 + ff 00]; + qcom,platform-lane-config = [00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 8f]; qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; - qcom,panel-allow-phy-poweroff; qcom,phy-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,phy-supply-entry@0 { reg = <0>; qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = - ; - qcom,supply-max-voltage = - ; - qcom,supply-off-min-voltage = - ; - qcom,supply-enable-load = <0>; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <975000>; + qcom,supply-enable-load = <36000>; qcom,supply-disable-load = <0>; }; }; }; - sde_dp: qcom,dp_display@ae90000 { - status = "disabled"; + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + sde_dp: qcom,dp_display@0{ cell-index = <0>; compatible = "qcom,dp-display"; - vdda-lp2-supply = <&L9A>; - reg = <0xae90000 0x0dc>, + vdda-1p2-supply = <&pm6150l_l3>; + vdda-0p9-supply = <&pm6150_l4>; + reg = <0xae90000 0x0f4>, <0xae90200 0x0c0>, - <0xae90400 0x508>, - <0xae91000 0x094>, - <0x88eaa00 0x198>, - <0x88ea200 0x150>, - <0x88ea600 0x150>, - <0xaf02000 0x2c4>, - <0x780000 0x6228>, - <0x88ea040 0x10>, - <0x88e8000 0x20>, - <0x0aee1000 0x2a>, - <0xae91400 0x095>; - reg-names = "dp_ahb", "dp_aux", "dp_link", - "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", - "dp_mmss_cc", "qfprom_physical", "dp_pll", - "usb3_dp_com", "hdcp_physical", "dp_p1"; + <0xae90400 0x5e0>, + <0xae90a00 0x098>, + <0x88e9000 0x17c>, + <0x88e9400 0x10c>, + <0x88e9800 0x10c>, + <0xaf02130 0x8>, + <0x780000 0x621c>, + <0x88e9c30 0x10>, + <0xaee1000 0x34>, + <0x1fcb24c 0x4>, + <0xae91000 0x098>; + + /* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */ + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_pixel_mn", "qfprom_physical", "dp_pll", + "hdcp_physical", "dp_tcsr","dp_p1"; interrupt-parent = <&mdss_mdp>; interrupts = <12 0>; - qcom,phy-version = <0x420>; + clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_AHB2PHY_WEST_CLK>, + <&clock_gcc GCC_USB3_SEC_CLKREF_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&mdss_dp_pll DP_PHY_PLL_VCO_DIV_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, + <&mdss_dp_pll DP_PHY_PLL_VCO_DIV_CLK>; + + clock-names = "core_aux_clk", "core_usb_ref_clk_src", + "core_usb_ahb_clk", "core_usb_sec_ref_clk", + "link_clk", "link_iface_clk", + "strm0_pixel_clk","strm1_pixel_clk", "crypto_clk", + "pixel_clk_rcg", "pixel_parent","pixel1_clk_rcg", + "pixel1_parent"; + + + qcom,phy-version = <0x200>; qcom,aux-cfg0-settings = [20 00]; - qcom,aux-cfg1-settings = [24 13]; - qcom,aux-cfg2-settings = [28 A4]; + qcom,aux-cfg1-settings = [24 13 23 1d]; + qcom,aux-cfg2-settings = [28 00]; qcom,aux-cfg3-settings = [2c 00]; qcom,aux-cfg4-settings = [30 0a]; qcom,aux-cfg5-settings = [34 26]; qcom,aux-cfg6-settings = [38 0a]; qcom,aux-cfg7-settings = [3c 03]; - qcom,aux-cfg8-settings = [40 b7]; + qcom,aux-cfg8-settings = [40 bb]; qcom,aux-cfg9-settings = [44 03]; - qcom,max-pclk-frequency-khz = <675000>; + qcom,logical2physical-lane-map = [03 02 00 01]; + + qcom,max-lclk-frequency-khz = <540000>; + qcom,max-pclk-frequency-khz = <195000>; + + qcom,max-hdisplay = <1920>; + qcom,max-vdisplay = <1200>; + + qcom,ext-disp = <&ext_disp>; + qcom,dp-aux-switch = <&fsa4480>; + + qcom,mux-sel-gpio = <&tlmm 49 0>; + qcom,usbplug-cc-gpio = <&tlmm 104 0>; + + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep", + "mdss_dp_hpd_active", "mdss_dp_hpd_tlmm", + "mdss_dp_hpd_ctrl"; + pinctrl-0 = <&sde_dp_usbplug_cc_active &sde_dp_switch_active>; + pinctrl-1 = <&sde_dp_usbplug_cc_suspend &sde_dp_switch_suspend>; + pinctrl-2 = <&sde_dp_connector_enable &sde_dp_switch_suspend + &sde_dp_hotplug_tlmm>; + pinctrl-3 = <&sde_dp_hotplug_tlmm>; + pinctrl-4 = <&sde_dp_hotplug_ctrl>; qcom,ctrl-supply-entries { #address-cells = <1>; @@ -536,27 +555,13 @@ qcom,ctrl-supply-entry@0 { reg = <0>; qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; + qcom,supply-min-voltage = <1232000>; + qcom,supply-max-voltage = <1232000>; qcom,supply-enable-load = <21800>; qcom,supply-disable-load = <0>; }; }; - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <880000>; - qcom,supply-enable-load = <36000>; - qcom,supply-disable-load = <0>; - }; - }; - qcom,core-supply-entries { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/qcom/sm6150-slpi-pinctrl.dtsi b/arch/arm/boot/dts/qcom/sm6150-slpi-pinctrl.dtsi new file mode 100644 index 000000000000..a5bac24136b7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-slpi-pinctrl.dtsi @@ -0,0 +1,461 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + slpi_tlmm: slpi_pinctrl@62B40000 { + compatible = "qcom,slpi-pinctrl"; + reg = <0x62B40000 0x20000>; + qcom,num-pins = <32>; + status = "disabled"; + + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_active: qupv3_se8_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "func1"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { + qupv3_se9_i2c_active: qupv3_se9_i2c_active { + mux { + pins = "gpio2", "gpio3"; + function = "func1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { + mux { + pins = "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { + qupv3_se10_i2c_active: qupv3_se10_i2c_active { + mux { + pins = "gpio8", "gpio9"; + function = "func1"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se11_i2c_pins: qupv3_se11_i2c_pins { + qupv3_se11_i2c_active: qupv3_se11_i2c_active { + mux { + pins = "gpio16", "gpio17"; + function = "func3"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep { + mux { + pins = "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se12_i2c_pins: qupv3_se12_i2c_pins { + qupv3_se12_i2c_active: qupv3_se12_i2c_active { + mux { + pins = "gpio16", "gpio17"; + function = "func2"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep { + mux { + pins = "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se13_i2c_pins: qupv3_se13_i2c_pins { + qupv3_se13_i2c_active: qupv3_se13_i2c_active { + mux { + pins = "gpio14", "gpio15"; + function = "func2"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep { + mux { + pins = "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se9_spi_pins: qupv3_se9_spi_pins { + qupv3_se9_spi_active: qupv3_se9_spi_active { + mux { + pins = "gpio2", "gpio3", "gpio4", + "gpio5"; + function = "func1"; + }; + + config { + pins = "gpio2", "gpio3", "gpio4", + "gpio5"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { + mux { + pins = "gpio2", "gpio3", "gpio4", + "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio2", "gpio3", "gpio4", + "gpio5"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se10_spi_pins: qupv3_se10_spi_pins { + qupv3_se10_spi_active: qupv3_se10_spi_active { + mux { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + function = "func1"; + }; + + config { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { + mux { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", "gpio10", + "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + quat_tdm_sclk_active: quat_tdm_sclk_active { + mux { + pins = "gpio23"; + function = "func3"; + }; + + config { + pins = "gpio23"; + drive-strength = <8>; + bias-disable; + }; + }; + + quat_tdm_sclk_sleep: quat_tdm_sclk_sleep { + mux { + pins = "gpio23"; + function = "func3"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + + quat_tdm_ws_active: quat_tdm_ws_active { + mux { + pins = "gpio24"; + function = "func1"; + }; + + config { + pins = "gpio24"; + drive-strength = <8>; + bias-disable; + }; + }; + + quat_tdm_ws_sleep: quat_tdm_ws_sleep { + mux { + pins = "gpio24"; + function = "func1"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; + bias-disable; + }; + }; + + quat_tdm_data1_active: quat_tdm_data1_active { + mux { + pins = "gpio26"; + function = "func2"; + }; + + config { + pins = "gpio26"; + drive-strength = <8>; + bias-disable; + }; + }; + + quat_tdm_data1_sleep: quat_tdm_data1_sleep { + mux { + pins = "gpio26"; + function = "func2"; + }; + + config { + pins = "gpio26"; + drive-strength = <2>; + bias-disable; + }; + }; + + quat_tdm_data0_active: quat_tdm_data0_active { + mux { + pins = "gpio25"; + function = "func1"; + }; + + config { + pins = "gpio25"; + drive-strength = <2>; + bias-disable; + }; + }; + + quat_tdm_data0_sleep: quat_tdm_data0_sleep { + mux { + pins = "gpio25"; + function = "func1"; + }; + + config { + pins = "gpio25"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + quin_tdm_sclk_active: quin_tdm_sclk_active { + mux { + pins = "gpio18"; + function = "func3"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; + bias-disable; + }; + }; + + quin_tdm_sclk_sleep: quin_tdm_sclk_sleep { + mux { + pins = "gpio18"; + function = "func3"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + quin_tdm_data0_active: quin_tdm_data0_active { + mux { + pins = "gpio20"; + function = "func3"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; + bias-disable; + }; + }; + + quin_tdm_data0_sleep: quin_tdm_data0_sleep { + mux { + pins = "gpio20"; + function = "func3"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + quin_tdm_ws_active: quin_tdm_ws_active { + mux { + pins = "gpio21"; + function = "func3"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; + bias-disable; + }; + }; + + quin_tdm_ws_sleep: quin_tdm_ws_sleep { + mux { + pins = "gpio21"; + function = "func3"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + quin_tdm_data1_active: quin_tdm_data1_active { + mux { + pins = "gpio22"; + function = "func3"; + }; + + config { + pins = "gpio22"; + drive-strength = <8>; + bias-disable; + }; + }; + + quin_tdm_data1_sleep: quin_tdm_data1_sleep { + mux { + pins = "gpio22"; + function = "func3"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>; + bias-disable; + }; + }; + + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-stub-regulator.dtsi b/arch/arm/boot/dts/qcom/sm6150-stub-regulator.dtsi new file mode 100644 index 000000000000..02213050f589 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-stub-regulator.dtsi @@ -0,0 +1,345 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +/* Stub regulators */ + +/ { + /* pm6150 S1 - VDD_CX supply */ + VDD_CX_LEVEL: + pm6150_s1_level: regulator-pm6150-s1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_s1_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + VDD_CX_LEVEL_AO: + pm6150_s1_level_ao: regulator-pm6150-s1-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_s1_level_ao"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + /* pm6150 S3 - VDD_MX supply */ + VDD_MX_LEVEL: + S3A_LEVEL: pm6150_s3_level: regulator-pm6150-s3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_s3_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + VDD_MX_LEVEL_AO: + S3A_LEVEL_AO: pm6150_s3_level_ao: regulator-pm6150-s3-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_s3_level_ao"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + S1C: pm6150l_s1: regulator-pm6150l-s1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_s1"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + }; + + S2C: pm6150l_s2: regulator-pm6150l-s2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_s2"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <348000>; + regulator-max-microvolt = <1200000>; + }; + + /* pm6150l S7 - VDD_MSS supply */ + VDD_MSS_LEVEL: + S7C_LEVEL: pm6150l_s7_level: regulator-pm6150l-s7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_s7_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + S8C: pm6150l_s8: regulator-pm6150l-s8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_s8"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + }; + + L1A: pm6150_l1: regulator-pm6150-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1252000>; + }; + + L2A: pm6150_l2: regulator-pm6150-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1050000>; + }; + + L3A: pm6150_l3: regulator-pm6150-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1060000>; + }; + + L4A: pm6150_l4: regulator-pm6150-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + }; + + L5A: pm6150_l5: regulator-pm6150-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2970000>; + }; + + L6A: pm6150_l6: regulator-pm6150-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <650000>; + }; + + /* pm6150 L7 - LPI_MX supply */ + L7A_LEVEL: pm6150_l7_level: regulator-pm6150-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l7_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + /* pm6150 L8 - LPI_CX supply */ + L8A_LEVEL: pm6150_l8_level: regulator-pm6150-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l8_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + L9A: pm6150_l9: regulator-pm6150-l9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + }; + + L10A: pm6150_l10: regulator-pm6150-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l10"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1829000>; + }; + + L11A: pm6150_l11: regulator-pm6150-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l11"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1890000>; + }; + + L12A: pm6150_l12: regulator-pm6150-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l12"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1950000>; + }; + + L13A: pm6150_l13: regulator-pm6150-l13 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l13"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + L14A: pm6150_l14: regulator-pm6150-l14 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l14"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1850000>; + }; + + L15A: pm6150_l15: regulator-pm6150-l15 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l15"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + L16A: pm6150_l16: regulator-pm6150-l16 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l16"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2430000>; + regulator-max-microvolt = <2970000>; + }; + + L17A: pm6150_l17: regulator-pm6150-l17 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l17"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3230000>; + }; + + L18A: pm6150_l18: regulator-pm6150-l18 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l18"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3008000>; + }; + + L19A: pm6150_l19: regulator-pm6150-l19 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l19"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3008000>; + }; + + L1C: pm6150l_l1: regulator-pm6150l-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + L2C: pm6150l_l2: regulator-pm6150l-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1304000>; + }; + + L3C: pm6150l_l3: regulator-pm6150l-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1260000>; + }; + + L4C: pm6150l_l4: regulator-pm6150l-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + }; + + L5C: pm6150l_l5: regulator-pm6150l-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + }; + + L6C: pm6150l_l6: regulator-pm6150l-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l6"; + qcom,hpm-min-load = <5000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3100000>; + }; + + L7C: pm6150l_l7: regulator-pm6150l-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + }; + + L8C: pm6150l_l8: regulator-pm6150l-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + L9C: pm6150l_l9: regulator-pm6150l-l9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + }; + + L10C: pm6150l_l10: regulator-pm6150l-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l10"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3312000>; + }; + + L11C: pm6150l_l11: regulator-pm6150l-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_l11"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + }; + + BOB: pm6150l_bob: regulator-pm6150l-bob { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_bob"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + }; + + BOB_AO: pm6150l_bob_ao: regulator-pm6150l-bob-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150l_bob_ao"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-thermal-overlay.dtsi b/arch/arm/boot/dts/qcom/sm6150-thermal-overlay.dtsi new file mode 100644 index 000000000000..f47d16937319 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-thermal-overlay.dtsi @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include + +&thermal_zones { + pm6150-tz { + cooling-maps { + trip0_bat { + trip = <&pm6150_trip0>; + cooling-device = + <&pm6150_charger (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip1_bat { + trip = <&pm6150_trip1>; + cooling-device = + <&pm6150_charger THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm6150l-tz { + cooling-maps { + trip0_cpu0 { + trip = <&pm6150l_trip0>; + cooling-device = + <&CPU0 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu1 { + trip = <&pm6150l_trip0>; + cooling-device = + <&CPU1 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu2 { + trip = <&pm6150l_trip0>; + cooling-device = + <&CPU2 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu3 { + trip = <&pm6150l_trip0>; + cooling-device = + <&CPU3 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu4 { + trip = <&pm6150l_trip0>; + cooling-device = + <&CPU4 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu5 { + trip = <&pm6150l_trip0>; + cooling-device = + <&CPU5 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu6 { + trip = <&pm6150l_trip0>; + cooling-device = + <&CPU6 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu7 { + trip = <&pm6150l_trip0>; + cooling-device = + <&CPU7 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip1_cpu1 { + trip = <&pm6150l_trip1>; + cooling-device = + <&CPU1 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu2 { + trip = <&pm6150l_trip1>; + cooling-device = + <&CPU2 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu3 { + trip = <&pm6150l_trip1>; + cooling-device = + <&CPU3 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu4 { + trip = <&pm6150l_trip1>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu5 { + trip = <&pm6150l_trip1>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu6 { + trip = <&pm6150l_trip1>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu7 { + trip = <&pm6150l_trip1>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm6150-vbat-lvl0 { + cooling-maps { + vbat_cpu6 { + trip = <&vbat_lvl0>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + vbat_cpu7 { + trip = <&vbat_lvl0>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm6150-ibat-lvl0 { + cooling-maps { + ibat_cpu6 { + trip = <&ibat_lvl0>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + ibat_cpu7 { + trip = <&ibat_lvl0>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + soc { + cooling-maps { + soc_cpu6 { + trip = <&soc_trip>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + soc_cpu7 { + trip = <&soc_trip>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; +}; + +&mdss_mdp { + #cooling-cells = <2>; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-thermal.dtsi b/arch/arm/boot/dts/qcom/sm6150-thermal.dtsi new file mode 100644 index 000000000000..d9862a9de0b2 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-thermal.dtsi @@ -0,0 +1,2087 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&clock_cpucc { + #address-cells = <1>; + #size-cells = <1>; + lmh_dcvs0: qcom,limits-dcvs@18358800 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + qcom,affinity = <0>; + reg = <0x18358800 0x1000>, + <0x18323000 0x1000>; + #thermal-sensor-cells = <0>; + }; + + lmh_dcvs1: qcom,limits-dcvs@18350800 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + qcom,affinity = <1>; + reg = <0x18350800 0x1000>, + <0x18325800 0x1000>; + #thermal-sensor-cells = <0>; + }; +}; + +&soc { + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + modem { + qcom,instance-id = <0x0>; + + modem_pa: modem_pa { + qcom,qmi-dev-name = "pa"; + #cooling-cells = <2>; + }; + + modem_proc: modem_proc { + qcom,qmi-dev-name = "modem"; + #cooling-cells = <2>; + }; + + modem_current: modem_current { + qcom,qmi-dev-name = "modem_current"; + #cooling-cells = <2>; + }; + + modem_skin: modem_skin { + qcom,qmi-dev-name = "modem_skin"; + #cooling-cells = <2>; + }; + + modem_vdd: modem_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + + adsp { + qcom,instance-id = <0x1>; + + adsp_vdd: adsp_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + + cdsp { + qcom,instance-id = <0x43>; + + cdsp_vdd: cdsp_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + }; + + cxip_cdev: cxip-cdev@1fed000 { + compatible = "qcom,cxip-lm-cooling-device"; + reg = <0x1fed000 0x24>; + #cooling-cells = <2>; + }; +}; + +&thermal_zones { + aoss-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 0>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 1>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 3>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpu-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + q6-hvx-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-core-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + wlan-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + display-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + video-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 15>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + lmh-dcvs-00 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&lmh_dcvs0>; + wake-capable-sensor; + + trips { + active-config { + temperature = <95000>; + hysteresis = <30000>; + type = "passive"; + }; + }; + }; + + lmh-dcvs-01 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&lmh_dcvs1>; + wake-capable-sensor; + + trips { + active-config { + temperature = <95000>; + hysteresis = <30000>; + type = "passive"; + }; + }; + }; + + gpu-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 9>; + wake-capable-sensor; + trips { + gpu_trip: gpu-trip { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + gpu_cx_mon: gpu-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + gpu_cdev { + trip = <&gpu_trip>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + gpu-cx-cdev0 { + trip = <&gpu_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + gpu-cx-cdev1 { + trip = <&gpu_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + gpu-cx-cdev2 { + trip = <&gpu_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + gpu-cx-cdev3 { + trip = <&gpu_cx_mon>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; + }; + }; + + cpuss0-max-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + silver-trip { + temperature = <120000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + apc1-max-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + gold-trip { + temperature = <120000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + cpuss-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 1>; + wake-capable-sensor; + trips { + cpu45_config: cpu45-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu4_cdev { + trip = <&cpu45_config>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + cpu5_cdev { + trip = <&cpu45_config>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpuss-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 2>; + wake-capable-sensor; + trips { + cpu23_config: cpu23-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu2_cdev { + trip = <&cpu23_config>; + cooling-device = + <&CPU2 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + cpu3_cdev { + trip = <&cpu23_config>; + cooling-device = + <&CPU3 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpuss-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu01_config: cpu01-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&cpu01_config>; + cooling-device = + <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + cpu1_cdev { + trip = <&cpu01_config>; + cooling-device = + <&CPU1 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu6_0_config: cpu6-0-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu6_cdev { + trip = <&cpu6_0_config>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu6_1_config: cpu6-1-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu6_cdev { + trip = <&cpu6_1_config>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu7_0_config: cpu7-0-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu7_cdev { + trip = <&cpu7_0_config>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu7_1_config: cpu7-1-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu7_cdev { + trip = <&cpu7_1_config>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + aoss-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 0>; + wake-capable-sensor; + tracks-low; + trips { + aoss0_trip: aoss0-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&aoss0_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&aoss0_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + cpuss-0-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 1>; + wake-capable-sensor; + tracks-low; + trips { + cpuss_0_trip: cpuss-0-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&cpuss_0_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&cpuss_0_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&cpuss_0_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&cpuss_0_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&cpuss_0_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&cpuss_0_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&cpuss_0_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&cpuss_0_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + cpuss-1-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 2>; + wake-capable-sensor; + tracks-low; + trips { + cpuss_1_trip: cpuss-1-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&cpuss_1_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&cpuss_1_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&cpuss_1_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&cpuss_1_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&cpuss_1_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&cpuss_1_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&cpuss_1_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&cpuss_1_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + cpuss-2-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 3>; + wake-capable-sensor; + tracks-low; + trips { + cpuss_2_trip: cpuss-2-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&cpuss_2_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&cpuss_2_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&cpuss_2_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&cpuss_2_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&cpuss_2_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&cpuss_2_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&cpuss_2_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&cpuss_2_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + cpuss-3-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 4>; + wake-capable-sensor; + tracks-low; + trips { + cpuss_3_trip: cpuss-3-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&cpuss_3_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&cpuss_3_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&cpuss_3_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&cpuss_3_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&cpuss_3_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&cpuss_3_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&cpuss_3_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&cpuss_3_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + cpu-1-0-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 5>; + wake-capable-sensor; + tracks-low; + trips { + cpu_1_0_trip: cpu-1-0-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&cpu_1_0_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&cpu_1_0_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&cpu_1_0_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&cpu_1_0_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&cpu_1_0_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&cpu_1_0_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&cpu_1_0_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&cpu_1_0_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + cpu-1-1-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 6>; + wake-capable-sensor; + tracks-low; + trips { + cpu_1_1_trip: cpu-1-1-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&cpu_1_1_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&cpu_1_1_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&cpu_1_1_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&cpu_1_1_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&cpu_1_1_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&cpu_1_1_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&cpu_1_1_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&cpu_1_1_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + cpu-1-2-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 7>; + wake-capable-sensor; + tracks-low; + trips { + cpu_1_2_trip: cpu-1-2-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&cpu_1_2_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&cpu_1_2_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&cpu_1_2_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&cpu_1_2_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&cpu_1_2_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&cpu_1_2_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&cpu_1_2_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&cpu_1_2_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + cpu-1-3-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 8>; + wake-capable-sensor; + tracks-low; + trips { + cpu_1_3_trip: cpu-1-3-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&cpu_1_3_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&cpu_1_3_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&cpu_1_3_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&cpu_1_3_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&cpu_1_3_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&cpu_1_3_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&cpu_1_3_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&cpu_1_3_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + gpu-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 9>; + wake-capable-sensor; + tracks-low; + trips { + gpu_lowf_trip: gpu-lowf-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&gpu_lowf_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&gpu_lowf_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&gpu_lowf_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&gpu_lowf_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&gpu_lowf_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&gpu_lowf_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&gpu_lowf_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&gpu_lowf_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + q6-hvx-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 10>; + wake-capable-sensor; + tracks-low; + trips { + q6_hvx_trip: q6-hvx-lowf-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&q6_hvx_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&q6_hvx_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&q6_hvx_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&q6_hvx_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&q6_hvx_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&q6_hvx_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&q6_hvx_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&q6_hvx_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + mdm-core-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 11>; + wake-capable-sensor; + tracks-low; + trips { + mdm_core_trip: mdm-core-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + camera-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 12>; + wake-capable-sensor; + tracks-low; + trips { + camera_trip: camera-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&camera_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&camera_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + wlan-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 13>; + wake-capable-sensor; + tracks-low; + trips { + wlan_trip: wlan-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&wlan_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&wlan_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&wlan_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&wlan_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&wlan_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&wlan_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&wlan_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&wlan_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + display-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 14>; + wake-capable-sensor; + tracks-low; + trips { + display_trip: display-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&display_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&display_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&display_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&display_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&display_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&display_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&display_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&display_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + video-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 15>; + wake-capable-sensor; + tracks-low; + trips { + video_trip: video-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&video_trip>; + cooling-device = <&CPU0 2 2>; + }; + cpu1_cdev { + trip = <&video_trip>; + cooling-device = <&CPU6 4 4>; + }; + gpu_vdd_cdev { + trip = <&video_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + cx_vdd_cdev { + trip = <&video_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&video_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&video_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&video_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&video_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + q6-hvx-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + q6_hvx_cxip: q6-hvx-config { + temperature = <95000>; + hysteresis = <20000>; + type = "passive"; + }; + q6_hvx_therm: q6-hvx-trip1 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + q6_hvx_cx_mon: q6-hvx-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cxip-cdev { + trip = <&q6_hvx_cxip>; + cooling-device = <&cxip_cdev 1 1>; + }; + cdsp-cdev { + trip = <&q6_hvx_therm>; + cooling-device = <&msm_cdsp_rm + THERMAL_NO_LIMIT 5>; + }; + hvx-cx-cdev0 { + trip = <&q6_hvx_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + hvx-cx-cdev1 { + trip = <&q6_hvx_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + hvx-cx-cdev2 { + trip = <&q6_hvx_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + hvx-cx-cdev3 { + trip = <&q6_hvx_cx_mon>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; + }; + }; + + mdm-core-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + mdm_core_cx_mon: mdm-core-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + mdm-cx-cdev0 { + trip = <&mdm_core_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + mdm-cx-cdev1 { + trip = <&mdm_core_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + mdm-cx-cdev2 { + trip = <&mdm_core_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + mdm-cx-cdev3 { + trip = <&mdm_core_cx_mon>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; + }; + }; + + camera-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + camera_cx_mon: camera-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + camera-cx-cdev0 { + trip = <&camera_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + camera-cx-cdev1 { + trip = <&camera_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + camera-cx-cdev2 { + trip = <&camera_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + camera-cx-cdev3 { + trip = <&camera_cx_mon>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; + }; + }; + + wlan-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + wlan_cx_mon: wlan-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + wlan-cx-cdev0 { + trip = <&wlan_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + wlan-cx-cdev1 { + trip = <&wlan_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + wlan-cx-cdev2 { + trip = <&wlan_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + wlan-cx-cdev3 { + trip = <&wlan_cx_mon>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; + }; + }; + + display-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + dispaly_cx_mon: display-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + display-cx-cdev0 { + trip = <&dispaly_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + display-cx-cdev1 { + trip = <&dispaly_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + display-cx-cdev2 { + trip = <&dispaly_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + display-cx-cdev3 { + trip = <&dispaly_cx_mon>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; + }; + }; + + video-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 15>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + video_cx_mon: video-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + video-cx-cdev0 { + trip = <&video_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + video-cx-cdev1 { + trip = <&video_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + video-cx-cdev2 { + trip = <&video_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + video-cx-cdev3 { + trip = <&video_cx_mon>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; + }; + }; + + xo-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6150_adc_tm ADC_XO_THERM_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdm-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6150_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6150_adc_tm ADC_AMUX_THM4_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + emmc_ufs-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6150l_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + rf_pa0_therm-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6150l_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + camera_flash-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6150l_adc_tm ADC_GPIO1_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6150l_adc_tm ADC_GPIO4_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet-therm-step { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6150l_adc_tm ADC_GPIO4_PU2>; + wake-capable-sensor; + trips { + gold_trip: gold-trip { + temperature = <46000>; + hysteresis = <0>; + type = "passive"; + }; + modem_trip0: modem-trip0 { + temperature = <46000>; + hysteresis = <4000>; + type = "passive"; + }; + skin_gpu_trip: skin-gpu-trip { + temperature = <48000>; + hysteresis = <0>; + type = "passive"; + }; + modem_trip1: modem-trip1 { + temperature = <48000>; + hysteresis = <2000>; + type = "passive"; + }; + modem_trip2: modem-trip2 { + temperature = <50000>; + hysteresis = <2000>; + type = "passive"; + }; + batt_trip0: batt-trip0 { + temperature = <50000>; + hysteresis = <4000>; + type = "passive"; + }; + silver_trip: silver-trip { + temperature = <52000>; + hysteresis = <0>; + type = "passive"; + }; + modem_trip3_batt_trip1: modem-trip3 { + temperature = <52000>; + hysteresis = <2000>; + type = "passive"; + }; + cx_emer_trip: cx-emer-trip { + temperature = <52000>; + hysteresis = <4000>; + type = "passive"; + }; + batt_trip2: batt-trip2 { + temperature = <54000>; + hysteresis = <2000>; + type = "passive"; + }; + batt_trip3: batt-trip3 { + temperature = <56000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + cooling-maps { + skin_cpu6 { + trip = <&gold_trip>; + cooling-device = + /* throttle from fmax to 1708800KHz */ + <&CPU6 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-9)>; + }; + skin_cpu7 { + trip = <&gold_trip>; + cooling-device = + <&CPU7 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-9)>; + }; + skin_cpu0 { + trip = <&silver_trip>; + /* throttle from fmax to 1516800KHz */ + cooling-device = <&CPU0 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-7)>; + }; + skin_cpu1 { + trip = <&silver_trip>; + cooling-device = <&CPU1 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-7)>; + }; + skin_cpu2 { + trip = <&silver_trip>; + cooling-device = <&CPU2 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-7)>; + }; + skin_cpu3 { + trip = <&silver_trip>; + cooling-device = <&CPU3 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-7)>; + }; + skin_cpu4 { + trip = <&silver_trip>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-7)>; + }; + skin_cpu5 { + trip = <&silver_trip>; + cooling-device = <&CPU5 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-7)>; + }; + skin_gpu { + trip = <&skin_gpu_trip>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-4)>; + }; + modem_lvl1 { + trip = <&modem_trip1>; + cooling-device = <&modem_pa 1 1>; + }; + modem_lvl2 { + trip = <&modem_trip2>; + cooling-device = <&modem_pa 2 2>; + }; + modem_lvl3 { + trip = <&modem_trip3_batt_trip1>; + cooling-device = <&modem_pa 3 3>; + }; + modem_proc_lvl1 { + trip = <&modem_trip0>; + cooling-device = <&modem_proc 1 1>; + }; + modem_proc_lvl3 { + trip = <&modem_trip3_batt_trip1>; + cooling-device = <&modem_proc 3 3>; + }; + battery_lvl0 { + trip = <&batt_trip0>; + cooling-device = <&pm6150_charger 1 1>; + }; + battery_lvl1 { + trip = <&modem_trip3_batt_trip1>; + cooling-device = <&pm6150_charger 2 2>; + }; + battery_lvl2 { + trip = <&batt_trip2>; + cooling-device = <&pm6150_charger 4 4>; + }; + battery_lvl3 { + trip = <&batt_trip3>; + cooling-device = <&pm6150_charger 5 5>; + }; + cx_skin_gpu { + trip = <&cx_emer_trip>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + cx-skin-cdsp { + trip = <&cx_emer_trip>; + cooling-device = <&msm_cdsp_rm 5 5>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-usb.dtsi b/arch/arm/boot/dts/qcom/sm6150-usb.dtsi new file mode 100644 index 000000000000..29f885820156 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-usb.dtsi @@ -0,0 +1,436 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&soc { + /* Primary USB port related controller */ + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x140 0x0>; + qcom,smmu-s1-bypass; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <0 489 0>, <0 130 0>, <0 486 0>, <0 488 0>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&usb30_prim_gdsc>; + dpdm-supply = <&qusb_phy0>; + clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>, + <&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "xo", "sleep_clk", "utmi_clk"; + + resets = <&clock_gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + qcom,pm-qos-latency = <61>; + + qcom,msm-bus,name = "usb0"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <3>; + qcom,msm-bus,vectors-KBps = + /* suspend vote */ + , + , + , + + /* nominal vote */ + , + , + , + + /* svs vote */ + , + , + , + + /* min vote */ + , + , + ; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xcd00>; + interrupt-parent = <&intc>; + interrupts = <0 133 0>; + usb-phy = <&qusb_phy0>, <&usb_qmp_phy>; + tx-fifo-resize; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + usb-core-id = <0>; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + + qcom,usbbam@a704000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa704000 0x17000>; + interrupts = <0 132 0>; + + qcom,usb-bam-fifo-baseaddr = <0x146a6000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + /* Primary USB port related High Speed PHY */ + qusb_phy0: qusb@88e2000 { + compatible = "qcom,qusb2phy"; + reg = <0x88e2000 0x180>, + <0x01fcb250 0x4>, + <0x007801f8 0x4>, + <0x01fcb3e4 0x4>; + reg-names = "qusb_phy_base", + "tcsr_clamp_dig_n_1p8", + "tune2_efuse_addr", + "tcsr_conn_box_spare_0"; + + vdd-supply = <&pm6150_l4>; + vdda18-supply = <&pm6150_l11>; + vdda33-supply = <&pm6150_l17>; + qcom,vdd-voltage-level = <0 925000 975000>; + qcom,tune2-efuse-bit-pos = <25>; + qcom,tune2-efuse-num-bits = <4>; + qcom,qusb-phy-init-seq = <0xc8 0x80 + 0xb3 0x84 + 0x83 0x88 + 0xc0 0x8c + 0x30 0x08 + 0x79 0x0c + 0x21 0x10 + 0x14 0x9c + 0x9f 0x1c + 0x00 0x18>; + phy_type = "utmi"; + qcom,phy-clk-scheme = "cml"; + qcom,major-rev = <1>; + + /* USB2PHY gets clock directly from CXO pad + * connected to differential pin cxo_core_in_1p8_vdda. + */ + clocks = <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_AHB2PHY_WEST_CLK>; + clock-names = "ref_clk_src", "cfg_ahb_clk"; + + resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + /* Primary USB port related QMP USB PHY */ + usb_qmp_phy: ssphy@88e6000 { + compatible = "qcom,usb-ssphy-qmp-usb3-or-dp"; + reg = <0x88e6000 0x1000>, + <0x01fcb244 0x4>; + reg-names = "qmp_phy_base", + "vls_clamp_reg"; + + vdd-supply = <&pm6150_l4>; + core-supply = <&pm6150_l11>; + qcom,vdd-voltage-level = <0 925000 975000>; + qcom,core-voltage-level = <0 1800000 1800000>; + qcom,qmp-phy-init-seq = + /* */ + <0xac 0x14 0x00 + 0x34 0x08 0x00 + 0x174 0x30 0x00 + 0x3c 0x06 0x00 + 0xb4 0x00 0x00 + 0xb8 0x08 0x00 + 0x70 0x0f 0x00 + 0x19c 0x01 0x00 + 0x178 0x00 0x00 + 0xd0 0x82 0x00 + 0xdc 0x55 0x00 + 0xe0 0x55 0x00 + 0xe4 0x03 0x00 + 0x78 0x0b 0x00 + 0x84 0x16 0x00 + 0x90 0x28 0x00 + 0x108 0x80 0x00 + 0x10c 0x00 0x00 + 0x184 0x0a 0x00 + 0x4c 0x15 0x00 + 0x50 0x34 0x00 + 0x54 0x00 0x00 + 0xc8 0x00 0x00 + 0x18c 0x00 0x00 + 0xcc 0x00 0x00 + 0x128 0x00 0x00 + 0x0c 0x0a 0x00 + 0x10 0x01 0x00 + 0x1c 0x31 0x00 + 0x20 0x01 0x00 + 0x14 0x00 0x00 + 0x18 0x00 0x00 + 0x24 0xde 0x00 + 0x28 0x07 0x00 + 0x48 0x0f 0x00 + 0x194 0x06 0x00 + 0x100 0x80 0x00 + 0xa8 0x01 0x00 + 0x430 0x0b 0x00 + 0x830 0x0b 0x00 + 0x444 0x00 0x00 + 0x844 0x00 0x00 + 0x43c 0x00 0x00 + 0x83c 0x00 0x00 + 0x440 0x00 0x00 + 0x840 0x00 0x00 + 0x408 0x0a 0x00 + 0x808 0x0a 0x00 + 0x414 0x06 0x00 + 0x814 0x06 0x00 + 0x434 0x75 0x00 + 0x834 0x75 0x00 + 0x4d4 0x02 0x00 + 0x8d4 0x02 0x00 + 0x4d8 0x4e 0x00 + 0x8d8 0x4e 0x00 + 0x4dc 0x18 0x00 + 0x8dc 0x18 0x00 + 0x4f8 0x77 0x00 + 0x8f8 0x77 0x00 + 0x4fc 0x80 0x00 + 0x8fc 0x80 0x00 + 0x4c0 0x0a 0x00 + 0x8c0 0x0a 0x00 + 0x504 0x03 0x00 + 0x904 0x03 0x00 + 0x50c 0x16 0x00 + 0x90c 0x16 0x00 + 0x500 0x00 0x00 + 0x900 0x00 0x00 + 0x564 0x00 0x00 + 0x964 0x00 0x00 + 0x260 0x10 0x00 + 0x660 0x10 0x00 + 0x2a4 0x12 0x00 + 0x6a4 0x12 0x00 + 0x28c 0xc6 0x00 + 0x68c 0xc6 0x00 + 0x244 0x00 0x00 + 0x644 0x00 0x00 + 0x248 0x00 0x00 + 0x648 0x00 0x00 + 0xc0c 0x9f 0x00 + 0xc24 0x17 0x00 + 0xc28 0x0f 0x00 + 0xcc8 0x83 0x00 + 0xcc4 0x02 0x00 + 0xccc 0x09 0x00 + 0xcd0 0xa2 0x00 + 0xcd4 0x85 0x00 + 0xc80 0xd1 0x00 + 0xc84 0x1f 0x00 + 0xc88 0x47 0x00 + 0xcb8 0x75 0x00 + 0xcbc 0x13 0x00 + 0xcb0 0x86 0x00 + 0xca0 0x04 0x00 + 0xc8c 0x44 0x00 + 0xc70 0xe7 0x00 + 0xc74 0x03 0x00 + 0xc78 0x40 0x00 + 0xc7c 0x00 0x00 + 0xdd8 0x88 0x00 + 0xffffffff 0xffffffff 0x00>; + + qcom,qmp-phy-reg-offset = + <0xd74 /* USB3_PHY_PCS_STATUS */ + 0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */ + 0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */ + 0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */ + 0xc00 /* USB3_PHY_SW_RESET */ + 0xc08 /* USB3_PHY_START */ + 0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */ + + clocks = <&clock_gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&clock_gcc GCC_AHB2PHY_WEST_CLK>; + + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk", "cfg_ahb_clk"; + + resets = <&clock_gcc GCC_USB3_PHY_PRIM_SP0_BCR>, + <&clock_gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x172f 0x0>; + qcom,usb-audio-stream-id = <0xf>; + qcom,usb-audio-intr-num = <2>; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + /* Secondary USB port related controller */ + usb1: hsusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa800000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0xE0 0x0>; + qcom,smmu-s1-bypass; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <0 491 0>, <0 663 0>, <0 490 0>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&usb20_sec_gdsc>; + clocks = <&clock_gcc GCC_USB20_SEC_MASTER_CLK>, + <&clock_gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>, + <&clock_gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, + <&clock_gcc GCC_USB3_SEC_CLKREF_CLK>, + <&clock_gcc GCC_USB20_SEC_SLEEP_CLK>, + <&clock_gcc GCC_USB20_SEC_MOCK_UTMI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "xo", "sleep_clk", "utmi_clk"; + + resets = <&clock_gcc GCC_USB20_SEC_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <120000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + qcom,charging-disabled; + + qcom,msm-bus,name = "usb1"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + /* svs vote */ + , + ; + + status = "disabled"; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0xa800000 0xcd00>; + interrupt-parent = <&intc>; + interrupts = <0 664 0>; + usb-phy = <&qusb_phy1>, <&usb_nop_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + usb-core-id = <1>; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + + /* Secondary USB port related High Speed PHY */ + qusb_phy1: qusb@88e3000 { + compatible = "qcom,qusb2phy"; + reg = <0x88e3000 0x180>, + <0x01fcb3e4 0x4>; + reg-names = "qusb_phy_base", + "tcsr_conn_box_spare_0"; + + vdd-supply = <&pm6150_l4>; + vdda18-supply = <&pm6150_l11>; + vdda33-supply = <&pm6150_l17>; + qcom,vdd-voltage-level = <0 925000 975000>; + qcom,qusb-phy-init-seq = <0xc8 0x80 + 0xb3 0x84 + 0x83 0x88 + 0xc0 0x8c + 0x30 0x08 + 0x79 0x0c + 0x21 0x10 + 0x14 0x9c + 0x9f 0x1c + 0x00 0x18>; + phy_type = "utmi"; + qcom,phy-clk-scheme = "cml"; + qcom,major-rev = <1>; + qcom,hold-reset; + + /* USB2PHY gets clock directly from CXO pad + * connected to differential pin cxo_core_in_1p8_vdda. + */ + clocks = <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_AHB2PHY_WEST_CLK>; + clock-names = "ref_clk_src", "cfg_ahb_clk"; + + resets = <&clock_gcc GCC_QUSB2PHY_SEC_BCR>; + reset-names = "phy_reset"; + }; + +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-usbc-idp-overlay.dts b/arch/arm/boot/dts/qcom/sm6150-usbc-idp-overlay.dts new file mode 100644 index 000000000000..c56081f94430 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-usbc-idp-overlay.dts @@ -0,0 +1,31 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "sm6150-idp.dtsi" +#include "sm6150-usbc-idp.dtsi" + +/ { + model = "USBC Audio IDP"; + compatible = "qcom,sm6150-idp", "qcom,sm6150", "qcom,idp"; + qcom,msm-id = <355 0x0>; + qcom,board-id = <34 2>; +}; + +&dsi_hx83112a_truly_vid_display { + qcom,dsi-display-active; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-usbc-idp.dts b/arch/arm/boot/dts/qcom/sm6150-usbc-idp.dts new file mode 100644 index 000000000000..dc1c415d21f2 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-usbc-idp.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm6150.dtsi" +#include "sm6150-idp.dtsi" +#include "sm6150-usbc-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM6150 PM6150 USBC Audio IDP"; + compatible = "qcom,sm6150-idp", "qcom,sm6150", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-usbc-idp.dtsi b/arch/arm/boot/dts/qcom/sm6150-usbc-idp.dtsi new file mode 100644 index 000000000000..86330a6c4cf8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-usbc-idp.dtsi @@ -0,0 +1,19 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm6150-audio-overlay.dtsi" + +&sm6150_snd { + qcom,msm-mbhc-usbc-audio-supported = <1>; + qcom,msm-mbhc-hphl-swh = <0>; + qcom,msm-mbhc-gnd-swh = <0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-usbc-minidp-idp-overlay.dts b/arch/arm/boot/dts/qcom/sm6150-usbc-minidp-idp-overlay.dts new file mode 100644 index 000000000000..86f784bad3bb --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-usbc-minidp-idp-overlay.dts @@ -0,0 +1,32 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "sm6150-idp.dtsi" +#include "sm6150-usbc-idp.dtsi" + +/ { + model = "USBC mini DP Primary Panel IDP"; + compatible = "qcom,sm6150-idp", "qcom,sm6150", "qcom,idp"; + qcom,msm-id = <355 0x0>; + qcom,board-id = <34 4>; +}; + +&sde_dp { + qcom,dp-hpd-gpio = <&tlmm 103 0>; + qcom,dp-low-power-hw-hpd; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-usbc-minidp-idp.dts b/arch/arm/boot/dts/qcom/sm6150-usbc-minidp-idp.dts new file mode 100644 index 000000000000..416d1d3df8b4 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-usbc-minidp-idp.dts @@ -0,0 +1,28 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm6150.dtsi" +#include "sm6150-idp.dtsi" +#include "sm6150-usbc-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM6150 PM6150 USBC mini DP Primary Panel IDP"; + compatible = "qcom,sm6150-idp", "qcom,sm6150", "qcom,idp"; + qcom,board-id = <34 4>; +}; + +&sde_dp { + qcom,dp-hpd-gpio = <&tlmm 103 0>; + qcom,dp-low-power-hw-hpd; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-vidc.dtsi b/arch/arm/boot/dts/qcom/sm6150-vidc.dtsi new file mode 100644 index 000000000000..cc3c68c2e3d8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-vidc.dtsi @@ -0,0 +1,109 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&soc { + msm_vidc: qcom,vidc@aa00000 { + compatible = "qcom,msm-vidc", "qcom,sm6150-vidc"; + status = "ok"; + reg = <0xaa00000 0x200000>; + interrupts = ; + + /* Supply */ + venus-supply = <&venus_gdsc>; + venus-core0-supply = <&vcodec0_gdsc>; + + /* Clocks */ + clock-names = "core_clk", "iface_clk", "bus_clk", + "core0_clk", "core0_bus_clk"; + clocks = <&clock_videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, + <&clock_videocc VIDEO_CC_VENUS_AHB_CLK>, + <&clock_videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, + <&clock_videocc VIDEO_CC_VCODEC0_CORE_CLK>, + <&clock_videocc VIDEO_CC_VCODEC0_AXI_CLK>; + qcom,proxy-clock-names = "core_clk", "iface_clk", + "bus_clk", "core0_clk", "core0_bus_clk"; + qcom,clock-configs = <0x1 0x0 0x0 0x1 0x0>; + qcom,allowed-clock-rates = <133330000 240000000 300000000 + 380000000 410000000>; + + /* Buses */ + bus_cnoc { + compatible = "qcom,msm-vidc,bus"; + label = "cnoc"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 1000>; + }; + + venus_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-ddr"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "vidc-ar50-ddr"; + qcom,bus-range-kbps = <1000 2128000>; + }; + arm9_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-arm9-ddr"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 1000>; + }; + + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_ns"; + iommus = + <&apps_smmu 0xE40 0x20>; + buffer-types = <0xfff>; + virtual-addr-pool = <0x70800000 0x6f800000>; + }; + + secure_bitstream_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_bitstream"; + iommus = + <&apps_smmu 0xE61 0x4>; + buffer-types = <0x241>; + virtual-addr-pool = <0x4b000000 0x25800000>; + qcom,secure-context-bank; + }; + + secure_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_pixel"; + iommus = + <&apps_smmu 0xE63 0x0>; + buffer-types = <0x106>; + virtual-addr-pool = <0x25800000 0x25800000>; + qcom,secure-context-bank; + }; + + secure_non_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_non_pixel"; + iommus = + <&apps_smmu 0xE44 0x20>; + buffer-types = <0x480>; + virtual-addr-pool = <0x1000000 0x24800000>; + qcom,secure-context-bank; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150-wcd.dtsi b/arch/arm/boot/dts/qcom/sm6150-wcd.dtsi new file mode 100644 index 000000000000..6a9f40895142 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150-wcd.dtsi @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&slim_aud { + tavil_codec { + tavil_wcd: wcd_pinctrl@5 { + compatible = "qcom,wcd-pinctrl"; + qcom,num-gpios = <5>; + gpio-controller; + #gpio-cells = <2>; + + us_euro_sw_active: us_euro_sw_wcd_active { + mux { + pins = "gpio1"; + }; + + config { + pins = "gpio1"; + output-high; + }; + }; + + us_euro_sw_sleep: us_euro_sw_wcd_sleep { + mux { + pins = "gpio1"; + }; + + config { + pins = "gpio1"; + output-low; + }; + }; + + spk_1_wcd_en_active: spkr_1_wcd_en_active { + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + output-high; + }; + }; + + spk_1_wcd_en_sleep: spkr_1_wcd_en_sleep { + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + input-enable; + }; + }; + + spk_2_wcd_en_active: spkr_2_sd_n_active { + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + output-high; + }; + }; + + spk_2_wcd_en_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + input-enable; + }; + }; + + hph_en0_wcd_active: hph_en0_wcd_active { + mux { + pins = "gpio4"; + }; + + config { + pins = "gpio4"; + output-high; + }; + }; + + hph_en0_wcd_sleep: hph_en0_wcd_sleep { + mux { + pins = "gpio4"; + }; + + config { + pins = "gpio4"; + output-low; + }; + }; + + hph_en1_wcd_active: hph_en1_wcd_active { + mux { + pins = "gpio5"; + }; + + config { + pins = "gpio5"; + output-high; + }; + }; + + hph_en1_wcd_sleep: hph_en1_wcd_sleep { + mux { + pins = "gpio5"; + }; + + config { + pins = "gpio5"; + output-low; + }; + }; + }; + + wsa_spk_wcd_sd1: msm_cdc_pinctrll { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spk_1_wcd_en_active>; + pinctrl-1 = <&spk_1_wcd_en_sleep>; + }; + + wsa_spk_wcd_sd2: msm_cdc_pinctrlr { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spk_2_wcd_en_active>; + pinctrl-1 = <&spk_2_wcd_en_sleep>; + }; + + tavil_us_euro_switch: msm_cdc_pinctrl_us_euro_sw { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&us_euro_sw_active>; + pinctrl-1 = <&us_euro_sw_sleep>; + }; + + tavil_hph_en0: msm_cdc_pinctrl_hph_en0 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&hph_en0_wcd_active>; + pinctrl-1 = <&hph_en0_wcd_sleep>; + }; + + tavil_hph_en1: msm_cdc_pinctrl_hph_en1 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&hph_en1_wcd_active>; + pinctrl-1 = <&hph_en1_wcd_sleep>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150.dts b/arch/arm/boot/dts/qcom/sm6150.dts new file mode 100644 index 000000000000..821857599650 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm6150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM6150 SoC"; + compatible = "qcom,sm6150"; + qcom,pmic-name = "PM6150"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150.dtsi b/arch/arm/boot/dts/qcom/sm6150.dtsi new file mode 100644 index 000000000000..bef0d618e3d1 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150.dtsi @@ -0,0 +1,3245 @@ + /* Copyright (c) 2018-2019, The Linux Foundation.All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "skeleton64.dtsi" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} + +/ { + model = "Qualcomm Technologies, Inc. SM6150"; + compatible = "qcom,sm6150"; + qcom,msm-name = "SM6150"; + qcom,msm-id = <355 0x0>; + interrupt-parent = <&pdc>; + + aliases { + ufshc1 = &ufshc_mem; /* Embedded UFS slot */ + serial0 = &qupv3_se0_2uart; + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ + sdhc2 = &sdhc_2; /* SDC2 SD Card slot */ + spi0 = &qupv3_se4_spi; + i2c0 = &qupv3_se5_i2c; + i2c1 = &qupv3_se1_i2c; + i2c2 = &qupv3_se3_i2c; + hsuart0 = &qupv3_se7_4uart; + hsuart1 = &qupv3_se4_2uart; + swr0 = &swr0; + swr1 = &swr1; + swr2 = &swr2; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + cache-size = <0x8000>; + next-level-cache = <&L2_0>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-size = <0x100000>; + cache-level = <3>; + }; + }; + + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_0: l2-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + cache-size = <0x8000>; + next-level-cache = <&L2_100>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_100: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_100: l1-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + cache-size = <0x8000>; + next-level-cache = <&L2_200>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_200: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_200: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_200: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_200: l1-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + cache-size = <0x8000>; + next-level-cache = <&L2_300>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_300: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_300: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_300: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_300: l1-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + cache-size = <0x8000>; + next-level-cache = <&L2_400>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_400: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_400: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_400: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_400: l1-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + cache-size = <0x8000>; + next-level-cache = <&L2_500>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_500: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_500: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_500: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_500: l1-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; + cache-size = <0x10000>; + next-level-cache = <&L2_600>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + #cooling-cells = <2>; + L2_600: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + qcom,dump-size = <0x48000>; + }; + + L1_I_600: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x11000>; + }; + + L1_D_600: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + + L1_ITLB_600: l1-itlb { + qcom,dump-size = <0x300>; + }; + + L1_DTLB_600: l1-dtlb { + qcom,dump-size = <0x480>; + }; + + L2_TLB_600: l2-tlb { + qcom,dump-size = <0x7800>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; + cache-size = <0x10000>; + next-level-cache = <&L2_700>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + #cooling-cells = <2>; + L2_700: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + qcom,dump-size = <0x48000>; + }; + + L1_I_700: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x11000>; + }; + + L1_D_700: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + + L1_ITLB_700: l1-itlb { + qcom,dump-size = <0x300>; + }; + + L1_DTLB_700: l1-dtlb { + qcom,dump-size = <0x480>; + }; + + L2_TLB_700: l2-tlb { + qcom,dump-size = <0x7800>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + }; + + cluster1 { + core0 { + cpu = <&CPU6>; + }; + + core1 { + cpu = <&CPU7>; + }; + }; + }; + }; + + energy_costs: energy-costs { + compatible = "sched-energy"; + + CPU_COST_0: core-cost0 { + busy-cost-data = < + 300000 24 + 576000 25 + 748800 31 + 1017600 54 + 1209600 78 + 1363200 105 + 1516800 116 + 1593600 139 + 1708800 168 + 1804800 178 + >; + idle-cost-data = < + 16 12 8 6 + >; + }; + + CPU_COST_1: core-cost1 { + busy-cost-data = < + 300000 180 + 652800 236 + 768000 273 + 979200 446 + 1017600 462 + 1209600 662 + 1363200 894 + 1516800 989 + 1708800 1276 + 1900800 1652 + 2016000 2040 + 2112000 2242 + 2208000 2713 + >; + idle-cost-data = < + 100 80 60 40 + >; + }; + + CLUSTER_COST_0: cluster-cost0 { + busy-cost-data = < + 300000 8 + 576000 8 + 748800 9 + 1017600 12 + 1209600 15 + 1363200 18 + 1516800 21 + 1593600 22 + 1708800 23 + 1804800 24 + >; + idle-cost-data = < + 4 3 2 1 + >; + }; + + CLUSTER_COST_1: cluster-cost1 { + busy-cost-data = < + 300000 28 + 652800 35 + 768000 36 + 979200 48 + 1017600 59 + 1209600 73 + 1363200 86 + 1516800 88 + 1708800 96 + 1900800 103 + 2016000 107 + 2112000 112 + 2208000 120 + >; + idle-cost-data = < + 4 3 2 1 + >; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + }; + + soc: soc { }; + + firmware: firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; + }; + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_region: hyp_region@85700000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x85700000 0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_mem@85e00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x85e00000 0x0 0x140000>; + }; + + sec_apps_mem: sec_apps_region@85fff000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x85fff000 0x0 0x1000>; + }; + + smem_region: smem@86000000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x86000000 0x0 0x200000>; + }; + + removed_region: removed_region@86200000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x86200000 0 0x2d00000>; + }; + + pil_camera_mem: camera_region@8ab00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x8ab00000 0 0x500000>; + }; + + pil_modem_mem: modem_region@8b000000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x8b000000 0 0x7e00000>; + }; + + pil_video_mem: pil_video_region@92e00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x92e00000 0 0x500000>; + }; + + wlan_msa_mem: wlan_msa_region@93300000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x93300000 0 0x200000>; + }; + + pil_cdsp_mem: cdsp_regions@93500000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x93500000 0 0x1e00000>; + }; + + pil_adsp_mem: pil_adsp_region@95300000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x95300000 0 0x1e00000>; + }; + + pil_ipa_fw_mem: ips_fw_region@0x97100000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x97100000 0 0x10000>; + }; + + pil_ipa_gsi_mem: ipa_gsi_region@0x97110000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x97110000 0 0x5000>; + }; + + pil_gpu_mem: gpu_region@0x97115000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x97115000 0 0x2000>; + }; + + qseecom_mem: qseecom_region@0x9e400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x9e400000 0 0x1400000>; + }; + + cdsp_sec_mem: cdsp_sec_regions@0x9f800000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x9f800000 0x0 0x1e00000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + sdsp_mem: sdsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x1000000>; + }; + + sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */ + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x8c00000>; + }; + + cont_splash_memory: cont_splash_region@9c000000 { + reg = <0x0 0x9c000000 0x0 0x01000000>; + label = "cont_splash_region"; + }; + + dfps_data_memory: dfps_data_region@9e300000 { + reg = <0x0 0x9cf00000 0x0 0x0100000>; + label = "dfps_data_region"; + }; + + disp_rdump_memory: disp_rdump_region@9c000000 { + reg = <0x0 0x9c000000 0x0 0x01000000>; + label = "disp_rdump_region"; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x2400000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x2000000>; + linux,cma-default; + }; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17a60000 0x100000>; /* GICR * 8 */ + interrupts = <1 9 4>; + interrupt-parent = <&intc>; + }; + + pdc: interrupt-controller@b220000{ + compatible = "qcom,pdc-sm6150"; + reg = <0xb220000 0x400>; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <2>; + label = "modem"; + }; + + mem_client_3_size: qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x500000>; + qcom,client-id = <1>; + qcom,allocate-on-request; + label = "modem"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 1 0xf08>, + <1 2 0xf08>, + <1 3 0xf08>, + <1 0 0xf08>; + clock-frequency = <19200000>; + }; + + timer@0x17c20000{ + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17c20000 0x1000>; + clock-frequency = <19200000>; + + frame@0x17c21000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 6 0x4>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0x17c23000 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0x17c25000 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0x17c27000 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0x17c29000 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0x17c2b000 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0x17c2d000 0x1000>; + status = "disabled"; + }; + }; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "chip_sleep_clk"; + #clock-cells = <1>; + }; + }; + + clock_rpmh: qcom,rpmhclk { + compatible = "qcom,rpmh-clk-sm6150"; + mboxes = <&apps_rsc 0>; + mbox-names = "apps"; + #clock-cells = <1>; + }; + + clock_aop: qcom,aopclk { + compatible = "qcom,aop-qmp-clk"; + #clock-cells = <1>; + mboxes = <&qmp_aop 0>; + mbox-names = "qdss_clk"; + }; + + clock_gcc: qcom,gcc@100000 { + compatible = "qcom,gcc-sm6150", "syscon"; + reg = <0x100000 0x1f0000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; + protected-clocks = , + , + , + , + , + , + ; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_videocc: qcom,videocc@ab00000 { + compatible = "qcom,videocc-sm6150", "syscon"; + reg = <0xab00000 0x10000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_camcc: qcom,camcc@ad00000 { + compatible = "qcom,camcc-sm6150", "syscon"; + reg = <0xad00000 0x10000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + #clock-cells = <1>; + #reset-cells = <1>; + qcom,cam_cc_csi0phytimer_clk_src-opp-handle = <&cam_csiphy0>; + qcom,cam_cc_csi1phytimer_clk_src-opp-handle = <&cam_csiphy1>; + qcom,cam_cc_csi2phytimer_clk_src-opp-handle = <&cam_csiphy2>; + qcom,cam_cc_cci_clk_src-opp-handle = <&cam_cci>; + qcom,cam_cc_ife_0_csid_clk_src-opp-handle = <&cam_csid0>; + qcom,cam_cc_ife_0_clk_src-opp-handle = <&cam_vfe0>; + qcom,cam_cc_ife_1_csid_clk_src-opp-handle = <&cam_csid1>; + qcom,cam_cc_ife_1_clk_src-opp-handle = <&cam_vfe1>; + qcom,cam_cc_ife_lite_csid_clk_src-opp-handle = <&cam_csid_lite>; + qcom,cam_cc_ife_lite_clk_src-opp-handle = <&cam_vfe_lite>; + qcom,cam_cc_icp_clk_src-opp-handle = <&cam_a5>; + qcom,cam_cc_ipe_0_clk_src-opp-handle = <&cam_ipe0>; + qcom,cam_cc_bps_clk_src-opp-handle = <&cam_bps>; + }; + + clock_dispcc: qcom,dispcc@af00000 { + compatible = "qcom,dispcc-sm6150", "syscon"; + reg = <0xaf00000 0x20000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_gpucc: qcom,gpupcc@5090000 { + compatible = "qcom,gpucc-sm6150", "syscon"; + reg = <0x5090000 0x9000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + #clock-cells = <1>; + #reset-cells = <1>; + qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>; + }; + + clock_scc: qcom,scc@62b10000 { + compatible = "qcom,scc-sm6150"; + reg = <0x62b10000 0x30000>; + vdd_scc_cx-supply = <&VDD_CX_LEVEL>; + #clock-cells = <1>; + status = "disabled"; + }; + + cpucc_debug: syscon@182a0018 { + compatible = "syscon"; + reg = <0x182a0018 0x4>; + }; + + mccc_debug: syscon@90b0000 { + compatible = "syscon"; + reg = <0x90b0000 0x1000>; + }; + + clock_cpucc: qcom,cpucc@18321000 { + compatible = "qcom,clk-cpu-osm-sm6150"; + reg = <0x18321000 0x1400>, + <0x18323000 0x1400>, + <0x18325800 0x1400>; + reg-names = "osm_l3_base", "osm_pwrcl_base", + "osm_perfcl_base"; + l3-devs = <&cpu0_cpu_l3_lat &cpu6_cpu_l3_lat + &cdsp_cdsp_l3_lat &msm_gpu>; + #clock-cells = <1>; + }; + + clock_debugcc: qcom,cc-debug { + compatible = "qcom,debugcc-sm6150"; + qcom,gcc = <&clock_gcc>; + qcom,videocc = <&clock_videocc>; + qcom,camcc = <&clock_camcc>; + qcom,dispcc = <&clock_dispcc>; + qcom,gpucc = <&clock_gpucc>; + qcom,cpucc = <&cpucc_debug>; + qcom,mccc = <&mccc_debug>; + clock-names = "cxo"; + clocks = <&clock_rpmh RPMH_CXO_CLK>; + #clock-cells = <1>; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = <1 5 4>; + }; + + dsu_pmu@0 { + compatible = "arm,dsu-pmu"; + interrupts = ; + cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, + <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>; + }; + + qcom,msm-imem@146aa000 { + compatible = "qcom,msm-imem"; + reg = <0x146aa000 0x1000>; + ranges = <0x0 0x146aa000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 32>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 12>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 200>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 200>; + }; + }; + + restart@c264000 { + compatible = "qcom,pshold"; + reg = <0xc264000 0x4>, + <0x1fd3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + qcom,mpm2-sleep-counter@0xc221000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xc221000 0x1000>; + clock-frequency = <32768>; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + + gpi_dma0: qcom,gpi-dma@0x800000 { + #dma-cells = <5>; + compatible = "qcom,gpi-dma"; + reg = <0x800000 0x60000>; + reg-names = "gpi-top"; + interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>, + <0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>; + qcom,ev-factor = <2>; + qcom,max-num-gpii = <8>; + qcom,gpii-mask = <0x0f>; + iommus = <&apps_smmu 0x00d6 0x0>; + qcom,smmu-cfg = <0x1>; + qcom,iova-range = <0x0 0x100000 0x0 0x100000>; + status = "ok"; + }; + + gpi_dma1: qcom,gpi-dma@0xa00000 { + #dma-cells = <5>; + compatible = "qcom,gpi-dma"; + reg = <0xa00000 0x60000>; + reg-names = "gpi-top"; + interrupts = <0 279 0>, <0 280 0>, <0 281 0>, <0 282 0>, + <0 283 0>, <0 284 0>, <0 293 0>, <0 294 0>; + qcom,ev-factor = <2>; + qcom,max-num-gpii = <8>; + qcom,gpii-mask = <0x0f>; + qcom,smmu-cfg = <0x1>; + qcom,iova-range = <0x0 0x100000 0x0 0x100000>; + iommus = <&apps_smmu 0x0376 0x0>; + status = "ok"; + }; + + aop-msg-client { + compatible = "qcom,debugfs-qmp-client"; + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + wdog: qcom,wdt@17c10000{ + compatible = "qcom,msm-watchdog"; + reg = <0x17c10000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 0 0>, <0 1 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + qcom,scandump-sizes = <0x10100 0x10100 0x10100 0x10100 + 0x10100 0x10100 0x25900 0x25900>; + }; + + qcom,chd_sliver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x18000058 0x18010058 + 0x18020058 0x18030058 + 0x18040058 0x18050058>; + qcom,config-arr = <0x18000060 0x18010060 + 0x18020060 0x18030060 + 0x18040060 0x18050060>; + }; + + qcom,chd_gold { + compatible = "qcom,core-hang-detect"; + label = "gold"; + qcom,threshold-arr = <0x18060058 0x18070058>; + qcom,config-arr = <0x18060060 0x18070060>; + }; + + kryo-erp { + compatible = "arm,arm64-kryo-cpu-erp"; + interrupts = <1 6 4>, + <0 35 4>; + + interrupt-names = "l1-l2-faultirq", + "l3-scu-faultirq"; + }; + + qcom,ghd { + compatible = "qcom,gladiator-hang-detect-v3"; + qcom,threshold-arr = <0x17e0041C>; + qcom,config-reg = <0x17e00434>; + }; + + cpuss_dump { + compatible = "qcom,cpuss-dump"; + + qcom,l1_i_cache0 { + qcom,dump-node = <&L1_I_0>; + qcom,dump-id = <0x60>; + }; + + qcom,l1_i_cache100 { + qcom,dump-node = <&L1_I_100>; + qcom,dump-id = <0x61>; + }; + + qcom,l1_i_cache200 { + qcom,dump-node = <&L1_I_200>; + qcom,dump-id = <0x62>; + }; + + qcom,l1_i_cache300 { + qcom,dump-node = <&L1_I_300>; + qcom,dump-id = <0x63>; + }; + + qcom,l1_i_cache400 { + qcom,dump-node = <&L1_I_400>; + qcom,dump-id = <0x64>; + }; + + qcom,l1_i_cache500 { + qcom,dump-node = <&L1_I_500>; + qcom,dump-id = <0x65>; + }; + + qcom,l1_i_cache600 { + qcom,dump-node = <&L1_I_600>; + qcom,dump-id = <0x66>; + }; + + qcom,l1_i_cache700 { + qcom,dump-node = <&L1_I_700>; + qcom,dump-id = <0x67>; + }; + + qcom,l1_d_cache0 { + qcom,dump-node = <&L1_D_0>; + qcom,dump-id = <0x80>; + }; + + qcom,l1_d_cache100 { + qcom,dump-node = <&L1_D_100>; + qcom,dump-id = <0x81>; + }; + + qcom,l1_d_cache200 { + qcom,dump-node = <&L1_D_200>; + qcom,dump-id = <0x82>; + }; + + qcom,l1_d_cache300 { + qcom,dump-node = <&L1_D_300>; + qcom,dump-id = <0x83>; + }; + + qcom,l1_d_cache400 { + qcom,dump-node = <&L1_D_400>; + qcom,dump-id = <0x84>; + }; + + qcom,l1_d_cache500 { + qcom,dump-node = <&L1_D_500>; + qcom,dump-id = <0x85>; + }; + + qcom,l1_d_cache600 { + qcom,dump-node = <&L1_D_600>; + qcom,dump-id = <0x86>; + }; + + qcom,l1_d_cache700 { + qcom,dump-node = <&L1_D_700>; + qcom,dump-id = <0x87>; + }; + + qcom,l1_i_tlb_dump600 { + qcom,dump-node = <&L1_ITLB_600>; + qcom,dump-id = <0x26>; + }; + + qcom,l1_i_tlb_dump700 { + qcom,dump-node = <&L1_ITLB_700>; + qcom,dump-id = <0x27>; + }; + + qcom,l1_d_tlb_dump600 { + qcom,dump-node = <&L1_DTLB_600>; + qcom,dump-id = <0x46>; + }; + + qcom,l1_d_tlb_dump700 { + qcom,dump-node = <&L1_DTLB_700>; + qcom,dump-id = <0x47>; + }; + + qcom,l2_cache_dump600 { + qcom,dump-node = <&L2_600>; + qcom,dump-id = <0xc6>; + }; + + qcom,l2_cache_dump700 { + qcom,dump-node = <&L2_700>; + qcom,dump-id = <0xc7>; + }; + + qcom,l2_tlb_dump0 { + qcom,dump-node = <&L2_TLB_0>; + qcom,dump-id = <0x120>; + }; + + qcom,l2_tlb_dump100 { + qcom,dump-node = <&L2_TLB_100>; + qcom,dump-id = <0x121>; + }; + + qcom,l2_tlb_dump200 { + qcom,dump-node = <&L2_TLB_200>; + qcom,dump-id = <0x122>; + }; + + qcom,l2_tlb_dump300 { + qcom,dump-node = <&L2_TLB_300>; + qcom,dump-id = <0x123>; + }; + + qcom,l2_tlb_dump400 { + qcom,dump-node = <&L2_TLB_400>; + qcom,dump-id = <0x124>; + }; + + qcom,l2_tlb_dump500 { + qcom,dump-node = <&L2_TLB_500>; + qcom,dump-id = <0x125>; + }; + + qcom,l2_tlb_dump600 { + qcom,dump-node = <&L2_TLB_600>; + qcom,dump-id = <0x126>; + }; + + qcom,l2_tlb_dump700 { + qcom,dump-node = <&L2_TLB_700>; + qcom,dump-id = <0x127>; + }; + + qcom,llcc1_d_cache { + qcom,dump-node = <&LLCC_1>; + qcom,dump-id = <0x140>; + }; + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + rpmh { + qcom,dump-size = <0x2000000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + tmc_etf { + qcom,dump-size = <0x8000>; + qcom,dump-id = <0xf0>; + }; + + etf_swao { + qcom,dump-size = <0x8000>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etf_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x101>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + }; + + apps_rsc: mailbox@18220000 { + compatible = "qcom,tcs-drv"; + label = "apps_rsc"; + reg = <0x18220000 0x100>, <0x18220d00 0x3000>; + interrupts = <0 5 0>; + #mbox-cells = <1>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + }; + + disp_rsc: mailbox@af20000 { + compatible = "qcom,tcs-drv"; + label = "display_rsc"; + reg = <0xaf20000 0x100>, <0xaf21c00 0x3000>; + interrupts = <0 129 0>; + #mbox-cells = <1>; + qcom,drv-id = <0>; + qcom,tcs-config = , + , + , + ; + }; + + system_pm { + compatible = "qcom,system-pm"; + mboxes = <&apps_rsc 0>; + }; + + cmd_db: qcom,cmd-db@c3f000c { + compatible = "qcom,cmd-db"; + reg = <0xc3f000c 8>; + }; + + dcc: dcc_v2@10a2000 { + compatible = "qcom,dcc-v2"; + reg = <0x10a2000 0x1000>, + <0x10ae000 0x2000>; + reg-names = "dcc-base", "dcc-ram-base"; + + dcc-ram-offset = <0x6000>; + }; + + qcom,llcc@9200000 { + compatible = "qcom,llcc-core", "syscon", "simple-mfd"; + reg = <0x9200000 0x450000>; + reg-names = "llcc_base"; + qcom,llcc-banks-off = <0x0>; + qcom,llcc-broadcast-off = <0x400000>; + + llcc: qcom,sm6150-llcc { + compatible = "qcom,sm6150-llcc"; + #cache-cells = <1>; + max-slices = <32>; + cap-based-alloc-and-pwr-collapse; + }; + + qcom,llcc-perfmon { + compatible = "qcom,llcc-perfmon"; + clocks = <&clock_aop QDSS_CLK>; + clock-names = "qdss_clk"; + }; + + qcom,llcc-erp { + compatible = "qcom,llcc-erp"; + }; + + qcom,llcc-amon { + compatible = "qcom,llcc-amon"; + }; + + LLCC_1: llcc_1_dcache { + qcom,dump-size = <0x6c000>; + }; + }; + + sdcc1_ice: sdcc1ice@7C8000{ + compatible = "qcom,ice"; + reg = <0x7C8000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ice_core_clk_src", "ice_core_clk", + "bus_clk", "iface_clk"; + clocks = <&clock_gcc GCC_SDCC1_ICE_CORE_CLK_SRC>, + <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>, + <&clock_gcc GCC_SDCC1_AHB_CLK>, + <&clock_gcc GCC_SDCC1_APPS_CLK>; + qcom,op-freq-hz = <300000000>, <0>, <0>, <0>; + qcom,msm-bus,name = "sdcc_ice_noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 757 0 0>, /* No vote */ + <1 757 1000 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "sdcc"; + }; + + sdhc_1: sdhci@7c4000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>; + reg-names = "hc_mem", "cmdq_mem"; + + interrupts = <0 641 0>, <0 644 0>; + interrupt-names = "hc_irq", "pwr_irq"; + sdhc-msm-crypto = <&sdcc1_ice>; + + qcom,bus-width = <8>; + qcom,large-address-bus; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 + 192000000 384000000>; + qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; + + qcom,devfreq,freq-table = <50000000 200000000>; + + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <9>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <78 512 0 0>, <1 606 0 0>, + /* 400 KB/s*/ + <78 512 1046 1600>, + <1 606 1600 1600>, + /* 20 MB/s */ + <78 512 52286 80000>, + <1 606 80000 80000>, + /* 25 MB/s */ + <78 512 65360 100000>, + <1 606 100000 100000>, + /* 50 MB/s */ + <78 512 130718 200000>, + <1 606 133320 133320>, + /* 100 MB/s */ + <78 512 130718 200000>, + <1 606 150000 150000>, + /* 200 MB/s */ + <78 512 261438 400000>, + <1 606 300000 300000>, + /* 400 MB/s */ + <78 512 261438 2718822>, + <1 606 300000 1359411>, + /* Max. bandwidth */ + <78 512 1338562 4096000>, + <1 606 1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100750000 200000000 400000000 4294967295>; + + /* PM QoS */ + qcom,pm-qos-irq-type = "affine_irq"; + qcom,pm-qos-irq-latency = <67 67>; + qcom,pm-qos-cpu-groups = <0x3f 0xc0>; + qcom,pm-qos-cmdq-latency-us = <67 67>, <67 67>; + qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>; + + clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, + <&clock_gcc GCC_SDCC1_APPS_CLK>, + <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface_clk", "core_clk", "ice_core_clk"; + + qcom,ice-clk-rates = <300000000 75000000>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x000F642C 0x0 0x0 0x00010800 0x80040868>; + + qcom,nonremovable; + status = "disabled"; + }; + + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x8804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = <0 204 0>, <0 222 0>; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <4>; + qcom,large-address-bus; + + qcom,clk-rates = <400000 20000000 25000000 + 50000000 100000000 202000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", + "SDR104"; + + qcom,devfreq,freq-table = <50000000 202000000>; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <81 512 0 0>, <1 608 0 0>, + /* 400 KB/s*/ + <81 512 1046 1600>, + <1 608 1600 1600>, + /* 20 MB/s */ + <81 512 52286 80000>, + <1 608 80000 80000>, + /* 25 MB/s */ + <81 512 65360 100000>, + <1 608 100000 100000>, + /* 50 MB/s */ + <81 512 130718 200000>, + <1 608 133320 133320>, + /* 100 MB/s */ + <81 512 261438 200000>, + <1 608 150000 150000>, + /* 200 MB/s */ + <81 512 261438 400000>, + <1 608 300000 300000>, + /* Max. bandwidth */ + <81 512 1338562 4096000>, + <1 608 1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100750000 200000000 4294967295>; + + /* PM QoS */ + qcom,pm-qos-irq-type = "affine_irq"; + qcom,pm-qos-irq-latency = <67 67>; + qcom,pm-qos-cpu-groups = <0x3f 0xc0>; + qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>; + + clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>, + <&clock_gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface_clk", "core_clk"; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642C 0x0 0x0 0x00010800 0x80040868>; + + status = "disabled"; + }; + + qcom_seecom: qseecom@86d00000 { + compatible = "qcom,qseecom"; + reg = <0x86d00000 0xe00000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,no-clock-support; + qcom,fde-key-size; + qcom,appsbl-qseecom-support; + qcom,commonlib64-loaded-by-uefi; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_smcinvoke: smcinvoke@86d00000 { + compatible = "qcom,smcinvoke"; + reg = <0x86d00000 0xe00000>; + reg-names = "secapp-region"; + }; + + qcom_rng: qrng@793000 { + compatible = "qcom,msm-rng"; + reg = <0x793000 0x1000>; + qcom,msm-rng-iface-clk; + qcom,no-qrng-config; + qcom,msm-bus,name = "msm-rng-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 618 0 0>, /* No vote */ + <1 618 0 300000>; /* 75 MHz */ + clocks = <&clock_gcc GCC_PRNG_AHB_CLK>; + clock-names = "iface_clk"; + }; + + ufs_ice: ufsice@1d90000 { + compatible = "qcom,ice"; + reg = <0x1d90000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk", "bus_clk", + "iface_clk", "ice_core_clk"; + clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>, + <&clock_gcc GCC_UFS_PHY_AHB_CLK>, + <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>; + qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; + vdd-hba-supply = <&ufs_phy_gdsc>; + qcom,msm-bus,name = "ufs_ice_noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 650 0 0>, /* No vote */ + <1 650 1000 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "ufs"; + }; + + ufsphy_mem: ufsphy_mem@1d87000 { + reg = <0x1d87000 0xdb8>; /* PHY regs */ + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <1>; + + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>, + <&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x3000>; + interrupts = <0 265 0>; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + ufs-qcom-crypto = <&ufs_ice>; + + lanes-per-direction = <1>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + spm-level = <5>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks = + <&clock_gcc GCC_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_UFS_PHY_AHB_CLK>, + <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + + qcom,msm-bus,name = "ufshc_mem"; + qcom,msm-bus,num-cases = <12>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <123 512 0 0>, <1 757 0 0>, /* No vote */ + <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */ + <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */ + <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */ + <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */ + <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */ + <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */ + <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */ + <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */ + <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */ + <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */ + <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", + "MAX"; + + /* PM QoS */ + qcom,pm-qos-cpu-groups = <0x3f 0xC0>; + qcom,pm-qos-cpu-group-latency-us = <67 67>; + qcom,pm-qos-default-cpu = <0>; + + pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; + pinctrl-0 = <&ufs_dev_reset_assert>; + pinctrl-1 = <&ufs_dev_reset_deassert>; + + resets = <&clock_gcc GCC_UFS_PHY_BCR>; + reset-names = "core_reset"; + non-removable; + + status = "disabled"; + }; + + qcom_cedev: qcedev@1de0000 { + compatible = "qcom,qcedev"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 272 0>; + qcom,bam-pipe-pair = <3>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,bam-ee = <0>; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <125 512 0 0>, + <125 512 393600 393600>; + qcom,smmu-s1-enable; + qcom,no-clock-support; + iommus = <&apps_smmu 0x0106 0x0011>, + <&apps_smmu 0x0116 0x0011>; + }; + + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; + + qcom_crypto: qcrypto@1de0000 { + compatible = "qcom,qcrypto"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 272 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + qcom,clk-mgmt-sus-res; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <125 512 0 0>, + <125 512 393600 393600>; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-aead-algo; + qcom,use-sw-hmac-algo; + qcom,smmu-s1-enable; + qcom,no-clock-support; + iommus = <&apps_smmu 0x0104 0x0011>, + <&apps_smmu 0x0114 0x0011>; + }; + + qcom_tzlog: tz-log@146aa720 { + compatible = "qcom,tz-log"; + reg = <0x146aa720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + + spmi_bus: qcom,spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0x1100>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>, + <0xe700000 0xa0000>, + <0xc40a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-core-supply = <&pm6150l_l1>; + qca,bt-vdd-pa-supply = <&pm6150l_l2>; + qca,bt-vdd-ldo-supply = <&pm6150l_l10>; + + qca,bt-vdd-core-voltage-level = <1800000 1900000>; + qca,bt-vdd-pa-voltage-level = <1304000 1370000>; + qca,bt-vdd-ldo-voltage-level = <3312000 3400000>; + + qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ + }; + + eud: qcom,msm-eud@88e0000 { + compatible = "qcom,msm-eud"; + interrupt-names = "eud_irq"; + interrupts = ; + reg = <0x88e0000 0x2000>, + <0x88e4000 0x1000>; + reg-names = "eud_base", "eud_mode_mgr2"; + qcom,secure-eud-en; + qcom,eud-clock-vote-req; + clocks = <&clock_gcc GCC_AHB2PHY_WEST_CLK>; + clock-names = "eud_ahb2phy_clk"; + status = "ok"; + }; + + slim_aud: slim@62dc0000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0x62dc0000 0x2c000>, + <0x62d84000 0x2a000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 163 0>, <0 164 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x7c0000>; + qcom,ea-pc = <0x2f0>; + status = "disabled"; + qcom,iommu-s1-bypass; + + iommu_slim_aud_ctrl_cb: qcom,iommu_slim_ctrl_cb { + compatible = "qcom,iommu-slim-ctrl-cb"; + iommus = <&apps_smmu 0x17e6 0x0>, + <&apps_smmu 0x17ed 0x0>, + <&apps_smmu 0x17ee 0x1>, + <&apps_smmu 0x17f0 0x1>; + }; + + }; + + slim_qca: slim@62e40000 { + cell-index = <3>; + compatible = "qcom,slim-ngd"; + reg = <0x62e40000 0x2c000>, + <0x62e04000 0x20000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 291 0>, <0 292 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + status = "ok"; + qcom,iommu-s1-bypass; + + iommu_slim_qca_ctrl_cb: qcom,iommu_slim_ctrl_cb { + compatible = "qcom,iommu-slim-ctrl-cb"; + iommus = <&apps_smmu 0x17f3 0x0>; + }; + + /* Slimbus Slave DT for WCN3990 */ + btfmslim_codec: wcn3990 { + compatible = "qcom,btfmslim_slave"; + elemental-addr = [00 01 20 02 17 02]; + qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; + qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; + }; + }; + + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 3>; + }; + + apcs: syscon@17c0000c { + compatible = "syscon"; + reg = <0x17c0000c 0x4>; + }; + + apcs_glb: mailbox@17c00000 { + compatible = "qcom,sm8150-apcs-hmss-global"; + reg = <0x17c00000 0x1000>; + + #mbox-cells = <1>; + }; + + qcom,msm-cdsp-loader { + compatible = "qcom,cdsp-loader"; + qcom,proc-img-to-load = "cdsp"; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + restrict-access; + }; + + qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,rpc-latency-us = <611>; + qcom,adsp-remoteheap-vmid = <22 37>; + qcom,fastrpc-adsp-audio-pdr; + qcom,fastrpc-adsp-sensors-pdr; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1081 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1082 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1083 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1084 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1085 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1086 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb9 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x1089 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb10 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1723 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb11 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1724 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb12 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1725 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb13 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1726 0x0>; + shared-cb = <5>; + dma-coherent; + }; + }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_modem: modem { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&apcs_glb 12>; + mbox-names = "mpss_smem"; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 0x2>; + }; + + qcom,modem_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>, + <&glink_cdsp>; + }; + }; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&apcs_glb 24>; + mbox-names = "adsp_smem"; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,apr_tal_rpmsg { + qcom,glink-channels = "apr_audio_svc"; + qcom,intents = <0x200 20>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,adsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_cdsp>; + }; + }; + + glink_cdsp: cdsp { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&apcs_glb 4>; + mbox-names = "cdsp_smem"; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12>; + + qcom,cdsp-cdsp-l3-gov { + compatible = "qcom,cdsp-l3"; + qcom,target-dev = <&cdsp_cdsp_l3_lat>; + }; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-latency-us = <44>; + qcom,qos-maxhold-ms = <20>; + #cooling-cells = <2>; + }; + + msm_hvx_rm: qcom,msm_hvx_rm { + compatible = "qcom,msm-hvx-rm"; + #cooling-cells = <2>; + }; + }; + + qcom,cdsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>; + }; + }; + + glink_spi_xprt_wdsp: wdsp { + qcom,remote-pid = <10>; + transport = "spi"; + tx-descriptors = <0x12000 0x12004>; + rx-descriptors = <0x1200c 0x12010>; + + label = "wdsp"; + qcom,glink-label = "wdsp"; + + qcom,wdsp_ctrl { + qcom,glink-channels = "g_glink_ctrl"; + qcom,intents = <0x400 1>; + }; + + qcom,wdsp_ild { + qcom,glink-channels = + "g_glink_persistent_data_ild"; + }; + + qcom,wdsp_nild { + qcom,glink-channels = + "g_glink_persistent_data_nild"; + }; + + qcom,wdsp_data { + qcom,glink-channels = "g_glink_audio_data"; + qcom,intents = <0x1000 2>; + }; + + qcom,diag_data { + qcom,glink-channels = "DIAG_DATA"; + qcom,intents = <0x4000 2>; + }; + + qcom,diag_ctrl { + qcom,glink-channels = "DIAG_CTRL"; + qcom,intents = <0x4000 1>; + }; + + qcom,diag_cmd { + qcom,glink-channels = "DIAG_CMD"; + qcom,intents = <0x4000 1 >; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qmp_aop: qcom,qmp-aop@c300000 { + compatible = "qcom,qmp-mbox"; + reg = <0xc300000 0x1000>, <0x17c0000C 0x4>; + reg-names = "msgram", "irq-reg-base"; + qcom,irq-mask = <0x1>; + interrupts = ; + + label = "aop"; + qcom,early-boot; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + interrupt-parent = <&sleepstate_smp2p_in>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + qcom,ipc = <&apcs 0 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = ; + qcom,ipc = <&apcs 0 26>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + qcom,smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts = ; + qcom,ipc = <&apcs 0 6>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + thermal_zones: thermal-zones {}; + + tsens0: tsens@c222000 { + compatible = "qcom,sm6150-tsens"; + reg = <0xc222000 0x8>, + <0xc263000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts = <0 506 0>, <0 508 0>; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + #thermal-sensor-cells = <1>; + }; + + qcom,lpass@62400000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x62400000 0x00100>; + + vdd_cx-supply = <&L8A_LEVEL>; + qcom,vdd_cx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx"; + + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <1>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,sysmon-id = <1>; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + + /* Inputs from lpass */ + interrupts-extended = <&pdc 0 162 1>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "adsp-pil"; + }; + + pil_modem: qcom,mss@4080000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x4080000 0x100>; + + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + vdd_mss-supply = <&VDD_MSS_LEVEL>; + qcom,vdd_mss-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx", "vdd_mss"; + + qcom,firmware-name = "modem"; + memory-region = <&pil_modem_mem>; + qcom,proxy-timeout-ms = <10000>; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x12>; + qcom,pas-id = <4>; + qcom,smem-id = <421>; + qcom,signal-aop; + qcom,minidump-id = <3>; + qcom,complete-ramdump; + + /* Inputs from mss */ + interrupts-extended = <&pdc 0 266 1>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "mss-pil"; + }; + + qcom,turing@8300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x8300000 0x100000>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <18>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <601>; + qcom,sysmon-id = <7>; + qcom,ssctl-instance-id = <0x17>; + qcom,firmware-name = "cdsp"; + memory-region = <&pil_cdsp_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + + /* Inputs from turing */ + interrupts-extended = <&pdc 0 578 1>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "cdsp-pil"; + }; + + qcom,venus@aae0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xaae0000 0x4000>; + + vdd-supply = <&venus_gdsc>; + qcom,proxy-reg-names = "vdd"; + + clocks = <&clock_videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, + <&clock_videocc VIDEO_CC_VENUS_AHB_CLK>, + <&clock_videocc VIDEO_CC_VENUS_CTL_AXI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_clk"; + qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk"; + + qcom,pas-id = <9>; + qcom,msm-bus,name = "pil-venus"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <63 512 0 0>, + <63 512 0 304000>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&pil_video_mem>; + }; + + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + qcom,ipa-platform-type-msm; + qcom,ipa-advertise-sg-support; + qcom,ipa-napi-enable; + }; + + ipa_hw: qcom,ipa@1e00000 { + compatible = "qcom,ipa"; + reg = <0x1e00000 0x34000>, + <0x1e04000 0x2c000>; + reg-names = "ipa-base", "gsi-base"; + interrupts = <0 311 0>, <0 432 0>; + interrupt-names = "ipa-irq", "gsi-irq"; + qcom,ipa-hw-ver = <16>; /* IPA core version = IPAv4.2 */ + qcom,ipa-hw-mode = <0>; + qcom,ee = <0>; + qcom,use-ipa-tethering-bridge; + qcom,modem-cfg-emb-pipe-flt; + qcom,ipa-wdi2; + qcom,ipa-wdi2_over_gsi; + qcom,ipa-fltrt-not-hashable; + qcom,use-64-bit-dma-mask; + qcom,arm-smmu; + qcom,smmu-fast-map; + qcom,use-ipa-pm; + qcom,bandwidth-vote-for-ipa; + qcom,ipa-endp-delay-wa; + qcom,msm-bus,name = "ipa"; + qcom,msm-bus,num-cases = <5>; + qcom,msm-bus,num-paths = <4>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + , + , + , + , + /* SVS2 */ + , + , + , + , + /* SVS */ + , + , + , + , + /* NOMINAL */ + , + , + , + , + /* TURBO */ + , + , + , + ; + qcom,bus-vector-names = + "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; + qcom,throughput-threshold = <310 600 1000>; + qcom,scaling-exceptions = <>; + + /* smp2p information */ + qcom,smp2p_map_ipa_1_out { + compatible = "qcom,smp2p-map-ipa-1-out"; + qcom,smem-states = <&smp2p_ipa_1_out 0>; + qcom,smem-state-names = "ipa-smp2p-out"; + }; + + qcom,smp2p_map_ipa_1_in { + compatible = "qcom,smp2p-map-ipa-1-in"; + interrupts-extended = <&smp2p_ipa_1_in 0 0>; + interrupt-names = "ipa-smp2p-in"; + }; + }; + + ipa_smmu_ap: ipa_smmu_ap { + compatible = "qcom,ipa-smmu-ap-cb"; + qcom,smmu-s1-bypass; + iommus = <&apps_smmu 0x1520 0x0>; + qcom,iova-mapping = <0x20000000 0x40000000>; + /* modem tables in IMEM */ + qcom,additional-mapping = <0x146A8000 0x146A8000 0x2000>; + }; + + ipa_smmu_wlan: ipa_smmu_wlan { + compatible = "qcom,ipa-smmu-wlan-cb"; + qcom,smmu-s1-bypass; + iommus = <&apps_smmu 0x1521 0x0>; + /* ipa-uc ram */ + qcom,additional-mapping = <0x1e60000 0x1e60000 0x80000>; + }; + + ipa_smmu_uc: ipa_smmu_uc { + compatible = "qcom,ipa-smmu-uc-cb"; + qcom,smmu-s1-bypass; + iommus = <&apps_smmu 0x1522 0x0>; + qcom,iova-mapping = <0x40400000 0x1fc00000>; + }; + + qcom,ipa_fws { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0xf>; + qcom,firmware-name = "ipa_fws"; + qcom,pil-force-shutdown; + memory-region = <&pil_ipa_fw_mem>; + }; + + icnss: qcom,icnss@18800000 { + compatible = "qcom,icnss"; + reg = <0x18800000 0x800000>, + <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa"; + iommus = <&apps_smmu 0x1640 0x1>; + interrupts = <0 414 0 /* CE0 */ >, + <0 415 0 /* CE1 */ >, + <0 416 0 /* CE2 */ >, + <0 417 0 /* CE3 */ >, + <0 418 0 /* CE4 */ >, + <0 419 0 /* CE5 */ >, + <0 420 0 /* CE6 */ >, + <0 421 0 /* CE7 */ >, + <0 422 0 /* CE8 */ >, + <0 423 0 /* CE9 */ >, + <0 424 0 /* CE10 */ >, + <0 425 0 /* CE11 */ >; + qcom,smmu-s1-bypass; + qcom,wlan-msa-memory = <0x100000>; + qcom,wlan-msa-fixed-region = <&wlan_msa_mem>; + vdd-cx-mx-supply = <&pm6150_l9>; + vdd-1.8-xo-supply = <&pm6150l_l1>; + vdd-1.3-rfa-supply = <&pm6150l_l2>; + vdd-3.3-ch0-supply = <&pm6150l_l10>; + qcom,vdd-cx-mx-config = <640000 640000>; + qcom,smp2p_map_wlan_1_in { + interrupts-extended = <&smp2p_wlan_1_in 0 0>, + <&smp2p_wlan_1_in 1 0>; + interrupt-names = "qcom,smp2p-force-fatal-error", + "qcom,smp2p-early-crash-ind"; + }; + + }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x200000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + qcom,guard-memory; + }; + + llcc_pmu: llcc-pmu@90cc000 { + compatible = "qcom,qcom-llcc-pmu"; + reg = <0x090cc000 0x300>; + reg-names = "lagg-base"; + }; + + llcc_bw_opp_table: llcc-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ + BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */ + BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */ + BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */ + BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */ + BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */ + }; + + cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x90b6300 0x300>, <0x90b6200 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_cpu_llcc_bw>; + qcom,count-unit = <0x10000>; + }; + + ddr_bw_opp_table: ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ + BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ + BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ + BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ + BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ + BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ + BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ + BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */ + BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ + BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ + }; + + cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@90cd000 { + compatible = "qcom,bimc-bwmon5"; + reg = <0x90cd000 0x1000>; + reg-names = "base"; + interrupts = ; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_llcc_ddr_bw>; + qcom,count-unit = <0x10000>; + }; + + suspendable_ddr_bw_opp_table: suspendable-ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 0, 4); /* 0 MB/s */ + BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ + BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ + BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ + BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ + BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ + BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ + BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ + BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */ + BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ + BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ + }; + + cdsp_cdsp_l3_lat: qcom,cdsp-cdsp-l3-lat { + compatible = "devfreq-simple-dev"; + clock-names = "devfreq_clk"; + clocks = <&clock_cpucc L3_MISC_VOTE_CLK>; + governor = "powersave"; + }; + + cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { + compatible = "devfreq-simple-dev"; + clock-names = "devfreq_clk"; + clocks = <&clock_cpucc L3_CLUSTER0_VOTE_CLK>; + governor = "performance"; + }; + + cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,target-dev = <&cpu0_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,stall-cycle-ev = <0xE7>; + qcom,core-dev-table = + < 576000 300000000 >, + < 1017600 556800000 >, + < 1209660 806400000 >, + < 1516800 940800000 >, + < 1804800 1363200000 >; + }; + + cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat { + compatible = "devfreq-simple-dev"; + clock-names = "devfreq_clk"; + clocks = <&clock_cpucc L3_CLUSTER1_VOTE_CLK>; + governor = "performance"; + }; + + cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,target-dev = <&cpu6_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,stall-cycle-ev = <0x15E>; + qcom,core-dev-table = + < 1017600 556800000 >, + < 1209600 806400000 >, + < 1516800 940800000 >, + < 1708800 1209600000 >, + < 2208000 1363200000 >; + }; + + cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,target-dev = <&cpu0_cpu_llcc_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,stall-cycle-ev = <0xE7>; + qcom,core-dev-table = + < 748000 MHZ_TO_MBPS(150, 16) >, + < 1209600 MHZ_TO_MBPS(300, 16) >, + < 1516800 MHZ_TO_MBPS(466, 16) >, + < 1804800 MHZ_TO_MBPS(600, 16) >; + }; + + cpu6_cpu_llcc_lat: qcom,cpu6-cpu-llcc-lat { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu6_cpu_llcc_latmon: qcom,cpu6-cpu-llcc-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,target-dev = <&cpu6_cpu_llcc_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,stall-cycle-ev = <0x15E>; + qcom,core-dev-table = + < 768000 MHZ_TO_MBPS(300, 16) >, + < 1017600 MHZ_TO_MBPS(466, 16) >, + < 1209600 MHZ_TO_MBPS(600, 16) >, + < 1708800 MHZ_TO_MBPS(806, 16) >, + < 2208000 MHZ_TO_MBPS(933, 16) >; + }; + + cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,target-dev = <&cpu0_llcc_ddr_lat>; + qcom,cachemiss-ev = <0x1000>; + qcom,stall-cycle-ev = <0xE7>; + qcom,core-dev-table = + < 748000 MHZ_TO_MBPS( 300, 4) >, + < 1017600 MHZ_TO_MBPS( 451, 4) >, + < 1209600 MHZ_TO_MBPS( 547, 4) >, + < 1516800 MHZ_TO_MBPS( 768, 4) >, + < 1804800 MHZ_TO_MBPS(1017, 4) >; + }; + + cpu6_llcc_ddr_lat: qcom,cpu6-llcc-ddr-lat { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu6_llcc_ddr_latmon: qcom,cpu6-llcc-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,target-dev = <&cpu6_llcc_ddr_lat>; + qcom,cachemiss-ev = <0x1000>; + qcom,stall-cycle-ev = <0x15E>; + qcom,core-dev-table = + < 768000 MHZ_TO_MBPS( 451, 4) >, + < 1017600 MHZ_TO_MBPS( 547, 4) >, + < 1209600 MHZ_TO_MBPS(1017, 4) >, + < 1708800 MHZ_TO_MBPS(1555, 4) >, + < 2208000 MHZ_TO_MBPS(1804, 4) >; + }; + + cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_computemon: qcom,cpu0-computemon { + compatible = "qcom,arm-cpu-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; + qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 748800 MHZ_TO_MBPS( 300, 4) >, + < 1209600 MHZ_TO_MBPS( 451, 4) >, + < 1593600 MHZ_TO_MBPS( 547, 4) >, + < 1804800 MHZ_TO_MBPS( 768, 4) >; + }; + + cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu6_computemon: qcom,cpu6-computemon { + compatible = "qcom,arm-cpu-mon"; + qcom,cpulist = <&CPU6 &CPU7>; + qcom,target-dev = <&cpu6_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1017600 MHZ_TO_MBPS( 300, 4) >, + < 1209600 MHZ_TO_MBPS( 547, 4) >, + < 1516800 MHZ_TO_MBPS( 768, 4) >, + < 1708800 MHZ_TO_MBPS(1017, 4) >, + < 2208000 MHZ_TO_MBPS(1804, 4) >; + }; + + bus_proxy_client: qcom,bus_proxy_client { + compatible = "qcom,bus-proxy-client"; + qcom,msm-bus,name = "bus-proxy-client"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + qcom,msm-bus,active-only; + status = "ok"; + }; + + keepalive_opp_table: keepalive-opp-table { + compatible = "operating-points-v2"; + opp-1 { + opp-hz = /bits/ 64 < 1 >; + }; + }; + + snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <1 627>; + qcom,active-only; + status = "ok"; + operating-points-v2 = <&keepalive_opp_table>; + }; + + cx_ipeak_lm: cx_ipeak@01fed000 { + compatible = "qcom,cx-ipeak-v1"; + reg = <0x1fed000 0x28>; + }; + + demux { + compatible = "qcom,demux"; + }; +}; + +#include "pm6150.dtsi" +#include "pm6150l.dtsi" +#include "sm6150-pinctrl.dtsi" +#include "sm6150-slpi-pinctrl.dtsi" +#include "sm6150-regulator.dtsi" +#include "sm6150-pm.dtsi" +#include "sm6150-gdsc.dtsi" +#include "sm6150-qupv3.dtsi" +#include "sm6150-thermal.dtsi" +#include "sm6150-gpu.dtsi" +#include "sm6150-usb.dtsi" + +&usb0 { + extcon = <&pm6150_pdphy>, <&pm6150_charger>, <&eud>; +}; + +&pm6150_vadc { + sdm_therm { + reg = ; + label = "sdm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + smb1390_therm { + reg = ; + label = "smb1390_therm"; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm6150_adc_tm { + io-channels = <&pm6150_vadc ADC_XO_THERM_PU2>, + <&pm6150_vadc ADC_AMUX_THM2_PU2>, + <&pm6150_vadc ADC_AMUX_THM4_PU2>; + + /* Channel nodes */ + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + sdm_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm6150l_vadc { + emmc_ufs_therm { + reg = ; + label = "emmc_ufs_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + rf_pa0_therm { + reg = ; + label = "rf_pa0_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + rf_pa1_therm { + reg = ; + label = "rf_pa1_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + camera_flash_therm { + reg = ; + label = "camera_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + quiet_therm { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm6150l_adc_tm { + io-channels = <&pm6150l_vadc ADC_AMUX_THM1_PU2>, + <&pm6150l_vadc ADC_AMUX_THM2_PU2>, + <&pm6150l_vadc ADC_GPIO1_PU2>, + <&pm6150l_vadc ADC_GPIO4_PU2>; + + /* Channel nodes */ + emmc_ufs_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + rf_pa0_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + camera_flash_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + quiet_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&emac_gdsc { + status = "ok"; +}; + +&pcie_0_gdsc { + status = "ok"; +}; + +&ufs_phy_gdsc { + status = "ok"; +}; + +&usb30_prim_gdsc { + status = "ok"; +}; + +&usb20_sec_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu1_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu2_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { + status = "ok"; +}; + +&bps_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&ife_0_gdsc { + status = "ok"; +}; + +&ife_1_gdsc { + status = "ok"; +}; + +&ipe_0_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&titan_top_gdsc { + status = "ok"; +}; + +&mdss_core_gdsc { + status = "ok"; +}; + +&gpu_cx_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_gx_gdsc { + clock-names = "core_root_clk"; + clocks = <&clock_gpucc GPU_CC_GX_GFX3D_CLK_SRC>; + qcom,force-enable-root-clk; + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&vcodec0_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&venus_gdsc { + status = "ok"; +}; + +&qupv3_se3_i2c { + status = "ok"; + fsa4480: fsa4480@43 { + compatible = "qcom,fsa4480-i2c"; + reg = <0x43>; + pinctrl-names = "default"; + pinctrl-0 = <&fsa_usbc_ana_en>; + }; +}; + +#include "sm6150-camera.dtsi" +#include "sm6150-ion.dtsi" +#include "msm-arm-smmu-sm6150.dtsi" +#include "sm6150-coresight.dtsi" +#include "sm6150-bus.dtsi" +#include "sm6150-vidc.dtsi" +#include "sm6150-audio.dtsi" +#include "sm6150-sde-pll.dtsi" +#include "sm6150-sde.dtsi" +#include "msm-rdbg.dtsi" +&msm_vidc { + qcom,cx-ipeak-data = <&cx_ipeak_lm 4>; + qcom,clock-freq-threshold = <460000000>; +}; + +&msm_audio_ion { + qcom,iova-start-addr = <0x20000000>; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150p-idp-overlay.dts b/arch/arm/boot/dts/qcom/sm6150p-idp-overlay.dts new file mode 100644 index 000000000000..785daecf1983 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150p-idp-overlay.dts @@ -0,0 +1,31 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "sm6150-idp.dtsi" +#include "sm6150-audio-overlay.dtsi" + +/ { + model = "IDP"; + compatible = "qcom,sm6150p-idp", "qcom,sm6150p", "qcom,idp"; + qcom,msm-id = <369 0x0>; + qcom,board-id = <34 0>; +}; + +&dsi_hx83112a_truly_vid_display { + qcom,dsi-display-active; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150p-idp.dts b/arch/arm/boot/dts/qcom/sm6150p-idp.dts new file mode 100644 index 000000000000..142a15bb6284 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150p-idp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm6150p.dtsi" +#include "sm6150-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM6150P PM6150 IDP"; + compatible = "qcom,sm6150p-idp", "qcom,sm6150p", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150p-qrd-overlay.dts b/arch/arm/boot/dts/qcom/sm6150p-qrd-overlay.dts new file mode 100644 index 000000000000..70dd2979a05f --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150p-qrd-overlay.dts @@ -0,0 +1,26 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "sm6150-qrd.dtsi" + +/ { + model = "QRD"; + compatible = "qcom,sm6150p-qrd", "qcom,sm6150p", "qcom,qrd"; + qcom,board-id = <11 0>; + qcom,msm-id = <369 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150p-qrd.dts b/arch/arm/boot/dts/qcom/sm6150p-qrd.dts new file mode 100644 index 000000000000..7778ec4faddb --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150p-qrd.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm6150p.dtsi" +#include "sm6150-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM6150P PM6150 QRD"; + compatible = "qcom,sm6150p-qrd", "qcom,sm6150p", "qcom,qrd"; + qcom,board-id = <11 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150p.dts b/arch/arm/boot/dts/qcom/sm6150p.dts new file mode 100644 index 000000000000..9f3e09cd2941 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150p.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm6150p.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM6150P SoC"; + compatible = "qcom,sm6150p"; + qcom,pmic-name = "PM6150"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm6150p.dtsi b/arch/arm/boot/dts/qcom/sm6150p.dtsi new file mode 100644 index 000000000000..d4db14ce3a0f --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm6150p.dtsi @@ -0,0 +1,19 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm6150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM6150P"; + qcom,msm-name = "SM6150P"; + qcom,msm-id = <369 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/sm8150-audio-overlay.dtsi new file mode 100644 index 000000000000..980a8bf9763e --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-audio-overlay.dtsi @@ -0,0 +1,355 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm8150-wcd.dtsi" +#include "msm-wsa881x.dtsi" +#include + +&snd_9360 { + qcom,ext-disp-audio-rx = <1>; + qcom,wcn-btfm = <1>; + qcom,mi2s-audio-intf = <1>; + qcom,auxpcm-audio-intf = <1>; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; + + qcom,audio-routing = + "AIF4 VI", "MCLK", + "MADINPUT", "MCLK", + "LDO_RXTX", "MCLK", + "AMIC3", "MIC BIAS3", + "AMIC4", "MIC BIAS4", + "MIC BIAS3", "Handset Mic", + "MIC BIAS3", "Analog Mic3", + "MIC BIAS4", "Analog Mic4", + "DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "DMIC4", "MIC BIAS4", + "MIC BIAS4", "Digital Mic4", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT"; + + qcom,pahu-ext-clk-freq = <19200000>; + + asoc-codec = <&stub_codec>, <&ext_disp_audio_codec>; + asoc-codec-names = "msm-stub-codec.1", + "msm-ext-disp-audio-codec-rx"; + + qcom,wsa-max-devs = <1>; + qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>, + <&wsa881x_0213>, <&wsa881x_0214>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", + "SpkrLeft", "SpkrRight"; +}; + +&snd_934x { + qcom,ext-disp-audio-rx = <1>; + qcom,wcn-btfm = <1>; + qcom,mi2s-audio-intf = <1>; + qcom,auxpcm-audio-intf = <1>; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; + + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "hifi amp", "LINEOUT1", + "hifi amp", "LINEOUT2", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC3", "MIC BIAS2", + "MIC BIAS2", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2", + "MIC BIAS2", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS3", + "MIC BIAS3", "Handset Mic", + "DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "DMIC4", "MIC BIAS4", + "MIC BIAS4", "Digital Mic4", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT"; + + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,msm-mbhc-hs-mic-max-threshold-mv = <1700>; + qcom,msm-mbhc-hs-mic-min-threshold-mv = <50>; + qcom,hph-en0-gpio = <&tavil_hph_en0>; + qcom,hph-en1-gpio = <&tavil_hph_en1>; + qcom,tavil-mclk-clk-freq = <9600000>; + + asoc-codec = <&stub_codec>, <&ext_disp_audio_codec>; + asoc-codec-names = "msm-stub-codec.1", + "msm-ext-disp-audio-codec-rx"; + + qcom,wsa-max-devs = <2>; + qcom,wsa-devs = <&wsa881x_70211>, <&wsa881x_70212>, + <&wsa881x_70213>, <&wsa881x_70214>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", + "SpkrLeft", "SpkrRight"; +}; + +&soc { + wcd9xxx_intc: wcd9xxx-irq { + status = "ok"; + compatible = "qcom,wcd9xxx-irq"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&tlmm>; + qcom,gpio-connect = <&tlmm 123 0>; + pinctrl-names = "default"; + pinctrl-0 = <&wcd_intr_default>; + }; + + clock_audio: audio_ext_clk { + status = "ok"; + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = <2>; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <278>; + qcom,use-pinctrl = <1>; + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&quin_mi2s_mclk_active>; + pinctrl-1 = <&quin_mi2s_mclk_sleep>; + #clock-cells = <1>; + }; + + wcd_rst_gpio: msm_cdc_pinctrl@143 { + compatible = "qcom,msm-cdc-pinctrl"; + qcom,cdc-rst-n-gpio = <&tlmm 143 0>; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_reset_active>; + pinctrl-1 = <&cdc_reset_sleep>; + }; + + qocm,wcd-dsp-glink { + compatible = "qcom,wcd-dsp-glink"; + qcom,wdsp-channels = "g_glink_ctrl", + "g_glink_persistent_data_nild", + "g_glink_persistent_data_ild", + "g_glink_audio_data"; + }; + + pahu_wdsp: wcd-dsp-mgr@1 { + compatible = "qcom,wcd-dsp-mgr"; + qcom,wdsp-components = <&wcd9360_cdc 0>, + <&wcd_spi_0 1>, + <&glink_spi_xprt_wdsp 2>; + qcom,img-filename = "cpe_9360"; + }; + + tavil_wdsp: wcd-dsp-mgr@2 { + compatible = "qcom,wcd-dsp-mgr"; + qcom,wdsp-components = <&wcd934x_cdc 0>, + <&tavil_spi_0 1>, + <&glink_spi_xprt_wdsp 2>; + qcom,img-filename = "cpe_9340"; + }; + + clock_audio_lnbb: audio_ext_clk_lnbb { + status = "ok"; + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = <1>; + clock-names = "osr_clk"; + clocks = <&clock_rpmh RPMH_LN_BB_CLK2>; + #clock-cells = <1>; + }; +}; + +&slim_aud { + wcd9360_cdc: pahu_codec { + compatible = "qcom,pahu-slim-pgd"; + elemental-addr = [00 01 C0 02 17 02]; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 + 30 31>; + + qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; + + clock-names = "wcd_clk"; + clocks = <&clock_audio 0>; + + cdc-vdd-ldo-rxtx-supply = <&pm8150_s5>; + qcom,cdc-vdd-ldo-rxtx-voltage = <2040000 2040000>; + qcom,cdc-vdd-ldo-rxtx-current = <30000>; + + cdc-vdd-buck-sido-supply = <&pm8150_s4>; + qcom,cdc-vdd-buck-sido-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-sido-current = <228000>; + + cdc-vdd-px-supply = <&pm8150_s4>; + qcom,cdc-vdd-px-voltage = <1800000 1800000>; + qcom,cdc-vdd-px-current = <15000>; + + cdc-vdd-mic-bias-supply = <&pm8150l_bob>; + qcom,cdc-vdd-mic-bias-voltage = <3300000 3300000>; + qcom,cdc-vdd-mic-bias-current = <16800>; + + cdc-vdd-pa-supply = <&pm8150l_bob>; + qcom,cdc-vdd-pa-voltage = <3300000 3300000>; + qcom,cdc-vdd-pa-current = <1000000>; + + qcom,cdc-static-supplies = "cdc-vdd-buck-sido", + "cdc-vdd-px", + "cdc-vdd-mic-bias", + "cdc-vdd-pa"; + qcom,cdc-on-demand-supplies = "cdc-vdd-ldo-rxtx"; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; + + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-slim-ifd = "pahu-slim-ifd"; + qcom,cdc-slim-ifd-elemental-addr = [00 00 C0 02 17 02]; + qcom,cdc-dmic-sample-rate = <4800000>; + qcom,cdc-mad-dmic-rate = <600000>; + + qcom,wdsp-cmpnt-dev-name = "pahu_codec"; + + wcd_spi_0: wcd_spi { + compatible = "qcom,wcd-spi-v2"; + qcom,master-bus-num = <0>; + qcom,chip-select = <0>; + qcom,max-frequency = <24000000>; + qcom,mem-base-addr = <0x100000>; + }; + + }; + + wcd934x_cdc: tavil_codec { + compatible = "qcom,tavil-slim-pgd"; + elemental-addr = [00 01 50 02 17 02]; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 + 30 31>; + + qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; + + clock-names = "wcd_clk"; + clocks = <&clock_audio_lnbb 0>; + + cdc-vdd-buck-supply = <&pm8150_s4>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <650000>; + + cdc-buck-sido-supply = <&pm8150_s4>; + qcom,cdc-buck-sido-voltage = <1800000 1800000>; + qcom,cdc-buck-sido-current = <500000>; + + cdc-vdd-tx-h-supply = <&pm8150_s4>; + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-tx-h-current = <25000>; + + cdc-vdd-rx-h-supply = <&pm8150_s4>; + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-rx-h-current = <25000>; + + cdc-vddpx-1-supply = <&pm8150_s4>; + qcom,cdc-vddpx-1-voltage = <1800000 1800000>; + qcom,cdc-vddpx-1-current = <10000>; + + cdc-vdd-3v3-supply = <&pm8150l_bob>; + qcom,cdc-vdd-3v3-voltage = <3300000 3300000>; + qcom,cdc-vdd-3v3-current = <16800>; + + qcom,cdc-static-supplies = "cdc-vdd-buck", + "cdc-buck-sido", + "cdc-vdd-tx-h", + "cdc-vdd-rx-h", + "cdc-vddpx-1", + "cdc-vdd-3v3"; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; + + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-slim-ifd = "tavil-slim-ifd"; + qcom,cdc-slim-ifd-elemental-addr = [00 00 50 02 17 02]; + qcom,cdc-dmic-sample-rate = <4800000>; + qcom,cdc-mad-dmic-rate = <600000>; + + qcom,wdsp-cmpnt-dev-name = "tavil_codec"; + + tavil_spi_0: wcd_spi { + compatible = "qcom,wcd-spi-v2"; + qcom,master-bus-num = <0>; + qcom,chip-select = <0>; + qcom,max-frequency = <24000000>; + qcom,mem-base-addr = <0x100000>; + }; + }; +}; + +&qupv3_se4_i2c { + #address-cells = <1>; + #size-cells = <0>; + + aqt1000_cdc: aqt1000-i2c-codec@d { + status = "disabled"; + compatible = "qcom,aqt1000-i2c-codec"; + reg = <0x0d>; + + clock-names = "aqt_clk"; + clocks = <&clock_audio_lnbb>; + + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&tlmm>; + qcom,gpio-connect = <&tlmm 125 0>; + pinctrl-names = "default"; + pinctrl-0 = <&aqt_intr_default>; + + cdc-vdd-rxtx-supply = <&pm8150_s4>; + qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>; + qcom,cdc-vdd-rxtx-current = <33300>; + + cdc-vdd-buck-supply = <&pm8150_s4>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <650000>; + + cdc-vdd-vbat-supply = <&pm8150l_bob>; + qcom,cdc-vdd-vbat-voltage = <3300000 3300000>; + qcom,cdc-vdd-vbat-current = <5000>; + + qcom,cdc-static-supplies = "cdc-vdd-rxtx", + "cdc-vdd-buck", + "cdc-vdd-vbat"; + + qcom,cdc-ext-clk-rate = <19200000>; + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-micbias1-mv = <1800>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-audio.dtsi b/arch/arm/boot/dts/qcom/sm8150-audio.dtsi new file mode 100644 index 000000000000..a94883687fdf --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-audio.dtsi @@ -0,0 +1,183 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msm-audio-lpass.dtsi" + +&msm_audio_ion { + iommus = <&apps_smmu 0x1b21 0x0>; + qcom,smmu-sid-mask = /bits/ 64 <0xf>; +}; + +&soc { + qcom,avtimer@170f7000 { + compatible = "qcom,avtimer"; + reg = <0x170f700c 0x4>, + <0x170f7010 0x4>; + reg-names = "avtimer_lsb_addr", "avtimer_msb_addr"; + qcom,clk-div = <192>; + qcom,clk-mult = <10>; + }; +}; + +&audio_apr { + snd_9360: sound-pahu { + compatible = "qcom,sm8150-asoc-snd-pahu"; + qcom,model = "sm8150-pahu-snd-card"; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq"; + asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, + <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, + <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, + <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, <&sb_5_rx>, <&sb_6_rx>, + <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, + <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, + <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", + "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", + "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", + "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", + "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", + "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", + "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", + "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", + "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", + "msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36929"; + }; + + snd_934x: sound-tavil { + compatible = "qcom,sm8150-asoc-snd-tavil"; + qcom,model = "sm8150-tavil-snd-card"; + + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-compr-dsp", + "msm-pcm-dsp-noirq"; + asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, + <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, + <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, + <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, <&sb_5_rx>, <&sb_6_rx>, + <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, + <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, + <&dai_quat_tdm_rx_1>, + <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", + "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", + "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", + "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", + "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", + "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", + "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", + "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", + "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", + "msm-dai-q6-tdm.36914", + "msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36929"; + fsa4480-i2c-handle = <&fsa4480>; + }; +}; + +&qupv3_se4_i2c { + status = "ok"; + fsa4480: fsa4480@42 { + compatible = "qcom,fsa4480-i2c"; + reg = <0x42>; + pinctrl-names = "default"; + pinctrl-0 = <&fsa_usbc_ana_en>; + }; +}; + +&slim_aud { + msm_dai_slim { + compatible = "qcom,msm-dai-slim"; + elemental-addr = [ff ff ff fe 17 02]; + }; +}; + +&tdm_quat_rx { + qcom,msm-cpudai-tdm-group-num-ports = <2>; + qcom,msm-cpudai-tdm-group-port-id = <36912 36914>; + dai_quat_tdm_rx_1: qcom,msm-dai-q6-tdm-quat-rx-1 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36914>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-bus.dtsi b/arch/arm/boot/dts/qcom/sm8150-bus.dtsi new file mode 100644 index 000000000000..f419222d6fd5 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-bus.dtsi @@ -0,0 +1,2180 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + ad_hoc_bus: ad-hoc-bus { + compatible = "qcom,msm-bus-device"; + reg = <0x016E0000 0x40000>, + <0x1700000 0x40000>, + <0x1500000 0x40000>, + <0x14E0000 0x40000>, + <0x17900000 0x40000>, + <0x9680000 0x40000>, + <0x9680000 0x40000>, + <0x1740000 0x40000>, + <0x1620000 0x40000>, + <0x1620000 0x40000>, + <0x1620000 0x40000>, + <0x1700000 0x40000>; + + reg-names = "aggre1_noc-base", "aggre2_noc-base", + "config_noc-base", "dc_noc-base", + "gladiator_noc-base", "mc_virt-base", "gem_noc-base", + "mmss_noc-base", "system_noc-base", "ipa_virt-base", + "camnoc_virt-base", "compute_noc-base"; + + mbox-names = "apps_rsc", "disp_rsc"; + mboxes = <&apps_rsc 0 &disp_rsc 0>; + + /*RSCs*/ + rsc_apps: rsc-apps { + cell-id = ; + label = "apps_rsc"; + qcom,rsc-dev; + qcom,req_state = <2>; + }; + + rsc_disp: rsc-disp { + cell-id = ; + label = "disp_rsc"; + qcom,rsc-dev; + qcom,req_state = <2>; + }; + + /*BCMs*/ + bcm_acv: bcm-acv { + cell-id = ; + label = "ACV"; + qcom,bcm-name = "ACV"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_alc: bcm-alc { + cell-id = ; + label = "ALC"; + qcom,bcm-name = "ALC"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_mc0: bcm-mc0 { + cell-id = ; + label = "MC0"; + qcom,bcm-name = "MC0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sh0: bcm-sh0 { + cell-id = ; + label = "SH0"; + qcom,bcm-name = "SH0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_mm0: bcm-mm0 { + cell-id = ; + label = "MM0"; + qcom,bcm-name = "MM0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_mm1: bcm-mm1 { + cell-id = ; + label = "MM1"; + qcom,bcm-name = "MM1"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sh2: bcm-sh2 { + cell-id = ; + label = "SH2"; + qcom,bcm-name = "SH2"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_mm2: bcm-mm2 { + cell-id = ; + label = "MM2"; + qcom,bcm-name = "MM2"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sh3: bcm-sh3 { + cell-id = ; + label = "SH3"; + qcom,bcm-name = "SH3"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_mm3: bcm-mm3 { + cell-id = ; + label = "MM3"; + qcom,bcm-name = "MM3"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sh4: bcm-sh4 { + cell-id = ; + label = "SH4"; + qcom,bcm-name = "SH4"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sh5: bcm-sh5 { + cell-id = ; + label = "SH5"; + qcom,bcm-name = "SH5"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn0: bcm-sn0 { + cell-id = ; + label = "SN0"; + qcom,bcm-name = "SN0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_co0: bcm-co0 { + cell-id = ; + label = "CO0"; + qcom,bcm-name = "CO0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_ce0: bcm-ce0 { + cell-id = ; + label = "CE0"; + qcom,bcm-name = "CE0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn1: bcm-sn1 { + cell-id = ; + label = "SN1"; + qcom,bcm-name = "SN1"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_co1: bcm-co1 { + cell-id = ; + label = "CO1"; + qcom,bcm-name = "CO1"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_ip0: bcm-ip0 { + cell-id = ; + label = "IP0"; + qcom,bcm-name = "IP0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_cn0: bcm-cn0 { + cell-id = ; + label = "CN0"; + qcom,bcm-name = "CN0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_qup0: bcm-qup0 { + cell-id = ; + label = "QUP0"; + qcom,bcm-name = "QUP0"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn2: bcm-sn2 { + cell-id = ; + label = "SN2"; + qcom,bcm-name = "SN2"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn3: bcm-sn3 { + cell-id = ; + label = "SN3"; + qcom,bcm-name = "SN3"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn4: bcm-sn4 { + cell-id = ; + label = "SN4"; + qcom,bcm-name = "SN4"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn5: bcm-sn5 { + cell-id = ; + label = "SN5"; + qcom,bcm-name = "SN5"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn8: bcm-sn8 { + cell-id = ; + label = "SN8"; + qcom,bcm-name = "SN8"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn9: bcm-sn9 { + cell-id = ; + label = "SN9"; + qcom,bcm-name = "SN9"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn11: bcm-sn11 { + cell-id = ; + label = "SN11"; + qcom,bcm-name = "SN11"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn12: bcm-sn12 { + cell-id = ; + label = "SN12"; + qcom,bcm-name = "SN12"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn14: bcm-sn14 { + cell-id = ; + label = "SN14"; + qcom,bcm-name = "SN14"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_sn15: bcm-sn15 { + cell-id = ; + label = "SN15"; + qcom,bcm-name = "SN15"; + qcom,rscs = <&rsc_apps>; + qcom,bcm-dev; + }; + + bcm_acv_display: bcm-acv_display { + cell-id = ; + label = "ACV_DISPLAY"; + qcom,bcm-name = "ACV"; + qcom,rscs = <&rsc_disp>; + qcom,bcm-dev; + }; + + bcm_alc_display: bcm-alc_display { + cell-id = ; + label = "ALC_DISPLAY"; + qcom,bcm-name = "ALC"; + qcom,rscs = <&rsc_disp>; + qcom,bcm-dev; + }; + + bcm_mc0_display: bcm-mc0_display { + cell-id = ; + label = "MC0_DISPLAY"; + qcom,bcm-name = "MC0"; + qcom,rscs = <&rsc_disp>; + qcom,bcm-dev; + }; + + bcm_sh0_display: bcm-sh0_display { + cell-id = ; + label = "SH0_DISPLAY"; + qcom,bcm-name = "SH0"; + qcom,rscs = <&rsc_disp>; + qcom,bcm-dev; + }; + + bcm_mm0_display: bcm-mm0_display { + cell-id = ; + label = "MM0_DISPLAY"; + qcom,bcm-name = "MM0"; + qcom,rscs = <&rsc_disp>; + qcom,bcm-dev; + }; + + bcm_mm1_display: bcm-mm1_display { + cell-id = ; + label = "MM1_DISPLAY"; + qcom,bcm-name = "MM1"; + qcom,rscs = <&rsc_disp>; + qcom,bcm-dev; + }; + + bcm_mm2_display: bcm-mm2_display { + cell-id = ; + label = "MM2_DISPLAY"; + qcom,bcm-name = "MM2"; + qcom,rscs = <&rsc_disp>; + qcom,bcm-dev; + }; + + bcm_mm3_display: bcm-mm3_display { + cell-id = ; + label = "MM3_DISPLAY"; + qcom,bcm-name = "MM3"; + qcom,rscs = <&rsc_disp>; + qcom,bcm-dev; + }; + + + /*Buses*/ + fab_aggre1_noc: fab-aggre1_noc{ + cell-id = ; + label = "fab-aggre1_noc"; + qcom,fab-dev; + qcom,base-name = "aggre1_noc-base"; + qcom,qos-off = <4096>; + qcom,base-offset = <16384>; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_aggre2_noc: fab-aggre2_noc{ + cell-id = ; + label = "fab-aggre2_noc"; + qcom,fab-dev; + qcom,base-name = "aggre2_noc-base"; + qcom,qos-off = <4096>; + qcom,base-offset = <24576>; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_camnoc_virt: fab-camnoc_virt{ + cell-id = ; + label = "fab-camnoc_virt"; + qcom,fab-dev; + qcom,base-name = "camnoc_virt-base"; + qcom,qos-off = <0>; + qcom,base-offset = <0>; + qcom,bypass-qos-prg; + clocks = <>; + }; + + fab_compute_noc: fab-compute_noc{ + cell-id = ; + label = "fab-compute_noc"; + qcom,fab-dev; + qcom,base-name = "compute_noc-base"; + qcom,qos-off = <8192>; + qcom,base-offset = <131072>; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_config_noc: fab-config_noc{ + cell-id = ; + label = "fab-config_noc"; + qcom,fab-dev; + qcom,base-name = "config_noc-base"; + qcom,qos-off = <0>; + qcom,base-offset = <0>; + qcom,sbm-offset = <24576>; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_dc_noc: fab-dc_noc{ + cell-id = ; + label = "fab-dc_noc"; + qcom,fab-dev; + qcom,base-name = "dc_noc-base"; + qcom,qos-off = <0>; + qcom,base-offset = <0>; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_gem_noc: fab-gem_noc{ + cell-id = ; + label = "fab-gem_noc"; + qcom,fab-dev; + qcom,base-name = "gem_noc-base"; + qcom,qos-off = <128>; + qcom,base-offset = <176128>; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_ipa_virt: fab-ipa_virt{ + cell-id = ; + label = "fab-ipa_virt"; + qcom,fab-dev; + qcom,base-name = "ipa_virt-base"; + qcom,qos-off = <0>; + qcom,base-offset = <0>; + qcom,bypass-qos-prg; + clocks = <>; + }; + + fab_mc_virt: fab-mc_virt{ + cell-id = ; + label = "fab-mc_virt"; + qcom,fab-dev; + qcom,base-name = "mc_virt-base"; + qcom,qos-off = <0>; + qcom,base-offset = <0>; + qcom,bypass-qos-prg; + clocks = <>; + }; + + fab_mmss_noc: fab-mmss_noc{ + cell-id = ; + label = "fab-mmss_noc"; + qcom,fab-dev; + qcom,base-name = "mmss_noc-base"; + qcom,qos-off = <4096>; + qcom,base-offset = <36864>; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_system_noc: fab-system_noc{ + cell-id = ; + label = "fab-system_noc"; + qcom,fab-dev; + qcom,base-name = "system_noc-base"; + qcom,qos-off = <4096>; + qcom,base-offset = <36864>; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_gem_noc_display: fab-gem_noc_display{ + cell-id = ; + label = "fab-gem_noc_display"; + qcom,fab-dev; + qcom,base-name = "gem_noc-base"; + qcom,qos-off = <128>; + qcom,base-offset = <176128>; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clocks = <>; + }; + + fab_mc_virt_display: fab-mc_virt_display{ + cell-id = ; + label = "fab-mc_virt_display"; + qcom,fab-dev; + qcom,base-name = "mc_virt-base"; + qcom,qos-off = <0>; + qcom,base-offset = <0>; + qcom,bypass-qos-prg; + clocks = <>; + }; + + fab_mmss_noc_display: fab-mmss_noc_display{ + cell-id = ; + label = "fab-mmss_noc_display"; + qcom,fab-dev; + qcom,base-name = "mmss_noc-base"; + qcom,qos-off = <4096>; + qcom,base-offset = <36864>; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clocks = <>; + }; + + /*Masters*/ + + mas_qhm_a1noc_cfg: mas-qhm-a1noc-cfg { + cell-id = ; + label = "mas-qhm-a1noc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_srvc_aggre1_noc>; + qcom,bus-dev = <&fab_aggre1_noc>; + }; + + mas_qhm_qup0: mas-qhm-qup0 { + cell-id = ; + label = "mas-qhm-qup0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,qport = <7>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,bcms = <&bcm_qup0>; + qcom,ap-owned; + qcom,prio = <2>; + }; + + mas_xm_emac: mas-xm-emac { + cell-id = ; + label = "mas-xm-emac"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <9>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,ap-owned; + qcom,prio = <2>; + }; + + mas_xm_ufs_mem: mas-xm-ufs-mem { + cell-id = ; + label = "mas-xm-ufs-mem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <0>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,ap-owned; + qcom,prio = <2>; + qcom,node-qos-clks { + clocks = + <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; + clock-names = + "clk-aggre-ufs-phy-axi-no-rate"; + }; + }; + + mas_xm_usb3_0: mas-xm-usb3-0 { + cell-id = ; + label = "mas-xm-usb3-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <2>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,ap-owned; + qcom,prio = <2>; + qcom,node-qos-clks { + clocks = + <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + clock-names = + "clk-usb3-prim-axi-no-rate"; + }; + }; + + mas_xm_usb3_1: mas-xm-usb3-1 { + cell-id = ; + label = "mas-xm-usb3-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <4>; + qcom,connections = <&slv_qns_a1noc_snoc>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,ap-owned; + qcom,prio = <2>; + qcom,node-qos-clks { + clocks = + <&clock_gcc GCC_AGGRE_USB3_SEC_AXI_CLK>; + clock-names = + "clk-usb3-sec-axi-no-rate"; + }; + }; + + mas_qhm_a2noc_cfg: mas-qhm-a2noc-cfg { + cell-id = ; + label = "mas-qhm-a2noc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_srvc_aggre2_noc>; + qcom,bus-dev = <&fab_aggre2_noc>; + }; + + mas_qhm_qdss_bam: mas-qhm-qdss-bam { + cell-id = ; + label = "mas-qhm-qdss-bam"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,qport = <47>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,ap-owned; + qcom,prio = <2>; + }; + + mas_qhm_qspi: mas-qhm-qspi { + cell-id = ; + label = "mas-qhm-qspi"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,qport = <51>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,ap-owned; + qcom,prio = <2>; + }; + + mas_qhm_qup1: mas-qhm-qup1 { + cell-id = ; + label = "mas-qhm-qup1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,qport = <48>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,bcms = <&bcm_qup0>; + qcom,ap-owned; + qcom,prio = <2>; + }; + + mas_qhm_qup2: mas-qhm-qup2 { + cell-id = ; + label = "mas-qhm-qup2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,qport = <49>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,bcms = <&bcm_qup0>; + qcom,ap-owned; + qcom,prio = <2>; + }; + + mas_qhm_sensorss_ahb: mas-qhm-sensorss-ahb { + cell-id = ; + label = "mas-qhm-sensorss-ahb"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + }; + + mas_qhm_tsif: mas-qhm-tsif { + cell-id = ; + label = "mas-qhm-tsif"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + }; + + mas_qnm_cnoc: mas-qnm-cnoc { + cell-id = ; + label = "mas-qnm-cnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <34>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,ap-owned; + qcom,prio = <2>; + qcom,forwarding; + }; + + mas_qxm_crypto: mas-qxm-crypto { + cell-id = ; + label = "mas-qxm-crypto"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <0>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,bcms = <&bcm_ce0>; + qcom,ap-owned; + qcom,prio = <2>; + qcom,forwarding; + }; + + mas_qxm_ipa: mas-qxm-ipa { + cell-id = ; + label = "mas-qxm-ipa"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <2>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,ap-owned; + qcom,prio = <2>; + qcom,forwarding; + qcom,defer-init-qos; + qcom,node-qos-bcms = <7035 0 1>; + }; + + mas_xm_pcie3_0: mas-xm-pcie3-0 { + cell-id = ; + label = "mas-xm-pcie3-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <39>; + qcom,connections = <&slv_qns_pcie_mem_noc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,ap-owned; + qcom,prio = <2>; + }; + + mas_xm_pcie3_1: mas-xm-pcie3-1 { + cell-id = ; + label = "mas-xm-pcie3-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <43>; + qcom,connections = <&slv_qns_pcie_mem_noc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,ap-owned; + qcom,prio = <2>; + }; + + mas_xm_qdss_etr: mas-xm-qdss-etr { + cell-id = ; + label = "mas-xm-qdss-etr"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <12>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,ap-owned; + qcom,prio = <2>; + }; + + mas_xm_sdc2: mas-xm-sdc2 { + cell-id = ; + label = "mas-xm-sdc2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <14>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,ap-owned; + qcom,prio = <2>; + }; + + mas_xm_sdc4: mas-xm-sdc4 { + cell-id = ; + label = "mas-xm-sdc4"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <16>; + qcom,connections = <&slv_qns_a2noc_snoc>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,ap-owned; + qcom,prio = <2>; + }; + + mas_qxm_camnoc_hf0_uncomp: mas-qxm-camnoc-hf0-uncomp { + cell-id = ; + label = "mas-qxm-camnoc-hf0-uncomp"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_camnoc_uncomp>; + qcom,bus-dev = <&fab_camnoc_virt>; + qcom,bcms = <&bcm_mm1>; + }; + + mas_qxm_camnoc_hf1_uncomp: mas-qxm-camnoc-hf1-uncomp { + cell-id = ; + label = "mas-qxm-camnoc-hf1-uncomp"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_camnoc_uncomp>; + qcom,bus-dev = <&fab_camnoc_virt>; + qcom,bcms = <&bcm_mm1>; + }; + + mas_qxm_camnoc_sf_uncomp: mas-qxm-camnoc-sf-uncomp { + cell-id = ; + label = "mas-qxm-camnoc-sf-uncomp"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_camnoc_uncomp>; + qcom,bus-dev = <&fab_camnoc_virt>; + qcom,bcms = <&bcm_mm1>; + }; + + mas_qnm_npu: mas-qnm-npu { + cell-id = ; + label = "mas-qnm-npu"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <2>; + qcom,connections = <&slv_qns_cdsp_mem_noc>; + qcom,bus-dev = <&fab_compute_noc>; + qcom,bcms = <&bcm_co1>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + }; + + mas_qhm_spdm: mas-qhm-spdm { + cell-id = ; + label = "mas-qhm-spdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_cnoc_a2noc>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + mas_qnm_snoc: mas-qnm-snoc { + cell-id = ; + label = "mas-qnm-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qhs_tlmm_south + &slv_qhs_compute_dsp &slv_qhs_spss_cfg + &slv_qhs_camera_cfg &slv_qhs_sdc4 + &slv_qhs_sdc2 &slv_qhs_mnoc_cfg + &slv_qhs_emac_cfg &slv_qhs_ufs_mem_cfg + &slv_qhs_tlmm_east &slv_qhs_ssc_cfg + &slv_qhs_snoc_cfg &slv_qhs_phy_refgen_north + &slv_qhs_qupv3_south &slv_qhs_glm + &slv_qhs_pcie1_cfg &slv_qhs_a2_noc_cfg + &slv_qhs_qdss_cfg &slv_qhs_display_cfg + &slv_qhs_tcsr &slv_qhs_ddrss_cfg + &slv_qhs_cpr_mmcx &slv_qhs_npu_cfg + &slv_qhs_pcie0_cfg &slv_qhs_gpuss_cfg + &slv_qhs_venus_cfg &slv_qhs_tsif + &slv_qhs_ipa &slv_qhs_clk_ctl + &slv_qhs_aop &slv_qhs_qupv3_north + &slv_qhs_ahb2phy_south &slv_qhs_usb3_1 + &slv_srvc_cnoc &slv_qhs_ufs_card_cfg + &slv_qhs_qupv3_east &slv_qhs_cpr_cx + &slv_qhs_tlmm_west &slv_qhs_a1_noc_cfg + &slv_qhs_aoss &slv_qhs_prng + &slv_qhs_vsense_ctrl_cfg &slv_qhs_qspi + &slv_qhs_usb3_0 &slv_qhs_spdm + &slv_qhs_crypto0_cfg &slv_qhs_pimem_cfg + &slv_qhs_tlmm_north &slv_qhs_cpr_mx + &slv_qhs_imem_cfg>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + mas_xm_qdss_dap: mas-xm-qdss-dap { + cell-id = ; + label = "mas-xm-qdss-dap"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qhs_tlmm_south + &slv_qhs_compute_dsp &slv_qhs_spss_cfg + &slv_qhs_camera_cfg &slv_qhs_sdc4 + &slv_qhs_sdc2 &slv_qhs_mnoc_cfg + &slv_qhs_emac_cfg &slv_qhs_ufs_mem_cfg + &slv_qhs_tlmm_east &slv_qhs_ssc_cfg + &slv_qhs_snoc_cfg &slv_qhs_phy_refgen_north + &slv_qhs_qupv3_south &slv_qhs_glm + &slv_qhs_pcie1_cfg &slv_qhs_a2_noc_cfg + &slv_qhs_qdss_cfg &slv_qhs_display_cfg + &slv_qhs_tcsr &slv_qhs_ddrss_cfg + &slv_qns_cnoc_a2noc &slv_qhs_cpr_mmcx + &slv_qhs_npu_cfg &slv_qhs_pcie0_cfg + &slv_qhs_gpuss_cfg &slv_qhs_venus_cfg + &slv_qhs_tsif &slv_qhs_ipa + &slv_qhs_clk_ctl &slv_qhs_aop + &slv_qhs_qupv3_north &slv_qhs_ahb2phy_south + &slv_qhs_usb3_1 &slv_srvc_cnoc + &slv_qhs_ufs_card_cfg &slv_qhs_qupv3_east + &slv_qhs_cpr_cx &slv_qhs_tlmm_west + &slv_qhs_a1_noc_cfg &slv_qhs_aoss + &slv_qhs_prng &slv_qhs_vsense_ctrl_cfg + &slv_qhs_qspi &slv_qhs_usb3_0 + &slv_qhs_spdm &slv_qhs_crypto0_cfg + &slv_qhs_pimem_cfg &slv_qhs_tlmm_north + &slv_qhs_cpr_mx &slv_qhs_imem_cfg>; + qcom,bus-dev = <&fab_config_noc>; + }; + + mas_qhm_cnoc_dc_noc: mas-qhm-cnoc-dc-noc { + cell-id = ; + label = "mas-qhm-cnoc-dc-noc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qhs_memnoc &slv_qhs_llcc>; + qcom,bus-dev = <&fab_dc_noc>; + }; + + mas_acm_apps: mas-acm-apps { + cell-id = ; + label = "mas-acm-apps"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,qport = <96 97 98 99>; + qcom,connections = <&slv_qns_ecc &slv_qns_llcc + &slv_qns_gem_noc_snoc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,bcms = <&bcm_sh5>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + }; + + mas_acm_gpu_tcu: mas-acm-gpu-tcu { + cell-id = ; + label = "mas-acm-gpu-tcu"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <352>; + qcom,connections = <&slv_qns_llcc + &slv_qns_gem_noc_snoc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,bcms = <&bcm_sh3>; + qcom,ap-owned; + qcom,prio = <6>; + }; + + mas_acm_sys_tcu: mas-acm-sys-tcu { + cell-id = ; + label = "mas-acm-sys-tcu"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <384>; + qcom,connections = <&slv_qns_llcc + &slv_qns_gem_noc_snoc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,bcms = <&bcm_sh3>; + qcom,ap-owned; + qcom,prio = <6>; + }; + + mas_qhm_gemnoc_cfg: mas-qhm-gemnoc-cfg { + cell-id = ; + label = "mas-qhm-gemnoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_srvc_gemnoc + &slv_qhs_mdsp_ms_mpu_cfg>; + qcom,bus-dev = <&fab_gem_noc>; + }; + + mas_qnm_cmpnoc: mas-qnm-cmpnoc { + cell-id = ; + label = "mas-qnm-cmpnoc"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,qport = <64 65>; + qcom,connections = <&slv_qns_ecc &slv_qns_llcc + &slv_qns_gem_noc_snoc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,bcms = <&bcm_sh4>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + }; + + mas_qnm_gpu: mas-qnm-gpu { + cell-id = ; + label = "mas-qnm-gpu"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,qport = <288 289>; + qcom,connections = <&slv_qns_llcc + &slv_qns_gem_noc_snoc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + }; + + mas_qnm_mnoc_hf: mas-qnm-mnoc-hf { + cell-id = ; + label = "mas-qnm-mnoc-hf"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,qport = <128 129>; + qcom,connections = <&slv_qns_llcc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,node-qos-bcms = <7012 0 1>; + }; + + mas_qnm_mnoc_sf: mas-qnm-mnoc-sf { + cell-id = ; + label = "mas-qnm-mnoc-sf"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <320>; + qcom,connections = <&slv_qns_llcc + &slv_qns_gem_noc_snoc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,node-qos-bcms = <7012 0 1>; + }; + + mas_qnm_pcie: mas-qnm-pcie { + cell-id = ; + label = "mas-qnm-pcie"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,qport = <224>; + qcom,connections = <&slv_qns_llcc + &slv_qns_gem_noc_snoc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + }; + + mas_qnm_snoc_gc: mas-qnm-snoc-gc { + cell-id = ; + label = "mas-qnm-snoc-gc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <192>; + qcom,connections = <&slv_qns_llcc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + }; + + mas_qnm_snoc_sf: mas-qnm-snoc-sf { + cell-id = ; + label = "mas-qnm-snoc-sf"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,qport = <160>; + qcom,connections = <&slv_qns_llcc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + }; + + mas_qxm_ecc: mas-qxm-ecc { + cell-id = ; + label = "mas-qxm-ecc"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,qport = <256 257>; + qcom,connections = <&slv_qns_llcc>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + }; + + mas_ipa_core_master: mas-ipa-core-master { + cell-id = ; + label = "mas-ipa-core-master"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_ipa_core_slave>; + qcom,bus-dev = <&fab_ipa_virt>; + }; + + mas_llcc_mc: mas-llcc-mc { + cell-id = ; + label = "mas-llcc-mc"; + qcom,buswidth = <4>; + qcom,agg-ports = <4>; + qcom,connections = <&slv_ebi>; + qcom,bus-dev = <&fab_mc_virt>; + }; + + mas_qhm_mnoc_cfg: mas-qhm-mnoc-cfg { + cell-id = ; + label = "mas-qhm-mnoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_srvc_mnoc>; + qcom,bus-dev = <&fab_mmss_noc>; + }; + + mas_qxm_camnoc_hf0: mas-qxm-camnoc-hf0 { + cell-id = ; + label = "mas-qxm-camnoc-hf0"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <1>; + qcom,connections = <&slv_qns_mem_noc_hf>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm1>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + qcom,node-qos-bcms = <7012 0 1>; + }; + + mas_qxm_camnoc_hf1: mas-qxm-camnoc-hf1 { + cell-id = ; + label = "mas-qxm-camnoc-hf1"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <2>; + qcom,connections = <&slv_qns_mem_noc_hf>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm1>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + qcom,node-qos-bcms = <7012 0 1>; + }; + + mas_qxm_camnoc_sf: mas-qxm-camnoc-sf { + cell-id = ; + label = "mas-qxm-camnoc-sf"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <0>; + qcom,connections = <&slv_qns2_mem_noc>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm2>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + qcom,node-qos-bcms = <7012 0 1>; + }; + + mas_qxm_mdp0: mas-qxm-mdp0 { + cell-id = ; + label = "mas-qxm-mdp0"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <3>; + qcom,connections = <&slv_qns_mem_noc_hf>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm1>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + qcom,node-qos-bcms = <7012 0 1>; + }; + + mas_qxm_mdp1: mas-qxm-mdp1 { + cell-id = ; + label = "mas-qxm-mdp1"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <4>; + qcom,connections = <&slv_qns_mem_noc_hf>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm1>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + qcom,node-qos-bcms = <7012 0 1>; + }; + + mas_qxm_rot: mas-qxm-rot { + cell-id = ; + label = "mas-qxm-rot"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <5>; + qcom,connections = <&slv_qns2_mem_noc>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm3>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + qcom,node-qos-bcms = <7012 0 1>; + }; + + mas_qxm_venus0: mas-qxm-venus0 { + cell-id = ; + label = "mas-qxm-venus0"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <6>; + qcom,connections = <&slv_qns2_mem_noc>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm3>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + qcom,node-qos-bcms = <7012 0 1>; + }; + + mas_qxm_venus1: mas-qxm-venus1 { + cell-id = ; + label = "mas-qxm-venus1"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <7>; + qcom,connections = <&slv_qns2_mem_noc>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm3>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + qcom,node-qos-bcms = <7012 0 1>; + }; + + mas_qxm_venus_arm9: mas-qxm-venus-arm9 { + cell-id = ; + label = "mas-qxm-venus-arm9"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <8>; + qcom,connections = <&slv_qns2_mem_noc>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,bcms = <&bcm_mm3>; + qcom,ap-owned; + qcom,prio = <0>; + qcom,forwarding; + qcom,node-qos-bcms = <7012 0 1>; + }; + + mas_qhm_snoc_cfg: mas-qhm-snoc-cfg { + cell-id = ; + label = "mas-qhm-snoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_srvc_snoc>; + qcom,bus-dev = <&fab_system_noc>; + }; + + mas_qnm_aggre1_noc: mas-qnm-aggre1-noc { + cell-id = ; + label = "mas-qnm-aggre1-noc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_gemnoc_sf + &slv_qxs_pimem &slv_qxs_imem + &slv_qhs_apss &slv_qns_cnoc + &slv_xs_qdss_stm>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn9>; + }; + + mas_qnm_aggre2_noc: mas-qnm-aggre2-noc { + cell-id = ; + label = "mas-qnm-aggre2-noc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qns_gemnoc_sf + &slv_qxs_pimem &slv_qxs_imem + &slv_qhs_apss &slv_qns_cnoc + &slv_xs_pcie_0 &slv_xs_pcie_1 + &slv_xs_sys_tcu_cfg &slv_xs_qdss_stm>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn11>; + }; + + mas_qnm_gemnoc: mas-qnm-gemnoc { + cell-id = ; + label = "mas-qnm-gemnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qxs_pimem + &slv_qxs_imem &slv_qhs_apss + &slv_qns_cnoc &slv_xs_sys_tcu_cfg + &slv_xs_qdss_stm>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn15>; + }; + + mas_qxm_pimem: mas-qxm-pimem { + cell-id = ; + label = "mas-qxm-pimem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <3>; + qcom,connections = <&slv_qns_gemnoc_gc &slv_qxs_imem>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn12>; + qcom,ap-owned; + qcom,prio = <2>; + qcom,forwarding; + }; + + mas_xm_gic: mas-xm-gic { + cell-id = ; + label = "mas-xm-gic"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <0>; + qcom,connections = <&slv_qns_gemnoc_gc &slv_qxs_imem>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn12>; + qcom,ap-owned; + qcom,prio = <2>; + qcom,forwarding; + }; + + mas_alc: mas-alc { + cell-id = ; + label = "mas-alc"; + qcom,buswidth = <1>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_mc_virt>; + qcom,bcms = <&bcm_alc>; + }; + + mas_qnm_mnoc_hf_display: mas-qnm-mnoc-hf_display { + cell-id = ; + label = "mas-qnm-mnoc-hf_display"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,qport = <128 129>; + qcom,connections = <&slv_qns_llcc_display>; + qcom,bus-dev = <&fab_gem_noc_display>; + }; + + mas_qnm_mnoc_sf_display: mas-qnm-mnoc-sf_display { + cell-id = ; + label = "mas-qnm-mnoc-sf_display"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <320>; + qcom,connections = <&slv_qns_llcc_display>; + qcom,bus-dev = <&fab_gem_noc_display>; + }; + + mas_llcc_mc_display: mas-llcc-mc_display { + cell-id = ; + label = "mas-llcc-mc_display"; + qcom,buswidth = <4>; + qcom,agg-ports = <4>; + qcom,connections = <&slv_ebi_display>; + qcom,bus-dev = <&fab_mc_virt_display>; + }; + + mas_qxm_mdp0_display: mas-qxm-mdp0_display { + cell-id = ; + label = "mas-qxm-mdp0_display"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <3>; + qcom,connections = <&slv_qns_mem_noc_hf_display>; + qcom,bus-dev = <&fab_mmss_noc_display>; + qcom,bcms = <&bcm_mm1_display>; + }; + + mas_qxm_mdp1_display: mas-qxm-mdp1_display { + cell-id = ; + label = "mas-qxm-mdp1_display"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <4>; + qcom,connections = <&slv_qns_mem_noc_hf_display>; + qcom,bus-dev = <&fab_mmss_noc_display>; + qcom,bcms = <&bcm_mm1_display>; + }; + + mas_qxm_rot_display: mas-qxm-rot_display { + cell-id = ; + label = "mas-qxm-rot_display"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,qport = <5>; + qcom,connections = <&slv_qns2_mem_noc_display>; + qcom,bus-dev = <&fab_mmss_noc_display>; + qcom,bcms = <&bcm_mm3_display>; + }; + + /*Internal nodes*/ + + /*Slaves*/ + + slv_qns_a1noc_snoc:slv-qns-a1noc-snoc { + cell-id = ; + label = "slv-qns-a1noc-snoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,connections = <&mas_qnm_aggre1_noc>; + }; + + slv_srvc_aggre1_noc:slv-srvc-aggre1-noc { + cell-id = ; + label = "slv-srvc-aggre1-noc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_aggre1_noc>; + qcom,bcms = <&bcm_sn3>; + }; + + slv_qns_a2noc_snoc:slv-qns-a2noc-snoc { + cell-id = ; + label = "slv-qns-a2noc-snoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,connections = <&mas_qnm_aggre2_noc>; + }; + + slv_qns_pcie_mem_noc:slv-qns-pcie-mem-noc { + cell-id = ; + label = "slv-qns-pcie-mem-noc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,connections = <&mas_qnm_pcie>; + qcom,bcms = <&bcm_sn14>; + }; + + slv_srvc_aggre2_noc:slv-srvc-aggre2-noc { + cell-id = ; + label = "slv-srvc-aggre2-noc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_aggre2_noc>; + qcom,bcms = <&bcm_sn3>; + }; + + slv_qns_camnoc_uncomp:slv-qns-camnoc-uncomp { + cell-id = ; + label = "slv-qns-camnoc-uncomp"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_camnoc_virt>; + }; + + slv_qns_cdsp_mem_noc:slv-qns-cdsp-mem-noc { + cell-id = ; + label = "slv-qns-cdsp-mem-noc"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,bus-dev = <&fab_compute_noc>; + qcom,connections = <&mas_qnm_cmpnoc>; + qcom,bcms = <&bcm_co0>; + }; + + slv_qhs_a1_noc_cfg:slv-qhs-a1-noc-cfg { + cell-id = ; + label = "slv-qhs-a1-noc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,connections = <&mas_qhm_a1noc_cfg>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_a2_noc_cfg:slv-qhs-a2-noc-cfg { + cell-id = ; + label = "slv-qhs-a2-noc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,connections = <&mas_qhm_a2noc_cfg>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_ahb2phy_south:slv-qhs-ahb2phy-south { + cell-id = ; + label = "slv-qhs-ahb2phy-south"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_aop:slv-qhs-aop { + cell-id = ; + label = "slv-qhs-aop"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_aoss:slv-qhs-aoss { + cell-id = ; + label = "slv-qhs-aoss"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_camera_cfg:slv-qhs-camera-cfg { + cell-id = ; + label = "slv-qhs-camera-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + qcom,disable-ports = <10 11 34>; + mmcx-supply = <&VDD_MMCX_LEVEL>; + node-reg-names = "mmcx"; + }; + + slv_qhs_clk_ctl:slv-qhs-clk-ctl { + cell-id = ; + label = "slv-qhs-clk-ctl"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_compute_dsp:slv-qhs-compute-dsp { + cell-id = ; + label = "slv-qhs-compute-dsp"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_cpr_cx:slv-qhs-cpr-cx { + cell-id = ; + label = "slv-qhs-cpr-cx"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_cpr_mmcx:slv-qhs-cpr-mmcx { + cell-id = ; + label = "slv-qhs-cpr-mmcx"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_cpr_mx:slv-qhs-cpr-mx { + cell-id = ; + label = "slv-qhs-cpr-mx"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_crypto0_cfg:slv-qhs-crypto0-cfg { + cell-id = ; + label = "slv-qhs-crypto0-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_ddrss_cfg:slv-qhs-ddrss-cfg { + cell-id = ; + label = "slv-qhs-ddrss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,connections = <&mas_qhm_cnoc_dc_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_display_cfg:slv-qhs-display-cfg { + cell-id = ; + label = "slv-qhs-display-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + qcom,disable-ports = <12 13>; + mmcx-supply = <&VDD_MMCX_LEVEL>; + node-reg-names = "mmcx"; + }; + + slv_qhs_emac_cfg:slv-qhs-emac-cfg { + cell-id = ; + label = "slv-qhs-emac-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_glm:slv-qhs-glm { + cell-id = ; + label = "slv-qhs-glm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_gpuss_cfg:slv-qhs-gpuss-cfg { + cell-id = ; + label = "slv-qhs-gpuss-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_imem_cfg:slv-qhs-imem-cfg { + cell-id = ; + label = "slv-qhs-imem-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_ipa:slv-qhs-ipa { + cell-id = ; + label = "slv-qhs-ipa"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_mnoc_cfg:slv-qhs-mnoc-cfg { + cell-id = ; + label = "slv-qhs-mnoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,connections = <&mas_qhm_mnoc_cfg>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_npu_cfg:slv-qhs-npu-cfg { + cell-id = ; + label = "slv-qhs-npu-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_pcie0_cfg:slv-qhs-pcie0-cfg { + cell-id = ; + label = "slv-qhs-pcie0-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_pcie1_cfg:slv-qhs-pcie1-cfg { + cell-id = ; + label = "slv-qhs-pcie1-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_phy_refgen_north:slv-qhs-phy-refgen-north { + cell-id = ; + label = "slv-qhs-phy-refgen-north"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_pimem_cfg:slv-qhs-pimem-cfg { + cell-id = ; + label = "slv-qhs-pimem-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_prng:slv-qhs-prng { + cell-id = ; + label = "slv-qhs-prng"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_qdss_cfg:slv-qhs-qdss-cfg { + cell-id = ; + label = "slv-qhs-qdss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_qspi:slv-qhs-qspi { + cell-id = ; + label = "slv-qhs-qspi"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_qupv3_east:slv-qhs-qupv3-east { + cell-id = ; + label = "slv-qhs-qupv3-east"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_qupv3_north:slv-qhs-qupv3-north { + cell-id = ; + label = "slv-qhs-qupv3-north"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_qupv3_south:slv-qhs-qupv3-south { + cell-id = ; + label = "slv-qhs-qupv3-south"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_sdc2:slv-qhs-sdc2 { + cell-id = ; + label = "slv-qhs-sdc2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_sdc4:slv-qhs-sdc4 { + cell-id = ; + label = "slv-qhs-sdc4"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_snoc_cfg:slv-qhs-snoc-cfg { + cell-id = ; + label = "slv-qhs-snoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,connections = <&mas_qhm_snoc_cfg>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_spdm:slv-qhs-spdm { + cell-id = ; + label = "slv-qhs-spdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_spss_cfg:slv-qhs-spss-cfg { + cell-id = ; + label = "slv-qhs-spss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_ssc_cfg:slv-qhs-ssc-cfg { + cell-id = ; + label = "slv-qhs-ssc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_tcsr:slv-qhs-tcsr { + cell-id = ; + label = "slv-qhs-tcsr"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_tlmm_east:slv-qhs-tlmm-east { + cell-id = ; + label = "slv-qhs-tlmm-east"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_tlmm_north:slv-qhs-tlmm-north { + cell-id = ; + label = "slv-qhs-tlmm-north"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_tlmm_south:slv-qhs-tlmm-south { + cell-id = ; + label = "slv-qhs-tlmm-south"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_tlmm_west:slv-qhs-tlmm-west { + cell-id = ; + label = "slv-qhs-tlmm-west"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_tsif:slv-qhs-tsif { + cell-id = ; + label = "slv-qhs-tsif"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_ufs_card_cfg:slv-qhs-ufs-card-cfg { + cell-id = ; + label = "slv-qhs-ufs-card-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_ufs_mem_cfg:slv-qhs-ufs-mem-cfg { + cell-id = ; + label = "slv-qhs-ufs-mem-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_usb3_0:slv-qhs-usb3-0 { + cell-id = ; + label = "slv-qhs-usb3-0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_usb3_1:slv-qhs-usb3-1 { + cell-id = ; + label = "slv-qhs-usb3-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_venus_cfg:slv-qhs-venus-cfg { + cell-id = ; + label = "slv-qhs-venus-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + qcom,disable-ports = <15 16 35>; + mmcx-supply = <&VDD_MMCX_LEVEL>; + node-reg-names = "mmcx"; + }; + + slv_qhs_vsense_ctrl_cfg:slv-qhs-vsense-ctrl-cfg { + cell-id = ; + label = "slv-qhs-vsense-ctrl-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qns_cnoc_a2noc:slv-qns-cnoc-a2noc { + cell-id = ; + label = "slv-qns-cnoc-a2noc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,connections = <&mas_qnm_cnoc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_srvc_cnoc:slv-srvc-cnoc { + cell-id = ; + label = "slv-srvc-cnoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_config_noc>; + qcom,bcms = <&bcm_cn0>; + }; + + slv_qhs_llcc:slv-qhs-llcc { + cell-id = ; + label = "slv-qhs-llcc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_dc_noc>; + }; + + slv_qhs_memnoc:slv-qhs-memnoc { + cell-id = ; + label = "slv-qhs-memnoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_dc_noc>; + qcom,connections = <&mas_qhm_gemnoc_cfg>; + }; + + slv_qhs_mdsp_ms_mpu_cfg:slv-qhs-mdsp-ms-mpu-cfg { + cell-id = ; + label = "slv-qhs-mdsp-ms-mpu-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_gem_noc>; + }; + + slv_qns_ecc:slv-qns-ecc { + cell-id = ; + label = "slv-qns-ecc"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_gem_noc>; + }; + + slv_qns_gem_noc_snoc:slv-qns-gem-noc-snoc { + cell-id = ; + label = "slv-qns-gem-noc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,connections = <&mas_qnm_gemnoc>; + qcom,bcms = <&bcm_sh2>; + }; + + slv_qns_llcc:slv-qns-llcc { + cell-id = ; + label = "slv-qns-llcc"; + qcom,buswidth = <16>; + qcom,agg-ports = <4>; + qcom,bus-dev = <&fab_gem_noc>; + qcom,connections = <&mas_llcc_mc>; + qcom,bcms = <&bcm_sh0>; + }; + + slv_srvc_gemnoc:slv-srvc-gemnoc { + cell-id = ; + label = "slv-srvc-gemnoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_gem_noc>; + }; + + slv_ipa_core_slave:slv-ipa-core-slave { + cell-id = ; + label = "slv-ipa-core-slave"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_ipa_virt>; + qcom,bcms = <&bcm_ip0>; + }; + + slv_ebi:slv-ebi { + cell-id = ; + label = "slv-ebi"; + qcom,buswidth = <4>; + qcom,agg-ports = <4>; + qcom,bus-dev = <&fab_mc_virt>; + qcom,bcms = <&bcm_mc0>, <&bcm_acv>; + }; + + slv_qns2_mem_noc:slv-qns2-mem-noc { + cell-id = ; + label = "slv-qns2-mem-noc"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,connections = <&mas_qnm_mnoc_sf>; + qcom,bcms = <&bcm_mm2>; + }; + + slv_qns_mem_noc_hf:slv-qns-mem-noc-hf { + cell-id = ; + label = "slv-qns-mem-noc-hf"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,bus-dev = <&fab_mmss_noc>; + qcom,connections = <&mas_qnm_mnoc_hf>; + qcom,bcms = <&bcm_mm0>; + }; + + slv_srvc_mnoc:slv-srvc-mnoc { + cell-id = ; + label = "slv-srvc-mnoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_mmss_noc>; + }; + + slv_qhs_apss:slv-qhs-apss { + cell-id = ; + label = "slv-qhs-apss"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + }; + + slv_qns_cnoc:slv-qns-cnoc { + cell-id = ; + label = "slv-qns-cnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,connections = <&mas_qnm_snoc>; + qcom,bcms = <&bcm_sn3>; + }; + + slv_qns_gemnoc_gc:slv-qns-gemnoc-gc { + cell-id = ; + label = "slv-qns-gemnoc-gc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,connections = <&mas_qnm_snoc_gc>; + qcom,bcms = <&bcm_sn2>; + }; + + slv_qns_gemnoc_sf:slv-qns-gemnoc-sf { + cell-id = ; + label = "slv-qns-gemnoc-sf"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,connections = <&mas_qnm_snoc_sf>; + qcom,bcms = <&bcm_sn0>; + }; + + slv_qxs_imem:slv-qxs-imem { + cell-id = ; + label = "slv-qxs-imem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn1>; + }; + + slv_qxs_pimem:slv-qxs-pimem { + cell-id = ; + label = "slv-qxs-pimem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn4>; + }; + + slv_srvc_snoc:slv-srvc-snoc { + cell-id = ; + label = "slv-srvc-snoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + }; + + slv_xs_pcie_0:slv-xs-pcie-0 { + cell-id = ; + label = "slv-xs-pcie-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn8>; + }; + + slv_xs_pcie_1:slv-xs-pcie-1 { + cell-id = ; + label = "slv-xs-pcie-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn8>; + }; + + slv_xs_qdss_stm:slv-xs-qdss-stm { + cell-id = ; + label = "slv-xs-qdss-stm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + qcom,bcms = <&bcm_sn5>; + }; + + slv_xs_sys_tcu_cfg:slv-xs-sys-tcu-cfg { + cell-id = ; + label = "slv-xs-sys-tcu-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_system_noc>; + }; + + slv_qns_llcc_display:slv-qns-llcc_display { + cell-id = ; + label = "slv-qns-llcc_display"; + qcom,buswidth = <16>; + qcom,agg-ports = <4>; + qcom,bus-dev = <&fab_gem_noc_display>; + qcom,connections = <&mas_llcc_mc_display>; + qcom,bcms = <&bcm_sh0_display>; + }; + + slv_ebi_display:slv-ebi_display { + cell-id = ; + label = "slv-ebi_display"; + qcom,buswidth = <4>; + qcom,agg-ports = <4>; + qcom,bus-dev = <&fab_mc_virt_display>; + qcom,bcms = <&bcm_mc0_display>, <&bcm_acv_display>; + }; + + slv_qns2_mem_noc_display:slv-qns2-mem-noc_display { + cell-id = ; + label = "slv-qns2-mem-noc_display"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_mmss_noc_display>; + qcom,connections = <&mas_qnm_mnoc_sf_display>; + qcom,bcms = <&bcm_mm2_display>; + }; + + slv_qns_mem_noc_hf_display:slv-qns-mem-noc-hf_display { + cell-id = ; + label = "slv-qns-mem-noc-hf_display"; + qcom,buswidth = <32>; + qcom,agg-ports = <2>; + qcom,bus-dev = <&fab_mmss_noc_display>; + qcom,connections = <&mas_qnm_mnoc_hf_display>; + qcom,bcms = <&bcm_mm0_display>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/qcom/sm8150-camera-sensor-cdp.dtsi b/arch/arm/boot/dts/qcom/sm8150-camera-sensor-cdp.dtsi new file mode 100644 index 000000000000..645640f5d62d --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-camera-sensor-cdp.dtsi @@ -0,0 +1,775 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + #address-cells = <1>; + #size-cells = <1>; + + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_front: qcom,camera-flash@2 { + cell-index = <2>; + reg = <0x02 0x00>; + compatible = "qcom,camera-flash"; + wled-flash-support; + flash-source = <&wled_flash>; + torch-source = <&wled_torch>; + switch-source = <&wled_switch>; + status = "ok"; + }; + + led_flash_iris: qcom,camera-flash@3 { + cell-index = <3>; + reg = <0x03 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash1>; + torch-source = <&pm8150l_torch1>; + switch-source = <&pm8150l_switch0>; + status = "ok"; + }; + + led_flash_triple_rear: qcom,camera-flash@4 { + cell-index = <4>; + reg = <0x04 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@5 { + cell-index = <5>; + reg = <0x05 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@6 { + cell-index = <6>; + reg = <0x06 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + actuator_triple_rear_regulator: gpio-regulator@4 { + compatible = "regulator-fixed"; + reg = <0x04 0x00>; + regulator-name = "actuator_triple_rear_regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&tlmm 158 0>; + vin-supply = <&pm8150l_bob>; + }; + + actuator_triple_rear_aux_regulator: gpio-regulator@5 { + compatible = "regulator-fixed"; + reg = <0x05 0x00>; + regulator-name = "actuator_triple_rear_aux_regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&tlmm 160 0>; + vin-supply = <&pm8150l_bob>; + }; + + actuator_triple_rear_aux2_regulator: gpio-regulator@6 { + compatible = "regulator-fixed"; + reg = <0x06 0x00>; + regulator-name = "actuator_triple_rear_aux2_regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&tlmm 24 0>; + vin-supply = <&pm8150l_bob>; + }; +}; + +&cam_cci0 { + #address-cells = <1>; + #size-cells = <0>; + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; + + actuator_rear: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <2856000>; + rgltr-load-current = <0>; + }; + + actuator_rear_aux: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <2856000>; + rgltr-load-current = <0>; + }; + + actuator_front: qcom,actuator@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <2856000>; + rgltr-load-current = <0>; + }; + + actuator_triple_rear: qcom,actuator@4 { + cell-index = <4>; + reg = <0x4>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&actuator_triple_rear_regulator>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + }; + + actuator_triple_rear_aux: qcom,actuator@5 { + cell-index = <5>; + reg = <0x5>; + compatible = "qcom,actuator"; + cci-device = <1>; + cci-master = <1>; + cam_vaf-supply = <&actuator_triple_rear_aux_regulator>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + }; + + actuator_triple_rear_aux2: qcom,actuator@6 { + cell-index = <6>; + reg = <0x6>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&actuator_triple_rear_aux2_regulator>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + }; + + ois_rear: qcom,ois@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,ois"; + cci-master = <0>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <2856000>; + rgltr-load-current = <0>; + status = "ok"; + }; + + eeprom_rear: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2800000 1200000 0 2856000>; + rgltr-max-voltage = <0 2800000 1200000 0 2856000>; + rgltr-load-current = <0 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2856000 1200000 0 2856000>; + rgltr-max-voltage = <0 2856000 1200000 0 2856000>; + rgltr-load-current = <0 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2856000 1200000 0 2856000>; + rgltr-max-voltage = <0 2856000 1200000 0 2856000>; + rgltr-load-current = <0 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-position = <1>; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear: qcom,eeprom@4 { + cell-index = <4>; + reg = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_s2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 2856000 0>; + rgltr-max-voltage = <1800000 4000000 3008000 0>; + rgltr-load-current = <180000 2000000 519000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_triple_rear>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_triple_rear>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 157 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET4", + "CAM_VDIG4"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear_aux: qcom,eeprom@5 { + cell-index = <5>; + reg = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_s2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 2856000 0>; + rgltr-max-voltage = <1800000 4000000 3008000 0>; + rgltr-load-current = <180000 2000000 519000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_triple_rear>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_triple_rear>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 157 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET5", + "CAM_VDIG5"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear_aux2: qcom,eeprom@6 { + cell-index = <6>; + reg = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_s2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 2856000 0>; + rgltr-max-voltage = <1800000 4000000 3008000 0>; + rgltr-load-current = <180000 2000000 519000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_triple_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_triple_rear>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 157 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET6", + "CAM_VDIG6"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear>; + ois-src = <&ois_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&pm8150l_l1>; + cam_bob-supply = <&pm8150l_bob>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <0 2800000 1200000 0 3008000>; + rgltr-max-voltage = <0 2800000 1200000 0 4000000>; + rgltr-load-current = <0 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_bob-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <0 2856000 1200000 0 3008000>; + rgltr-max-voltage = <0 2856000 1200000 0 4000000>; + rgltr-load-current = <0 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + actuator-src = <&actuator_front>; + led-flash-src = <&led_flash_front>; + cam_vio-supply = <&pm8150l_l1>; + cam_bob-supply = <&pm8150l_bob>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <0 2856000 1200000 0 3008000>; + rgltr-max-voltage = <0 2856000 1200000 0 4000000>; + rgltr-load-current = <0 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x03>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + led-flash-src = <&led_flash_iris>; + cam_vio-supply = <&pm8150l_l1>; + cam_bob-supply = <&pm8150l_bob>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <0 2800000 1200000 0 3008000>; + rgltr-max-voltage = <0 2800000 1200000 0 4000000>; + rgltr-load-current = <0 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_iris>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_active_iris>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + reg = <0x4>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear>; + actuator-src = <&actuator_triple_rear>; + eeprom-src = <&eeprom_triple_rear>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_s2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 2856000 0>; + rgltr-max-voltage = <1800000 4000000 3008000 0>; + rgltr-load-current = <180000 2000000 519000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_triple_rear>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_triple_rear>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 157 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET4", + "CAM_VDIG4"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + reg = <0x5>; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear_aux>; + actuator-src = <&actuator_triple_rear_aux>; + eeprom-src = <&eeprom_triple_rear_aux>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_s2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 2856000 0>; + rgltr-max-voltage = <1800000 4000000 3008000 0>; + rgltr-load-current = <180000 2000000 519000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_triple_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_triple_rear_aux>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&tlmm 159 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET5", + "CAM_VDIG5"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@6 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + reg = <0x06>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear_aux2>; + actuator-src = <&actuator_triple_rear_aux2>; + eeprom-src = <&eeprom_triple_rear_aux2>; + cam_vdig-supply = <&pm8009_s2>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 2856000 0>; + rgltr-max-voltage = <1800000 4000000 3008000 0>; + rgltr-load-current = <180000 2000000 519000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_triple_rear_aux2>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_triple_rear_aux2>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET6", + "VDIG6"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-camera-sensor-hdk.dtsi b/arch/arm/boot/dts/qcom/sm8150-camera-sensor-hdk.dtsi new file mode 100644 index 000000000000..04258207c3d9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-camera-sensor-hdk.dtsi @@ -0,0 +1,425 @@ +/* + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + #address-cells = <1>; + #size-cells = <1>; + + qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_front: qcom,camera-flash@2 { + cell-index = <2>; + reg = <0x02 0x00>; + compatible = "qcom,camera-flash"; + wled-flash-support; + flash-source = <&wled_flash>; + torch-source = <&wled_torch>; + switch-source = <&wled_switch>; + status = "ok"; + }; + + qcom,camera-flash@3 { + cell-index = <3>; + reg = <0x03 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash1>; + torch-source = <&pm8150l_torch1>; + switch-source = <&pm8150l_switch0>; + status = "ok"; + }; +}; + +&cam_cci0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; + + qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <2856000>; + rgltr-load-current = <0>; + }; + + qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <2856000>; + rgltr-load-current = <0>; + }; + + qcom,actuator@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <2856000>; + rgltr-load-current = <0>; + }; + + qcom,ois@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,ois"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <2856000>; + rgltr-load-current = <0>; + status = "ok"; + }; + + qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2800000 1200000 0 2856000>; + rgltr-max-voltage = <0 2800000 1200000 0 2856000>; + rgltr-load-current = <0 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-position = <0>; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2856000 1200000 0 2856000>; + rgltr-max-voltage = <0 2856000 1200000 0 2856000>; + rgltr-load-current = <0 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2856000 1200000 0 2856000>; + rgltr-max-voltage = <0 2856000 1200000 0 2856000>; + rgltr-load-current = <0 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-position = <1>; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear>; + ois-src = <&ois_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&pm8150l_l1>; + cam_bob-supply = <&pm8150l_bob>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <0 2800000 1200000 0 3008000>; + rgltr-max-voltage = <0 2800000 1200000 0 4000000>; + rgltr-load-current = <0 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_bob-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <0 2856000 1200000 0 3008000>; + rgltr-max-voltage = <0 2856000 1200000 0 4000000>; + rgltr-load-current = <0 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + actuator-src = <&actuator_front>; + led-flash-src = <&led_flash_front>; + cam_vio-supply = <&pm8150l_l1>; + cam_bob-supply = <&pm8150l_bob>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <0 2856000 1200000 0 3008000>; + rgltr-max-voltage = <0 2856000 1200000 0 4000000>; + rgltr-load-current = <0 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x03>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + led-flash-src = <&led_flash_iris>; + cam_vio-supply = <&pm8150l_l1>; + cam_bob-supply = <&pm8150l_bob>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <0 2800000 1200000 0 3008000>; + rgltr-max-voltage = <0 2800000 1200000 0 4000000>; + rgltr-load-current = <0 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_iris>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_active_iris>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-camera-sensor-mtp.dtsi b/arch/arm/boot/dts/qcom/sm8150-camera-sensor-mtp.dtsi new file mode 100644 index 000000000000..7de91fecbd1c --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-camera-sensor-mtp.dtsi @@ -0,0 +1,780 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + #address-cells = <1>; + #size-cells = <1>; + + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_front: qcom,camera-flash@2 { + cell-index = <2>; + reg = <0x02 0x00>; + compatible = "qcom,camera-flash"; + wled-flash-support; + flash-source = <&wled_flash>; + torch-source = <&wled_torch>; + switch-source = <&wled_switch>; + status = "ok"; + }; + + led_flash_iris: qcom,camera-flash@3 { + cell-index = <3>; + reg = <0x03 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash1>; + torch-source = <&pm8150l_torch1>; + switch-source = <&pm8150l_switch0>; + status = "ok"; + }; + + led_flash_triple_rear: qcom,camera-flash@4 { + cell-index = <4>; + reg = <0x04 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@5 { + cell-index = <5>; + reg = <0x05 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@6 { + cell-index = <6>; + reg = <0x06 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + actuator_triple_rear_regulator: gpio-regulator@4 { + compatible = "regulator-fixed"; + reg = <0x04 0x00>; + regulator-name = "actuator_triple_rear_regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&tlmm 158 0>; + vin-supply = <&pm8150l_bob>; + }; + + actuator_triple_rear_aux_regulator: gpio-regulator@5 { + compatible = "regulator-fixed"; + reg = <0x05 0x00>; + regulator-name = "actuator_triple_rear_aux_regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&tlmm 160 0>; + vin-supply = <&pm8150l_bob>; + }; + + actuator_triple_rear_aux2_regulator: gpio-regulator@6 { + compatible = "regulator-fixed"; + status = "disable"; + reg = <0x06 0x00>; + regulator-name = "actuator_triple_rear_aux2_regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <135>; + enable-active-high; + gpio = <&tlmm 24 0>; + vin-supply = <&pm8150l_bob>; + }; +}; + +&cam_cci0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; + + actuator_rear: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <2856000>; + rgltr-load-current = <0>; + }; + + actuator_rear_aux: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <2856000>; + rgltr-load-current = <0>; + }; + + actuator_front: qcom,actuator@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <2856000>; + rgltr-load-current = <0>; + }; + + actuator_triple_rear: qcom,actuator@4 { + cell-index = <4>; + reg = <0x4>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&actuator_triple_rear_regulator>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + }; + + actuator_triple_rear_aux: qcom,actuator@5 { + cell-index = <5>; + reg = <0x5>; + compatible = "qcom,actuator"; + cci-device = <1>; + cci-master = <1>; + cam_vaf-supply = <&actuator_triple_rear_aux_regulator>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + }; + + actuator_triple_rear_aux2: qcom,actuator@6 { + cell-index = <6>; + reg = <0x6>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&actuator_triple_rear_aux2_regulator>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + }; + + ois_rear: qcom,ois@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,ois"; + cci-master = <0>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <2856000>; + rgltr-load-current = <0>; + status = "ok"; + }; + + eeprom_rear: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2800000 1200000 0 2856000>; + rgltr-max-voltage = <0 2800000 1200000 0 2856000>; + rgltr-load-current = <0 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2856000 1200000 0 2856000>; + rgltr-max-voltage = <0 2856000 1200000 0 2856000>; + rgltr-load-current = <0 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2856000 1200000 0 2856000>; + rgltr-max-voltage = <0 2856000 1200000 0 2856000>; + rgltr-load-current = <0 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-position = <1>; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear: qcom,eeprom@4 { + cell-index = <4>; + reg = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_s2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 2856000 0>; + rgltr-max-voltage = <1800000 4000000 3008000 0>; + rgltr-load-current = <180000 2000000 519000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_triple_rear>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_triple_rear>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 157 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET4", + "CAM_VDIG4"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear_aux: qcom,eeprom@5 { + cell-index = <5>; + reg = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_s2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 2856000 0>; + rgltr-max-voltage = <1800000 4000000 3008000 0>; + rgltr-load-current = <180000 2000000 519000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_triple_rear>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_triple_rear>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 157 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET5", + "CAM_VDIG5"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear_aux2: qcom,eeprom@6 { + cell-index = <6>; + reg = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_s2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 2856000 0>; + rgltr-max-voltage = <1800000 4000000 3008000 0>; + rgltr-load-current = <180000 2000000 519000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_triple_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_triple_rear>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 157 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET6", + "CAM_VDIG6"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear>; + ois-src = <&ois_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&pm8150l_l1>; + cam_bob-supply = <&pm8150l_bob>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <0 2800000 1200000 0 3008000>; + rgltr-max-voltage = <0 2800000 1200000 0 4000000>; + rgltr-load-current = <0 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_bob-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <0 2856000 1200000 0 3008000>; + rgltr-max-voltage = <0 2856000 1200000 0 4000000>; + rgltr-load-current = <0 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + actuator-src = <&actuator_front>; + led-flash-src = <&led_flash_front>; + cam_vio-supply = <&pm8150l_l1>; + cam_bob-supply = <&pm8150l_bob>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <0 2856000 1200000 0 3008000>; + rgltr-max-voltage = <0 2856000 1200000 0 4000000>; + rgltr-load-current = <0 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x03>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + led-flash-src = <&led_flash_iris>; + cam_vio-supply = <&pm8150l_l1>; + cam_bob-supply = <&pm8150l_bob>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <0 2800000 1200000 0 3008000>; + rgltr-max-voltage = <0 2800000 1200000 0 4000000>; + rgltr-load-current = <0 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_iris>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_iris>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&tlmm 26 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "IMG_START"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + reg = <0x4>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear>; + actuator-src = <&actuator_triple_rear>; + eeprom-src = <&eeprom_triple_rear>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_s2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 2856000 0>; + rgltr-max-voltage = <1800000 4000000 3008000 0>; + rgltr-load-current = <180000 2000000 519000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_triple_rear>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_triple_rear>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 157 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET4", + "CAM_VDIG4"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + reg = <0x5>; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear_aux>; + actuator-src = <&actuator_triple_rear_aux>; + eeprom-src = <&eeprom_triple_rear_aux>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_s2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 2856000 0>; + rgltr-max-voltage = <1800000 4000000 3008000 0>; + rgltr-load-current = <180000 2000000 519000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_triple_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_triple_rear_aux>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&tlmm 159 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET5", + "CAM_VDIG5"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@6 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + reg = <0x06>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear_aux2>; + actuator-src = <&actuator_triple_rear_aux2>; + eeprom-src = <&eeprom_triple_rear_aux2>; + cam_vdig-supply = <&pm8009_s2>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 3008000 2856000 0>; + rgltr-max-voltage = <1800000 4000000 3008000 0>; + rgltr-load-current = <180000 2000000 519000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_triple_rear_aux2>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_triple_rear_aux2>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-vdig = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET6", + "VDIG6"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-camera-sensor-qrd.dtsi b/arch/arm/boot/dts/qcom/sm8150-camera-sensor-qrd.dtsi new file mode 100644 index 000000000000..51751d45d947 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-camera-sensor-qrd.dtsi @@ -0,0 +1,415 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + #address-cells = <1>; + #size-cells = <1>; + + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_iris: qcom,camera-flash@3 { + cell-index = <3>; + reg = <0x03 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash1>; + torch-source = <&pm8150l_torch1>; + switch-source = <&pm8150l_switch0>; + status = "ok"; + }; +}; + +&cam_cci0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; + + actuator_rear: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <2856000>; + rgltr-load-current = <0>; + }; + + actuator_rear_aux: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <2856000>; + rgltr-load-current = <0>; + }; + + actuator_front: qcom,actuator@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,actuator"; + cci-device = <1>; + cci-master = <0>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <2856000>; + rgltr-load-current = <0>; + }; + + ois_rear: qcom,ois@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,ois"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <2856000>; + rgltr-load-current = <0>; + status = "ok"; + }; + + eeprom_rear: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2800000 1200000 0 2856000>; + rgltr-max-voltage = <0 2800000 1200000 0 2856000>; + rgltr-load-current = <0 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-position = <0>; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2856000 1200000 0 2856000>; + rgltr-max-voltage = <0 2856000 1200000 0 2856000>; + rgltr-load-current = <0 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8009_s2>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2856000 1200000 0 2856000>; + rgltr-max-voltage = <0 2856000 1200000 0 2856000>; + rgltr-load-current = <0 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-position = <1>; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear>; + ois-src = <&ois_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&pm8150l_l1>; + cam_bob-supply = <&pm8150l_bob>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <0 2800000 1200000 0 3008000>; + rgltr-max-voltage = <0 2800000 1200000 0 4000000>; + rgltr-load-current = <0 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_bob-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <0 2856000 1200000 0 3008000>; + rgltr-max-voltage = <0 2856000 1200000 0 4000000>; + rgltr-load-current = <0 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + actuator-src = <&actuator_front>; + cam_vio-supply = <&pm8150l_l1>; + cam_bob-supply = <&pm8150l_bob>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <0 2856000 1200000 0 3008000>; + rgltr-max-voltage = <0 2856000 1200000 0 4000000>; + rgltr-load-current = <0 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x03>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + led-flash-src = <&led_flash_iris>; + cam_vio-supply = <&pm8150l_l1>; + cam_bob-supply = <&pm8150l_bob>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <0 2800000 1200000 0 3008000>; + rgltr-max-voltage = <0 2800000 1200000 0 4000000>; + rgltr-load-current = <0 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_iris>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_active_iris>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-camera.dtsi b/arch/arm/boot/dts/qcom/sm8150-camera.dtsi new file mode 100644 index 000000000000..51944ac4c0cb --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-camera.dtsi @@ -0,0 +1,1248 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + cam_csiphy0: qcom,csiphy@ac65000 { + cell-index = <0>; + compatible = "qcom,csiphy-v1.1", "qcom,csiphy"; + reg = <0x0ac65000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x65000>; + interrupts = <0 477 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&titan_top_gdsc>; + regulator-names = "gdscr"; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&pm8150l_l3>; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY0_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "turbo"; + clock-rates = + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy@ac66000{ + cell-index = <1>; + compatible = "qcom,csiphy-v1.1", "qcom,csiphy"; + reg = <0xac66000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x66000>; + interrupts = <0 478 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&titan_top_gdsc>; + regulator-names = "gdscr"; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&pm8150l_l3>; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY1_CLK>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "turbo"; + clock-rates = + <400000000 0 300000000 0>; + + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy@ac67000 { + cell-index = <2>; + compatible = "qcom,csiphy-v1.1", "qcom,csiphy"; + reg = <0xac67000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x67000>; + interrupts = <0 479 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&titan_top_gdsc>; + regulator-names = "gdscr"; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&pm8150l_l3>; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY2_CLK>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "turbo"; + clock-rates = + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy@ac68000 { + cell-index = <3>; + compatible = "qcom,csiphy-v1.1", "qcom,csiphy"; + reg = <0xac68000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x68000>; + interrupts = <0 448 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&titan_top_gdsc>; + regulator-names = "gdscr"; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&pm8150l_l3>; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY3_CLK>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + src-clock-name = "csi3phytimer_clk_src"; + clock-cntl-level = "turbo"; + clock-rates = + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci@ac4a000 { + cell-index = <0>; + compatible = "qcom,cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xac4a000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x4a000>; + interrupt-names = "cci"; + interrupts = <0 460 0>; + status = "ok"; + gdscr-supply = <&titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&clock_camcc CAM_CC_CCI_0_CLK_SRC>, + <&clock_camcc CAM_CC_CCI_0_CLK>; + clock-names = "cci_0_clk_src", + "cci_0_clk"; + src-clock-name = "cci_0_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <37500000 0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 17 0>, + <&tlmm 18 0>, + <&tlmm 19 0>, + <&tlmm 20 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci@ac4b000 { + cell-index = <1>; + compatible = "qcom,cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xac4b000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x4b000>; + interrupt-names = "cci"; + interrupts = <0 271 0>; + status = "ok"; + gdscr-supply = <&titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&clock_camcc CAM_CC_CCI_1_CLK_SRC>, + <&clock_camcc CAM_CC_CCI_1_CLK>; + clock-names = "cci_1_clk_src", + "cci_1_clk"; + src-clock-name = "cci_1_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <37500000 0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci2_active &cci3_active>; + pinctrl-1 = <&cci2_suspend &cci3_suspend>; + gpios = <&tlmm 31 0>, + <&tlmm 32 0>, + <&tlmm 33 0>, + <&tlmm 34 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA2", + "CCI_I2C_CLK2", + "CCI_I2C_DATA3", + "CCI_I2C_CLK3"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu"; + status = "ok"; + + msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x840 0x620>, + <&apps_smmu 0x860 0x620>, + <&apps_smmu 0xA40 0x620>, + <&apps_smmu 0xA60 0x620>, + <&apps_smmu 0xC40 0x620>, + <&apps_smmu 0xC60 0x620>, + <&apps_smmu 0xE40 0x620>, + <&apps_smmu 0xE60 0x620>; + label = "ife"; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1180 0x20>, + <&apps_smmu 0x11A0 0x20>; + label = "jpeg"; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_icp_fw { + compatible = "qcom,msm-cam-smmu-fw-dev"; + label="icp"; + memory-region = <&pil_camera_mem>; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1222 0x0>, + <&apps_smmu 0x1080 0x20>, + <&apps_smmu 0x10A0 0x20>, + <&apps_smmu 0x1100 0x20>, + <&apps_smmu 0x1120 0x20>, + <&apps_smmu 0x10C0 0x0>, + <&apps_smmu 0x1140 0x0>; + label = "icp"; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-firmware { + /* Firmware region is 5MB */ + iova-region-name = "firmware"; + iova-region-start = <0x0>; + iova-region-len = <0x500000>; + iova-region-id = <0x0>; + status = "ok"; + }; + + iova-mem-region-shared { + /* Shared region is 200MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0xc800000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-secondary-heap { + /* Secondary heap region is 1MB long */ + iova-region-name = "secheap"; + iova-region-start = <0x13C00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x4>; + status = "ok"; + }; + + iova-mem-region-io { + /* IO region is approximately 3 GB */ + iova-region-name = "io"; + iova-region-start = <0x13E00000>; + iova-region-len = <0xa6a00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x13D00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x1000 0x0>; + label = "cpas-cdm0"; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + label = "cam-secure"; + qcom,secure-cb; + }; + + msm_cam_smmu_fd { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x11C0 0x20>, + <&apps_smmu 0x11E0 0x20>; + label = "fd"; + fd_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_lrme { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x10e0 0x0>, + <&apps_smmu 0x1160 0x0>; + label = "lrme"; + lrme_iova_mem_map: iova-mem-map { + iova-mem-region-shared { + /* Shared region is 100MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x6400000>; + iova-region-id = <0x1>; + status = "ok"; + }; + /* IO region is approximately 3.3 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0xd800000>; + iova-region-len = <0xd2800000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + }; + + qcom,cam-cpas@ac40000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + status = "ok"; + reg-names = "cam_cpas_top", "cam_camnoc"; + reg = <0xac40000 0x1000>, + <0xac42000 0x5000>; + reg-cam-base = <0x40000 0x42000>; + interrupt-names = "cpas_camnoc"; + interrupts = <0 459 0>; + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = + "gcc_ahb_clk", + "gcc_axi_hf_clk", + "gcc_axi_sf_clk", + "slow_ahb_clk_src", + "cpas_ahb_clk", + "camnoc_axi_clk_src", + "camnoc_axi_clk"; + clocks = + <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_HF_AXI_CLK>, + <&clock_gcc GCC_CAMERA_SF_AXI_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; + src-clock-name = "camnoc_axi_clk_src"; + clock-rates = + <0 0 0 0 0 0 0>, + <0 0 0 19200000 0 19200000 0>, + <0 0 0 80000000 0 150000000 0>, + <0 0 0 80000000 0 266670000 0>, + <0 0 0 80000000 0 320000000 0>, + <0 0 0 80000000 0 400000000 0>, + <0 0 0 80000000 0 480000000 0>; + clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + qcom,msm-bus,name = "cam_ahb"; + qcom,msm-bus,num-cases = <7>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + , + , + , + , + ; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "suspend", + "minsvs", "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", + "cci0", "cci1", + "csid0", "csid1", "csid2", "csid3", + "ife0", "ife1", "ife2", "ife3", + "ipe0", "ipe1", "cam-cdm-intf0", "cpas-cdm0", + "bps0", "icp0", "jpeg-dma0", "jpeg-enc0", + "fd0", "lrmecpas0"; + client-axi-port-names = + "cam_hf_1", "cam_hf_2", "cam_hf_1", "cam_hf_2", + "cam_sf_1", "cam_sf_1", + "cam_hf_1", "cam_hf_2", "cam_hf_1", "cam_hf_2", + "cam_hf_1", "cam_hf_2", "cam_hf_1", "cam_hf_2", + "cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1", + "cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1", + "cam_sf_1", "cam_sf_1"; + client-bus-camnoc-based; + qcom,axi-port-list { + qcom,axi-port1 { + qcom,axi-port-name = "cam_hf_1"; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + qcom,msm-bus,name = "cam_hf_1_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + qcom,axi-port-camnoc { + qcom,msm-bus,name = "cam_hf_1_camnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + qcom,axi-port2 { + qcom,axi-port-name = "cam_hf_2"; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + qcom,msm-bus,name = "cam_hf_2_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + qcom,axi-port-camnoc { + qcom,msm-bus,name = "cam_hf_2_camnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + qcom,axi-port3 { + qcom,axi-port-name = "cam_sf_1"; + qcom,axi-port-mnoc { + qcom,msm-bus,name = "cam_sf_1_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + qcom,axi-port-camnoc { + qcom,msm-bus,name = "cam_sf_1_camnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc", + "fd", + "lrmecdm"; + status = "ok"; + }; + + qcom,cpas-cdm0@ac48000 { + cell-index = <0>; + compatible = "qcom,cam170-cpas-cdm0"; + label = "cpas-cdm"; + reg = <0xac48000 0x1000>; + reg-names = "cpas-cdm"; + reg-cam-base = <0x48000>; + interrupts = <0 461 0>; + interrupt-names = "cpas-cdm"; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = "cam_cc_cpas_slow_ahb_clk", + "cam_cc_cpas_ahb_clk"; + clocks = <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <0 0>; + clock-cntl-level = "svs"; + cdm-client-names = "ife"; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; + + cam_csid0: qcom,csid0@acb3000 { + cell-index = <0>; + compatible = "qcom,csid175"; + reg-names = "csid"; + reg = <0xacb3000 0x1000>; + reg-cam-base = <0xb3000>; + interrupt-names = "csid"; + interrupts = <0 464 0>; + regulator-names = "camss", "ife0"; + camss-supply = <&titan_top_gdsc>; + ife0-supply = <&ife_0_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <400000000 0 0 0 400000000 0 0>, + <400000000 0 0 0 558000000 0 0>, + <480000000 0 0 0 637000000 0 0>, + <600000000 0 0 0 760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe0: qcom,vfe0@acaf000 { + cell-index = <0>; + compatible = "qcom,vfe175"; + reg-names = "ife", "cam_camnoc"; + reg = <0xacaf000 0x4000>, + <0xac42000 0x5000>; + reg-cam-base = <0xaf000 0x42000>; + interrupt-names = "ife"; + interrupts = <0 465 0>; + regulator-names = "camss", "ife0"; + camss-supply = <&titan_top_gdsc>; + ife0-supply = <&ife_0_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <400000000 0 0>, + <558000000 0 0>, + <637000000 0 0>, + <760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <760000000>; + status = "ok"; + }; + + cam_csid1: qcom,csid1@acba000 { + cell-index = <1>; + compatible = "qcom,csid175"; + reg-names = "csid"; + reg = <0xacba000 0x1000>; + reg-cam-base = <0xba000>; + interrupt-names = "csid"; + interrupts = <0 466 0>; + regulator-names = "camss", "ife1"; + camss-supply = <&titan_top_gdsc>; + ife1-supply = <&ife_1_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <400000000 0 0 0 400000000 0 0>, + <400000000 0 0 0 558000000 0 0>, + <480000000 0 0 0 637000000 0 0>, + <600000000 0 0 0 760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe1: qcom,vfe1@acb6000 { + cell-index = <1>; + compatible = "qcom,vfe175"; + reg-names = "ife", "cam_camnoc"; + reg = <0xacb6000 0x4000>, + <0xac42000 0x5000>; + reg-cam-base = <0xb6000 0x42000>; + interrupt-names = "ife"; + interrupts = <0 467 0>; + regulator-names = "camss", "ife1"; + camss-supply = <&titan_top_gdsc>; + ife1-supply = <&ife_1_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <400000000 0 0>, + <558000000 0 0>, + <637000000 0 0>, + <760000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&clock_camcc CAM_CC_IFE_1_DSP_CLK>; + clock-rates-option = <760000000>; + status = "ok"; + }; + + cam_csid_lite0: qcom,csid-lite0@acc8000 { + cell-index = <2>; + compatible = "qcom,csid-lite175"; + reg-names = "csid-lite"; + reg = <0xacc8000 0x1000>; + reg-cam-base = <0xc8000>; + interrupt-names = "csid-lite"; + interrupts = <0 468 0>; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_LITE_0_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_0_CSID_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_0_CLK>; + clock-rates = + <400000000 0 0 0 320000000 0>, + <400000000 0 0 0 400000000 0>, + <480000000 0 0 0 480000000 0>, + <600000000 0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite0: qcom,vfe-lite0@acc4000 { + cell-index = <2>; + compatible = "qcom,vfe-lite175"; + reg-names = "ife-lite"; + reg = <0xacc4000 0x4000>; + reg-cam-base = <0xc4000>; + interrupt-names = "ife-lite"; + interrupts = <0 469 0>; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_LITE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_0_CLK>; + clock-rates = + <320000000 0>, + <400000000 0>, + <480000000 0>, + <600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_csid_lite1: qcom,csid-lite1@accf000 { + cell-index = <3>; + compatible = "qcom,csid-lite175"; + reg-names = "csid-lite"; + reg = <0xaccf000 0x1000>; + reg-cam-base = <0xcf000>; + interrupt-names = "csid-lite"; + interrupts = <0 359 0>; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_LITE_1_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_1_CSID_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_1_CLK>; + clock-rates = + <400000000 0 0 0 320000000 0>, + <400000000 0 0 0 400000000 0>, + <480000000 0 0 0 480000000 0>, + <600000000 0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite1: qcom,vfe-lite1@accb000 { + cell-index = <3>; + compatible = "qcom,vfe-lite175"; + reg-names = "ife-lite"; + reg = <0xaccb000 0x4000>; + reg-cam-base = <0xcb000>; + interrupt-names = "ife-lite"; + interrupts = <0 360 0>; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_LITE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_1_CLK>; + clock-rates = + <320000000 0>, + <400000000 0>, + <480000000 0>, + <600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,a5", + "qcom,ipe0", + "qcom,ipe1", + "qcom,bps"; + num-a5 = <1>; + num-ipe = <2>; + num-bps = <1>; + icp_pc_en; + ipe_bps_pc_en; + status = "ok"; + }; + + cam_a5: qcom,a5@ac00000 { + cell-index = <0>; + compatible = "qcom,cam-a5"; + reg = <0xac00000 0x6000>, + <0xac10000 0x8000>, + <0xac18000 0x3000>; + reg-names = "a5_qgic", "a5_sierra", "a5_csr"; + reg-cam-base = <0x00000 0x10000 0x18000>; + interrupts = <0 463 0>; + interrupt-names = "a5"; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = + "soc_fast_ahb", + "icp_ahb_clk", + "icp_clk_src", + "icp_clk"; + clocks = + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_ICP_AHB_CLK>, + <&clock_camcc CAM_CC_ICP_CLK_SRC>, + <&clock_camcc CAM_CC_ICP_CLK>; + + clock-rates = + <200000000 0 400000000 0>, + <400000000 0 600000000 0>; + clock-cntl-level = "svs", "turbo"; + fw_name = "CAMERA_ICP.elf"; + ubwc-cfg = <0x7B 0x1EF>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0 { + cell-index = <0>; + compatible = "qcom,cam-ipe"; + reg = <0xac87000 0x3000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x87000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&ipe_0_gdsc>; + clock-names = + "ipe_0_ahb_clk", + "ipe_0_areg_clk", + "ipe_0_axi_clk", + "ipe_0_clk_src", + "ipe_0_clk"; + src-clock-name = "ipe_0_clk_src"; + clock-control-debugfs = "true"; + clocks = + <&clock_camcc CAM_CC_IPE_0_AHB_CLK>, + <&clock_camcc CAM_CC_IPE_0_AREG_CLK>, + <&clock_camcc CAM_CC_IPE_0_AXI_CLK>, + <&clock_camcc CAM_CC_IPE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IPE_0_CLK>; + + clock-rates = + <0 0 0 300000000 0>, + <0 0 0 475000000 0>, + <0 0 0 520000000 0>, + <0 0 0 600000000 0>, + <0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + status = "ok"; + }; + + cam_ipe1: qcom,ipe1 { + cell-index = <1>; + compatible = "qcom,cam-ipe"; + reg = <0xac91000 0x3000>; + reg-names = "ipe1_top"; + reg-cam-base = <0x91000>; + regulator-names = "ipe1-vdd"; + ipe1-vdd-supply = <&ipe_1_gdsc>; + clock-names = + "ipe_1_ahb_clk", + "ipe_1_areg_clk", + "ipe_1_axi_clk", + "ipe_1_clk_src", + "ipe_1_clk"; + src-clock-name = "ipe_1_clk_src"; + clock-control-debugfs = "true"; + clocks = + <&clock_camcc CAM_CC_IPE_1_AHB_CLK>, + <&clock_camcc CAM_CC_IPE_1_AREG_CLK>, + <&clock_camcc CAM_CC_IPE_1_AXI_CLK>, + <&clock_camcc CAM_CC_IPE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IPE_1_CLK>; + + clock-rates = + <0 0 0 300000000 0>, + <0 0 0 475000000 0>, + <0 0 0 520000000 0>, + <0 0 0 600000000 0>, + <0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + status = "ok"; + }; + + cam_bps: qcom,bps { + cell-index = <0>; + compatible = "qcom,cam-bps"; + reg = <0xac6f000 0x3000>; + reg-names = "bps_top"; + reg-cam-base = <0x6f000>; + regulator-names = "bps-vdd"; + bps-vdd-supply = <&bps_gdsc>; + clock-names = + "bps_ahb_clk", + "bps_areg_clk", + "bps_axi_clk", + "bps_clk_src", + "bps_clk"; + src-clock-name = "bps_clk_src"; + clock-control-debugfs = "true"; + clocks = + <&clock_camcc CAM_CC_BPS_AHB_CLK>, + <&clock_camcc CAM_CC_BPS_AREG_CLK>, + <&clock_camcc CAM_CC_BPS_AXI_CLK>, + <&clock_camcc CAM_CC_BPS_CLK_SRC>, + <&clock_camcc CAM_CC_BPS_CLK>; + + clock-rates = + <0 0 0 200000000 0>, + <0 0 0 400000000 0>, + <0 0 0 480000000 0>, + <0 0 0 600000000 0>, + <0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc", + "qcom,jpegdma"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + cam_jpeg_enc: qcom,jpegenc@ac4e000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc"; + reg-names = "jpege_hw"; + reg = <0xac4e000 0x4000>; + reg-cam-base = <0x4e000>; + interrupt-names = "jpeg"; + interrupts = <0 474 0>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = + "jpegenc_clk_src", + "jpegenc_clk"; + clocks = + <&clock_camcc CAM_CC_JPEG_CLK_SRC>, + <&clock_camcc CAM_CC_JPEG_CLK>; + + clock-rates = <600000000 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "nominal"; + status = "ok"; + }; + + cam_jpeg_dma: qcom,jpegdma@0xac52000{ + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma"; + reg-names = "jpegdma_hw"; + reg = <0xac52000 0x4000>; + reg-cam-base = <0x52000>; + interrupt-names = "jpegdma"; + interrupts = <0 475 0>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = + "jpegdma_clk_src", + "jpegdma_clk"; + clocks = + <&clock_camcc CAM_CC_JPEG_CLK_SRC>, + <&clock_camcc CAM_CC_JPEG_CLK>; + + clock-rates = <600000000 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "nominal"; + status = "ok"; + }; + + qcom,cam-fd { + compatible = "qcom,cam-fd"; + compat-hw-name = "qcom,fd"; + num-fd = <1>; + status = "ok"; + }; + + cam_fd: qcom,fd@ac5a000 { + cell-index = <0>; + compatible = "qcom,fd501"; + reg-names = "fd_core", "fd_wrapper"; + reg = <0xac5a000 0x1000>, + <0xac5b000 0x400>; + reg-cam-base = <0x5a000 0x5b000>; + interrupt-names = "fd"; + interrupts = <0 462 0>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = + "fd_core_clk_src", + "fd_core_clk", + "fd_core_uar_clk"; + clocks = + <&clock_camcc CAM_CC_FD_CORE_CLK_SRC>, + <&clock_camcc CAM_CC_FD_CORE_CLK>, + <&clock_camcc CAM_CC_FD_CORE_UAR_CLK>; + src-clock-name = "fd_core_clk_src"; + clock-control-debugfs = "true"; + clock-cntl-level = "svs", "svs_l1", "turbo"; + clock-rates = + <400000000 0 0>, + <480000000 0 0>, + <600000000 0 0>; + status = "ok"; + }; + + qcom,cam-lrme { + compatible = "qcom,cam-lrme"; + arch-compat = "lrme"; + status = "ok"; + }; + + cam_lrme: qcom,lrme@ac6b000 { + cell-index = <0>; + compatible = "qcom,lrme"; + reg-names = "lrme"; + reg = <0xac6b000 0xa00>; + reg-cam-base = <0x6b000>; + interrupt-names = "lrme"; + interrupts = <0 476 0>; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = + "lrme_clk_src", + "lrme_clk"; + clocks = + <&clock_camcc CAM_CC_LRME_CLK_SRC>, + <&clock_camcc CAM_CC_LRME_CLK>; + clock-rates = + <240000000 0>, + <300000000 0>, + <320000000 0>, + <400000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "lrme_clk_src"; + status = "ok"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-cdp-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/sm8150-cdp-audio-overlay.dtsi new file mode 100644 index 000000000000..6680b32ae3d8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-cdp-audio-overlay.dtsi @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm8150-audio-overlay.dtsi" + +&snd_934x { + qcom,model = "sm8150-tavil-cdp-snd-card"; + qcom,us-euro-gpios = <&tavil_us_euro_switch>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-cdp-overlay.dts b/arch/arm/boot/dts/qcom/sm8150-cdp-overlay.dts new file mode 100644 index 000000000000..df760237d9a7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-cdp-overlay.dts @@ -0,0 +1,32 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-cdp.dtsi" +#include "sm8150-cdp-audio-overlay.dtsi" + +/ { + model = "CDP"; + compatible = "qcom,sm8150-cdp", "qcom,sm8150", "qcom,cdp"; + qcom,board-id = <1 0>; +}; + +&dsi_sharp_4k_dsc_cmd_display { + qcom,dsi-display-active; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-cdp.dts b/arch/arm/boot/dts/qcom/sm8150-cdp.dts new file mode 100644 index 000000000000..f74b0f047d1d --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-cdp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150.dtsi" +#include "sm8150-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150 CDP"; + compatible = "qcom,sm8150-cdp", "qcom,sm8150", "qcom,cdp"; + qcom,board-id = <1 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-cdp.dtsi b/arch/arm/boot/dts/qcom/sm8150-cdp.dtsi new file mode 100644 index 000000000000..0446a279deb0 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-cdp.dtsi @@ -0,0 +1,663 @@ +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "sm8150-pmic-overlay.dtsi" +#include "sm8150-sde-display.dtsi" +#include "sm8150-camera-sensor-cdp.dtsi" +#include "sm8150-thermal-overlay.dtsi" + +&qupv3_se12_2uart { + status = "ok"; +}; + +&vendor { + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-core-supply = <&pm8150_l7>; + qca,bt-vdd-pa-supply = <&pm8150l_l2>; + qca,bt-vdd-ldo-supply = <&pm8150l_l11>; + + qca,bt-vdd-core-voltage-level = <1800000 1800000>; + qca,bt-vdd-pa-voltage-level = <1304000 1304000>; + qca,bt-vdd-ldo-voltage-level = <3312000 3312000>; + + qca,bt-vdd-core-current-level = <0>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <0>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <0>; /* LPM/PFM */ + }; + + extcon_usb1: extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + vbus-gpio = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>; + id-gpio = <&tlmm 101 GPIO_ACTIVE_HIGH>; + vbus-out-gpio = <&pm8150_gpios 9 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&usb2_vbus_det_default + &usb2_id_det_default + &usb2_vbus_boost_default>; + }; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + +&qupv3_se3_spi { + status = "ok"; +}; + +&qupv3_se4_i2c { + status = "ok"; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_home_default + &key_vol_up_default>; + + home { + label = "home"; + gpios = <&pm8150_gpios 1 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + + vol_up { + label = "volume_up"; + gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; + + qcom,qbt1000 { + compatible = "qcom,qbt1000"; + clock-names = "core", "iface"; + clock-frequency = <25000000>; + qcom,ipc-gpio = <&tlmm 118 0>; + qcom,finger-detect-gpio = <&pm8150_gpios 1 0>; + status = "disabled"; + }; +}; + +&dsi_panel_pwr_supply_vdd_no_labibb { + qcom,panel-supply-entry@1 { + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + }; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_nt35597_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_nt35597_truly_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_nt35597_truly_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sharp_1080_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_vdd_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; + qcom,panel-sec-mode-gpio = <&tlmm 77 0>; + qcom,platform-sec-reset-gpio = <&tlmm 66 0>; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_vdd_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; + qcom,panel-sec-mode-gpio = <&tlmm 77 0>; + qcom,platform-sec-reset-gpio = <&tlmm 66 0>; +}; + +&dsi_nt35695b_truly_fhd_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_vdd_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; + qcom,panel-sec-mode-gpio = <&tlmm 77 0>; + qcom,platform-sec-reset-gpio = <&tlmm 66 0>; +}; + +&qupv3_se9_i2c { + status = "ok"; + + #address-cells = <1>; + #size-cells = <0>; + + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 47 0x00>; + qcom,nq-ven = <&tlmm 41 0x00>; + qcom,nq-firm = <&tlmm 48 0x00>; + qcom,nq-clkreq = <&tlmm 113 0x00>; + qcom,nq-esepwr = <&tlmm 42 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <47 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active + &nfc_clk_req_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend + &nfc_clk_req_suspend>; + }; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4"; + + vdda-phy-supply = <&pm8150_l5>; + vdda-phy-always-on; + vdda-pll-supply = <&pm8150l_l3>; + vdda-phy-max-microamp = <90200>; + vdda-pll-max-microamp = <19000>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8150_l10>; + vcc-voltage-level = <2504000 2950000>; + vcc-low-voltage-sup; + vccq-supply = <&pm8150_l9>; + vccq2-supply = <&pm8150_s4>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <700000>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&pm8150_l9>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm8150l_l9>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8150l_l6>; + qcom,vdd-io-voltage-level = <1808000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>; + + cd-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; + +&spmi_debug_bus { + status = "ok"; +}; + +&pm8150l_wled { + qcom,string-cfg= <7>; + qcom,leds-per-string = <6>; + status = "ok"; +}; + +&pm8150l_lcdb { + status = "ok"; +}; + +&pm8150b_charger { + qcom,batteryless-platform; + io-channels = <&pm8150b_vadc ADC_USB_IN_V_16>, + <&pm8150b_vadc ADC_USB_IN_I>, + <&pm8150b_vadc ADC_CHG_TEMP>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "chg_temp"; +}; + +&pm8150b_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + wp_therm { + reg = ; + label = "wp_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + chg_sbux { + reg = ; + label = "chg_sbux"; + qcom,pre-scaling = <1 3>; + }; + + mid_chg_div6 { + reg = ; + label = "chg_mid"; + qcom,pre-scaling = <1 6>; + }; + + usb_in_i_uv { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + usb_in_v_div_16 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; +}; + +&pm8150_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_therm { + reg = ; + label = "skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm1 { + reg = ; + label = "pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150l_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + camera_flash_therm { + reg = ; + label = "camera_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_msm_therm { + reg = ; + label = "skin_msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm2 { + reg = ; + label = "pa_therm2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&wil6210 { + status = "ok"; +}; + +&mhi_0 { + mhi,fw-name = "debug.mbn"; +}; + +&pm8150b_adc_tm { + wp_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150_adc_tm { + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150l_adc_tm { + camera_flash_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin_msm_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm2 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + wp-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + camera-flash-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-msm-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-therm2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&usb1 { + extcon = <&extcon_usb1>; + status = "ok"; +}; + +&usb2_phy1 { + status = "ok"; +}; + +&usb_qmp_phy { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-coresight.dtsi b/arch/arm/boot/dts/qcom/sm8150-coresight.dtsi new file mode 100644 index 000000000000..38a77ef24bd4 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-coresight.dtsi @@ -0,0 +1,2795 @@ +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + + replicator_qdss: replicator@6046000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b909>; + + reg = <0x6046000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-qdss"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator0_out_tmc_etr: endpoint { + remote-endpoint= + <&tmc_etr_in_replicator0>; + }; + }; + + port@1 { + reg = <1>; + replicator0_out_replicator1_in: endpoint { + remote-endpoint= + <&replicator1_in_replicator0_out>; + }; + }; + + port@2 { + reg = <0>; + replicator0_in_tmc_etf: endpoint { + slave-mode; + remote-endpoint= + <&tmc_etf_out_replicator0>; + }; + }; + }; + }; + + replicator_qdss1: replicator@604A000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b909>; + + reg = <0x604A000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-qdss1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <1>; + replicator1_out_funnel_swao: endpoint { + remote-endpoint= + <&funnel_swao_in_replicator1_out>; + }; + }; + + port@1 { + reg = <1>; + replicator1_in_replicator0_out: endpoint { + slave-mode; + remote-endpoint= + <&replicator0_out_replicator1_in>; + }; + }; + }; + }; + + replicator_swao: replicator@6b0a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b909>; + + reg = <0x6b0a000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-swao"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* Always have EUD before funnel leading to ETR. If both + * sink are active we need to give preference to EUD + * over ETR + */ + port@0 { + reg = <1>; + replicator_swao_out_eud: endpoint { + remote-endpoint = + <&eud_in_replicator_swao>; + }; + }; + + port@1 { + reg = <0>; + replicator_swao_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_replicator_swao>; + }; + }; + + port@2 { + reg = <0>; + replicator_swao_in_tmc_etf_swao: endpoint { + slave-mode; + remote-endpoint = + <&tmc_etf_swao_out_replicator_swao>; + }; + }; + + }; + }; + + tmc_etf_swao: tmc@6b09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + + reg = <0x6b09000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etf-swao"; + coresight-csr = <&csr>; + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tmc_etf_swao_out_replicator_swao: endpoint { + remote-endpoint= + <&replicator_swao_in_tmc_etf_swao>; + }; + }; + + port@1 { + reg = <0>; + tmc_etf_swao_in_funnel_swao: endpoint { + slave-mode; + remote-endpoint= + <&funnel_swao_out_tmc_etf_swao>; + }; + }; + }; + + }; + + funnel_swao:funnel@0x6b08000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6b08000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-swao"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_swao_out_tmc_etf_swao: endpoint { + remote-endpoint = + <&tmc_etf_swao_in_funnel_swao>; + }; + }; + port@1 { + reg = <5>; + funnel_swao_in_ssc_etm0: endpoint { + slave-mode; + remote-endpoint= + <&ssc_etm0_out_funnel_swao>; + }; + }; + port@2 { + reg = <6>; + funnel_swao_in_replicator1_out: endpoint { + slave-mode; + remote-endpoint= + <&replicator1_out_funnel_swao>; + }; + }; + port@3 { + reg = <7>; + funnel_swao_in_tpda_swao: endpoint { + slave-mode; + remote-endpoint= + <&tpda_swao_out_funnel_swao>; + }; + }; + }; + }; + + tpda_swao: tpda@6b01000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6b01000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-swao"; + + qcom,tpda-atid = <71>; + qcom,dsb-elem-size = <1 32>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_swao_out_funnel_swao: endpoint { + remote-endpoint = + <&funnel_swao_in_tpda_swao>; + }; + + }; + + port@1 { + reg = <0>; + tpda_swao_in_tpdm_swao0: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_swao0_out_tpda_swao>; + }; + }; + + port@2 { + reg = <1>; + tpda_swao_in_tpdm_swao1: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_swao1_out_tpda_swao>; + }; + + }; + }; + }; + + tpdm_swao0: tpdm@6b02000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + + reg = <0x6b02000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-swao-0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_swao0_out_tpda_swao: endpoint { + remote-endpoint = <&tpda_swao_in_tpdm_swao0>; + }; + }; + }; + + tpdm_swao1: tpdm@6b03000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6b03000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name="coresight-tpdm-swao-1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_swao1_out_tpda_swao: endpoint { + remote-endpoint = <&tpda_swao_in_tpdm_swao1>; + }; + }; + }; + + tmc_etr: tmc@6048000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + + reg = <0x6048000 0x1000>, + <0x6064000 0x15000>; + reg-names = "tmc-base", "bam-base"; + + qcom,smmu-s1-bypass; + iommus = <&apps_smmu 0x05e0 0>, + <&apps_smmu 0x04a0 0>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + arm,buffer-size = <0x400000>; + + coresight-name = "coresight-tmc-etr"; + coresight-ctis = <&cti0 &cti0>; + coresight-csr = <&csr>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + port { + tmc_etr_in_replicator0: endpoint { + slave-mode; + remote-endpoint = <&replicator0_out_tmc_etr>; + }; + }; + }; + + tmc_etf: tmc@6047000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + + reg = <0x6047000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etf"; + coresight-ctis = <&cti0 &cti0>; + coresight-csr = <&csr>; + arm,default-sink; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tmc_etf_out_replicator0: endpoint { + remote-endpoint = + <&replicator0_in_tmc_etf>; + }; + }; + + port@1 { + reg = <0>; + tmc_etf_in_funnel_merg: endpoint { + slave-mode; + remote-endpoint = + <&funnel_merg_out_tmc_etf>; + }; + }; + }; + + }; + + funnel_merg: funnel@6045000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6045000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-merg"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_merg_out_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_in_funnel_merg>; + }; + }; + + port@1 { + reg = <0>; + funnel_merg_in_funnel_in0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in0_out_funnel_merg>; + }; + }; + + port@2 { + reg = <1>; + funnel_merg_in_funnel_in1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in1_out_funnel_merg>; + }; + }; + + port@3 { + reg = <2>; + funnel_merg_in_funnel_in2: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in2_out_funnel_merg>; + }; + }; + }; + }; + + stm: stm@6002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b962>; + + reg = <0x6002000 0x1000>, + <0x16280000 0x180000>, + <0x7820f0 0x4>; + reg-names = "stm-base", "stm-stimulus-base", "stm-debug-status"; + + coresight-name = "coresight-stm"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + stm_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_stm>; + }; + }; + + }; + + hwevent: hwevent@0x091866F0 { + compatible = "qcom,coresight-hwevent"; + reg = <0x091866F0 0x4>, + <0x91966F0 0x4>, + <0x9186038 0x4>, + <0x9196038 0x4>, + <0x17E00034 0x4>, + <0x18200050 0x80>, + <0x02C8D050 0x80>, + <0x0AF20050 0x80>; + reg-names = "ddr-ch0-cfg", "ddr-ch23-cfg", "ddr-ch0-ctrl", + "ddr-ch23-ctrl", "apss-testbus-mux-cfg", + "apss-rsc-hwevent-mux0-select", + "gpu-rsc-hwevent-mux0-select", + "sde-rsc-hwevent-mux0-select"; + + coresight-name = "coresight-hwevent"; + coresight-csr = <&csr>; + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + csr: csr@0x6001000 { + compatible = "qcom,coresight-csr"; + reg = <0x6001000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-csr"; + qcom,usb-bam-support; + qcom,hwctrl-set-support; + qcom,set-byte-cntr-support; + + qcom,blk-size = <1>; + }; + + swao_csr: csr@6b0e000 { + compatible = "qcom,coresight-csr"; + reg = <0x6b0e000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-swao-csr"; + qcom,timestamp-support; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,blk-size = <1>; + }; + + funnel_in0: funnel@0x6041000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6041000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in0_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in0>; + }; + }; + + port@1 { + reg = <1>; + funnel_in0_in_funnel_spss: endpoint { + slave-mode; + remote-endpoint = + <&funnel_spss_out_funnel_in0>; + }; + }; + + port@2 { + reg = <6>; + funnel_in0_in_funnel_qatb: endpoint { + slave-mode; + remote-endpoint = + <&funnel_qatb_out_funnel_in0>; + }; + }; + + port@3 { + reg = <7>; + funnel_in0_in_stm: endpoint { + slave-mode; + remote-endpoint = <&stm_out_funnel_in0>; + }; + }; + }; + }; + + funnel_in1: funnel@0x6042000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6042000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in1_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in1>; + }; + }; + port@1 { + reg = <2>; + funnel_in1_in_funnel_dl_south: endpoint { + slave-mode; + remote-endpoint = + <&funnel_dl_south_out_funnel_in1>; + }; + }; + port@2 { + reg = <3>; + funnel_in1_in_modem_etm0: endpoint { + slave-mode; + remote-endpoint = + <&modem_etm0_out_funnel_in1>; + }; + }; + port@3 { + reg = <4>; + funnel_in1_in_replicator_swao: endpoint { + slave-mode; + remote-endpoint = + <&replicator_swao_out_funnel_in1>; + }; + }; + port@4 { + reg = <6>; + funnel_in1_in_funnel_dl_north: endpoint { + slave-mode; + remote-endpoint = + <&funnel_dl_north_out_funnel_in1>; + }; + }; + }; + }; + + funnel_in2: funnel@0x6043000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6043000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_in2_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in2>; + }; + }; + port@1 { + reg = <2>; + funnel_in2_in_funnel_apss_merg: endpoint { + slave-mode; + remote-endpoint = + <&funnel_apss_merg_out_funnel_in2>; + }; + }; + port@2 { + reg = <3>; + funnel_in2_in_funnel_gfx: endpoint { + slave-mode; + remote-endpoint = + <&funnel_gfx_out_funnel_in2>; + }; + }; + port@3 { + reg = <4>; + funnel_in2_in_tpda_modem: endpoint { + slave-mode; + remote-endpoint = + <&tpda_modem_out_funnel_in2>; + }; + }; + }; + }; + + funnel_gfx: funnel@0x6943000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6943000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-gfx"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_gfx_out_funnel_in2: endpoint { + remote-endpoint = + <&funnel_in2_in_funnel_gfx>; + }; + }; + port@1 { + reg = <1>; + funnel_gfx_in_gfx: endpoint { + slave-mode; + remote-endpoint = + <&gfx_out_funnel_gfx>; + }; + }; + port@2 { + reg = <2>; + funnel_gfx_in_gfx_cx: endpoint { + slave-mode; + remote-endpoint = + <&gfx_cx_out_funnel_gfx>; + }; + }; + }; + }; + + tpda: tpda@6004000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6004000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda"; + + qcom,tpda-atid = <65>; + qcom,bc-elem-size = <10 32>, + <13 32>; + qcom,tc-elem-size = <13 32>; + qcom,dsb-elem-size = <0 32>, + <2 32>, + <3 32>, + <5 32>, + <6 32>, + <10 32>, + <11 32>, + <13 32>; + qcom,cmb-elem-size = <3 64>, + <7 64>, + <10 64>, + <13 64>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_tpda>; + }; + + }; + + port@1 { + reg = <0>; + tpda_in_funnel_dl_mm: endpoint { + slave-mode; + remote-endpoint = + <&funnel_dl_mm_out_tpda>; + }; + }; + port@2 { + reg = <1>; + tpda_in_funnel_dl_mm1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_dl_mm1_out_tpda>; + }; + }; + + port@3 { + reg = <2>; + tpda_in_tpdm_center: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_center_out_tpda>; + }; + }; + + + port@4 { + reg = <4>; + tpda_in_funnel_lpass: endpoint { + slave-mode; + remote-endpoint = + <&funnel_lpass_out_tpda>; + }; + }; + + port@5 { + reg = <5>; + tpda_in_funnel_turing: endpoint { + slave-mode; + remote-endpoint = + <&funnel_turing_out_tpda>; + }; + }; + + port@6 { + reg = <6>; + tpda_in_funnel_ddr_0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_ddr_0_out_tpda>; + }; + }; + + port@7 { + reg = <8>; + tpda_in_tpdm_vsense: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_vsense_out_tpda>; + }; + }; + + port@8 { + reg = <10>; + tpda_in_tpdm_prng: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_prng_out_tpda>; + }; + }; + + port@9 { + reg = <13>; + tpda_in_tpdm_pimem: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_pimem_out_tpda>; + }; + }; + + port@10 { + reg = <14>; + tpda_in_tpdm_npu: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_npu_out_tpda>; + }; + }; + }; + }; + + tpda_modem: tpda@6832000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x6832000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-modem"; + + qcom,tpda-atid = <67>; + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_modem_out_funnel_in2: endpoint { + remote-endpoint = + <&funnel_in2_in_tpda_modem>; + }; + }; + + port@1 { + reg = <0>; + tpda_modem_in_tpdm_modem: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_modem_out_tpda_modem>; + }; + }; + }; + }; + + tpdm_modem: tpdm@6830000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6830000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-modem"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_modem_out_tpda_modem: endpoint { + remote-endpoint = <&tpda_modem_in_tpdm_modem>; + }; + }; + }; + + funnel_lpass: funnel@6846000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6846000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-lpass"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_lpass_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_funnel_lpass>; + }; + }; + + port@1 { + reg = <0>; + funnel_lpass_in_tpdm_lpass: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_lpass_out_funnel_lpass>; + }; + }; + }; + }; + + funnel_lpass_1: funnel_1@6846000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6867020 0x10>, + <0x6846000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + + coresight-name = "coresight-funnel-lpass-1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,duplicate-funnel; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_lpass_1_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_funnel_lpass_1>; + }; + }; + + port@1 { + reg = <2>; + funnel_lpass_1_in_audio_etm0: endpoint { + slave-mode; + remote-endpoint = + <&audio_etm0_out_funnel_lpass_1>; + }; + }; + }; + }; + + tpdm_lpass: tpdm@6844000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6844000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-lpass"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_lpass_out_funnel_lpass: endpoint { + remote-endpoint = <&funnel_lpass_in_tpdm_lpass>; + }; + }; + }; + + tpdm_center: tpdm@6c28000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6c28000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-center"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_center_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_center>; + }; + }; + }; + + tpdm_dl_north: tpdm@6ac0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6ac0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dl-north"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_dl_north_out_tpda_dl_north: endpoint { + remote-endpoint = + <&tpda_dl_north_in_tpdm_dl_north>; + }; + }; + }; + + tpda_dl_north: tpda@6ac1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x06ac1000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-dl-north"; + qcom,tpda-atid = <97>; + + qcom,cmb-elem-size = <0 32>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_dl_north_out_funnel_dl_north: endpoint { + remote-endpoint = + <&funnel_dl_north_in_tpda_dl_north>; + }; + }; + + port@1 { + reg = <0>; + tpda_dl_north_in_tpdm_dl_north: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dl_north_out_tpda_dl_north>; + }; + }; + }; + }; + + funnel_dl_south: funnel@69c2000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + reg = <0x69c2000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dl-south"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_dl_south_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_dl_south>; + }; + }; + + port@1 { + reg = <0>; + funnel_dl_south_in_tpdm_dl_south: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dl_south_out_funnel_dl_south>; + }; + }; + }; + }; + + tpdm_dl_south: tpdm@69c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x69c0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dl-south"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_dl_south_out_funnel_dl_south: endpoint { + remote-endpoint = + <&funnel_dl_south_in_tpdm_dl_south>; + }; + }; + }; + + funnel_dl_north: funnel@6ac2000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6ac2000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dl-north"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl_north_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_dl_north>; + }; + }; + + port@1 { + reg = <0>; + funnel_dl_north_in_tpda_dl_north: endpoint { + slave-mode; + remote-endpoint = + <&tpda_dl_north_out_funnel_dl_north>; + }; + }; + + port@2 { + reg = <1>; + funnel_dl_north_in_tpdm_wcss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_wcss_out_funnel_dl_north>; + }; + }; + }; + }; + + tpdm_wcss: tpdm@699c000 { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-tpdm-wcss"; + qcom,dummy-source; + + port { + tpdm_wcss_out_funnel_dl_north: endpoint { + remote-endpoint = <&funnel_dl_north_in_tpdm_wcss>; + }; + }; + }; + + tpdm_prng: tpdm@684c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x684c000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-prng"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_prng_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_prng>; + }; + }; + }; + + funnel_spss: funnel@6883000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6883000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-spss"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_spss_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_spss>; + }; + }; + + port@1 { + reg = <0>; + funnel_spss_in_tpda_spss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_spss_out_funnel_spss>; + }; + }; + + port@2 { + reg = <1>; + funnel_spss_in_spss_etm0: endpoint { + slave-mode; + remote-endpoint = + <&spss_etm0_out_funnel_spss>; + }; + }; + }; + }; + + tpda_spss: tpda@6882000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x06882000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-spss"; + + qcom,tpda-atid = <70>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_spss_out_funnel_spss: endpoint { + remote-endpoint = + <&funnel_spss_in_tpda_spss>; + }; + }; + + port@1 { + reg = <0>; + tpda_spss_in_tpdm_spss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_spss_out_tpda_spss>; + }; + }; + }; + }; + + tpdm_spss: tpdm@6880000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6880000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-spss"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_spss_out_tpda_spss: endpoint { + remote-endpoint = <&tpda_spss_in_tpdm_spss>; + }; + }; + }; + + spss_etm0 { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-spss-etm0"; + qcom,dummy-source; + + port { + spss_etm0_out_funnel_spss: endpoint { + remote-endpoint = <&funnel_spss_in_spss_etm0>; + }; + }; + }; + + tpdm_qm: tpdm@69d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x69d0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-qm"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_qm_out_funnel_dl_mm: endpoint { + remote-endpoint = <&funnel_dl_mm_in_tpdm_qm>; + }; + }; + }; + + tpda_apss: tpda@7862000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x7862000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-apss"; + + qcom,tpda-atid = <66>; + qcom,dsb-elem-size = <0 32>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_apss_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_tpda_apss>; + }; + }; + + port@1 { + reg = <0>; + tpda_apss_in_tpdm_apss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_apss_out_tpda_apss>; + }; + }; + }; + }; + + tpdm_apss: tpdm@7860000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x7860000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-apss"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_apss_out_tpda_apss: endpoint { + remote-endpoint = <&tpda_apss_in_tpdm_apss>; + }; + }; + }; + + tpda_llm_silver: tpda@78c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x78c0000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-llm-silver"; + + qcom,tpda-atid = <72>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_llm_silver_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_tpda_llm_silver>; + }; + }; + + port@1 { + reg = <0>; + tpda_llm_silver_in_tpdm_llm_silver: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_llm_silver_out_tpda_llm_silver>; + }; + }; + }; + }; + + tpdm_llm_silver: tpdm@78a0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x78a0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-llm-silver"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_llm_silver_out_tpda_llm_silver: endpoint { + remote-endpoint = + <&tpda_llm_silver_in_tpdm_llm_silver>; + }; + }; + }; + + tpda_llm_gold: tpda@78d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x78d0000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-llm-gold"; + + qcom,tpda-atid = <73>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_llm_gold_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_tpda_llm_gold>; + }; + }; + + port@1 { + reg = <0>; + tpda_llm_gold_in_tpdm_llm_gold: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_llm_gold_out_tpda_llm_gold>; + }; + }; + }; + }; + + tpdm_llm_gold: tpdm@78b0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x78b0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-llm-gold"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_llm_gold_out_tpda_llm_gold: endpoint { + remote-endpoint = + <&tpda_llm_gold_in_tpdm_llm_gold>; + }; + }; + }; + + funnel_dl_mm: funnel@6c0b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6c0b000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dl-mm"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl_mm_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_funnel_dl_mm>; + }; + }; + + port@1 { + reg = <0>; + funnel_dl_mm_in_tpdm_qm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_qm_out_funnel_dl_mm>; + }; + }; + }; + }; + + funnel_dl_mm1: funnel_1@6c0b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6867000 0x10>, + <0x6c0b000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + + coresight-name = "coresight-funnel-dl-mm1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,duplicate-funnel; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dl_mm1_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_funnel_dl_mm1>; + }; + }; + + port@1 { + reg = <1>; + funnel_dl_mm1_in_tpdm_mm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_mm_out_funnel_dl_mm1>; + }; + }; + }; + }; + + tpdm_mm: tpdm@6c08000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6c08000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-mm"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_mm_out_funnel_dl_mm1: endpoint { + remote-endpoint = <&funnel_dl_mm1_in_tpdm_mm>; + }; + }; + }; + + funnel_turing: funnel@6861000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6861000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-turing"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_turing_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_funnel_turing>; + }; + }; + + port@1 { + reg = <0>; + funnel_turing_in_tpdm_turing: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_turing_out_funnel_turing>; + }; + }; + }; + }; + + funnel_turing_1: funnel_1@6861000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6867010 0x10>, + <0x6861000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + + coresight-name = "coresight-funnel-turing-1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,duplicate-funnel; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_turing_1_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_funnel_turing_1>; + }; + }; + + port@1 { + reg = <1>; + funnel_turing_1_in_turing_etm0: endpoint { + slave-mode; + remote-endpoint = + <&turing_etm0_out_funnel_turing_1>; + }; + }; + }; + }; + + tpdm_turing: tpdm@6860000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6860000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-turing"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_turing_out_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_in_tpdm_turing>; + }; + }; + }; + + funnel_ddr_0: funnel@6a05000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6a05000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-ddr-0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_ddr_0_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_funnel_ddr_0>; + }; + }; + + port@1 { + reg = <0>; + funnel_ddr_0_in_tpdm_ddr: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_ddr_out_funnel_ddr_0>; + }; + }; + }; + }; + + tpdm_ddr: tpdm@6A00000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x06A00000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-ddr"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_ddr_out_funnel_ddr_0: endpoint { + remote-endpoint = <&funnel_ddr_0_in_tpdm_ddr>; + }; + }; + }; + + tpdm_pimem: tpdm@6850000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6850000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-pimem"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_pimem_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_pimem>; + }; + }; + }; + + tpdm_vsense: tpdm@6840000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6840000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-vsense"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port{ + tpdm_vsense_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_vsense>; + }; + }; + }; + + tpda_olc: tpda@7832000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x7832000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-olc"; + + qcom,tpda-atid = <69>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_olc_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_tpda_olc>; + }; + }; + port@1 { + reg = <0>; + tpda_olc_in_tpdm_olc: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_olc_out_tpda_olc>; + }; + }; + }; + }; + + tpdm_olc: tpdm@7830000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x7830000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-olc"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port{ + tpdm_olc_out_tpda_olc: endpoint { + remote-endpoint = <&tpda_olc_in_tpdm_olc>; + }; + }; + }; + + tpdm_npu: tpdm@6980000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x6980000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-npu"; + + clocks = <&clock_aop QDSS_CLK>, + <&clock_gcc GCC_NPU_TRIG_CLK>, + <&clock_gcc GCC_NPU_AT_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_APB_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_CLK_SRC>, + <&clock_npucc NPU_CC_NPU_CORE_CTI_CLK>; + + clock-names = "apb_pclk", + "gcc_npu_trig_clk", + "gcc_npu_at_clk", + "npu_core_apb_clk", + "npu_core_atb_clk", + "npu_core_clk", + "npu_core_clk_src", + "npu_core_cti_clk"; + + qcom,tpdm-clks = "gcc_npu_trig_clk", + "gcc_npu_at_clk", + "npu_core_apb_clk", + "npu_core_atb_clk", + "npu_core_clk", + "npu_core_clk_src", + "npu_core_cti_clk"; + + vdd-supply = <&npu_core_gdsc>; + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,tpdm-regs = "vdd", "vdd_cx"; + + port{ + tpdm_npu_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_npu>; + }; + }; + }; + + funnel_qatb: funnel@6005000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6005000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-qatb"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_qatb_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_qatb>; + }; + }; + + port@1 { + reg = <0>; + funnel_qatb_in_tpda: endpoint { + slave-mode; + remote-endpoint = + <&tpda_out_funnel_qatb>; + }; + }; + + port@2 { + reg = <4>; + funnel_qatb_in_funnel_lpass_1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_lpass_1_out_funnel_qatb>; + }; + }; + + port@3 { + reg = <5>; + funnel_qatb_in_funnel_turing_1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_turing_1_out_funnel_qatb>; + }; + }; + }; + }; + + cti0_apss: cti@78e0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x78e0000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss_cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_apss: cti@78f0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x78f0000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss_cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti2_apss: cti@7900000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7900000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss_cti2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_ddr0: cti@6a02000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6a02000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_0_cti_0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_ddr0: cti@6a03000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6a03000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_0_cti_1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_ddr1: cti@6a10000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6a10000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_1_cti_0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_ddr1: cti@6a11000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6a11000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-ddr_dl_1_cti_1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_dlmm: cti@6c09000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6c09000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlmm_cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_dlmm: cti@6c0a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6c0a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlmm_cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_dlct: cti@6c29000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6c29000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct_cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_dlct: cti@6c2a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6c2a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct_cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0: cti@6010000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6010000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti1: cti@6011000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6011000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti2: cti@6012000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6012000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,cti-gpio-trigout = <4>; + pinctrl-names = "cti-trigout-pctrl"; + pinctrl-0 = <&trigout_a>; + }; + + cti3: cti@6013000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6013000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti3"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti4: cti@6014000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6014000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti4"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti5: cti@6015000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6015000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti5"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti6: cti@6016000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6016000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti6"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti7: cti@6017000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6017000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti7"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti8: cti@6018000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6018000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti8"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti9: cti@6019000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6019000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti9"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti10: cti@601a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti10"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti11: cti@601b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti11"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti12: cti@601c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti12"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti13: cti@601d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601d000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti13"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti14: cti@601e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601e000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti14"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti15: cti@601f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x601f000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti15"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti_cpu0: cti@7020000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7020000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu0"; + cpu = <&CPU0>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti_cpu1: cti@7120000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7120000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu1"; + cpu = <&CPU1>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu2: cti@7220000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7220000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu2"; + cpu = <&CPU2>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu3: cti@7320000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7320000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu3"; + cpu = <&CPU3>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu4: cti@7420000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7420000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu4"; + cpu = <&CPU4>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu5: cti@7520000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7520000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu5"; + cpu = <&CPU5>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu6: cti@7620000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7620000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu6"; + cpu = <&CPU6>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu7: cti@7720000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x7720000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu7"; + cpu = <&CPU7>; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_swao:cti@6b04000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x6b04000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-swao_cti0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + ipcb_tgu: tgu@6b0c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b999>; + reg = <0x06B0C000 0x1000>; + reg-names = "tgu-base"; + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <4>; + tgu-timer-counters = <8>; + + coresight-name = "coresight-tgu-ipcb"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + turing_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-turing-etm0"; + qcom,inst-id = <13>; + + port{ + turing_etm0_out_funnel_turing_1: endpoint { + remote-endpoint = + <&funnel_turing_1_in_turing_etm0>; + }; + }; + }; + + dummy_eud: dummy_sink { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-eud"; + + qcom,dummy-sink; + port { + eud_in_replicator_swao: endpoint { + slave-mode; + remote-endpoint = + <&replicator_swao_out_eud>; + }; + }; + }; + + modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem-etm0"; + qcom,inst-id = <2>; + + port { + modem_etm0_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_modem_etm0>; + }; + }; + }; + + audio_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-audio-etm0"; + qcom,inst-id = <5>; + + port { + audio_etm0_out_funnel_lpass_1: endpoint { + remote-endpoint = + <&funnel_lpass_1_in_audio_etm0>; + }; + }; + }; + + ssc_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-ssc-etm0"; + qcom,inst-id = <8>; + + port { + ssc_etm0_out_funnel_swao: endpoint { + remote-endpoint = + <&funnel_swao_in_ssc_etm0>; + }; + }; + }; + + funnel_apss_merg: funnel@7810000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x7810000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss-merg"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss_merg_out_funnel_in2: endpoint { + remote-endpoint = + <&funnel_in2_in_funnel_apss_merg>; + }; + }; + + port@1 { + reg = <0>; + funnel_apss_merg_in_funnel_apss: endpoint { + slave-mode; + remote-endpoint = + <&funnel_apss_out_funnel_apss_merg>; + }; + }; + + port@2 { + reg = <2>; + funnel_apss_merg_in_tpda_olc: endpoint { + slave-mode; + remote-endpoint = + <&tpda_olc_out_funnel_apss_merg>; + }; + }; + + port@3 { + reg = <3>; + funnel_apss_merg_in_tpda_llm_silver: endpoint { + slave-mode; + remote-endpoint = + <&tpda_llm_silver_out_funnel_apss_merg>; + }; + }; + + port@4 { + reg = <4>; + funnel_apss_merg_in_tpda_llm_gold: endpoint { + slave-mode; + remote-endpoint = + <&tpda_llm_gold_out_funnel_apss_merg>; + }; + }; + + port@5 { + reg = <5>; + funnel_apss_merg_in_tpda_apss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_apss_out_funnel_apss_merg>; + }; + }; + + }; + }; + + etm0: etm@7040000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7040000 0x1000>; + cpu = <&CPU0>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm0"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm0_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm0>; + }; + }; + }; + + etm1: etm@7140000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7140000 0x1000>; + cpu = <&CPU1>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm1"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm1_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm1>; + }; + }; + }; + + etm2: etm@7240000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7240000 0x1000>; + cpu = <&CPU2>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm2"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm2_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm2>; + }; + }; + }; + + etm3: etm@7340000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7340000 0x1000>; + cpu = <&CPU3>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm3"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm3_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm3>; + }; + }; + }; + + etm4: etm@7440000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7440000 0x1000>; + cpu = <&CPU4>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm4"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm4_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm4>; + }; + }; + }; + + etm5: etm@7540000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7540000 0x1000>; + cpu = <&CPU5>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm5"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm5_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm5>; + }; + }; + }; + + etm6: etm@7640000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7640000 0x1000>; + cpu = <&CPU6>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm6"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm6_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm6>; + }; + }; + }; + + etm7: etm@7740000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x7740000 0x1000>; + cpu = <&CPU7>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm7"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm7_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm7>; + }; + }; + }; + + funnel_apss: funnel@7800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x7800000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_funnel_apss>; + }; + }; + port@1 { + reg = <0>; + funnel_apss_in_etm0: endpoint { + slave-mode; + remote-endpoint = + <&etm0_out_funnel_apss>; + }; + }; + + port@2 { + reg = <1>; + funnel_apss_in_etm1: endpoint { + slave-mode; + remote-endpoint = + <&etm1_out_funnel_apss>; + }; + }; + + port@3 { + reg = <2>; + funnel_apss_in_etm2: endpoint { + slave-mode; + remote-endpoint = + <&etm2_out_funnel_apss>; + }; + }; + + port@4 { + reg = <3>; + funnel_apss_in_etm3: endpoint { + slave-mode; + remote-endpoint = + <&etm3_out_funnel_apss>; + }; + }; + + port@5 { + reg = <4>; + funnel_apss_in_etm4: endpoint { + slave-mode; + remote-endpoint = + <&etm4_out_funnel_apss>; + }; + }; + + port@6 { + reg = <5>; + funnel_apss_in_etm5: endpoint { + slave-mode; + remote-endpoint = + <&etm5_out_funnel_apss>; + }; + }; + + port@7 { + reg = <6>; + funnel_apss_in_etm6: endpoint { + slave-mode; + remote-endpoint = + <&etm6_out_funnel_apss>; + }; + }; + + port@8 { + reg = <7>; + funnel_apss_in_etm7: endpoint { + slave-mode; + remote-endpoint = + <&etm7_out_funnel_apss>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-gdsc.dtsi b/arch/arm/boot/dts/qcom/sm8150-gdsc.dtsi new file mode 100644 index 000000000000..af4a8712c26a --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-gdsc.dtsi @@ -0,0 +1,267 @@ +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + /* GDSCs in Global CC */ + emac_gdsc: qcom,gdsc@0x106004 { + compatible = "qcom,gdsc"; + regulator-name = "emac_gdsc"; + reg = <0x106004 0x4>; + status = "disabled"; + }; + + pcie_0_gdsc: qcom,gdsc@0x16b004 { + compatible = "qcom,gdsc"; + regulator-name = "pcie_0_gdsc"; + reg = <0x16b004 0x4>; + status = "disabled"; + }; + + pcie_1_gdsc: qcom,gdsc@0x18d004 { + compatible = "qcom,gdsc"; + regulator-name = "pcie_1_gdsc"; + reg = <0x18d004 0x4>; + status = "disabled"; + }; + + ufs_card_gdsc: qcom,gdsc@0x175004 { + compatible = "qcom,gdsc"; + regulator-name = "ufs_card_gdsc"; + reg = <0x175004 0x4>; + status = "disabled"; + }; + + ufs_phy_gdsc: qcom,gdsc@0x177004 { + compatible = "qcom,gdsc"; + regulator-name = "ufs_phy_gdsc"; + reg = <0x177004 0x4>; + status = "disabled"; + }; + + usb30_prim_gdsc: qcom,gdsc@0x10f004 { + compatible = "qcom,gdsc"; + regulator-name = "usb30_prim_gdsc"; + reg = <0x10f004 0x4>; + status = "disabled"; + }; + + usb30_sec_gdsc: qcom,gdsc@0x110004 { + compatible = "qcom,gdsc"; + regulator-name = "usb30_sec_gdsc"; + reg = <0x110004 0x4>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc: qcom,gdsc@0x17d040 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc"; + reg = <0x17d040 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_tbu1_gdsc: qcom,gdsc@0x17d044 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc"; + reg = <0x17d044 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_tbu2_gdsc: qcom,gdsc@0x17d048 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc"; + reg = <0x17d048 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc: qcom,gdsc@0x17d04c { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc"; + reg = <0x17d04c 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@0x17d050 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; + reg = <0x17d050 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@0x17d054 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc"; + reg = <0x17d054 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@0x17d058 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc"; + reg = <0x17d058 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@0x17d05c { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc"; + reg = <0x17d05c 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@0x17d060 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc"; + reg = <0x17d060 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + /* GDSCs in Camera CC */ + bps_gdsc: qcom,gdsc@0xad07004 { + compatible = "qcom,gdsc"; + regulator-name = "bps_gdsc"; + reg = <0xad07004 0x4>; + status = "disabled"; + }; + + ipe_0_gdsc: qcom,gdsc@0xad08004 { + compatible = "qcom,gdsc"; + regulator-name = "ipe_0_gdsc"; + reg = <0xad08004 0x4>; + status = "disabled"; + }; + + ipe_1_gdsc: qcom,gdsc@0xad09004 { + compatible = "qcom,gdsc"; + regulator-name = "ipe_1_gdsc"; + reg = <0xad09004 0x4>; + status = "disabled"; + }; + + ife_0_gdsc: qcom,gdsc@0xad0a004 { + compatible = "qcom,gdsc"; + regulator-name = "ife_0_gdsc"; + reg = <0xad0a004 0x4>; + status = "disabled"; + }; + + ife_1_gdsc: qcom,gdsc@0xad0b004 { + compatible = "qcom,gdsc"; + regulator-name = "ife_1_gdsc"; + reg = <0xad0b004 0x4>; + status = "disabled"; + }; + + titan_top_gdsc: qcom,gdsc@0xad0c1bc { + compatible = "qcom,gdsc"; + regulator-name = "titan_top_gdsc"; + reg = <0xad0c1bc 0x4>; + status = "disabled"; + }; + + /* GDSCs in Display CC */ + mdss_core_gdsc: qcom,gdsc@0xaf03000 { + compatible = "qcom,gdsc"; + regulator-name = "mdss_core_gdsc"; + reg = <0xaf03000 0x4>; + qcom,support-hw-trigger; + status = "disabled"; + proxy-supply = <&mdss_core_gdsc>; + qcom,proxy-consumer-enable; + }; + + /* GDSCs in Graphics CC */ + gpu_cx_hw_ctrl: syscon@0x2c91540 { + compatible = "syscon"; + reg = <0x2c91540 0x4>; + }; + + gpu_cx_gdsc: qcom,gdsc@0x2c9106c { + compatible = "qcom,gdsc"; + regulator-name = "gpu_cx_gdsc"; + reg = <0x2c9106c 0x4>; + hw-ctrl-addr = <&gpu_cx_hw_ctrl>; + qcom,skip-disable; + qcom,gds-timeout = <500>; + qcom,clk-dis-wait-val = <8>; + mboxes = <&qmp_aop 0>; + status = "disabled"; + }; + + gpu_gx_domain_addr: syscon@0x2c91508 { + compatible = "syscon"; + reg = <0x2c91508 0x4>; + }; + + gpu_gx_sw_reset: syscon@0x2c91008 { + compatible = "syscon"; + reg = <0x2c91008 0x4>; + }; + + gpu_gx_gdsc: qcom,gdsc@0x2c9100c { + compatible = "qcom,gdsc"; + regulator-name = "gpu_gx_gdsc"; + reg = <0x2c9100c 0x4>; + domain-addr = <&gpu_gx_domain_addr>; + sw-reset = <&gpu_gx_sw_reset>; + qcom,reset-aon-logic; + status = "disabled"; + }; + + /* GDSCs in Video CC */ + mvsc_gdsc: qcom,gdsc@0xab00814 { + compatible = "qcom,gdsc"; + regulator-name = "mvsc_gdsc"; + reg = <0xab00814 0x4>; + status = "disabled"; + }; + + mvs0_gdsc: qcom,gdsc@0xab00874 { + compatible = "qcom,gdsc"; + regulator-name = "mvs0_gdsc"; + reg = <0xab00874 0x4>; + status = "disabled"; + }; + + mvs1_gdsc: qcom,gdsc@0xab008b4 { + compatible = "qcom,gdsc"; + regulator-name = "mvs1_gdsc"; + reg = <0xab008b4 0x4>; + status = "disabled"; + }; + + /* GDSCs in NPU CC */ + npu_core_gdsc: qcom,gdsc@0x9911028 { + compatible = "qcom,gdsc"; + regulator-name = "npu_core_gdsc"; + reg = <0x9911028 0x4>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-gpu-v2.dtsi b/arch/arm/boot/dts/qcom/sm8150-gpu-v2.dtsi new file mode 100644 index 000000000000..bbf88b802122 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-gpu-v2.dtsi @@ -0,0 +1,47 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + gpu_opp_table_v2: gpu_opp_table_v2 { + compatible = "operating-points-v2"; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; + opp-microvolt = ; + }; + + opp-585000000 { + opp-hz = /bits/ 64 <585000000>; + opp-microvolt = ; + }; + + opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + opp-microvolt = ; + }; + + opp-427000000 { + opp-hz = /bits/ 64 <427000000>; + opp-microvolt = ; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + opp-microvolt = ; + }; + + opp-257000000 { + opp-hz = /bits/ 64 <257000000>; + opp-microvolt = ; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-gpu.dtsi b/arch/arm/boot/dts/qcom/sm8150-gpu.dtsi new file mode 100644 index 000000000000..3dbcdb82af51 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-gpu.dtsi @@ -0,0 +1,404 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + pil_gpu: qcom,kgsl-hyp { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <13>; + qcom,firmware-name = "a640_zap"; + }; + + msm_bus: qcom,kgsl-busmon{ + label = "kgsl-busmon"; + compatible = "qcom,kgsl-busmon"; + }; + + gpubw: qcom,gpubw { + compatible = "qcom,devbw"; + governor = "bw_vbif"; + qcom,src-dst-ports = <26 512>; + operating-points-v2 = <&suspendable_ddr_bw_opp_table>; + }; + + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = ; + }; + + opp-553850000 { + opp-hz = /bits/ 64 <553850000>; + opp-microvolt = ; + }; + + opp-486460000 { + opp-hz = /bits/ 64 <486460000>; + opp-microvolt = ; + }; + + opp-379650000 { + opp-hz = /bits/ 64 <379650000>; + opp-microvolt = ; + }; + + opp-309110000 { + opp-hz = /bits/ 64 <309110000>; + opp-microvolt = ; + }; + + opp-215000000 { + opp-hz = /bits/ 64 <215000000>; + opp-microvolt = ; + }; + }; + + msm_gpu: qcom,kgsl-3d0@2C00000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; + status = "ok"; + reg = <0x2c00000 0x40000>, <0x2c61000 0x800>, + <0x6900000 0x44000>, <0x780000 0x6fff>; + reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", + "qdss_gfx", "qfprom_memory"; + interrupts = <0 300 0>; + interrupt-names = "kgsl_3d0_irq"; + qcom,id = <0>; + + qcom,chipid = <0x06040000>; + + qcom,initial-pwrlevel = <5>; + + qcom,gpu-quirk-secvid-set-once; + qcom,gpu-quirk-cx-gdsc; + + qcom,idle-timeout = <80>; //msecs + qcom,no-nap; + + qcom,highest-bank-bit = <15>; + + qcom,min-access-length = <32>; + + qcom,ubwc-mode = <3>; + + qcom,snapshot-size = <0x200000>; //bytes + + qcom,gpu-qdss-stm = <0x161c0000 0x40000>; // base addr, size + + qcom,tsens-name = "tsens_tz_sensor12"; + #cooling-cells = <2>; + + tzone-names = "gpuss-0-usr", "gpuss-1-usr"; + + qcom,pm-qos-active-latency = <44>; + + clocks = <&clock_gpucc GPU_CC_CXO_CLK>, + <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gpucc GPU_CC_CX_GMU_CLK>, + <&clock_gpucc GPU_CC_AHB_CLK>, + <&clock_cpucc L3_GPU_VOTE_CLK>; + + clock-names = "rbbmtimer_clk", "mem_clk", + "mem_iface_clk", "gmu_clk", + "gpu_cc_ahb", "l3_vote"; + + qcom,isense-clk-on-level = <1>; + + /* Bus Scale Settings */ + qcom,gpubw-dev = <&gpubw>; + qcom,bus-control; + qcom,msm-bus,name = "grp3d"; + qcom,bus-width = <32>; + qcom,msm-bus,num-cases = <13>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, + + <26 512 0 400000>, // 1 bus=100 + <26 512 0 600000>, // 2 bus=150 + <26 512 0 800000>, // 3 bus=200 + <26 512 0 1200000>, // 4 bus=300 + <26 512 0 1648000>, // 5 bus=412 + <26 512 0 2188000>, // 6 bus=547 + <26 512 0 2724000>, // 7 bus=681 + <26 512 0 3072000>, // 8 bus=768 + <26 512 0 4068000>, // 9 bus=1017 + <26 512 0 5184000>, // 10 bus=1296 + <26 512 0 6220000>, // 11 bus=1555 + <26 512 0 7216000>; // 12 bus=1804 + + /* GDSC regulator names */ + regulator-names = "vddcx", "vdd"; + /* GDSC oxili regulators */ + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + + /* GPU OPP data */ + operating-points-v2 = <&gpu_opp_table>; + + /* GPU related llc slices */ + cache-slice-names = "gpu", "gpuhtw"; + cache-slices = <&llcc 12>, <&llcc 11>; + + + qcom,gpu-coresights { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-coresight"; + + qcom,gpu-coresight@0 { + reg = <0>; + coresight-name = "coresight-gfx"; + coresight-atid = <50>; + port { + gfx_out_funnel_gfx: endpoint { + remote-endpoint = + <&funnel_gfx_in_gfx>; + }; + }; + }; + qcom,gpu-coresight@1 { + reg = <1>; + coresight-name = "coresight-gfx-cx"; + coresight-atid = <51>; + port { + gfx_cx_out_funnel_gfx: endpoint { + remote-endpoint = + <&funnel_gfx_in_gfx_cx>; + }; + }; + }; + }; + + qcom,l3-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,l3-pwrlevels"; + + qcom,l3-pwrlevel@0 { + reg = <0>; + qcom,l3-freq = <0>; + }; + + qcom,l3-pwrlevel@1 { + reg = <1>; + qcom,l3-freq = <864000000>; + }; + + qcom,l3-pwrlevel@2 { + reg = <2>; + qcom,l3-freq = <1344000000>; + }; + }; + + /* GPU Mempools */ + qcom,gpu-mempools { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-reserved = <2048>; + qcom,mempool-allocate; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-reserved = <1024>; + qcom,mempool-allocate; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; + + /* Power levels */ + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <600000000>; + qcom,bus-freq = <12>; + qcom,bus-min = <10>; + qcom,bus-max = <12>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <553850000>; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <486460000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <379650000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <309110000>; + qcom,bus-freq = <5>; + qcom,bus-min = <5>; + qcom,bus-max = <7>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <215000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + }; + + kgsl_msm_iommu: qcom,kgsl-iommu@0x02CA0000 { + compatible = "qcom,kgsl-smmu-v2"; + + reg = <0x02CA0000 0x10000>; + /* CB5(ATOS) & CB5/6/7 are protected by HYP */ + qcom,protect = <0xa0000 0xc000>; + + clocks =<&clock_gcc GCC_GPU_CFG_AHB_CLK>, + <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>; + + clock-names = "iface_clk", "mem_clk", "mem_iface_clk"; + + qcom,secure_align_mask = <0xfff>; + qcom,retention; + qcom,hyp_secure_alloc; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + label = "gfx3d_user"; + iommus = <&kgsl_smmu 0x0 0x401>; + qcom,gpu-offset = <0xa8000>; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + label = "gfx3d_secure"; + iommus = <&kgsl_smmu 0x2 0x400>; + }; + }; + + gmu: qcom,gmu@0x2C6A000 { + label = "kgsl-gmu"; + compatible = "qcom,gpu-gmu"; + + reg = <0x2c6a000 0x30000>, + <0xb280000 0x10000>, + <0xb480000 0x10000>; + reg-names = "kgsl_gmu_reg", + "kgsl_gmu_pdc_cfg", + "kgsl_gmu_pdc_seq"; + + interrupts = <0 304 0>, <0 305 0>; + interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq"; + + qcom,msm-bus,name = "cnoc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 10036 0 0>, // CNOC off + <26 10036 0 100>; // CNOC on + + regulator-names = "vddcx", "vdd"; + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + + clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>, + <&clock_gpucc GPU_CC_CXO_CLK>, + <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gpucc GPU_CC_AHB_CLK>; + + clock-names = "gmu_clk", "cxo_clk", "axi_clk", + "memnoc_clk", "gpu_cc_ahb"; + + /* AOP mailbox for sending ACD enable and disable messages */ + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + + qcom,gmu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gmu-pwrlevels"; + + /* GMU power levels must go from lowest to highest */ + qcom,gmu-pwrlevel@0 { + reg = <0>; + qcom,gmu-freq = <0>; + }; + + qcom,gmu-pwrlevel@1 { + reg = <1>; + qcom,gmu-freq = <200000000>; + }; + }; + + gmu_user: gmu_user { + compatible = "qcom,smmu-gmu-user-cb"; + iommus = <&kgsl_smmu 0x4 0x400>; + }; + + gmu_kernel: gmu_kernel { + compatible = "qcom,smmu-gmu-kernel-cb"; + iommus = <&kgsl_smmu 0x5 0x400>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-hdk-overlay.dts b/arch/arm/boot/dts/qcom/sm8150-hdk-overlay.dts new file mode 100644 index 000000000000..e1580d227fd9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-hdk-overlay.dts @@ -0,0 +1,143 @@ +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-hdk.dtsi" + +/ { + model = "HDK"; + compatible = "qcom,sm8150-hdk", "qcom,sm8150", "qcom,hdk"; + qcom,board-id = <0x1f 0x0>; +}; + +&dsi_dual_nt36850_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&pm8150l_wled { + qcom,string-cfg= <7>; + qcom,leds-per-string = <6>; + status = "ok"; +}; + +&pm8150l_lcdb { + status = "ok"; +}; + +&dsi_sw43404_amoled_cmd_display { + /delete-property/ qcom,dsi-display-active; +}; + +&dsi_dual_nt36850_truly_cmd_display { + /delete-property/ qcom,dsi-display-active; +}; + +&qupv3_se9_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + lt9611: lt,lt9611@3b { + compatible = "lt,lt9611"; + reg = <0x3b>; + interrupt-parent = <&tlmm>; + interrupts = <63 0>; + interrupt-names = "lt_irq"; + lt,irq-gpio = <&tlmm 9 0x0>; + lt,reset-gpio = <&tlmm 7 0x0>; + instance_id = <0>; + lt,non-pluggable; + + lt,preferred-mode = "1920x1080"; + + lt,customize-modes { + lt,customize-mode-id@0 { + lt,mode-h-active = <1920>; + lt,mode-h-front-porch = <88>; + lt,mode-h-pulse-width = <44>; + lt,mode-h-back-porch = <148>; + lt,mode-h-active-high; + lt,mode-v-active = <1080>; + lt,mode-v-front-porch = <4>; + lt,mode-v-pulse-width = <5>; + lt,mode-v-back-porch = <36>; + lt,mode-v-active-high; + lt,mode-refresh-rate = <60>; + lt,mode-clock-in-khz = <148500>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lt9611_in: endpoint { + remote-endpoint = <&ext_dsi_out>; + }; + }; + }; + }; +}; + +#include "dsi-panel-ext-bridge-hdmi-1080p.dtsi" + +&dsi_ext_bridge_hdmi_1080p { + qcom,mdss-dsi-ext-bridge = <0>; +}; + +&soc { + ext_dsi_bridge_display: qcom,dsi-display@50 { + label = "ext_dsi_bridge_display hdmi 1080p"; + qcom,display-type = "primary"; + qcom,dsi-display-active; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_ext_bridge_hdmi_1080p>; + }; +}; + +&sde_dsi { + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + qcom,dsi-display-list = <&ext_dsi_bridge_display + &dsi_dual_nt36850_truly_cmd_display>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ext_dsi_out: endpoint { + remote-endpoint = <<9611_in>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-hdk.dts b/arch/arm/boot/dts/qcom/sm8150-hdk.dts new file mode 100644 index 000000000000..f81480718397 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-hdk.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150-v2.dtsi" +#include "sm8150-hdk.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150 HDK"; + compatible = "qcom,sm8150-hdk", "qcom,sm8150", "qcom,hdk"; + qcom,board-id = <0x01001f 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-hdk.dtsi b/arch/arm/boot/dts/qcom/sm8150-hdk.dtsi new file mode 100644 index 000000000000..b3bfde76fffb --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-hdk.dtsi @@ -0,0 +1,101 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "sm8150-qrd.dtsi" +#include "sm8150-qrd-audio-overlay.dtsi" +#include "sm8150-camera-sensor-hdk.dtsi" + +&tlmm { + pmx_ts_rst_active { + ts_rst_active: ts_rst_active { + mux { + pins = "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio54"; + drive-strength = <16>; + bias-pull-up; + }; + }; + }; + + pmx_ts_rst_suspend { + ts_rst_suspend: ts_rst_suspend { + mux { + pins = "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; +}; + +&soc { + hbtp { + compatible = "qcom,hbtp-input"; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; + pinctrl-0 = <&ts_rst_active>; + pinctrl-1 = <&ts_rst_suspend>; + vcc_ana-supply = <&pm8150_l17>; + vcc_dig-supply = <&pm8150_s4>; + qcom,afe-load = <20000>; + qcom,afe-vtg-min = <3000000>; + qcom,afe-vtg-max = <3000000>; + qcom,dig-load = <40000>; + qcom,dig-vtg-min = <1800000>; + qcom,dig-vtg-max = <1800000>; + qcom,fb-resume-delay-us = <1000>; + qcom,afe-force-power-on; + qcom,afe-power-on-delay-us = <6>; + qcom,afe-power-off-delay-us = <6>; + qcom,platform-en-gpio = <&tlmm 53 0>; + }; + + usb1_otg_supply: usb1_otg_supply { + compatible = "regulator-fixed"; + regulator-name = "regulator_fixed"; + gpio = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>; + status = "ok"; + }; +}; + +&usb1 { + vbus_dwc3-supply = <&usb1_otg_supply>; + status = "ok"; + dwc3@a800000 { + dr_mode = "host"; + }; +}; + +&usb2_phy1 { + status = "ok"; +}; + +&usb_qmp_phy { + status = "ok"; +}; + +&usb2_phy0 { + qcom,param-override-seq = + <0x40 0x70 + 0x28 0x74>; +}; + +&qupv3_se17_i2c { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-ion.dtsi b/arch/arm/boot/dts/qcom/sm8150-ion.dtsi new file mode 100644 index 000000000000..5fd5253e3907 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-ion.dtsi @@ -0,0 +1,74 @@ +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = <25>; + qcom,ion-heap-type = "SYSTEM"; + }; + + qcom,ion-heap@22 { /* ADSP HEAP */ + reg = <22>; + memory-region = <&adsp_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@26 { /* USER CONTIG HEAP */ + reg = <26>; + memory-region = <&user_contig_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = <27>; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@19 { /* QSEECOM TA HEAP */ + reg = <19>; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@13 { /* SPSS HEAP */ + reg = <13>; + memory-region = <&sp_mem>; + qcom,ion-heap-type = "HYP_CMA"; + }; + + qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ + reg = <10>; + memory-region = <&secure_display_memory>; + qcom,ion-heap-type = "HYP_CMA"; + }; + + qcom,ion-heap@14 { /* SECURE CARVEOUT HEAP */ + reg = <14>; + qcom,ion-heap-type = "SECURE_CARVEOUT"; + cdsp { + memory-region = <&cdsp_sec_mem>; + token = <0x20000000>; + }; + }; + + qcom,ion-heap@9 { + reg = <9>; + qcom,ion-heap-type = "SYSTEM_SECURE"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-mhi.dtsi b/arch/arm/boot/dts/qcom/sm8150-mhi.dtsi new file mode 100644 index 000000000000..9f53e564ccdf --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-mhi.dtsi @@ -0,0 +1,1097 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&pcie_rc1 { + reg = <0 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + mhi_0: qcom,mhi@0 { + reg = <0 0 0 0 0 >; + + pci-ids = "17cb:0305", "17cb:0306"; + + /* controller specific configuration */ + qcom,smmu-cfg = <0x3>; + + /* mhi bus specific settings */ + mhi,max-channels = <110>; + mhi,timeout = <2000>; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@2 { + reg = <2>; + label = "SAHARA"; + mhi,num-elements = <128>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x2>; + }; + + mhi_chan@3 { + reg = <3>; + label = "SAHARA"; + mhi,num-elements = <128>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x2>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@8 { + reg = <8>; + label = "QDSS"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@9 { + reg = <9>; + label = "QDSS"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@10 { + reg = <10>; + label = "EFS"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@11 { + reg = <11>; + label = "EFS"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,wake-capable; + }; + + mhi_chan@14 { + reg = <14>; + label = "QMI0"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@15 { + reg = <15>; + label = "QMI0"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@16 { + reg = <16>; + label = "QMI1"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@17 { + reg = <17>; + label = "QMI1"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@18 { + reg = <18>; + label = "IP_CTRL"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@19 { + reg = <19>; + label = "IP_CTRL"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,auto-queue; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,auto-queue; + mhi,auto-start; + }; + + mhi_chan@22 { + reg = <22>; + label = "TF"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@23 { + reg = <23>; + label = "TF"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@25 { + reg = <25>; + label = "BL"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x2>; + mhi,auto-queue; + mhi,auto-start; + }; + + mhi_chan@26 { + reg = <26>; + label = "DCI"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@27 { + reg = <27>; + label = "DCI"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@32 { + reg = <32>; + label = "DUN"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@33 { + reg = <33>; + label = "DUN"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@100 { + reg = <100>; + label = "IP_HW0"; + mhi,num-elements = <512>; + mhi,event-ring = <4>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <3>; + mhi,ee = <0x4>; + mhi,db-mode-switch; + }; + + mhi_chan@101 { + reg = <101>; + label = "IP_HW0"; + mhi,num-elements = <512>; + mhi,event-ring = <5>; + mhi,chan-dir = <2>; + mhi,data-type = <4>; + mhi,doorbell-mode = <3>; + mhi,ee = <0x4>; + }; + + mhi_chan@102 { + reg = <102>; + label = "IP_HW_ADPL"; + mhi,event-ring = <6>; + mhi,chan-dir = <2>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + mhi,lpm-notify; + }; + + mhi_chan@103 { + reg = <103>; + label = "IP_HW_QDSS"; + mhi,num-elements = <128>; + mhi,event-ring = <7>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@104 { + reg = <104>; + label = "IP_HW_OFFLOAD_0"; + mhi,event-ring = <4>; + mhi,chan-dir = <1>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + }; + + mhi_chan@105 { + reg = <105>; + label = "IP_HW_OFFLOAD_0"; + mhi,event-ring = <5>; + mhi,chan-dir = <2>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + mhi,lpm-notify; + }; + + mhi_chan@107 { + reg = <107>; + label = "IP_HW_MHIP_1"; + mhi,event-ring = <10>; + mhi,chan-dir = <1>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + }; + + mhi_chan@108 { + reg = <108>; + label = "IP_HW_MHIP_1"; + mhi,event-ring = <11>; + mhi,chan-dir = <2>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + mhi,lpm-notify; + }; + }; + + mhi_events { + #address-cells = <1>; + #size-cells = <0>; + + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@2 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <3>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@3 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <4>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@4 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <5>; + mhi,chan = <100>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + }; + + mhi_event@5 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <6>; + mhi,chan = <101>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + }; + + mhi_event@6 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <7>; + mhi,chan = <102>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_event@7 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <8>; + mhi,chan = <103>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,hw-ev; + }; + + mhi_event@8 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <9>; + mhi,chan = <105>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_event@9 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <10>; + mhi,chan = <106>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_event@10 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <11>; + mhi,chan = <107>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_event@11 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <12>; + mhi,chan = <108>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + }; + + mhi_devices { + #address-cells = <1>; + #size-cells = <0>; + mhi_netdev_0: mhi_rmnet@0 { + reg = <0x0>; + mhi,chan = "IP_HW0"; + mhi,interface-name = "rmnet_mhi"; + mhi,mru = <0x8000>; + mhi,chan-skb; + }; + + mhi_rmnet@1 { + reg = <0x1>; + mhi,chan = "IP_HW0_RSC"; + mhi,mru = <0x8000>; + mhi,rsc-parent = <&mhi_netdev_0>; + }; + }; + }; +}; + +&pcie_rc0 { + reg = <0 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + mhi_1: qcom,mhi@0 { + reg = <0 0 0 0 0 >; + + pci-ids = "17cb:0305", "17cb:0306"; + + /* controller specific configuration */ + qcom,smmu-cfg = <0x3>; + qcom,msm-bus,name = "mhi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 1200000000 650000000>; + + /* mhi bus specific settings */ + mhi,max-channels = <110>; + mhi,timeout = <2000>; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@2 { + reg = <2>; + label = "SAHARA"; + mhi,num-elements = <128>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x2>; + }; + + mhi_chan@3 { + reg = <3>; + label = "SAHARA"; + mhi,num-elements = <128>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x2>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@8 { + reg = <8>; + label = "QDSS"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@9 { + reg = <9>; + label = "QDSS"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@10 { + reg = <10>; + label = "EFS"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@11 { + reg = <11>; + label = "EFS"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,wake-capable; + }; + + mhi_chan@14 { + reg = <14>; + label = "QMI0"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@15 { + reg = <15>; + label = "QMI0"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@16 { + reg = <16>; + label = "QMI1"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@17 { + reg = <17>; + label = "QMI1"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@18 { + reg = <18>; + label = "IP_CTRL"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@19 { + reg = <19>; + label = "IP_CTRL"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,auto-queue; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,auto-queue; + mhi,auto-start; + }; + + mhi_chan@22 { + reg = <22>; + label = "TF"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@23 { + reg = <23>; + label = "TF"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@25 { + reg = <25>; + label = "BL"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x2>; + mhi,auto-queue; + mhi,auto-start; + }; + + mhi_chan@26 { + reg = <26>; + label = "DCI"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@27 { + reg = <27>; + label = "DCI"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@32 { + reg = <32>; + label = "DUN"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@33 { + reg = <33>; + label = "DUN"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@100 { + reg = <100>; + label = "IP_HW0"; + mhi,num-elements = <512>; + mhi,event-ring = <4>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <3>; + mhi,ee = <0x4>; + mhi,db-mode-switch; + }; + + mhi_chan@101 { + reg = <101>; + label = "IP_HW0"; + mhi,num-elements = <512>; + mhi,event-ring = <5>; + mhi,chan-dir = <2>; + mhi,data-type = <4>; + mhi,doorbell-mode = <3>; + mhi,ee = <0x4>; + }; + + mhi_chan@102 { + reg = <102>; + label = "IP_HW_ADPL"; + mhi,event-ring = <6>; + mhi,chan-dir = <2>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + mhi,lpm-notify; + }; + + mhi_chan@103 { + reg = <103>; + label = "IP_HW_QDSS"; + mhi,num-elements = <128>; + mhi,event-ring = <7>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@104 { + reg = <104>; + label = "IP_HW_OFFLOAD_0"; + mhi,event-ring = <4>; + mhi,chan-dir = <1>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + }; + + mhi_chan@105 { + reg = <105>; + label = "IP_HW_OFFLOAD_0"; + mhi,event-ring = <5>; + mhi,chan-dir = <2>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + mhi,lpm-notify; + }; + + mhi_chan@107 { + reg = <107>; + label = "IP_HW_MHIP_1"; + mhi,event-ring = <10>; + mhi,chan-dir = <1>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + }; + + mhi_chan@108 { + reg = <108>; + label = "IP_HW_MHIP_1"; + mhi,event-ring = <11>; + mhi,chan-dir = <2>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + mhi,lpm-notify; + }; + }; + + mhi_events { + #address-cells = <1>; + #size-cells = <0>; + + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@2 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <3>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@3 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <4>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@4 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <5>; + mhi,chan = <100>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + }; + + mhi_event@5 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <6>; + mhi,chan = <101>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + }; + + mhi_event@6 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <7>; + mhi,chan = <102>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_event@7 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <8>; + mhi,chan = <103>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,hw-ev; + }; + + mhi_event@8 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <9>; + mhi,chan = <105>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_event@9 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <10>; + mhi,chan = <106>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_event@10 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <11>; + mhi,chan = <107>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_event@11 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <12>; + mhi,chan = <108>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + }; + + mhi_devices { + #address-cells = <1>; + #size-cells = <0>; + mhi_netdev_2: mhi_rmnet@0 { + reg = <0x0>; + mhi,chan = "IP_HW0"; + mhi,interface-name = "rmnet_mhi"; + mhi,mru = <0x8000>; + mhi,chan-skb; + }; + + mhi_rmnet@1 { + reg = <0x1>; + mhi,chan = "IP_HW0_RSC"; + mhi,mru = <0x8000>; + mhi,rsc-parent = <&mhi_netdev_0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-mtp-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/sm8150-mtp-audio-overlay.dtsi new file mode 100644 index 000000000000..00ea584754dc --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-mtp-audio-overlay.dtsi @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm8150-audio-overlay.dtsi" + +&snd_9360 { + qcom,wsa-max-devs = <1>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-mtp-overlay.dts b/arch/arm/boot/dts/qcom/sm8150-mtp-overlay.dts new file mode 100644 index 000000000000..2f454362dfa6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-mtp-overlay.dts @@ -0,0 +1,32 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +/ { + model = "MTP"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; +}; + +&dsi_sharp_4k_dsc_cmd_display { + qcom,dsi-display-active; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-mtp.dts b/arch/arm/boot/dts/qcom/sm8150-mtp.dts new file mode 100644 index 000000000000..897f14959154 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-mtp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150.dtsi" +#include "sm8150-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150 MTP"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-mtp.dtsi b/arch/arm/boot/dts/qcom/sm8150-mtp.dtsi new file mode 100644 index 000000000000..54c520d0981d --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-mtp.dtsi @@ -0,0 +1,686 @@ +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "sm8150-pmic-overlay.dtsi" +#include "sm8150-sde-display.dtsi" +#include "sm8150-camera-sensor-mtp.dtsi" +#include "sm8150-thermal-overlay.dtsi" + +&qupv3_se4_i2c { +#address-cells = <1>; +#size-cells = <0>; + +#include "smb1390.dtsi" +#include "smb1355.dtsi" +}; + +&qupv3_se12_2uart { + status = "ok"; +}; + +&vendor { + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-core-supply = <&pm8150_l7>; + qca,bt-vdd-pa-supply = <&pm8150l_l2>; + qca,bt-vdd-ldo-supply = <&pm8150l_l11>; + + qca,bt-vdd-core-voltage-level = <1800000 1800000>; + qca,bt-vdd-pa-voltage-level = <1304000 1304000>; + qca,bt-vdd-ldo-voltage-level = <3312000 3312000>; + + qca,bt-vdd-core-current-level = <0>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <0>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <0>; /* LPM/PFM */ + }; + + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "fg-gen4-batterydata-alium-3600mah.dtsi" + }; + + extcon_usb1: extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + /*pm8150_gpios 10 is for step motor, use the dummy gpio 165 for driver probe */ + vbus-gpio = <&tlmm 165 GPIO_ACTIVE_HIGH>; + id-gpio = <&tlmm 101 GPIO_ACTIVE_HIGH>; + vbus-out-gpio = <&pm8150_gpios 9 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&usb2_vbus_det_default + &usb2_id_det_default + &usb2_vbus_boost_default>; + }; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + +&qupv3_se3_spi { + status = "ok"; +}; + +&qupv3_se4_i2c { + status = "ok"; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; + + qcomqbt1000:qcom,qbt1000 { + compatible = "qcom,qbt1000"; + clock-names = "core", "iface"; + clock-frequency = <25000000>; + qcom,ipc-gpio = <&tlmm 118 0>; + pinctrl-names = "default"; + pinctrl-0 = <&key_home_default>; + qcom,finger-detect-gpio = <&pm8150_gpios 1 0>; + }; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_vdd_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; + qcom,panel-sec-mode-gpio = <&tlmm 77 0>; + qcom,platform-sec-reset-gpio = <&tlmm 66 0>; +}; + +&dsi_dual_nt35597_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_nt35597_truly_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_nt35597_truly_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_nt35695b_truly_fhd_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&qupv3_se9_i2c { + status = "ok"; + + #address-cells = <1>; + #size-cells = <0>; + + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 47 0x00>; + qcom,nq-ven = <&tlmm 41 0x00>; + qcom,nq-firm = <&tlmm 48 0x00>; + qcom,nq-clkreq = <&tlmm 113 0x00>; + qcom,nq-esepwr = <&tlmm 42 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <47 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active + &nfc_clk_req_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend + &nfc_clk_req_suspend>; + }; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4"; + + vdda-phy-supply = <&pm8150_l5>; + vdda-phy-always-on; + vdda-pll-supply = <&pm8150l_l3>; + vdda-phy-max-microamp = <90200>; + vdda-pll-max-microamp = <19000>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8150_l10>; + vcc-voltage-level = <2504000 2950000>; + vcc-low-voltage-sup; + vccq-supply = <&pm8150_l9>; + vccq2-supply = <&pm8150_s4>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <700000>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&pm8150_l9>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&spmi_debug_bus { + status = "ok"; +}; + +&pm8150l_wled { + qcom,string-cfg= <7>; + qcom,leds-per-string = <6>; + status = "ok"; +}; + +&pm8150l_lcdb { + status = "ok"; +}; + +&pm8150b_fg { + qcom,battery-data = <&mtp_batterydata>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,five-pin-battery; + qcom,cl-wt-enable; + /* ESR fast calibration */ + qcom,fg-esr-timer-chg-fast = <0 7>; + qcom,fg-esr-timer-dischg-fast = <0 7>; + qcom,fg-esr-timer-chg-slow = <0 96>; + qcom,fg-esr-timer-dischg-slow = <0 96>; + /*op disable ers calibration*/ + /*qcom,fg-esr-cal-soc-thresh = <26 230>;*/ + /*qcom,fg-esr-cal-temp-thresh = <10 40>;*/ +}; + +&sdhc_2 { + vdd-supply = <&pm8150l_l9>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8150l_l6>; + qcom,vdd-io-voltage-level = <1808000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>; + + cd-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; + +&pm8150b_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + wp_therm { + reg = ; + label = "wp_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + chg_sbux { + reg = ; + label = "chg_sbux"; + qcom,pre-scaling = <1 3>; + }; + + mid_chg_div6 { + reg = ; + label = "chg_mid"; + qcom,pre-scaling = <1 6>; + }; + + usb_in_i_uv { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + usb_in_v_div_16 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; +}; + +&pm8150_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_therm { + reg = ; + label = "skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm1 { + reg = ; + label = "pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150l_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + camera_flash_therm { + reg = ; + label = "camera_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_msm_therm { + reg = ; + label = "skin_msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm2 { + reg = ; + label = "pa_therm2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&wil6210 { + status = "ok"; +}; + +&mhi_0 { + mhi,fw-name = "debug.mbn"; +}; + +&pm8150b_adc_tm { + wp_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150_adc_tm { + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150l_adc_tm { + camera_flash_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin_msm_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm2 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + wp-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + camera-flash-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-msm-therm { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>; + }; + + pa-therm2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&pm8150b_charger { + qcom,sec-charger-config = <3>; + qcom,auto-recharge-soc = <98>; + io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>, + <&pm8150b_vadc ADC_USB_IN_I>, + <&pm8150b_vadc ADC_SBUx>, + <&pm8150b_vadc ADC_VPH_PWR>, + <&pm8150b_vadc ADC_CHG_TEMP>, + <&pm8150b_vadc ADC_USB_IN_V_16>; + io-channel-names = "mid_voltage", + "usb_in_current", + "sbux_res", + "vph_voltage", + "chg_temp", + "usb_in_voltage"; + qcom,battery-data = <&mtp_batterydata>; + qcom,step-charging-enable; + //qcom,sw-jeita-enable; + qcom,wd-bark-time-secs = <16>; + qcom,suspend-input-on-debug-batt; +}; + +&smb1390 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1390_charger { + /delete-property/ compatible; + compatible = "qcom,smb1390-charger-psy"; + io-channels = <&pm8150b_vadc ADC_AMUX_THM2>; + io-channel-names = "cp_die_temp"; + status = "ok"; +}; + +&usb1 { + extcon = <&extcon_usb1>; + status = "ok"; +}; + +&usb2_phy1 { + status = "ok"; +}; + +&usb_qmp_phy { + status = "ok"; +}; + +&smb1355 { + status = "ok"; +}; + +&smb1355_charger { + io-channels = <&pm8150b_vadc ADC_AMUX_THM2>; + io-channel-names = "charger_temp"; + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-npu.dtsi b/arch/arm/boot/dts/qcom/sm8150-npu.dtsi new file mode 100644 index 000000000000..dfad17576681 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-npu.dtsi @@ -0,0 +1,204 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + msm_npu: qcom,msm_npu@9800000 { + compatible = "qcom,msm-npu"; + status = "ok"; + reg = <0x9800000 0x40000>, + <0x9900000 0x10000>, + <0x9960200 0x600>; + reg-names = "tcm", "core", "bwmon"; + interrupts = , + , + ; + interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq"; + iommus = <&apps_smmu 0x1461 0x0>, <&apps_smmu 0x2061 0x0>; + cache-slice-names = "npu"; + cache-slices = <&llcc 23>; + clocks = <&clock_aop QDSS_CLK>, + <&clock_gcc GCC_NPU_AT_CLK>, + <&clock_gcc GCC_NPU_TRIG_CLK>, + <&clock_npucc NPU_CC_ARMWIC_CORE_CLK>, + <&clock_npucc NPU_CC_CAL_DP_CLK>, + <&clock_npucc NPU_CC_CAL_DP_CDC_CLK>, + <&clock_npucc NPU_CC_CONF_NOC_AHB_CLK>, + <&clock_npucc NPU_CC_COMP_NOC_AXI_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_CTI_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_APB_CLK>, + <&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>, + <&clock_npucc NPU_CC_NPU_CPC_CLK>, + <&clock_npucc NPU_CC_NPU_CPC_TIMER_CLK>, + <&clock_npucc NPU_CC_QTIMER_CORE_CLK>, + <&clock_npucc NPU_CC_SLEEP_CLK>, + <&clock_npucc NPU_CC_BWMON_CLK>, + <&clock_npucc NPU_CC_PERF_CNT_CLK>, + <&clock_npucc NPU_CC_BTO_CORE_CLK>, + <&clock_npucc NPU_CC_XO_CLK>; + clock-names = "qdss_clk", + "at_clk", + "trig_clk", + "armwic_core_clk", + "cal_dp_clk", + "cal_dp_cdc_clk", + "conf_noc_ahb_clk", + "comp_noc_axi_clk", + "npu_core_clk", + "npu_core_cti_clk", + "npu_core_apb_clk", + "npu_core_atb_clk", + "npu_cpc_clk", + "npu_cpc_timer_clk", + "qtimer_core_clk", + "sleep_clk", + "bwmon_clk", + "perf_cnt_clk", + "bto_core_clk", + "xo_clk"; + vdd-supply = <&npu_core_gdsc>; + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,proxy-reg-names ="vdd", "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + #cooling-cells = <2>; + qcom,npubw-dev = <&npu_npu_ddr_bw>; + qcom,npu-cxlimit-enable; + qcom,npu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,npu-pwrlevels"; + initial-pwrlevel = <4>; + qcom,npu-pwrlevel@0 { + reg = <0>; + vreg = <1>; + clk-freq = <0 + 0 + 0 + 100000000 + 300000000 + 300000000 + 19200000 + 150000000 + 100000000 + 37500000 + 19200000 + 60000000 + 100000000 + 19200000 + 19200000 + 0 + 19200000 + 300000000 + 19200000 + 19200000>; + }; + qcom,npu-pwrlevel@1 { + reg = <1>; + vreg = <2>; + clk-freq = <0 + 0 + 0 + 150000000 + 350000000 + 350000000 + 37500000 + 200000000 + 150000000 + 75000000 + 19200000 + 120000000 + 150000000 + 19200000 + 19200000 + 0 + 19200000 + 350000000 + 19200000 + 19200000>; + }; + qcom,npu-pwrlevel@2 { + reg = <2>; + vreg = <3>; + clk-freq = <0 + 0 + 0 + 200000000 + 400000000 + 400000000 + 37500000 + 300000000 + 200000000 + 75000000 + 19200000 + 120000000 + 200000000 + 19200000 + 19200000 + 0 + 19200000 + 400000000 + 19200000 + 19200000>; + }; + qcom,npu-pwrlevel@3 { + reg = <3>; + vreg = <4>; + clk-freq = <0 + 0 + 0 + 300000000 + 600000000 + 600000000 + 75000000 + 403000000 + 300000000 + 150000000 + 19200000 + 240000000 + 300000000 + 19200000 + 19200000 + 0 + 19200000 + 600000000 + 19200000 + 19200000>; + }; + qcom,npu-pwrlevel@4 { + reg = <4>; + vreg = <6>; + clk-freq = <0 + 0 + 0 + 350000000 + 715000000 + 715000000 + 75000000 + 533000000 + 350000000 + 150000000 + 19200000 + 240000000 + 350000000 + 19200000 + 19200000 + 0 + 19200000 + 715000000 + 19200000 + 19200000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-oem-camera-guacamoleb.dtsi b/arch/arm/boot/dts/qcom/sm8150-oem-camera-guacamoleb.dtsi new file mode 100644 index 000000000000..0647e8ebf677 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-oem-camera-guacamoleb.dtsi @@ -0,0 +1,889 @@ +/*this is for camera dtsi*/ +&pm8150l_gpios{ + cam_sensor_pmi_gpio { + + cam_sensor_rear_1_dvdd_active: cam_sensor_rear_1_dvdd_active { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_1_dvdd_suspend: cam_sensor_rear_1_dvdd_suspend { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + }; + + cam_sensor_front_0_ana { + cam_sensor_front_0_ana_active: cam_sensor_front_0_ana_active { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_ana_suspend: cam_sensor_front_0_ana_suspend { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; + + cam_sensor_front_0_dvdd { + cam_sensor_front_0_dvdd_active: cam_sensor_front_0_dvdd_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_dvdd_suspend: cam_sensor_front_0_dvdd_suspend { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; + +}; + +&soc { + led_flash_rear_0: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + + led_flash_rear_1: qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; +}; + +&cam_cci0 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + shared-gpios = <14 13>; + pinctrl-names = "cam_res_mgr_default", "cam_res_mgr_suspend"; + status = "ok"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_1_mclk_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_1_mclk_suspend>; + }; + + actuator_rear_0: qcom,actuator@7 { + cell-index = <7>; + reg = <0x7>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_0_vaf_suspend>; + gpios = <&tlmm 35 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_0"; + }; + + actuator_rear_1: qcom,actuator@8 { + cell-index = <8>; + reg = <0x8>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_0_vaf_suspend>; + gpios = <&tlmm 35 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + ois_rear_0: qcom,ois@2 { + cell-index = <2>; + reg = <2>; + compatible = "qcom,ois"; + cam_vio-supply = <&pm8150l_l1>; + cam_vdig-supply = <&pm8150l_s8>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vio", "cam_vdig", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1352000 3300000>; + rgltr-max-voltage = <0 1352000 3300000>; + rgltr-load-current = <0 1100000 0>; + gpio-no-mux = <0>; + use-shared-clk; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_ois_active + &cam_sensor_rear_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_rear_0_ois_suspend + &cam_sensor_rear_0_dvdd_suspend>; + gpios = <&tlmm 87 0>, + <&tlmm 24 0>; + gpio-vaf = <0>; + gpio-vdig = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <0 0>; + gpio-req-tbl-label = "OIS_REAR_0", + "CAM_VDIG"; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + }; + + ois_rear_1: qcom,ois@1 { + }; + + eeprom_rear_0: qcom,eeprom@7 { + cell-index = <7>; + reg = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_s8>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1352000 0>; + rgltr-max-voltage = <0 3300000 1352000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_dvdd_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 24 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_VDIG_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_1: qcom,eeprom@8 { + cell-index = <8>; + reg = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150_s4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1800000 0>; + rgltr-max-voltage = <0 3300000 1800000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active + &cam_sensor_rear_1_dvdd_active + &cam_sensor_rear_0_ois_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend + &cam_sensor_rear_1_dvdd_suspend + &cam_sensor_rear_0_ois_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>, + <&tlmm 87 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-custom1 = <4>; + gpio-req-tbl-num = <0 1 2 3 0>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1", + "CAM_VDIG_1", + "OIS_REAR_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front_0: qcom,eeprom@9 { + cell-index = <9>; + reg = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_s8>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1352000 0>; + rgltr-max-voltage = <0 3300000 1352000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active + &cam_sensor_front_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend + &cam_sensor_front_0_dvdd_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>, + <&pm8150l_gpios 1 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2", + "CAM_VDIG_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_0>; + actuator-src = <&actuator_rear_0>; + ois-src = <&ois_rear_0>; + eeprom-src = <&eeprom_rear_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_s8>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1352000 0>; + rgltr-max-voltage = <0 3300000 1352000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_ana2_active + &cam_sensor_rear_0_pvdd_active + &cam_sensor_rear_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_ana2_suspend + &cam_sensor_rear_0_pvdd_suspend + &cam_sensor_rear_0_dvdd_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 29 0>, + <&tlmm 25 0>, + <&tlmm 24 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-custom1 = <3>; + gpio-custom2 = <4>; + gpio-vdig = <5>; + gpio-req-tbl-num = <0 1 2 3 4 5>; + gpio-req-tbl-flags = <1 0 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_VANA2_0", + "CAM_PVDD", + "CAM_VDIG"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_1>; + eeprom-src = <&eeprom_rear_1>;//for imx586&s5k3m5 use same eeprom located on master imx586 + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150_s4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1800000 0>; + rgltr-max-voltage = <0 3300000 1800000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active + &cam_sensor_rear_1_dvdd_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend + &cam_sensor_rear_1_dvdd_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1", + "CAM_VDIG_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_s8>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1352000 0>; + rgltr-max-voltage = <0 3300000 1352000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active + &cam_sensor_front_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend + &cam_sensor_front_0_dvdd_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>, + <&pm8150l_gpios 1 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2", + "CAM_VDIG_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; +&tlmm { + cam_sensor_rear_0_mclk_active: cam_sensor_rear_0_mclk_active { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_mclk_suspend: cam_sensor_rear_0_mclk_suspend { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_active: cam_sensor_rear_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_suspend: cam_sensor_rear_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_active: cam_sensor_rear_0_ana_active { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_suspend: cam_sensor_rear_0_ana_suspend { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_active: cam_sensor_rear_0_ana2_active { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_suspend: cam_sensor_rear_0_ana2_suspend { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_pvdd_active: cam_sensor_rear_0_pvdd_active { + /* PVDD */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_pvdd_suspend: cam_sensor_rear_0_pvdd_suspend { + /* PVDD */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_dvdd_active: cam_sensor_rear_0_dvdd_active { + /* VDIG */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_dvdd_suspend: cam_sensor_rear_0_dvdd_suspend { + /* VDIG */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + + cam_sensor_rear_0_vaf_active: cam_sensor_rear_0_vaf_active { + /* AF */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_suspend: cam_sensor_rear_0_vaf_suspend { + /* AF */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ois_active: cam_sensor_rear_0_ois_active { + /* OIS */ + mux { + pins = "gpio87"; + function = "gpio"; + }; + + config { + pins = "gpio87"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ois_suspend: cam_sensor_rear_0_ois_suspend { + /* OIS */ + mux { + pins = "gpio87"; + function = "gpio"; + }; + + config { + pins = "gpio87"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + + cam_sensor_rear_1_mclk_active: cam_sensor_rear_1_mclk_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_suspend: cam_sensor_rear_1_mclk_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_active: cam_sensor_rear_1_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_suspend: cam_sensor_rear_1_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_active: cam_sensor_rear_1_ana_active { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_suspend: cam_sensor_rear_1_ana_suspend { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_active: cam_sensor_rear_1_vaf_active { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_suspend: cam_sensor_rear_1_vaf_suspend { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_active: cam_sensor_front_0_mclk_active { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_suspend: cam_sensor_front_0_mclk_suspend { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_active: cam_sensor_front_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_suspend: cam_sensor_front_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-oem-camera-ov.dtsi b/arch/arm/boot/dts/qcom/sm8150-oem-camera-ov.dtsi new file mode 100644 index 000000000000..c8f15fd08a07 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-oem-camera-ov.dtsi @@ -0,0 +1,854 @@ +&pm8150_gpios{ + cam_sensor_front_0_dig { + cam_sensor_front_0_dig_active: cam_sensor_front_0_dig_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_dig_suspend: cam_sensor_front_0_dig_suspend{ + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; + +&pm8150l_gpios{ + cam_sensor_tof_pmi_gpio { + cam_sensor_tof_ana_active: cam_sensor_tof_ana_active { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_ana_suspend: cam_sensor_tof_ana_suspend { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_tof_dig_active: cam_sensor_tof_dig_active { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_dig_suspend: cam_sensor_tof_dig_suspend { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_tof_vcc_active: cam_sensor_tof_vcc_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_vcc_suspend: cam_sensor_tof_vcc_suspend { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_tof_lvcc_active: cam_sensor_tof_lvcc_active { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_lvcc_suspend: cam_sensor_tof_lvcc_suspend { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; + + cam_sensor_front_0_ana { + cam_sensor_front_0_ana_active: cam_sensor_front_0_ana_active { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_ana_suspend: cam_sensor_front_0_ana_suspend { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; + +&soc { + actuator_rear_1: qcom,actuator@8 { + cell-index = <8>; + reg = <0x8>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_1_vaf_suspend>; + gpios = <&tlmm 35 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + actuator_rear_0: qcom,actuator@7 { + cell-index = <7>; + reg = <0x7>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_0_vaf_suspend>; + gpios = <&tlmm 29 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_0"; + }; + + eeprom_rear_0: qcom,eeprom@7 { + cell-index = <7>; + reg = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1000000 0>; + rgltr-max-voltage = <0 3300000 1200000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_dig_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_dig_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_DIG_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_1: qcom,eeprom@8 { + cell-index = <8>; + reg = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1000000 0>; + rgltr-max-voltage = <0 3300000 1200000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_mclk_active + &cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active + &cam_sensor_rear_1_dig_active>; + pinctrl-1 = <&cam_sensor_rear_1_mclk_suspend + &cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend + &cam_sensor_rear_1_dig_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>, + <&tlmm 26 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1", + "CAM_DIG_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_front_0: qcom,eeprom@9 { + cell-index = <9>; + reg = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1000000 0>; + rgltr-max-voltage = <0 3300000 1200000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active + &cam_sensor_front_0_dig_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend + &cam_sensor_front_0_dig_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>, + <&pm8150_gpios 1 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2", + "CAM_DIG_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_tof: qcom,eeprom@10 { + cell-index = <10>; + reg = <0xA>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0>; + rgltr-max-voltage = <0 0>; + rgltr-load-current = <0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_tof_mclk_active + &cam_sensor_tof_rest_active>; + pinctrl-1 = <&cam_sensor_tof_mclk_suspend + &cam_sensor_tof_rest_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear_0>; + //ois-src = <&ois_rear>; + //eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_dig_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_dig_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&pm8150l_gpios 4 GPIO_ACTIVE_HIGH>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_DIG_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + //eeprom-src = <&eeprom_front>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active + &cam_sensor_front_0_dig_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend + &cam_sensor_front_0_dig_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 4 GPIO_ACTIVE_HIGH>, + <&pm8150l_gpios 1 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2", + "CAM_DIG_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + //laser start + stmvl53l1: st,stmvl53l1@0 { + compatible = "st,stmvl53l1"; + //reg = <0x29>; + //avdd-supply = <&pm8150l_bob>; + laser_vdd-supply = <&pm8150l_l1>; + //pinctrl-names = "laser_default", "laser_suspend"; + //pinctrl-0 = <&stm_laser_pwren_active>; + //pinctrl-1 = <&stm_laser_pwren_suspend>; + xsdn-gpio = <24>; + pwren-gpio = <26>; + intr-gpio = <131>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + }; +//laser end +}; + +&tlmm { + cam_sensor_rear_0_mclk_active: cam_sensor_rear_0_mclk_active { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_mclk_suspend: cam_sensor_rear_0_mclk_suspend { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_active: cam_sensor_rear_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_suspend: cam_sensor_rear_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_active: cam_sensor_rear_0_ana_active { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_suspend: cam_sensor_rear_0_ana_suspend { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_dig_active: cam_sensor_rear_0_dig_active { + /* DIG */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_dig_suspend: cam_sensor_rear_0_dig_suspend { + /* DIG */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_active: cam_sensor_rear_0_vaf_active { + /* DIG */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_suspend: cam_sensor_rear_0_vaf_suspend { + /* DIG */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_active: cam_sensor_rear_1_mclk_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_suspend: cam_sensor_rear_1_mclk_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_active: cam_sensor_rear_1_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_suspend: cam_sensor_rear_1_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_active: cam_sensor_rear_1_ana_active { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_suspend: cam_sensor_rear_1_ana_suspend { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_active: cam_sensor_rear_1_vaf_active { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_suspend: cam_sensor_rear_1_vaf_suspend { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_dig_active: cam_sensor_rear_1_dig_active { + /* DIG */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_dig_suspend: cam_sensor_rear_1_dig_suspend { + /* DIG */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_active: cam_sensor_front_0_mclk_active { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_suspend: cam_sensor_front_0_mclk_suspend { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_active: cam_sensor_front_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_suspend: cam_sensor_front_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_mclk_active: cam_sensor_tof_mclk_active { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_mclk_suspend: cam_sensor_tof_mclk_suspend { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_rest_active: cam_sensor_tof_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_rest_suspend: cam_sensor_tof_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-oem-camera-t0.dtsi b/arch/arm/boot/dts/qcom/sm8150-oem-camera-t0.dtsi new file mode 100644 index 000000000000..137c6903ebca --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-oem-camera-t0.dtsi @@ -0,0 +1,1055 @@ +&pm8150_gpios{ + cam_sensor_laser { + cam_sensor_laser_xsdn_active: cam_sensor_laser_xsdn_active { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_laser_xsdn_suspend: cam_sensor_laser_xsdn_suspend{ + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; + +&pm8150b_gpios{ + cam_sensor_laser { + cam_sensor_laser_intr_active: cam_sensor_laser_intr_active { + pins = "gpio10"; + function = "normal"; + power-source = <0>; + //bias-pull-up; + bias-disable; + output-high; + input-enable; + }; + + cam_sensor_laser_intr_suspend: cam_sensor_laser_intr_suspend{ + pins = "gpio10"; + function = "normal"; + power-source = <0>; + //bias-pull-down; + bias-disable; + output-low; + input-enable; + }; + }; +}; + +&pm8150l_gpios{ + cam_sensor_pmi_gpio { + cam_sensor_rear_0_dvdd_active: cam_sensor_rear_0_dvdd_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_0_dvdd_suspend: cam_sensor_rear_0_dvdd_suspend { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_rear_2_ana_active: cam_sensor_rear_2_ana_active { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_2_ana_suspend: cam_sensor_rear_2_ana_suspend { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_rear_2_af_active: cam_sensor_rear_2_af_active { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_2_af_suspend: cam_sensor_rear_2_af_suspend { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; + + cam_sensor_front_0_ana { + cam_sensor_front_0_ana_active: cam_sensor_front_0_ana_active { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_ana_suspend: cam_sensor_front_0_ana_suspend { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; + +&soc { +//laser start + stmvl53l1: st,stmvl53l1@0 { + compatible = "st,stmvl53l1"; + //reg = <0x29>; + //avdd-supply = <&pm8150l_bob>; + laser_vdd-supply = <&pm8150l_l1>; + pinctrl-names = "laser_default", "laser_suspend"; + pinctrl-0 = <&cam_sensor_laser_xsdn_active + &cam_sensor_laser_pwren_active + &cam_sensor_laser_intr_active>; + pinctrl-1 = <&cam_sensor_laser_xsdn_suspend + &cam_sensor_laser_pwren_suspend + &cam_sensor_laser_intr_suspend>; + xsdn-gpio = <&pm8150_gpios 4 GPIO_ACTIVE_HIGH>; + pwren-gpio = <&tlmm 26 0>; + intr-gpio = <&pm8150b_gpios 10 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&spmi_bus>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + }; +//laser end + + led_flash_rear_0: qcom,camera-flash@7 { + cell-index = <7>; + reg = <0x07 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_1: qcom,camera-flash@8 { + cell-index = <8>; + reg = <0x08 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_2: qcom,camera-flash@9 { + cell-index = <9>; + reg = <0x09 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; +}; + +&cam_cci0 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + shared-gpios = <14 13>; + pinctrl-names = "cam_res_mgr_default", "cam_res_mgr_suspend"; + status = "ok"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_1_mclk_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_1_mclk_suspend>; + }; + + actuator_rear_0: qcom,actuator@7 { + cell-index = <7>; + reg = <0x7>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_0_vaf_suspend>; + gpios = <&tlmm 25 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_0"; + }; + + actuator_rear_1: qcom,actuator@8 { + cell-index = <8>; + reg = <0x8>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_1_vaf_suspend>; + gpios = <&tlmm 35 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + actuator_rear_2: qcom,actuator@9 { + cell-index = <9>; + reg = <0x9>; + compatible = "qcom,actuator"; + cci-device = <1>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_af_active>; + pinctrl-1 = <&cam_sensor_rear_2_af_suspend>; + gpios = <&pm8150l_gpios 4 GPIO_ACTIVE_HIGH>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + ois_rear_0: qcom,ois@02{ + cell-index = <2>; + reg = <2>; + compatible = "qcom,ois"; + cam_vio-supply = <&pm8150l_l1>; + cam_vdig-supply = <&pm8009_l6>;//s5k3m5 ois + cam_vaf-supply = <&pm8009_l5>; + regulator-names = "cam_vio", "cam_vdig", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2856000 2800000>; + rgltr-max-voltage = <0 2856000 2800000>; + rgltr-load-current = <0 80000 0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + }; + + ois_rear_1: qcom,ois@3 { + cell-index = <3>; + reg = <3>; + compatible = "qcom,ois"; + cam_vio-supply = <&pm8150l_l1>; + cam_vdig-supply = <&pm8009_l5>;//imx586 ois + cam_vaf-supply = <&pm8009_l6>; + regulator-names = "cam_vio", "cam_vdig", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2800000 2856000>; + rgltr-max-voltage = <0 2800000 2856000>; + rgltr-load-current = <0 80000 0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + }; + + eeprom_rear_0: qcom,eeprom@7 { + cell-index = <7>; + reg = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1104000 0>; + rgltr-max-voltage = <0 3300000 1104000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_1: qcom,eeprom@8 { + cell-index = <8>; + reg = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front_0: qcom,eeprom@9 { + cell-index = <9>; + reg = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_2: qcom,eeprom@10 { + cell-index = <10>; + reg = <0xA>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_mclk_active + &cam_sensor_rear_2_rest_active + &cam_sensor_rear_2_ana_active>; + pinctrl-1 = <&cam_sensor_rear_2_mclk_suspend + &cam_sensor_rear_2_rest_suspend + &cam_sensor_rear_2_ana_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2 >; + gpio-req-tbl-flags = <1 0 0 >; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA_3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_0>; + actuator-src = <&actuator_rear_0>; + ois-src = <&ois_rear_0>; + eeprom-src = <&eeprom_rear_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1104000 0>; + rgltr-max-voltage = <0 3300000 1104000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_ana2_active + &cam_sensor_rear_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_ana2_suspend + &cam_sensor_rear_0_dvdd_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 29 0>, + <&pm8150l_gpios 1 GPIO_ACTIVE_HIGH>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-custom1 = <3>; + gpio-custom2 = <4>; + gpio-req-tbl-num = <0 1 2 3 4>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_VANA2_0", + "CAM_PVDD"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_1>; + led-flash-src = <&led_flash_rear_1>; + eeprom-src = <&eeprom_rear_0>;//for imx586&s5k3m5 use same eeprom located on master imx586 + ois-src = <&ois_rear_1>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x03>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + led-flash-src = <&led_flash_rear_2>; + eeprom-src = <&eeprom_rear_2>; + actuator-src = <&actuator_rear_2>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_mclk_active + &cam_sensor_rear_2_rest_active + &cam_sensor_rear_2_ana_active>; + pinctrl-1 = <&cam_sensor_rear_2_mclk_suspend + &cam_sensor_rear_2_rest_suspend + &cam_sensor_rear_2_ana_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2 >; + gpio-req-tbl-flags = <1 0 0 >; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA_3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; + +&tlmm { + cam_sensor_rear_0_mclk_active: cam_sensor_rear_0_mclk_active { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_mclk_suspend: cam_sensor_rear_0_mclk_suspend { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_active: cam_sensor_rear_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_suspend: cam_sensor_rear_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_active: cam_sensor_rear_0_ana_active { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_suspend: cam_sensor_rear_0_ana_suspend { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_active: cam_sensor_rear_0_ana2_active { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_suspend: cam_sensor_rear_0_ana2_suspend { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_active: cam_sensor_rear_0_vaf_active { + /* AF */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_suspend: cam_sensor_rear_0_vaf_suspend { + /* AF */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_active: cam_sensor_rear_1_mclk_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_suspend: cam_sensor_rear_1_mclk_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_active: cam_sensor_rear_1_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_suspend: cam_sensor_rear_1_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_active: cam_sensor_rear_1_ana_active { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_suspend: cam_sensor_rear_1_ana_suspend { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_active: cam_sensor_rear_1_vaf_active { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_suspend: cam_sensor_rear_1_vaf_suspend { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_active: cam_sensor_front_0_mclk_active { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_suspend: cam_sensor_front_0_mclk_suspend { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_active: cam_sensor_front_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_suspend: cam_sensor_front_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_mclk_active: cam_sensor_rear_2_mclk_active { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_mclk_suspend: cam_sensor_rear_2_mclk_suspend { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_rest_active: cam_sensor_rear_2_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_rest_suspend: cam_sensor_rear_2_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_pwren_active: cam_sensor_laser_pwren_active { + /* RESET, STANDBY */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_pwren_suspend: cam_sensor_laser_pwren_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-oem-camera-v2.dtsi b/arch/arm/boot/dts/qcom/sm8150-oem-camera-v2.dtsi new file mode 100644 index 000000000000..e80107dee1c1 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-oem-camera-v2.dtsi @@ -0,0 +1,1035 @@ +&pm8150l_gpios{ + cam_sensor_pmi_gpio { + cam_sensor_rear_0_dvdd_active: cam_sensor_rear_0_dvdd_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_0_dvdd_suspend: cam_sensor_rear_0_dvdd_suspend { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_rear_2_ana_active: cam_sensor_rear_2_ana_active { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_2_ana_suspend: cam_sensor_rear_2_ana_suspend { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_rear_2_af_active: cam_sensor_rear_2_af_active { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_2_af_suspend: cam_sensor_rear_2_af_suspend { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; + + cam_sensor_front_0_ana { + cam_sensor_front_0_ana_active: cam_sensor_front_0_ana_active { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_ana_suspend: cam_sensor_front_0_ana_suspend { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; + +&soc { +//laser start + stmvl53l1: st,stmvl53l1@0 { + compatible = "st,stmvl53l1"; + //reg = <0x29>; + //avdd-supply = <&pm8150l_bob>; + laser_vdd-supply = <&pm8150l_l1>; + pinctrl-names = "laser_default", "laser_suspend"; + pinctrl-0 = <&cam_sensor_laser_xsdn_active + &cam_sensor_laser_pwren_active + &cam_sensor_laser_intr_active>; + pinctrl-1 = <&cam_sensor_laser_xsdn_suspend + &cam_sensor_laser_pwren_suspend + &cam_sensor_laser_intr_suspend>; + xsdn-gpio = <&tlmm 24 0>; + pwren-gpio = <&tlmm 26 0>; + intr-gpio = <&tlmm 131 0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + }; +//laser end +}; + +&cam_cci0 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + shared-gpios = <14 13>; + pinctrl-names = "cam_res_mgr_default", "cam_res_mgr_suspend"; + status = "ok"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_1_mclk_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_1_mclk_suspend>; + }; + + actuator_rear_0: qcom,actuator@7 { + cell-index = <7>; + reg = <0x7>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_0_vaf_suspend>; + gpios = <&tlmm 25 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_0"; + }; + + actuator_rear_1: qcom,actuator@8 { + cell-index = <8>; + reg = <0x8>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_1_vaf_suspend>; + gpios = <&tlmm 35 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + actuator_rear_2: qcom,actuator@9 { + cell-index = <9>; + reg = <0x9>; + compatible = "qcom,actuator"; + cci-device = <1>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_af_active>; + pinctrl-1 = <&cam_sensor_rear_2_af_suspend>; + gpios = <&pm8150l_gpios 4 GPIO_ACTIVE_HIGH>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + ois_rear_0: qcom,ois@2 { + cell-index = <2>; + reg = <2>; + compatible = "qcom,ois"; + cam_vio-supply = <&pm8150l_l1>; + cam_vdig-supply = <&pm8009_l6>;//s5k3m5 ois + cam_vaf-supply = <&pm8009_l5>; + regulator-names = "cam_vio", "cam_vdig", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2856000 2800000>; + rgltr-max-voltage = <0 2856000 2800000>; + rgltr-load-current = <0 80000 0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + }; + + ois_rear_1: qcom,ois@3 { + cell-index = <3>; + reg = <3>; + compatible = "qcom,ois"; + cam_vio-supply = <&pm8150l_l1>; + cam_vdig-supply = <&pm8009_l5>;//imx586 ois + cam_vaf-supply = <&pm8009_l6>; + regulator-names = "cam_vio", "cam_vdig", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2800000 2856000>; + rgltr-max-voltage = <0 2800000 2856000>; + rgltr-load-current = <0 80000 0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + }; + + eeprom_rear_0: qcom,eeprom@7 { + cell-index = <7>; + reg = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1104000 0>; + rgltr-max-voltage = <0 3300000 1104000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_1: qcom,eeprom@8 { + cell-index = <8>; + reg = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1050000 0>; + rgltr-max-voltage = <0 3300000 1050000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front_0: qcom,eeprom@9 { + cell-index = <9>; + reg = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_2: qcom,eeprom@10 { + cell-index = <10>; + reg = <0xA>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1050000 0>; + rgltr-max-voltage = <0 3300000 1050000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_mclk_active + &cam_sensor_rear_2_rest_active + &cam_sensor_rear_2_ana_active>; + pinctrl-1 = <&cam_sensor_rear_2_mclk_suspend + &cam_sensor_rear_2_rest_suspend + &cam_sensor_rear_2_ana_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2 >; + gpio-req-tbl-flags = <1 0 0 >; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA_3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear_0>; + ois-src = <&ois_rear_0>; + eeprom-src = <&eeprom_rear_1>;//for imx586&s5k3m5 use same eeprom located on slave s5k3m5 + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1104000 0>; + rgltr-max-voltage = <0 3300000 1104000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_ana2_active + &cam_sensor_rear_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_ana2_suspend + &cam_sensor_rear_0_dvdd_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 29 0>, + <&pm8150l_gpios 1 GPIO_ACTIVE_HIGH>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-custom1 = <3>; + gpio-custom2 = <4>; + gpio-req-tbl-num = <0 1 2 3 4>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_VANA2_0", + "CAM_PVDD"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_1>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_1>; + ois-src = <&ois_rear_1>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1050000 0>; + rgltr-max-voltage = <0 3300000 1050000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x03>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_rear_2>; + actuator-src = <&actuator_rear_2>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1050000 0>; + rgltr-max-voltage = <0 3300000 1050000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_mclk_active + &cam_sensor_rear_2_rest_active + &cam_sensor_rear_2_ana_active>; + pinctrl-1 = <&cam_sensor_rear_2_mclk_suspend + &cam_sensor_rear_2_rest_suspend + &cam_sensor_rear_2_ana_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2 >; + gpio-req-tbl-flags = <1 0 0 >; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA_3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; + +&tlmm { + cam_sensor_rear_0_mclk_active: cam_sensor_rear_0_mclk_active { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_mclk_suspend: cam_sensor_rear_0_mclk_suspend { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_active: cam_sensor_rear_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_suspend: cam_sensor_rear_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_active: cam_sensor_rear_0_ana_active { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_suspend: cam_sensor_rear_0_ana_suspend { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_active: cam_sensor_rear_0_ana2_active { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_suspend: cam_sensor_rear_0_ana2_suspend { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_active: cam_sensor_rear_0_vaf_active { + /* AF */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_suspend: cam_sensor_rear_0_vaf_suspend { + /* AF */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_active: cam_sensor_rear_1_mclk_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_suspend: cam_sensor_rear_1_mclk_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_active: cam_sensor_rear_1_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_suspend: cam_sensor_rear_1_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_active: cam_sensor_rear_1_ana_active { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_suspend: cam_sensor_rear_1_ana_suspend { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_active: cam_sensor_rear_1_vaf_active { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_suspend: cam_sensor_rear_1_vaf_suspend { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_active: cam_sensor_front_0_mclk_active { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_suspend: cam_sensor_front_0_mclk_suspend { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_active: cam_sensor_front_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_suspend: cam_sensor_front_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_mclk_active: cam_sensor_rear_2_mclk_active { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_mclk_suspend: cam_sensor_rear_2_mclk_suspend { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_rest_active: cam_sensor_rear_2_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_rest_suspend: cam_sensor_rear_2_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_xsdn_active: cam_sensor_laser_xsdn_active { + /* RESET, STANDBY */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_xsdn_suspend: cam_sensor_laser_xsdn_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_pwren_active: cam_sensor_laser_pwren_active { + /* RESET, STANDBY */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_pwren_suspend: cam_sensor_laser_pwren_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_intr_active: cam_sensor_laser_intr_active { + /* RESET, STANDBY */ + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_intr_suspend: cam_sensor_laser_intr_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-oem-camera.dtsi b/arch/arm/boot/dts/qcom/sm8150-oem-camera.dtsi new file mode 100644 index 000000000000..08f12def4458 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-oem-camera.dtsi @@ -0,0 +1,968 @@ +&pm8150_gpios{ + cam_sensor_front_0_dig { + cam_sensor_front_0_dig_active: cam_sensor_front_0_dig_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_dig_suspend: cam_sensor_front_0_dig_suspend{ + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; + +&pm8150l_gpios{ + cam_sensor_tof_pmi_gpio { + cam_sensor_tof_ana_active: cam_sensor_tof_ana_active { + pins = "gpio3"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_ana_suspend: cam_sensor_tof_ana_suspend { + pins = "gpio3"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_tof_dig_active: cam_sensor_tof_dig_active { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_dig_suspend: cam_sensor_tof_dig_suspend { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_tof_vcc_active: cam_sensor_tof_vcc_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_vcc_suspend: cam_sensor_tof_vcc_suspend { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_tof_lvcc_active: cam_sensor_tof_lvcc_active { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_lvcc_suspend: cam_sensor_tof_lvcc_suspend { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; + + cam_sensor_front_0_ana { + cam_sensor_front_0_ana_active: cam_sensor_front_0_ana_active { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_ana_suspend: cam_sensor_front_0_ana_suspend { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; +&soc { + actuator_rear_0: qcom,actuator@7 { + cell-index = <7>; + reg = <0x7>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_0_vaf_suspend>; + gpios = <&tlmm 24 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_0"; + }; + + actuator_rear_1: qcom,actuator@8 { + cell-index = <8>; + reg = <0x8>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_1_vaf_suspend>; + gpios = <&tlmm 35 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + eeprom_rear_0: qcom,eeprom@7 { + cell-index = <7>; + reg = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_dig_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_dig_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 29 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_DIG_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_1: qcom,eeprom@8 { + cell-index = <8>; + reg = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_mclk_active + &cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active + &cam_sensor_rear_1_dig_active>; + pinctrl-1 = <&cam_sensor_rear_1_mclk_suspend + &cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend + &cam_sensor_rear_1_dig_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>, + <&tlmm 26 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1", + "CAM_DIG_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_front_0: qcom,eeprom@9 { + cell-index = <9>; + reg = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active + &cam_sensor_front_0_dig_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend + &cam_sensor_front_0_dig_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>, + <&pm8150_gpios 1 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2", + "CAM_DIG_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_tof: qcom,eeprom@10 { + cell-index = <10>; + reg = <0xA>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0>; + rgltr-max-voltage = <0 0>; + rgltr-load-current = <0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_tof_mclk_active + &cam_sensor_tof_rest_active>; + pinctrl-1 = <&cam_sensor_tof_mclk_suspend + &cam_sensor_tof_rest_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear_0>; + //ois-src = <&ois_rear>; + eeprom-src = <&eeprom_rear_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_dig_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_dig_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 29 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_DIG_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_1>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_1>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_mclk_active + &cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active + &cam_sensor_rear_1_dig_active>; + pinctrl-1 = <&cam_sensor_rear_1_mclk_suspend + &cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend + &cam_sensor_rear_1_dig_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>, + <&tlmm 26 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1", + "CAM_DIG_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active + &cam_sensor_front_0_dig_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend + &cam_sensor_front_0_dig_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>, + <&pm8150_gpios 1 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2", + "CAM_DIG_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x03>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_rear_tof>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_tof_mclk_active + &cam_sensor_tof_rest_active + &cam_sensor_tof_ana_active + &cam_sensor_tof_dig_active + &cam_sensor_tof_vcc_active + &cam_sensor_tof_lvcc_active>; + pinctrl-1 = <&cam_sensor_tof_mclk_suspend + &cam_sensor_tof_rest_suspend + &cam_sensor_tof_ana_suspend + &cam_sensor_tof_dig_suspend + &cam_sensor_tof_vcc_suspend + &cam_sensor_tof_lvcc_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&pm8150l_gpios 3 GPIO_ACTIVE_HIGH>, + <&pm8150l_gpios 4 GPIO_ACTIVE_HIGH>, + <&pm8150l_gpios 1 GPIO_ACTIVE_HIGH>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-custom1 = <4>; + gpio-custom2 = <5>; + gpio-req-tbl-num = <0 1 2 3 4 5>; + gpio-req-tbl-flags = <1 0 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA_3", + "CAM_DIG_3", + "CAM_VCC_3", + "CAM_LVCC_3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +//laser start + stmvl53l1: st,stmvl53l1@0 { + compatible = "st,stmvl53l1"; + //reg = <0x29>; + //avdd-supply = <&pm8150l_bob>; + laser_vdd-supply = <&pm8150l_l1>; + //pinctrl-names = "laser_default", "laser_suspend"; + //pinctrl-0 = <&stm_laser_pwren_active>; + //pinctrl-1 = <&stm_laser_pwren_suspend>; + xsdn-gpio = <30>; + pwren-gpio = <11>; + intr-gpio = <131>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + }; +//laser end +}; + +&tlmm { + cam_sensor_rear_0_mclk_active: cam_sensor_rear_0_mclk_active { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_mclk_suspend: cam_sensor_rear_0_mclk_suspend { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_active: cam_sensor_rear_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_suspend: cam_sensor_rear_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_active: cam_sensor_rear_0_ana_active { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_suspend: cam_sensor_rear_0_ana_suspend { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_dig_active: cam_sensor_rear_0_dig_active { + /* DIG */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_dig_suspend: cam_sensor_rear_0_dig_suspend { + /* DIG */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_active: cam_sensor_rear_0_vaf_active { + /* DIG */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_suspend: cam_sensor_rear_0_vaf_suspend { + /* DIG */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_active: cam_sensor_rear_1_mclk_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_suspend: cam_sensor_rear_1_mclk_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_active: cam_sensor_rear_1_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_suspend: cam_sensor_rear_1_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_active: cam_sensor_rear_1_ana_active { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_suspend: cam_sensor_rear_1_ana_suspend { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_active: cam_sensor_rear_1_vaf_active { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_suspend: cam_sensor_rear_1_vaf_suspend { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_dig_active: cam_sensor_rear_1_dig_active { + /* DIG */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_dig_suspend: cam_sensor_rear_1_dig_suspend { + /* DIG */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_active: cam_sensor_front_0_mclk_active { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_suspend: cam_sensor_front_0_mclk_suspend { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_active: cam_sensor_front_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_suspend: cam_sensor_front_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_mclk_active: cam_sensor_tof_mclk_active { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_mclk_suspend: cam_sensor_tof_mclk_suspend { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_rest_active: cam_sensor_tof_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_rest_suspend: cam_sensor_tof_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-oem.dtsi b/arch/arm/boot/dts/qcom/sm8150-oem.dtsi new file mode 100644 index 000000000000..57eba48c3557 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-oem.dtsi @@ -0,0 +1,1340 @@ +/* Display */ +&soc { + dsi_samsung_oneplus_dsc_cmd_display: qcom,dsi-display@23 { + label = "dsi_samsung_oneplus_dsc_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-panel = <&dsi_samsung_oneplus_dsc_cmd>; + }; + + dsi_samsung_s6e3fc2x01_cmd_display: qcom,dsi-display@24 { + label = "dsi_samsung_s6e3fc2x01_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-panel = <&dsi_samsung_s6e3fc2x01_cmd>; + }; + + dsi_samsung_sofef00_m_video_display: qcom,dsi-display@27 { + label = "dsi_samsung_sofef00_m_video_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-panel = <&dsi_samsung_sofef00_m_video>; + }; + + + tri_state_key:tri_state_key { + compatible = "oneplus, tri-state-key"; + status = "okay"; + interrupt-parent = <&tlmm>; + tristate,gpio_key1 = <&tlmm 27 0x00>; + tristate,gpio_key2 = <&tlmm 134 0x00>; + tristate,gpio_key3 = <&tlmm 125 0x00>; + pinctrl-names = + "pmx_tri_state_key_active", + "pmx_tri_state_key_suspend"; + pinctrl-0 = <&tri_state_key_active>; + pinctrl-1 = <&tri_state_key_suspend>; + }; + + fingerprint_detect:fingerprint_detect { + compatible = "oneplus,fpdetect"; + fp-gpio-id0 = <&tlmm 90 0>; + fp-gpio-id1 = <&pm8150_gpios 3 0>; + pinctrl-names = "fp_id_init"; + pinctrl-0 = <&fp_id0_init &fp_id1_init>; + }; + + goodix_fp { + compatible = "goodix,fingerprint"; + interrupt-parent = <&tlmm>; + //vdd-3v2-supply = <&pm8998_l22>; + //vdd-voltage = <3200000 3200000>; + //vdd-current = <50000>; + fp-gpio-irq = <&tlmm 118 0x00>; + fp-gpio-reset = <&tlmm 131 0x00>; + fp-gpio-enable = <&tlmm 101 0x00>; + pinctrl-names = "fp_en_init", "fp_dis_init"; + pinctrl-0 = <&fp_vdd_init &fp_irq_init>; + pinctrl-1 = <&fp_vdd_dis_init>; + status = "okay"; + }; +}; + +&qcomqbt1000{ + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; + qfp-int2 = <&tlmm 131 0x00>; + qcom,finger-detect-gpio = <&tlmm 101 0>; +}; + +&sde_dsi { + pinctrl-names = "panel_active", "panel_suspend","default"; + pinctrl-0 = <&sde_dsi_active &sde_te_active &display_panel_avdd_eldo_default>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend &display_panel_avdd_eldo_off>; + /delete-property/ lab-supply; + /delete-property/ ibb-supply; + /delete-property/ vdd-supply; + qcom,dsi-display-list = + <&dsi_samsung_oneplus_dsc_cmd_display + &dsi_samsung_s6e3fc2x01_cmd_display + &dsi_samsung_sofef00_m_video_display>; +}; + +&tlmm{ + display_panel_avdd_eldo_off: display_panel_avdd_eldo_off { + mux { + pins = "gpio130"; + function = "gpio"; + }; + config { + pins = "gpio130"; + drive-strength = <8>; + bias-disable = <0>; + output-low; + }; + }; + + tri_state_key_active: tri_state_key_active { + mux { + pins = "gpio125", "gpio134", "gpio27"; + function = "gpio"; + }; + config { + pins = "gpio125", "gpio134", "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; + + tri_state_key_suspend: tri_state_key_suspend { + mux { + pins = "gpio125", "gpio134", "gpio27"; + function = "gpio"; + }; + config { + pins = "gpio125", "gpio134", "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; + +}; + +//wangdongdong@AudioDrv, add for 4M memory increase of adsp begain +&pil_adsp_mem { + reg = <0x0 0x8be00000 0x0 0x1e00000>; +}; + +&pil_modem_mem { + reg = <0x0 0x8dc00000 0x0 0x9600000>; +}; + +&pil_video_mem { + reg = <0x0 0x97200000 0x0 0x500000>; +}; + +&pil_slpi_mem { + reg = <0x0 0x97700000 0x0 0x1400000>; +}; + +&pil_ipa_fw_mem { + reg = <0x0 0x98b00000 0x0 0x10000>; +}; + +&pil_ipa_gsi_mem { + reg = <0x0 0x98b10000 0x0 0x5000>; +}; + +&pil_gpu_mem { + reg = <0x0 0x98b15000 0x0 0x2000>; +}; + +&pil_spss_mem { + reg = <0x0 0x98c00000 0x0 0x100000>; +}; + +&pil_cdsp_mem { + reg = <0x0 0x98d00000 0x0 0x1400000>; +}; +//wangdongdong@AudioDrv, add for 4M memory increase of adsp end + +//dujie@MM.Audio add begain +/* #if OP_FEATURE_MM_RECORDING_SCREEN == 1*/ +/* zhanglixia@MM.Audio, 2019/07/13, add for screen record*/ + +&snd_934x { + qcom,afe-rxtx-lb = <1>; + asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, + <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, + <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, + <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, <&sb_5_rx>, <&sb_6_rx>, + <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, + <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, + <&dai_quat_tdm_rx_1>, + <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>, + <&afe_loopback_tx>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", + "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", + "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", + "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", + "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", + "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", + "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", + "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", + "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", + "msm-dai-q6-tdm.36914", + "msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36929", + "msm-dai-q6-dev.24577"; +}; +/* #endif*/ +&snd_9360 { + status = "disabled"; +}; +&wcd9360_cdc { + status = "disabled"; +}; +&clock_audio { + status = "disabled"; +}; + +&snd_934x { + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "hifi amp", "LINEOUT1", + "hifi amp", "LINEOUT2", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC3", "MIC BIAS4", + "MIC BIAS4", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS1", + "MIC BIAS1", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS1", + "MIC BIAS1", "Handset Mic", + "DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "DMIC4", "MIC BIAS4", + "MIC BIAS4", "Digital Mic4", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT"; + + qcom,wsa-max-devs = <0>; + qcom,msm-mbhc-usbc-audio-supported = <1>; + qcom,msm-mbhc-hs-mic-max-threshold-mv = <2550>; + pinctrl-names = "quat_mi2s_enable","quat_mi2s_disable", + "quat_tdm_enable","quat_tdm_disable"; + pinctrl-0 = <&quat_mi2s_active + &quat_mi2s_sd0_active &quat_mi2s_sd1_active>; + pinctrl-1 = <&quat_mi2s_sleep + &quat_mi2s_sd0_sleep &quat_mi2s_sd1_sleep>; + pinctrl-2 = <&quat_tdm_active + &quat_tdm_din_active &quat_tdm_dout_active>; + pinctrl-3 = <&quat_tdm_sleep + &quat_tdm_din_sleep &quat_tdm_dout_sleep>; + + // yewenliang@MM.Audio, 2019/06/07, fix cap noise issues in handset mode + vreg_ldo-supply = <&pm8150l_l10>; + vreg_bob-supply = <&pm8150l_bob>; +}; + +&wcd934x_cdc { + qcom,cdc-micbias1-mv = <2700>; + qcom,cdc-micbias2-mv = <2700>; + qcom,cdc-micbias4-mv = <2700>; +}; + +&wsa881x_70211{ + status = "disabled"; +}; + +&wsa881x_70212{ + status = "disabled"; +}; + +&wsa881x_70213{ + status = "disabled"; +}; + +&wsa881x_70214{ + status = "disabled"; +}; + +&qupv3_se4_i2c { + tfa98xx_right: tfa98xx_right@34 { + compatible = "nxp,tfa98xx"; + reg = <0x34>; + reset-gpio = <&tlmm 37 0>; + status = "ok"; + }; + + tfa98xx_left: tfa98xx_left@35 { + compatible = "nxp,tfa98xx"; + reg = <0x35>; + reset-gpio = <&tlmm 100 0>; + status = "ok"; + }; +}; + +&dai_mi2s3 { + qcom,msm-mi2s-rx-lines = <2>; + qcom,msm-mi2s-tx-lines = <1>; +}; + +//Because pcie0 wakeup-gpio is same pa-gpio, so disabled it +&pcie0 { + status = "disabled"; +}; +//dujie@MM.Audio add end + +&sde_dsi_active { + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + drive-strength = <8>; + bias-disable = <0>; + }; +}; +&sde_dsi_suspend { + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + drive-strength = <2>; + bias-pull-down; + }; +}; + +/*for aw haptic start*/ +&qupv3_se7_i2c { + status = "ok"; + aw8697_haptic:aw8697_haptic@5A { + compatible = "awinic,aw8697_haptic"; + reg = <0x5A>; + reset-gpio = <&tlmm 116 0x00>; + irq-gpio = <&tlmm 24 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <&aw_irq &aw_reset>; + status = "okay"; + }; +}; +/*for aw haptic end*/ + +/* Touch */ +&qupv3_se17_i2c { + status = "ok"; + sec-s6sy761@48 { + compatible = "sec-s6sy761"; + reg = <0x48>; + project-name = "18821"; + chip-name = "SY761"; + module_id = <7>; + reset-gpio = <&tlmm 54 0x00>; + irq-gpio = <&tlmm 122 0x2008>; + vdd_2v8-supply = <&pm8150_l17>; //set 3.3 by ldo + vdd_2v8_volt = <3008000>; + //enable1v8_gpio = <&tlmm 119 0x00>; //set 1.8v by gpio + touchpanel,display-coords = <1439 3119>; + touchpanel,panel-coords = <1439 3119>; + touchpanel,tx-rx-num = <17 37>; + //edge_limit_support = <1>; + //spurious_fingerprint_support = <1>; + //charger_pump_support = <1>; + charge_detect_support = <1>; + black_gesture_support = <1>; + //black_gesture_test_support = <1>; + game_switch_support = <1>; + face_detect_support = <1>; + lcd_refresh_rate_switch = <1>; + touch_hold_support = <1>; + //lcd_trigger_fp_check = <1>; + pinctrl-names = "pin_set_high", "pin_set_low"; + pinctrl-0 = <&tp_1v8_active &tp_irq_active &tp_rst_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_suspend>; + }; +}; +&qupv3_se17_i2c { + status = "ok"; + synaptics-s3706@20 { + compatible = "synaptics-s3706"; + reg = <0x20>; + //project-name = "18857"; + chip-name = "S3706"; + //reset-gpio = <&tlmm 54 0x00>; + irq-gpio = <&tlmm 122 0x2008>; + vdd_2v8-supply = <&pm8150_l17>; //set 3.3 by ldo + vdd_2v8_volt = <3008000>; + //enable1v8_gpio = <&tlmm 59 0x00>; //set 1.8v by gpio + //touchpanel,display-coords = <1080 2340>; + //touchpanel,panel-coords = <1080 2340>; + //touchpanel,tx-rx-num = <16 33>; + black_gesture_support = <1>; + face_detect_support = <1>; + touch_hold_support = <1>; + charge_detect_support = <1>; + module_id = <7>; + pinctrl-names = "pin_set_high", "pin_set_low"; + pinctrl-0 = <&tp_irq_active &tp_rst_active &tp_1v8_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_suspend>; + }; +}; + +/* Add for NXP NFCC */ +&qupv3_se9_i2c { + nq@28 { + status = "disabled"; + }; + + pn5xx@28 { + compatible = "nxp,pn544"; + reg = <0x28>; + nxp,pn544-irq = <&tlmm 47 0x00>; + nxp,pn544-ven = <&tlmm 41 0x00>; + nxp,pn544-fw-dwnld = <&tlmm 48 0x00>; + nxp,pn544-clk-gpio = <&tlmm 113 0x00>; + nxp,pn544-ese-pwr = <&tlmm 49 0x00>; + nfc_voltage_s4-supply = <&pm8150_s4>; + interrupt-parent = <&tlmm>; + qcom,clk-src = "BBCLK3"; + interrupts = <47 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + +/* Add for NXP eSE */ +&qupv3_se0_spi { + status = "ok"; + + ese@0 { + compatible = "nxp,p61"; + reg = <0>; + spi-max-frequency = <8000000>; + nxp,nfcc = "4-0028"; + }; +}; + +&tlmm { + +aw_irq: aw_irq { + mux { + pins = "gpio116"; + function = "gpio"; + }; + + config { + pins = "gpio116"; + drive-strength = <2>; + }; + }; + +aw_reset: aw_reset { + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; + bias-disable; + }; + }; + +tp_irq_active: tp_irq_active { + mux { + pins = "gpio122"; + function = "gpio"; + }; + config { + pins = "gpio122"; + drive-strength = <8>; + bias-disable; + input-enable; + }; + }; + tp_rst_active: tp_rst_active { + mux { + pins = "gpio54"; + function = "gpio"; + }; + config { + pins = "gpio54"; + drive-strength = <8>; + bias-disable; + }; + }; + tp_1v8_active: tp_1v8_active { + mux { + pins = "gpio119"; + function = "gpio"; + }; + config { + pins = "gpio119"; + drive-strength = <8>; + bias-pull-up; + }; + }; + tp_rst_suspend: tp_rst_suspend { + mux { + pins = "gpio54"; + function = "gpio"; + }; + config { + pins = "gpio54"; + drive-strength = <8>; + bias-pull-down; + }; + }; + tp_1v8_suspend: tp_1v8_suspend { + mux { + pins = "gpio119"; + function = "gpio"; + }; + config { + pins = "gpio119"; + drive-strength = <8>; + bias-pull-down; + }; + }; + + fp_irq_init: fp_irq_init { + mux { + pins = "gpio118"; + function = "gpio"; + }; + + config { + pins = "gpio118"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + }; + + fp_reset_init: fp_reset_init { + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + fp_vdd_init: fp_vdd_init { + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + drive-strength = <8>; + bias-pull-up; + output-high; + }; + }; + + fp_vdd_dis_init: fp_vdd_dis_init { + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + drive-strength = <8>; + bias-pull-down; + output-low; + }; + }; + + fp_id0_init: fp_id0_init { + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; + bias-disable; /* No Pull */ + input-enable; + }; + }; +}; + +&vendor { + infrared_pl: infrared_pl { + compatible = "oneplus-infrared"; + vdd-supply = <&pm8150l_l9>; + }; +}; + + +//quentin.lin add 2018/11/07 +&vendor { + motor_pl: motor_pl { + compatible = "oneplus-motor"; + interrupt-parent = <&tlmm>; + interrupts = <163 0x2>; + motor,irq-gpio = <&tlmm 163 0x2008>; + pinctrl-names = "free_fall_input"; + pinctrl-0 = <&free_fall_input>; + structure,id = <0>; + }; +}; + + +// quentin.lin@oneplus.com 2018/11/26 edit for free fall +&tlmm { + free_fall_input: free_fall_input { + mux { + pins = "gpio163"; + function = "gpio"; + }; + config { + pins = "gpio163"; + drive-strength = <2>; + input-enable; + bias-disable; //No Pull + }; + }; + +}; + + +&qupv3_se1_i2c { + status = "ok"; + magnachip@0C { + compatible = "magnachip,mxm1120,up"; + reg = <0x0C>; + vdd-supply = <&pm8150l_l7>; + vio-supply = <&pm8150l_l8>; + magnachip,init-interval = <200>; + interrupt-parent = <&tlmm>; + interrupts = <120 0x2>; + dhall,irq-gpio = <&tlmm 120 0x2008>; + mxm,id = <1>; + }; + magnachip@0D { + compatible = "magnachip,mxm1120,down"; + reg = <0x0D>; + vdd-supply = <&pm8150l_l7>; + vio-supply = <&pm8150l_l8>; + magnachip,init-interval = <200>; + interrupt-parent = <&tlmm>; + interrupts = <121 0x2>; + dhall,irq-gpio = <&tlmm 121 0x2008>; + mxm,id = <2>; + }; +}; + + +/* @bsp, 2019/04/17 Battery & Charging porting STRAT */ +&qupv3_se8_i2c { + qcom,clk-freq-out = <100000>; + status = "ok"; + bq27541_battery:bq27541-battery@55 { + status = "ok"; + compatible = "ti,bq27541-battery"; + reg = <0x55>; + qcom,modify-soc-smooth; + }; + + oneplus_fastchg@26{ + status = "ok"; + compatible = "microchip,oneplus_fastchg"; + reg = <0x26>; + microchip,mcu-en-gpio = <&tlmm 10 0x00>; + microchip,usb-sw-1-gpio = <&tlmm 94 0x00>; + microchip,usb-sw-2-gpio = <&tlmm 59 0x00>; + microchip,ap-clk = <&tlmm 92 0x00>; + microchip,ap-data = <&tlmm 93 0x00>; + + pinctrl-names = "mux_fastchg_active", + "mux_fastchg_suspend", + "mcu_data_active", + "mcu_data_suspend"; + pinctrl-0 = <&fastchg_active + &usb_sw_active + &ap_clk_active>; + pinctrl-1 = <&usb_sw_suspend + &fastchg_suspend + &ap_clk_suspend>; + pinctrl-2 =<&ap_data_active>; + pinctrl-3 =<&ap_data_suspend>; + op,fw-erase-count = <384>; + op,fw-addr-low = <0x88>; + op,fw-addr-high = <0>; + }; +}; + +&pm8150b_gpios { + gpio1_adc { + gpio1_adc_default: gpio1_adc_default { + pins = "gpio1"; /* GPIO 1 */ + function = "normal"; /* normal */ + bias-pull-up; + bias-high-impedance; /* DISABLE GPIO1 for ADC*/ + }; + }; + + gpio12_adc { + gpio12_adc_default: gpio12_adc_default { + pins = "gpio12"; /* GPIO 12 */ + function = "normal"; /* normal */ + bias-pull-up; + bias-high-impedance; /* DISABLE GPIO12 for ADC*/ + }; + }; +}; + +&pm8150b_vadc { + gpio12_v { + reg = ; + label = "gpio12_v"; + qcom,pre-scaling = <1 1>; + }; + gpio1_v { + reg = ;/* 0x30*/ + label = "gpio1_v"; + qcom,ratiometric; + qcom,hw-settle-time = <800>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150b_charger { + qcom,dc-icl-ua = <1200000>; + qcom,fcc-max-ua = <500000>; + qcom,usb-icl-ua = <1800000>; + qcom,fv-max-uv = <4365000>; + /* ibatmax setting for different temp regions */ + ibatmax-little-cold-ma = <350>; + ibatmax-cool-ma = <2000>; + ibatmax-little-cool-ma = <2100>; + ibatmax-pre-normal-ma = <2100>; + ibatmax-normal-ma = <3000>; + ibatmax-warm-ma = <1100>; + ibatmax-little-cool-thr-ma = <1900>; + ibatmax-cool-thr-ma = <1100>; + /* vbatmax setting for different temp regions */ + vbatmax-little-cold-mv = <3975>; + vbatmax-cool-mv = <4390>; + vbatmax-little-cool-mv = <4390>; + vbatmax-pre-normal-mv = <4390>; + vbatmax-normal-mv = <4390>; + vbatmax-warm-mv = <4130>; + little-cool-vbat-thr-mv = <4180>; + cool-vbat-thr-mv = <4180>; + /* vbatdet setting for different temp regions */ + vbatdet-little-cold-mv = <3700>; + vbatdet-cool-mv = <4150>; + vbatdet-little-cool-mv = <4270>; + vbatdet-pre-normal-mv = <4270>; + vbatdet-normal-mv = <4270>; + vbatdet-warm-mv = <3980>; + /* temp region settings */ + cold-bat-decidegc = <20>; + little-cold-bat-decidegc = <0>; + cool-bat-decidegc = <50>; + little-cool-bat-decidegc = <120>; + pre-normal-bat-decidegc = <160>; + warm-bat-decidegc = <450>; + hot-bat-decidegc = <500>; + qcom,otg-cl-ua = <1500000>; + op,sw-iterm-ma = <310>; + op,sw-check-full-enable; + + /*otg low battery current limit*/ + op,otg-icl-ctrl-enable; + otg-low-battery-thr = <15>; + otg-low-bat-icl-thr = <1000000>; + otg-normal-bat-icl-thr = <1500000>; + //disable-pd; + qcom,lpd-disable; + /*add to disable HVDCP*/ + qcom,hvdcp-disable; + /*usb connector hw auto detection*/ + op,usb-check = <&tlmm 91 0x00>; + /* other settings */ + qcom,cutoff-voltage-with-charger = <3250>; + qcom,msm-bus,name = "dash_clk_vote"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <1 731 0 300000000>, + <1 731 0 0>; + /*ffc temp region*/ + ffc-pre-normal-decidegc = <160>; + ffc-normal-decidegc = <350>; + ffc-warm-decidegc = <400>; + ffc-normal-fcc-ma = <650>; + ffc-warm-fcc-ma = <750>; + ffc-normal-cutoff-ma = <550>; + ffc-warm-cutoff-ma = <650>; + ffc-full-vbat-mv = <4430>; + + /* for external ship mode suppot */ + pinctrl-names = "op_ship_mode_default","op_usb_temp_adc_default"; + pinctrl-0 = <&ship_mode_default>; + pinctrl-1= <&gpio1_adc_default>; + + op,stm-ctrl-gpio = <&tlmm 21 0x00>; + /* for usb connector temp protect */ + op,low-voltage-charger; + io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>, + <&pm8150b_vadc ADC_USB_IN_V_16>, + <&pm8150b_vadc ADC_USB_IN_I>, + <&pm8150b_vadc ADC_CHG_TEMP>, + <&pm8150b_vadc ADC_AMUX_THM4_PU1>, + <&pm8150b_vadc ADC_VPH_PWR>, + <&pm8150b_vadc ADC_SBUx>; + io-channel-names = "mid_voltage", + "usb_in_voltage", + "usb_in_current", + "chg_temp", + "gpio1_voltage", + "vph_voltage", + "sbux_res"; + op,vbus-ctrl-gpio = <&pm8150l_gpios 9 GPIO_ACTIVE_LOW>; +}; + +&pm8150b_fg { + qcom,fg-force-load-profile; + oem,use_external_fg; + qcom,fg-rsense-sel = <0>; + qcom,fg-sys-term-current = <180>; + qcom,fg-chg-term-current = <165>; +}; + +&tlmm { + pm8150b_charger { + ship_mode_default: ship_mode_default { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <8>; + bias-pull-down; + }; + }; + }; + + oneplus_fastchg { + usb_sw_active: usb_sw_active { + mux { + pins = "gpio94", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio94", "gpio59"; + drive-strength = <16>; + bias-pull-down; + }; + }; + + usb_sw_suspend: usb_sw_suspend { + mux { + pins = "gpio94", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio94", "gpio59"; + drive-strength = <2>; + bias-disable; + }; + }; + + fastchg_active: fastchg_active { + mux { + pins = "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio10"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + fastchg_suspend: fastchg_suspend { + mux { + pins = "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-disable; + }; + }; + + ap_clk_active: ap_clk_active { + mux { + pins = "gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio92"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + ap_clk_suspend: ap_clk_suspend { + mux { + pins = "gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio92"; + drive-strength = <2>; + bias-disable; + }; + }; + + ap_data_active: ap_data_active { + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + ap_data_suspend: ap_data_suspend { + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + drive-strength = <2>; + bias-disable; + }; + }; + }; +}; +/* @bsp, 2018/07/20 Battery & Charging porting END */ +/* @bsp,step motor START*/ +&pm8150b_gpios { + motor_mode0_gpio: motor_mode0_gpio { + pins = "gpio5"; /* GPIO 5 */ + function = "normal"; /* normal */ + output-high; + bias-disable; /* No Pull */ + }; + motor_mode0_hi_impedance: motor_mode0_hi_impedance { + pins = "gpio5"; /* GPIO 5 */ + function = "normal"; /* normal */ + bias-high-impedance; + }; + motor_boost_en: motor_boost_en { + pins = "gpio12"; /* GPIO 12 */ + function = "normal"; /* normal */ + output-low; + bias-disable; /* No Pull */ + }; + ab_id2 { + ab_id2_default: ab_id2_default { + pins = "gpio2"; + function = "normal"; + input-enable; + bias-disable; + power-source = <0>; + }; + }; +}; + +&pm8150l_gpios { + motor_pwm_config: motor_pwm_config { + pins = "gpio10"; + function = "func1"; + bias-disable; + power-source = <0>; + output-low; + qcom,drive-strength = <3>; + drive-push-pull; + }; + motor_mode1_gpio: motor_mode1_gpio { + pins = "gpio8"; + function = "normal"; + power-source = <0>; /* 3.6V */ + bias-disable; /* No Pull */ + output-low; /* digital output, no invert */ + qcom,drive-strength = <3>; /* LOW strength */ + }; + motor_dir_gpio: motor_dir_gpio { + pins = "gpio11"; + function = "normal"; + bias-disable; /* No Pull */ + power-source = <0>; /* VIN0 3.6V*/ + output-low; /* digital output, no invert */ + qcom,drive-strength = <3>; /* LOW strength */ + }; +}; + +&pm8150_gpios { + motor_sleep_gpio: motor_sleep_gpio { + pins = "gpio10"; + function = "normal"; + power-source = <0>; + bias-disable; + output-low; + }; + fp_id1_init: fp_id1_init { + pins = "gpio3"; + function = "normal"; + power-source = <0>; + bias-disable; + input-enable; + }; +}; + +&vendor { + step_motor { + compatible = "oneplus,step-motor"; + status = "okay"; + + pwms = <&pm8150l_pwm 1 20000000>; + op,boost-en-pin = <&pm8150b_gpios 12 GPIO_ACTIVE_LOW>; + op,mode0-pin = <&pm8150b_gpios 5 GPIO_ACTIVE_LOW>; + op,mode1-pin = <&pm8150l_gpios 8 GPIO_ACTIVE_LOW>; + op,nsleep-pin = <&pm8150_gpios 10 GPIO_ACTIVE_LOW>; + op,dir-pin = <&pm8150l_gpios 11 GPIO_ACTIVE_LOW>; + op,step-pin = <&pm8150l_gpios 10 GPIO_ACTIVE_LOW>; + pinctrl-names = "boost", + "m0_gpio", + "m0_high_impedance", + "m1_gpio", + "sleep_gpio", + "dir_gpio", + "pwm_config"; + pinctrl-0 = <&motor_boost_en>; + pinctrl-1 = <&motor_mode0_gpio>; + pinctrl-2 = <&motor_mode0_hi_impedance>; + pinctrl-3 = <&motor_mode1_gpio>; + pinctrl-4 = <&motor_sleep_gpio>; + pinctrl-5 = <&motor_dir_gpio>; + pinctrl-6 = <&motor_pwm_config>; + }; +}; + +&usb1 { + status = "disabled"; +}; + +/* @bsp,step motor END*/ + +&extcon_usb1 { + status = "disabled"; +}; + +&usb1 { + extcon = <&extcon_usb1>; + status = "disabled"; +}; + +&spmi_bus { + qcom,pm8009@10 { + compatible = "qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm8009_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0x400>; + interrupts = <0xa 0xc0 0 IRQ_TYPE_NONE>, + <0xa 0xc1 0 IRQ_TYPE_NONE>, + <0xa 0xc2 0 IRQ_TYPE_NONE>, + <0xa 0xc3 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8009_gpio1", "pm8009_gpio2", + "pm8009_gpio3", "pm8009_gpio4"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + /*power key + vol down long press hard reset*/ + qcom,pm8150@0 { + qcom,power-on@800 { + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>, + <0x0 0x8 0x5 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr", "resin", "kpdpwr-resin-bark"; + qcom,s3-src = "kpdpwr-and-resin"; + qcom,pon_1 { + qcom,support-reset = <0>; + qcom,s1-timer = <6720>; + qcom,s2-timer = <2000>; + qcom,s2-type = ; + qcom,pull-up; + }; + + qcom,pon_2 { + qcom,support-reset = <0>; + qcom,s1-timer = <6720>; + qcom,s2-timer = <2000>; + qcom,s2-type = ; + qcom,pull-up; + }; + + qcom,pon_3 { + qcom,pon-type = ; + qcom,support-reset = <0>; + qcom,s1-timer = <6720>; + qcom,s2-timer = <2000>; + qcom,s2-type = ; + qcom,pull-up; + }; + }; + }; +}; +&pm8150_gpios { + key_vol_down { + key_vol_down_default: key_vol_down_default { + pins = "gpio7"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <1>; + }; + }; + ab_id1 { + ab_id1_default: ab_id1_default { + pins = "gpio1"; + function = "normal"; + input-enable; + bias-disable; + power-source = <0>; + }; + }; +}; + +&soc { + gpio_keys { + pinctrl-0 = <&key_vol_up_default &key_vol_down_default>; + vol_down { + label = "volume_down"; + gpios = <&pm8150_gpios 7 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; + + bootloader_log { + compatible = "bootloader_log"; + linux,contiguous-region = <&bootloader_log_mem>; + }; +}; + +&reserved_memory { + + bootloader_log_mem: bootloader_log_mem@0x9FFF7000 { + reg = <0 0x9FFF7000 0 0x00009000>; + label = "bootloader_log_mem"; + }; + + param_mem: param_mem@ac200000 { + reg = <0 0xAC200000 0 0x00100000>; + label = "param_mem"; + }; + + //after cdsp_sec_mem + ramoops: ramoops@0xA9800000 { + compatible = "ramoops"; + reg = <0 0xA9800000 0 0x00400000>; + record-size = <0x40000>; //256x1024 + console-size = <0x40000>; + ftrace-size = <0x40000>; + pmsg-size= <0x200000>; + devinfo-size= <0x01000>; + ecc-size= <0x0>; + }; + + mtp_mem: mtp_mem@ac300000 { + reg = <0 0xAC300000 0 0x00B00000>; + label = "mtp_mem"; + }; +}; + +&pm8009_gpios { + pm8009_gpios_pinctl: pm8009_gpios_pinctl { + + rf_cable_ant1: rf_cable_ant1{ + pins = "gpio3"; + function = "normal"; + power-source = <1>; + bias-pull-up; + qcom,pull-up-strength = <0>; /* 30uA pull up */ + input-enable; /* digital input */ + }; + rf_cable_ant3: rf_cable_ant3 { + pins = "gpio4"; + function = "normal"; + power-source = <1>; + bias-pull-up; + qcom,pull-up-strength = <0>; /* 30uA pull up */ + input-enable; /* digital input */ + }; + }; +}; + +&soc { + oem_aboard_check:oem_aboard_check { + compatible = "oem,aboard"; + interrupt-parent = <&tlmm>; + oem,aboard-gpio-0 = <&pm8150_gpios 1 0>; + oem,aboard-gpio-1 = <&pm8150b_gpios 2 0>; + pinctrl-names = "oem_aboard_active"; + pinctrl-0 = <&ab_id1_default &ab_id2_default>; + }; + oem_serial_pinctrl { + compatible = "oem,oem_serial_pinctrl"; + pinctrl-names = "uart_pinctrl_active","uart_pinctrl_deactive"; + pinctrl-0 = <&qupv3_se12_2uart_active>; + pinctrl-1 = <&qupv3_se12_2uart_oem_sleep>; + }; + + oem_rf_cable:oem_rf_cable { + compatible = "oem,rf_cable"; + interrupt-parent = <&tlmm>; + rf,cable-gpio-0 = <&tlmm 36 0>; + rf,cable-gpio-1 = <&pm8009_gpios 4 0>; + rf,cable-support-timer = <0>; + pinctrl-names = "oem_rf_cable_active"; + pinctrl-0 = <&rf_cable_ant0_active &rf_cable_ant1 &rf_cable_ant3 >; + }; +}; + +&tlmm { + rf_cable_ant0_active: rf_cable_ant0_active { + mux { + pins = "gpio36"; + function = "gpio"; + }; + config { + pins = "gpio36"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se12_2uart_oem_sleep: qupv3_se12_2uart_oem_sleep { + mux { + pins = "gpio85", "gpio86"; + function = "gpio"; + }; + config { + pins = "gpio85", "gpio86"; + drive-strength = <2>; + bias-pull-down; + }; + }; +}; + +&qupv3_se12_2uart { + compatible = "qcom,msm-geni-console-oem"; +}; + +/*disable smb3190 config */ +&smb1390 { + status = "disabled"; +}; +&smb1390_charger { + status = "disabled"; +}; +&smb1355 { + status = "disabled"; +}; +&smb1355_charger { + status = "disabled"; +}; + +/* neil.sun@Connectivity, 2019/05/16, disable SMMU S1 for WLAN and ipa */ +&ipa_smmu_wlan { + qcom,smmu-s1-bypass; +}; + +&icnss { + qcom,smmu-s1-bypass; +}; + +/* eleven.xie@Connectivity, 2019/05/20, disable wil6210 dts config */ +&wil6210 { + status = "disabled"; +}; + diff --git a/arch/arm/boot/dts/qcom/sm8150-pcie.dtsi b/arch/arm/boot/dts/qcom/sm8150-pcie.dtsi new file mode 100644 index 000000000000..d37a1aaab096 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-pcie.dtsi @@ -0,0 +1,824 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + pcie0: qcom,pcie@1c00000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x1c00000 0x4000>, + <0x1c04000 0x1000>, + <0x60000000 0xf1d>, + <0x60000f20 0xa8>, + <0x60001000 0x1000>, + <0x60100000 0x100000>, + <0x60200000 0x100000>, + <0x60300000 0x3d00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>; + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = < 0 0 0 0 &intc 0 140 0 + 0 0 0 1 &intc 0 149 0 + 0 0 0 2 &intc 0 150 0 + 0 0 0 3 &intc 0 151 0 + 0 0 0 4 &intc 0 152 0>; + + qcom,phy-sequence = <0x0840 0x03 0x0 + 0x0094 0x08 0x0 + 0x0154 0x34 0x0 + 0x016c 0x08 0x0 + 0x0058 0x0f 0x0 + 0x00a4 0x42 0x0 + 0x0110 0x24 0x0 + 0x011c 0x03 0x0 + 0x0118 0xb4 0x0 + 0x010c 0x02 0x0 + 0x01bc 0x11 0x0 + 0x00bc 0x82 0x0 + 0x00d4 0x03 0x0 + 0x00d0 0x55 0x0 + 0x00cc 0x55 0x0 + 0x00b0 0x1a 0x0 + 0x00ac 0x0a 0x0 + 0x00c4 0x68 0x0 + 0x00e0 0x02 0x0 + 0x00dc 0xaa 0x0 + 0x00d8 0xab 0x0 + 0x00b8 0x34 0x0 + 0x00b4 0x14 0x0 + 0x0158 0x01 0x0 + 0x0074 0x06 0x0 + 0x007c 0x16 0x0 + 0x0084 0x36 0x0 + 0x0078 0x06 0x0 + 0x0080 0x16 0x0 + 0x0088 0x36 0x0 + 0x01b0 0x1e 0x0 + 0x01ac 0xb9 0x0 + 0x01b8 0x18 0x0 + 0x01b4 0x94 0x0 + 0x0050 0x07 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x029c 0x12 0x0 + 0x0284 0x05 0x0 + 0x0c38 0x03 0x0 + 0x0518 0x1c 0x0 + 0x0524 0x14 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x05b4 0x04 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0510 0x17 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x39 0x0 + 0x05a8 0x31 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x39 0x0 + 0x0594 0x37 0x0 + 0x0570 0x7f 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0xdb 0x0 + 0x0580 0x75 0x0 + 0x04fc 0x00 0x0 + 0x04f8 0xc0 0x0 + 0x0414 0x04 0x0 + 0x09a4 0x01 0x0 + 0x0c90 0x00 0x0 + 0x0c40 0x01 0x0 + 0x0c48 0x01 0x0 + 0x0c50 0x00 0x0 + 0x0048 0x90 0x0 + 0x0c1c 0xc1 0x0 + 0x0988 0x66 0x0 + 0x0998 0x08 0x0 + 0x08dc 0x0d 0x0 + 0x09ec 0x01 0x0 + 0x04b4 0x02 0x0 + 0x04b8 0x02 0x0 + 0x04bc 0xaa 0x0 + 0x04c0 0x00 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x0460 0xa0 0x0 + 0x05c4 0x0c 0x0 + 0x0464 0x00 0x0 + 0x05c0 0x10 0x0 + 0x04dc 0x05 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x0800 0x00 0x0 + 0x0844 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + + perst-gpio = <&tlmm 35 0>; + wake-gpio = <&tlmm 37 0>; + + gdsc-vdd-supply = <&pcie_0_gdsc>; + vreg-1.8-supply = <&pm8150l_l3>; + vreg-0.9-supply = <&pm8150_l5>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0.9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + msi-parent = <&pcie0_msi>; + + qcom,no-l0s-supported; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x4000000>; + + qcom,phy-status-offset = <0x814>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0x840>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <0>; + + qcom,pcie-phy-ver = <0x40>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x1d80>; + + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>, + <0x200 &apps_smmu 0x1d82 0x1>, + <0x300 &apps_smmu 0x1d83 0x1>, + <0x400 &apps_smmu 0x1d84 0x1>, + <0x500 &apps_smmu 0x1d85 0x1>, + <0x600 &apps_smmu 0x1d86 0x1>, + <0x700 &apps_smmu 0x1d87 0x1>, + <0x800 &apps_smmu 0x1d88 0x1>, + <0x900 &apps_smmu 0x1d89 0x1>, + <0xa00 &apps_smmu 0x1d8a 0x1>, + <0xb00 &apps_smmu 0x1d8b 0x1>, + <0xc00 &apps_smmu 0x1d8c 0x1>, + <0xd00 &apps_smmu 0x1d8d 0x1>, + <0xe00 &apps_smmu 0x1d8e 0x1>, + <0xf00 &apps_smmu 0x1d8f 0x1>; + + qcom,msm-bus,name = "pcie0"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 500 800>; + + clocks = <&clock_gcc GCC_PCIE_0_PIPE_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_PCIE_0_AUX_CLK>, + <&clock_gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&clock_gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&clock_gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&clock_gcc GCC_PCIE_0_CLKREF_CLK>, + <&clock_gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&clock_gcc GCC_PCIE0_PHY_REFGEN_CLK>, + <&clock_gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&clock_gcc GCC_PCIE_0_BCR>, + <&clock_gcc GCC_PCIE_0_PHY_BCR>; + + reset-names = "pcie_0_core_reset", + "pcie_0_phy_reset"; + + pcie_rc0: pcie_rc0 { + #address-cells = <5>; + #size-cells = <0>; + reg = <0 0 0 0 0>; + pci-ids = "17cb:0108"; + }; + }; + + pcie0_msi: qcom,pcie0_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupt-parent = <&pdc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pcie1: qcom,pcie@1c08000 { + compatible = "qcom,pci-msm"; + cell-index = <1>; + + reg = <0x1c08000 0x4000>, + <0x1c0c000 0x2000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>, + <0x40200000 0x100000>, + <0x40300000 0x1fd00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "iatu", "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>; + interrupt-parent = <&pcie1>; + interrupts = <0 1 2 3 4>; + interrupt-names = "int_global_int", "int_a", "int_b", "int_c", + "int_d"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc 0 306 0 + 0 0 0 1 &intc 0 434 0 + 0 0 0 2 &intc 0 435 0 + 0 0 0 3 &intc 0 438 0 + 0 0 0 4 &intc 0 439 0>; + + qcom,phy-sequence = <0x0a40 0x03 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0048 0x90 0x0 + 0x0050 0x07 0x0 + 0x0058 0x0f 0x0 + 0x0074 0x06 0x0 + 0x0078 0x06 0x0 + 0x007c 0x16 0x0 + 0x0080 0x16 0x0 + 0x0084 0x36 0x0 + 0x0088 0x36 0x0 + 0x0094 0x08 0x0 + 0x00a4 0x42 0x0 + 0x00ac 0x0a 0x0 + 0x00b0 0x1a 0x0 + 0x00b4 0x14 0x0 + 0x00b8 0x34 0x0 + 0x00bc 0x82 0x0 + 0x00c4 0x68 0x0 + 0x00cc 0x55 0x0 + 0x00d0 0x55 0x0 + 0x00d4 0x03 0x0 + 0x00d8 0xab 0x0 + 0x00dc 0xaa 0x0 + 0x00e0 0x02 0x0 + 0x010c 0x02 0x0 + 0x0110 0x24 0x0 + 0x0118 0xb4 0x0 + 0x011c 0x03 0x0 + 0x0154 0x32 0x0 + 0x0158 0x01 0x0 + 0x016c 0x08 0x0 + 0x01ac 0xb9 0x0 + 0x01b0 0x1e 0x0 + 0x01b4 0x94 0x0 + 0x01b8 0x18 0x0 + 0x01bc 0x01 0x0 + 0x0284 0x05 0x0 + 0x029c 0x12 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x04d8 0x01 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x04f8 0xc0 0x0 + 0x04fc 0x00 0x0 + 0x0510 0x17 0x0 + 0x0518 0x1c 0x0 + 0x051c 0x03 0x0 + 0x0524 0x14 0x0 + 0x0570 0x7f 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0xdb 0x0 + 0x0580 0x75 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x39 0x0 + 0x0594 0x36 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x39 0x0 + 0x05a8 0x31 0x0 + 0x05b4 0x04 0x0 + 0x04b4 0x02 0x0 + 0x04b8 0x02 0x0 + 0x04bc 0xaa 0x0 + 0x04c0 0x00 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x0460 0xa0 0x0 + 0x05c4 0x0c 0x0 + 0x0464 0x00 0x0 + 0x05c0 0x10 0x0 + 0x04dc 0x05 0x0 + 0x0684 0x05 0x0 + 0x069c 0x12 0x0 + 0x0808 0x0c 0x0 + 0x0814 0x03 0x0 + 0x0834 0x7f 0x0 + 0x0844 0x70 0x0 + 0x08d8 0x01 0x0 + 0x08e8 0x00 0x0 + 0x08ec 0x0e 0x0 + 0x08f0 0x4a 0x0 + 0x08f4 0x0f 0x0 + 0x08f8 0xc0 0x0 + 0x08fc 0x00 0x0 + 0x0910 0x17 0x0 + 0x0918 0x1c 0x0 + 0x091c 0x03 0x0 + 0x0924 0x14 0x0 + 0x0970 0x7f 0x0 + 0x0974 0xff 0x0 + 0x0978 0xff 0x0 + 0x097c 0xdb 0x0 + 0x0980 0x75 0x0 + 0x0984 0x24 0x0 + 0x0988 0xe4 0x0 + 0x098c 0xec 0x0 + 0x0990 0x3a 0x0 + 0x0994 0x36 0x0 + 0x0998 0xd4 0x0 + 0x099c 0x54 0x0 + 0x09a0 0xdb 0x0 + 0x09a4 0x39 0x0 + 0x09a8 0x31 0x0 + 0x09b4 0x04 0x0 + 0x08b4 0x02 0x0 + 0x08b8 0x02 0x0 + 0x08bc 0xaa 0x0 + 0x08c0 0x00 0x0 + 0x08d4 0x54 0x0 + 0x08d8 0x07 0x0 + 0x0860 0xa0 0x0 + 0x09c4 0x0c 0x0 + 0x0864 0x00 0x0 + 0x09c0 0x10 0x0 + 0x08dc 0x05 0x0 + 0x0a98 0x01 0x0 + 0x0abc 0x56 0x0 + 0x0adc 0x0d 0x0 + 0x0b88 0x66 0x0 + 0x0ba4 0x01 0x0 + 0x0b98 0x08 0x0 + 0x0e14 0x07 0x0 + 0x0e1c 0xc1 0x0 + 0x0e40 0x01 0x0 + 0x0e48 0x01 0x0 + 0x0e78 0x50 0x0 + 0x0e90 0x00 0x0 + 0x0ea0 0x11 0x0 + 0x0e38 0x03 0x0 + 0x0e50 0x00 0x0 + 0x0e20 0x01 0x0 + 0x0a00 0x00 0x0 + 0x0a44 0x03 0x0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_clkreq_default + &pcie1_perst_default + &pcie1_wake_default>; + + perst-gpio = <&tlmm 102 0>; + wake-gpio = <&tlmm 104 0>; + + gdsc-vdd-supply = <&pcie_1_gdsc>; + vreg-1.8-supply = <&pm8150l_l3>; + vreg-0.9-supply = <&pm8150_l5>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0.9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + msi-parent = <&pcie1_msi>; + + qcom,no-l0s-supported; + + qcom,ep-latency = <10>; + + qcom,slv-addr-space-size = <0x20000000>; + + qcom,phy-status-offset = <0xa14>; + qcom,phy-status-bit = <6>; + qcom,phy-power-down-offset = <0xa40>; + + qcom,boot-option = <0x1>; + + linux,pci-domain = <1>; + + qcom,pcie-phy-ver = <0x40>; + qcom,use-19p2mhz-aux-clk; + + qcom,smmu-sid-base = <0x1e00>; + + iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, + <0x100 &apps_smmu 0x1e01 0x1>, + <0x200 &apps_smmu 0x1e02 0x1>, + <0x300 &apps_smmu 0x1e03 0x1>, + <0x400 &apps_smmu 0x1e04 0x1>, + <0x500 &apps_smmu 0x1e05 0x1>, + <0x600 &apps_smmu 0x1e06 0x1>, + <0x700 &apps_smmu 0x1e07 0x1>, + <0x800 &apps_smmu 0x1e08 0x1>, + <0x900 &apps_smmu 0x1e09 0x1>, + <0xa00 &apps_smmu 0x1e0a 0x1>, + <0xb00 &apps_smmu 0x1e0b 0x1>, + <0xc00 &apps_smmu 0x1e0c 0x1>, + <0xd00 &apps_smmu 0x1e0d 0x1>, + <0xe00 &apps_smmu 0x1e0e 0x1>, + <0xf00 &apps_smmu 0x1e0f 0x1>; + + qcom,msm-bus,name = "pcie1"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <100 512 0 0>, + <100 512 500 800>; + + clocks = <&clock_gcc GCC_PCIE_1_PIPE_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_PCIE_1_AUX_CLK>, + <&clock_gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&clock_gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&clock_gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&clock_gcc GCC_PCIE_1_CLKREF_CLK>, + <&clock_gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&clock_gcc GCC_PCIE1_PHY_REFGEN_CLK>, + <&clock_gcc GCC_PCIE_PHY_AUX_CLK>; + + clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src", + "pcie_1_aux_clk", "pcie_1_cfg_ahb_clk", + "pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk", + "pcie_1_ldo", "pcie_1_slv_q2a_axi_clk", + "pcie_tbu_clk", "pcie_phy_refgen_clk", + "pcie_phy_aux_clk"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <100000000>, <0>; + + resets = <&clock_gcc GCC_PCIE_1_BCR>, + <&clock_gcc GCC_PCIE_1_PHY_BCR>; + + reset-names = "pcie_1_core_reset", + "pcie_1_phy_reset"; + + pcie_rc1: pcie_rc1 { + #address-cells = <5>; + #size-cells = <0>; + reg = <0 0 0 0 0>; + pci-ids = "17cb:0108"; + }; + }; + + pcie1_msi: qcom,pcie1_msi@17a00040 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0x17a00040 0x0>; + interrupt-parent = <&pdc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pcie1_edma: qcom,pcie1_edma@40002000 { + compatible = "qcom,pci-edma"; + #dma-cells = <2>; + reg = <0x40002000 0x2000>; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-names = "pci-edma-int"; + }; + + pcie_ep: qcom,pcie@40004000 { + compatible = "qcom,pcie-ep"; + + reg = <0x40004000 0x1000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40002000 0x2000>, + <0x01c08000 0x4000>, + <0x01c0c000 0x2000>, + <0x01c0e000 0x1000>; + reg-names = "msi", "dm_core", "elbi", "iatu", "edma", "parf", + "phy", "mmio"; + + #address-cells = <0>; + interrupt-parent = <&pcie_ep>; + interrupts = <0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 306 0>; + interrupt-names = "int_global"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default + &pcie_ep_wake_default>; + + clkreq-gpio = <&tlmm 103 0>; + perst-gpio = <&tlmm 102 0>; + wake-gpio = <&tlmm 104 0>; + + gdsc-vdd-supply = <&pcie_1_gdsc>; + vreg-1.8-supply = <&pm8150l_l3>; + vreg-0.9-supply = <&pm8150_l5>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + + qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0.9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + clocks = <&clock_gcc GCC_PCIE_1_PIPE_CLK>, + <&clock_gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&clock_gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&clock_gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&clock_gcc GCC_PCIE_1_AUX_CLK>, + <&clock_gcc GCC_PCIE_1_CLKREF_CLK>, + <&clock_gcc GCC_PCIE_PHY_AUX_CLK>, + <&clock_gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + + clock-names = "pcie_pipe_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_aux_clk", "pcie_ldo", "pcie_sleep_clk", + "pcie_slv_q2a_axi_clk"; + + resets = <&clock_gcc GCC_PCIE_1_BCR>, + <&clock_gcc GCC_PCIE_1_PHY_BCR>; + + reset-names = "pcie_core_reset", + "pcie_phy_reset"; + + qcom,msm-bus,name = "pcie-ep"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <100 512 0 0>, + <100 512 500 800>; + + qcom,pcie-link-speed = <3>; + qcom,pcie-phy-ver = <6>; + qcom,pcie-aggregated-irq; + qcom,pcie-mhi-a7-irq; + qcom,phy-status-reg = <0xa14>; + qcom,tcsr-not-supported; + + qcom,phy-init = <0x0a40 0x01 0x0 0x1 + 0x0094 0x00 0x0 0x1 + 0x000c 0x02 0x0 0x1 + 0x004c 0x07 0x0 0x1 + 0x0050 0x07 0x0 0x1 + 0x0058 0x0f 0x0 0x1 + 0x0074 0x36 0x0 0x1 + 0x0078 0x36 0x0 0x1 + 0x007c 0x12 0x0 0x1 + 0x0080 0x12 0x0 0x1 + 0x0084 0x00 0x0 0x1 + 0x0088 0x00 0x0 0x1 + 0x00a4 0x42 0x0 0x1 + 0x00ac 0xff 0x0 0x1 + 0x00b0 0x04 0x0 0x1 + 0x00b4 0xff 0x0 0x1 + 0x00b8 0x09 0x0 0x1 + 0x00bc 0x19 0x0 0x1 + 0x00c4 0x14 0x0 0x1 + 0x00ec 0xfb 0x0 0x1 + 0x00f0 0x01 0x0 0x1 + 0x00f4 0xfb 0x0 0x1 + 0x00f8 0x01 0x0 0x1 + 0x010c 0x02 0x0 0x1 + 0x0110 0x24 0x0 0x1 + 0x0118 0xb4 0x0 0x1 + 0x011c 0x03 0x0 0x1 + 0x0158 0x01 0x0 0x1 + 0x016c 0x08 0x0 0x1 + 0x01ac 0x56 0x0 0x1 + 0x01b0 0x1d 0x0 0x1 + 0x01b4 0x78 0x0 0x1 + 0x01b8 0x17 0x0 0x1 + 0x0154 0x31 0x0 0x1 + 0x01bc 0x11 0x0 0x1 + 0x0284 0x05 0x0 0x1 + 0x029c 0x12 0x0 0x1 + 0x0414 0x04 0x0 0x1 + 0x0434 0x7f 0x0 0x1 + 0x0444 0x70 0x0 0x1 + 0x04d8 0x01 0x0 0x1 + 0x04ec 0x0e 0x0 0x1 + 0x04f0 0x4a 0x0 0x1 + 0x04f4 0x0f 0x0 0x1 + 0x04f8 0xc0 0x0 0x1 + 0x04fc 0x00 0x0 0x1 + 0x0510 0x17 0x0 0x1 + 0x0518 0x1c 0x0 0x1 + 0x051c 0x03 0x0 0x1 + 0x0524 0x14 0x0 0x1 + 0x05b4 0x04 0x0 0x1 + 0x0570 0xbd 0x0 0x1 + 0x0574 0xbd 0x0 0x1 + 0x0578 0x7f 0x0 0x1 + 0x057c 0xdb 0x0 0x1 + 0x0580 0x76 0x0 0x1 + 0x0584 0x24 0x0 0x1 + 0x0588 0xe4 0x0 0x1 + 0x058c 0xec 0x0 0x1 + 0x0590 0x39 0x0 0x1 + 0x0594 0x37 0x0 0x1 + 0x0598 0xd4 0x0 0x1 + 0x059c 0x54 0x0 0x1 + 0x05a0 0xdb 0x0 0x1 + 0x05a4 0x39 0x0 0x1 + 0x05a8 0x31 0x0 0x1 + 0x0684 0x05 0x0 0x1 + 0x069c 0x12 0x0 0x1 + 0x0814 0x04 0x0 0x1 + 0x0834 0x7f 0x0 0x1 + 0x0844 0x70 0x0 0x1 + 0x08d8 0x01 0x0 0x1 + 0x08ec 0x0e 0x0 0x1 + 0x08f0 0x4a 0x0 0x1 + 0x08f4 0x0f 0x0 0x1 + 0x08f8 0xc0 0x0 0x1 + 0x08fc 0x00 0x0 0x1 + 0x0910 0x17 0x0 0x1 + 0x0918 0x1c 0x0 0x1 + 0x091c 0x03 0x0 0x1 + 0x0924 0x14 0x0 0x1 + 0x09b4 0x04 0x0 0x1 + 0x0970 0xbd 0x0 0x1 + 0x0974 0xbd 0x0 0x1 + 0x0978 0x7f 0x0 0x1 + 0x097c 0xdb 0x0 0x1 + 0x0980 0x76 0x0 0x1 + 0x0984 0x24 0x0 0x1 + 0x0988 0xe4 0x0 0x1 + 0x098c 0xec 0x0 0x1 + 0x0990 0x39 0x0 0x1 + 0x0994 0x37 0x0 0x1 + 0x0998 0xd4 0x0 0x1 + 0x099c 0x54 0x0 0x1 + 0x09a0 0xdb 0x0 0x1 + 0x09a4 0x39 0x0 0x1 + 0x09a8 0x31 0x0 0x1 + 0x0a98 0x01 0x0 0x1 + 0x0abc 0x56 0x0 0x1 + 0x0adc 0x0d 0x0 0x1 + 0x0b88 0xaa 0x0 0x1 + 0x0ba4 0x01 0x0 0x1 + 0x0e0c 0x04 0x0 0x1 + 0x0e14 0x07 0x0 0x1 + 0x0e40 0x01 0x0 0x1 + 0x0e48 0x01 0x0 0x1 + 0x0e78 0x50 0x0 0x1 + 0x0ea0 0x11 0x0 0x1 + 0x0ebc 0x00 0x0 0x1 + 0x0ee0 0x58 0x0 0x1 + 0x0a00 0x00 0x0 0x1 + 0x0a44 0x03 0x0 0x1>; + + edma-parent = <&pcie1_edma>; + iommus = <&apps_smmu 0x1e00 0x0>; + qcom,pcie-edma; + status = "disabled"; + }; + + mhi_device: mhi_dev@1c0b000 { + compatible = "qcom,msm-mhi-dev"; + reg = <0x1c0b000 0x1000>; + reg-names = "mhi_mmio_base"; + qcom,mhi-ep-msi = <0>; + qcom,mhi-version = <0x1000000>; + qcom,use-pcie-edma; + dmas = <&pcie1_edma 0 0>, <&pcie1_edma 1 0>; + dma-names = "tx", "rx"; + interrupts = <0 440 0>; + interrupt-names = "mhi-device-inta"; + qcom,mhi-ifc-id = <0x010817cb>; + qcom,mhi-interrupt; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-pinctrl.dtsi b/arch/arm/boot/dts/qcom/sm8150-pinctrl.dtsi new file mode 100644 index 000000000000..416bba8e3bd8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-pinctrl.dtsi @@ -0,0 +1,4577 @@ +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tlmm: pinctrl@03000000 { + compatible = "qcom,sm8150-pinctrl"; + reg = <0x03000000 0xdc2000>, <0x17c000f0 0x60>; + reg-names = "pinctrl", "spi_cfg"; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + ufs_dev_reset_assert: ufs_dev_reset_assert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * UFS_RESET driver strengths are having + * different values/steps compared to typical + * GPIO drive strengths. + * + * Following table clarifies: + * + * HDRV value | UFS_RESET | Typical GPIO + * (dec) | (mA) | (mA) + * 0 | 0.8 | 2 + * 1 | 1.55 | 4 + * 2 | 2.35 | 6 + * 3 | 3.1 | 8 + * 4 | 3.9 | 10 + * 5 | 4.65 | 12 + * 6 | 5.4 | 14 + * 7 | 6.15 | 16 + * + * POR value for UFS_RESET HDRV is 3 which means + * 3.1mA and we want to use that. Hence just + * specify 8mA to "drive-strength" binding and + * that should result into writing 3 to HDRV + * field. + */ + drive-strength = <8>; /* default: 3.1 mA */ + output-low; /* active low reset */ + }; + }; + + ufs_dev_reset_deassert: ufs_dev_reset_deassert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * default: 3.1 mA + * check comments under ufs_dev_reset_assert + */ + drive-strength = <8>; + output-high; /* active low reset */ + }; + }; + + storage_cd: storage_cd { + mux { + /*pins = "gpio96"; + function = "gpio";*/ + }; + + config { + /*pins = "gpio96";*/ + /*bias-pull-up;*/ /* pull up */ + /*drive-strength = <2>;*/ /* 2 MA */ + }; + }; + + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_clk_ds_400KHz: sdc2_clk_ds_400KHz { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_ds_50MHz: sdc2_clk_ds_50MHz { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_ds_100MHz: sdc2_clk_ds_100MHz { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_ds_200MHz: sdc2_clk_ds_200MHz { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cmd_ds_400KHz: sdc2_cmd_ds_400KHz { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_cmd_ds_50MHz: sdc2_cmd_ds_50MHz { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_cmd_ds_100MHz: sdc2_cmd_ds_100MHz { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_cmd_ds_200MHz: sdc2_cmd_ds_200MHz { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_data_ds_400KHz: sdc2_data_ds_400KHz { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_data_ds_50MHz: sdc2_data_ds_50MHz { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_data_ds_100MHz: sdc2_data_ds_100MHz { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_data_ds_200MHz: sdc2_data_ds_200MHz { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + qupv3_se12_2uart_pins: qupv3_se12_2uart_pins { + qupv3_se12_2uart_active: qupv3_se12_2uart_active { + mux { + pins = "gpio85", "gpio86"; + function = "qup12"; + }; + + config { + pins = "gpio85", "gpio86"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se12_2uart_sleep: qupv3_se12_2uart_sleep { + mux { + pins = "gpio85", "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio85", "gpio86"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se13_4uart_pins: qupv3_se13_4uart_pins { + qupv3_se13_default_ctsrtsrx: + qupv3_se13_default_ctsrtsrx { + mux { + pins = "gpio43", "gpio44", "gpio46"; + function = "gpio"; + }; + + config { + pins = "gpio43", "gpio44", "gpio46"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se13_default_tx: qupv3_se13_default_tx { + mux { + pins = "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio45"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se13_ctsrx: qupv3_se13_ctsrx { + mux { + pins = "gpio43", "gpio46"; + function = "qup13"; + }; + + config { + pins = "gpio43", "gpio46"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se13_rts: qupv3_se13_rts { + mux { + pins = "gpio44"; + function = "qup13"; + }; + + config { + pins = "gpio44"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se13_tx: qupv3_se13_tx { + mux { + pins = "gpio45"; + function = "qup13"; + }; + + config { + pins = "gpio45"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pmx_ts_active { + ts_active: ts_active { + mux { + pins = "gpio122", "gpio54"; + function = "gpio"; + }; + config { + pins = "gpio122", "gpio54"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio122"; + function = "gpio"; + }; + config { + pins = "gpio122"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio54"; + function = "gpio"; + }; + config { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pcie0 { + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio36"; + function = "pci_e0"; + }; + + config { + pins = "gpio36"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie1 { + pcie1_clkreq_default: pcie1_clkreq_default { + mux { + pins = "gpio103"; + function = "pci_e1"; + }; + + config { + pins = "gpio103"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_perst_default: pcie1_perst_default { + mux { + pins = "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio102"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie1_wake_default: pcie1_wake_default { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio169"; + function = "gpio"; + }; + + config { + pins = "gpio169"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio169"; + function = "gpio"; + }; + + config { + pins = "gpio169"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + }; + + pcie_ep { + pcie_ep_clkreq_default: pcie_ep_clkreq_default { + mux { + pins = "gpio103"; + function = "pci_e1"; + }; + config { + pins = "gpio103"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio102"; + function = "gpio"; + }; + config { + pins = "gpio102"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio104"; + function = "gpio"; + }; + config { + pins = "gpio104"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + wil6210_refclk3_en_pin: wil6210_refclk3_en_pin { + mux { + /*pins = "gpio87"; + function = "gpio";*/ + }; + + config { + /*pins = "gpio87";*/ + /*bias-pull-down;*/ /* PULL DOWN */ + /*drive-strength = <2>;*/ /* 2 MA */ + }; + }; + + /* SE0 pin mappings */ + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_active: qupv3_se0_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "qup0"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_active: qupv3_se0_spi_active { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "qup0"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 1 pin mappings */ + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_active: qupv3_se1_i2c_active { + mux { + pins = "gpio114", "gpio115"; + function = "qup1"; + }; + + config { + pins = "gpio114", "gpio115"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio114", "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio114", "gpio115"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_active: qupv3_se1_spi_active { + mux { + pins = "gpio114", "gpio115", "gpio116", + "gpio117"; + function = "qup1"; + }; + + config { + pins = "gpio114", "gpio115", "gpio116", + "gpio117"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio114", "gpio115", "gpio116", + "gpio117"; + function = "gpio"; + }; + + config { + pins = "gpio114", "gpio115", "gpio116", + "gpio117"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 2 pin mappings */ + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio126", "gpio127"; + function = "qup2"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio126", "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_active: qupv3_se2_spi_active { + mux { + pins = "gpio126", "gpio127", "gpio128", + "gpio129"; + function = "qup2"; + }; + + config { + pins = "gpio126", "gpio127", "gpio128", + "gpio129"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio126", "gpio127", "gpio128", + "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio126", "gpio127", "gpio128", + "gpio129"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 3 pin mappings */ + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_active: qupv3_se3_i2c_active { + mux { + pins = "gpio144", "gpio145"; + function = "qup3"; + }; + + config { + pins = "gpio144", "gpio145"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio144", "gpio145"; + function = "gpio"; + }; + + config { + pins = "gpio144", "gpio145"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se3_spi_pins: qupv3_se3_spi_pins { + qupv3_se3_spi_active: qupv3_se3_spi_active { + mux { + pins = "gpio144", "gpio145", "gpio146", + "gpio147"; + function = "qup3"; + }; + + config { + pins = "gpio144", "gpio145", "gpio146", + "gpio147"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { + mux { + pins = "gpio145", "gpio146", "gpio147"; + function = "qup3"; + }; + + config { + pins = "gpio145", "gpio146", "gpio147"; + drive-strength = <6>; + bias-disable; + }; + }; + qupv3_se3_spi_miso_sleep: qupv3_se3_spi_miso_sleep { + mux { + pins = "gpio144"; + function = "qup3"; + }; + + config { + pins = "gpio144"; + drive-strength = <6>; + bias-pull-down; /* pull down */ + }; + }; + }; + + /* SE 4 pin mappings */ + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_active: qupv3_se4_i2c_active { + mux { + pins = "gpio51", "gpio52"; + function = "qup4"; + }; + + config { + pins = "gpio51", "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio51", "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio51", "gpio52"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se4_spi_pins: qupv3_se4_spi_pins { + qupv3_se4_spi_active: qupv3_se4_spi_active { + mux { + pins = "gpio51", "gpio52", "gpio53", + "gpio54"; + function = "qup4"; + }; + + config { + pins = "gpio51", "gpio52", "gpio53", + "gpio54"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { + mux { + pins = "gpio51", "gpio52", "gpio53", + "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio51", "gpio52", "gpio53", + "gpio54"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 5 pin mappings */ + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_active: qupv3_se5_i2c_active { + mux { + pins = "gpio121", "gpio122"; + function = "qup5"; + }; + + config { + pins = "gpio121", "gpio122"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio121", "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio121", "gpio122"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se5_spi_pins: qupv3_se5_spi_pins { + qupv3_se5_spi_active: qupv3_se5_spi_active { + mux { + pins = "gpio119", "gpio120", "gpio121", + "gpio122"; + function = "qup5"; + }; + + config { + pins = "gpio119", "gpio120", "gpio121", + "gpio122"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { + mux { + pins = "gpio119", "gpio120", "gpio121", + "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio119", "gpio120", "gpio121", + "gpio122"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 6 pin mappings */ + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_active: qupv3_se6_i2c_active { + mux { + pins = "gpio6", "gpio7"; + function = "qup6"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_active: qupv3_se6_spi_active { + mux { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + function = "qup6"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 7 pin mappings */ + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_active: qupv3_se7_i2c_active { + mux { + pins = "gpio98", "gpio99"; + function = "qup7"; + }; + + config { + pins = "gpio98", "gpio99"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio98", "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio98", "gpio99"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se7_spi_pins: qupv3_se7_spi_pins { + qupv3_se7_spi_active: qupv3_se7_spi_active { + mux { + pins = "gpio98", "gpio99", "gpio100", + "gpio101"; + function = "qup7"; + }; + + config { + pins = "gpio98", "gpio99", "gpio100", + "gpio101"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_sleep: qupv3_se7_spi_sleep { + mux { + pins = "gpio98", "gpio99", "gpio100", + "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio98", "gpio99", "gpio100", + "gpio101"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* QUPv3 North instances */ + /* SE 8 pin mappings */ + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_active: qupv3_se8_i2c_active { + mux { + pins = "gpio88", "gpio89"; + function = "qup8"; + }; + + config { + pins = "gpio88", "gpio89"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio88", "gpio89"; + function = "gpio"; + }; + + config { + pins = "gpio88", "gpio89"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se8_spi_pins: qupv3_se8_spi_pins { + qupv3_se8_spi_active: qupv3_se8_spi_active { + mux { + pins = "gpio88", "gpio89", "gpio90", + "gpio91"; + function = "qup8"; + }; + + config { + pins = "gpio88", "gpio89", "gpio90", + "gpio91"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { + mux { + pins = "gpio88", "gpio89", "gpio90", + "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio88", "gpio89", "gpio90", + "gpio91"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 9 pin mappings */ + qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { + qupv3_se9_i2c_active: qupv3_se9_i2c_active { + mux { + pins = "gpio39", "gpio40"; + function = "qup9"; + }; + + config { + pins = "gpio39", "gpio40"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { + mux { + pins = "gpio39", "gpio40"; + function = "gpio"; + }; + + config { + pins = "gpio39", "gpio40"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 47 NFC Read Interrupt */ + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 47 NFC Read Interrupt */ + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_active: nfc_enable_active { + /* active state */ + mux { + /* 41: NFC ENABLE 42:ESE Enable */ + pins = "gpio41", "gpio42", "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio41", "gpio42", "gpio48"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + /* sleep state */ + mux { + /* 41: NFC ENABLE 42:ESE Enable */ + pins = "gpio41", "gpio42", "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio41", "gpio42", "gpio48"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_clk_req_active: nfc_clk_req_active { + /* active state */ + mux { + /* 113: NFC CLOCK REQUEST */ + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_clk_req_suspend: nfc_clk_req_suspend { + /* sleep state */ + mux { + /* 113: NFC CLOCK REQUEST */ + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + + qupv3_se9_spi_pins: qupv3_se9_spi_pins { + qupv3_se9_spi_active: qupv3_se9_spi_active { + mux { + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; + function = "qup9"; + }; + + config { + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { + mux { + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; + function = "gpio"; + }; + + config { + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 10 pin mappings */ + qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { + qupv3_se10_i2c_active: qupv3_se10_i2c_active { + mux { + pins = "gpio9", "gpio10"; + function = "qup10"; + }; + + config { + pins = "gpio9", "gpio10"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { + mux { + pins = "gpio9", "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio9", "gpio10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se10_spi_pins: qupv3_se10_spi_pins { + qupv3_se10_spi_active: qupv3_se10_spi_active { + mux { + pins = "gpio9", "gpio10", "gpio11", + "gpio12"; + function = "qup10"; + }; + + config { + pins = "gpio9", "gpio10", "gpio11", + "gpio12"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { + mux { + pins = "gpio9", "gpio10", "gpio11", + "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio9", "gpio10", "gpio11", + "gpio12"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 11 pin mappings */ + qupv3_se11_i2c_pins: qupv3_se11_i2c_pins { + qupv3_se11_i2c_active: qupv3_se11_i2c_active { + mux { + pins = "gpio94", "gpio95"; + function = "qup11"; + }; + + config { + pins = "gpio94", "gpio95"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep { + mux { + pins = "gpio94", "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio94", "gpio95"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se11_spi_pins: qupv3_se11_spi_pins { + qupv3_se11_spi_active: qupv3_se11_spi_active { + mux { + pins = "gpio92", "gpio93", "gpio94", + "gpio95"; + function = "qup11"; + }; + + config { + pins = "gpio92", "gpio93", "gpio94", + "gpio95"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_sleep: qupv3_se11_spi_sleep { + mux { + pins = "gpio92", "gpio93", "gpio94", + "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio92", "gpio93", "gpio94", + "gpio95"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 12 pin mappings */ + qupv3_se12_i2c_pins: qupv3_se12_i2c_pins { + qupv3_se12_i2c_active: qupv3_se12_i2c_active { + mux { + pins = "gpio83", "gpio84"; + function = "qup12"; + }; + + config { + pins = "gpio83", "gpio84"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep { + mux { + pins = "gpio83", "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio83", "gpio84"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se12_spi_pins: qupv3_se12_spi_pins { + qupv3_se12_spi_active: qupv3_se12_spi_active { + mux { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + function = "qup12"; + }; + + config { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_sleep: qupv3_se12_spi_sleep { + mux { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 13 pin mappings */ + qupv3_se13_i2c_pins: qupv3_se13_i2c_pins { + qupv3_se13_i2c_active: qupv3_se13_i2c_active { + mux { + pins = "gpio43", "gpio44"; + function = "qup13"; + }; + + config { + pins = "gpio43", "gpio44"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep { + mux { + pins = "gpio43", "gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio43", "gpio44"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se13_spi_pins: qupv3_se13_spi_pins { + qupv3_se13_spi_active: qupv3_se13_spi_active { + mux { + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; + function = "qup13"; + }; + + config { + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se13_spi_sleep: qupv3_se13_spi_sleep { + mux { + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; + function = "gpio"; + }; + + config { + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + + /* SE 14 pin mappings */ + qupv3_se14_i2c_pins: qupv3_se14_i2c_pins { + qupv3_se14_i2c_active: qupv3_se14_i2c_active { + mux { + pins = "gpio47", "gpio48"; + function = "qup14"; + }; + + config { + pins = "gpio47", "gpio48"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep { + mux { + pins = "gpio47", "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio47", "gpio48"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se14_spi_pins: qupv3_se14_spi_pins { + qupv3_se14_spi_active: qupv3_se14_spi_active { + mux { + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; + function = "qup14"; + }; + + config { + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se14_spi_sleep: qupv3_se14_spi_sleep { + mux { + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 15 pin mappings */ + qupv3_se15_i2c_pins: qupv3_se15_i2c_pins { + qupv3_se15_i2c_active: qupv3_se15_i2c_active { + mux { + pins = "gpio27", "gpio28"; + function = "qup15"; + }; + + config { + pins = "gpio27", "gpio28"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep { + mux { + pins = "gpio27", "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio27", "gpio28"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se15_spi_pins: qupv3_se15_spi_pins { + qupv3_se15_spi_active: qupv3_se15_spi_active { + mux { + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; + function = "qup15"; + }; + + config { + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_sleep: qupv3_se15_spi_sleep { + mux { + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 16 pin mappings */ + qupv3_se16_i2c_pins: qupv3_se16_i2c_pins { + qupv3_se16_i2c_active: qupv3_se16_i2c_active { + mux { + pins = "gpio86", "gpio85"; + function = "qup16"; + }; + + config { + pins = "gpio86", "gpio85"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se16_i2c_sleep: qupv3_se16_i2c_sleep { + mux { + pins = "gpio86", "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio86", "gpio85"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se16_spi_pins: qupv3_se16_spi_pins { + qupv3_se16_spi_active: qupv3_se16_spi_active { + mux { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + function = "qup16"; + }; + + config { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se16_spi_sleep: qupv3_se16_spi_sleep { + mux { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 17 pin mappings */ + qupv3_se17_i2c_pins: qupv3_se17_i2c_pins { + qupv3_se17_i2c_active: qupv3_se17_i2c_active { + mux { + pins = "gpio55", "gpio56"; + function = "qup17"; + }; + + config { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se17_i2c_sleep: qupv3_se17_i2c_sleep { + mux { + pins = "gpio55", "gpio56"; + function = "gpio"; + }; + + config { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + }; + }; + + qupv3_se17_spi_pins: qupv3_se17_spi_pins { + qupv3_se17_spi_active: qupv3_se17_spi_active { + mux { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + function = "qup17"; + }; + + config { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se17_spi_sleep: qupv3_se17_spi_sleep { + mux { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + function = "gpio"; + }; + + config { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 18 pin mappings */ + qupv3_se18_i2c_pins: qupv3_se18_i2c_pins { + qupv3_se18_i2c_active: qupv3_se18_i2c_active { + mux { + pins = "gpio23", "gpio24"; + function = "qup18"; + }; + + config { + pins = "gpio23", "gpio24"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se18_i2c_sleep: qupv3_se18_i2c_sleep { + mux { + pins = "gpio23", "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio24"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se18_spi_pins: qupv3_se18_spi_pins { + qupv3_se18_spi_active: qupv3_se18_spi_active { + mux { + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; + function = "qup18"; + }; + + config { + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se18_spi_sleep: qupv3_se18_spi_sleep { + mux { + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 19 pin mappings */ + qupv3_se19_i2c_pins: qupv3_se19_i2c_pins { + qupv3_se19_i2c_active: qupv3_se19_i2c_active { + mux { + pins = "gpio57", "gpio58"; + function = "qup19"; + }; + + config { + pins = "gpio57", "gpio58"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se19_i2c_sleep: qupv3_se19_i2c_sleep { + mux { + pins = "gpio57", "gpio58"; + function = "gpio"; + }; + + config { + pins = "gpio57", "gpio58"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se19_spi_pins: qupv3_se19_spi_pins { + qupv3_se19_spi_active: qupv3_se19_spi_active { + mux { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + function = "qup19"; + }; + + config { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se19_spi_sleep: qupv3_se19_spi_sleep { + mux { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + function = "gpio"; + }; + + config { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + aqt_intr { + aqt_intr_default: aqt_intr_default { + mux { + pins = "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio125"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + wcd9xxx_intr { + wcd_intr_default: wcd_intr_default { + mux { + pins = "gpio123"; + function = "gpio"; + }; + + config { + pins = "gpio123"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + cdc_reset_ctrl { + cdc_reset_sleep: cdc_reset_sleep { + mux { + pins = "gpio143"; + function = "gpio"; + }; + config { + pins = "gpio143"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_reset_active:cdc_reset_active { + mux { + pins = "gpio143"; + function = "gpio"; + }; + config { + pins = "gpio143"; + drive-strength = <8>; + bias-pull-down; + output-high; + }; + }; + }; + + sec_aux_pcm { + sec_aux_pcm_sleep: sec_aux_pcm_sleep { + mux { + pins = "gpio126", "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_active: sec_aux_pcm_active { + mux { + pins = "gpio126", "gpio127"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_aux_pcm_din { + sec_aux_pcm_din_sleep: sec_aux_pcm_din_sleep { + mux { + pins = "gpio128"; + function = "gpio"; + }; + + config { + pins = "gpio128"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_din_active: sec_aux_pcm_din_active { + mux { + pins = "gpio128"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio128"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_aux_pcm_dout { + sec_aux_pcm_dout_sleep: sec_aux_pcm_dout_sleep { + mux { + pins = "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio129"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_dout_active: sec_aux_pcm_dout_active { + mux { + pins = "gpio129"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio129"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_aux_pcm { + tert_aux_pcm_sleep: tert_aux_pcm_sleep { + mux { + pins = "gpio133", "gpio134"; + function = "gpio"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_active: tert_aux_pcm_active { + mux { + pins = "gpio133", "gpio134"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_aux_pcm_din { + tert_aux_pcm_din_sleep: tert_aux_pcm_din_sleep { + mux { + pins = "gpio135"; + function = "gpio"; + }; + + config { + pins = "gpio135"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_din_active: tert_aux_pcm_din_active { + mux { + pins = "gpio135"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio135"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_aux_pcm_dout { + tert_aux_pcm_dout_sleep: tert_aux_pcm_dout_sleep { + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_dout_active: tert_aux_pcm_dout_active { + mux { + pins = "gpio131"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio131"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_aux_pcm { + quat_aux_pcm_sleep: quat_aux_pcm_sleep { + mux { + pins = "gpio137", "gpio138"; + function = "gpio"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_pcm_active: quat_aux_pcm_active { + mux { + pins = "gpio137", "gpio138"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_aux_pcm_din { + quat_aux_pcm_din_sleep: quat_aux_pcm_din_sleep { + mux { + pins = "gpio139"; + function = "gpio"; + }; + + config { + pins = "gpio139"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_pcm_din_active: quat_aux_pcm_din_active { + mux { + pins = "gpio139"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio139"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_aux_pcm_dout { + quat_aux_pcm_dout_sleep: quat_aux_pcm_dout_sleep { + mux { + pins = "gpio140"; + function = "gpio"; + }; + + config { + pins = "gpio140"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_pcm_dout_active: quat_aux_pcm_dout_active { + mux { + pins = "gpio140"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio140"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_aux_pcm_clk { + pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep { + mux { + pins = "gpio144"; + function = "gpio"; + }; + + config { + pins = "gpio144"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_clk_active: pri_aux_pcm_clk_active { + mux { + pins = "gpio144"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio144"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_aux_pcm_sync { + pri_aux_pcm_sync_sleep: pri_aux_pcm_sync_sleep { + mux { + pins = "gpio145"; + function = "gpio"; + }; + + config { + pins = "gpio145"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_sync_active: pri_aux_pcm_sync_active { + mux { + pins = "gpio145"; + function = "pri_mi2s_ws"; + }; + + config { + pins = "gpio145"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_aux_pcm_din { + pri_aux_pcm_din_sleep: pri_aux_pcm_din_sleep { + mux { + pins = "gpio146"; + function = "gpio"; + }; + + config { + pins = "gpio146"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_din_active: pri_aux_pcm_din_active { + mux { + pins = "gpio146"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio146"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_aux_pcm_dout { + pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep { + mux { + pins = "gpio147"; + function = "gpio"; + }; + + config { + pins = "gpio147"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_dout_active: pri_aux_pcm_dout_active { + mux { + pins = "gpio147"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio147"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_aux_pcm { + quin_aux_pcm_sleep: quin_aux_pcm_sleep { + mux { + pins = "gpio149", "gpio151"; + function = "gpio"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_aux_pcm_active: quin_aux_pcm_active { + mux { + pins = "gpio149", "gpio151"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quin_aux_pcm_din { + quin_aux_pcm_din_sleep: quin_aux_pcm_din_sleep { + mux { + pins = "gpio150"; + function = "gpio"; + }; + + config { + pins = "gpio150"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_aux_pcm_din_active: quin_aux_pcm_din_active { + mux { + pins = "gpio150"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio150"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_aux_pcm_dout { + quin_aux_pcm_dout_sleep: quin_aux_pcm_dout_sleep { + mux { + pins = "gpio152"; + function = "gpio"; + }; + + config { + pins = "gpio152"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_aux_pcm_dout_active: quin_aux_pcm_dout_active { + mux { + pins = "gpio152"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio152"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_tdm { + sec_tdm_sleep: sec_tdm_sleep { + mux { + pins = "gpio126", "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_active: sec_tdm_active { + mux { + pins = "gpio126", "gpio127"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_tdm_din { + sec_tdm_din_sleep: sec_tdm_din_sleep { + mux { + pins = "gpio128"; + function = "gpio"; + }; + + config { + pins = "gpio128"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_din_active: sec_tdm_din_active { + mux { + pins = "gpio128"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio128"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_tdm_dout { + sec_tdm_dout_sleep: sec_tdm_dout_sleep { + mux { + pins = "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio129"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_dout_active: sec_tdm_dout_active { + mux { + pins = "gpio129"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio129"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_tdm { + tert_tdm_sleep: tert_tdm_sleep { + mux { + pins = "gpio133", "gpio134"; + function = "gpio"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_active: tert_tdm_active { + mux { + pins = "gpio133", "gpio134"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_tdm_din { + tert_tdm_din_sleep: tert_tdm_din_sleep { + mux { + pins = "gpio135"; + function = "gpio"; + }; + + config { + pins = "gpio135"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_din_active: tert_tdm_din_active { + mux { + pins = "gpio135"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio135"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_tdm_dout { + tert_tdm_dout_sleep: tert_tdm_dout_sleep { + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_dout_active: tert_tdm_dout_active { + mux { + pins = "gpio131"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio131"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_tdm { + quat_tdm_sleep: quat_tdm_sleep { + mux { + pins = "gpio137", "gpio138"; + function = "gpio"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_active: quat_tdm_active { + mux { + pins = "gpio137", "gpio138"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_tdm_din { + quat_tdm_din_sleep: quat_tdm_din_sleep { + mux { + pins = "gpio139"; + function = "gpio"; + }; + + config { + pins = "gpio139"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_din_active: quat_tdm_din_active { + mux { + pins = "gpio139"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio139"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_tdm_dout { + quat_tdm_dout_sleep: quat_tdm_dout_sleep { + mux { + pins = "gpio140"; + function = "gpio"; + }; + + config { + pins = "gpio140"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_dout_active: quat_tdm_dout_active { + mux { + pins = "gpio140"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio140"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_tdm_clk { + pri_tdm_clk_sleep: pri_tdm_clk_sleep { + mux { + pins = "gpio144"; + function = "gpio"; + }; + + config { + pins = "gpio144"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_clk_active: pri_tdm_clk_active { + mux { + pins = "gpio144"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio144"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_tdm_sync { + pri_tdm_sync_sleep: pri_tdm_sync_sleep { + mux { + pins = "gpio145"; + function = "gpio"; + }; + + config { + pins = "gpio145"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_sync_active: pri_tdm_sync_active { + mux { + pins = "gpio145"; + function = "pri_mi2s_ws"; + }; + + config { + pins = "gpio145"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_tdm_din { + pri_tdm_din_sleep: pri_tdm_din_sleep { + mux { + pins = "gpio146"; + function = "gpio"; + }; + + config { + pins = "gpio146"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_din_active: pri_tdm_din_active { + mux { + pins = "gpio146"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio146"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_tdm_dout { + pri_tdm_dout_sleep: pri_tdm_dout_sleep { + mux { + pins = "gpio147"; + function = "gpio"; + }; + + config { + pins = "gpio147"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_dout_active: pri_tdm_dout_active { + mux { + pins = "gpio147"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio147"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_tdm { + quin_tdm_sleep: quin_tdm_sleep { + mux { + pins = "gpio149", "gpio151"; + function = "gpio"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_tdm_active: quin_tdm_active { + mux { + pins = "gpio149", "gpio151"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quin_tdm_din { + quin_tdm_din_sleep: quin_tdm_din_sleep { + mux { + pins = "gpio150"; + function = "gpio"; + }; + + config { + pins = "gpio150"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_tdm_din_active: quin_tdm_din_active { + mux { + pins = "gpio150"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio150"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_tdm_dout { + quin_tdm_dout_sleep: quin_tdm_dout_sleep { + mux { + pins = "gpio152"; + function = "gpio"; + }; + + config { + pins = "gpio152"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_tdm_dout_active: quin_tdm_dout_active { + mux { + pins = "gpio152"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio152"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_mclk { + sec_mi2s_mclk_sleep: sec_mi2s_mclk_sleep { + mux { + pins = "gpio130"; + function = "gpio"; + }; + + config { + pins = "gpio130"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_mclk_active: sec_mi2s_mclk_active { + mux { + pins = "gpio130"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio130"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s { + sec_mi2s_sleep: sec_mi2s_sleep { + mux { + pins = "gpio126", "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO PULL */ + input-enable; + }; + }; + + sec_mi2s_active: sec_mi2s_active { + mux { + pins = "gpio126", "gpio127"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_sd0 { + sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep { + mux { + pins = "gpio128"; + function = "gpio"; + }; + + config { + pins = "gpio128"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sd0_active: sec_mi2s_sd0_active { + mux { + pins = "gpio128"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio128"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_sd1 { + sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep { + mux { + pins = "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio129"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sd1_active: sec_mi2s_sd1_active { + mux { + pins = "gpio129"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio129"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s_mclk { + tert_mi2s_mclk_sleep: tert_mi2s_mclk_sleep { + mux { + pins = "gpio132"; + function = "gpio"; + }; + + config { + pins = "gpio132"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_mclk_active: tert_mi2s_mclk_active { + mux { + pins = "gpio132"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio132"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s { + tert_mi2s_sleep: tert_mi2s_sleep { + mux { + pins = "gpio133", "gpio134"; + function = "gpio"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_active: tert_mi2s_active { + mux { + pins = "gpio133", "gpio134"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_mi2s_sd0 { + tert_mi2s_sd0_sleep: tert_mi2s_sd0_sleep { + mux { + pins = "gpio135"; + function = "gpio"; + }; + + config { + pins = "gpio135"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_sd0_active: tert_mi2s_sd0_active { + mux { + pins = "gpio135"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio135"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s_sd1 { + tert_mi2s_sd1_sleep: tert_mi2s_sd1_sleep { + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_sd1_active: tert_mi2s_sd1_active { + mux { + pins = "gpio131"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio131"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_mclk { + quat_mi2s_mclk_sleep: quat_mi2s_mclk_sleep { + mux { + pins = "gpio136"; + function = "gpio"; + }; + + config { + pins = "gpio136"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_mclk_active: quat_mi2s_mclk_active { + mux { + pins = "gpio136"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio136"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s { + quat_mi2s_sleep: quat_mi2s_sleep { + mux { + pins = "gpio137", "gpio138"; + function = "gpio"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_active: quat_mi2s_active { + mux { + pins = "gpio137", "gpio138"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_mi2s_sd0 { + quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { + mux { + pins = "gpio139"; + function = "gpio"; + }; + + config { + pins = "gpio139"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd0_active: quat_mi2s_sd0_active { + mux { + pins = "gpio139"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio139"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_sd1 { + quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { + mux { + pins = "gpio140"; + function = "gpio"; + }; + + config { + pins = "gpio140"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd1_active: quat_mi2s_sd1_active { + mux { + pins = "gpio140"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio140"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_sd2 { + quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { + mux { + pins = "gpio141"; + function = "gpio"; + }; + + config { + pins = "gpio141"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd2_active: quat_mi2s_sd2_active { + mux { + pins = "gpio141"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio141"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_sd3 { + quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { + mux { + pins = "gpio142"; + function = "gpio"; + }; + + config { + pins = "gpio142"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd3_active: quat_mi2s_sd3_active { + mux { + pins = "gpio142"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio142"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_mi2s_mclk { + pri_mi2s_mclk_sleep: pri_mi2s_mclk_sleep { + mux { + pins = "gpio143"; + function = "gpio"; + }; + + config { + pins = "gpio143"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_mclk_active: pri_mi2s_mclk_active { + mux { + pins = "gpio143"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio143"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sck { + pri_mi2s_sck_sleep: pri_mi2s_sck_sleep { + mux { + pins = "gpio144"; + function = "gpio"; + }; + + config { + pins = "gpio144"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sck_active: pri_mi2s_sck_active { + mux { + pins = "gpio144"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio144"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_ws { + pri_mi2s_ws_sleep: pri_mi2s_ws_sleep { + mux { + pins = "gpio145"; + function = "gpio"; + }; + + config { + pins = "gpio145"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_ws_active: pri_mi2s_ws_active { + mux { + pins = "gpio145"; + function = "pri_mi2s_ws"; + }; + + config { + pins = "gpio145"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sd0 { + pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep { + mux { + pins = "gpio146"; + function = "gpio"; + }; + + config { + pins = "gpio146"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd0_active: pri_mi2s_sd0_active { + mux { + pins = "gpio146"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio146"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_mi2s_sd1 { + pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep { + mux { + pins = "gpio147"; + function = "gpio"; + }; + + config { + pins = "gpio147"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd1_active: pri_mi2s_sd1_active { + mux { + pins = "gpio147"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio147"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_mi2s_mclk { + quin_mi2s_mclk_sleep: quin_mi2s_mclk_sleep { + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + quin_mi2s_mclk_active: quin_mi2s_mclk_active { + mux { + pins = "gpio148"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio148"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_mi2s { + quin_mi2s_sleep: quin_mi2s_sleep { + mux { + pins = "gpio149", "gpio151"; + function = "gpio"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_mi2s_active: quin_mi2s_active { + mux { + pins = "gpio149", "gpio151"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quin_mi2s_sd0 { + quin_mi2s_sd0_sleep: quin_mi2s_sd0_sleep { + mux { + pins = "gpio150"; + function = "gpio"; + }; + + config { + pins = "gpio150"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_mi2s_sd0_active: quin_mi2s_sd0_active { + mux { + pins = "gpio150"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio150"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_mi2s_sd1 { + quin_mi2s_sd1_sleep: quin_mi2s_sd1_sleep { + mux { + pins = "gpio152"; + function = "gpio"; + }; + + config { + pins = "gpio152"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_mi2s_sd1_active: quin_mi2s_sd1_active { + mux { + pins = "gpio152"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio152"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_dsi1_active: sde_dsi1_active { + mux { + pins = "gpio130"; + function = "gpio"; + }; + + config { + pins = "gpio130"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + sde_dsi1_suspend: sde_dsi1_suspend { + mux { + pins = "gpio130"; + function = "gpio"; + }; + + config { + pins = "gpio130"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio8"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio8"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te1_active: sde_te1_active { + mux { + pins = "gpio9"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te1_suspend: sde_te1_suspend { + mux { + pins = "gpio9"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + /* add pins for DisplayPort */ + sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + bias-disable; + drive-strength = <16>; + }; + }; + + sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + ap2mdm { + ap2mdm_active: ap2mdm_active { + mux { + /* ap2mdm-status + * ap2mdm-errfatal + * ap2mdm-vddmin + */ + pins = "gpio135", "gpio141"; + function = "gpio"; + }; + + config { + pins = "gpio135", "gpio141"; + drive-strength = <16>; + bias-disable; + }; + }; + ap2mdm_sleep: ap2mdm_sleep { + mux { + /* ap2mdm-status + * ap2mdm-errfatal + * ap2mdm-vddmin + */ + pins = "gpio135", "gpio141"; + function = "gpio"; + }; + + config { + pins = "gpio135", "gpio141"; + drive-strength = <8>; + bias-disable; + }; + + }; + }; + + mdm2ap { + mdm2ap_active: mdm2ap_active { + mux { + /* mdm2ap-status + * mdm2ap-errfatal + * mdm2ap-vddmin + */ + pins = "gpio142", "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio142", "gpio53"; + drive-strength = <8>; + bias-disable; + }; + }; + mdm2ap_sleep: mdm2ap_sleep { + mux { + /* mdm2ap-status + * mdm2ap-errfatal + * mdm2ap-vddmin + */ + pins = "gpio142", "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio142", "gpio53"; + drive-strength = <8>; + bias-disable; + }; + }; + }; + + fsa_usbc_ana_en_n@100 { + fsa_usbc_ana_en: fsa_usbc_ana_en { + mux { + pins = "gpio100"; + function = "gpio"; + }; + + config { + pins = "gpio100"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_eldo2_default: cam_sensor_eldo2_default { + /* AVDD ELDO2 */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* NO PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + camera_vaf_en_default: camera_vaf_en_default { + /* VAF ELDO1 */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + camera_vana_en_default: camera_vana_en_default { + /* VANA ELDO2 */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rear: cam_sensor_active_rear { + /* RESET REAR2 */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rear: cam_sensor_suspend_rear { + /* RESET REAR2 */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rear_aux: cam_sensor_active_rear_aux { + /* RESET REARAUX */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rear_aux: cam_sensor_suspend_rear_aux { + /* RESET REARAUX */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_front: cam_sensor_active_front { + /* RESET FRONT */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_front: cam_sensor_suspend_front { + /* RESET FRONT */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_iris: cam_sensor_active_iris { + /* RESET IRIS */ + mux { + pins = "gpio23", "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_iris: cam_sensor_suspend_iris { + /* RESET IRIS */ + mux { + pins = "gpio23", "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio26"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_triple_rear: cam_sensor_active_triple_rear { + mux { + pins = "gpio30", "gpio157", "gpio158"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio157", "gpio158"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_triple_rear: cam_sensor_suspend_triple_rear { + mux { + pins = "gpio30", "gpio157", "gpio158"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio157", "gpio158"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_triple_rear_aux: + cam_sensor_active_triple_rear_aux { + mux { + pins = "gpio23", "gpio159", "gpio160"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio159", "gpio160"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_triple_rear_aux: + cam_sensor_suspend_triple_rear_aux { + mux { + pins = "gpio23", "gpio159", "gpio160"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio159", "gpio160"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_triple_rear_aux2: + cam_sensor_active_triple_rear_aux2 { + mux { + pins = "gpio28", "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio24", "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_triple_rear_aux2: + cam_sensor_suspend_triple_rear_aux2 { + mux { + pins = "gpio28", "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio24", "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cci0_active: cci0_active { + mux { + /* CLK, DATA */ + pins = "gpio17","gpio18"; // Only 2 + function = "cci_i2c"; + }; + + config { + pins = "gpio17","gpio18"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio17","gpio18"; + function = "cci_i2c"; + }; + + config { + pins = "gpio17","gpio18"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA */ + pins = "gpio19","gpio20"; + function = "cci_i2c"; + }; + + config { + pins = "gpio19","gpio20"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio19","gpio20"; + function = "cci_i2c"; + }; + + config { + pins = "gpio19","gpio20"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_active: cci2_active { + mux { + /* CLK, DATA */ + pins = "gpio31","gpio32"; + function = "cci_i2c"; + }; + + config { + pins = "gpio31","gpio32"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_suspend: cci2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio31","gpio32"; + function = "cci_i2c"; + }; + + config { + pins = "gpio31","gpio32"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_active: cci3_active { + mux { + /* CLK, DATA */ + pins = "gpio33","gpio34"; + function = "cci_i2c"; + }; + + config { + pins = "gpio33","gpio34"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_suspend: cci3_suspend { + mux { + /* CLK, DATA */ + pins = "gpio33","gpio34"; + function = "cci_i2c"; + }; + + config { + pins = "gpio33","gpio34"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + tsif0_signals_active: tsif0_signals_active { + tsif1_clk { + pins = "gpio88"; /* TSIF0 CLK */ + function = "tsif1_clk"; + }; + tsif1_en { + pins = "gpio89"; /* TSIF0 Enable */ + function = "tsif1_en"; + }; + tsif1_data { + pins = "gpio90"; /* TSIF0 DATA */ + function = "tsif1_data"; + }; + signals_cfg { + pins = "gpio88", "gpio89", "gpio90"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + /* sync signal is only used if configured to mode-2 */ + tsif0_sync_active: tsif0_sync_active { + tsif1_sync { + pins = "gpio91"; /* TSIF0 SYNC */ + function = "tsif1_sync"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + tsif1_signals_active: tsif1_signals_active { + tsif2_clk { + pins = "gpio92"; /* TSIF1 CLK */ + function = "tsif2_clk"; + }; + tsif2_en { + pins = "gpio93"; /* TSIF1 Enable */ + function = "tsif2_en"; + }; + tsif2_data { + pins = "gpio94"; /* TSIF1 DATA */ + function = "tsif2_data"; + }; + signals_cfg { + pins = "gpio92", "gpio93", "gpio94"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + /* sync signal is only used if configured to mode-2 */ + tsif1_sync_active: tsif1_sync_active { + tsif2_sync { + pins = "gpio95"; /* TSIF1 SYNC */ + function = "tsif2_sync"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + trigout_a: trigout_a { + mux { + pins = "gpio49"; + function = "qdss_cti"; + }; + config { + pins = "gpio49"; + drive-strength = <2>; + bias-disable; + }; + }; + + usb2_id_det_default: usb2_id_det_default { + config { + pins = "gpio101"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + }; + + emac { + emac_mdc: emac_mdc { + mux { + pins = "gpio7"; + function = "rgmii_mdc"; + }; + + config { + pins = "gpio7"; + bias-pull-up; + }; + }; + emac_mdio: emac_mdio { + mux { + pins = "gpio59"; + function = "rgmii_mdio"; + }; + + config { + pins = "gpio59"; + bias-pull-up; + }; + }; + + emac_rgmii_txd0: emac_rgmii_txd0 { + mux { + pins = "gpio122"; + function = "rgmii_txd0"; + }; + + config { + pins = "gpio122"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txd1: emac_rgmii_txd1 { + mux { + pins = "gpio4"; + function = "rgmii_txd1"; + }; + + config { + pins = "gpio4"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txd2: emac_rgmii_txd2 { + mux { + pins = "gpio5"; + function = "rgmii_txd2"; + }; + + config { + pins = "gpio5"; + bias-pull-up; + drive-strength = <16>; + }; + }; + emac_rgmii_txd3: emac_rgmii_txd3 { + mux { + pins = "gpio6"; + function = "rgmii_txd3"; + }; + + config { + pins = "gpio6"; + bias-pull-up; + drive-strength = <16>; + }; + }; + emac_rgmii_txc: emac_rgmii_txc { + mux { + pins = "gpio114"; + function = "rgmii_txc"; + }; + + config { + pins = "gpio114"; + bias-pull-up; + drive-strength = <16>; + }; + }; + emac_rgmii_tx_ctl: emac_rgmii_tx_ctl { + mux { + pins = "gpio121"; + function = "rgmii_tx"; + }; + + config { + pins = "gpio121"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + + emac_rgmii_rxd0: emac_rgmii_rxd0 { + mux { + pins = "gpio117"; + function = "rgmii_rxd0"; + }; + + config { + pins = "gpio117"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2MA */ + }; + }; + + emac_rgmii_rxd1: emac_rgmii_rxd1 { + mux { + pins = "gpio118"; + function = "rgmii_rxd1"; + }; + + config { + pins = "gpio118"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_rgmii_rxd2: emac_rgmii_rxd2 { + mux { + pins = "gpio119"; + function = "rgmii_rxd2"; + }; + + config { + pins = "gpio119"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + emac_rgmii_rxd3: emac_rgmii_rxd3 { + mux { + pins = "gpio120"; + function = "rgmii_rxd3"; + }; + + config { + pins = "gpio120"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + emac_rgmii_rxc: emac_rgmii_rxc { + mux { + pins = "gpio115"; + function = "rgmii_rxc"; + }; + + config { + pins = "gpio115"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + emac_rgmii_rx_ctl: emac_rgmii_rx_ctl { + mux { + pins = "gpio116"; + function = "rgmii_rx"; + }; + + config { + pins = "gpio116"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + emac_phy_intr: emac_phy_intr { + mux { + pins = "gpio124"; + function = "emac_phy"; + }; + config { + pins = "gpio124"; + bias-disable; /* NO pull */ + drive-strength = <8>; + }; + }; + emac_phy_reset_state: emac_phy_reset_state { + mux { + pins = "gpio79"; + function = "gpio"; + }; + config { + pins = "gpio79"; + bias-pull-up; + drive-strength = <16>; + }; + }; + emac_pin_pps_0: emac_pin_pps_0 { + mux { + pins = "gpio81"; + function = "emac_pps"; + }; + + config { + pins = "gpio81"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + }; + + bt_en_active: bt_en_active { + mux { + pins = "gpio172"; + function = "gpio"; + }; + + config { + pins = "gpio172"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + conn_power_1p8_active: conn_power_1p8_active { + mux { + pins = "gpio173"; + function = "gpio"; + }; + + config { + pins = "gpio173"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + conn_power_pa_active: conn_power_pa_active { + mux { + pins = "gpio174"; + function = "gpio"; + }; + + config { + pins = "gpio174"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + usb2phy_ac_en1_default: usb2phy_ac_en1_default { + mux { + pins = "gpio113"; + function = "usb2phy_ac"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; + bias-disable; + }; + }; + + usb2phy_ac_en2_default: usb2phy_ac_en2_default { + mux { + pins = "gpio123"; + function = "usb2phy_ac"; + }; + + config { + pins = "gpio123"; + drive-strength = <2>; + bias-disable; + }; + }; + + audio_ioexp_reset_active: audio_ioexp_reset_active { + mux { + pins = "gpio166"; + function = "gpio"; + }; + config { + pins = "gpio166"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-pm.dtsi b/arch/arm/boot/dts/qcom/sm8150-pm.dtsi new file mode 100644 index 000000000000..f8555b6e07a9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-pm.dtsi @@ -0,0 +1,122 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include + +&soc { + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + qcom,use-psci; + #address-cells = <1>; + #size-cells = <0>; + qcom,pm-cluster@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + label = "L3"; + qcom,clstr-tmr-add = <1000>; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xfff>; + + qcom,pm-cluster-level@0 { /* D1 */ + reg = <0>; + label = "l3-wfi"; + qcom,psci-mode = <0x1>; + qcom,entry-latency-us = <48>; + qcom,exit-latency-us = <51>; + qcom,min-residency-us = <99>; + }; + + qcom,pm-cluster-level@1 { /* LLCC off, AOSS sleep */ + reg = <1>; + label = "llcc-off"; + qcom,psci-mode = <0xC24>; + qcom,entry-latency-us = <3263>; + qcom,exit-latency-us = <6562>; + qcom,min-residency-us = <9987>; + qcom,min-child-idx = <1>; + qcom,is-reset; + qcom,notify-rpm; + }; + + qcom,pm-cpu@0 { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,ref-stddev = <500>; + qcom,tmr-add = <1000>; + qcom,ref-premature-cnt = <1>; + qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>; + + qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + label = "wfi"; + qcom,psci-cpu-mode = <0x1>; + qcom,entry-latency-us = <57>; + qcom,exit-latency-us = <43>; + qcom,min-residency-us = <100>; + }; + + qcom,pm-cpu-level@1 { /* C4 */ + reg = <1>; + label = "rail-pc"; + qcom,psci-cpu-mode = <0x4>; + qcom,entry-latency-us = <355>; + qcom,exit-latency-us = <909>; + qcom,min-residency-us = <3934>; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + + qcom,pm-cpu@1 { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>; + + qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + label = "wfi"; + qcom,psci-cpu-mode = <0x1>; + qcom,entry-latency-us = <57>; + qcom,exit-latency-us = <43>; + qcom,min-residency-us = <83>; + }; + + qcom,pm-cpu-level@1 { /* C4 */ + reg = <1>; + label = "rail-pc"; + qcom,psci-cpu-mode = <0x4>; + qcom,entry-latency-us = <241>; + qcom,exit-latency-us = <1461>; + qcom,min-residency-us = <4488>; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + }; + }; + + qcom,rpm-stats@c300000 { + compatible = "qcom,rpm-stats"; + reg = <0xc300000 0x1000>, <0xc3f0004 0x4>; + reg-names = "phys_addr_base", "offset_addr"; + qcom,num-records = <3>; + }; + + qcom,rpmh-master-stats@b221200 { + compatible = "qcom,rpmh-master-stats-v1"; + reg = <0xb221200 0x60>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-pmic-overlay.dtsi b/arch/arm/boot/dts/qcom/sm8150-pmic-overlay.dtsi new file mode 100644 index 000000000000..f1c4666aa1a3 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-pmic-overlay.dtsi @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "pm8150.dtsi" +#include "pm8150b.dtsi" +#include "pm8150l.dtsi" +#include + +/* PMIC GPIO pin control configurations: */ +&pm8150_gpios { + key_home { + key_home_default: key_home_default { + pins = "gpio1"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; + + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <1>; + }; + }; + + usb2_vbus_boost { + usb2_vbus_boost_default: usb2_vbus_boost_default { + pins = "gpio9"; + function = "normal"; + output-low; + power-source = <1>; /* 1.8V input supply */ + }; + }; + + usb2_vbus_det { + usb2_vbus_det_default: usb2_vbus_det_default { + pins = "gpio10"; + function = "normal"; + input-enable; + bias-pull-down; + power-source = <1>; /* 1.8V input supply */ + }; + }; +}; + +&pm8150l_gpios { + cam_sensor_eldo4 { + cam_sensor_eldo4_default: cam_sensor_eldo4_default { + pins = "gpio3"; + function = "normal"; + power-source = <0>; + output-low; + }; + }; + + cam_sensor_eldo3 { + cam_sensor_eldo3_default: cam_sensor_eldo3_default { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + }; + }; +}; + +&pm8150b_charger { + dpdm-supply = <&usb2_phy0>; + smb5_vconn: qcom,smb5-vconn { + regulator-name = "smb5-vconn"; + }; + smb5_vbus: qcom,smb5-vbus { + regulator-name = "smb5-vbus"; + }; +}; + +&pm8150b_fg { + nvmem-names = "fg_sdam"; + nvmem = <&pm8150_sdam_2>; +}; + +&pm8150b_qnovo { + pinctrl-names = "q_state1", "q_state2"; + pinctrl-0 = <&qnovo_fet_ctrl_state1>; + pinctrl-1 = <&qnovo_fet_ctrl_state2>; +}; + +&pm8150b_gpios { + smb_stat { + smb_stat_default: smb_stat_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = <0>; + }; + }; + + qnovo_fet_ctrl { + qnovo_fet_ctrl_state1: qnovo_fet_ctrl_state1 { + pins = "gpio8"; + function = "normal"; + input-enable; + output-disable; + bias-disable; + power-source = <0>; + }; + + qnovo_fet_ctrl_state2: qnovo_fet_ctrl_state2 { + pins = "gpio8"; + function = "normal"; + input-enable; + output-disable; + bias-pull-down; + power-source = <0>; + }; + }; +}; + +&usb0 { + extcon = <&pm8150b_pdphy>, <&eud>; +}; + +&usb_qmp_dp_phy { + extcon = <&pm8150b_pdphy>; +}; + +&sde_dp { + extcon = <&pm8150b_pdphy>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-qrd-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/sm8150-qrd-audio-overlay.dtsi new file mode 100644 index 000000000000..512fc98ceb2b --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-qrd-audio-overlay.dtsi @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm8150-audio-overlay.dtsi" + +&snd_9360 { + qcom,model = "sm8150-pahu-qrd-snd-card"; + qcom,audio-routing = + "AIF4 VI", "MCLK", + "MADINPUT", "MCLK", + "DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "SpkrRight IN", "SPK2 OUT"; + + qcom,wsa-max-devs = <1>; + qcom,wsa-devs = <&wsa881x_0212>, <&wsa881x_0214>; + qcom,wsa-aux-dev-prefix = "SpkrRight", "SpkrRight"; +}; + +&snd_934x { + qcom,model = "sm8150-tavil-qrd-snd-card"; + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "SpkrRight IN", "SPK2 OUT"; + + qcom,wsa-max-devs = <1>; + qcom,wsa-devs = <&wsa881x_70212>, <&wsa881x_70214>; + qcom,wsa-aux-dev-prefix = "SpkrRight", "SpkrRight"; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-qrd-dvt-overlay.dts b/arch/arm/boot/dts/qcom/sm8150-qrd-dvt-overlay.dts new file mode 100644 index 000000000000..f06a3931bffb --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-qrd-dvt-overlay.dts @@ -0,0 +1,28 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-qrd-dvt.dtsi" +#include "sm8150-qrd-audio-overlay.dtsi" + +/ { + model = "QRD DVT"; + compatible = "qcom,sm8150-qrd", "qcom,sm8150", "qcom,qrd"; + qcom,board-id = <0x01000B 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-qrd-dvt.dtsi b/arch/arm/boot/dts/qcom/sm8150-qrd-dvt.dtsi new file mode 100644 index 000000000000..c525073ac2af --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-qrd-dvt.dtsi @@ -0,0 +1,29 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm8150-qrd.dtsi" + +&usb_qmp_dp_phy { + vdd-supply = <&pm8150_l18>; + qcom,vdd-voltage-level = <0 912000 912000>; +}; + +&sde_dp { + vdda-0p9-supply = <&pm8150_l18>; + qcom,phy-supply-entries { + qcom,phy-supply-entry@0 { + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <912000>; + }; + }; + +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-qrd-overlay.dts b/arch/arm/boot/dts/qcom/sm8150-qrd-overlay.dts new file mode 100644 index 000000000000..301d7265dfd7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-qrd-overlay.dts @@ -0,0 +1,28 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-qrd.dtsi" +#include "sm8150-qrd-audio-overlay.dtsi" + +/ { + model = "QRD"; + compatible = "qcom,sm8150-qrd", "qcom,sm8150", "qcom,qrd"; + qcom,board-id = <11 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-qrd.dts b/arch/arm/boot/dts/qcom/sm8150-qrd.dts new file mode 100644 index 000000000000..6eb1c61975a9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-qrd.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150.dtsi" +#include "sm8150-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150 QRD"; + compatible = "qcom,sm8150-qrd", "qcom,sm8150", "qcom,qrd"; + qcom,board-id = <11 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-qrd.dtsi b/arch/arm/boot/dts/qcom/sm8150-qrd.dtsi new file mode 100644 index 000000000000..10b07a2dd36d --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-qrd.dtsi @@ -0,0 +1,687 @@ +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "sm8150-pmic-overlay.dtsi" +#include "sm8150-sde-display.dtsi" +#include "sm8150-camera-sensor-qrd.dtsi" +#include "sm8150-thermal-overlay.dtsi" + +&qupv3_se4_i2c { +#address-cells = <1>; +#size-cells = <0>; + +#include "smb1390.dtsi" +#include "smb1355.dtsi" +}; + +&vendor { + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-core-supply = <&pm8150_l7>; + qca,bt-vdd-pa-supply = <&pm8150l_l2>; + qca,bt-vdd-ldo-supply = <&pm8150l_l11>; + + qca,bt-vdd-core-voltage-level = <1800000 1800000>; + qca,bt-vdd-pa-voltage-level = <1304000 1304000>; + qca,bt-vdd-ldo-voltage-level = <3312000 3312000>; + + qca,bt-vdd-core-current-level = <0>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <0>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <0>; /* LPM/PFM */ + }; + + qrd_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "fg-gen4-batterydata-mlp466076-3250mah.dtsi" + }; +}; + +&pm8150b_fg { + qcom,battery-data = <&qrd_batterydata>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,five-pin-battery; + qcom,cl-wt-enable; + /* ESR fast calibration */ + qcom,fg-esr-timer-chg-fast = <0 7>; + qcom,fg-esr-timer-dischg-fast = <0 7>; + qcom,fg-esr-timer-chg-slow = <0 96>; + qcom,fg-esr-timer-dischg-slow = <0 96>; + qcom,fg-esr-cal-soc-thresh = <26 230>; + qcom,fg-esr-cal-temp-thresh = <10 40>; +}; + +&pm8150a_amoled { + status = "ok"; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; + + qcom,qbt1000 { + compatible = "qcom,qbt1000"; + clock-names = "core", "iface"; + clock-frequency = <25000000>; + qcom,ipc-gpio = <&tlmm 118 0>; + pinctrl-names = "default"; + pinctrl-0 = <&key_home_default>; + qcom,finger-detect-gpio = <&pm8150_gpios 1 0>; + }; +}; + +&qupv3_se17_i2c { + status = "ok"; + + #address-cells = <1>; + #size-cells = <0>; + + st_fts@49 { + compatible = "st,fts"; + reg = <0x49>; + interrupt-parent = <&tlmm>; + interrupts = <122 0x2008>; + vdd-supply = <&pm8150_s4>; + avdd-supply = <&pm8150_l17>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + st,irq-gpio = <&tlmm 122 0x2008>; + st,reset-gpio = <&tlmm 54 0x00>; + st,regulator_dvdd = "vdd"; + st,regulator_avdd = "avdd"; + }; +}; + +&qupv3_se9_i2c { + status = "ok"; + + #address-cells = <1>; + #size-cells = <0>; + + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 47 0x00>; + qcom,nq-ven = <&tlmm 41 0x00>; + qcom,nq-firm = <&tlmm 48 0x00>; + qcom,nq-clkreq = <&tlmm 113 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <47 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active + &nfc_clk_req_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend + &nfc_clk_req_suspend>; + }; +}; + +&dsi_panel_pwr_supply_vdd_no_labibb { + qcom,panel-supply-entry@1 { + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + }; +}; + +&sde_dsi { + lab-supply = &ab_vreg; + ibb-supply = &ibb_vreg; +}; + +&dsi_sw43404_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_vdd_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sw43404_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_vdd_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sw43404_amoled_fhd_plus_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_vdd_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sw43404_amoled_cmd_display { + qcom,dsi-display-active; +}; + +&sde_dsi { + vdd-supply = <&display_panel_avdd_eldo>; +}; + +&qupv3_se12_2uart { + status = "ok"; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + +&qupv3_se3_spi { + status = "ok"; +}; + +&qupv3_se4_i2c { + status = "ok"; + + #address-cells = <1>; + #size-cells = <0>; + + redriver@19 { + compatible = "onnn,redriver"; + reg = <0x19>; + extcon = <&pm8150b_pdphy>, <&pm8150b_pdphy>; + eq = /bits/ 8 < + /* Parameters for USB */ + 0x4 0x4 0x4 0x4 + /* Parameters for DP */ + 0x6 0x4 0x4 0x6>; + flat-gain = /bits/ 8 < + /* Parameters for USB */ + 0x3 0x1 0x1 0x3 + /* Parameters for DP */ + 0x2 0x1 0x1 0x2>; + output-comp = /bits/ 8 < + /* Parameters for USB */ + 0x3 0x3 0x3 0x3 + /* Parameters for DP */ + 0x3 0x3 0x3 0x3>; + loss-match = /bits/ 8 < + /* Parameters for USB */ + 0x1 0x3 0x3 0x1 + /* Parameters for DP */ + 0x3 0x3 0x3 0x3>; + }; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4"; + + vdda-phy-supply = <&pm8150_l5>; + vdda-phy-always-on; + vdda-pll-supply = <&pm8150l_l3>; + vdda-phy-max-microamp = <90200>; + vdda-pll-max-microamp = <19000>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8150_l10>; + vcc-voltage-level = <2504000 2950000>; + vcc-low-voltage-sup; + vccq-supply = <&pm8150_l9>; + vccq2-supply = <&pm8150_s4>; + vcc-max-microamp = <750000>; + vccq-max-microamp = <700000>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&pm8150_l9>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm8150l_l9>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8150l_l6>; + qcom,vdd-io-voltage-level = <1808000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>; + + cd-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + + status = "ok"; +}; + +&pm8150b_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + wp_therm { + reg = ; + label = "wp_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + chg_sbux { + reg = ; + label = "chg_sbux"; + qcom,pre-scaling = <1 3>; + }; + + mid_chg_div6 { + reg = ; + label = "chg_mid"; + qcom,pre-scaling = <1 6>; + }; + + usb_in_i_uv { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + usb_in_v_div_16 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; +}; + +&pm8150_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_therm { + reg = ; + label = "skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm1 { + reg = ; + label = "pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150l_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + camera_flash_therm { + reg = ; + label = "camera_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_msm_therm { + reg = ; + label = "skin_msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm2 { + reg = ; + label = "pa_therm2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&wil6210 { + status = "ok"; +}; + +&pm8150b_adc_tm { + wp_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150_adc_tm { + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150l_adc_tm { + camera_flash_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin_msm_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm2 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + wp-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + camera-flash-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-msm-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-therm2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&spmi_debug_bus { + status = "ok"; +}; + +&pm8150b_haptics { + qcom,vmax-mv = <2545>; + qcom,play-rate-us = <4255>; + wf_0 { + /* CLICK */ + qcom,wf-pattern = [3e 3e 3e 3e]; + qcom,wf-play-rate-us = <4255>; + }; + wf_1 { + /* DOUBLE CLICK */ + qcom,wf-play-rate-us = <7143>; + }; + wf_2 { + /* TICK */ + qcom,wf-play-rate-us = <4000>; + }; + wf_3 { + /* THUD */ + qcom,wf-pattern = [7e 7e 7e 7e]; + qcom,wf-play-rate-us = <4255>; + }; + wf_4 { + /* POP */ + qcom,wf-play-rate-us = <5000>; + }; + wf_5 { + /* HEAVY CLICK */ + qcom,wf-pattern = [7e 7e 7e 7e]; + qcom,wf-play-rate-us = <4255>; + }; +}; + +&pm8150b_charger { + qcom,sec-charger-config = <1>; + qcom,auto-recharge-soc = <98>; + io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>, + <&pm8150b_vadc ADC_USB_IN_I>, + <&pm8150b_vadc ADC_SBUx>, + <&pm8150b_vadc ADC_VPH_PWR>, + <&pm8150b_vadc ADC_CHG_TEMP>, + <&pm8150b_vadc ADC_USB_IN_V_16>; + io-channel-names = "mid_voltage", + "usb_in_current", + "sbux_res", + "vph_voltage", + "chg_temp", + "usb_in_voltage"; + qcom,battery-data = <&qrd_batterydata>; + qcom,sw-jeita-enable; + qcom,wd-bark-time-secs = <16>; + qcom,suspend-input-on-debug-batt; + qcom,thermal-mitigation = <4875000 4000000 3500000 + 3000000 2500000 2000000 + 1500000 1000000 500000>; +}; + +&smb1390 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1390_charger { + /delete-property/ compatible; + compatible = "qcom,smb1390-charger-psy"; + io-channels = <&pm8150b_vadc ADC_AMUX_THM2>; + io-channel-names = "cp_die_temp"; + status = "ok"; +}; + +&usb2_phy0 { + /* + * update SQRXTUNE0 to appropriate value if analog + * audio switch is installed. + * otherwise use power on default(i.e 0x3) + */ + qcom,param-override-seq = + <0xc1 0x6c + 0x49 0x70 + 0x28 0x74>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-qupv3.dtsi b/arch/arm/boot/dts/qcom/sm8150-qupv3.dtsi new file mode 100644 index 000000000000..aa109f9a7f94 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-qupv3.dtsi @@ -0,0 +1,1081 @@ +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + /* QUPv3 South Instances */ + qupv3_0: qcom,qupv3_0_geni_se@8c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x8c0000 0x6000>; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; + qcom,iommu-s1-bypass; + + iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0xc3 0x0>; + }; + }; + + /* I2C */ + qupv3_se0_i2c: i2c@880000 { + compatible = "qcom,i2c-geni"; + reg = <0x880000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + dmas = <&gpi_dma0 0 0 3 64 0>, + <&gpi_dma0 1 0 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@884000 { + compatible = "qcom,i2c-geni"; + reg = <0x884000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + dmas = <&gpi_dma0 0 1 3 64 0>, + <&gpi_dma0 1 1 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@888000 { + compatible = "qcom,i2c-geni"; + reg = <0x888000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + dmas = <&gpi_dma0 0 2 3 64 0>, + <&gpi_dma0 1 2 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@88c000 { + compatible = "qcom,i2c-geni"; + reg = <0x88c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + dmas = <&gpi_dma0 0 3 3 64 0>, + <&gpi_dma0 1 3 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@890000 { + compatible = "qcom,i2c-geni"; + reg = <0x890000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + dmas = <&gpi_dma0 0 4 3 64 0>, + <&gpi_dma0 1 4 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se5_i2c: i2c@894000 { + compatible = "qcom,i2c-geni"; + reg = <0x894000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + dmas = <&gpi_dma0 0 5 3 64 0>, + <&gpi_dma0 1 5 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@898000 { + compatible = "qcom,i2c-geni"; + reg = <0x898000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + dmas = <&gpi_dma0 0 6 3 64 0>, + <&gpi_dma0 1 6 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se7_i2c: i2c@89c000 { + compatible = "qcom,i2c-geni"; + reg = <0x89c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + dmas = <&gpi_dma0 0 7 3 64 0>, + <&gpi_dma0 1 7 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se0_spi: spi@880000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x880000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + dmas = <&gpi_dma0 0 0 1 64 0>, + <&gpi_dma0 1 0 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se1_spi: spi@884000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x884000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_spi_active>; + pinctrl-1 = <&qupv3_se1_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + dmas = <&gpi_dma0 0 1 1 64 0>, + <&gpi_dma0 1 1 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se2_spi: spi@888000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x888000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + dmas = <&gpi_dma0 0 2 1 64 0>, + <&gpi_dma0 1 2 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se3_spi: spi@88c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x88c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_spi_active>; + pinctrl-1 = <&qupv3_se3_spi_sleep &qupv3_se3_spi_miso_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + dmas = <&gpi_dma0 0 3 1 64 0>, + <&gpi_dma0 1 3 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se4_spi: spi@890000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x890000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_spi_active>; + pinctrl-1 = <&qupv3_se4_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + dmas = <&gpi_dma0 0 4 1 64 0>, + <&gpi_dma0 1 4 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se5_spi: spi@894000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x894000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + dmas = <&gpi_dma0 0 5 1 64 0>, + <&gpi_dma0 1 5 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se6_spi: spi@898000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x898000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + dmas = <&gpi_dma0 0 6 1 64 0>, + <&gpi_dma0 1 6 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se7_spi: spi@89c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x89c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_spi_active>; + pinctrl-1 = <&qupv3_se7_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + dmas = <&gpi_dma0 0 7 1 64 0>, + <&gpi_dma0 1 7 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + /* QUPv3 North & East Instances + * North 0 : SE 8 + * North 1 : SE 9 + * North 2 : SE 10 + * North 3 : SE 11 + * North 4 : SE 12 + * North 5 : SE 16 + * East 0 : SE 17 + * East 1 : SE 18 + * East 2 : SE 19 + * East 3 : SE 13 + * East 4 : SE 14 + * East 5 : SE 15 + */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0xac0000 0x6000>; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; + qcom,iommu-s1-bypass; + + iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0x603 0x0>; + }; + }; + + /* 2-wire UART */ + + /* Debug UART Instance for CDP/MTP platform */ + qupv3_se12_2uart: qcom,qup_uart@0xa90000 { + compatible = "qcom,msm-geni-console"; + reg = <0xa90000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_2uart_active>; + pinctrl-1 = <&qupv3_se12_2uart_sleep>; + interrupts = ; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* 4-wire UART */ + qupv3_se13_4uart: qcom,qup_uart@0xc8c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0xc8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "active", "sleep"; + pinctrl-0 = <&qupv3_se13_default_ctsrtsrx>, + <&qupv3_se13_default_tx>; + pinctrl-1 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>, + <&qupv3_se13_tx>; + pinctrl-2 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>, + <&qupv3_se13_tx>; + interrupts-extended = <&pdc GIC_SPI 585 0>, + <&tlmm 46 0>; + qcom,wrapper-core = <&qupv3_2>; + qcom,wakeup-byte = <0xFD>; + status = "disabled"; + }; + + /* I2C */ + qupv3_se8_i2c: i2c@a80000 { + compatible = "qcom,i2c-geni"; + reg = <0xa80000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + dmas = <&gpi_dma1 0 0 3 64 0>, + <&gpi_dma1 1 0 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@a84000 { + compatible = "qcom,i2c-geni"; + reg = <0xa84000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + dmas = <&gpi_dma1 0 1 3 64 0>, + <&gpi_dma1 1 1 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se10_i2c: i2c@a88000 { + compatible = "qcom,i2c-geni"; + reg = <0xa88000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + dmas = <&gpi_dma1 0 2 3 64 0>, + <&gpi_dma1 1 2 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_i2c_active>; + pinctrl-1 = <&qupv3_se10_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se11_i2c: i2c@a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xa8c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + dmas = <&gpi_dma1 0 3 3 64 0>, + <&gpi_dma1 1 3 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_i2c_active>; + pinctrl-1 = <&qupv3_se11_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se12_i2c: i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + dmas = <&gpi_dma1 0 4 3 64 0>, + <&gpi_dma1 1 4 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_i2c_active>; + pinctrl-1 = <&qupv3_se12_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se13_i2c: i2c@c8c000 { + compatible = "qcom,i2c-geni"; + reg = <0xc8c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + dmas = <&gpi_dma2 0 3 3 64 0>, + <&gpi_dma2 1 3 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_i2c_active>; + pinctrl-1 = <&qupv3_se13_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se8_spi: spi@a80000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa80000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_spi_active>; + pinctrl-1 = <&qupv3_se8_spi_active>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + dmas = <&gpi_dma1 0 0 1 64 0>, + <&gpi_dma1 1 0 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se9_spi: spi@a84000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa84000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + dmas = <&gpi_dma1 0 1 1 64 0>, + <&gpi_dma1 1 1 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se10_spi: spi@a88000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa88000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_spi_active>; + pinctrl-1 = <&qupv3_se10_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + dmas = <&gpi_dma1 0 2 1 64 0>, + <&gpi_dma1 1 2 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se11_spi: spi@a8c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se11_spi_active>; + pinctrl-1 = <&qupv3_se11_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + dmas = <&gpi_dma1 0 3 1 64 0>, + <&gpi_dma1 1 3 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se12_spi: spi@a90000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa90000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se12_spi_active>; + pinctrl-1 = <&qupv3_se12_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + dmas = <&gpi_dma1 0 4 1 64 0>, + <&gpi_dma1 1 4 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se13_spi: spi@c8c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se13_spi_active>; + pinctrl-1 = <&qupv3_se13_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + dmas = <&gpi_dma2 0 3 1 64 0>, + <&gpi_dma2 1 3 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + /* QUPv3 East Instances */ + qupv3_2: qcom,qupv3_2_geni_se@cc0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0xcc0000 0x6000>; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; + qcom,iommu-s1-bypass; + + iommu_qupv3_2_geni_se_cb: qcom,iommu_qupv3_2_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0x7a3 0x0>; + }; + }; + + /* I2C */ + qupv3_se14_i2c: i2c@0xc90000 { + compatible = "qcom,i2c-geni"; + reg = <0xc90000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + dmas = <&gpi_dma2 0 4 3 64 0>, + <&gpi_dma2 1 4 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_i2c_active>; + pinctrl-1 = <&qupv3_se14_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se15_i2c: i2c@0xc94000 { + compatible = "qcom,i2c-geni"; + reg = <0xc94000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S5_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + dmas = <&gpi_dma2 0 5 3 64 0>, + <&gpi_dma2 1 5 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_i2c_active>; + pinctrl-1 = <&qupv3_se15_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se16_i2c: i2c@0xa94000 { + compatible = "qcom,i2c-geni"; + reg = <0xa94000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + dmas = <&gpi_dma2 0 5 3 64 0>, + <&gpi_dma2 1 5 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se16_i2c_active>; + pinctrl-1 = <&qupv3_se16_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se17_i2c: i2c@0xc80000 { + compatible = "qcom,i2c-geni"; + reg = <0xc80000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + dmas = <&gpi_dma2 0 0 3 64 0>, + <&gpi_dma2 1 0 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se17_i2c_active>; + pinctrl-1 = <&qupv3_se17_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se18_i2c: i2c@0xc84000 { + compatible = "qcom,i2c-geni"; + reg = <0xc84000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S1_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + dmas = <&gpi_dma2 0 1 3 64 0>, + <&gpi_dma2 1 1 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se18_i2c_active>; + pinctrl-1 = <&qupv3_se18_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + qupv3_se19_i2c: i2c@0xc88000 { + compatible = "qcom,i2c-geni"; + reg = <0xc88000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + dmas = <&gpi_dma2 0 2 3 64 0>, + <&gpi_dma2 1 2 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se19_i2c_active>; + pinctrl-1 = <&qupv3_se19_i2c_sleep>; + qcom,wrapper-core = <&qupv3_2>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se14_spi: spi@c90000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc90000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se14_spi_active>; + pinctrl-1 = <&qupv3_se14_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + dmas = <&gpi_dma2 0 4 1 64 0>, + <&gpi_dma2 1 4 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se15_spi: spi@c94000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc94000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S5_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se15_spi_active>; + pinctrl-1 = <&qupv3_se15_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + dmas = <&gpi_dma2 0 5 1 64 0>, + <&gpi_dma2 1 5 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se16_spi: spi@a94000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa94000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se16_spi_active>; + pinctrl-1 = <&qupv3_se16_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + dmas = <&gpi_dma1 0 5 1 64 0>, + <&gpi_dma1 1 5 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se17_spi: spi@c80000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc80000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se17_spi_active>; + pinctrl-1 = <&qupv3_se17_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + dmas = <&gpi_dma2 0 0 1 64 0>, + <&gpi_dma2 1 0 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se18_spi: spi@c84000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc84000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S1_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se18_spi_active>; + pinctrl-1 = <&qupv3_se18_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + dmas = <&gpi_dma2 0 1 1 64 0>, + <&gpi_dma2 1 1 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se19_spi: spi@c88000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc88000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP2_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se19_spi_active>; + pinctrl-1 = <&qupv3_se19_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_2>; + dmas = <&gpi_dma2 0 2 1 64 0>, + <&gpi_dma2 1 2 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + /* QUPv3 SSC Instances */ + qupv3_3: qcom,qupv3_3_geni_se@26c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x26c0000 0x6000>; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; + qcom,iommu-s1-bypass; + + iommu_qupv3_3_geni_se_cb: qcom,iommu_qupv3_3_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0x4e3 0x0>; + }; + }; + + /* I2C */ + qupv3_se20_i2c: i2c@2680000 { + compatible = "qcom,i2c-geni"; + reg = <0x2680000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_scc SCC_QUPV3_SE0_CLK>, + <&clock_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se20_i2c_active>; + pinctrl-1 = <&qupv3_se20_i2c_sleep>; + qcom,wrapper-core = <&qupv3_3>; + status = "disabled"; + }; + + qupv3_se21_i2c: i2c@2684000 { + compatible = "qcom,i2c-geni"; + reg = <0x2684000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_scc SCC_QUPV3_SE1_CLK>, + <&clock_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se21_i2c_active>; + pinctrl-1 = <&qupv3_se21_i2c_sleep>; + qcom,wrapper-core = <&qupv3_3>; + status = "disabled"; + }; + + qupv3_se22_i2c: i2c@2688000 { + compatible = "qcom,i2c-geni"; + reg = <0x2688000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_scc SCC_QUPV3_SE2_CLK>, + <&clock_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se22_i2c_active>; + pinctrl-1 = <&qupv3_se22_i2c_sleep>; + qcom,wrapper-core = <&qupv3_3>; + status = "disabled"; + }; + + qupv3_se23_i2c: i2c@268c000 { + compatible = "qcom,i2c-geni"; + reg = <0x268c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_scc SCC_QUPV3_SE3_CLK>, + <&clock_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se23_i2c_active>; + pinctrl-1 = <&qupv3_se23_i2c_sleep>; + qcom,wrapper-core = <&qupv3_3>; + status = "disabled"; + }; + + /* SPI */ + qupv3_se21_spi: spi@2684000 { + compatible = "qcom,spi-geni"; + reg = <0x2684000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_scc SCC_QUPV3_SE1_CLK>, + <&clock_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se21_spi_active>; + pinctrl-1 = <&qupv3_se21_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_3>; + status = "disabled"; + }; + + qupv3_se22_spi: spi@2688000 { + compatible = "qcom,spi-geni"; + reg = <0x2688000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_scc SCC_QUPV3_SE2_CLK>, + <&clock_scc SCC_QUPV3_M_HCLK_CLK>, + <&clock_scc SCC_QUPV3_S_HCLK_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se22_spi_active>; + pinctrl-1 = <&qupv3_se22_spi_sleep>; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_3>; + qcom,disable-dma; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-regulator.dtsi b/arch/arm/boot/dts/qcom/sm8150-regulator.dtsi new file mode 100644 index 000000000000..e12333e4bc09 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-regulator.dtsi @@ -0,0 +1,1001 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + + +&soc { + /* Stub regulators */ + + /* + * RPMh does not provide support for PM8150 S4 because it is always-on + * at 1.8 V in auto mode. Therefore, use a stub regulator for S4. + */ + S4A: pm8150_s4: regulator-pm8150-s4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_s4"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&soc { + /* RPMh regulators: */ + + /* PM8150 S1 = VDD_MODEM supply */ + rpmh-regulator-msslvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "mss.lvl"; + S1A_LEVEL: pm8150_s1_level: regulator-pm8150-s1-level { + regulator-name = "pm8150_s1_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + rpmh-regulator-smpa2 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpa2"; + S2A: pm8150_s2: regulator-pm8150-s2 { + regulator-name = "pm8150_s2"; + qcom,set = ; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + qcom,init-voltage = <600000>; + }; + }; + + /* PM8150 S3 = VDD_EBI supply */ + rpmh-regulator-ebilvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ebi.lvl"; + S3A_LEVEL: pm8150_s3_level: regulator-pm8150-s3-level { + regulator-name = "pm8150_s3_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + ebi_cdev: regulator-cdev { + compatible = "qcom,rpmh-reg-cdev"; + mboxes = <&qmp_aop 0>; + qcom,reg-resource-name = "ebi"; + #cooling-cells = <2>; + }; + }; + + rpmh-regulator-smpa5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpa5"; + S5A: pm8150_s5: regulator-pm8150-s5 { + regulator-name = "pm8150_s5"; + qcom,set = ; + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1904000>; + }; + }; + + rpmh-regulator-smpa6 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpa6"; + S6A: pm8150_s6: regulator-pm8150-s6 { + regulator-name = "pm8150_s6"; + qcom,set = ; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1128000>; + qcom,init-voltage = <920000>; + }; + }; + + rpmh-regulator-ldoa1 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L1A: pm8150_l1: regulator-pm8150-l1 { + regulator-name = "pm8150_l1"; + qcom,set = ; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + qcom,init-voltage = <752000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa2 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L2A: pm8150_l2: regulator-pm8150-l2 { + regulator-name = "pm8150_l2"; + qcom,set = ; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + qcom,init-voltage = <3072000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa3 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L3A: pm8150_l3: regulator-pm8150-l3 { + regulator-name = "pm8150_l3"; + qcom,set = ; + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <932000>; + qcom,init-voltage = <480000>; + qcom,init-mode = ; + }; + }; + + /* PM8150 L4 = VDD_SSC_MX supply */ + rpmh-regulator-lmxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "lmx.lvl"; + L4A_LEVEL: pm8150_l4_level: regulator-pm8150-l4-level { + regulator-name = "pm8150_l4_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level + = ; + }; + }; + + rpmh-regulator-ldoa5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + proxy-supply = <&pm8150_l5>; + L5A: pm8150_l5: regulator-pm8150-l5 { + regulator-name = "pm8150_l5"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <23800>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + + L5A_AO: pm8150_l5_ao: regulator-pm8150-l5-ao { + regulator-name = "pm8150_l5_ao"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + }; + + regulator-pm8150-l5-so { + regulator-name = "pm8150_l5_so"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + qcom,init-voltage = <880000>; + qcom,init-mode = ; + qcom,init-enable = <0>; + }; + }; + + rpmh-regulator-ldoa6 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L6A: pm8150_l6: regulator-pm8150-l6 { + regulator-name = "pm8150_l6"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa7 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L7A: pm8150_l7: regulator-pm8150-l7 { + regulator-name = "pm8150_l7"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + /* PM8150 L8 = VDD_SSC_CX supply */ + rpmh-regulator-lcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "lcx.lvl"; + L8A_LEVEL: pm8150_l8_level: regulator-pm8150-l8-level { + regulator-name = "pm8150_l8_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + rpmh-regulator-ldoa9 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L9A: pm8150_l9: regulator-pm8150-l9 { + regulator-name = "pm8150_l9"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa10 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L10A: pm8150_l10: regulator-pm8150-l10 { + regulator-name = "pm8150_l10"; + qcom,set = ; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <2504000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa11 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L11A: pm8150_l11: regulator-pm8150-l11 { + regulator-name = "pm8150_l11"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa12 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L12A: pm8150_l12: regulator-pm8150-l12 { + regulator-name = "pm8150_l12"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + + L12A_AO: pm8150_l12_ao: regulator-pm8150-l12-ao { + regulator-name = "pm8150_l12_ao"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + + regulator-pm8150-l12-so { + regulator-name = "pm8150_l12_so"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + qcom,init-enable = <0>; + }; + }; + + rpmh-regulator-ldoa13 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L13A: pm8150_l13: regulator-pm8150-l13 { + regulator-name = "pm8150_l13"; + qcom,set = ; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + qcom,init-voltage = <2704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa14 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa14"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + proxy-supply = <&pm8150_l14>; + L14A: pm8150_l14: regulator-pm8150-l14 { + regulator-name = "pm8150_l14"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1880000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <115000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa15 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa15"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L15A: pm8150_l15: regulator-pm8150-l15 { + regulator-name = "pm8150_l15"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1704000>; + qcom,init-voltage = <1704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa16 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L16A: pm8150_l16: regulator-pm8150-l16 { + regulator-name = "pm8150_l16"; + qcom,set = ; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <2704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa17 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L17A: pm8150_l17: regulator-pm8150-l17 { + regulator-name = "pm8150_l17"; + qcom,set = ; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + qcom,init-voltage = <2856000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoa18 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoa18"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L18A: pm8150_l18: regulator-pm8150-l18 { + regulator-name = "pm8150_l18"; + qcom,set = ; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + qcom,init-voltage = <880000>; + }; + }; + + rpmh-regulator-smpc1 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpc1"; + S1C: pm8150l_s1: regulator-pm8150l-s1 { + regulator-name = "pm8150l_s1"; + qcom,set = ; + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + qcom,init-voltage = <1128000>; + }; + }; + + /* PM8150L S2 + S3 = 2 phase VDD_GFX supply */ + rpmh-regulator-gfxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "gfx.lvl"; + S2C_LEVEL: pm8150l_s2_level: regulator-pm8150l-s2-level { + regulator-name = "pm8150l_s2_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + }; + + /* PM8150L S4 = VDD_MX supply */ + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "mx.lvl"; + + VDD_MX_LEVEL: S4C_LEVEL: + pm8150l_s4_level: regulator-pm8150l-s4-level { + regulator-name = "pm8150l_s4_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + VDD_MX_LEVEL_AO: S4C_LEVEL_AO: + pm8150l_s4_level_ao: regulator-pm8150l-s4-level-ao { + regulator-name = "pm8150l_s4_level_ao"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + mx_cdev: mx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&VDD_MX_LEVEL>; + regulator-levels = ; + #cooling-cells = <2>; + }; + }; + + /* PM8150L S5 = VDD_MM_CX supply */ + rpmh-regulator-mmcxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "mmcx.lvl"; + + VDD_MMCX_LEVEL: S5C_LEVEL: + pm8150l_s5_level: regulator-pm8150l-s5-level { + regulator-name = "pm8150l_s5_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + VDD_MMCX_LEVEL_AO: S5C_LEVEL_AO: + pm8150l_s5_level_ao: regulator-pm8150l-s5-level-ao { + regulator-name = "pm8150l_s5_level_ao"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + regulator-pm8150l-s5-level-so { + regulator-name = "pm8150l_s5_level_so"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + }; + + mm_cx_cdev: mm-cx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&VDD_MMCX_LEVEL_AO>; + regulator-levels = ; + #cooling-cells = <2>; + }; + }; + + /* PM8150L S6 + S7 = VDD_CX supply */ + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "cx.lvl"; + pm8150l_s6_level-parent-supply = <&VDD_MX_LEVEL>; + pm8150l_s6_level_ao-parent-supply = <&VDD_MX_LEVEL_AO>; + + VDD_CX_LEVEL: S6C_LEVEL: + pm8150l_s6_level: regulator-pm8150l-s6-level { + regulator-name = "pm8150l_s6_level"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + + VDD_CX_LEVEL_AO: S6C_LEVEL_AO: + pm8150l_s6_level_ao: regulator-pm8150l-s6-level-ao { + regulator-name = "pm8150l_s6_level_ao"; + qcom,set = ; + regulator-min-microvolt + = ; + regulator-max-microvolt + = ; + qcom,init-voltage-level + = ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + + cx_cdev: regulator-cdev { + compatible = "qcom,rpmh-reg-cdev"; + mboxes = <&qmp_aop 0>; + qcom,reg-resource-name = "cx"; + #cooling-cells = <2>; + }; + }; + + rpmh-regulator-smpc8 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpc8"; + S8C: pm8150l_s8: regulator-pm8150l-s8 { + regulator-name = "pm8150l_s8"; + qcom,set = ; + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + qcom,init-voltage = <1352000>; + }; + }; + + rpmh-regulator-ldoc1 { + compatible = "qcom,rpmh-xob-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc1"; + L1C: pm8150l_l1: regulator-pm8150l-l1 { + regulator-name = "pm8150l_l1"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + rpmh-regulator-ldoc2 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L2C: pm8150l_l2: regulator-pm8150l-l2 { + regulator-name = "pm8150l_l2"; + qcom,set = ; + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1304000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc3 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + proxy-supply = <&pm8150l_l3>; + L3C: pm8150l_l3: regulator-pm8150l-l3 { + regulator-name = "pm8150l_l3"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <51800>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc4 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L4C: pm8150l_l4: regulator-pm8150l-l4 { + regulator-name = "pm8150l_l4"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + qcom,init-voltage = <1704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc5 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L5C: pm8150l_l5: regulator-pm8150l-l5 { + regulator-name = "pm8150l_l5"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + qcom,init-voltage = <1704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc6 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L6C: pm8150l_l6: regulator-pm8150l-l6 { + regulator-name = "pm8150l_l6"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc7 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc7"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L7C: pm8150l_l7: regulator-pm8150l-l7 { + regulator-name = "pm8150l_l7"; + qcom,set = ; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + qcom,init-voltage = <2856000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc8 { + compatible = "qcom,rpmh-xob-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc8"; + L8C: pm8150l_l8: regulator-pm8150l-l8 { + regulator-name = "pm8150l_l8"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + rpmh-regulator-ldoc9 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L9C: pm8150l_l9: regulator-pm8150l-l9 { + regulator-name = "pm8150l_l9"; + qcom,set = ; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + qcom,init-voltage = <2704000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc10 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L10C: pm8150l_l10: regulator-pm8150l-l10 { + regulator-name = "pm8150l_l10"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldoc11 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldoc11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1>; + L11C: pm8150l_l11: regulator-pm8150l-l11 { + regulator-name = "pm8150l_l11"; + qcom,set = ; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + qcom,init-voltage = <3000000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-bobc1 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "bobc1"; + qcom,regulator-type = "pmic5-bob"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 1000000 2000000>; + qcom,send-defaults; + + BOB: pm8150l_bob: regulator-pm8150l-bob { + regulator-name = "pm8150l_bob"; + qcom,set = ; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <4000000>; + qcom,init-voltage = <3312000>; + qcom,init-mode = ; + }; + + BOB_AO: pm8150l_bob_ao: regulator-pm8150l-bob-ao { + regulator-name = "pm8150l_bob_ao"; + qcom,set = ; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <4000000>; + qcom,init-voltage = <3008000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-smpf2 { + compatible = "qcom,rpmh-xob-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "smpf2"; + S2F: pm8009_s2: regulator-pm8009-s2 { + regulator-name = "pm8009_s2"; + qcom,set = ; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <2856000>; + }; + }; + + rpmh-regulator-ldof2 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof2"; + L2F: pm8009_l2: regulator-pm8009-l2 { + regulator-name = "pm8009_l2"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + }; + + rpmh-regulator-ldof5 { + compatible = "qcom,rpmh-xob-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof5"; + L5F: pm8009_l5: regulator-pm8009-l5 { + regulator-name = "pm8009_l5"; + qcom,set = ; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + }; + + rpmh-regulator-ldof6 { + compatible = "qcom,rpmh-xob-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof6"; + L6F: pm8009_l6: regulator-pm8009-l6 { + regulator-name = "pm8009_l6"; + qcom,set = ; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <2856000>; + }; + }; + + rpmh-regulator-ldof1 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof1"; + L1F: pm8009_l1: regulator-pm8009-l1 { + regulator-name = "pm8009_l1"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + }; + + rpmh-regulator-ldof3 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof3"; + L3F: pm8009_l3: regulator-pm8009-l3 { + regulator-name = "pm8009_l3"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + }; + + rpmh-regulator-ldof4 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof4"; + L4F: pm8009_l4: regulator-pm8009-l4 { + regulator-name = "pm8009_l4"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + }; + + rpmh-regulator-ldof7 { + compatible = "qcom,rpmh-xob-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof7"; + L7F: pm8009_l7: regulator-pm8009-l7 { + regulator-name = "pm8009_l7"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + refgen: refgen-regulator@88e7000 { + compatible = "qcom,refgen-regulator"; + reg = <0x88e7000 0x60>; + regulator-name = "refgen"; + regulator-enable-ramp-delay = <5>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-rumi-overlay.dts b/arch/arm/boot/dts/qcom/sm8150-rumi-overlay.dts new file mode 100644 index 000000000000..b2f32817b7b6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-rumi-overlay.dts @@ -0,0 +1,27 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-rumi.dtsi" + +/ { + model = "RUMI"; + compatible = "qcom,sm8150-rumi", "qcom,sm8150", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-rumi.dts b/arch/arm/boot/dts/qcom/sm8150-rumi.dts new file mode 100644 index 000000000000..8fadf9cd9913 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-rumi.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/memreserve/ 0x90000000 0x00000100; + +#include "sm8150.dtsi" +#include "sm8150-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150 RUMI"; + compatible = "qcom,sm8150-rumi", "qcom,sm8150", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-rumi.dtsi b/arch/arm/boot/dts/qcom/sm8150-rumi.dtsi new file mode 100644 index 000000000000..99c291d9fb79 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-rumi.dtsi @@ -0,0 +1,163 @@ +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msm-audio-lpass.dtsi" +#include "sm8150-sde-display.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + + usb_emu_phy: usb_emu_phy@a720000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x0a720000 0x9500>, + <0x0a6f8800 0x100>; + reg-names = "base", "qcratch_base"; + + qcom,emu-init-seq = <0xfff0 0x4 + 0xfff3 0x4 + 0x40 0x4 + 0xfff3 0x4 + 0xfff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x1a0 0x20 + 0x100000 0x3c + 0x0 0x3c + 0x10060 0x3c + 0x0 0x4>; + }; + + timer { + clock-frequency = <95000>; + }; + + timer@0x17c00000 { + clock-frequency = <95000>; + }; + + qcom,icnss@18800000 { + compatible = "qcom,icnss"; + reg = <0x18800000 0x800000>; + reg-names = "membase"; + interrupts = <0 414 0 /* CE0 */ >, + <0 415 0 /* CE1 */ >, + <0 416 0 /* CE2 */ >, + <0 417 0 /* CE3 */ >, + <0 418 0 /* CE4 */ >, + <0 419 0 /* CE5 */ >, + <0 420 0 /* CE6 */ >, + <0 421 0 /* CE7 */ >, + <0 422 0 /* CE8 */ >, + <0 423 0 /* CE9 */ >, + <0 424 0 /* CE10 */ >, + <0 425 0 /* CE11 */ >; + qcom,wlan-msa-memory = <0x100000>; + }; + + wdog: qcom,wdt@17c10000{ + status = "disabled"; + }; + +}; + +&audio_apr { + sound-stub { + compatible = "qcom,sm8150-asoc-snd-stub"; + qcom,model = "sm8150-stub-snd-card"; + + qcom,audio-routing = + "AIF4 VI", "MCLK"; + + asoc-platform = <&pcm0>, <&routing>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-routing"; + asoc-cpu = <&sb_0_rx>, <&sb_0_tx>; + asoc-cpu-names = "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385"; + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + qcom,wsa-max-devs = <0>; + }; +}; + +#include "sm8150-pmic-overlay.dtsi" + +&VDD_MMCX_LEVEL { + regulator-always-on; +}; + +&qupv3_se12_2uart { + status = "ok"; +}; + +&usb0 { + extcon = <0>, <0>, <0>; + dwc3@a600000 { + usb-phy = <&usb_emu_phy>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + }; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qrbtc-sdm845"; + + vdda-phy-supply = <&pm8150_l5>; + vdda-pll-supply = <&pm8150_l3>; + vdda-phy-max-microamp = <87100>; + vdda-pll-max-microamp = <18800>; + + status = "ok"; +}; + +&ufshc_mem { + limit-tx-hs-gear = <1>; + limit-rx-hs-gear = <1>; + + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8150_l10>; + vccq2-supply = <&pm8150_s4>; + vcc-max-microamp = <750000>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&pm8150_l9>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,disable-lpm; + rpm-level = <0>; + spm-level = <0>; + status = "ok"; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sim_cmd_display { + qcom,dsi-display-active; +}; + +&slim_qca { + status = "disabled"; +}; + +&usb_qmp_dp_phy { + status = "disabled"; +}; + +&usb2_phy0 { + status = "disabled"; +}; +&ipa_hw { + qcom,ipa-hw-mode = <1>; /* IPA hw type = Virtual */ +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-sde-display.dtsi b/arch/arm/boot/dts/qcom/sm8150-sde-display.dtsi new file mode 100644 index 000000000000..5e6720c77084 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-sde-display.dtsi @@ -0,0 +1,949 @@ +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-sim-cmd.dtsi" +#include "dsi-panel-sim-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-video.dtsi" +#include "dsi-panel-sim-dualmipi-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" +#include "dsi-panel-sim-sec-hd-cmd.dtsi" +#include "dsi-panel-sharp-dsc-4k-video.dtsi" +#include "dsi-panel-sharp-dsc-4k-cmd.dtsi" +#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi" +#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi" +#include "dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi" +#include "dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi" +#include "dsi-panel-nt35695b-truly-fhd-video.dtsi" +#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi" +#include "dsi-panel-sharp-1080p-cmd.dtsi" +#include "dsi-panel-sharp-dualmipi-1080p-120hz.dtsi" +#include "dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi" +#include "dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi" +#include "dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi" +#include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi" +#include +#include "dsi-panel-samsung_oneplus_dsc.dtsi" +#include "dsi-panel-samsung_s6e3fc2x01.dtsi" +#include "dsi-panel-samsung_sofef00_m_video.dtsi" + + +&tlmm { + display_panel_avdd_eldo_default: display_panel_avdd_eldo_default { + mux { + pins = "gpio130"; + function = "gpio"; + }; + config { + pins = "gpio130"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; +}; + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_vdd_no_labibb: dsi_panel_pwr_supply_vdd_no_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <857000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + }; + + dsi_panel_pwr_supply_vdd_labibb: dsi_panel_pwr_supply_vdd_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <857000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <1>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <5200000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@3 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <800000>; + qcom,supply-max-voltage = <5400000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + display_panel_avdd_eldo: display-gpio-regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "display_panel_avdd_eldo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <233>; +// gpio = <&tlmm 130 0>; + enable-active-high; + regulator-boot-on; + pinctrl-names = "default"; + pintctrl-0 = <&display_panel_avdd_eldo_default>; + }; + + dsi_sharp_4k_dsc_video_display: qcom,dsi-display@0 { + label = "dsi_sharp_4k_dsc_video_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sharp_4k_dsc_video>; + }; + + dsi_sharp_4k_dsc_cmd_display: qcom,dsi-display@1 { + label = "dsi_sharp_4k_dsc_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sharp_4k_dsc_cmd>; + }; + + dsi_sharp_1080_cmd_display: qcom,dsi-display@2 { + label = "dsi_sharp_1080_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sharp_1080_cmd>; + }; + + dsi_dual_sharp_1080_120hz_cmd_display: qcom,dsi-display@3 { + label = "dsi_dual_sharp_1080_120hz_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_dual_sharp_1080_120hz_cmd>; + }; + + dsi_dual_nt35597_truly_video_display: qcom,dsi-display@4 { + label = "dsi_dual_nt35597_truly_video_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_dual_nt35597_truly_video>; + }; + + dsi_dual_nt35597_truly_cmd_display: qcom,dsi-display@5 { + label = "dsi_dual_nt35597_truly_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_dual_nt35597_truly_cmd>; + }; + + dsi_nt35597_truly_dsc_cmd_display: qcom,dsi-display@6 { + label = "dsi_nt35597_truly_dsc_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <1>; + qcom,dsi-phy-num = <1>; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,dsi-panel = <&dsi_nt35597_truly_dsc_cmd>; + }; + + dsi_nt35597_truly_dsc_video_display: qcom,dsi-display@7 { + label = "dsi_nt35597_truly_dsc_video_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <1>; + qcom,dsi-phy-num = <1>; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,dsi-panel = <&dsi_nt35597_truly_dsc_video>; + }; + + dsi_sim_vid_display: qcom,dsi-display@8 { + label = "dsi_sim_vid_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sim_vid>; + }; + + dsi_dual_sim_vid_display: qcom,dsi-display@9 { + label = "dsi_dual_sim_vid_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_dual_sim_vid>; + }; + + dsi_sim_cmd_display: qcom,dsi-display@10 { + label = "dsi_sim_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sim_cmd>; + }; + + dsi_dual_sim_cmd_display: qcom,dsi-display@11 { + label = "dsi_dual_sim_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_dual_sim_cmd>; + }; + + dsi_sim_dsc_375_cmd_display: qcom,dsi-display@12 { + label = "dsi_sim_dsc_375_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sim_dsc_375_cmd>; + }; + + dsi_dual_sim_dsc_375_cmd_display: qcom,dsi-display@13 { + label = "dsi_dual_sim_dsc_375_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_dual_sim_dsc_375_cmd>; + }; + + dsi_sw43404_amoled_cmd_display: qcom,dsi-display@14 { + label = "dsi_sw43404_amoled_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sw43404_amoled_cmd>; + }; + + dsi_nt35695b_truly_fhd_cmd_display: qcom,dsi-display@15 { + label = "dsi_nt35695b_truly_fhd_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_cmd>; + + }; + + dsi_nt35695b_truly_fhd_video_display: qcom,dsi-display@16 { + label = "dsi_nt35695b_truly_fhd_video_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_video>; + }; + + dsi_sw43404_amoled_video_display: qcom,dsi-display@17 { + label = "dsi_sw43404_amoled_video_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sw43404_amoled_video>; + }; + + dsi_sw43404_amoled_fhd_plus_cmd_display: qcom,dsi-display@18 { + label = "dsi_sw43404_amoled_fhd_plus_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sw43404_amoled_fhd_plus_cmd>; + }; + + dsi_dual_nt36850_truly_cmd_display: qcom,dsi-display@19 { + label = "dsi_dual_nt36850_truly_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_dual_nt36850_truly_cmd>; + }; + + dsi_nt35695b_truly_fhd_cmd_sec_display: qcom,dsi-display@20 { + label = "dsi_nt35695b_truly_fhd_cmd_display"; + qcom,display-type = "secondary"; + + qcom,dsi-ctrl-num = <1>; + qcom,dsi-phy-num = <1>; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_cmd>; + + }; + + dsi_nt35695b_truly_fhd_video_sec_display: qcom,dsi-display@21 { + label = "dsi_nt35695b_truly_fhd_video_display"; + qcom,display-type = "secondary"; + + qcom,dsi-ctrl-num = <1>; + qcom,dsi-phy-num = <1>; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_video>; + }; + + dsi_sim_sec_hd_cmd_display: qcom,dsi-display@22 { + + label = "dsi_sim_sec_hd_cmd_display"; + qcom,display-type = "secondary"; + + qcom,dsi-ctrl-num = <1>; + qcom,dsi-phy-num = <1>; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; + + qcom,dsi-panel = <&dsi_sim_sec_hd_cmd>; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, + <&mdss_dsi0_pll PCLK_MUX_0_CLK>, + <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, + <&mdss_dsi1_pll PCLK_MUX_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,panel-te-source = <0>; + + vddio-supply = <&pm8150_l14>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + vdd-supply = <&display_panel_avdd_eldo>; + + qcom,dsi-display-list = + <&dsi_sharp_4k_dsc_video_display + &dsi_sharp_4k_dsc_cmd_display + &dsi_sharp_1080_cmd_display + &dsi_dual_sharp_1080_120hz_cmd_display + &dsi_dual_nt35597_truly_video_display + &dsi_dual_nt35597_truly_cmd_display + &dsi_nt35597_truly_dsc_cmd_display + &dsi_nt35597_truly_dsc_video_display + &dsi_sim_vid_display + &dsi_dual_sim_vid_display + &dsi_sim_cmd_display + &dsi_dual_sim_cmd_display + &dsi_sim_dsc_375_cmd_display + &dsi_dual_sim_dsc_375_cmd_display + &dsi_sw43404_amoled_cmd_display + &dsi_nt35695b_truly_fhd_cmd_display + &dsi_nt35695b_truly_fhd_video_display + &dsi_sw43404_amoled_video_display + &dsi_sw43404_amoled_fhd_plus_cmd_display + &dsi_dual_nt36850_truly_cmd_display>; + }; + + sde_dsi1: qcom,dsi-display-secondary { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, + <&mdss_dsi0_pll PCLK_MUX_0_CLK>, + <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, + <&mdss_dsi1_pll PCLK_MUX_1_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1"; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; + pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; + + qcom,platform-te-gpio = <&tlmm 9 0>; + qcom,panel-te-source = <1>; + + vddio-supply = <&pm8150_l14>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + vdd-supply = <&display_panel_avdd_eldo>; + + qcom,dsi-display-list = + <&dsi_nt35695b_truly_fhd_cmd_sec_display + &dsi_nt35695b_truly_fhd_video_sec_display + &dsi_sim_sec_hd_cmd_display>; + }; + + sde_wb: qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display"; + }; + + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; +}; + +&sde_dp { + qcom,dp-usbpd-detection = <&pm8150b_pdphy>; + qcom,ext-disp = <&ext_disp>; + qcom,dp-aux-switch = <&fsa4480>; + + qcom,usbplug-cc-gpio = <&tlmm 38 0>; + + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; + pinctrl-0 = <&sde_dp_usbplug_cc_active>; + pinctrl-1 = <&sde_dp_usbplug_cc_suspend>; +}; + +&mdss_mdp { + connectors = <&sde_rscc &sde_wb &sde_dp &sde_dsi &sde_dsi1>; +}; + +/* PHY TIMINGS REVISION T */ +&dsi_dual_nt35597_truly_video { + qcom,dsi-supported-dfps-list = <60 55 53>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt35597_truly_dsc_cmd { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05 + 05 03 02 04 00 12 15]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + }; +}; + +&dsi_nt35597_truly_dsc_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05 + 05 03 02 04 00 12 15]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + }; +}; + +&dsi_sharp_4k_dsc_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x77>; + qcom,mdss-dsi-panel-on-check-value = <0x77>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-qsync-min-refresh-rate = <55>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 02 04 00 19 18]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x77>; + qcom,mdss-dsi-panel-on-check-value = <0x77>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 02 04 00 19 18]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt35695b_truly_fhd_video { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 + 08 08 05 02 04 00 19 17]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt35695b_truly_fhd_cmd { + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 + 08 08 05 02 04 00 19 17]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_sec_hd_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 + 08 08 05 02 04 00 19 17]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; + +&dsi_dual_sharp_1080_120hz_cmd { + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09 + 09 06 02 04 00]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_1080_cmd { + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1E 08 08 24 22 08 + 08 05 02 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + qcom,mdss-dsi-panel-clockrate = <900000000>; + }; + }; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 0 1>, + <2 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_vid { + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@1{ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <540 40 540 40 540 40>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@2{ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment = <360 40 360 40 360 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; + +&dsi_dual_sim_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09 + 09 06 02 04 00 18 17]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + timing@1{ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + timing@2{ + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 02 04 00 19 18]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { /* 1080p */ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + timing@1 { /* qhd */ + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 02 04 00 19 18]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { /* qhd */ + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07 + 07 05 02 04 00 18 17]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + timing@1 { /* 4k */ + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08 + 08 05 02 04 00 19 18]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sw43404_amoled_cmd { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 20 1f 06 + 06 03 03 04 00 13 15]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sw43404_amoled_fhd_plus_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 1e 1e 04 + 05 02 03 04 00 11 14]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sw43404_amoled_video { + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 22 21 07 + 07 04 02 04 00 16 16]; + /*qcom,mdss-dsi-panel-clockrate = <700000000>;*/ + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_1080_cmd { + qcom,mdss-dsi-t-clk-post = <0x18>; + qcom,mdss-dsi-t-clk-pre = <0x19>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07 + 07 04 03 04 00 16 16]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_nt36850_truly_cmd { + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 1f 08 08 24 23 08 + 08 05 03 04 00 1a 18]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + qcom,mdss-mdp-transfer-time-us = <16700>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/qcom/sm8150-sde-pll.dtsi b/arch/arm/boot/dts/qcom/sm8150-sde-pll.dtsi new file mode 100644 index 000000000000..eb4318423ae7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-sde-pll.dtsi @@ -0,0 +1,96 @@ +/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + mdss_dsi0_pll: qcom,mdss_dsi_pll@ae94900 { + compatible = "qcom,mdss_dsi_pll_7nm"; + label = "MDSS DSI 0 PLL"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae94900 0x260>, + <0xae94400 0x800>, + <0xaf03000 0x8>; + reg-names = "pll_base", "phy_base", "gdsc_base"; + clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + clock-rate = <0>; + gdsc-supply = <&mdss_core_gdsc>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1_pll: qcom,mdss_dsi_pll@ae96900 { + compatible = "qcom,mdss_dsi_pll_7nm"; + label = "MDSS DSI 1 PLL"; + cell-index = <1>; + #clock-cells = <1>; + reg = <0xae96900 0x260>, + <0xae96400 0x800>, + <0xaf03000 0x8>; + reg-names = "pll_base", "phy_base", "gdsc_base"; + clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + clock-rate = <0>; + gdsc-supply = <&mdss_core_gdsc>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dp_pll: qcom,mdss_dp_pll@c011000 { + compatible = "qcom,mdss_dp_pll_7nm"; + label = "MDSS DP PLL"; + cell-index = <0>; + #clock-cells = <1>; + + reg = <0x088ea000 0x200>, + <0x088eaa00 0x200>, + <0x088ea200 0x200>, + <0x088ea600 0x200>, + <0xaf03000 0x8>; + reg-names = "pll_base", "phy_base", "ln_tx0_base", + "ln_tx1_base", "gdsc_base"; + + clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_DISP_AHB_CLK>, + <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "iface_clk", "ref_clk_src", "gcc_iface", + "ref_clk", "pipe_clk"; + clock-rate = <0>; + }; + +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-sde.dtsi b/arch/arm/boot/dts/qcom/sm8150-sde.dtsi new file mode 100644 index 000000000000..4d3fdfb0c5a2 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-sde.dtsi @@ -0,0 +1,691 @@ +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + compatible = "qcom,sde-kms"; + reg = <0x0ae00000 0x84208>, + <0x0aeb0000 0x2008>, + <0x0aeac000 0x214>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys"; + + clocks = + <&clock_gcc GCC_DISP_AHB_CLK>, + <&clock_gcc GCC_DISP_HF_AXI_CLK>, + <&clock_gcc GCC_DISP_SF_AXI_CLK>, + <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, + <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk", "rot_clk"; + clock-rate = <0 0 0 0 300000000 19200000 300000000 19200000>; + clock-max-rate = <0 0 0 0 460000000 19200000 460000000 + 460000000>; + + sde-vdd-supply = <&mdss_core_gdsc>; + mmcx-supply = <&VDD_MMCX_LEVEL>; + + /* interrupt config */ + interrupts = <0 83 0>; + interrupt-controller; + #interrupt-cells = <1>; + iommus = <&apps_smmu 0x800 0x420>; + + #address-cells = <1>; + #size-cells = <0>; + + #power-domain-cells = <0>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x45c>; + + qcom,sde-ctl-off = <0x2000 0x2200 0x2400 + 0x2600 0x2800 0x2a00>; + qcom,sde-ctl-size = <0x1e0>; + qcom,sde-ctl-display-pref = "primary", "none", "none", + "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 + 0x48000 0x49000 0x4a000>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none", "none", "none"; + + qcom,sde-mixer-cwb-pref = "none", "none", "cwb", + "cwb", "cwb", "cwb"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dest-scaler-top-off = <0x00061000>; + qcom,sde-dest-scaler-top-size = <0x1c>; + qcom,sde-dest-scaler-off = <0x800 0x1000>; + qcom,sde-dest-scaler-size = <0xa0>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x3b8 24>; + + qcom,sde-intf-off = <0x6b000 0x6b800 + 0x6c000 0x6c800>; + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + + qcom,sde-pp-off = <0x71000 0x71800 + 0x72000 0x72800 0x73000 0x73800>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0>; + qcom,sde-pp-size = <0xd4>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2>; + + qcom,sde-merge-3d-off = <0x84000 0x84100 0x84200>; + qcom,sde-merge-3d-size = <0x100>; + + qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0 0x0 0x0>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + qcom,sde-dsc-off = <0x81000 0x81400 0x81800 0x81c00>; + qcom,sde-dsc-size = <0x140>; + + qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 + 0x30e0 0x30e0 0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "vig", "vig", "vig", + "dma", "dma", "dma", "dma"; + + qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 + 0x25000 0x27000 0x29000 0x2b000>; + qcom,sde-sspp-src-size = <0x1f0>; + + qcom,sde-sspp-xin-id = <0 4 8 12 + 1 5 9 13>; + qcom,sde-sspp-excl-rect = <1 1 1 1 + 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3 6 5>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-max-per-pipe-bw-kbps = <4500000 4500000 + 4500000 4500000 + 4500000 4500000 + 4500000 4500000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>, + <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-type = "qseedv3"; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <4096>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-mixer-blendstages = <0xb>; + qcom,sde-highest-bank-bit = <0x2>; + qcom,sde-ubwc-version = <0x300>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-idle-pc; + qcom,sde-has-dest-scaler; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-max-bw-low-kbps = <12800000>; + qcom,sde-max-bw-high-kbps = <12800000>; + qcom,sde-min-core-ib-kbps = <2400000>; + qcom,sde-min-llcc-ib-kbps = <800000>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + qcom,sde-dspp-ad-version = <0x00040000>; + qcom,sde-dspp-ad-off = <0x28000 0x27000>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1040>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + + /* macrotile & macrotile-qseed has the same configs */ + qcom,sde-danger-lut = <0x0000000f 0x0000ffff + 0x00000000 0x00000000 0x0000ffff>; + + qcom,sde-safe-lut-linear = <0 0xfff8>; + qcom,sde-safe-lut-macrotile = <0 0xf000>; + /* same as safe-lut-macrotile */ + qcom,sde-safe-lut-macrotile-qseed = <0 0xf000>; + qcom,sde-safe-lut-nrt = <0 0xffff>; + qcom,sde-safe-lut-cwb = <0 0xffff>; + + qcom,sde-qos-lut-linear = <0 0x00112222 0x22223357>; + qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>; + qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>; + qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>; + qcom,sde-qos-lut-cwb = <0 0x75300000 0x00000000>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <44>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + + qcom,sde-reg-dma-off = <0>; + qcom,sde-reg-dma-version = <0x00010001>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + + qcom,sde-secure-sid-mask = <0x4200801>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + qcom,sde-vig-gamut = <0x1d00 0x00050000>; + qcom,sde-vig-igc = <0x1d00 0x00050000>; + qcom,sde-vig-inverse-pma; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + qcom,sde-dma-igc = <0x400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x200>; + }; + dgm@1 { + qcom,sde-dma-igc = <0x1400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1200>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040001>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "mmcx"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x801 0x420>; + }; + + /* data and reg bus scale settings */ + qcom,sde-data-bus { + qcom,msm-bus,name = "mdss_sde"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, <23 512 0 0>, + <22 512 0 6400000>, <23 512 0 6400000>, + <22 512 0 6400000>, <23 512 0 6400000>; + }; + + qcom,sde-reg-bus { + qcom,msm-bus,name = "mdss_reg"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 590 0 0>, + <1 590 0 76800>, + <1 590 0 150000>, + <1 590 0 300000>; + }; + }; + + sde_rscc: qcom,sde_rscc@af20000 { + cell-index = <0>; + compatible = "qcom,sde-rsc"; + reg = <0xaf20000 0x1c44>, + <0xaf30000 0x3fd4>; + reg-names = "drv", "wrapper"; + qcom,sde-rsc-version = <2>; + + vdd-supply = <&mdss_core_gdsc>; + clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>, + <&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>; + clock-names = "vsync_clk", "gdsc_clk", "iface_clk"; + clock-rate = <0 0 0>; + + qcom,sde-dram-channels = <2>; + + mboxes = <&disp_rsc 0>; + mbox-names = "disp_rsc"; + + /* data and reg bus scale settings */ + qcom,sde-data-bus { + qcom,msm-bus,name = "disp_rsc_mnoc"; + qcom,msm-bus,active-only; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <20003 20515 0 0>, <20004 20515 0 0>, + <20003 20515 0 6400000>, <20004 20515 0 6400000>, + <20003 20515 0 6400000>, <20004 20515 0 6400000>; + }; + + qcom,sde-llcc-bus { + qcom,msm-bus,name = "disp_rsc_llcc"; + qcom,msm-bus,active-only; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <20001 20513 0 0>, + <20001 20513 0 6400000>, + <20001 20513 0 6400000>; + }; + + qcom,sde-ebi-bus { + qcom,msm-bus,name = "disp_rsc_ebi"; + qcom,msm-bus,active-only; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <20000 20512 0 0>, + <20000 20512 0 6400000>, + <20000 20512 0 6400000>; + }; + }; + + mdss_rotator: qcom,mdss_rotator@ae00000 { + compatible = "qcom,sde_rotator"; + reg = <0x0ae00000 0xac000>, + <0x0aeb8000 0x3000>; + reg-names = "mdp_phys", + "rot_vbif_phys"; + + #list-cells = <1>; + + qcom,mdss-rot-mode = <1>; + qcom,mdss-highest-bank-bit = <0x2>; + + /* Bus Scale Settings */ + qcom,msm-bus,name = "mdss_rotator"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <25 512 0 0>, + <25 512 0 6400000>, + <25 512 0 6400000>; + + rot-vdd-supply = <&mdss_core_gdsc>; + qcom,supply-names = "rot-vdd"; + + clocks = + <&clock_gcc GCC_DISP_AHB_CLK>, + <&clock_gcc GCC_DISP_SF_AXI_CLK>, + <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", + "iface_clk", "rot_clk"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <2 0>; + + power-domains = <&mdss_mdp>; + + /* Offline rotator QoS setting */ + qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>; + qcom,mdss-rot-vbif-memtype = <3 3>; + qcom,mdss-rot-cdp-setting = <1 1>; + qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>; + qcom,mdss-rot-danger-lut = <0x0 0x0>; + qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>; + + qcom,mdss-default-ot-rd-limit = <32>; + qcom,mdss-default-ot-wr-limit = <32>; + + qcom,mdss-sbuf-headroom = <20>; + + cache-slice-names = "rotator"; + cache-slices = <&llcc 4>; + + /* reg bus scale settings */ + rot_reg: qcom,rot-reg-bus { + qcom,msm-bus,name = "mdss_rot_reg"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 590 0 0>, + <1 590 0 76800>; + }; + + smmu_rot_unsec: qcom,smmu_rot_unsec_cb { + compatible = "qcom,smmu_sde_rot_unsec"; + iommus = <&apps_smmu 0x1040 0x0>; + }; + + smmu_rot_sec: qcom,smmu_rot_sec_cb { + compatible = "qcom,smmu_sde_rot_sec"; + iommus = <&apps_smmu 0x1041 0x0>; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.3"; + label = "dsi-ctrl-0"; + cell-index = <0>; + reg = <0xae94000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + vdda-1p2-supply = <&pm8150l_l3>; + clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", + "esc_clk"; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.3"; + label = "dsi-ctrl-1"; + cell-index = <1>; + reg = <0xae96000 0x400>, + <0xaf08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <5 0>; + vdda-1p2-supply = <&pm8150l_l3>; + clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 { + compatible = "qcom,dsi-phy-v4.0"; + label = "dsi-phy-0"; + cell-index = <0>; + reg = <0xae94400 0x760>; + reg-names = "dsi_phy"; + vdda-0p9-supply = <&pm8150_l5>; + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <36000>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy1: qcom,mdss_dsi_phy0@ae96400 { + compatible = "qcom,dsi-phy-v4.0"; + label = "dsi-phy-1"; + cell-index = <1>; + reg = <0xae96400 0x760>; + reg-names = "dsi_phy"; + vdda-0p9-supply = <&pm8150_l5>; + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <36000>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + sde_dp: qcom,dp_display@0{ + cell-index = <0>; + compatible = "qcom,dp-display"; + + vdda-1p2-supply = <&pm8150l_l3>; + vdda-0p9-supply = <&pm8150_l5>; + + reg = <0xae90000 0x0dc>, + <0xae90200 0x0c0>, + <0xae90400 0x508>, + <0xae90a00 0x094>, + <0x88eaa00 0x200>, + <0x88ea200 0x200>, + <0x88ea600 0x200>, + <0xaf02000 0x1a0>, + <0x780000 0x621c>, + <0x88ea040 0x10>, + <0x88e8000 0x20>, + <0x0aee1000 0x034>, + <0xae91000 0x094>; + /* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */ + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_mmss_cc", "qfprom_physical", "dp_pll", + "usb3_dp_com", "hdcp_physical", "dp_p1"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, + <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + clock-names = "core_aux_clk", "core_usb_ref_clk_src", + "core_usb_ref_clk", "core_usb_pipe_clk", + "link_clk", "link_iface_clk", + "crypto_clk", "pixel_clk_rcg", "pixel_parent", + "pixel1_clk_rcg", "pixel1_parent", + "strm0_pixel_clk", "strm1_pixel_clk"; + + qcom,phy-version = <0x420>; + qcom,aux-cfg0-settings = [20 00]; + qcom,aux-cfg1-settings = [24 13]; + qcom,aux-cfg2-settings = [28 24]; + qcom,aux-cfg3-settings = [2c 00]; + qcom,aux-cfg4-settings = [30 0a]; + qcom,aux-cfg5-settings = [34 26]; + qcom,aux-cfg6-settings = [38 0a]; + qcom,aux-cfg7-settings = [3c 03]; + qcom,aux-cfg8-settings = [40 b7]; + qcom,aux-cfg9-settings = [44 03]; + + qcom,max-pclk-frequency-khz = <675000>; + + qcom,mst-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; + qcom,max-dp-dsc-blks = <2>; + qcom,max-dp-dsc-input-width-pixs = <2048>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <36000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-sdx50-camera-sensor-qrd.dtsi b/arch/arm/boot/dts/qcom/sm8150-sdx50-camera-sensor-qrd.dtsi new file mode 100644 index 000000000000..174d572515b9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-sdx50-camera-sensor-qrd.dtsi @@ -0,0 +1,415 @@ +/* + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + #address-cells = <1>; + #size-cells = <1>; + + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_iris: qcom,camera-flash@3 { + cell-index = <3>; + reg = <0x03 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash1>; + torch-source = <&pm8150l_torch1>; + switch-source = <&pm8150l_switch0>; + status = "ok"; + }; +}; + +&cam_cci0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; + camera_vaf_ldo: camera-vaf-regulator { + compatible = "regulator-fixed"; + regulator-name = "camera_vaf_ldo"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-enable-ramp-delay = <135>; //Check + enable-active-high; + gpio = <&tlmm 29 0>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_vaf_en_default>; + vin-supply = <&pm8150l_bob>; + }; + + camera_vana_ldo: camera-vana-regulator { + compatible = "regulator-fixed"; + regulator-name = "camera_vana_ldo"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-enable-ramp-delay = <135>; // Check + enable-active-high; + gpio = <&tlmm 11 0>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_vana_en_default>; + vin-supply = <&pm8150l_bob>; + }; + + camera_vana2_ldo: camera-vana2-regulator { + compatible = "regulator-fixed"; + regulator-name = "camera_vana2_ldo"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-enable-ramp-delay = <135>; // Check + enable-active-high; + gpio = <&pm8150l_gpios 4 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_sensor_eldo4_default>; + vin-supply = <&pm8150l_bob>; + }; + + camera_vdd_ldo: camera-vdd-regulator { + compatible = "regulator-fixed"; + regulator-name = "camera_vdd_ldo"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <135>; // Check + enable-active-high; + gpio = <&pm8150l_gpios 3 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_sensor_eldo3_default>; + vin-supply = <&pm8150l_s8>; + }; + + overlay_actuator_rear: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&camera_vaf_ldo>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2850000>; + rgltr-max-voltage = <2850000>; + rgltr-load-current = <0>; + }; + + overlay_actuator_rear_aux: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&camera_vaf_ldo>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2850000>; + rgltr-max-voltage = <2850000>; + rgltr-load-current = <0>; + }; + + overlay_ois_rear: qcom,ois@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,ois"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&camera_vaf_ldo>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2850000>; + rgltr-max-voltage = <2850000>; + rgltr-load-current = <0>; + status = "ok"; + }; + + overlay_eeprom_rear: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&camera_vana_ldo>; + cam_vdig-supply = <&camera_vdd_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2850000 1200000 0>; + rgltr-max-voltage = <0 2850000 1200000 0>; + rgltr-load-current = <0 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-position = <0>; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + overlay_eeprom_rear_aux: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vdig-supply = <&camera_vdd_ldo>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&camera_vana2_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2850000 1200000 0>; + rgltr-max-voltage = <0 2850000 1200000 0>; + rgltr-load-current = <0 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + overlay_qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&overlay_actuator_rear>; + ois-src = <&overlay_ois_rear>; + eeprom-src = <&overlay_eeprom_rear>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&camera_vana_ldo>; + cam_vdig-supply = <&camera_vdd_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2850000 1200000 0>; + rgltr-max-voltage = <0 2850000 1200000 0>; + rgltr-load-current = <0 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + overlay_qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&overlay_actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&overlay_eeprom_rear_aux>; + cam_vdig-supply = <&camera_vdd_ldo>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&camera_vana2_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2850000 1200000 0>; + rgltr-max-voltage = <0 2850000 1200000 0>; + rgltr-load-current = <0 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; + +&cam_cci1 { + #address-cells = <1>; + #size-cells = <0>; + overlay_actuator_front: qcom,actuator@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,actuator"; + cci-device = <1>; + cci-master = <0>; + cam_vaf-supply = <&camera_vaf_ldo>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2850000>; + rgltr-max-voltage = <2850000>; + rgltr-load-current = <0>; + }; + overlay_eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&camera_vana2_ldo>; + cam_vdig-supply = <&camera_vdd_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2850000 1200000 0>; + rgltr-max-voltage = <0 2850000 1200000 0>; + rgltr-load-current = <0 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-position = <1>; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + overlay_qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&overlay_eeprom_front>; + actuator-src = <&overlay_actuator_front>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&camera_vana2_ldo>; + cam_vdig-supply = <&camera_vdd_ldo>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2850000 1200000 0>; + rgltr-max-voltage = <0 2850000 1200000 0>; + rgltr-load-current = <0 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-sdx50m-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/sm8150-sdx50m-audio-overlay.dtsi new file mode 100644 index 000000000000..eba5354ca883 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-sdx50m-audio-overlay.dtsi @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm8150-qrd-audio-overlay.dtsi" + +&snd_934x { + qcom,msm-mbhc-usbc-audio-supported = <1>; + qcom,msm-mbhc-hphl-swh = <0>; + qcom,msm-mbhc-gnd-swh = <0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-sdx50m-cdp-overlay.dts b/arch/arm/boot/dts/qcom/sm8150-sdx50m-cdp-overlay.dts new file mode 100644 index 000000000000..5a76be032547 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-sdx50m-cdp-overlay.dts @@ -0,0 +1,31 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-cdp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-cdp-audio-overlay.dtsi" + +/ { + model = "SDX50M CDP"; + compatible = "qcom,sm8150-cdp", "qcom,sm8150", "qcom,cdp"; + qcom,board-id = <1 1>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-sdx50m-mtp-2.5k-panel-overlay.dts b/arch/arm/boot/dts/qcom/sm8150-sdx50m-mtp-2.5k-panel-overlay.dts new file mode 100644 index 000000000000..8020e287fc53 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-sdx50m-mtp-2.5k-panel-overlay.dts @@ -0,0 +1,66 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +/ { + model = "SDX50M 2.5k panel MTP"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010108 0x1>; +}; + +&dsi_sharp_4k_dsc_cmd_display { + /delete-property/ qcom,dsi-display-active; +}; + +&dsi_dual_nt35597_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_dual_nt35597_truly_cmd_display { + qcom,dsi-display-active; +}; + +&pm8150l_wled { + qcom,string-cfg = <6>; + qcom,leds-per-string = <8>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-sdx50m-mtp-overlay.dts b/arch/arm/boot/dts/qcom/sm8150-sdx50m-mtp-overlay.dts new file mode 100644 index 000000000000..fb74f162754f --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-sdx50m-mtp-overlay.dts @@ -0,0 +1,31 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +/ { + model = "SDX50M MTP"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-sdx50m-qrd-overlay.dts b/arch/arm/boot/dts/qcom/sm8150-sdx50m-qrd-overlay.dts new file mode 100644 index 000000000000..b4d2424cc63f --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-sdx50m-qrd-overlay.dts @@ -0,0 +1,32 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-sdx50m-qrd.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-sdx50m-audio-overlay.dtsi" + +/ { + model = "SDX50M QRD"; + compatible = "qcom,sm8150-qrd", "qcom,sm8150", "qcom,qrd"; + qcom,board-id = <11 1>; +}; + diff --git a/arch/arm/boot/dts/qcom/sm8150-sdx50m-qrd.dtsi b/arch/arm/boot/dts/qcom/sm8150-sdx50m-qrd.dtsi new file mode 100644 index 000000000000..187a93fea2a2 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-sdx50m-qrd.dtsi @@ -0,0 +1,733 @@ +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "sm8150-pmic-overlay.dtsi" +#include "sm8150-sde-display.dtsi" +#include "sm8150-sdx50-camera-sensor-qrd.dtsi" +#include "sm8150-thermal-overlay.dtsi" + +&qupv3_se4_i2c { +#include "smb1390.dtsi" +#include "smb1355.dtsi" +}; + +&vendor { + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-core-supply = <&pm8150_l7>; + qca,bt-vdd-pa-supply = <&pm8150l_l2>; + qca,bt-vdd-ldo-supply = <&pm8150l_l11>; + + qca,bt-vdd-core-voltage-level = <1800000 1800000>; + qca,bt-vdd-pa-voltage-level = <1304000 1304000>; + qca,bt-vdd-ldo-voltage-level = <3312000 3312000>; + + qca,bt-vdd-core-current-level = <0>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <0>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <0>; /* LPM/PFM */ + }; + + fusion_qrd_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "fg-gen4-batterydata-alium-3600mah.dtsi" + }; +}; + +&pm8150b_fg { + qcom,battery-data = <&fusion_qrd_batterydata>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-wt-enable; + /* ESR fast calibration */ + qcom,fg-esr-timer-chg-fast = <0 7>; + qcom,fg-esr-timer-dischg-fast = <0 7>; + qcom,fg-esr-timer-chg-slow = <0 96>; + qcom,fg-esr-timer-dischg-slow = <0 96>; + qcom,fg-esr-cal-soc-thresh = <26 230>; + qcom,fg-esr-cal-temp-thresh = <10 40>; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; + + qcom,qbt1000 { + compatible = "qcom,qbt1000"; + clock-names = "core", "iface"; + clock-frequency = <25000000>; + qcom,ipc-gpio = <&tlmm 118 0>; + pinctrl-names = "default"; + pinctrl-0 = <&key_home_default>; + qcom,finger-detect-gpio = <&pm8150_gpios 1 0>; + }; +}; + +&qupv3_se17_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + + st_fts@49 { + compatible = "st,fts"; + reg = <0x49>; + interrupt-parent = <&tlmm>; + interrupts = <122 0x2008>; + vdd-supply = <&pm8150_s4>; + avdd-supply = <&pm8150_l17>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + st,irq-gpio = <&tlmm 122 0x2008>; + st,reset-gpio = <&tlmm 54 0x00>; + st,regulator_dvdd = "vdd"; + st,regulator_avdd = "avdd"; + }; +}; + +&qupv3_se9_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 47 0x00>; + qcom,nq-ven = <&tlmm 41 0x00>; + qcom,nq-firm = <&tlmm 48 0x00>; + qcom,nq-clkreq = <&tlmm 113 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <47 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active + &nfc_clk_req_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend + &nfc_clk_req_suspend>; + }; +}; + +&dsi_panel_pwr_supply_vdd_no_labibb { + qcom,panel-supply-entry@1 { + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + }; +}; + +&dsi_sw43404_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_vdd_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sw43404_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_vdd_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sw43404_amoled_fhd_plus_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_vdd_no_labibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-mode-gpio = <&tlmm 7 0>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&dsi_sw43404_amoled_cmd_display { + qcom,dsi-display-active; +}; + +&sde_dsi { + vdd-supply = <&display_panel_avdd_eldo>; +}; + +&qupv3_se12_2uart { + status = "ok"; +}; + +&qupv3_se13_4uart { + status = "ok"; +}; + +&qupv3_se3_spi { + status = "ok"; +}; + +&qupv3_se4_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "ok"; + redriver@19 { + compatible = "onnn,redriver"; + reg = <0x19>; + extcon = <&pm8150b_pdphy>, <&pm8150b_pdphy>; + eq = /bits/ 8 <0x4 0x4 0x4 0x4>; + flat-gain = /bits/ 8 <0x3 0x1 0x1 0x3>; + output-comp = /bits/ 8 <0x3 0x3 0x3 0x3>; + loss-match = /bits/ 8 <0x1 0x3 0x3 0x1>; + }; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4"; + + vdda-phy-supply = <&pm8150_l5>; + vdda-pll-supply = <&pm8150l_l3>; + vdda-phy-max-microamp = <90200>; + vdda-pll-max-microamp = <19000>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8150_l10>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm8150_s4>; + vcc-max-microamp = <750000>; + vccq2-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&pm8150_l9>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm8150l_l9>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8150l_l6>; + qcom,vdd-io-voltage-level = <1808000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>; + + cd-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + + status = "ok"; +}; + +&pm8150b_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + wp_therm { + reg = ; + label = "wp_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + chg_sbux { + reg = ; + label = "chg_sbux"; + qcom,pre-scaling = <1 3>; + }; + + mid_chg_div6 { + reg = ; + label = "chg_mid"; + qcom,pre-scaling = <1 6>; + }; + + usb_in_i_uv { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + usb_in_v_div_16 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; +}; + +&pm8150_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vcoin { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_therm { + reg = ; + label = "skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm1 { + reg = ; + label = "pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150l_vadc { + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + camera_flash_therm { + reg = ; + label = "camera_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_msm_therm { + reg = ; + label = "skin_msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm2 { + reg = ; + label = "pa_therm2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&wil6210 { + status = "ok"; +}; + +&pm8150b_adc_tm { + wp_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150_adc_tm { + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150l_adc_tm { + camera_flash_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin_msm_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm2 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + wp-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + camera-flash-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-msm-therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-therm2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&spmi_debug_bus { + status = "ok"; +}; + +&pm8150b_haptics { + qcom,vmax-mv = <2545>; + qcom,play-rate-us = <4255>; + wf_0 { + /* CLICK */ + qcom,wf-pattern = [3e 3e 3e 3e]; + qcom,wf-play-rate-us = <4255>; + }; + wf_1 { + /* DOUBLE CLICK */ + qcom,wf-play-rate-us = <7143>; + }; + wf_2 { + /* TICK */ + qcom,wf-play-rate-us = <4000>; + }; + wf_3 { + /* THUD */ + qcom,wf-pattern = [7e 7e 7e 7e]; + qcom,wf-play-rate-us = <4255>; + }; + wf_4 { + /* POP */ + qcom,wf-play-rate-us = <5000>; + }; + wf_5 { + /* HEAVY CLICK */ + qcom,wf-pattern = [7e 7e 7e 7e]; + qcom,wf-play-rate-us = <4255>; + }; +}; + +&pm8150b_charger { + qcom,sec-charger-config = <1>; + qcom,auto-recharge-soc = <98>; + io-channels = <&pm8150b_vadc ADC_USB_IN_V_16>, + <&pm8150b_vadc ADC_USB_IN_I>, + <&pm8150b_vadc ADC_SBUx>, + <&pm8150b_vadc ADC_VPH_PWR>, + <&pm8150b_vadc ADC_CHG_TEMP>; + io-channel-names = "usb_in_voltage", + "usb_in_current", + "sbux_res", + "vph_voltage", + "chg_temp"; + qcom,battery-data = <&fusion_qrd_batterydata>; + qcom,sw-jeita-enable; + qcom,step-charging-enable; + qcom,wd-bark-time-secs = <16>; + qcom,suspend-input-on-debug-batt; +}; + +&smb1390 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1390_charger { + /delete-property/ compatible; + compatible = "qcom,smb1390-charger-psy"; + io-channels = <&pm8150b_vadc ADC_AMUX_THM2>; + io-channel-names = "cp_die_temp"; + status = "ok"; +}; + +&usb2_phy0 { + qcom,param-override-seq = + <0x49 0x70 + 0x28 0x74>; +}; + +&thermal_zones { + modem1-pa1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&qmi_sensor 101>; + trips { + pa1_lvl0: active-config0 { + temperature = <40000>; + hysteresis = <5000>; + type = "passive"; + }; + pa1_lvl1: active-config1 { + temperature = <45000>; + hysteresis = <3000>; + type = "passive"; + }; + pa1_lvl2: active-config2 { + temperature = <52000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + cooling-maps { + pa1_skin_lvl0 { + trip = <&pa1_lvl0>; + cooling-device = <&modem1_skin0 1 1>; + }; + pa1_skin_lvl1 { + trip = <&pa1_lvl1>; + cooling-device = <&modem1_skin0 2 2>; + }; + pa1_skin_lvl2 { + trip = <&pa1_lvl2>; + cooling-device = <&modem1_skin0 3 3>; + }; + }; + }; + + pa-therm2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>; + trips { + pa2_lvl0: active-config0 { + temperature = <40000>; + hysteresis = <5000>; + type = "passive"; + }; + pa2_lvl1: active-config1 { + temperature = <45000>; + hysteresis = <3000>; + type = "passive"; + }; + pa2_lvl2: active-config2 { + temperature = <52000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + cooling-maps { + pa2_skin_lvl0 { + trip = <&pa2_lvl0>; + cooling-device = <&modem1_skin1 1 1>; + }; + pa2_skin_lvl1 { + trip = <&pa2_lvl1>; + cooling-device = <&modem1_skin1 2 2>; + }; + pa2_skin_lvl2 { + trip = <&pa2_lvl2>; + cooling-device = <&modem1_skin1 3 3>; + }; + }; + }; + + camera-ftherm-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>; + trips { + cam_lvl0: active-config0 { + temperature = <34000>; + hysteresis = <4000>; + type = "passive"; + }; + cam_lvl1: active-config1 { + temperature = <43000>; + hysteresis = <3000>; + type = "passive"; + }; + cam_lvl2: active-config2 { + temperature = <52000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + cooling-maps { + cam_skin_lvl0 { + trip = <&cam_lvl0>; + cooling-device = <&modem1_skin2 1 1>; + }; + cam_skin_lvl1 { + trip = <&cam_lvl1>; + cooling-device = <&modem1_skin2 2 2>; + }; + cam_skin_lvl2 { + trip = <&cam_lvl2>; + cooling-device = <&modem1_skin2 3 3>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-sdx50m.dtsi b/arch/arm/boot/dts/qcom/sm8150-sdx50m.dtsi new file mode 100644 index 000000000000..63b6df46735a --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-sdx50m.dtsi @@ -0,0 +1,605 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdm3 { + compatible = "qcom,ext-sdx50m"; + qcom,mdm-link-info = "0305_01.01.00"; +}; + +&pil_modem { + qcom,poff-depends-on = "esoc0"; +}; + +&wil6210 { + status = "disabled"; +}; + +&mhi_0 { + esoc-names = "mdm"; + esoc-0 = <&mdm3>; + qcom,smmu-cfg = <0>; + memory-region = <&mhi_mem>; + mhi,use-bb; + mhi,buffer-len = <0x8000>; + qcom,addr-win = <0x0 0xa0000000 0x0 0xa4bfffff>; + + mhi_channels { + mhi_chan@1 { + mhi,num-elements = <32>; + }; + + mhi_chan@11 { + mhi,num-elements = <32>; + }; + + mhi_chan@21 { + mhi,num-elements = <32>; + }; + + mhi_chan@100 { + status = "disabled"; + }; + + mhi_chan@101 { + status = "disabled"; + }; + + mhi_chan@102 { + status = "disabled"; + }; + + mhi_chan@103 { + status = "disabled"; + }; + + mhi_chan@104 { + mhi,offload-chan; + }; + + mhi_chan@107 { + status = "disabled"; + }; + + mhi_chan@108 { + status = "disabled"; + }; + }; + + mhi_events { + mhi_event@4 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <5>; + mhi,chan = <104>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_event@5 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <6>; + mhi,chan = <105>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_events@6 { + status = "disabled"; + }; + + mhi_events@7 { + status = "disabled"; + }; + + mhi_events@8 { + status = "disabled"; + }; + + mhi_events@9 { + status = "disabled"; + }; + + mhi_events@10 { + status = "disabled"; + }; + + mhi_events@11 { + status = "disabled"; + }; + }; +}; + +&mhi_1 { + mhi_channels { + mhi_chan@1 { + mhi,num-elements = <32>; + }; + + mhi_chan@11 { + mhi,num-elements = <32>; + }; + + mhi_chan@21 { + mhi,num-elements = <32>; + }; + + mhi_chan@100 { + status = "disabled"; + }; + + mhi_chan@101 { + status = "disabled"; + }; + + mhi_chan@102 { + status = "disabled"; + }; + + mhi_chan@103 { + status = "disabled"; + }; + + mhi_chan@107 { + status = "disabled"; + }; + + mhi_chan@108 { + status = "disabled"; + }; + }; + + mhi_events { + mhi_event@4 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <5>; + mhi,chan = <104>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_event@5 { + mhi,num-elements = <0>; + mhi,intmod = <0>; + mhi,msi = <6>; + mhi,chan = <105>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + mhi,offload; + }; + + mhi_events@6 { + status = "disabled"; + }; + + mhi_events@7 { + status = "disabled"; + }; + + mhi_events@8 { + status = "disabled"; + }; + + mhi_events@9 { + status = "disabled"; + }; + + mhi_events@10 { + status = "disabled"; + }; + + mhi_events@11 { + status = "disabled"; + }; + }; +}; + +&tlmm { + pcie1 { + pcie1_sdx50m_wake_default: pcie1_sdx50m_wake_default { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + drive-strength = <2>; + bias-disable; + }; + }; + }; +}; + +&pcie1 { + pinctrl-0 = <&pcie1_clkreq_default + &pcie1_perst_default + &pcie1_sdx50m_wake_default>; + + iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, + <0x100 &apps_smmu 0x1e7f 0x1>; + + qcom,msm-bus,name = "pcie1"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <100 512 0 0>, + <100 512 4500000 0>; +}; + +&soc { + ipa_hw: qcom,ipa@1e00000 { + qcom,ipa-mhi-proxy; + }; + + imp: qcom,ipa-mhi-proxy { + compatible = "qcom,ipa-mhi-proxy"; + qcom,mhi-chdb-base = <0x40300300>; + qcom,mhi-erdb-base = <0x40300700>; + }; + + qmi-tmd-devices { + modem1 { + qcom,instance-id = <0x64>; + + modem1_pa: modem1_pa { + qcom,qmi-dev-name = "pa"; + #cooling-cells = <2>; + }; + + modem1_proc: modem1_proc { + qcom,qmi-dev-name = "modem"; + #cooling-cells = <2>; + }; + + modem1_current: modem1_current { + qcom,qmi-dev-name = "modem_current"; + #cooling-cells = <2>; + }; + + modem1_skin: modem1_skin { + qcom,qmi-dev-name = "modem_skin"; + #cooling-cells = <2>; + }; + + modem1_skin0: modem1_skin0 { + qcom,qmi-dev-name = "modem_skin0"; + #cooling-cells = <2>; + }; + + modem1_skin1: modem1_skin1 { + qcom,qmi-dev-name = "modem_skin1"; + #cooling-cells = <2>; + }; + + modem1_skin2: modem1_skin2 { + qcom,qmi-dev-name = "modem_skin2"; + #cooling-cells = <2>; + }; + + modem1_skin3: modem1_skin3 { + qcom,qmi-dev-name = "modem_skin3"; + #cooling-cells = <2>; + }; + + modem1_mmw0: modem1_mmw0 { + qcom,qmi-dev-name = "mmw0"; + #cooling-cells = <2>; + }; + + modem1_mmw1: modem1_mmw1 { + qcom,qmi-dev-name = "mmw1"; + #cooling-cells = <2>; + }; + + modem1_mmw2: modem1_mmw2 { + qcom,qmi-dev-name = "mmw2"; + #cooling-cells = <2>; + }; + + modem1_mmw3: modem1_mmw3 { + qcom,qmi-dev-name = "mmw3"; + #cooling-cells = <2>; + }; + + modem1_vdd: modem1_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + }; + + qmi_sensor: qmi-ts-sensors { + compatible = "qcom,qmi-sensors"; + #thermal-sensor-cells = <1>; + + modem { + qcom,instance-id = <0x0>; + qcom,qmi-sensor-names = "pa", + "pa_1", + "qfe_pa0", + "qfe_wtr0"; + }; + + modem1 { + qcom,instance-id = <100>; + qcom,qmi-sensor-names = "pa", + "pa_1", + "pa_2", + "qfe_pa0", + "qfe_wtr0", + "modem_tsens", + "qfe_mmw0", + "qfe_mmw1", + "qfe_mmw2", + "qfe_mmw3", + "xo_therm", + "qfe_pa_mdm", + "qfe_pa_wtr"; + }; + }; +}; + +&thermal_zones { + modem0-pa0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor 0>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem0-pa1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor 1>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem1-pa0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor 100>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem1-pa1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor 101>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem1-qfe-wtr-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor 104>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem1-modem-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor 105>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem1-mmw0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor 106>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem1-mmw1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor 107>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem1-mmw2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor 108>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem1-mmw3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor 109>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem1-skin-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor 110>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem1-pa-mdm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor 111>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem1-pa-wtr-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor 112>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem1-pa2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor 102>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + + pil_buffer_p2_mem: pil_buffer_p2_region@a0000000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0xa0000000 0x0 0x01000000>; + }; + + pil_buffer_p1_mem: pil_buffer_p1_region@0a1000000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0xa1000000 0x0 0x02c00000>; + }; + + mhi_mem: mhi_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0xa3c00000 0x0 0x01000000>; + alignment = <0x0 0x400000>; + size = <0x0 0x01000000>; + no-map; + }; +}; + +&usb1 { + dwc3@a800000 { + snps,bus-suspend-enable; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-sdxprairie-cdp-overlay.dts b/arch/arm/boot/dts/qcom/sm8150-sdxprairie-cdp-overlay.dts new file mode 100644 index 000000000000..069530ebfbc3 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-sdxprairie-cdp-overlay.dts @@ -0,0 +1,62 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-cdp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdxprairie.dtsi" +#include "sm8150-cdp-audio-overlay.dtsi" + +/ { + model = "SDXPRAIRIE CDP"; + compatible = "qcom,sm8150-cdp", "qcom,sm8150", "qcom,cdp"; + qcom,board-id = <1 2>; +}; + +&dsi_sharp_4k_dsc_cmd_display { + /delete-property/ qcom,dsi-display-active; +}; + +&dsi_dual_nt35597_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 9 0>; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 9 0>; +}; + +&dsi_dual_nt35597_truly_cmd_display { + qcom,dsi-display-active; +}; + +&pm8150l_wled { + qcom,string-cfg = <6>; + qcom,leds-per-string = <8>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-sdxprairie-mtp-overlay.dts b/arch/arm/boot/dts/qcom/sm8150-sdxprairie-mtp-overlay.dts new file mode 100644 index 000000000000..8e62d71f7763 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-sdxprairie-mtp-overlay.dts @@ -0,0 +1,64 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdxprairie.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" + +/ { + model = "SDXPRAIRIE MTP"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 2>; +}; + +&dsi_sharp_4k_dsc_cmd_display { + /delete-property/ qcom,dsi-display-active; +}; + +&dsi_dual_nt35597_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 9 0>; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 9 0>; +}; + +&dsi_dual_nt35597_truly_cmd_display { + qcom,dsi-display-active; +}; + +&pm8150l_wled { + qcom,string-cfg = <6>; + qcom,leds-per-string = <8>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-sdxprairie-v2-cdp-overlay.dts b/arch/arm/boot/dts/qcom/sm8150-sdxprairie-v2-cdp-overlay.dts new file mode 100644 index 000000000000..98212133ee81 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-sdxprairie-v2-cdp-overlay.dts @@ -0,0 +1,66 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-cdp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdxprairie-v2.dtsi" +#include "sm8150-cdp-audio-overlay.dtsi" + +/ { + model = "SDXPRAIRIE V2 CDP"; + compatible = "qcom,sm8150-cdp", "qcom,sm8150", "qcom,cdp"; + qcom,board-id = <1 4>; +}; + +&dsi_sharp_4k_dsc_cmd_display { + /delete-property/ qcom,dsi-display-active; +}; + +&dsi_dual_nt35597_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 9 0>; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 9 0>; +}; + +&dsi_dual_nt35597_truly_cmd_display { + qcom,dsi-display-active; +}; + +&pm8150l_wled { + qcom,string-cfg = <6>; + qcom,leds-per-string = <8>; +}; + +&icnss { + qcom,clk-monitor-enable; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-sdxprairie-v2-mtp-overlay.dts b/arch/arm/boot/dts/qcom/sm8150-sdxprairie-v2-mtp-overlay.dts new file mode 100644 index 000000000000..3d8a9956d8d8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-sdxprairie-v2-mtp-overlay.dts @@ -0,0 +1,66 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdxprairie-v2.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +/ { + model = "SDXPRAIRIE V2 MTP"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 4>; +}; + +&dsi_sharp_4k_dsc_cmd_display { + /delete-property/ qcom,dsi-display-active; +}; + +&dsi_dual_nt35597_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 9 0>; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 9 0>; +}; + +&dsi_dual_nt35597_truly_cmd_display { + qcom,dsi-display-active; +}; + +&pm8150l_wled { + qcom,string-cfg = <6>; + qcom,leds-per-string = <8>; +}; + +&icnss { + qcom,clk-monitor-enable; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-sdxprairie-v2.dtsi b/arch/arm/boot/dts/qcom/sm8150-sdxprairie-v2.dtsi new file mode 100644 index 000000000000..1db2ca04e534 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-sdxprairie-v2.dtsi @@ -0,0 +1,18 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm8150-sdxprairie.dtsi" + +&icnss { + esoc-names = "mdm"; + esoc-0 = <&mdm3>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-sdxprairie.dtsi b/arch/arm/boot/dts/qcom/sm8150-sdxprairie.dtsi new file mode 100644 index 000000000000..2c01b219613a --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-sdxprairie.dtsi @@ -0,0 +1,581 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&mdm3 { + compatible = "qcom,ext-sdxprairie"; + qcom,mdm-link-info = "0306_01.01.00"; +}; + +&pil_modem { + /delete-property/ vdd_mss-supply; + /delete-property/ qcom,vdd_mss-uV-uA; + qcom,proxy-reg-names = "vdd_cx"; +}; + +&pcie1 { + dma-coherent; +}; + +&mhi_0 { + esoc-names = "mdm"; + esoc-0 = <&mdm3>; + qcom,smmu-cfg = <0x1d>; + qcom,addr-win = <0x0 0x20000000 0x0 0x2fffffff>; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + + mhi_chan@9 { + mhi,num-elements = <128>; + }; + + mhi_chan@25 { + status = "disabled"; + }; + + mhi_chan@80 { + reg = <80>; + label = "AUDIO_VOICE_0"; + mhi,event-ring = <0>; + mhi,chan-dir = <0>; + mhi,ee = <0x4>; + mhi,data-type = <3>; + mhi,offload-chan; + status = "ok"; + }; + + mhi_chan@104 { + label = "IP_HW0_RSC"; + mhi,num-elements = <512>; + mhi,local-elements = <3078>; + mhi,event-ring = <5>; + mhi,chan-dir = <2>; + mhi,data-type = <5>; + mhi,doorbell-mode = <3>; + mhi,chan-type = <3>; + }; + + mhi_chan@105 { + label = "IP_HW_MHIP_0"; + mhi,event-ring = <8>; + mhi,chan-dir = <1>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + }; + + mhi_chan@106 { + reg = <106>; + label = "IP_HW_MHIP_0"; + mhi,event-ring = <9>; + mhi,chan-dir = <2>; + mhi,data-type = <3>; + mhi,ee = <0x4>; + mhi,offload-chan; + mhi,lpm-notify; + }; + }; + + mhi_devices { + mhi_qrtr { + mhi,chan = "IPCR"; + qcom,net-id = <3>; + }; + }; +}; + +&glink_adsp { + qcom,adsp_qrtr { + qcom,net-id = <2>; + }; +}; + +&glink_slpi { + qcom,slpi_qrtr { + qcom,net-id = <1>; + }; +}; + +&glink_cdsp { + qcom,cdsp_qrtr { + qcom,net-id = <1>; + }; +}; + +&glink_modem { + qcom,modem_qrtr { + qcom,net-id = <2>; + }; +}; + +&soc { + ipa_hw: qcom,ipa@1e00000 { + qcom,platform-type = <2>; /* APQ platform */ + qcom,entire-ipa-block-size = <0x100000>; + qcom,register-collection-on-crash; + qcom,testbus-collection-on-crash; + qcom,non-tn-collection-on-crash; + qcom,secure-debug-check-action = <0>; + qcom,throughput-threshold = <600 2500 5000>; + qcom,scaling-exceptions = "USB DPL", "0", "2500", + "5000", "ODL", "0", "2500", "5000"; + }; + + qcom,ipa_fws { + memory-region = <&pil_ipa_gsi_mem>; + }; + + qcom,ipa_uc { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0x1B>; + qcom,firmware-name = "ipa_uc"; + qcom,pil-force-shutdown; + memory-region = <&pil_ipa_fw_mem>; + }; + ipa_mpm: qcom,ipa-mpm { + compatible = "qcom,ipa-mpm"; + qcom,mhi-chdb-base = <0x40300300>; + qcom,mhi-erdb-base = <0x40300700>; + qcom,iova-mapping = <0x10000000 0x0FFFFFFF>; + }; +}; + +&reserved_memory { + mailbox_mem: mailbox_region { + compatible = "shared-dma-pool"; + no-map; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + alignment = <0x0 0x400000>; + size = <0x0 0x20000>; + }; +}; + +&pil_modem_mem { + reg = <0x0 0x8d800000 0x0 0x3200000>; +}; + +&pil_video_mem { + reg = <0x0 0x90a00000 0x0 0x500000>; +}; + +&pil_slpi_mem { + reg = <0x0 0x90f00000 0x0 0x1500000>; +}; + +&pil_ipa_fw_mem { + reg = <0x0 0x92400000 0x0 0x10000>; +}; + +&pil_ipa_gsi_mem { + reg = <0x0 0x92410000 0x0 0xa000>; +}; + +&pil_gpu_mem { + reg = <0x0 0x9241a000 0x0 0x2000>; +}; + +&pil_spss_mem { + reg = <0x0 0x92500000 0x0 0x100000>; +}; + +&pil_cdsp_mem { + reg = <0x0 0x92600000 0x0 0x1400000>; +}; + +&audio_apr { + voice_mhi_audio: qcom,voice-mhi-audio { + compatible = "qcom,voice-mhi-audio"; + memory-region = <&mailbox_mem>; + voice_mhi_voting; + }; +}; + +&wil6210 { + status = "disabled"; +}; + + +&icnss { + esoc-names = "mdm"; + esoc-0 = <&mdm3>; +}; + +&icnss { + qcom,clk-monitor-enable; +}; + +&soc { + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + modem { + qcom,instance-id = ; + + modem_pa: modem_pa { + qcom,qmi-dev-name = "pa"; + #cooling-cells = <2>; + }; + + modem_tj: modem_tj { + qcom,qmi-dev-name = "modem"; + #cooling-cells = <2>; + }; + + modem_current: modem_current { + qcom,qmi-dev-name = "modem_current"; + #cooling-cells = <2>; + }; + + modem_skin: modem_skin { + qcom,qmi-dev-name = "modem_skin"; + #cooling-cells = <2>; + }; + + modem_mmw_skin0: modem_mmw_skin0 { + qcom,qmi-dev-name = "modem_skin0"; + #cooling-cells = <2>; + }; + + modem_mmw_skin1: modem_mmw_skin1 { + qcom,qmi-dev-name = "modem_skin1"; + #cooling-cells = <2>; + }; + + modem_mmw_skin2: modem_mmw_skin2 { + qcom,qmi-dev-name = "modem_skin2"; + #cooling-cells = <2>; + }; + + modem_mmw_skin3: modem_mmw_skin3 { + qcom,qmi-dev-name = "modem_skin3"; + #cooling-cells = <2>; + }; + + modem_mmw0: modem_mmw0 { + qcom,qmi-dev-name = "mmw0"; + #cooling-cells = <2>; + }; + + modem_mmw1: modem_mmw1 { + qcom,qmi-dev-name = "mmw1"; + #cooling-cells = <2>; + }; + + modem_mmw2: modem_mmw2 { + qcom,qmi-dev-name = "mmw2"; + #cooling-cells = <2>; + }; + + modem_mmw3: modem_mmw3 { + qcom,qmi-dev-name = "mmw3"; + #cooling-cells = <2>; + }; + + modem_bcl: modem_bcl { + qcom,qmi-dev-name = "vbatt_low"; + #cooling-cells = <2>; + }; + }; + }; + + qmi_sensor: qmi-ts-sensors { + compatible = "qcom,qmi-sensors"; + #thermal-sensor-cells = <1>; + + modem { + qcom,instance-id = ; + qcom,qmi-sensor-names = "pa", + "pa_1", + "qfe_wtr0", + "modem_tsens", + "qfe_mmw0", + "qfe_mmw1", + "qfe_mmw2", + "qfe_mmw3", + "xo_therm", + "qfe_mmw_streamer0", + "qfe_mmw0_mod", + "qfe_mmw1_mod", + "qfe_mmw2_mod", + "qfe_mmw3_mod", + "qfe_ret_pa0", + "qfe_wtr_pa0", + "qfe_wtr_pa1", + "qfe_wtr_pa2", + "qfe_wtr_pa3", + "sys_therm1", + "sys_therm2", + "modem_tsens1"; + }; + }; +}; + +&thermal_zones { + modem-lte-sub6-pa1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_NR_INST_ID+QMI_PA)>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-lte-sub6-pa2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_NR_INST_ID+QMI_PA_1)>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-mmw0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_0)>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-mmw1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_1)>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-mmw2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_2)>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-mmw3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_3)>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-skin-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_NR_INST_ID+QMI_XO_THERM)>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-wifi-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_NR_INST_ID+QMI_SYS_THERM_1)>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-ambient-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_NR_INST_ID+QMI_SYS_THERM_2)>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_NR_INST_ID+QMI_MODEM_TSENS)>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_NR_INST_ID+QMI_MODEM_TSENS_1)>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-streamer-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_STREAMER_0)>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-mmw0-mod-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_0_MOD)>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-mmw1-mod-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_1_MOD)>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-mmw2-mod-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_2_MOD)>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem-mmw3-mod-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_3_MOD)>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-slpi-pinctrl.dtsi b/arch/arm/boot/dts/qcom/sm8150-slpi-pinctrl.dtsi new file mode 100644 index 000000000000..1821370d47a8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-slpi-pinctrl.dtsi @@ -0,0 +1,198 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + slpi_tlmm: slpi_pinctrl@02B40000 { + compatible = "qcom,slpi-pinctrl"; + reg = <0x2B40000 0x20000>; + qcom,num-pins = <14>; + status = "disabled"; + + qupv3_se20_i2c_pins: qupv3_se20_i2c_pins { + qupv3_se20_i2c_active: qupv3_se20_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "func1"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se20_i2c_sleep: qupv3_se20_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se21_i2c_pins: qupv3_se21_i2c_pins { + qupv3_se21_i2c_active: qupv3_se21_i2c_active { + mux { + pins = "gpi2", "gpio3"; + function = "func1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se21_i2c_sleep: qupv3_se21_i2c_sleep { + mux { + pins = "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se22_i2c_pins: qupv3_se22_i2c_pins { + qupv3_se22_i2c_active: qupv3_se22_i2c_active { + mux { + pins = "gpio6", "gpio7"; + function = "func1"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se22_i2c_sleep: qupv3_se22_i2c_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se23_i2c_pins: qupv3_se23_i2c_pins { + qupv3_se23_i2c_active: qupv3_se23_i2c_active { + mux { + pins = "gpio8", "gpio9"; + function = "func3"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se23_i2c_sleep: qupv3_se23_i2c_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + /* SE21 pin mappings */ + qupv3_se21_spi_pins: qupv3_se21_spi_pins { + qupv3_se21_spi_active: qupv3_se21_spi_active { + mux { + pins = "gpio2", "gpio3", "gpio4", + "gpio5"; + function = "func1"; + }; + + config { + pins = "gpio2", "gpio3", "gpio4", + "gpio5"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se21_spi_sleep: qupv3_se21_spi_sleep { + mux { + pins = "gpio2", "gpio3", "gpio4", + "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio2", "gpio3", "gpio4", + "gpio5"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /*SE22 pin mappings*/ + qupv3_se22_spi_pins: qupv3_se22_spi_pins { + qupv3_se22_spi_active: qupv3_se22_spi_active { + mux { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + function = "func1"; + }; + + config { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se22_spi_sleep: qupv3_se22_spi_sleep { + mux { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-smp2p.dtsi b/arch/arm/boot/dts/qcom/sm8150-smp2p.dtsi new file mode 100644 index 000000000000..50cf62763f2c --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-smp2p.dtsi @@ -0,0 +1,154 @@ +/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + + qcom,smp2p-modem@1799000c { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + qcom,ipc = <&apcs 0 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + qcom,smp2p-adsp@1799000c { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = ; + qcom,ipc = <&apcs 0 10>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-dsps@1799000c { + compatible = "qcom,smp2p"; + qcom,smem = <481>, <430>; + interrupts = ; + qcom,ipc = <&apcs 0 26>; + qcom,local-pid = <0>; + qcom,remote-pid = <3>; + + dsps_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + dsps_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-cdsp@1799000c { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts = ; + qcom,ipc = <&apcs 0 6>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_qvrexternal5_out: qcom,smp2p-qvrexternal5-out { + qcom,entry-name = "qvrexternal"; + #qcom,smem-state-cells = <1>; + }; + }; + +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-thermal-overlay.dtsi b/arch/arm/boot/dts/qcom/sm8150-thermal-overlay.dtsi new file mode 100644 index 000000000000..87e75cf559e7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-thermal-overlay.dtsi @@ -0,0 +1,302 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include + +&thermal_zones { + pm8150b_tz { + cooling-maps { + trip0_bat { + trip = <&pm8150b_trip0>; + cooling-device = + <&pm8150b_charger (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip1_bat { + trip = <&pm8150b_trip1>; + cooling-device = + <&pm8150b_charger THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm8150_tz { + cooling-maps { + trip0_cpu0 { + trip = <&pm8150_trip0>; + cooling-device = + <&CPU0 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu1 { + trip = <&pm8150_trip0>; + cooling-device = + <&CPU1 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu2 { + trip = <&pm8150_trip0>; + cooling-device = + <&CPU2 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu3 { + trip = <&pm8150_trip0>; + cooling-device = + <&CPU3 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu4 { + trip = <&pm8150_trip0>; + cooling-device = + <&CPU4 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu5 { + trip = <&pm8150_trip0>; + cooling-device = + <&CPU5 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu6 { + trip = <&pm8150_trip0>; + cooling-device = + <&CPU6 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu7 { + trip = <&pm8150_trip0>; + cooling-device = + <&CPU7 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip1_cpu1 { + trip = <&pm8150_trip1>; + cooling-device = + <&CPU1 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu2 { + trip = <&pm8150_trip1>; + cooling-device = + <&CPU2 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu3 { + trip = <&pm8150_trip1>; + cooling-device = + <&CPU3 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu4 { + trip = <&pm8150_trip1>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu5 { + trip = <&pm8150_trip1>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu6 { + trip = <&pm8150_trip1>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu7 { + trip = <&pm8150_trip1>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + soc { + cooling-maps { + soctrip_cpu4 { + trip = <&soc_trip2>; + cooling-device = + <&CPU4 6 6>; + }; + soctrip_cpu7 { + trip = <&soc_trip2>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + soctrip_cpu6 { + trip = <&soc_trip>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm8150b-vbat-lvl0 { + cooling-maps { + vbat_cpu4 { + trip = <&vbat_lvl0>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + vbat_cpu5 { + trip = <&vbat_lvl0>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + vbat_gpu0 { + trip = <&vbat_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm8150b-vbat-lvl1 { + cooling-maps { + vbat_cpu6 { + trip = <&vbat_lvl1>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + vbat_cpu7 { + trip = <&vbat_lvl1>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + vbat_gpu1 { + trip = <&vbat_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + }; + }; + + pm8150b-vbat-lvl2 { + cooling-maps { + vbat_gpu2 { + trip = <&vbat_lvl2>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm8150b-ibat-lvl0 { + cooling-maps { + ibat_cpu4 { + trip = <&ibat_lvl0>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + ibat_cpu5 { + trip = <&ibat_lvl0>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + ibat_gpu0 { + trip = <&ibat_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm8150b-ibat-lvl1 { + cooling-maps { + ibat_cpu6 { + trip = <&ibat_lvl1>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + ibat_cpu7 { + trip = <&ibat_lvl1>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + ibat_gpu1 { + trip = <&ibat_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + }; + }; + + pm8150l-vph-lvl0 { + disable-thermal-zone; + cooling-maps { + vph_cpu4 { + trip = <&vph_lvl0>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + vph_cpu5 { + trip = <&vph_lvl0>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + vph_gpu0 { + trip = <&vph_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm8150l-vph-lvl1 { + disable-thermal-zone; + cooling-maps { + vph_cpu6 { + trip = <&vph_lvl1>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + vph_cpu7 { + trip = <&vph_lvl1>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + vph_gpu1 { + trip = <&vph_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + }; + }; + + pm8150l-vph-lvl2 { + disable-thermal-zone; + cooling-maps { + vph_gpu2 { + trip = <&vph_lvl2>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; +}; + +&mdss_mdp { + #cooling-cells = <2>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-thermal.dtsi b/arch/arm/boot/dts/qcom/sm8150-thermal.dtsi new file mode 100644 index 000000000000..79460e4d4401 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-thermal.dtsi @@ -0,0 +1,1274 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&clock_cpucc { + #address-cells = <1>; + #size-cells = <1>; + lmh_dcvs0: qcom,limits-dcvs@18358800 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + qcom,affinity = <0>; + reg = <0x18358800 0x1000>, + <0x18323000 0x1000>; + #thermal-sensor-cells = <0>; + }; + + lmh_dcvs1: qcom,limits-dcvs@18350800 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + qcom,affinity = <1>; + reg = <0x18350800 0x1000>, + <0x18325800 0x1000>; + #thermal-sensor-cells = <0>; + isens_vref_0p8-supply = <&pm8150_l5_ao>; + isens-vref-0p8-settings = <880000 880000 20000>; + isens_vref_1p8-supply = <&pm8150_l12_ao>; + isens-vref-1p8-settings = <1800000 1800000 20000>; + }; +}; + +&soc { + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + modem0 { + qcom,instance-id = <0x0>; + + modem0_pa: modem0_pa { + qcom,qmi-dev-name = "pa"; + #cooling-cells = <2>; + }; + + modem0_proc: modem0_proc { + qcom,qmi-dev-name = "modem"; + #cooling-cells = <2>; + }; + + modem0_current: modem0_current { + qcom,qmi-dev-name = "modem_current"; + #cooling-cells = <2>; + }; + + modem0_skin: modem0_skin { + qcom,qmi-dev-name = "modem_skin"; + #cooling-cells = <2>; + }; + + modem0_vdd: modem0_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + + adsp { + qcom,instance-id = <0x1>; + + adsp_vdd: adsp_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + + cdsp { + qcom,instance-id = <0x43>; + + cdsp_vdd: cdsp_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + + slpi { + qcom,instance-id = <0x53>; + + slpi_vdd: slpi_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + }; +}; + +&thermal_zones { + aoss0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 0>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-0-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 1>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-0-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-0-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 3>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-0-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpuss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-1-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-1-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-1-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-1-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-1-4-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-1-5-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-1-6-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-1-7-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + gpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 15>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + aoss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 0>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cwlan-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 1>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + video-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 2>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + ddr-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + q6-hvx-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + camera-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 5>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cmpss-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 6>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mdm-core-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 7>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + npu-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mdm-vec-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 9>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mdm-scl-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 10>; + thermal-governor = "user_space"; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + gpuss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens1 11>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu-1-7-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + thermal-governor = "low_limits_floor"; + wake-capable-sensor; + tracks-low; + trips { + cpu17_trip: cpu17-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&cpu17_trip>; + cooling-device = <&CPU0 1 1>; + }; + cpu1_cdev { + trip = <&cpu17_trip>; + cooling-device = <&CPU4 5 5>; + }; + cx_vdd_cdev { + trip = <&cpu17_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&cpu17_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + ebi_vdd_cdev { + trip = <&cpu17_trip>; + cooling-device = <&ebi_cdev 0 0>; + }; + mmcx_vdd_cdev { + trip = <&cpu17_trip>; + cooling-device = <&mm_cx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&cpu17_trip>; + cooling-device = <&modem0_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&cpu17_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&cpu17_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + slpi_vdd_cdev { + trip = <&cpu17_trip>; + cooling-device = <&slpi_vdd 0 0>; + }; + gpu_vdd_cdev { + trip = <&cpu17_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; + }; + }; + }; + + gpuss-0-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 15>; + thermal-governor = "low_limits_floor"; + wake-capable-sensor; + tracks-low; + trips { + gpuss0_trip: gpuss0-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&gpuss0_trip>; + cooling-device = <&CPU0 1 1>; + }; + cpu1_cdev { + trip = <&gpuss0_trip>; + cooling-device = <&CPU4 5 5>; + }; + cx_vdd_cdev { + trip = <&gpuss0_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&gpuss0_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + ebi_vdd_cdev { + trip = <&gpuss0_trip>; + cooling-device = <&ebi_cdev 0 0>; + }; + mmcx_vdd_cdev { + trip = <&gpuss0_trip>; + cooling-device = <&mm_cx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&gpuss0_trip>; + cooling-device = <&modem0_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&gpuss0_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&gpuss0_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + slpi_vdd_cdev { + trip = <&gpuss0_trip>; + cooling-device = <&slpi_vdd 0 0>; + }; + gpu_vdd_cdev { + trip = <&gpuss0_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; + }; + }; + }; + + camera-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 5>; + thermal-governor = "low_limits_floor"; + wake-capable-sensor; + tracks-low; + trips { + camera_trip: camera-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&camera_trip>; + cooling-device = <&CPU0 1 1>; + }; + cpu1_cdev { + trip = <&camera_trip>; + cooling-device = <&CPU4 5 5>; + }; + cx_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + ebi_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&ebi_cdev 0 0>; + }; + mmcx_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&mm_cx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&modem0_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + slpi_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&slpi_vdd 0 0>; + }; + gpu_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; + }; + }; + }; + + mdm-scl-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 10>; + thermal-governor = "low_limits_floor"; + wake-capable-sensor; + tracks-low; + trips { + mdms_trip: mdms-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&mdms_trip>; + cooling-device = <&CPU0 1 1>; + }; + cpu1_cdev { + trip = <&mdms_trip>; + cooling-device = <&CPU4 5 5>; + }; + cx_vdd_cdev { + trip = <&mdms_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&mdms_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + ebi_vdd_cdev { + trip = <&mdms_trip>; + cooling-device = <&ebi_cdev 0 0>; + }; + mmcx_vdd_cdev { + trip = <&mdms_trip>; + cooling-device = <&mm_cx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&mdms_trip>; + cooling-device = <&modem0_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&mdms_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&mdms_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + slpi_vdd_cdev { + trip = <&mdms_trip>; + cooling-device = <&slpi_vdd 0 0>; + }; + gpu_vdd_cdev { + trip = <&mdms_trip>; + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-2) + (THERMAL_MAX_LIMIT-2)>; + }; + }; + }; + + gpuss-max-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + gpu_trip0: gpu-trip0 { + temperature = <85000>; + hysteresis = <0>; + type = "passive"; + }; + }; + cooling-maps { + gpu_cdev { + trip = <&gpu_trip0>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + apc-0-max-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + silver-trip { + temperature = <120000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + apc-1-max-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + gold-trip { + temperature = <120000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + pop-mem-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + pop_trip: pop-trip { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + }; + cooling-maps { + pop_cdev4 { + trip = <&pop_trip>; + cooling-device = + <&CPU4 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + pop_cdev5 { + trip = <&pop_trip>; + cooling-device = + <&CPU5 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + pop_cdev6 { + trip = <&pop_trip>; + cooling-device = + <&CPU6 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + pop_cdev7 { + trip = <&pop_trip>; + cooling-device = + <&CPU7 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + }; + }; + + lmh-dcvs-01 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&lmh_dcvs1>; + wake-capable-sensor; + + trips { + active-config { + temperature = <85000>; + hysteresis = <25000>; + type = "passive"; + }; + }; + }; + + lmh-dcvs-00 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&lmh_dcvs0>; + wake-capable-sensor; + + trips { + active-config { + temperature = <85000>; + hysteresis = <25000>; + type = "passive"; + }; + }; + }; + + npu-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + npu_trip0: npu-trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + }; + cooling-maps { + npu_cdev { + trip = <&npu_trip0>; + cooling-device = + <&msm_npu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-0-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 1>; + wake-capable-sensor; + trips { + cpu00_config: cpu00-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu00_cdev { + trip = <&cpu00_config>; + cooling-device = + <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-0-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 2>; + wake-capable-sensor; + trips { + cpu01_config: cpu01-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu01_cdev { + trip = <&cpu01_config>; + cooling-device = + <&CPU1 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-0-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 3>; + wake-capable-sensor; + trips { + cpu02_config: cpu02-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu02_cdev { + trip = <&cpu02_config>; + cooling-device = + <&CPU2 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-0-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu03_config: cpu03-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu03_cdev { + trip = <&cpu03_config>; + cooling-device = + <&CPU3 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu10_config: cpu10-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu10_cdev { + trip = <&cpu10_config>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu11_config: cpu11-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu11_cdev { + trip = <&cpu11_config>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu12_config: cpu12-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu12_cdev { + trip = <&cpu12_config>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu13_config: cpu13-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu13_cdev { + trip = <&cpu13_config>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-4-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu14_config: cpu14-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu14_cdev { + trip = <&cpu14_config>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-5-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu15_config: cpu15-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu15_cdev { + trip = <&cpu15_config>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-6-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu16_config: cpu16-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu16_cdev { + trip = <&cpu16_config>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-7-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cpu17_config: cpu17-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu17_cdev { + trip = <&cpu17_config>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pop-mem-test { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + pop_test_trip: pop-test-trip { + temperature = <125000>; + hysteresis = <0>; + type = "passive"; + }; + }; + cooling-maps { + pop_test_cdev0 { + trip = <&pop_test_trip>; + cooling-device = + <&modem0_pa THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + pop_test_cdev1 { + trip = <&pop_test_trip>; + cooling-device = + <&modem0_proc THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + pop_test_cdev2 { + trip = <&pop_test_trip>; + cooling-device = + <&modem0_current THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + pop_test_cdev3 { + trip = <&pop_test_trip>; + cooling-device = + <&modem0_skin THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + pop_test_cdev4 { + trip = <&pop_test_trip>; + cooling-device = + <&mdss_mdp THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + q6-hvx-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + q6_hvx_step0: q6-hvx-step0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + q6_hvx_step1: q6-hvx-step1 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + hvx_cdev_lvl0 { + trip = <&q6_hvx_step0>; + cooling-device = <&msm_cdsp_rm + THERMAL_NO_LIMIT 6>; + }; + hvx_cdev_lvl1 { + trip = <&q6_hvx_step1>; + cooling-device = <&msm_cdsp_rm 6 6>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-usb.dtsi b/arch/arm/boot/dts/qcom/sm8150-usb.dtsi new file mode 100644 index 000000000000..cc1d4930aa87 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-usb.dtsi @@ -0,0 +1,586 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&soc { + /* Primary USB port related controller */ + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a600000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x140 0x0>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <0 489 0>, <0 130 0>, <0 486 0>, <0 488 0>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&usb30_prim_gdsc>; + dpdm-supply = <&usb2_phy0>; + clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>, + <&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>, + /* + * GCC_USB3_SEC_CLKREF_CLK provides ref_clk for both + * USB instances. Hence GCC_USB3_PRIM_CLKREF_CLK is not + * used here. + */ + <&clock_gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&clock_gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + qcom,pm-qos-latency = <44>; + + qcom,msm-bus,name = "usb0"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <3>; + qcom,msm-bus,vectors-KBps = + /* suspend vote */ + , + , + , + + /* nominal vote */ + , + , + , + + /* svs vote */ + , + , + , + + /* min vote */ + , + , + ; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0x0a600000 0xcd00>; + interrupts = <0 133 0>; + usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,ssp-u3-u0-quirk; + //snps,usb3-u1u2-disable; + usb-core-id = <0>; + tx-fifo-resize; + maximum-speed = "super-speed"; + //maximum-speed = "super-speed-plus"; + dr_mode = "otg"; + }; + + qcom,usbbam@a704000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa704000 0x17000>; + interrupts = <0 132 0>; + + qcom,usb-bam-fifo-baseaddr = <0x146bb000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + /* Primary USB port related High Speed PHY */ + usb2_phy0: hsphy@88e2000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e2000 0x110>, + <0x007801f8 0x4>; + reg-names = "hsusb_phy_base", + "phy_rcal_reg"; + + vdd-supply = <&pm8150_l5>; + vdda18-supply = <&pm8150_l12>; + vdda33-supply = <&pm8150_l2>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + qcom,param-override-seq = <0x43 0x70>; + qcom,rcal-mask = <0x1e00000>; + }; + + /* Primary USB port related QMP USB DP Combo PHY */ + usb_qmp_dp_phy: ssphy@88e8000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88e8000 0x3000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&pm8150_l5>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&pm8150l_l3>; + qcom,vbus-valid-override; + qcom,link-training-reset; + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + + clocks = <&clock_gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&clock_gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x1b2f 0x0>; + qcom,usb-audio-stream-id = <0xf>; + qcom,usb-audio-intr-num = <2>; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + /* Secondary USB port related controller */ + usb1: ssusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a800000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x160 0x0>; + qcom,smmu-s1-bypass; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <0 491 0>, <0 135 0>, <0 487 0>, <0 490 0>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&usb30_sec_gdsc>; + clocks = <&clock_gcc GCC_USB30_SEC_MASTER_CLK>, + <&clock_gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&clock_gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&clock_gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&clock_gcc GCC_USB30_SEC_SLEEP_CLK>, + <&clock_gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + resets = <&clock_gcc GCC_USB30_SEC_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + qcom,charging-disabled; + qcom,pm-qos-latency = <44>; + + qcom,msm-bus,name = "usb1"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <3>; + qcom,msm-bus,vectors-KBps = + /* suspend vote */ + , + , + , + + /* nominal vote */ + , + , + , + + /* svs vote */ + , + , + ; + + status = "disabled"; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0x0a800000 0xcd00>; + interrupts = <0 138 0>; + usb-phy = <&usb2_phy1>, <&usb_qmp_phy>; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + usb-core-id = <1>; + tx-fifo-resize; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + + /* Primary USB port related High Speed PHY */ + usb2_phy1: hsphy@88e3000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e3000 0x110>, + <0x007801f8 0x4>; + reg-names = "hsusb_phy_base", + "phy_rcal_reg"; + + vdd-supply = <&pm8150_l5>; + vdda18-supply = <&pm8150_l12>; + vdda33-supply = <&pm8150_l2>; + qcom,vdd-voltage-level = <0 880000 880000>; + + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&clock_gcc GCC_QUSB2PHY_SEC_BCR>; + reset-names = "phy_reset"; + qcom,rcal-mask = <0x1e00000>; + + status = "disabled"; + }; + + /* Secondary USB port related QMP PHY */ + usb_qmp_phy: ssphy@88eb000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x88eb000 0x1000>, + <0x088eb88c 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&pm8150_l5>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&pm8150l_l3>; + qcom,vbus-valid-override; + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + + clocks = <&clock_gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&clock_gcc GCC_USB3_SEC_PHY_PIPE_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB3_SEC_CLKREF_CLK>, + <&clock_gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&clock_gcc GCC_USB3_PHY_SEC_BCR>, + <&clock_gcc GCC_USB3PHY_PHY_SEC_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-v2-camera.dtsi b/arch/arm/boot/dts/qcom/sm8150-v2-camera.dtsi new file mode 100644 index 000000000000..9bcdf51cfe09 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-v2-camera.dtsi @@ -0,0 +1,340 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + cam_vfe0: qcom,vfe0@acaf000 { + cell-index = <0>; + compatible = "qcom,vfe175"; + reg-names = "ife", "cam_camnoc"; + reg = <0xacaf000 0x4000>, + <0xac42000 0x5000>; + reg-cam-base = <0xaf000 0x42000>; + interrupt-names = "ife"; + interrupts = <0 465 0>; + regulator-names = "camss", "ife0"; + camss-supply = <&titan_top_gdsc>; + ife0-supply = <&ife_0_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <400000000 0 0>, + <558000000 0 0>, + <637000000 0 0>, + <847000000 0 0>, + <950000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <760000000>; + status = "ok"; + }; + + cam_csid0: qcom,csid0@acb3000 { + cell-index = <0>; + compatible = "qcom,csid175"; + reg-names = "csid"; + reg = <0xacb3000 0x1000>; + reg-cam-base = <0xb3000>; + interrupt-names = "csid"; + interrupts = <0 464 0>; + regulator-names = "camss", "ife0"; + camss-supply = <&titan_top_gdsc>; + ife0-supply = <&ife_0_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <400000000 0 0 0 400000000 0 0>, + <400000000 0 0 0 558000000 0 0>, + <480000000 0 0 0 637000000 0 0>, + <600000000 0 0 0 847000000 0 0>, + <600000000 0 0 0 950000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe1: qcom,vfe1@acb6000 { + cell-index = <1>; + compatible = "qcom,vfe175"; + reg-names = "ife", "cam_camnoc"; + reg = <0xacb6000 0x4000>, + <0xac42000 0x5000>; + reg-cam-base = <0xb6000 0x42000>; + interrupt-names = "ife"; + interrupts = <0 467 0>; + regulator-names = "camss", "ife1"; + camss-supply = <&titan_top_gdsc>; + ife1-supply = <&ife_1_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <400000000 0 0>, + <558000000 0 0>, + <637000000 0 0>, + <847000000 0 0>, + <950000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + src-clock-name = "ife_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&clock_camcc CAM_CC_IFE_1_DSP_CLK>; + clock-rates-option = <760000000>; + status = "ok"; + }; + + cam_csid1: qcom,csid1@acba000 { + cell-index = <1>; + compatible = "qcom,csid175"; + reg-names = "csid"; + reg = <0xacba000 0x1000>; + reg-cam-base = <0xba000>; + interrupt-names = "csid"; + interrupts = <0 466 0>; + regulator-names = "camss", "ife1"; + camss-supply = <&titan_top_gdsc>; + ife1-supply = <&ife_1_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <400000000 0 0 0 400000000 0 0>, + <400000000 0 0 0 558000000 0 0>, + <480000000 0 0 0 637000000 0 0>, + <600000000 0 0 0 847000000 0 0>, + <600000000 0 0 0 950000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", + "nominal", "turbo"; + src-clock-name = "ife_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu"; + status = "ok"; + + msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x840 0x620>, + <&apps_smmu 0x860 0x620>, + <&apps_smmu 0xA40 0x620>, + <&apps_smmu 0xA60 0x620>, + <&apps_smmu 0xC40 0x620>, + <&apps_smmu 0xC60 0x620>, + <&apps_smmu 0xE40 0x620>, + <&apps_smmu 0xE60 0x620>; + label = "ife"; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x2180 0x20>, + <&apps_smmu 0x21A0 0x20>; + label = "jpeg"; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_icp_fw { + compatible = "qcom,msm-cam-smmu-fw-dev"; + label="icp"; + memory-region = <&pil_camera_mem>; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x2222 0x0>, + <&apps_smmu 0x2080 0x20>, + <&apps_smmu 0x20A0 0x20>, + <&apps_smmu 0x2100 0x20>, + <&apps_smmu 0x2120 0x20>, + <&apps_smmu 0x20C0 0x0>, + <&apps_smmu 0x2140 0x0>; + label = "icp"; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-firmware { + /* Firmware region is 5MB */ + iova-region-name = "firmware"; + iova-region-start = <0x0>; + iova-region-len = <0x500000>; + iova-region-id = <0x0>; + status = "ok"; + }; + + iova-mem-region-shared { + /* Shared region is 150MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0xc800000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-secondary-heap { + /* Secondary heap region is 1MB long */ + iova-region-name = "secheap"; + iova-region-start = <0x13C00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x4>; + status = "ok"; + }; + + iova-mem-region-io { + /* IO region is approximately 3.3 GB */ + iova-region-name = "io"; + iova-region-start = <0x13E00000>; + iova-region-len = <0xCC100000>; + iova-region-id = <0x3>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x13D00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x2000 0x0>; + label = "cpas-cdm0"; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + label = "cam-secure"; + qcom,secure-cb; + }; + + msm_cam_smmu_fd { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x21C0 0x20>, + <&apps_smmu 0x21E0 0x20>; + label = "fd"; + fd_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_lrme { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x20e0 0x0>, + <&apps_smmu 0x2160 0x0>; + label = "lrme"; + lrme_iova_mem_map: iova-mem-map { + iova-mem-region-shared { + /* Shared region is 100MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x6400000>; + iova-region-id = <0x1>; + status = "ok"; + }; + /* IO region is approximately 3.3 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0xd800000>; + iova-region-len = <0xd2800000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-v2-cdp.dts b/arch/arm/boot/dts/qcom/sm8150-v2-cdp.dts new file mode 100644 index 000000000000..ffeadfafe7c8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-v2-cdp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150-v2.dtsi" +#include "sm8150-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150 V2 CDP"; + compatible = "qcom,sm8150-cdp", "qcom,sm8150", "qcom,cdp"; + qcom,board-id = <1 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-v2-mtp.dts b/arch/arm/boot/dts/qcom/sm8150-v2-mtp.dts new file mode 100644 index 000000000000..e3774ae7060a --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-v2-mtp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150-v2.dtsi" +#include "sm8150-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150 V2 MTP"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-v2-qrd-dvt.dts b/arch/arm/boot/dts/qcom/sm8150-v2-qrd-dvt.dts new file mode 100644 index 000000000000..297bc1c14358 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-v2-qrd-dvt.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150-v2.dtsi" +#include "sm8150-qrd-dvt.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150 V2 QRD DVT"; + compatible = "qcom,sm8150-qrd", "qcom,sm8150", "qcom,qrd"; + qcom,board-id = <0x01000B 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-v2-qrd.dts b/arch/arm/boot/dts/qcom/sm8150-v2-qrd.dts new file mode 100644 index 000000000000..4845a6dc3b38 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-v2-qrd.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150-v2.dtsi" +#include "sm8150-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150 V2 QRD"; + compatible = "qcom,sm8150-qrd", "qcom,sm8150", "qcom,qrd"; + qcom,board-id = <11 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-v2-rumi.dts b/arch/arm/boot/dts/qcom/sm8150-v2-rumi.dts new file mode 100644 index 000000000000..2632844ed686 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-v2-rumi.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/memreserve/ 0x90000000 0x00000100; + +#include "sm8150-v2.dtsi" +#include "sm8150-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150 V2 RUMI"; + compatible = "qcom,sm8150-rumi", "qcom,sm8150", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-v2.dts b/arch/arm/boot/dts/qcom/sm8150-v2.dts new file mode 100644 index 000000000000..eeecde086421 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-v2.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150 v2 SoC"; + compatible = "qcom,sm8150"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-v2.dtsi b/arch/arm/boot/dts/qcom/sm8150-v2.dtsi new file mode 100644 index 000000000000..a94098ec58ca --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-v2.dtsi @@ -0,0 +1,1358 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm8150.dtsi" +#include "sm8150-v2-camera.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150 V2"; + qcom,msm-name = "SM8150 V2"; + qcom,msm-id = <339 0x20000>; +}; + +/* Remove smmu nodes specific to SM8150 */ +/delete-node/ &apps_smmu; +/delete-node/ &kgsl_smmu; + +&soc { + /delete-node/ llcc-bw-opp-table; + /delete-node/ ddr-bw-opp-table; + /delete-node/ suspendable-ddr-bw-opp-table; +}; + +&mdss_mdp { + qcom,fullsize-va-map; + qcom,sde-min-core-ib-kbps = <0>; + qcom,sde-min-llcc-ib-kbps = <0>; +}; + +&mdss_rotator { + smmu_rot_unsec: qcom,smmu_rot_unsec_cb { + compatible = "qcom,smmu_sde_rot_unsec"; + iommus = <&apps_smmu 0x2040 0x0>; + qcom,fullsize-va-map; + }; + smmu_rot_sec: qcom,smmu_rot_sec_cb { + compatible = "qcom,smmu_sde_rot_sec"; + iommus = <&apps_smmu 0x2041 0x0>; + qcom,fullsize-va-map; + }; +}; + +&tmc_etr { + /delete-property/ qcom,smmu-s1-bypass; +}; + +&mdss_dsi0_pll { + compatible = "qcom,mdss_dsi_pll_7nm_v2"; +}; + +&mdss_dsi1_pll { + compatible = "qcom,mdss_dsi_pll_7nm_v2"; +}; + +&spss_utils { + qcom,spss-dev-firmware-name = "spss2d"; /* 8 chars max */ + qcom,spss-test-firmware-name = "spss2t"; /* 8 chars max */ + qcom,spss-prod-firmware-name = "spss2p"; /* 8 chars max */ +}; + +&clock_gcc { + compatible = "qcom,gcc-sm8150-v2", "syscon"; +}; + +&clock_camcc { + compatible = "qcom,camcc-sm8150-v2", "syscon"; +}; + +&clock_dispcc { + compatible = "qcom,dispcc-sm8150-v2", "syscon"; +}; + +&clock_videocc { + compatible = "qcom,videocc-sm8150-v2", "syscon"; +}; + +&clock_npucc { + compatible = "qcom,npucc-sm8150-v2", "syscon"; +}; + +&clock_scc { + compatible = "qcom,scc-sm8150-v2"; +}; + +#include "msm-arm-smmu-sm8150-v2.dtsi" + +&pcie0 { + reg = <0x1c00000 0x4000>, + <0x1c06000 0x1000>, + <0x60000000 0xf1d>, + <0x60000f20 0xa8>, + <0x60001000 0x1000>, + <0x60100000 0x100000>, + <0x60200000 0x100000>, + <0x60300000 0x3d00000>; + + qcom,pcie-phy-ver = <2110>; + + qcom,phy-sequence = <0x0840 0x03 0x0 + 0x0094 0x08 0x0 + 0x0154 0x34 0x0 + 0x016c 0x08 0x0 + 0x0058 0x0f 0x0 + 0x00a4 0x42 0x0 + 0x0110 0x24 0x0 + 0x011c 0x03 0x0 + 0x0118 0xb4 0x0 + 0x010c 0x02 0x0 + 0x01bc 0x11 0x0 + 0x00bc 0x82 0x0 + 0x00d4 0x03 0x0 + 0x00d0 0x55 0x0 + 0x00cc 0x55 0x0 + 0x00b0 0x1a 0x0 + 0x00ac 0x0a 0x0 + 0x00c4 0x68 0x0 + 0x00e0 0x02 0x0 + 0x00dc 0xaa 0x0 + 0x00d8 0xab 0x0 + 0x00b8 0x34 0x0 + 0x00b4 0x14 0x0 + 0x0158 0x01 0x0 + 0x0074 0x06 0x0 + 0x007c 0x16 0x0 + 0x0084 0x36 0x0 + 0x0078 0x06 0x0 + 0x0080 0x16 0x0 + 0x0088 0x36 0x0 + 0x01b0 0x1e 0x0 + 0x01ac 0xb9 0x0 + 0x01b8 0x18 0x0 + 0x01b4 0x94 0x0 + 0x0050 0x07 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x029c 0x12 0x0 + 0x0284 0x35 0x0 + 0x023c 0x11 0x0 + 0x051c 0x03 0x0 + 0x0518 0x1c 0x0 + 0x0524 0x1e 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x05b4 0x04 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0510 0x17 0x0 + 0x04d4 0x54 0x0 + 0x04d8 0x07 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x04fc 0x00 0x0 + 0x04f8 0xc0 0x0 + 0x0460 0x30 0x0 + 0x0464 0xc0 0x0 + 0x05bc 0x0c 0x0 + 0x04dc 0x0d 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x09a4 0x01 0x0 + 0x0c90 0x00 0x0 + 0x0c40 0x01 0x0 + 0x0c48 0x01 0x0 + 0x0c50 0x00 0x0 + 0x0cbc 0x00 0x0 + 0x0ce0 0x58 0x0 + 0x0048 0x90 0x0 + 0x0c1c 0xc1 0x0 + 0x0988 0x88 0x0 + 0x0998 0x0b 0x0 + 0x08dc 0x0d 0x0 + 0x09ec 0x01 0x0 + 0x0800 0x00 0x0 + 0x0844 0x03 0x0>; +}; + +&pcie1 { + reg = <0x1c08000 0x4000>, + <0x1c0e000 0x2000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>, + <0x40200000 0x100000>, + <0x40300000 0x1fd00000>; + + qcom,pcie-phy-ver = <2109>; + + qcom,phy-sequence = <0x0a40 0x03 0x0 + 0x0010 0x00 0x0 + 0x001c 0x31 0x0 + 0x0020 0x01 0x0 + 0x0024 0xde 0x0 + 0x0028 0x07 0x0 + 0x0030 0x4c 0x0 + 0x0034 0x06 0x0 + 0x0048 0x90 0x0 + 0x0058 0x0f 0x0 + 0x0074 0x06 0x0 + 0x0078 0x06 0x0 + 0x007c 0x16 0x0 + 0x0080 0x16 0x0 + 0x0084 0x36 0x0 + 0x0088 0x36 0x0 + 0x0094 0x08 0x0 + 0x00a4 0x42 0x0 + 0x00ac 0x0a 0x0 + 0x00b0 0x1a 0x0 + 0x00b4 0x14 0x0 + 0x00b8 0x34 0x0 + 0x00bc 0x82 0x0 + 0x00c4 0x68 0x0 + 0x00cc 0x55 0x0 + 0x00d0 0x55 0x0 + 0x00d4 0x03 0x0 + 0x00d8 0xab 0x0 + 0x00dc 0xaa 0x0 + 0x00e0 0x02 0x0 + 0x010c 0x02 0x0 + 0x0110 0x24 0x0 + 0x0118 0xb4 0x0 + 0x011c 0x03 0x0 + 0x0154 0x34 0x0 + 0x0158 0x01 0x0 + 0x016c 0x08 0x0 + 0x01ac 0xb9 0x0 + 0x01b0 0x1e 0x0 + 0x01b4 0x94 0x0 + 0x01b8 0x18 0x0 + 0x01bc 0x11 0x0 + 0x023c 0x11 0x0 + 0x0284 0x35 0x0 + 0x029c 0x12 0x0 + 0x0304 0x02 0x0 + 0x0408 0x0c 0x0 + 0x0414 0x03 0x0 + 0x0434 0x7f 0x0 + 0x0444 0x70 0x0 + 0x0460 0x30 0x0 + 0x0464 0x00 0x0 + 0x04d4 0x04 0x0 + 0x04d8 0x07 0x0 + 0x04dc 0x0d 0x0 + 0x04e8 0x00 0x0 + 0x04ec 0x0e 0x0 + 0x04f0 0x4a 0x0 + 0x04f4 0x0f 0x0 + 0x04f8 0xc0 0x0 + 0x04fc 0x00 0x0 + 0x0510 0x17 0x0 + 0x0518 0x1c 0x0 + 0x051c 0x03 0x0 + 0x0524 0x1e 0x0 + 0x0570 0xff 0x0 + 0x0574 0xff 0x0 + 0x0578 0xff 0x0 + 0x057c 0x7f 0x0 + 0x0580 0x66 0x0 + 0x0584 0x24 0x0 + 0x0588 0xe4 0x0 + 0x058c 0xec 0x0 + 0x0590 0x3b 0x0 + 0x0594 0x36 0x0 + 0x0598 0xd4 0x0 + 0x059c 0x54 0x0 + 0x05a0 0xdb 0x0 + 0x05a4 0x3b 0x0 + 0x05a8 0x31 0x0 + 0x05bc 0x0c 0x0 + 0x063c 0x11 0x0 + 0x0684 0x35 0x0 + 0x069c 0x12 0x0 + 0x0704 0x20 0x0 + 0x0808 0x0c 0x0 + 0x0814 0x03 0x0 + 0x0834 0x7f 0x0 + 0x0844 0x70 0x0 + 0x0860 0x30 0x0 + 0x0864 0x00 0x0 + 0x08d4 0x04 0x0 + 0x08d8 0x07 0x0 + 0x08dc 0x0d 0x0 + 0x08e8 0x00 0x0 + 0x08ec 0x0e 0x0 + 0x08f0 0x4a 0x0 + 0x08f4 0x0f 0x0 + 0x08f8 0xc0 0x0 + 0x08fc 0x00 0x0 + 0x0910 0x17 0x0 + 0x0918 0x1c 0x0 + 0x091c 0x03 0x0 + 0x0924 0x1e 0x0 + 0x0970 0xff 0x0 + 0x0974 0xff 0x0 + 0x0978 0xff 0x0 + 0x097c 0x7f 0x0 + 0x0980 0x66 0x0 + 0x0984 0x24 0x0 + 0x0988 0xe4 0x0 + 0x098c 0xec 0x0 + 0x0990 0x3b 0x0 + 0x0994 0x36 0x0 + 0x0998 0xd4 0x0 + 0x099c 0x54 0x0 + 0x09a0 0xdb 0x0 + 0x09a4 0x3b 0x0 + 0x09a8 0x31 0x0 + 0x09bc 0x0c 0x0 + 0x0adc 0x05 0x0 + 0x0b88 0x88 0x0 + 0x0b98 0x0b 0x0 + 0x0ba4 0x01 0x0 + 0x0bec 0x12 0x0 + 0x0e0c 0x0d 0x0 + 0x0e14 0x07 0x0 + 0x0e1c 0xc1 0x0 + 0x0e40 0x01 0x0 + 0x0e48 0x01 0x0 + 0x0e90 0x00 0x0 + 0x0eb4 0x33 0x0 + 0x0ebc 0x00 0x0 + 0x0ee0 0x58 0x0 + 0x0ea4 0x0f 0x0 + 0x0a00 0x00 0x0 + 0x0a44 0x03 0x0>; +}; + +&pcie_ep { + reg = <0x40004000 0x1000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40002000 0x2000>, + <0x01c08000 0x3000>, + <0x01c0e000 0x2000>, + <0x01c0b000 0x1000>; +}; + +&msm_vidc { + qcom,allowed-clock-rates = <240000000 338000000 + 365000000 444000000 533000000>; + + non_secure_cb { + iommus = <&apps_smmu 0x2300 0x60>; + }; + secure_bitstream_cb { + iommus = <&apps_smmu 0x2301 0x4>; + }; + secure_pixel_cb { + iommus = <&apps_smmu 0x2303 0x20>; + }; + secure_non_pixel_cb { + iommus = <&apps_smmu 0x2304 0x60>; + }; +}; + +&msm_fastrpc { + qcom,msm_fastrpc_compute_cb1 { + iommus = <&apps_smmu 0x1001 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb2 { + iommus = <&apps_smmu 0x1002 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb3 { + iommus = <&apps_smmu 0x1003 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb4 { + iommus = <&apps_smmu 0x1004 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb5 { + iommus = <&apps_smmu 0x1005 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb6 { + iommus = <&apps_smmu 0x1006 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb7 { + iommus = <&apps_smmu 0x1007 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb8 { + iommus = <&apps_smmu 0x1008 0x0460>; + }; + + qcom,msm_fastrpc_compute_cb9 { + iommus = <&apps_smmu 0x1009 0x0460>; + }; +}; + +&energy_costs { + CPU_COST_0: core-cost0 { + busy-cost-data = < + 300000 24 + 403200 25 + 499200 27 + 576000 29 + 672000 33 + 768000 37 + 844800 42 + 940800 47 + 1036800 54 + 1113600 59 + 1209600 66 + 1305600 73 + 1382400 79 + 1478400 88 + 1555200 96 + 1632000 105 + 1708800 115 + 1785600 128 + >; + idle-cost-data = < + 18 14 12 + >; + }; + + CPU_COST_1: core-cost1 { + busy-cost-data = < + 710400 165 + 825600 195 + 940800 228 + 1056000 264 + 1171200 301 + 1286400 339 + 1401600 378 + 1497600 411 + 1612800 453 + 1708800 491 + 1804800 534 + 1920000 594 + 2016000 654 + 2131200 740 + 2227200 825 + 2323200 920 + 2419200 1022 + >; + idle-cost-data = < + 80 60 40 + >; + }; + + CPU_COST_2: core-cost2 { + busy-cost-data = < + 825600 227 + 940800 262 + 1056000 302 + 1171200 348 + 1286400 398 + 1401600 451 + 1497600 498 + 1612800 556 + 1708800 606 + 1804800 655 + 1920000 716 + 2016000 766 + 2131200 826 + 2227200 878 + 2323200 933 + 2419200 992 + 2534400 1075 + 2649600 1179 + 2745600 1288 + 2841600 1427 + 2956800 1670 + >; + idle-cost-data = < + 110 90 70 + >; + }; + + CLUSTER_COST_0: cluster-cost0 { + busy-cost-data = < + 300000 3 + 403200 4 + 499200 4 + 576000 4 + 672000 5 + 768000 5 + 844800 6 + 940800 7 + 1036800 8 + 1113600 9 + 1209600 10 + 1305600 11 + 1382400 12 + 1478400 13 + 1555200 14 + 1632000 15 + 1708800 16 + 1785600 17 + >; + idle-cost-data = < + 3 2 1 + >; + }; + + CLUSTER_COST_1: cluster-cost1 { + busy-cost-data = < + 710400 25 + 825600 26 + 940800 27 + 1056000 28 + 1171200 29 + 1286400 30 + 1401600 32 + 1497600 34 + 1612800 37 + 1708800 40 + 1804800 45 + 1920000 50 + 2016000 57 + 2131200 64 + 2227200 74 + 2323200 90 + 2419200 106 + >; + idle-cost-data = < + 3 2 1 + >; + }; + + CLUSTER_COST_2: cluster-cost2 { + busy-cost-data = < + 825600 30 + 940800 33 + 1056000 36 + 1171200 39 + 1286400 42 + 1401600 46 + 1497600 49 + 1612800 55 + 1708800 67 + 1804800 77 + 1920000 87 + 2016000 100 + 2131200 110 + 2227200 120 + 2323200 128 + 2419200 135 + 2534400 140 + 2649600 147 + 2745600 160 + 2841600 180 + 2956800 197 + >; + idle-cost-data = < + 3 2 1 + >; + }; +}; + +#include "sm8150-gpu-v2.dtsi" + +/* GPU overrides */ +&msm_gpu { + /* Updated chip ID */ + qcom,chipid = <0x06040001>; + + /* Power level to start throttling */ + qcom,throttle-pwrlevel = <0>; + + /* Updated Bus Scale Settings */ + qcom,msm-bus,num-cases = <12>; + + /* + * Value for vote is: (DDR freq) * 4 - 5 + * The 5 value is to ensure that there is no rounding errors + * where the total request doesn't divide evenly by the BCM + * DDR bandwidth unit (note, 5 is greater than this unit). + */ + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, // 0 bus=0 + <26 512 0 795000>, // 1 bus=200 + <26 512 0 1195000>, // 2 bus=300 + <26 512 0 1799000>, // 3 bus=451 + <26 512 0 2183000>, // 4 bus=547 + <26 512 0 2719000>, // 5 bus=681 + <26 512 0 3067000>, // 6 bus=768 + <26 512 0 4063000>, // 7 bus=1017 + <26 512 0 5407000>, // 8 bus=1353 + <26 512 0 6215000>, // 9 bus=1555 + <26 512 0 7211000>, // 10 bus=1804 + <26 512 0 8363000>; // 11 bus=2092 + + /delete-property/qcom,initial-pwrlevel; + + operating-points-v2 = <&gpu_opp_table_v2>; + + qcom,gpu-speed-bin = <0x4130 0xe0000000 29>; + + /delete-node/qcom,gpu-pwrlevels; + qcom,gpu-pwrlevel-bins { + #address-cells = <1>; + #size-cells = <0>; + + compatible="qcom,gpu-pwrlevel-bins"; + qcom,gpu-pwrlevels-0 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <0>; + qcom,initial-pwrlevel = <4>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <585000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <499200000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <427000000>; + qcom,bus-freq = <6>; + qcom,bus-min = <5>; + qcom,bus-max = <9>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <345000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <257000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <4>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + qcom,gpu-pwrlevels-1 { + #address-cells = <1>; + #size-cells = <0>; + + qcom,speed-bin = <1>; + qcom,initial-pwrlevel = <5>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <675000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <11>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <585000000>; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <499200000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <427000000>; + qcom,bus-freq = <6>; + qcom,bus-min = <5>; + qcom,bus-max = <9>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <345000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <257000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <4>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + }; + + qcom,l3-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,l3-pwrlevels"; + + qcom,l3-pwrlevel@0 { + reg = <0>; + qcom,l3-freq = <0>; + }; + + qcom,l3-pwrlevel@1 { + reg = <1>; + qcom,l3-freq = <1344000000>; + }; + + qcom,l3-pwrlevel@2 { + reg = <2>; + qcom,l3-freq = <1612800000>; + }; + }; +}; + +&gmu { + reg = <0x2c6a000 0x30000>, + <0xb290000 0x10000>, + <0xb490000 0x10000>; + reg-names = "kgsl_gmu_reg", + "kgsl_gmu_pdc_cfg", + "kgsl_gmu_pdc_seq"; + + qcom,gpu-acd-table { + /* Corresponds to levels in the GPU perf table */ + qcom,acd-enable-by-level = <0x7e>; + qcom,acd-stride = <0x2>; + qcom,acd-num-levels = <0x6>; + + /* ACDCR, ACDTD */ + qcom,acd-data = <0xa02d5ffd 0x00007611 /* LowSVS */ + 0xa02d5ffd 0x00006911 /* SVS */ + 0xa02d5ffd 0x00006111 /* SVS_L1 */ + 0xa02d5ffd 0x00006011 /* SVS_L2 */ + 0x802d5ffd 0x00005411 /* NOM */ + 0x802d5ffd 0x00005411>; /* NOM_L1 */ + }; +}; + +/* NPU overrides */ +&msm_npu { + iommus = <&apps_smmu 0x1081 0x400>; + qcom,npu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,npu-pwrlevels"; + initial-pwrlevel = <5>; + qcom,npu-pwrlevel@0 { + reg = <0>; + vreg = <1>; + clk-freq = <0 + 0 + 0 + 100000000 + 300000000 + 300000000 + 19200000 + 150000000 + 100000000 + 37500000 + 19200000 + 60000000 + 100000000 + 19200000 + 19200000 + 0 + 19200000 + 300000000 + 19200000 + 19200000>; + }; + qcom,npu-pwrlevel@1 { + reg = <1>; + vreg = <2>; + clk-freq = <0 + 0 + 0 + 150000000 + 400000000 + 400000000 + 37500000 + 200000000 + 150000000 + 75000000 + 19200000 + 120000000 + 150000000 + 19200000 + 19200000 + 0 + 19200000 + 400000000 + 19200000 + 19200000>; + }; + qcom,npu-pwrlevel@2 { + reg = <2>; + vreg = <3>; + clk-freq = <0 + 0 + 0 + 200000000 + 487000000 + 487000000 + 37500000 + 300000000 + 200000000 + 150000000 + 19200000 + 240000000 + 200000000 + 19200000 + 19200000 + 0 + 19200000 + 487000000 + 19200000 + 19200000>; + }; + qcom,npu-pwrlevel@3 { + reg = <3>; + vreg = <4>; + clk-freq = <0 + 0 + 0 + 300000000 + 652000000 + 652000000 + 75000000 + 403000000 + 300000000 + 150000000 + 19200000 + 240000000 + 300000000 + 19200000 + 19200000 + 0 + 19200000 + 652000000 + 19200000 + 19200000>; + }; + qcom,npu-pwrlevel@4 { + reg = <4>; + vreg = <6>; + clk-freq = <0 + 0 + 0 + 400000000 + 811000000 + 811000000 + 75000000 + 533000000 + 400000000 + 150000000 + 19200000 + 300000000 + 400000000 + 19200000 + 19200000 + 0 + 19200000 + 811000000 + 19200000 + 19200000>; + }; + qcom,npu-pwrlevel@5 { + reg = <5>; + vreg = <7>; + clk-freq = <0 + 0 + 0 + 400000000 + 908000000 + 908000000 + 75000000 + 533000000 + 400000000 + 150000000 + 19200000 + 300000000 + 400000000 + 19200000 + 19200000 + 0 + 19200000 + 908000000 + 19200000 + 19200000>; + }; + }; +}; + +&soc { + llcc_bw_opp_table: llcc-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ + BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */ + BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */ + BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */ + BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */ + BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */ + BW_OPP_ENTRY(1000, 16); /* 15258 MB/s */ + }; + + ddr_bw_opp_table: ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ + BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ + BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ + BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ + BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ + BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ + BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ + BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */ + BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ + BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ + BW_OPP_ENTRY(2092, 4); /* 7980 MB/s */ + }; + + suspendable_ddr_bw_opp_table: suspendable-ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 0, 4); /* 0 MB/s */ + BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ + BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ + BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ + BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ + BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ + BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ + BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ + BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */ + BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ + BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ + BW_OPP_ENTRY(2092, 4); /* 7980 MB/s */ + }; +}; +&cpu4_computemon { + qcom,core-dev-table = + < 1920000 MHZ_TO_MBPS( 200, 4) >, + < 2793600 MHZ_TO_MBPS(1017, 4) >, + < 3000000 MHZ_TO_MBPS(2092, 4) >; +}; + +&cpu0_llcc_ddr_latmon { + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS( 200, 4) >, + < 768000 MHZ_TO_MBPS( 451, 4) >, + < 1113600 MHZ_TO_MBPS( 547, 4) >, + < 1478400 MHZ_TO_MBPS( 768, 4) >, + < 1632000 MHZ_TO_MBPS(1017, 4) >; +}; + +&cpu4_llcc_ddr_latmon { + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS( 200, 4) >, + < 710400 MHZ_TO_MBPS( 451, 4) >, + < 825600 MHZ_TO_MBPS( 547, 4) >, + < 1056000 MHZ_TO_MBPS( 768, 4) >, + < 1286400 MHZ_TO_MBPS(1017, 4) >, + < 1612800 MHZ_TO_MBPS(1353, 4) >, + < 1804800 MHZ_TO_MBPS(1555, 4) >, + < 2649600 MHZ_TO_MBPS(1804, 4) >, + < 3000000 MHZ_TO_MBPS(2092, 4) >; +}; + +&cpu0_cpu_l3_latmon { + qcom,core-dev-table = + < 300000 300000000 >, + < 499200 403200000 >, + < 576000 499200000 >, + < 672000 614400000 >, + < 768000 710400000 >, + < 940800 806400000 >, + < 1036800 902400000 >, + < 1113600 998400000 >, + < 1209600 1075280000 >, + < 1305600 1171200000 >, + < 1382400 1267200000 >, + < 1478400 1344000000 >, + < 1632000 1536000000 >, + < 1785600 1612800000 >; +}; + +&cpu4_cpu_l3_latmon { + qcom,core-dev-table = + < 300000 300000000 >, + < 825600 614400000 >, + < 1171200 806400000 >, + < 1401600 998400000 >, + < 1708800 1267200000 >, + < 2016000 1344000000 >, + < 2419200 1536000000 >, + < 2841600 1612800000 >; +}; + +&cpu7_cpu_l3_latmon { + qcom,core-dev-table = + < 300000 300000000 >, + < 825600 614400000 >, + < 1171200 806400000 >, + < 1401600 998400000 >, + < 1708800 1267200000 >, + < 2016000 1344000000 >, + < 2419200 1536000000 >, + < 2841600 1612000000 >; +}; + +&cpu0_cpu_llcc_latmon { + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS( 150, 16) >, + < 768000 MHZ_TO_MBPS( 300, 16) >, + < 1478400 MHZ_TO_MBPS( 466, 16) >, + < 1632000 MHZ_TO_MBPS( 600, 16) >; +}; + +&cpu4_cpu_llcc_latmon { + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS( 150, 16) >, + < 710400 MHZ_TO_MBPS( 300, 16) >, + < 1056000 MHZ_TO_MBPS( 466, 16) >, + < 1286400 MHZ_TO_MBPS( 600, 16) >, + < 1804800 MHZ_TO_MBPS( 806, 16) >, + < 2649600 MHZ_TO_MBPS( 933, 16) >, + < 3000000 MHZ_TO_MBPS(1000, 16) >; +}; + +&usb_qmp_dp_phy { + qcom,qmp-phy-init-seq = + ; +}; + +&usb_qmp_phy { + qcom,qmp-phy-init-seq = + ; +}; + +/* qcedev override */ +&qcom_cedev { + qcom_cedev_ns_cb { + iommus = <&apps_smmu 0x512 0>, + <&apps_smmu 0x518 0>, + <&apps_smmu 0x519 0>, + <&apps_smmu 0x51f 0>; + }; + + qcom_cedev_s_cb { + iommus = <&apps_smmu 0x513 0>, + <&apps_smmu 0x51c 0>, + <&apps_smmu 0x51d 0>, + <&apps_smmu 0x51e 0>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-vidc.dtsi b/arch/arm/boot/dts/qcom/sm8150-vidc.dtsi new file mode 100644 index 000000000000..371859ade666 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-vidc.dtsi @@ -0,0 +1,139 @@ +/* Copyright (c) 2018 - 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&soc { + msm_vidc: qcom,vidc@aa00000 { + compatible = "qcom,msm-vidc", "qcom,sm8150-vidc"; + status = "ok"; + reg = <0xaa00000 0x200000>; + interrupts = ; + + /* LLCC Info */ + cache-slice-names = "vidsc0", "vidsc1"; + cache-slices = <&llcc 2>, <&llcc 3>; + + /* Supply */ + iris-ctl-supply = <&mvsc_gdsc>; + vcodec-supply = <&mvs0_gdsc>; + cvp-supply = <&mvs1_gdsc>; + + /* Clocks */ + clock-names = "gcc_video_axic", "gcc_video_axi0", + "gcc_video_axi1", "core_clk", "vcodec_clk", + "cvp_clk"; + clocks = <&clock_gcc GCC_VIDEO_AXIC_CLK>, + <&clock_gcc GCC_VIDEO_AXI0_CLK>, + <&clock_gcc GCC_VIDEO_AXI1_CLK>, + <&clock_videocc VIDEO_CC_MVSC_CORE_CLK>, + <&clock_videocc VIDEO_CC_MVS0_CORE_CLK>, + <&clock_videocc VIDEO_CC_MVS1_CORE_CLK>; + qcom,proxy-clock-names = "gcc_video_axic", + "gcc_video_axi0", "gcc_video_axi1", + "core_clk", "vcodec_clk", "cvp_clk"; + + resets = <&clock_gcc GCC_VIDEO_AXIC_CLK_BCR>, + <&clock_videocc VIDEO_CC_MVSC_CORE_CLK_BCR>, + <&clock_gcc GCC_VIDEO_AXI0_CLK_BCR>, + <&clock_gcc GCC_VIDEO_AXI1_CLK_BCR>; + reset-names = "video_axi_reset", "video_core_reset", + "video_axi0_reset", "video_axi1_reset"; + + qcom,clock-configs = <0x0 0x0 0x0 0x1 0x1 0x1>; + qcom,allowed-clock-rates = <225000000 300000000 + 365000000 432000000 480000000>; + + /* Buses */ + bus_cnoc { + compatible = "qcom,msm-vidc,bus"; + label = "cnoc"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 1000>; + }; + + venus_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-ddr"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "msm-vidc-ddr"; + qcom,bus-range-kbps = <1000 6533000>; + }; + arm9_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-arm9-ddr"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 1000>; + }; + venus_bus_llcc { + compatible = "qcom,msm-vidc,bus"; + label = "venus-llcc"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "msm-vidc-llcc"; + qcom,bus-range-kbps = <1000 6533000>; + }; + + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_ns"; + iommus = + <&apps_smmu 0x1300 0x60>; + buffer-types = <0xfff>; + virtual-addr-pool = <0x25800000 0xba800000>; + }; + + secure_non_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_non_pixel"; + iommus = + <&apps_smmu 0x1304 0x60>; + buffer-types = <0x480>; + virtual-addr-pool = <0x1000000 0x24800000>; + qcom,secure-context-bank; + }; + + secure_bitstream_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_bitstream"; + iommus = + <&apps_smmu 0x1301 0x4>; + buffer-types = <0x241>; + virtual-addr-pool = <0x500000 0xdfb00000>; + qcom,secure-context-bank; + }; + + secure_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_pixel"; + iommus = + <&apps_smmu 0x1303 0x20>; + buffer-types = <0x106>; + virtual-addr-pool = <0x500000 0xdfb00000>; + qcom,secure-context-bank; + }; + + /* Memory Heaps */ + qcom,msm-vidc,mem_cdsp { + compatible = "qcom,msm-vidc,mem-cdsp"; + memory-region = <&cdsp_mem>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150-wcd.dtsi b/arch/arm/boot/dts/qcom/sm8150-wcd.dtsi new file mode 100644 index 000000000000..6b529d6be61b --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150-wcd.dtsi @@ -0,0 +1,235 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&slim_aud { + tavil_codec { + tavil_wcd: wcd_pinctrl@5 { + compatible = "qcom,wcd-pinctrl"; + qcom,num-gpios = <5>; + gpio-controller; + #gpio-cells = <2>; + + us_euro_sw_active: us_euro_sw_wcd_active { + mux { + pins = "gpio1"; + }; + + config { + pins = "gpio1"; + output-high; + }; + }; + + us_euro_sw_sleep: us_euro_sw_wcd_sleep { + mux { + pins = "gpio1"; + }; + + config { + pins = "gpio1"; + output-low; + }; + }; + + spk_1_wcd_en_active: spkr_1_wcd_en_active { + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + output-high; + }; + }; + + spk_1_wcd_en_sleep: spkr_1_wcd_en_sleep { + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + input-enable; + }; + }; + + spk_2_wcd_en_active: spkr_2_sd_n_active { + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + output-high; + }; + }; + + spk_2_wcd_en_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + input-enable; + }; + }; + + hph_en0_wcd_active: hph_en0_wcd_active { + mux { + pins = "gpio4"; + }; + + config { + pins = "gpio4"; + output-high; + }; + }; + + hph_en0_wcd_sleep: hph_en0_wcd_sleep { + mux { + pins = "gpio4"; + }; + + config { + pins = "gpio4"; + output-low; + }; + }; + + hph_en1_wcd_active: hph_en1_wcd_active { + mux { + pins = "gpio5"; + }; + + config { + pins = "gpio5"; + output-high; + }; + }; + + hph_en1_wcd_sleep: hph_en1_wcd_sleep { + mux { + pins = "gpio5"; + }; + + config { + pins = "gpio5"; + output-low; + }; + }; + }; + + wsa_spk_wcd_sd1: msm_cdc_pinctrll { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spk_1_wcd_en_active>; + pinctrl-1 = <&spk_1_wcd_en_sleep>; + }; + + wsa_spk_wcd_sd2: msm_cdc_pinctrlr { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spk_2_wcd_en_active>; + pinctrl-1 = <&spk_2_wcd_en_sleep>; + }; + + tavil_us_euro_switch: msm_cdc_pinctrl_us_euro_sw { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&us_euro_sw_active>; + pinctrl-1 = <&us_euro_sw_sleep>; + }; + + tavil_hph_en0: msm_cdc_pinctrl_hph_en0 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&hph_en0_wcd_active>; + pinctrl-1 = <&hph_en0_wcd_sleep>; + }; + + tavil_hph_en1: msm_cdc_pinctrl_hph_en1 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&hph_en1_wcd_active>; + pinctrl-1 = <&hph_en1_wcd_sleep>; + }; + }; + + pahu_codec { + wcd: wcd_pinctrl { + compatible = "qcom,wcd-pinctrl"; + qcom,num-gpios = <5>; + gpio-controller; + #gpio-cells = <2>; + + spkr_1_wcd_en_active: spkr_1_wcd_en_active { + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + output-high; + }; + }; + + spkr_1_wcd_en_sleep: spkr_1_wcd_en_sleep { + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + input-enable; + }; + }; + + spkr_2_wcd_en_active: spkr_2_sd_n_active { + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + output-high; + }; + }; + + spkr_2_wcd_en_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + input-enable; + }; + }; + }; + + wsa_spkr_wcd_sd1: msm_cdc_pinctrll { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_wcd_en_active>; + pinctrl-1 = <&spkr_1_wcd_en_sleep>; + }; + + wsa_spkr_wcd_sd2: msm_cdc_pinctrlr { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_2_wcd_en_active>; + pinctrl-1 = <&spkr_2_wcd_en_sleep>; + }; + + }; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150.dts b/arch/arm/boot/dts/qcom/sm8150.dts new file mode 100644 index 000000000000..019a3ba946f0 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150 v1 SoC"; + compatible = "qcom,sm8150"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150.dtsi b/arch/arm/boot/dts/qcom/sm8150.dtsi new file mode 100644 index 000000000000..f5e52a2e1f48 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150.dtsi @@ -0,0 +1,4164 @@ +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "skeleton64.dtsi" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} + +/ { + model = "Qualcomm Technologies, Inc. SM8150"; + compatible = "qcom,sm8150"; + qcom,msm-name = "SM8150 V1"; + qcom,msm-id = <339 0x10000>; + interrupt-parent = <&pdc>; + + mem-offline { + compatible = "qcom,mem-offline"; + offline-sizes = <0x1 0x40000000 0x0 0x40000000>, + <0x1 0xc0000000 0x0 0x80000000>; + granule = <512>; + mboxes = <&qmp_aop 0>; + }; + + aliases { + ufshc1 = &ufshc_mem; /* Embedded UFS slot */ + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + pci-domain0 = &pcie0; /* PCIe0 domain */ + pci-domain1 = &pcie1; /* PCIe1 domain */ + mhi0 = &mhi_0; + mhi1 = &mhi_1; + mhi_netdev0 = &mhi_netdev_0; + mhi_netdev2 = &mhi_netdev_2; + }; + + aliases { + serial0 = &qupv3_se12_2uart; + hsuart0 = &qupv3_se13_4uart; + spi0 = &qupv3_se3_spi; + i2c0 = &qupv3_se4_i2c; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cache-size = <0x8000>; + next-level-cache = <&L2_0>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-size = <0x200000>; + cache-level = <3>; + }; + }; + + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_0: l2-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cache-size = <0x8000>; + next-level-cache = <&L2_1>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_100: l2-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cache-size = <0x8000>; + next-level-cache = <&L2_2>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_2: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_200: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_200: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_200: l2-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cache-size = <0x8000>; + next-level-cache = <&L2_3>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_3: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_300: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x8800>; + }; + + L1_D_300: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9000>; + }; + + L2_TLB_300: l2-tlb { + qcom,dump-size = <0x5000>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + cache-size = <0x20000>; + next-level-cache = <&L2_4>; + sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + #cooling-cells = <2>; + L2_4: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + qcom,dump-size = <0x88000>; + }; + + L1_I_400: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x11000>; + }; + + L1_D_400: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + + L1_ITLB_400: l1-itlb { + qcom,dump-size = <0x300>; + }; + + L1_DTLB_400: l1-dtlb { + qcom,dump-size = <0x480>; + }; + + L2_TLB_400: l2-tlb { + qcom,dump-size = <0x7800>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + cache-size = <0x20000>; + next-level-cache = <&L2_5>; + sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + #cooling-cells = <2>; + L2_5: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + qcom,dump-size = <0x88000>; + }; + + L1_I_500: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x11000>; + }; + + L1_D_500: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + + L1_ITLB_500: l1-itlb { + qcom,dump-size = <0x300>; + }; + + L1_DTLB_500: l1-dtlb { + qcom,dump-size = <0x480>; + }; + + L2_TLB_500: l2-tlb { + qcom,dump-size = <0x7800>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + cache-size = <0x20000>; + next-level-cache = <&L2_6>; + sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + #cooling-cells = <2>; + L2_6: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + qcom,dump-size = <0x88000>; + }; + + L1_I_600: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x11000>; + }; + + L1_D_600: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + + L1_ITLB_600: l1-itlb { + qcom,dump-size = <0x300>; + }; + + L1_DTLB_600: l1-dtlb { + qcom,dump-size = <0x480>; + }; + + L2_TLB_600: l2-tlb { + qcom,dump-size = <0x7800>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + cache-size = <0x20000>; + next-level-cache = <&L2_7>; + sched-energy-costs = <&CPU_COST_2 &CLUSTER_COST_2>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + #cooling-cells = <2>; + L2_7: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x80000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + qcom,dump-size = <0x110000>; + }; + + L1_I_700: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x11000>; + }; + + L1_D_700: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + + L1_ITLB_700: l1-itlb { + qcom,dump-size = <0x300>; + }; + + L1_DTLB_700: l1-dtlb { + qcom,dump-size = <0x480>; + }; + + L2_TLB_700: l2-tlb { + qcom,dump-size = <0x7800>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + }; + + cluster2 { + core0 { + cpu = <&CPU7>; + }; + }; + }; + }; + + energy_costs: energy-costs { + compatible = "sched-energy"; + + CPU_COST_0: core-cost0 { + busy-cost-data = < + 300000 28 + 403200 30 + 480000 33 + 576000 37 + 672000 42 + 768000 47 + 864000 54 + 979200 63 + 1075200 70 + 1171200 79 + 1267200 88 + >; + idle-cost-data = < + 18 14 12 + >; + }; + + CPU_COST_1: core-cost1 { + busy-cost-data = < + 576000 133 + 672000 152 + 768000 175 + 864000 202 + 960000 233 + 1056000 267 + 1152000 304 + 1248000 344 + 1344000 386 + 1420800 421 + 1497600 458 + 1593600 505 + 1689600 560 + 1785600 622 + 1862400 678 + 1939200 740 + 2016000 807 + >; + idle-cost-data = < + 80 60 40 + >; + }; + + CPU_COST_2: core-cost2 { + busy-cost-data = < + 691200 171 + 768000 195 + 864000 230 + 940800 261 + 1017600 294 + 1113600 337 + 1190400 373 + 1286400 418 + 1363200 455 + 1459200 503 + 1536000 545 + 1632000 602 + 1728000 666 + 1824000 739 + 1900800 806 + 1977600 879 + 2054400 960 + >; + idle-cost-data = < + 110 90 70 + >; + }; + + CLUSTER_COST_0: cluster-cost0 { + busy-cost-data = < + 300000 3 + 403200 4 + 480000 4 + 576000 4 + 672000 5 + 768000 5 + 864000 6 + 979200 7 + 1075200 8 + 1171200 9 + 1267200 10 + >; + idle-cost-data = < + 3 2 1 + >; + }; + + CLUSTER_COST_1: cluster-cost1 { + busy-cost-data = < + 576000 25 + 672000 26 + 768000 27 + 864000 28 + 960000 29 + 1056000 30 + 1152000 32 + 1248000 34 + 1344000 37 + 1420800 40 + 1497600 45 + 1593600 50 + 1689600 57 + 1785600 64 + 1862400 74 + 1939200 90 + 2016000 106 + + >; + idle-cost-data = < + 3 2 1 + >; + }; + + CLUSTER_COST_2: cluster-cost2 { + busy-cost-data = < + 691200 30 + 768000 33 + 864000 36 + 940800 39 + 1017600 42 + 1113600 46 + 1190400 49 + 1286400 55 + 1363200 67 + 1459200 77 + 1536000 87 + 1632000 100 + 1728000 110 + 1824000 120 + 1900800 128 + 1977600 135 + 2054400 140 + >; + idle-cost-data = < + 3 2 1 + >; + }; + }; /* energy-costs */ + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 cgroup.memory=nokmem,nosocket"; + }; + + soc: soc { }; + + firmware: firmware { + android { + compatible = "android,firmware"; + shared_meta: vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo,odm"; + }; + android_q_fstab: fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/1d84000.sdhci/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + odm { + compatible = "android,odm"; + dev = "/dev/block/platform/soc/8804000.sdhci/by-name/odm"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp_mem { + no-map; + reg = <0x0 0x85700000 0x0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_mem { + no-map; + reg = <0x0 0x85e00000 0x0 0x140000>; + }; + + smem_region: smem { + no-map; + reg = <0x0 0x86000000 0x0 0x200000>; + }; + + removed_regions: removed_regions { + no-map; + reg = <0x0 0x86200000 0x0 0x5500000>; + }; + + pil_camera_mem: camera_region { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x8b700000 0x0 0x500000>; + }; + + pil_wlan_fw_mem: pil_wlan_fw_region { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x8bc00000 0x0 0x180000>; + }; + + pil_npu_mem: pil_npu_region { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x8bd80000 0x0 0x80000>; + }; + + pil_adsp_mem: pil_adsp_region { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x8be00000 0x0 0x1a00000>; + }; + + pil_modem_mem: modem_region { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x8d800000 0x0 0x9600000>; + }; + + pil_video_mem: pil_video_region { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x96e00000 0x0 0x500000>; + }; + + pil_slpi_mem: pil_slpi_region { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x97300000 0x0 0x1400000>; + }; + + pil_ipa_fw_mem: pil_ipa_fw_region { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x98700000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: pil_ipa_gsi_region { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x98710000 0x0 0x5000>; + }; + + pil_gpu_mem: pil_gpu_region { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x98715000 0x0 0x2000>; + }; + + pil_spss_mem: pil_spss_region { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x98800000 0x0 0x100000>; + }; + + pil_cdsp_mem: cdsp_regions { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x98900000 0x0 0x1400000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x9e400000 0 0x1400000>; + }; + + cdsp_sec_mem: cdsp_sec_regions { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0xa4c00000 0x0 0x3c00000>; + }; + + cont_splash_memory: cont_splash_region { + reg = <0x0 0x9c000000 0x0 0x02400000>; + label = "cont_splash_region"; + }; + + disp_rdump_memory: disp_rdump_region { + reg = <0x0 0x9c000000 0x0 0x02400000>; + label = "disp_rdump_region"; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + cdsp_mem: cdsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x400000>; + }; + + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; + }; + + secure_display_memory: secure_display_region { /* Secure UI */ + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xA000000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x2400000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2800000>; + linux,cma-default; + }; + }; + + vendor: vendor { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + }; +}; + +#include "sm8150-gdsc.dtsi" + +#include "sm8150-sde-pll.dtsi" +#include "sm8150-sde.dtsi" +#include "msm-rdbg.dtsi" + +#include "sm8150-camera.dtsi" + +#include "msm-qvr-external.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + spss_utils: qcom,spss_utils { + compatible = "qcom,spss-utils"; + /* spss fuses physical address */ + qcom,spss-fuse1-addr = <0x007841c4>; + qcom,spss-fuse1-bit = <27>; + qcom,spss-fuse2-addr = <0x007841c4>; + qcom,spss-fuse2-bit = <26>; + qcom,spss-dev-firmware-name = "spss1d"; /* 8 chars max */ + qcom,spss-test-firmware-name = "spss1t"; /* 8 chars max */ + qcom,spss-prod-firmware-name = "spss1p"; /* 8 chars max */ + qcom,spss-debug-reg-addr = <0x01886020>; + qcom,spss-emul-type-reg-addr = <0x01fc8004>; + status = "ok"; + }; + + qcom,spcom { + compatible = "qcom,spcom"; + + /* predefined channels, remote side is server */ + qcom,spcom-ch-names = "sp_kernel", "sp_ssr"; + status = "ok"; + }; + + jtag_mm0: jtagmm@7040000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7040000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU0>; + }; + + jtag_mm1: jtagmm@7140000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7140000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU1>; + }; + + jtag_mm2: jtagmm@7240000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7240000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU2>; + }; + + jtag_mm3: jtagmm@7340000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7340000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU3>; + }; + + jtag_mm4: jtagmm@7440000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7440000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU4>; + }; + + jtag_mm5: jtagmm@7540000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7540000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU5>; + }; + + jtag_mm6: jtagmm@7640000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7640000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU6>; + }; + + jtag_mm7: jtagmm@7740000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7740000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU7>; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17a60000 0x100000>; /* GICR * 8 */ + interrupts = <1 9 4>; + interrupt-parent = <&intc>; + }; + + gict: gict@17a20000 { + compatible = "arm,gic-600-erp"; + reg = <0x17a20000 0x10000>; + reg-names = "gict-base"; + interrupt-config = <46 17>; + interrupt-names = "gict-fault", "gict-err"; + interrupts = , + ; + }; + + pdc: interrupt-controller@0xb220000{ + compatible = "qcom,pdc-sm8150"; + reg = <0xb220000 0x400>; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 1 0xf08>, + <1 2 0xf08>, + <1 3 0xf08>, + <1 0 0xf08>; + clock-frequency = <19200000>; + }; + + timer@0x17c20000{ + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17c20000 0x1000>; + clock-frequency = <19200000>; + + frame@0x17c21000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 6 0x4>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0x17c23000 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0x17c25000 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0x17c26000 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0x17c29000 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0x17c2b000 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0x17c2d000 0x1000>; + status = "disabled"; + }; + }; + + llcc_pmu: llcc-pmu@90cc000 { + compatible = "qcom,qcom-llcc-pmu"; + reg = <0x090cc000 0x300>; + reg-names = "lagg-base"; + }; + + llcc_bw_opp_table: llcc-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ + BW_OPP_ENTRY( 200, 16); /* 3051 MB/s */ + BW_OPP_ENTRY( 403, 16); /* 6149 MB/s */ + BW_OPP_ENTRY( 533, 16); /* 8132 MB/s */ + BW_OPP_ENTRY( 666, 16); /* 10162 MB/s */ + BW_OPP_ENTRY( 777, 16); /* 11856 MB/s */ + }; + + cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x90b6400 0x300>, <0x90b6300 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_cpu_llcc_bw>; + qcom,count-unit = <0x10000>; + }; + + ddr_bw_opp_table: ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ + BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ + BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ + BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ + BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ + BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ + BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ + BW_OPP_ENTRY(1296, 4); /* 4943 MB/s */ + BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ + BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ + BW_OPP_ENTRY(2092, 4); /* 7980 MB/s */ + }; + + cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@90cd000 { + compatible = "qcom,bimc-bwmon5"; + reg = <0x90cd000 0x1000>; + reg-names = "base"; + interrupts = ; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_llcc_ddr_bw>; + qcom,count-unit = <0x10000>; + }; + + suspendable_ddr_bw_opp_table: suspendable-ddr-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 0, 4); /* 0 MB/s */ + BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ + BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ + BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ + BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ + BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ + BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ + BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ + BW_OPP_ENTRY(1296, 4); /* 4943 MB/s */ + BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ + BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ + BW_OPP_ENTRY(2092, 4); /* 7980 MB/s */ + }; + + npu_npu_ddr_bw: qcom,npu-npu-ddr-bw { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = ; + operating-points-v2 = <&suspendable_ddr_bw_opp_table>; + }; + + npu_npu_ddr_bwmon: qcom,npu-npu-ddr-bwmon@9960300 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x9960300 0x300>, <0x9960200 0x200>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&npu_npu_ddr_bw>; + qcom,count-unit = <0x10000>; + }; + + cdsp_cdsp_l3_lat: qcom,cdsp-cdsp-l3-lat { + compatible = "devfreq-simple-dev"; + clock-names = "devfreq_clk"; + clocks = <&clock_cpucc L3_MISC_VOTE_CLK>; + governor = "powersave"; + }; + + cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { + compatible = "devfreq-simple-dev"; + clock-names = "devfreq_clk"; + clocks = <&clock_cpucc L3_CLUSTER0_VOTE_CLK>; + governor = "performance"; + }; + + cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = + < 300000 300000000 >, + < 480000 403200000 >, + < 672000 480000000 >, + < 768000 576000000 >, + < 864000 672000000 >, + < 979200 768000000 >, + < 1075200 864000000 >, + < 1267200 960000000 >; + }; + + cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat { + compatible = "devfreq-simple-dev"; + clock-names = "devfreq_clk"; + clocks = <&clock_cpucc L3_CLUSTER1_VOTE_CLK>; + governor = "performance"; + }; + + cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6>; + qcom,target-dev = <&cpu4_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = + < 300000 300000000 >, + < 768000 576000000 >, + < 1152000 768000000 >, + < 1344000 960000000 >, + < 1689600 1228800000 >, + < 2016000 1344000000 >; + }; + + cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat { + compatible = "devfreq-simple-dev"; + clock-names = "devfreq_clk"; + clocks = <&clock_cpucc L3_CLUSTER2_VOTE_CLK>; + governor = "performance"; + }; + + cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU7>; + qcom,target-dev = <&cpu7_cpu_l3_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,core-dev-table = + < 300000 300000000 >, + < 768000 576000000 >, + < 1152000 768000000 >, + < 1344000 960000000 >, + < 1689600 1228800000 >, + < 2016000 1344000000 >; + }; + + cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_cpu_llcc_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS(150, 16) >, + < 768000 MHZ_TO_MBPS(200, 16) >, + < 1075200 MHZ_TO_MBPS(403, 16) >, + < 1267200 MHZ_TO_MBPS(403, 16) >; + }; + + cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&llcc_bw_opp_table>; + }; + + cpu4_cpu_llcc_latmon: qcom,cpu4-cpu-llcc-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&cpu4_cpu_llcc_lat>; + qcom,cachemiss-ev = <0x2A>; + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS(150, 16) >, + < 576000 MHZ_TO_MBPS(200, 16) >, + < 768000 MHZ_TO_MBPS(403, 16) >, + < 960000 MHZ_TO_MBPS(403, 16) >, + < 1248000 MHZ_TO_MBPS(533, 16) >, + < 1728000 MHZ_TO_MBPS(666, 16) >, + < 2016000 MHZ_TO_MBPS(777, 16) >; + }; + + cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_llcc_ddr_lat>; + qcom,cachemiss-ev = <0x1000>; + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS( 200, 4) >, + < 768000 MHZ_TO_MBPS( 451, 4) >, + < 1075200 MHZ_TO_MBPS( 547, 4) >, + < 1267200 MHZ_TO_MBPS( 768, 4) >; + }; + + cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&cpu4_llcc_ddr_lat>; + qcom,cachemiss-ev = <0x1000>; + qcom,core-dev-table = + < 300000 MHZ_TO_MBPS( 200, 4) >, + < 576000 MHZ_TO_MBPS( 451, 4) >, + < 768000 MHZ_TO_MBPS( 547, 4) >, + < 960000 MHZ_TO_MBPS( 768, 4) >, + < 1248000 MHZ_TO_MBPS(1017, 4) >, + < 1728000 MHZ_TO_MBPS(1555, 4) >, + < 2016000 MHZ_TO_MBPS(1804, 4) >, + < 2054400 MHZ_TO_MBPS(2092, 4) >; + }; + + cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + operating-points-v2 = <&ddr_bw_opp_table>; + }; + + cpu4_computemon: qcom,cpu4-computemon { + compatible = "qcom,arm-cpu-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&cpu4_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1593600 MHZ_TO_MBPS( 200, 4) >, + < 2016000 MHZ_TO_MBPS(1017, 4) >, + < 2054400 MHZ_TO_MBPS(2092, 4) >; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = <1 5 4>; + }; + + qcom,msm-imem@146bf000 { + compatible = "qcom,msm-imem"; + reg = <0x146bf000 0x1000>; + ranges = <0x0 0x146bf000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 32>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 12>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 200>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 200>; + }; + }; + + restart@c264000 { + compatible = "qcom,pshold"; + reg = <0xc264000 0x4>, + <0x1fd3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + qcom,aop-ddr-msgs { + compatible = "qcom,aop-ddr-msgs"; + mboxes = <&qmp_aop 0>; + mbox-name = "restart-ddr-mbox"; + }; + + qcom,aop-ddrss-cmds { + compatible = "qcom,aop-ddrss-cmds"; + mboxes = <&qmp_aop 0>; + mbox-name = "ddrss-cmds-mbox"; + }; + + qcom,mpm2-sleep-counter@0xc221000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xc221000 0x1000>; + clock-frequency = <32768>; + }; + + bus_proxy_client: qcom,bus_proxy_client { + compatible = "qcom,bus-proxy-client"; + qcom,msm-bus,name = "bus-proxy-client"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <5>; + qcom,msm-bus,vectors-KBps = + , + , + , + , + , + , + , + , + , + ; + status = "ok"; + }; + + keepalive_opp_table: keepalive-opp-table { + compatible = "operating-points-v2"; + opp-1 { + opp-hz = /bits/ 64 < 1 >; + }; + }; + + snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <1 627>; + qcom,active-only; + status = "ok"; + operating-points-v2 = <&keepalive_opp_table>; + }; + + cdsp_keepalive: qcom,cdsp_keepalive { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <154 10070>; + qcom,active-only; + status = "ok"; + operating-points-v2 = <&keepalive_opp_table>; + }; + + clock_rpmh: qcom,rpmhclk { + compatible = "qcom,rpmh-clk-sm8150"; + mboxes = <&apps_rsc 0>; + mbox-names = "apps"; + #clock-cells = <1>; + }; + + clock_aop: qcom,aopclk { + compatible = "qcom,aop-qmp-clk"; + #clock-cells = <1>; + mboxes = <&qmp_aop 0>; + mbox-names = "qdss_clk"; + }; + + clock_gcc: qcom,gcc { + compatible = "qcom,gcc-sm8150", "syscon"; + reg = <0x100000 0x1f0000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_videocc: qcom,videocc@ab00000 { + compatible = "qcom,videocc-sm8150", "syscon"; + reg = <0xab00000 0x10000>; + reg-names = "cc_base"; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + clock-names = "cfg_ahb_clk"; + clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_camcc: qcom,camcc { + compatible = "qcom,camcc-sm8150", "syscon"; + reg = <0xad00000 0x10000>; + reg-names = "cc_base"; + vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + clock-names = "cfg_ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + + qcom,cam_cc_csi0phytimer_clk_src-opp-handle = <&cam_csiphy0>; + qcom,cam_cc_csi1phytimer_clk_src-opp-handle = <&cam_csiphy1>; + qcom,cam_cc_csi2phytimer_clk_src-opp-handle = <&cam_csiphy2>; + qcom,cam_cc_csi3phytimer_clk_src-opp-handle = <&cam_csiphy3>; + qcom,cam_cc_cci_0_clk_src-opp-handle = <&cam_cci0>; + qcom,cam_cc_cci_1_clk_src-opp-handle = <&cam_cci1>; + qcom,cam_cc_ife_0_csid_clk_src-opp-handle = <&cam_csid0>; + qcom,cam_cc_ife_0_clk_src-opp-handle = <&cam_vfe0>; + qcom,cam_cc_ife_1_csid_clk_src-opp-handle = <&cam_csid1>; + qcom,cam_cc_ife_1_clk_src-opp-handle = <&cam_vfe1>; + qcom,cam_cc_ife_lite_0_csid_clk_src-opp-handle = + <&cam_csid_lite0>; + qcom,cam_cc_ife_lite_1_csid_clk_src-opp-handle = + <&cam_csid_lite1>; + qcom,cam_cc_ife_lite_0_clk_src-opp-handle = <&cam_vfe_lite0>; + qcom,cam_cc_ife_lite_1_clk_src-opp-handle = <&cam_vfe_lite1>; + qcom,cam_cc_icp_clk_src-opp-handle = <&cam_a5>; + qcom,cam_cc_ipe_0_clk_src-opp-handle = <&cam_ipe0>; + qcom,cam_cc_bps_clk_src-opp-handle = <&cam_bps>; + + #clock-cells = <1>; + }; + + clock_dispcc: qcom,dispcc { + compatible = "qcom,dispcc-sm8150", "syscon"; + reg = <0xaf00000 0x20000>; + reg-names = "cc_base"; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + clock-names = "cfg_ahb_clk"; + clocks = <&clock_gcc GCC_DISP_AHB_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_npucc: qcom,npucc { + compatible = "qcom,npucc-sm8150", "syscon"; + reg = <0x9910000 0x10000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_gdsc-supply = <&npu_core_gdsc>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_gpucc: qcom,gpucc { + compatible = "qcom,gpucc-sm8150", "syscon"; + reg = <0x2c90000 0x9000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + qcom,gpu_cc_gmu_clk_src-opp-handle = <&gmu>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_scc: qcom,scc@2b10000 { + compatible = "qcom,scc-sm8150"; + reg = <0x2b10000 0x30000>; + vdd_scc_cx-supply = <&pm8150_l8_level>; + #clock-cells = <1>; + status = "disabled"; + }; + + cpucc_debug: syscon@182a0018 { + compatible = "syscon"; + reg = <0x182a0018 0x4>; + }; + + mccc_debug: syscon@90b0000 { + compatible = "syscon"; + reg = <0x90b0000 0x1000>; + }; + + clock_cpucc: qcom,cpucc { + compatible = "qcom,clk-cpu-osm"; + reg = <0x18321000 0x1400>, + <0x18323000 0x1400>, + <0x18325800 0x1400>, + <0x18327800 0x1400>; + reg-names = "osm_l3_base", "osm_pwrcl_base", + "osm_perfcl_base", "osm_perfpcl_base"; + l3-devs = <&cpu0_cpu_l3_lat &cpu4_cpu_l3_lat &cdsp_cdsp_l3_lat + &cpu7_cpu_l3_lat>; + + #clock-cells = <1>; + }; + + clock_debugcc: qcom,cc-debug { + compatible = "qcom,debugcc-sm8150"; + qcom,gcc = <&clock_gcc>; + qcom,videocc = <&clock_videocc>; + qcom,camcc = <&clock_camcc>; + qcom,dispcc = <&clock_dispcc>; + qcom,npucc = <&clock_npucc>; + qcom,gpucc = <&clock_gpucc>; + qcom,cpucc = <&cpucc_debug>; + qcom,mccc = <&mccc_debug>; + clock-names = "xo_clk_src"; + clocks = <&clock_rpmh RPMH_CXO_CLK>; + #clock-cells = <1>; + }; + + spmi_bus: qcom,spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0x1100>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>, + <0xe700000 0xa0000>, + <0xc40a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + spmi_debug_bus: qcom,spmi-debug@6b22000 { + compatible = "qcom,spmi-pmic-arb-debug"; + reg = <0x6b22000 0x60>, <0x7820a8 4>; + reg-names = "core", "fuse"; + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + qcom,fuse-disable-bit = <24>; + #address-cells = <2>; + #size-cells = <0>; + status = "disabled"; + + qcom,pm8150-debug@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8150-debug@1 { + compatible = "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8150b-debug@2 { + compatible = "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8150b-debug@3 { + compatible = "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8150l-debug@4 { + compatible = "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8150l-debug@5 { + compatible = "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + }; + + eud: qcom,msm-eud@88e0000 { + compatible = "qcom,msm-eud"; + interrupt-names = "eud_irq"; + interrupts = ; + reg = <0x88e0000 0x2000>; + reg-names = "eud_base"; + status = "ok"; + }; + + pil_modem: qcom,mss@4080000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x4080000 0x100>; + + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + vdd_mss-supply = <&pm8150_s1_level>; + qcom,vdd_mss-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx", "vdd_mss"; + + qcom,firmware-name = "modem"; + memory-region = <&pil_modem_mem>; + qcom,proxy-timeout-ms = <10000>; + qcom,sysmon-id = <0>; + qcom,minidump-id = <3>; + qcom,aux-minidump-ids = <4>; + qcom,ssctl-instance-id = <0x12>; + qcom,pas-id = <4>; + qcom,smem-id = <421>; + qcom,signal-aop; + qcom,complete-ramdump; + + /* Inputs from mss */ + interrupts-extended = <&pdc 0 266 1>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "mss-pil"; + }; + + qcom,lpass@17300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x17300000 0x00100>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx"; + + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <1>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,sysmon-id = <1>; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + + /* Inputs from lpass */ + interrupts-extended = <&pdc 0 162 1>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "adsp-pil"; + }; + + pil_ssc: qcom,ssc@5c00000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x5c00000 0x4000>; + + vdd_cx-supply = <&pm8150_l8_level>; + qcom,vdd_cx-uV-uA = ; + vdd_mx-supply = <&pm8150_l4_level>; + qcom,vdd_mx-uV-uA = ; + + qcom,proxy-reg-names = "vdd_cx", "vdd_mx"; + qcom,keep-proxy-regs-on; + + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <12>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <424>; + qcom,sysmon-id = <3>; + qcom,ssctl-instance-id = <0x16>; + qcom,firmware-name = "slpi"; + status = "ok"; + memory-region = <&pil_slpi_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + + /* Inputs from ssc */ + interrupts-extended = <&pdc 0 494 1>, + <&dsps_smp2p_in 0 0>, + <&dsps_smp2p_in 2 0>, + <&dsps_smp2p_in 1 0>, + <&dsps_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to ssc */ + qcom,smem-states = <&dsps_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "slpi-pil"; + }; + + qcom,spss@1880000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x188101c 0x4>, + <0x1881024 0x4>, + <0x1881028 0x4>, + <0x188103c 0x4>, + <0x1882014 0x4>; + reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", + "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2"; + interrupts = <0 352 1>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_mx-uV = ; + + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + qcom,pil-generic-irq-handler; + status = "ok"; + qcom,signal-aop; + qcom,complete-ramdump; + + qcom,pas-id = <14>; + qcom,proxy-timeout-ms = <10000>; + qcom,firmware-name = "spss"; + memory-region = <&pil_spss_mem>; + qcom,spss-scsr-bits = <24 25>; + + mboxes = <&qmp_aop 0>; + mbox-names = "spss-pil"; + }; + + wdog: qcom,wdt@17c10000{ + compatible = "qcom,msm-watchdog"; + reg = <0x17c10000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 0 0>, <0 1 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + qcom,scandump-sizes = <0x10100 0x10100 0x10100 0x10100 + 0x18100 0x18100 0x18100 0x18100>; + }; + + qcom,npu@0x9800000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x9800000 0x800000>; + + status = "ok"; + qcom,pas-id = <23>; + qcom,firmware-name = "npu"; + + memory-region = <&pil_npu_mem>; + }; + + qcom,turing@8300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x8300000 0x100000>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <18>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <601>; + qcom,sysmon-id = <7>; + qcom,ssctl-instance-id = <0x17>; + qcom,firmware-name = "cdsp"; + memory-region = <&pil_cdsp_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + + qcom,msm-bus,name = "pil-cdsp"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <154 10070 0 0>, + <154 10070 0 1>; + + /* Inputs from turing */ + interrupts-extended = <&pdc 0 578 1>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "cdsp-pil"; + }; + + qcom,venus@aae0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xaae0000 0x4000>; + + vdd-supply = <&mvsc_gdsc>; + qcom,proxy-reg-names = "vdd"; + qcom,complete-ramdump; + + clocks = <&clock_videocc VIDEO_CC_XO_CLK>, + <&clock_videocc VIDEO_CC_MVSC_CORE_CLK>, + <&clock_videocc VIDEO_CC_IRIS_AHB_CLK>; + clock-names = "xo", "core", "ahb"; + qcom,proxy-clock-names = "xo", "core", "ahb"; + + qcom,core-freq = <200000000>; + qcom,ahb-freq = <200000000>; + + qcom,pas-id = <9>; + qcom,msm-bus,name = "pil-venus"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <63 512 0 0>, + <63 512 0 304000>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&pil_video_mem>; + }; + + kryo-erp { + compatible = "arm,arm64-kryo-cpu-erp"; + interrupts = <1 6 4>, + <1 7 4>, + <0 34 4>, + <0 35 4>; + + interrupt-names = "l1-l2-faultirq", + "l1-l2-errirq", + "l3-scu-errirq", + "l3-scu-faultirq"; + }; + + qcom,chd_sliver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x18000058 0x18010058 + 0x18020058 0x18030058>; + qcom,config-arr = <0x18000060 0x18010060 + 0x18020060 0x18030060>; + }; + + qcom,chd_gold { + compatible = "qcom,core-hang-detect"; + label = "gold"; + qcom,threshold-arr = <0x18040058 0x18050058 + 0x18060058 0x18070058>; + qcom,config-arr = <0x18040060 0x18050060 + 0x18060060 0x18070060>; + }; + + qcom,ghd { + compatible = "qcom,gladiator-hang-detect-v3"; + qcom,threshold-arr = <0x17e0041C>; + qcom,config-reg = <0x17e00434>; + }; + + qcom,llcc@9200000 { + compatible = "qcom,llcc-core", "syscon", "simple-mfd"; + reg = <0x9200000 0x450000>; + reg-names = "llcc_base"; + qcom,llcc-banks-off = <0x0 0x80000 0x100000 0x180000>; + qcom,llcc-broadcast-off = <0x400000>; + + llcc: qcom,sm8150-llcc { + compatible = "qcom,sm8150-llcc"; + #cache-cells = <1>; + max-slices = <32>; + cap-based-alloc-and-pwr-collapse; + }; + + qcom,llcc-perfmon { + compatible = "qcom,llcc-perfmon"; + + clocks = <&clock_aop QDSS_CLK>; + clock-names = "qdss_clk"; + }; + + qcom,llcc-erp { + compatible = "qcom,llcc-erp"; + }; + + qcom,llcc-amon { + compatible = "qcom,llcc-amon"; + }; + }; + + ssc_sensors: qcom,msm-ssc-sensors { + compatible = "qcom,msm-ssc-sensors"; + status = "ok"; + qcom,firmware-name = "slpi"; + }; + + cpuss_dump { + compatible = "qcom,cpuss-dump"; + + qcom,l1_i_cache0 { + qcom,dump-node = <&L1_I_0>; + qcom,dump-id = <0x60>; + }; + + qcom,l1_i_cache1 { + qcom,dump-node = <&L1_I_100>; + qcom,dump-id = <0x61>; + }; + + qcom,l1_i_cache2 { + qcom,dump-node = <&L1_I_200>; + qcom,dump-id = <0x62>; + }; + + qcom,l1_i_cache3 { + qcom,dump-node = <&L1_I_300>; + qcom,dump-id = <0x63>; + }; + + qcom,l1_i_cache100 { + qcom,dump-node = <&L1_I_400>; + qcom,dump-id = <0x64>; + }; + + qcom,l1_i_cache101 { + qcom,dump-node = <&L1_I_500>; + qcom,dump-id = <0x65>; + }; + + qcom,l1_i_cache102 { + qcom,dump-node = <&L1_I_600>; + qcom,dump-id = <0x66>; + }; + + qcom,l1_i_cache103 { + qcom,dump-node = <&L1_I_700>; + qcom,dump-id = <0x67>; + }; + + qcom,l1_d_cache0 { + qcom,dump-node = <&L1_D_0>; + qcom,dump-id = <0x80>; + }; + + qcom,l1_d_cache1 { + qcom,dump-node = <&L1_D_100>; + qcom,dump-id = <0x81>; + }; + + qcom,l1_d_cache2 { + qcom,dump-node = <&L1_D_200>; + qcom,dump-id = <0x82>; + }; + + qcom,l1_d_cache3 { + qcom,dump-node = <&L1_D_300>; + qcom,dump-id = <0x83>; + }; + + qcom,l1_d_cache100 { + qcom,dump-node = <&L1_D_400>; + qcom,dump-id = <0x84>; + }; + + qcom,l1_d_cache101 { + qcom,dump-node = <&L1_D_500>; + qcom,dump-id = <0x85>; + }; + + qcom,l1_d_cache102 { + qcom,dump-node = <&L1_D_600>; + qcom,dump-id = <0x86>; + }; + + qcom,l1_d_cache103 { + qcom,dump-node = <&L1_D_700>; + qcom,dump-id = <0x87>; + }; + + qcom,l1_i_tlb_dump400 { + qcom,dump-node = <&L1_ITLB_400>; + qcom,dump-id = <0x24>; + }; + + qcom,l1_i_tlb_dump500 { + qcom,dump-node = <&L1_ITLB_500>; + qcom,dump-id = <0x25>; + }; + + qcom,l1_i_tlb_dump600 { + qcom,dump-node = <&L1_ITLB_600>; + qcom,dump-id = <0x26>; + }; + + qcom,l1_i_tlb_dump700 { + qcom,dump-node = <&L1_ITLB_700>; + qcom,dump-id = <0x27>; + }; + + qcom,l1_d_tlb_dump400 { + qcom,dump-node = <&L1_DTLB_400>; + qcom,dump-id = <0x44>; + }; + + qcom,l1_d_tlb_dump500 { + qcom,dump-node = <&L1_DTLB_500>; + qcom,dump-id = <0x45>; + }; + + qcom,l1_d_tlb_dump600 { + qcom,dump-node = <&L1_DTLB_600>; + qcom,dump-id = <0x46>; + }; + + qcom,l1_d_tlb_dump700 { + qcom,dump-node = <&L1_DTLB_700>; + qcom,dump-id = <0x47>; + }; + + qcom,l2_cache_dump400 { + qcom,dump-node = <&L2_4>; + qcom,dump-id = <0xc4>; + }; + + qcom,l2_cache_dump500 { + qcom,dump-node = <&L2_5>; + qcom,dump-id = <0xc5>; + }; + + qcom,l2_cache_dump600 { + qcom,dump-node = <&L2_6>; + qcom,dump-id = <0xc6>; + }; + + qcom,l2_cache_dump700 { + qcom,dump-node = <&L2_7>; + qcom,dump-id = <0xc7>; + }; + + qcom,l2_tlb_dump0 { + qcom,dump-node = <&L2_TLB_0>; + qcom,dump-id = <0x120>; + }; + + qcom,l2_tlb_dump100 { + qcom,dump-node = <&L2_TLB_100>; + qcom,dump-id = <0x121>; + }; + + qcom,l2_tlb_dump200 { + qcom,dump-node = <&L2_TLB_200>; + qcom,dump-id = <0x122>; + }; + + qcom,l2_tlb_dump300 { + qcom,dump-node = <&L2_TLB_300>; + qcom,dump-id = <0x123>; + }; + + qcom,l2_tlb_dump400 { + qcom,dump-node = <&L2_TLB_400>; + qcom,dump-id = <0x124>; + }; + + qcom,l2_tlb_dump500 { + qcom,dump-node = <&L2_TLB_500>; + qcom,dump-id = <0x125>; + }; + + qcom,l2_tlb_dump600 { + qcom,dump-node = <&L2_TLB_600>; + qcom,dump-id = <0x126>; + }; + + qcom,l2_tlb_dump700 { + qcom,dump-node = <&L2_TLB_700>; + qcom,dump-id = <0x127>; + }; + }; + + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <2>; + label = "modem"; + }; + + mem_client_3_size: qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x500000>; + qcom,client-id = <1>; + qcom,allocate-boot-time; + label = "modem"; + }; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem@8600000 { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 3>; + }; + + apcs: syscon@17c0000c { + compatible = "syscon"; + reg = <0x17c0000c 0x4>; + }; + + ufs_ice: ufsice@1d90000 { + compatible = "qcom,ice"; + reg = <0x1d90000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk", "bus_clk", + "iface_clk", "ice_core_clk"; + clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>, + <&clock_gcc GCC_UFS_PHY_AHB_CLK>, + <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>; + qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; + vdd-hba-supply = <&ufs_phy_gdsc>; + qcom,msm-bus,name = "ufs_ice_noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 650 0 0>, /* No vote */ + <1 650 1000 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "ufs"; + }; + + ufsphy_mem: ufsphy_mem@1d87000 { + reg = <0x1d87000 0xda8>; /* PHY regs */ + reg-names = "phy_mem"; + #phy-cells = <0>; + ufs-qcom-crypto = <&ufs_ice>; + + lanes-per-direction = <2>; + + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>, + <&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x2500>; + interrupts = <0 265 0>; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + ufs-qcom-crypto = <&ufs_ice>; + + lanes-per-direction = <2>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&clock_gcc GCC_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_UFS_PHY_AHB_CLK>, + <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <37500000 300000000>, + <0 0>, + <0 0>, + <37500000 300000000>, + <37500000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + qcom,msm-bus,name = "ufshc_mem"; + qcom,msm-bus,num-cases = <26>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <123 512 0 0>, <1 757 0 0>, /* No vote */ + <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */ + <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */ + <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */ + <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */ + <123 512 1844 0>, <1 757 1000 0>, /* PWM G1 L2 */ + <123 512 3688 0>, <1 757 1000 0>, /* PWM G2 L2 */ + <123 512 7376 0>, <1 757 1000 0>, /* PWM G3 L2 */ + <123 512 14752 0>, <1 757 1000 0>, /* PWM G4 L2 */ + <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */ + <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */ + <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */ + <123 512 4194304 0>, <1 757 204800 0>, /* HS G4 RA */ + <123 512 255591 0>, <1 757 1000 0>, /* HS G1 RA L2 */ + <123 512 511181 0>, <1 757 1000 0>, /* HS G2 RA L2 */ + <123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */ + <123 512 8388608 0>, <1 757 409600 0>, /* HS G4 RA L2 */ + <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */ + <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */ + <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */ + <123 512 4194304 0>, <1 757 204800 0>, /* HS G4 RB */ + <123 512 298189 0>, <1 757 1000 0>, /* HS G1 RB L2 */ + <123 512 596378 0>, <1 757 1000 0>, /* HS G2 RB L2 */ + /* As UFS working in HS G3 RB L2 mode, aggregated + * bandwidth (AB) should take care of providing + * optimum throughput requested. However, as tested, + * in order to scale up CNOC clock, instantaneous + * bindwidth (IB) needs to be given a proper value too. + */ + <123 512 4194304 0>, <1 757 204800 409600>, /* HS G3 RB L2 */ + <123 512 8388608 0>, <1 757 409600 409600>, /* HS G4 RB L2 */ + <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", + "MAX"; + + /* PM QoS */ + qcom,pm-qos-cpu-groups = <0x0f 0xf0>; + qcom,pm-qos-cpu-group-latency-us = <44 44>; + qcom,pm-qos-default-cpu = <0>; + + pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; + pinctrl-0 = <&ufs_dev_reset_assert>; + pinctrl-1 = <&ufs_dev_reset_deassert>; + + resets = <&clock_gcc GCC_UFS_PHY_BCR>; + reset-names = "core_reset"; + + status = "disabled"; + }; + + qcom,msm-cdsp-loader { + compatible = "qcom,cdsp-loader"; + qcom,proc-img-to-load = "cdsp"; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + }; + + msm_fastrpc: qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,fastrpc-adsp-audio-pdr; + qcom,rpc-latency-us = <235>; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x1401 0x2040>, + <&apps_smmu 0x1421 0x0>, + <&apps_smmu 0x2001 0x420>, + <&apps_smmu 0x2041 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x4 0x3440>, + <&apps_smmu 0x24 0x3400>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x5 0x3440>, + <&apps_smmu 0x25 0x3400>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x6 0x3460>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb7 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x7 0x3460>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb8 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x8 0x3460>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x2 0x3440>, + <&apps_smmu 0x22 0x3400>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x3 0x3440>, + <&apps_smmu 0x1423 0x0>, + <&apps_smmu 0x2023 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb9 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x9 0x3460>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb10 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1b23 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb11 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1b24 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb12 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x1b25 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb13 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "sdsprpc-smd"; + iommus = <&apps_smmu 0x5a1 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb14 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "sdsprpc-smd"; + iommus = <&apps_smmu 0x5a2 0x0>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb15 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "sdsprpc-smd"; + iommus = <&apps_smmu 0x5a3 0x0>; + shared-cb = <4>; + dma-coherent; + }; + }; + + sdhc_2: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x8804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = <0 204 0>, <0 222 0>; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <4>; + qcom,large-address-bus; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <81 512 0 0>, <1 608 0 0>, + /* 400 KB/s*/ + <81 512 1046 1600>, + <1 608 1600 1600>, + /* 20 MB/s */ + <81 512 52286 80000>, + <1 608 80000 80000>, + /* 25 MB/s */ + <81 512 65360 100000>, + <1 608 100000 100000>, + /* 50 MB/s */ + <81 512 130718 200000>, + <1 608 133320 133320>, + /* 100 MB/s */ + <81 512 261438 200000>, + <1 608 150000 150000>, + /* 200 MB/s */ + <81 512 261438 400000>, + <1 608 300000 300000>, + /* Max. bandwidth */ + <81 512 1338562 4096000>, + <1 608 1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100750000 200000000 4294967295>; + + qcom,restore-after-cx-collapse; + + qcom,clk-rates = <400000 20000000 25000000 + 50000000 100000000 201500000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", + "SDR104"; + + qcom,devfreq,freq-table = <50000000 201500000>; + clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>, + <&clock_gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface_clk", "core_clk"; + + /* PM QoS */ + qcom,pm-qos-irq-type = "affine_irq"; + qcom,pm-qos-irq-latency = <44 44>; + qcom,pm-qos-cpu-groups = <0x3f 0xc0>; + qcom,pm-qos-legacy-latency-us = <44 44>, <44 44>; + + status = "disabled"; + }; + + apps_rsc: mailbox@18220000 { + compatible = "qcom,tcs-drv"; + label = "apps_rsc"; + reg = <0x18220000 0x100>, <0x18220d00 0x3000>; + interrupts = <0 5 0>; + #mbox-cells = <1>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + }; + + disp_rsc: mailbox@af20000 { + compatible = "qcom,tcs-drv"; + label = "display_rsc"; + reg = <0xaf20000 0x100>, <0xaf21c00 0x3000>; + interrupts = <0 129 0>; + #mbox-cells = <1>; + qcom,drv-id = <0>; + qcom,tcs-config = , + , + , + ; + }; + + apcs_glb: mailbox@17c00000 { + compatible = "qcom,sm8150-apcs-hmss-global"; + reg = <0x17c00000 0x1000>; + + #mbox-cells = <1>; + }; + + sp_scsr: mailbox@188501c { + compatible = "qcom,sm8150-spcs-global"; + reg = <0x188501c 0x4>; + + #mbox-cells = <1>; + }; + + sp_scsr_block: syscon@1880000 { + compatible = "syscon"; + reg = <0x1880000 0x10000>; + }; + + intsp: qcom,qsee_irq { + compatible = "qcom,sm8150-qsee-irq"; + + syscon = <&sp_scsr_block>; + interrupts = <0 348 IRQ_TYPE_LEVEL_HIGH>, + <0 349 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-names = "sp_ipc0", + "sp_ipc1"; + + interrupt-controller; + #interrupt-cells = <3>; + }; + + qcom,qsee_irq_bridge { + compatible = "qcom,qsee-ipc-irq-bridge"; + + qcom,qsee-ipc-irq-spss { + qcom,dev-name = "qsee_ipc_irq_spss"; + label = "spss"; + interrupt-parent = <&intsp>; + interrupts = <1 0 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_modem: modem { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&apcs_glb 12>; + mbox-names = "mpss_smem"; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 0x2>; + }; + + qcom,modem_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>, + <&glink_slpi>, + <&glink_cdsp>, + <&glink_spss>; + }; + }; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&apcs_glb 8>; + mbox-names = "adsp_smem"; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + cpu-affinity = <1 2>; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,apr_tal_rpmsg { + qcom,glink-channels = "apr_audio_svc"; + qcom,intents = <0x200 20>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,adsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_slpi>, + <&glink_cdsp>; + }; + }; + + glink_slpi: dsps { + qcom,remote-pid = <3>; + transport = "smem"; + mboxes = <&apcs_glb 24>; + mbox-names = "dsps_smem"; + interrupts = ; + + label = "slpi"; + qcom,glink-label = "dsps"; + + qcom,slpi_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,slpi_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>, + <&glink_cdsp>; + }; + }; + + glink_cdsp: cdsp { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&apcs_glb 4>; + mbox-names = "cdsp_smem"; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12>; + + qcom,cdsp-cdsp-l3-gov { + compatible = "qcom,cdsp-l3"; + qcom,target-dev = <&cdsp_cdsp_l3_lat>; + }; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-latency-us = <44>; + qcom,qos-maxhold-ms = <20>; + qcom,compute-cx-limit-en; + qcom,compute-priority-mode = <2>; + #cooling-cells = <2>; + }; + + msm_hvx_rm: qcom,msm_hvx_rm { + compatible = "qcom,msm-hvx-rm"; + #cooling-cells = <2>; + }; + }; + + qcom,cdsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>, + <&glink_slpi>; + }; + }; + + glink_spss: spss { + qcom,remote-pid = <8>; + transport = "spss"; + mboxes = <&sp_scsr 0>; + mbox-names = "spss_spss"; + interrupt-parent = <&intsp>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; + + reg = <0x1885008 0x8>, + <0x1885010 0x4>; + reg-names = "qcom,spss-addr", + "qcom,spss-size"; + + label = "spss"; + qcom,glink-label = "spss"; + + qcom,spss_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>; + }; + }; + + glink_spi_xprt_wdsp: wdsp { + transport = "spi"; + tx-descriptors = <0x12000 0x12004>; + rx-descriptors = <0x1200c 0x12010>; + + label = "wdsp"; + qcom,glink-label = "wdsp"; + + qcom,wdsp_ctrl { + qcom,glink-channels = "g_glink_ctrl"; + qcom,intents = <0x400 1>; + }; + + qcom,wdsp_ild { + qcom,glink-channels = + "g_glink_persistent_data_ild"; + }; + + qcom,wdsp_nild { + qcom,glink-channels = + "g_glink_persistent_data_nild"; + }; + + qcom,wdsp_data { + qcom,glink-channels = "g_glink_audio_data"; + qcom,intents = <0x1000 2>; + }; + + qcom,diag_data { + qcom,glink-channels = "DIAG_DATA"; + qcom,intents = <0x4000 2>; + }; + + qcom,diag_ctrl { + qcom,glink-channels = "DIAG_CTRL"; + qcom,intents = <0x4000 1>; + }; + + qcom,diag_cmd { + qcom,glink-channels = "DIAG_CMD"; + qcom,intents = <0x4000 1 >; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qmp_aop: qcom,qmp-aop@c300000 { + compatible = "qcom,qmp-mbox"; + reg = <0xc300000 0x1000>, <0x17c0000C 0x4>; + reg-names = "msgram", "irq-reg-base"; + qcom,irq-mask = <0x1>; + interrupts = ; + + label = "aop"; + qcom,early-boot; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; + + qmp_npu0: qcom,qmp-npu-low@9818000 { + compatible = "qcom,qmp-mbox"; + reg = <0x9818000 0x8000>, <0x9901008 0x4>; + reg-names = "msgram", "irq-reg-base"; + qcom,irq-mask = <0x12>; + interrupts = ; + + label = "npu_qmp_low"; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; + + qmp_npu1: qcom,qmp-npu-high@9818000 { + compatible = "qcom,qmp-mbox"; + reg = <0x9818000 0x8000>, <0x9901008 0x4>; + reg-names = "msgram", "irq-reg-base"; + qcom,irq-mask = <0x14>; + interrupts = ; + + label = "npu_qmp_high"; + priority = <1>; + mbox-desc-offset = <0x2000>; + #mbox-cells = <1>; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + interrupt-parent = <&sleepstate_smp2p_in>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; + }; + + system_pm { + compatible = "qcom,system-pm"; + mboxes = <&apps_rsc 0>; + }; + + cmd_db: qcom,cmd-db@c3f000c { + compatible = "qcom,cmd-db"; + reg = <0xc3f000c 8>; + }; + + qcom_seecom: qseecom@87900000 { + compatible = "qcom,qseecom"; + /* enlarge TA memory size from 34M to 62M on 2018/11/22 */ + reg = <0x87900000 0x3E00000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,no-clock-support; + qcom,fde-key-size; + qcom,appsbl-qseecom-support; + qcom,commonlib64-loaded-by-uefi; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_smcinvoke: smcinvoke@87900000 { + compatible = "qcom,smcinvoke"; + /* enlarge TA memory size from 34M to 62M on 2018/11/22 */ + reg = <0x87900000 0x3E00000>; + reg-names = "secapp-region"; + }; + + qcom_rng: qrng@793000 { + compatible = "qcom,msm-rng"; + reg = <0x793000 0x1000>; + qcom,msm-rng-iface-clk; + qcom,no-qrng-config; + qcom,msm-bus,name = "msm-rng-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 618 0 0>, /* No vote */ + <1 618 0 300000>; /* 75 MHz */ + clocks = <&clock_gcc GCC_PRNG_AHB_CLK>; + clock-names = "iface_clk"; + }; + + qcom_cedev: qcedev@1de0000 { + compatible = "qcom,qcedev"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 272 0>; + qcom,bam-pipe-pair = <3>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,bam-ee = <0>; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <125 512 0 0>, + <125 512 393600 393600>; + qcom,smmu-s1-enable; + qcom,no-clock-support; + iommus = <&apps_smmu 0x0506 0x0011>, + <&apps_smmu 0x0516 0x0011>; + + qcom_cedev_ns_cb { + compatible = "qcom,qcedev,context-bank"; + label = "ns_context"; + iommus = <&apps_smmu 0x512 0>; + virtual-addr = <0x60000000>; + virtual-size = <0x40000000>; + }; + + qcom_cedev_s_cb { + compatible = "qcom,qcedev,context-bank"; + label = "secure_context"; + iommus = <&apps_smmu 0x513 0>; + virtual-addr = <0xa0000000>; + virtual-size = <0x40000000>; + qcom,secure-context-bank; + }; + }; + + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; + + qcom_crypto: qcrypto@1de0000 { + compatible = "qcom,qcrypto"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 272 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + qcom,clk-mgmt-sus-res; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <125 512 0 0>, + <125 512 393600 393600>; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-aead-algo; + qcom,use-sw-hmac-algo; + qcom,smmu-s1-enable; + qcom,no-clock-support; + iommus = <&apps_smmu 0x0504 0x0011>, + <&apps_smmu 0x0514 0x0011>; + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + rpmh { + qcom,dump-size = <0x2000000>; + qcom,dump-id = <0xec>; + }; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x80000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + tmc_etf { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xf0>; + }; + + etf_swao { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xf1>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etf_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x101>; + }; + + etfswao_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x102>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + }; + + qcom_tzlog: tz-log@146bf720 { + compatible = "qcom,tz-log"; + reg = <0x146bf720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + + dcc: dcc_v2@10a2000 { + compatible = "qcom,dcc-v2"; + reg = <0x10a2000 0x1000>, + <0x10ad000 0x3000>; + reg-names = "dcc-base", "dcc-ram-base"; + + dcc-ram-offset = <0x5000>; + + qcom,curr-link-list = <3>; + qcom,link-list = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + tsens0: tsens@c222000 { + compatible = "qcom,tsens24xx"; + reg = <0xc222000 0x4>, + <0xc263000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts = <0 506 0>, <0 508 0>; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: tsens@c223000 { + compatible = "qcom,tsens24xx"; + reg = <0xc223000 0x4>, + <0xc265000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts = <0 507 0>, <0 509 0>; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + #thermal-sensor-cells = <1>; + }; + + thermal_zones: thermal-zones { + }; + + slim_aud: slim@171c0000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0x171c0000 0x2c000>, + <0x17184000 0x2c000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 163 0>, <0 164 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x780000>; + qcom,ea-pc = <0x2a0>; + qcom,iommu-s1-bypass; + + iommu_slim_aud_ctrl_cb: qcom,iommu_slim_ctrl_cb { + compatible = "qcom,iommu-slim-ctrl-cb"; + iommus = <&apps_smmu 0x1b46 0x8>, + <&apps_smmu 0x1b4d 0x2>, + <&apps_smmu 0x1b50 0x1>; + }; + }; + + slim_qca: slim@17240000 { + status = "ok"; + cell-index = <3>; + compatible = "qcom,slim-ngd"; + reg = <0x17240000 0x2c000>, + <0x17204000 0x20000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 291 0>, <0 292 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,iommu-s1-bypass; + + iommu_slim_qca_ctrl_cb: qcom,iommu_slim_ctrl_cb { + compatible = "qcom,iommu-slim-ctrl-cb"; + iommus = <&apps_smmu 0x1b53 0x0>; + }; + + /* Slimbus Slave DT for WCN3990 */ + btfmslim_codec: wcn3990 { + compatible = "qcom,btfmslim_slave"; + elemental-addr = [00 01 20 02 17 02]; + qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; + qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; + }; + }; + + gpi_dma0: qcom,gpi-dma@0x800000 { + #dma-cells = <5>; + compatible = "qcom,gpi-dma"; + reg = <0x800000 0x60000>; + reg-names = "gpi-top"; + interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>, + <0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>, + <0 252 0>, <0 253 0>, <0 254 0>, <0 255 0>, + <0 256 0>; + qcom,max-num-gpii = <13>; + qcom,gpii-mask = <0xfa>; + qcom,ev-factor = <2>; + iommus = <&apps_smmu 0x00d6 0x0>; + qcom,smmu-cfg = <0x1>; + qcom,iova-range = <0x0 0x100000 0x0 0x100000>; + status = "ok"; + }; + + gpi_dma1: qcom,gpi-dma@0xa00000 { + #dma-cells = <5>; + compatible = "qcom,gpi-dma"; + reg = <0xa00000 0x60000>; + reg-names = "gpi-top"; + interrupts = <0 279 0>, <0 280 0>, <0 281 0>, <0 282 0>, + <0 283 0>, <0 284 0>, <0 293 0>, <0 294 0>, + <0 295 0>, <0 296 0>, <0 297 0>, <0 298 0>, + <0 299 0>; + qcom,max-num-gpii = <13>; + qcom,gpii-mask = <0xfa>; + qcom,ev-factor = <2>; + iommus = <&apps_smmu 0x0616 0x0>; + qcom,smmu-cfg = <0x1>; + qcom,iova-range = <0x0 0x100000 0x0 0x100000>; + status = "ok"; + }; + + gpi_dma2: qcom,gpi-dma@0xc00000 { + #dma-cells = <5>; + compatible = "qcom,gpi-dma"; + reg = <0xc00000 0x60000>; + reg-names = "gpi-top"; + interrupts = <0 588 0>, <0 589 0>, <0 590 0>, <0 591 0>, + <0 592 0>, <0 593 0>, <0 594 0>, <0 595 0>, + <0 596 0>, <0 597 0>, <0 598 0>, <0 599 0>, + <0 600 0>; + qcom,max-num-gpii = <13>; + qcom,gpii-mask = <0xfa>; + qcom,ev-factor = <2>; + iommus = <&apps_smmu 0x07b6 0x0>; + qcom,smmu-cfg = <0x1>; + qcom,iova-range = <0x0 0x100000 0x0 0x100000>; + status = "ok"; + }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x200000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + qcom,guard-memory; + }; + + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + qcom,ipa-platform-type-msm; + qcom,ipa-advertise-sg-support; + qcom,ipa-napi-enable; + }; + + ipa_hw: qcom,ipa@1e00000 { + compatible = "qcom,ipa"; + mboxes = <&qmp_aop 0>; + reg = <0x1e00000 0x34000>, + <0x1e04000 0x28000>; + reg-names = "ipa-base", "gsi-base"; + interrupts = + <0 311 0>, + <0 432 0>; + interrupt-names = "ipa-irq", "gsi-irq"; + qcom,ipa-hw-ver = <15>; /* IPA core version = IPAv4.1 */ + qcom,ipa-hw-mode = <0>; + qcom,ee = <0>; + qcom,use-ipa-tethering-bridge; + qcom,modem-cfg-emb-pipe-flt; + qcom,ipa-wdi2; + qcom,use-64-bit-dma-mask; + qcom,arm-smmu; + qcom,smmu-fast-map; + qcom,use-ipa-pm; + qcom,bandwidth-vote-for-ipa; + qcom,msm-bus,name = "ipa"; + qcom,msm-bus,num-cases = <5>; + qcom,msm-bus,num-paths = <4>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + , + , + , + , + + /* SVS2 */ + , + , + , + , + + /* SVS */ + , + , + , + , + + /* NOMINAL */ + , + , + , + , + + /* TURBO */ + , + , + , + ; + + qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", + "TURBO"; + qcom,throughput-threshold = <310 600 1000>; + qcom,scaling-exceptions = <>; + + /* smp2p information */ + qcom,smp2p_map_ipa_1_out { + compatible = "qcom,smp2p-map-ipa-1-out"; + qcom,smem-states = <&smp2p_ipa_1_out 0>; + qcom,smem-state-names = "ipa-smp2p-out"; + }; + + qcom,smp2p_map_ipa_1_in { + compatible = "qcom,smp2p-map-ipa-1-in"; + interrupts-extended = <&smp2p_ipa_1_in 0 0>; + interrupt-names = "ipa-smp2p-in"; + }; + }; + + ipa_smmu_ap: ipa_smmu_ap { + compatible = "qcom,ipa-smmu-ap-cb"; + iommus = <&apps_smmu 0x520 0x0>; + qcom,iova-mapping = <0x20000000 0x40000000>; + qcom,additional-mapping = + /* modem tables in IMEM */ + <0x146BD000 0x146BD000 0x2000>; + dma-coherent; + }; + + ipa_smmu_wlan: ipa_smmu_wlan { + compatible = "qcom,ipa-smmu-wlan-cb"; + iommus = <&apps_smmu 0x521 0x0>; + qcom,additional-mapping = + /* ipa-uc ram */ + <0x1E60000 0x1E60000 0x80000>; + }; + + ipa_smmu_uc: ipa_smmu_uc { + compatible = "qcom,ipa-smmu-uc-cb"; + iommus = <&apps_smmu 0x522 0x0>; + qcom,iova-mapping = <0x40400000 0x1FC00000>; + }; + + qcom,ipa_fws { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0xf>; + qcom,firmware-name = "ipa_fws"; + qcom,pil-force-shutdown; + memory-region = <&pil_ipa_fw_mem>; + }; + + aop-msg-client { + compatible = "qcom,debugfs-qmp-client"; + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + }; + + qcom,cnss-qca6390@a0000000 { + compatible = "qcom,cnss-qca6390"; + reg = <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "smmu_iova_base", "smmu_iova_ipa"; + wlan-en-gpio = <&tlmm 169 0>; + pinctrl-names = "wlan_en_active", "wlan_en_sleep"; + pinctrl-0 = <&cnss_wlan_en_active>; + pinctrl-1 = <&cnss_wlan_en_sleep>; + qcom,wlan-rc-num = <0>; + qcom,wlan-ramdump-dynamic = <0x400000>; + qcom,smmu-s1-enable; + + mhi,max-channels = <30>; + mhi,timeout = <10000>; + + #address-cells = <1>; + #size-cells = <0>; + + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <32>; + mhi,event-ring = <1>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x14>; + mhi,auto-queue; + mhi,auto-start; + }; + + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + }; + + icnss: qcom,icnss@18800000 { + compatible = "qcom,icnss"; + reg = <0x18800000 0x800000>, + <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa"; + iommus = <&apps_smmu 0x0640 0x1>; + interrupts = <0 414 0 /* CE0 */ >, + <0 415 0 /* CE1 */ >, + <0 416 0 /* CE2 */ >, + <0 417 0 /* CE3 */ >, + <0 418 0 /* CE4 */ >, + <0 419 0 /* CE5 */ >, + <0 420 0 /* CE6 */ >, + <0 421 0 /* CE7 */ >, + <0 422 0 /* CE8 */ >, + <0 423 0 /* CE9 */ >, + <0 424 0 /* CE10 */ >, + <0 425 0 /* CE11 */ >; + qcom,wlan-msa-memory = <0x100000>; + qcom,wlan-msa-fixed-region = <&pil_wlan_fw_mem>; + + vdd-cx-mx-supply = <&pm8150_l1>; + vdd-1.8-xo-supply = <&pm8150_l7>; + vdd-1.3-rfa-supply = <&pm8150l_l2>; + vdd-3.3-ch0-supply = <&pm8150l_l11>; + qcom,vdd-cx-mx-config = <752000 752000>; + qcom,vdd-3.3-ch0-config = <3104000 3312000>; + qcom,smp2p_map_wlan_1_in { + interrupts-extended = <&smp2p_wlan_1_in 0 0>, + <&smp2p_wlan_1_in 1 0>; + interrupt-names = "qcom,smp2p-force-fatal-error", + "qcom,smp2p-early-crash-ind"; + }; + }; + + wil6210: qcom,wil6210 { + compatible = "qcom,wil6210"; + qcom,pcie-parent = <&pcie1>; + pinctrl-names = "default"; + pinctrl-0 = <&wil6210_refclk3_en_pin>; + qcom,wigig-en = <&tlmm 131 0>; + qcom,msm-bus,name = "wil6210"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <100 512 0 0>, + <100 512 600000 800000>; /* ~4.6Gbps (MCS12) */ + qcom,use-ext-supply; + vddio-supply= <&pm8150_s5>; + qcom,use-ext-clocks; + clocks = <&clock_rpmh RPMH_RF_CLK3>; + clock-names = "rf_clk3_clk"; + qcom,smmu-support; + qcom,smmu-mapping = <0x20000000 0xe0000000>; + qcom,smmu-s1-en; + qcom,smmu-fast-map; + qcom,smmu-coherent; + qcom,keep-radio-on-during-sleep; + status = "disabled"; + }; + + tspp: msm_tspp@0x8880000 { + compatible = "qcom,msm_tspp"; + reg = <0x088a7000 0x200>, /* MSM_TSIF0_PHYS */ + <0x088a8000 0x200>, /* MSM_TSIF1_PHYS */ + <0x088a9000 0x1000>, /* MSM_TSPP_PHYS */ + <0x08884000 0x23000>; /* MSM_TSPP_BAM_PHYS */ + reg-names = "MSM_TSIF0_PHYS", + "MSM_TSIF1_PHYS", + "MSM_TSPP_PHYS", + "MSM_TSPP_BAM_PHYS"; + interrupts = <0 121 0>, /* TSIF_TSPP_IRQ */ + <0 119 0>, /* TSIF0_IRQ */ + <0 120 0>, /* TSIF1_IRQ */ + <0 122 0>; /* TSIF_BAM_IRQ */ + interrupt-names = "TSIF_TSPP_IRQ", + "TSIF0_IRQ", + "TSIF1_IRQ", + "TSIF_BAM_IRQ"; + + clock-names = "iface_clk", "ref_clk"; + clocks = <&clock_gcc GCC_TSIF_AHB_CLK>, + <&clock_gcc GCC_TSIF_REF_CLK>; + + qcom,msm-bus,name = "tsif"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <82 512 0 0>, /* No vote */ + <82 512 12288 24576>; + /* Max. bandwidth, 2xTSIF, each max of 96Mbps */ + + pinctrl-names = "disabled", + "tsif0-mode1", "tsif0-mode2", + "tsif1-mode1", "tsif1-mode2", + "dual-tsif-mode1", "dual-tsif-mode2"; + + pinctrl-0 = <>; /* disabled */ + pinctrl-1 = <&tsif0_signals_active>; /* tsif0-mode1 */ + pinctrl-2 = <&tsif0_signals_active + &tsif0_sync_active>; /* tsif0-mode2 */ + pinctrl-3 = <&tsif1_signals_active>; /* tsif1-mode1 */ + pinctrl-4 = <&tsif1_signals_active + &tsif1_sync_active>; /* tsif1-mode2 */ + pinctrl-5 = <&tsif0_signals_active + &tsif1_signals_active>; /* dual-tsif-mode1 */ + pinctrl-6 = <&tsif0_signals_active + &tsif0_sync_active + &tsif1_signals_active + &tsif1_sync_active>; /* dual-tsif-mode2 */ + + memory-region = <&qseecom_mem>; + qcom,smmu-s1-bypass; + iommus = <&apps_smmu 0x620 0x00>; + }; + + demux { + compatible = "qcom,demux"; + }; +}; + +&emac_gdsc { + status = "ok"; +}; + +&pcie_0_gdsc { + status = "ok"; +}; + +&pcie_1_gdsc { + status = "ok"; +}; + +&ufs_phy_gdsc { + status = "ok"; +}; + +&usb30_prim_gdsc { + status = "ok"; +}; + +&usb30_sec_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu1_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu2_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu0_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu1_gdsc { + status = "ok"; +}; + +&bps_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; + qcom,msm-bus,name = "bps_gdsc_ahb"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + qcom,support-hw-trigger; + status = "ok"; +}; + +&ipe_0_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; + qcom,msm-bus,name = "ipe_0_gdsc_ahb"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + qcom,support-hw-trigger; + status = "ok"; +}; + +&ipe_1_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; + qcom,msm-bus,name = "ipe_1_gdsc_ahb"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + qcom,support-hw-trigger; + status = "ok"; +}; + +&ife_0_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; + qcom,msm-bus,name = "ife_0_gdsc_ahb"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + status = "ok"; +}; + +&ife_1_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; + qcom,msm-bus,name = "ife_1_gdsc_ahb"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + status = "ok"; +}; + +&titan_top_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; + qcom,msm-bus,name = "titan_top_gdsc_ahb"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + status = "ok"; +}; + +&mdss_core_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_DISP_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; + qcom,msm-bus,name = "mdss_core_gdsc_ahb"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + status = "ok"; +}; + +&gpu_cx_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_gx_gdsc { + parent-supply = <&pm8150l_s2_level>; + vdd_parent-supply = <&pm8150l_s2_level>; + status = "ok"; +}; + +&mvsc_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; + qcom,msm-bus,name = "mvsc_gdsc_ahb"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + status = "ok"; +}; + +&mvs0_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; + qcom,msm-bus,name = "mvs0_gdsc_ahb"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + qcom,support-hw-trigger; + status = "ok"; +}; + +&mvs1_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + vdd_parent-supply = <&VDD_MMCX_LEVEL>; + qcom,msm-bus,name = "mvs1_gdsc_ahb"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + qcom,support-hw-trigger; + status = "ok"; +}; + +&npu_core_gdsc { + clock-names = "ahb_clk"; + clocks = <&clock_gcc GCC_NPU_CFG_AHB_CLK>; + status = "ok"; +}; +#include "sm8150-pinctrl.dtsi" +#include "sm8150-slpi-pinctrl.dtsi" +#include "sm8150-regulator.dtsi" +#include "sm8150-ion.dtsi" +#include "sm8150-bus.dtsi" +#include "sm8150-pcie.dtsi" +#include "sm8150-smp2p.dtsi" +#include "sm8150-coresight.dtsi" +#include "msm-arm-smmu-sm8150.dtsi" +#include "sm8150-qupv3.dtsi" +#include "sm8150-npu.dtsi" +#include "sm8150-pm.dtsi" +#include "sm8150-audio.dtsi" +#include "sm8150-vidc.dtsi" +#include "sm8150-thermal.dtsi" +#include "sm8150-usb.dtsi" +#include "sm8150-gpu.dtsi" +#include "sm8150-mhi.dtsi" diff --git a/arch/arm/boot/dts/qcom/sm8150p-cdp.dts b/arch/arm/boot/dts/qcom/sm8150p-cdp.dts new file mode 100644 index 000000000000..0020b813b64d --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150p-cdp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150p.dtsi" +#include "sm8150-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150P CDP"; + compatible = "qcom,sm8150p-cdp", "qcom,sm8150p", "qcom,cdp"; + qcom,board-id = <1 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150p-hdk.dts b/arch/arm/boot/dts/qcom/sm8150p-hdk.dts new file mode 100644 index 000000000000..c715bc8849f0 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150p-hdk.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150p.dtsi" +#include "sm8150-hdk.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150P HDK"; + compatible = "qcom,sm8150p-hdk", "qcom,sm8150p", "qcom,hdk"; + qcom,board-id = <0x01001f 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150p-mtp.dts b/arch/arm/boot/dts/qcom/sm8150p-mtp.dts new file mode 100644 index 000000000000..9a7fd33ae9b2 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150p-mtp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150p.dtsi" +#include "sm8150-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150P MTP"; + compatible = "qcom,sm8150p-mtp", "qcom,sm8150p", "qcom,mtp"; + qcom,board-id = <8 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150p-qrd.dts b/arch/arm/boot/dts/qcom/sm8150p-qrd.dts new file mode 100644 index 000000000000..50039ff12ad8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150p-qrd.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150p.dtsi" +#include "sm8150-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150P QRD"; + compatible = "qcom,sm8150p-qrd", "qcom,sm8150p", "qcom,qrd"; + qcom,board-id = <11 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150p-v2-cdp.dts b/arch/arm/boot/dts/qcom/sm8150p-v2-cdp.dts new file mode 100644 index 000000000000..70ff898cfff4 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150p-v2-cdp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150p-v2.dtsi" +#include "sm8150-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150P V2 CDP"; + compatible = "qcom,sm8150p-cdp", "qcom,sm8150p", "qcom,cdp"; + qcom,board-id = <1 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150p-v2-mtp.dts b/arch/arm/boot/dts/qcom/sm8150p-v2-mtp.dts new file mode 100644 index 000000000000..a799969fc5a9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150p-v2-mtp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150p-v2.dtsi" +#include "sm8150-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150P V2 MTP"; + compatible = "qcom,sm8150p-mtp", "qcom,sm8150p", "qcom,mtp"; + qcom,board-id = <8 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150p-v2-qrd.dts b/arch/arm/boot/dts/qcom/sm8150p-v2-qrd.dts new file mode 100644 index 000000000000..9e2b45317c81 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150p-v2-qrd.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150p-v2.dtsi" +#include "sm8150-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150P V2 QRD"; + compatible = "qcom,sm8150p-qrd", "qcom,sm8150p", "qcom,qrd"; + qcom,board-id = <11 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150p-v2.dts b/arch/arm/boot/dts/qcom/sm8150p-v2.dts new file mode 100644 index 000000000000..50386105e70d --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150p-v2.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150p-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150P v2 SoC"; + compatible = "qcom,sm8150p"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150p-v2.dtsi b/arch/arm/boot/dts/qcom/sm8150p-v2.dtsi new file mode 100644 index 000000000000..d4d2cf37d745 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150p-v2.dtsi @@ -0,0 +1,19 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm8150-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150P v2"; + qcom,msm-name = "SM8150P v2"; + qcom,msm-id = <361 0x20000>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150p.dts b/arch/arm/boot/dts/qcom/sm8150p.dts new file mode 100644 index 000000000000..d6809d8ffc9f --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150p.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "sm8150p.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150P v1 SoC"; + compatible = "qcom,sm8150p"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm/boot/dts/qcom/sm8150p.dtsi b/arch/arm/boot/dts/qcom/sm8150p.dtsi new file mode 100644 index 000000000000..2ed1d50cd296 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sm8150p.dtsi @@ -0,0 +1,19 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sm8150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150P v1"; + qcom,msm-name = "SM8150P v1"; + qcom,msm-id = <361 0x10000>; +}; diff --git a/arch/arm/boot/dts/qcom/smb1355.dtsi b/arch/arm/boot/dts/qcom/smb1355.dtsi new file mode 100644 index 000000000000..f04eb77c6fb0 --- /dev/null +++ b/arch/arm/boot/dts/qcom/smb1355.dtsi @@ -0,0 +1,56 @@ +/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +smb1355: qcom,smb1355@c { + compatible = "qcom,i2c-pmic"; + reg = <0xc>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&spmi_bus>; + interrupts = <0x2 0xC5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt_names = "smb1355"; + interrupt-controller; + #interrupt-cells = <3>; + qcom,periph-map = <0x10 0x12 0x13 0x16>; + status = "disabled"; + + smb1355_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + smb1355_charger: qcom,smb1355-charger@1000 { + compatible = "qcom,smb1355"; + qcom,pmic-revid = <&smb1355_revid>; + reg = <0x1000 0x700>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&smb1355>; + status = "disabled"; + + qcom,chgr@1000 { + reg = <0x1000 0x100>; + interrupts = <0x10 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "chg-state-change"; + }; + + qcom,chgr-misc@1600 { + reg = <0x1600 0x100>; + interrupts = <0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x16 0x6 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog-bark", + "temperature-change"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/smb1390.dtsi b/arch/arm/boot/dts/qcom/smb1390.dtsi new file mode 100644 index 000000000000..b67c55911c91 --- /dev/null +++ b/arch/arm/boot/dts/qcom/smb1390.dtsi @@ -0,0 +1,72 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +smb1390: qcom,smb1390@10 { + compatible = "qcom,i2c-pmic"; + reg = <0x10>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&spmi_bus>; + interrupts = <0x2 0xC5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt_names = "smb1390"; + interrupt-controller; + #interrupt-cells = <3>; + qcom,periph-map = <0x10>; + status = "disabled"; + + smb1390_revid: qcom,revid { + compatible = "qcom,qpnp-revid"; + reg = <0x100>; + }; + + smb1390_charger: qcom,charge_pump { + compatible = "qcom,smb1390-charger"; + qcom,pmic-revid = <&smb1390_revid>; + interrupt-parent = <&smb1390>; + status = "disabled"; + + qcom,core { + interrupts = <0x10 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x10 0x5 IRQ_TYPE_EDGE_RISING>, + <0x10 0x6 IRQ_TYPE_EDGE_RISING>, + <0x10 0x7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "switcher-off-window", + "switcher-off-fault", + "tsd-fault", + "irev-fault", + "vph-ov-hard", + "vph-ov-soft", + "ilim", + "temp-alarm"; + }; + }; +}; + +smb1390_slave: qcom,smb1390_slave@18 { + compatible = "qcom,i2c-pmic"; + reg = <0x18>; + #address-cells = <1>; + #size-cells = <0>; + qcom,periph-map = <0x10>; + status = "disabled"; + + smb1390_slave_charger: qcom,charge_pump_slave { + compatible = "qcom,smb1390-slave"; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/spi-panel-st7789v2-qvga-cmd.dtsi b/arch/arm/boot/dts/qcom/spi-panel-st7789v2-qvga-cmd.dtsi new file mode 100644 index 000000000000..6340528838bf --- /dev/null +++ b/arch/arm/boot/dts/qcom/spi-panel-st7789v2-qvga-cmd.dtsi @@ -0,0 +1,50 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_spi_display { + spi_st7789v2_qvga_cmd: qcom,mdss_spi_st7789v2_qvga_cmd { + qcom,mdss-spi-panel-name = + "st7789v2 qvga command mode spi panel"; + qcom,mdss-spi-panel-destination = "display_1"; + qcom,mdss-spi-panel-controller = <&mdss_spi_panel>; + qcom,mdss-spi-panel-framerate = <30>; + qcom,mdss-spi-panel-te-per-vsync = <2>; + qcom,mdss-spi-panel-width = <240>; + qcom,mdss-spi-panel-height = <240>; + qcom,mdss-spi-bpp = <16>; + qcom,mdss-spi-on-command = [ + 96 01 11 + 00 02 36 00 + 00 02 3A 05 + 00 02 35 00 + 00 06 B2 0C 0C 00 33 33 + 00 02 B7 75 + 00 02 BB 3D + 00 02 C2 01 + 00 02 C3 19 + 00 02 04 20 + 00 02 C6 0F + 00 03 D0 A4 A1 + 00 0F E0 70 04 08 09 09 05 2A 33 + 41 07 13 13 29 2F + 00 0F E1 70 03 09 0A 09 06 2B 34 + 41 07 12 14 28 2E + 00 01 21 + 00 01 29 + 00 05 2A 00 00 00 EF + 00 05 2B 00 00 00 EF + 00 01 2C]; + qcom,mdss-spi-off-command = [20 01 28 + 20 01 10]; + qcom,mdss-spi-reset-sequence = <1 20>, <0 1>, <1 20>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/trinket-audio-overlay.dtsi new file mode 100644 index 000000000000..2568fab8077b --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-audio-overlay.dtsi @@ -0,0 +1,463 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&bolero { + qcom,num-macros = <4>; + qcom,va-without-decimation; + slew_rate_reg1 = <0xD8E000 0x0>; + slew_rate_val1 = <0x3 0x0>; + tx_macro: tx-macro@0a460000 { + compatible = "qcom,tx-macro"; + reg = <0x0a460000 0x0>; + clock-names = "tx_core_clk", "tx_npl_clk"; + clocks = <&clock_audio_tx_1 0>, + <&clock_audio_tx_2 0>; + qcom,tx-swr-gpios = <&tx_swr_gpios>; + qcom,tx-dmic-sample-rate = <2400000>; + swr2: tx_swr_master { + compatible = "qcom,swr-mstr"; + #address-cells = <2>; + #size-cells = <0>; + qcom,swr_master_id = <3>; + swrm-io-base = <0x0a470000 0x0>; + interrupts = <0 184 0>; + interrupt-names = "swr_master_irq"; + qcom,swr-wakeup-irq = <&tlmm 107 0>; + qcom,swr-wakeup-required = <1>; + qcom,swr-num-ports = <5>; + qcom,swr-port-mapping = <1 PCM_OUT1 0xF>, + <2 ADC1 0x1>, <2 ADC2 0x2>, + <3 ADC3 0x1>, <3 ADC4 0x2>, + <4 DMIC0 0x1>, <4 DMIC1 0x2>, + <4 DMIC2 0x4>, <4 DMIC3 0x8>, + <5 DMIC4 0x1>, <5 DMIC5 0x2>, + <5 DMIC6 0x4>, <5 DMIC7 0x8>; + qcom,swr-num-dev = <1>; + qcom,swr-clock-stop-mode0 = <1>; + qcom,swr-mstr-irq-wakeup-capable = <1>; + wcd937x_tx_slave: wcd937x-tx-slave { + compatible = "qcom,wcd937x-slave"; + reg = <0x0 0x01170223>; + }; + }; + }; + + rx_macro: rx-macro@0a440000 { + compatible = "qcom,rx-macro"; + reg = <0x0a440000 0x0>; + clock-names = "rx_core_clk", "rx_npl_clk"; + clocks = <&clock_audio_rx_1 0>, + <&clock_audio_rx_2 0>; + qcom,rx-swr-gpios = <&rx_swr_gpios>; + qcom,rx_mclk_mode_muxsel = <0x0a041020>; + qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>; + swr1: rx_swr_master { + compatible = "qcom,swr-mstr"; + #address-cells = <2>; + #size-cells = <0>; + qcom,swr_master_id = <2>; + swrm-io-base = <0x0a450000 0x0>; + interrupts = <0 188 0>; + interrupt-names = "swr_master_irq"; + qcom,swr-num-ports = <5>; + qcom,swr-port-mapping = <1 HPH_L 0x1>, + <1 HPH_R 0x2>, <2 CLSH 0x1>, + <3 COMP_L 0x1>, <3 COMP_R 0x2>, + <4 LO 0x1>, <5 DSD_L 0x1>, + <5 DSD_R 0x2>; + qcom,swr-num-dev = <1>; + qcom,swr-clock-stop-mode0 = <1>; + wcd937x_rx_slave: wcd937x-rx-slave { + compatible = "qcom,wcd937x-slave"; + reg = <0x0 0x01170224>; + }; + }; + }; + + wsa_macro: wsa-macro@0a480000 { + compatible = "qcom,wsa-macro"; + reg = <0x0a480000 0x0>; + clock-names = "wsa_core_clk", "wsa_npl_clk"; + clocks = <&clock_audio_wsa_1 0>, + <&clock_audio_wsa_2 0>; + qcom,wsa-swr-gpios = <&wsa_swr_gpios>; + qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x00 0x1E>; + swr0: wsa_swr_master { + compatible = "qcom,swr-mstr"; + #address-cells = <2>; + #size-cells = <0>; + qcom,swr_master_id = <1>; + swrm-io-base = <0x0a490000 0x0>; + interrupts = <0 79 0>; + interrupt-names = "swr_master_irq"; + qcom,swr-num-ports = <8>; + qcom,swr-port-mapping = <1 SPKR_L 0x1>, + <2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>, + <4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>, + <6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>, + <8 SPKR_R_VI 0x3>; + qcom,swr-num-dev = <1>; + wsa881x_0211: wsa881x@20170211 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x20170211>; + qcom,spkr-sd-n-node = <&wsa_spkr_en1>; + }; + + wsa881x_0212: wsa881x@20170212 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x20170212>; + qcom,spkr-sd-n-node = <&wsa_spkr_en1>; + }; + + wsa881x_0213: wsa881x@21170213 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x21170213>; + qcom,spkr-sd-n-node = <&wsa_spkr_en1>; + }; + + wsa881x_0214: wsa881x@21170214 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x21170214>; + qcom,spkr-sd-n-node = <&wsa_spkr_en1>; + }; + }; + }; + + va_macro: va-macro@0a4a0000 { + compatible = "qcom,va-macro"; + reg = <0x0a4a0000 0x0>; + clock-names = "va_core_clk"; + clocks = <&clock_audio_va 0>; + }; + + wcd937x_codec: wcd937x-codec { + compatible = "qcom,wcd937x-codec"; + qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>, + <0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>, + <2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>, + <3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>, + <4 DSD_R 0x2 0 DSD_R>; + qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>, + <1 ADC2 0x1 0 ADC3>, <1 ADC3 0x2 0 ADC4>, + <2 DMIC0 0x1 0 DMIC0>, <2 DMIC1 0x2 0 DMIC1>, + <2 MBHC 0x4 0 DMIC2>, <3 DMIC2 0x1 0 DMIC4>, + <3 DMIC3 0x2 0 DMIC5>, <3 DMIC4 0x4 0 DMIC6>, + <3 DMIC5 0x8 0 DMIC7>; + + qcom,wcd-rst-gpio-node = <&wcd937x_rst_gpio>; + qcom,rx-slave = <&wcd937x_rx_slave>; + qcom,tx-slave = <&wcd937x_tx_slave>; + + cdc-vdd-ldo-rxtx-supply = <&L9A>; + qcom,cdc-vdd-ldo-rxtx-voltage = <1800000 1800000>; + qcom,cdc-vdd-ldo-rxtx-current = <25000>; + + cdc-vddpx-1-supply = <&L9A>; + qcom,cdc-vddpx-1-voltage = <1800000 1800000>; + qcom,cdc-vddpx-1-current = <10000>; + + cdc-vdd-buck-supply = <&L14A>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <650000>; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + + qcom,cdc-static-supplies = "cdc-vdd-ldo-rxtx", + "cdc-vddpx-1"; + qcom,cdc-on-demand-supplies = "cdc-vdd-buck"; + }; +}; + +&sm6150_snd { + qcom,model = "trinket-idp-snd-card"; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; + qcom,ext-disp-audio-rx = <1>; + qcom,audio-routing = + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Analog Mic2", + "TX DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "TX DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "TX DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "TX DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "TX_AIF1 CAP", "VA_MCLK", + "TX_AIF2 CAP", "VA_MCLK", + "RX AIF1 PB", "VA_MCLK", + "RX AIF2 PB", "VA_MCLK", + "RX AIF3 PB", "VA_MCLK", + "RX AIF4 PB", "VA_MCLK", + "HPHL_OUT", "VA_MCLK", + "HPHR_OUT", "VA_MCLK", + "AUX_OUT", "VA_MCLK", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "IN3_AUX", "AUX_OUT", + "TX SWR_ADC0", "ADC1_OUTPUT", + "TX SWR_ADC2", "ADC2_OUTPUT", + "WSA SRC0_INP", "SRC0", + "WSA_TX DEC0_INP", "TX DEC0 MUX", + "WSA_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "WSA_SPK1 OUT", "VA_MCLK", + "WSA_SPK2 OUT", "VA_MCLK"; + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; + qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; + asoc-codec = <&stub_codec>, <&bolero>, <&ext_disp_audio_codec>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec", + "msm-ext-disp-audio-codec-rx"; + qcom,wsa-max-devs = <1>; + qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>, + <&wsa881x_0213>, <&wsa881x_0214>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", + "SpkrLeft", "SpkrRight"; + qcom,codec-max-aux-devs = <1>; + qcom,codec-aux-devs = <&wcd937x_codec>; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, + <&bolero>; +}; + +&soc { + cdc_dmic01_gpios: cdc_dmic01_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>; + pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>; + }; + + cdc_dmic23_gpios: cdc_dmic23_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>; + pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>; + }; + + wsa_swr_gpios: wsa_swr_clk_data_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wsa_swr_clk_active &wsa_swr_data_active>; + pinctrl-1 = <&wsa_swr_clk_sleep &wsa_swr_data_sleep>; + }; + + rx_swr_gpios: rx_swr_clk_data_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active>; + pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep>; + }; + + tx_swr_gpios: tx_swr_clk_data_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&tx_swr_clk_active &tx_swr_data1_active + &tx_swr_data2_active>; + pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data1_sleep + &tx_swr_data2_sleep>; + }; + + wsa_spkr_en1: wsa_spkr_en1_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-1 = <&spkr_1_sd_n_sleep>; + }; + + wcd937x_rst_gpio: msm_cdc_pinctrl@120 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&wcd937x_reset_active>; + pinctrl-1 = <&wcd937x_reset_sleep>; + }; + + clock_audio_wsa_1: wsa_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x309>; + #clock-cells = <1>; + }; + + clock_audio_wsa_2: wsa_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x30A>; + #clock-cells = <1>; + }; + + clock_audio_va: va_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x30B>; + #clock-cells = <1>; + }; + + clock_audio_rx_1: rx_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <22579200>; + qcom,codec-lpass-clk-id = <0x30E>; + #clock-cells = <1>; + }; + + clock_audio_rx_2: rx_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <22579200>; + qcom,codec-lpass-clk-id = <0x30F>; + #clock-cells = <1>; + }; + + clock_audio_tx_1: tx_core_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x30C>; + #clock-cells = <1>; + }; + + clock_audio_tx_2: tx_npl_clk { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-ext-clk-freq = <19200000>; + qcom,codec-lpass-clk-id = <0x30D>; + #clock-cells = <1>; + }; + + wcd9xxx_intc: wcd9xxx-irq { + status = "disabled"; + compatible = "qcom,wcd9xxx-irq"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&tlmm>; + qcom,gpio-connect = <&tlmm 110 0>; + pinctrl-names = "default"; + pinctrl-0 = <&wcd_intr_default>; + }; + + wcd_rst_gpio: tasha_rst_gpio { + status = "disabled"; + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&tasha_cdc_reset_active>; + pinctrl-1 = <&tasha_cdc_reset_sleep>; + }; + + clock_audio_native: audio_ext_clk_native { + status = "disabled"; + compatible = "qcom,audio-ref-clk"; + #clock-cells = <1>; + qcom,codec-ext-clk-src = ; + clock-names = "osr_clk"; + qcom,lpass-mclk-id = <0x116>; + qcom,codec-mclk-clk-freq = <11289600>; + qcom,audio-ref-clk-gpio = <&tlmm 112 0>; + pinctrl-names = "sleep", "active"; + pinctrl-0 = <&audio_ref_clk_sleep>; + pinctrl-1 = <&audio_ref_clk_active>; + }; + + clock_audio: audio_ext_clk { + status = "disabled"; + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = <0>; + qcom,use-pinctrl = <1>; + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&tasha_mclk_default>; + pinctrl-1 = <&tasha_mclk_default>; + qcom,audio-ref-clk-gpio = <&pm6125_gpios 1 0>; + clock-names = "osr_clk"; + clocks = <&pm6125_clkdiv>; + pmic-clock-names = "pm6125_div_clk1"; + qcom,node_has_rpm_clock; + #clock-cells = <1>; + }; + + dbu1: dbu1 { + compatible = "regulator-fixed"; + regulator-name = "dbu1"; + startup-delay-us = <0>; + enable-active-high; + }; +}; + +&slim_aud { + wcd9335: tasha_codec { + status = "disabled"; + compatible = "qcom,tasha-slim-pgd"; + elemental-addr = [00 01 a0 01 17 02]; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 + 30>; + + qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; + + clock-names = "wcd_clk", "wcd_native_clk"; + clocks = <&clock_audio 0>, + <&clock_audio_native 0>; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; + + cdc-vdd-buck-supply = <&dbu1>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <650000>; + + cdc-buck-sido-supply = <&dbu1>; + qcom,cdc-buck-sido-voltage = <1800000 1800000>; + qcom,cdc-buck-sido-current = <200000>; + + cdc-vdd-tx-h-supply = <&dbu1>; + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-tx-h-current = <25000>; + + cdc-vdd-rx-h-supply = <&dbu1>; + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-rx-h-current = <25000>; + + cdc-vddio-1-supply = <&dbu1>; + qcom,cdc-vddio-1-voltage = <1800000 1800000>; + qcom,cdc-vddio-1-current = <10000>; + + qcom,cdc-static-supplies = "cdc-vdd-buck", + "cdc-buck-sido", + "cdc-vdd-tx-h", + "cdc-vdd-rx-h", + "cdc-vddio-1"; + + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-slim-ifd = "tasha-slim-ifd"; + qcom,cdc-slim-ifd-elemental-addr = [00 00 a0 01 17 02]; + qcom,cdc-dmic-sample-rate = <4800000>; + qcom,cdc-mad-dmic-rate = <600000>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll-audio.dtsi b/arch/arm/boot/dts/qcom/trinket-audio.dtsi similarity index 69% rename from arch/arm64/boot/dts/qcom/atoll-audio.dtsi rename to arch/arm/boot/dts/qcom/trinket-audio.dtsi index 9f0a1900f936..1cce93e729f7 100644 --- a/arch/arm64/boot/dts/qcom/atoll-audio.dtsi +++ b/arch/arm/boot/dts/qcom/trinket-audio.dtsi @@ -11,19 +11,18 @@ * GNU General Public License for more details. */ -#include #include "msm-audio-lpass.dtsi" &msm_audio_ion { - iommus = <&apps_smmu 0x1001 0x0>; + iommus = <&apps_smmu 0x0041 0x0>; qcom,smmu-sid-mask = /bits/ 64 <0xf>; }; &soc { - qcom,avtimer@62DF0000 { + qcom,avtimer@0a22e000 { compatible = "qcom,avtimer"; - reg = <0x62DF000C 0x4>, - <0x62DF0010 0x4>; + reg = <0x0a22e00c 0x4>, + <0x0a22e010 0x4>; reg-names = "avtimer_lsb_addr", "avtimer_msb_addr"; qcom,clk-div = <192>; qcom,clk-mult = <10>; @@ -33,40 +32,19 @@ &audio_apr { q6core: qcom,q6core-audio { compatible = "qcom,q6core-audio"; - - lpass_core_hw_vote: vote_lpass_core_hw { - compatible = "qcom,audio-ref-clk"; - qcom,codec-ext-clk-src = ; - #clock-cells = <1>; - }; - - lpass_audio_hw_vote: vote_lpass_audio_hw { - compatible = "qcom,audio-ref-clk"; - qcom,codec-ext-clk-src = ; - #clock-cells = <1>; - }; - bolero: bolero-cdc { compatible = "qcom,bolero-codec"; - clock-names = "lpass_core_hw_vote", - "lpass_audio_hw_vote"; - clocks = <&lpass_core_hw_vote 0>, - <&lpass_audio_hw_vote 0>; - bolero-clk-rsc-mngr { - compatible = "qcom,bolero-clk-rsc-mngr"; - }; - - tx_macro: tx-macro@62620000 { + tx_macro: tx-macro@0a460000 { swr2: tx_swr_master { }; }; - rx_macro: rx-macro@62600000 { + rx_macro: rx-macro@0a440000 { swr1: rx_swr_master { }; }; - wsa_macro: wsa-macro@62640000 { + wsa_macro: wsa-macro@0a480000 { swr0: wsa_swr_master { }; }; @@ -75,13 +53,11 @@ }; &q6core { - atoll_snd: sound { - compatible = "qcom,kona-asoc-snd"; + sm6150_snd: sound { + compatible = "qcom,sm6150-asoc-snd"; qcom,mi2s-audio-intf = <1>; qcom,auxpcm-audio-intf = <1>; - qcom,wcn-btfm = <0>; - qcom,ext-disp-audio-rx = <0>; - qcom,afe-rxtx-lb = <0>; + qcom,wcn-btfm = <1>; asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, <&loopback>, <&compress>, <&hostless>, @@ -97,64 +73,54 @@ asoc-cpu = <&dai_dp>, <&dai_mi2s0>, <&dai_mi2s1>, <&dai_mi2s2>, <&dai_mi2s3>, - <&dai_mi2s4>, <&dai_mi2s5>, <&dai_pri_auxpcm>, + <&dai_mi2s4>, <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, - <&dai_sen_auxpcm>, <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, <&afe_proxy_tx>, <&incall_record_rx>, <&incall_record_tx>, <&incall_music_rx>, <&incall_music_2_rx>, + <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, <&sb_8_rx>, <&usb_audio_rx>, <&usb_audio_tx>, - <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>, - <&dai_sen_tdm_rx_0>, <&dai_sen_tdm_tx_0>, <&wsa_cdc_dma_0_rx>, <&wsa_cdc_dma_0_tx>, <&wsa_cdc_dma_1_rx>, <&wsa_cdc_dma_1_tx>, <&wsa_cdc_dma_2_tx>, - <&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>, - <&va_cdc_dma_2_tx>, <&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>, <&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>, <&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>, <&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>, <&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>, <&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>, - <&rx_cdc_dma_6_rx>, <&rx_cdc_dma_7_rx>, - <&afe_loopback_tx>; + <&rx_cdc_dma_6_rx>, <&rx_cdc_dma_7_rx>; asoc-cpu-names = "msm-dai-q6-dp.24608", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", - "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5", - "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", - "msm-dai-q6-auxpcm.6", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", - "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16398", + "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", + "msm-dai-q6-dev.16400", "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", - "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", - "msm-dai-q6-dev.16401", "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", "msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36929", - "msm-dai-q6-tdm.36944", "msm-dai-q6-tdm.36945", "msm-dai-cdc-dma-dev.45056", "msm-dai-cdc-dma-dev.45057", "msm-dai-cdc-dma-dev.45058", "msm-dai-cdc-dma-dev.45059", "msm-dai-cdc-dma-dev.45061", - "msm-dai-cdc-dma-dev.45089", - "msm-dai-cdc-dma-dev.45091", - "msm-dai-cdc-dma-dev.45093", "msm-dai-cdc-dma-dev.45104", "msm-dai-cdc-dma-dev.45105", "msm-dai-cdc-dma-dev.45106", @@ -168,8 +134,16 @@ "msm-dai-cdc-dma-dev.45114", "msm-dai-cdc-dma-dev.45115", "msm-dai-cdc-dma-dev.45116", - "msm-dai-cdc-dma-dev.45118", - "msm-dai-q6-dev.24577"; + "msm-dai-cdc-dma-dev.45118"; + fsa4480-i2c-handle = <&fsa4480>; }; }; +&slim_aud { + status = "disabled"; + dai_slim: msm_dai_slim { + status = "disabled"; + compatible = "qcom,msm-dai-slim"; + elemental-addr = [ff ff ff fe 17 02]; + }; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-bus.dtsi b/arch/arm/boot/dts/qcom/trinket-bus.dtsi new file mode 100644 index 000000000000..d569bfb39817 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-bus.dtsi @@ -0,0 +1,1117 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&soc { + ad_hoc_bus: ad-hoc-bus { + compatible = "qcom,msm-bus-device"; + reg = <0x1880000 0x60200>, + <0x4480000 0x80000>, + <0x1900000 0x8200>, + <0x1880000 0x60200>, + <0x1880000 0x60200>, + <0x1880000 0x60200>, + <0x1880000 0x60200>; + reg-names = "sys_noc-base", "bimc-base", "config_noc-base", + "qup_virt-base", "fab-gpu_vert-base", + "mmnrt_virt-base", "mmrt_virt-base"; + + /*Buses*/ + + fab_bimc: fab-bimc { + cell-id = ; + label = "fab-bimc"; + qcom,fab-dev; + qcom,base-name = "bimc-base"; + qcom,bus-type = <2>; + qcom,util-fact = <153>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_rpmcc BIMC_MSMBUS_CLK>, + <&clock_rpmcc BIMC_MSMBUS_A_CLK>; + }; + + fab_config_noc: fab-config_noc { + cell-id = ; + label = "fab-config_noc"; + qcom,fab-dev; + qcom,base-name = "config_noc-base"; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_rpmcc CNOC_MSMBUS_CLK>, + <&clock_rpmcc CNOC_MSMBUS_A_CLK>; + }; + + fab_qup_virt: fab-qup_virt { + cell-id = ; + label = "fab-qup_virt"; + qcom,fab-dev; + qcom,base-name = "qup_virt-base"; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_rpmcc RPM_SMD_QUP_CLK>, + <&clock_rpmcc RPM_SMD_QUP_A_CLK>; + }; + + fab_sys_noc: fab-sys_noc { + cell-id = ; + label = "fab-sys_noc"; + qcom,fab-dev; + qcom,base-name = "sys_noc-base"; + qcom,bus-type = <3>; + qcom,base-offset = <0x15000>; + qcom,qos-off = <0x1000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_rpmcc SNOC_MSMBUS_CLK>, + <&clock_rpmcc SNOC_MSMBUS_A_CLK>; + }; + + fab_gpu_vert: fab-gpu_vert { + cell-id = ; + label = "fab-gpu_vert"; + qcom,vert-dev; + qcom,base-name = "fab-gpu_vert-base"; + qcom,bypass-qos-prg; + qcom,bus-type = <3>; + }; + + fab_mmnrt_virt: fab-mmnrt_virt { + cell-id = ; + label = "fab-mmnrt_virt"; + qcom,fab-dev; + qcom,base-name = "mmnrt_virt-base"; + qcom,bus-type = <3>; + qcom,base-offset = <0x15000>; + qcom,qos-off = <0x1000>; + qcom,util-fact = <142>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_rpmcc CPP_MMNRT_MSMBUS_CLK>, + <&clock_rpmcc CPP_MMNRT_MSMBUS_A_CLK>; + }; + + fab_mmrt_virt: fab-mmrt_virt { + cell-id = ; + label = "fab-mmrt_virt"; + qcom,fab-dev; + qcom,base-name = "mmrt_virt-base"; + qcom,bus-type = <3>; + qcom,base-offset = <0x15000>; + qcom,qos-off = <0x1000>; + qcom,util-fact = <139>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_rpmcc MDP_MMRT_MSMBUS_CLK>, + <&clock_rpmcc MDP_MMRT_MSMBUS_A_CLK>; + }; + + /*Masters*/ + + mas_apps_proc: mas-apps-proc { + cell-id = ; + label = "mas-apps-proc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <0>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_ebi &slv_bimc_snoc>; + qcom,prio-lvl = <0>; + qcom,prio-rd = <0>; + qcom,prio-wr = <0>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_snoc_bimc_rt: mas-snoc-bimc-rt { + cell-id = ; + label = "mas-snoc-bimc-rt"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <2>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_ebi>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_snoc_bimc_nrt: mas-snoc-bimc-nrt { + cell-id = ; + label = "mas-snoc-bimc-nrt"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <3>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_ebi>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_snoc_bimc: mas-snoc-bimc { + cell-id = ; + label = "mas-snoc-bimc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <6>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_ebi>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_gpu_cdsp_bimc: mas-gpu-cdsp-bimc { + cell-id = ; + label = "mas-gpu-cdsp-bimc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <1>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_ebi &slv_bimc_snoc>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_tcu_0: mas-tcu-0 { + cell-id = ; + label = "mas-tcu-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <4>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_ebi &slv_bimc_snoc>; + qcom,prio-lvl = <6>; + qcom,prio-rd = <6>; + qcom,prio-wr = <6>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_snoc_cnoc: mas-snoc-cnoc { + cell-id = ; + label = "mas-snoc-cnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_qhs_tlmm_south + &slv_qhs_camera_rt_throttle_cfg + &slv_qhs_cdsp_throttle_cfg &slv_qhs_sdc2 + &slv_qhs_sdc1 &slv_qhs_ufs_mem_cfg + &slv_qhs_qm_cfg &slv_qhs_tlmm_east + &slv_qhs_bimc_cfg &slv_qhs_qm_mpu_cfg + &slv_qhs_camera_nrt_throttle_cfg + &slv_qhs_tlmm_west &slv_qhs_qdss_cfg + &slv_qhs_pdm &slv_qhs_ipa_cfg + &slv_qhs_display_throttle_cfg &slv_qhs_tcsr + &slv_qhs_mesg_ram &slv_qhs_pmic_arb + &slv_qhs_lpass &slv_qhs_venus_cfg + &slv_qhs_gpu_cfg &slv_qhs_imem_cfg + &slv_snoc_cfg &slv_srvc_cnoc + &slv_qhs_venus_throttle_cfg &slv_qhs_prng + &slv_qhs_vsense_ctrl_cfg &slv_qhs_crypto0_cfg + &slv_qhs_pimem_cfg &slv_qhs_usb3 + &slv_qhs_qup0 &slv_qhs_qup1 + &slv_qhs_camera_ss_cfg &slv_qhs_clk_ctl>; + qcom,bus-dev = <&fab_config_noc>; + qcom,mas-rpm-id = ; + }; + + mas_crypto_c0: mas-crypto-c0 { + cell-id = ; + label = "mas-crypto-c0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <22>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_anoc_snoc>; + qcom,prio = <2>; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc CRYPTO_MSMBUS_SNOC_PERIPH_CLK>, + <&clock_rpmcc CRYPTO_MSMBUS_SNOC_PERIPH_A_CLK>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_qup_core_master_0: mas-qup-core-master-0 { + cell-id = ; + label = "mas-qup-core-master-0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qup_core_slave_0>; + qcom,bus-dev = <&fab_qup_virt>; + qcom,mas-rpm-id = ; + }; + + mas_qup_core_master_1: mas-qup-core-master-1 { + cell-id = ; + label = "mas-qup-core-master-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qup_core_slave_1>; + qcom,bus-dev = <&fab_qup_virt>; + qcom,mas-rpm-id = ; + }; + + mas_snoc_cfg: mas-snoc-cfg { + cell-id = ; + label = "mas-snoc-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_srvc_snoc>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_anoc_snoc: mas-anoc-snoc { + cell-id = ; + label = "mas-anoc-snoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qxs_pimem &slv_qxs_imem + &slv_qhs_apss &slv_snoc_bimc + &slv_snoc_cnoc &slv_xs_sys_tcu_cfg + &slv_xs_qdss_stm>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_bimc_snoc: mas-bimc-snoc { + cell-id = ; + label = "mas-bimc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_qxs_pimem &slv_qxs_imem + &slv_qhs_apss &slv_snoc_cnoc + &slv_xs_sys_tcu_cfg &slv_xs_qdss_stm>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_qxm_cpp: mas-qxm-cpp { + cell-id = ; + label = "mas-qxm-cpp"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <15>; + qcom,qos-mode = "fixed"; + qcom,prio = <3>; + qcom,connections = <&slv_snoc_bimc_nrt>; + qcom,bus-dev = <&fab_mmnrt_virt>; + qcom,mas-rpm-id = ; + }; + + mas_qxm_jpeg: mas-qxm-jpeg { + cell-id = ; + label = "mas-qxm-jpeg"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <4>; + qcom,qos-mode = "fixed"; + qcom,prio = <1>; + qcom,connections = <&slv_snoc_bimc_nrt>; + qcom,bus-dev = <&fab_mmnrt_virt>; + qcom,mas-rpm-id = ; + }; + + mas_qxm_mdp0: mas-qxm-mdp0 { + cell-id = ; + label = "mas-qxm-mdp0"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <5>; + qcom,qos-mode = "bypass"; + qcom,forwarding; + qcom,connections = <&slv_snoc_bimc_rt>; + qcom,bus-dev = <&fab_mmrt_virt>; + qcom,mas-rpm-id = ; + }; + + mas_qxm_pimem: mas-qxm-pimem { + cell-id = ; + label = "mas-qxm-pimem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <20>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_qxs_imem &slv_snoc_bimc>; + qcom,prio = <2>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_qxm_venus0: mas-qxm-venus0 { + cell-id = ; + label = "mas-qxm-venus0"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <9>; + qcom,qos-mode = "bypass"; + qcom,forwarding; + qcom,connections = <&slv_snoc_bimc_nrt>; + qcom,bus-dev = <&fab_mmnrt_virt>; + qcom,mas-rpm-id = ; + }; + + mas_qxm_venus_arm9: mas-qxm-venus-arm9 { + cell-id = ; + label = "mas-qxm-venus-arm9"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <13>; + qcom,qos-mode = "fixed"; + qcom,prio = <4>; + qcom,forwarding; + qcom,connections = <&slv_snoc_bimc_nrt>; + qcom,bus-dev = <&fab_mmnrt_virt>; + qcom,mas-rpm-id = ; + + }; + + mas_qxm_vfe0: mas-qxm-vfe0 { + cell-id = ; + label = "mas-qxm-vfe0"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <10>; + qcom,qos-mode = "bypass"; + qcom,forwarding; + qcom,connections = <&slv_snoc_bimc_rt>; + qcom,bus-dev = <&fab_mmrt_virt>; + qcom,mas-rpm-id = ; + }; + + mas_qhm_qdss_bam: mas-qhm-qdss-bam { + cell-id = ; + label = "mas-qhm-qdss-bam"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <2>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_anoc_snoc>; + qcom,prio = <2>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_qhm_qup0: mas-qhm-qup0 { + cell-id = ; + label = "mas-qhm-qup0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <0>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_anoc_snoc>; + qcom,prio = <2>; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc QUP0_MSMBUS_SNOC_PERIPH_CLK>, + <&clock_rpmcc QUP0_MSMBUS_SNOC_PERIPH_A_CLK>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_qhm_qup1: mas-qhm-qup1 { + cell-id = ; + label = "mas-qhm-qup1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <1>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_anoc_snoc>; + qcom,prio = <2>; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc QUP1_MSMBUS_SNOC_PERIPH_CLK>, + <&clock_rpmcc QUP1_MSMBUS_SNOC_PERIPH_A_CLK>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_qhm_spdm: mas-qhm-spdm { + cell-id = ; + label = "mas-qhm-spdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_anoc_snoc>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_qxm_ipa: mas-qxm-ipa { + cell-id = ; + label = "mas-qxm-ipa"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <3>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_anoc_snoc>; + qcom,prio = <2>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_xm_dap: mas-xm-dap { + cell-id = ; + label = "mas-xm-dap"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_anoc_snoc>; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc DAP_MSMBUS_SNOC_PERIPH_CLK>, + <&clock_rpmcc DAP_MSMBUS_SNOC_PERIPH_A_CLK>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_xm_qdss_etr: mas-xm-qdss-etr { + cell-id = ; + label = "mas-xm-qdss-etr"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <12>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_anoc_snoc>; + qcom,prio = <2>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_xm_sdc1: mas-xm-sdc1 { + cell-id = ; + label = "mas-xm-sdc1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <17>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_anoc_snoc>; + qcom,prio = <2>; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc SDC1_MSMBUS_SNOC_PERIPH_CLK>, + <&clock_rpmcc SDC1_MSMBUS_SNOC_PERIPH_A_CLK>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_xm_sdc2: mas-xm-sdc2 { + cell-id = ; + label = "mas-xm-sdc2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <23>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_anoc_snoc>; + qcom,prio = <2>; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc SDC2_MSMBUS_SNOC_PERIPH_CLK>, + <&clock_rpmcc SDC2_MSMBUS_SNOC_PERIPH_A_CLK>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_xm_ufs_mem: mas-xm-ufs-mem { + cell-id = ; + label = "mas-xm-ufs-mem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <25>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_anoc_snoc>; + qcom,prio = <2>; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc RPM_SMD_SNOC_LPASS_CLK>, + <&clock_rpmcc RPM_SMD_SNOC_LPASS_A_CLK>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_xm_usb3_0: mas-xm-usb3-0 { + cell-id = ; + label = "mas-xm-usb3-0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <24>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_anoc_snoc>; + qcom,prio = <2>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,mas-rpm-id = ; + }; + + mas_qnm_gpu_qos: mas-qnm-gpu-qos { + cell-id = ; + label = "mas-qnm-gpu-qos"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <16>; + qcom,qos-mode = "fixed"; + qcom,bus-dev = <&fab_sys_noc>; + qcom,prio = <0>; + qcom,mas-rpm-id = ; + }; + + mas_qnm_gpu: mas-qnm-gpu { + cell-id = ; + label = "mas-qnm-gpu"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_gpu_cdsp_bimc>; + qcom,bus-dev = <&fab_gpu_vert>; + qcom,mas-rpm-id = ; + + }; + + /*Slaves*/ + + slv_ebi:slv-ebi { + cell-id = ; + label = "slv-ebi"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_bimc>; + qcom,slv-rpm-id = ; + }; + + slv_bimc_snoc:slv-bimc-snoc { + cell-id = ; + label = "slv-bimc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_bimc>; + qcom,connections = <&mas_bimc_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_bimc_cfg:slv-qhs-bimc-cfg { + cell-id = ; + label = "slv-qhs-bimc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_camera_nrt_throttle_cfg:slv-qhs-camera-nrt-throtle-cfg { + cell-id = ; + label = "slv-qhs-camera-nrt-throttle-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_camera_rt_throttle_cfg:slv-qhs-camera-rt-throttle-cfg { + cell-id = ; + label = "slv-qhs-camera-rt-throttle-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_camera_ss_cfg:slv-qhs-camera-ss-cfg { + cell-id = ; + label = "slv-qhs-camera-ss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_cdsp_throttle_cfg:slv-qhs-cdsp-throttle-cfg { + cell-id = ; + label = "slv-qhs-cdsp-throttle-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_clk_ctl:slv-qhs-clk-ctl { + cell-id = ; + label = "slv-qhs-clk-ctl"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_crypto0_cfg:slv-qhs-crypto0-cfg { + cell-id = ; + label = "slv-qhs-crypto0-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_display_throttle_cfg:slv-qhs-display-throttle-cfg { + cell-id = ; + label = "slv-qhs-display-throttle-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_gpu_cfg:slv-qhs-gpu-cfg { + cell-id = ; + label = "slv-qhs-gpu-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_imem_cfg:slv-qhs-imem-cfg { + cell-id = ; + label = "slv-qhs-imem-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_ipa_cfg:slv-qhs-ipa-cfg { + cell-id = ; + label = "slv-qhs-ipa-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_lpass:slv-qhs-lpass { + cell-id = ; + label = "slv-qhs-lpass"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_mesg_ram:slv-qhs-mesg-ram { + cell-id = ; + label = "slv-qhs-mesg-ram"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_pdm:slv-qhs-pdm { + cell-id = ; + label = "slv-qhs-pdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_pimem_cfg:slv-qhs-pimem-cfg { + cell-id = ; + label = "slv-qhs-pimem-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_pmic_arb:slv-qhs-pmic-arb { + cell-id = ; + label = "slv-qhs-pmic-arb"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_prng:slv-qhs-prng { + cell-id = ; + label = "slv-qhs-prng"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_qdss_cfg:slv-qhs-qdss-cfg { + cell-id = ; + label = "slv-qhs-qdss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_qm_cfg:slv-qhs-qm-cfg { + cell-id = ; + label = "slv-qhs-qm-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_qm_mpu_cfg:slv-qhs-qm-mpu-cfg { + cell-id = ; + label = "slv-qhs-qm-mpu-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_qup0:slv-qhs-qup0 { + cell-id = ; + label = "slv-qhs-qup0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_qup1:slv-qhs-qup1 { + cell-id = ; + label = "slv-qhs-qup1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_sdc1:slv-qhs-sdc1 { + cell-id = ; + label = "slv-qhs-sdc1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc SDC1_SLV_MSMBUS_SNOC_PERIPH_CLK>, + <&clock_rpmcc + SDC1_SLV_MSMBUS_SNOC_PERIPH_A_CLK>; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_sdc2:slv-qhs-sdc2 { + cell-id = ; + label = "slv-qhs-sdc2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + clock-names = "node_clk", "node_a_clk"; + clocks = <&clock_rpmcc SDC2_SLV_MSMBUS_SNOC_PERIPH_CLK>, + <&clock_rpmcc + SDC2_SLV_MSMBUS_SNOC_PERIPH_A_CLK>; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_snoc_cfg:slv-snoc-cfg { + cell-id = ; + label = "slv-snoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,connections = <&mas_snoc_cfg>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_tcsr:slv-qhs-tcsr { + cell-id = ; + label = "slv-qhs-tcsr"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_tlmm_east:slv-qhs-tlmm-east { + cell-id = ; + label = "slv-qhs-tlmm-east"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_tlmm_south:slv-qhs-tlmm-south { + cell-id = ; + label = "slv-qhs-tlmm-south"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_tlmm_west:slv-qhs-tlmm-west { + cell-id = ; + label = "slv-qhs-tlmm-west"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_ufs_mem_cfg:slv-qhs-ufs-mem-cfg { + cell-id = ; + label = "slv-qhs-ufs-mem-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_usb3:slv-qhs-usb3 { + cell-id = ; + label = "slv-qhs-usb3"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_venus_cfg:slv-qhs-venus-cfg { + cell-id = ; + label = "slv-qhs-venus-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_venus_throttle_cfg:slv-qhs-venus-throttle-cfg { + cell-id = ; + label = "slv-qhs-venus-throttle-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_vsense_ctrl_cfg:slv-qhs-vsense-ctrl-cfg { + cell-id = ; + label = "slv-qhs-vsense-ctrl-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_srvc_cnoc:slv-srvc-cnoc { + cell-id = ; + label = "slv-srvc-cnoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_config_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qup_core_slave_0:slv-qup-core-slave-0 { + cell-id = ; + label = "slv-qup-core-slave-0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_qup_virt>; + qcom,slv-rpm-id = ; + }; + + slv_qup_core_slave_1:slv-qup-core-slave-1 { + cell-id = ; + label = "slv-qup-core-slave-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_qup_virt>; + qcom,slv-rpm-id = ; + }; + + slv_qhs_apss:slv-qhs-apss { + cell-id = ; + label = "slv-qhs-apss"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_sys_noc>; + qcom,slv-rpm-id = ; + }; + + slv_snoc_bimc_nrt:slv-snoc-bimc-nrt { + cell-id = ; + label = "slv-snoc-bimc-nrt"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mmnrt_virt>; + qcom,connections = <&mas_snoc_bimc_nrt>; + qcom,slv-rpm-id = ; + }; + + slv_snoc_bimc_rt:slv-snoc-bimc-rt { + cell-id = ; + label = "slv-snoc-bimc-rt"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mmrt_virt>; + qcom,connections = <&mas_snoc_bimc_rt>; + qcom,slv-rpm-id = ; + }; + + slv_snoc_cnoc:slv-snoc-cnoc { + cell-id = ; + label = "slv-snoc-cnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,connections = <&mas_snoc_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_qxs_imem:slv-qxs-imem { + cell-id = ; + label = "slv-qxs-imem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,slv-rpm-id = ; + }; + + slv_qxs_pimem:slv-qxs-pimem { + cell-id = ; + label = "slv-qxs-pimem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_sys_noc>; + qcom,slv-rpm-id = ; + }; + + slv_snoc_bimc:slv-snoc-bimc { + cell-id = ; + label = "slv-snoc-bimc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,connections = <&mas_snoc_bimc>; + qcom,slv-rpm-id = ; + }; + + slv_srvc_snoc:slv-srvc-snoc { + cell-id = ; + label = "slv-srvc-snoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_sys_noc>; + qcom,slv-rpm-id = ; + }; + + slv_xs_qdss_stm:slv-xs-qdss-stm { + cell-id = ; + label = "slv-xs-qdss-stm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,slv-rpm-id = ; + }; + + slv_xs_sys_tcu_cfg:slv-xs-sys-tcu-cfg { + cell-id = ; + label = "slv-xs-sys-tcu-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_sys_noc>; + qcom,slv-rpm-id = ; + }; + + slv_anoc_snoc:slv-anoc-snoc { + cell-id = ; + label = "slv-anoc-snoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_sys_noc>; + qcom,connections = <&mas_anoc_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_gpu_cdsp_bimc:slv-gpu-cdsp-bimc { + cell-id = ; + label = "slv-gpu-cdsp-bimc"; + qcom,buswidth = <32>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_gpu_vert>; + qcom,connections = <&mas_gpu_cdsp_bimc>; + qcom,slv-rpm-id = ; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-camera-sensor-idp.dtsi b/arch/arm/boot/dts/qcom/trinket-camera-sensor-idp.dtsi new file mode 100644 index 000000000000..fa723548bcb4 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-camera-sensor-idp.dtsi @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + led_flash0: qcom,camera-flash@0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + qcom,flash-source = <&pmi632_flash0 &pmi632_flash1>; + qcom,torch-source = <&pmi632_torch0 &pmi632_torch1>; + qcom,switch-source = <&pmi632_switch0 &pmi632_switch0>; + status = "ok"; + }; +}; + +&cci { + actuator0: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + cam_vaf-supply = <&L5P>; + qcom,cam-vreg-name = "cam_vaf"; + qcom,cam-vreg-min-voltage = <2800000>; + qcom,cam-vreg-max-voltage = <2800000>; + qcom,cam-vreg-op-mode = <0>; + }; + + actuator1: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + qcom,cci-master = <1>; + cam_vaf-supply = <&L5P>; + qcom,cam-vreg-name = "cam_vaf"; + qcom,cam-vreg-min-voltage = <2800000>; + qcom,cam-vreg-max-voltage = <2800000>; + qcom,cam-vreg-op-mode = <0>; + }; + + eeprom0: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L12A>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&camss_top_gdsc>; + cam_vaf-supply = <&L5P>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + qcom,cam-vreg-min-voltage = <1800000 2800000 1104000 0 2800000>; + qcom,cam-vreg-max-voltage = <1800000 2800000 1104000 0 2800000>; + qcom,cam-vreg-op-mode = <0 80000 105000 0 100000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 34 0>, + <&tlmm 48 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + qcom,sensor-position = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_gcc GCC_CAMSS_MCLK0_CLK_SRC>, + <&clock_gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + eeprom1: qcom,eeprom@1 { + cell-index = <1>; + reg = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L12A>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&camss_top_gdsc>; + cam_vaf-supply = <&L5P>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + qcom,cam-vreg-min-voltage = <1800000 2800000 1200000 0 2800000>; + qcom,cam-vreg-max-voltage = <1800000 2800000 1200000 0 2800000>; + qcom,cam-vreg-op-mode = <0 80000 105000 0 100000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 35 0>, + <&tlmm 46 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + qcom,sensor-position = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_gcc GCC_CAMSS_MCLK1_CLK_SRC>, + <&clock_gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + eeprom2: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L12A>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&camss_top_gdsc>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + qcom,cam-vreg-min-voltage = <1800000 2800000 1200000 0>; + qcom,cam-vreg-max-voltage = <1800000 2800000 1200000 0>; + qcom,cam-vreg-op-mode = <0 80000 105000 0>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 36 0>, + <&tlmm 42 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_gcc GCC_CAMSS_MCLK2_CLK_SRC>, + <&clock_gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@0 { + cell-index = <0>; + compatible = "qcom,camera"; + reg = <0x0>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <90>; + qcom,actuator-src = <&actuator0>; + qcom,eeprom-src = <&eeprom0>; + qcom,led-flash-src = <&led_flash0>; + cam_vio-supply = <&L12A>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&camss_top_gdsc>; + cam_vaf-supply = <&L5P>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + qcom,cam-vreg-min-voltage = <1800000 2800000 1104000 0 2800000>; + qcom,cam-vreg-max-voltage = <1800000 2800000 1104000 0 2800000>; + qcom,cam-vreg-op-mode = <0 80000 105000 0 100000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 34 0>, + <&tlmm 48 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_gcc GCC_CAMSS_MCLK0_CLK_SRC>, + <&clock_gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@1 { + cell-index = <1>; + compatible = "qcom,camera"; + reg = <0x1>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <1>; + qcom,mount-angle = <90>; + qcom,actuator-src = <&actuator1>; + qcom,eeprom-src = <&eeprom1>; + cam_vio-supply = <&L12A>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&camss_top_gdsc>; + cam_vaf-supply = <&L5P>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + qcom,cam-vreg-min-voltage = <1800000 2800000 1200000 0 2800000>; + qcom,cam-vreg-max-voltage = <1800000 2800000 1200000 0 2800000>; + qcom,cam-vreg-op-mode = <0 80000 105000 0 100000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 35 0>, + <&tlmm 46 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_gcc GCC_CAMSS_MCLK1_CLK_SRC>, + <&clock_gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@2 { + cell-index = <2>; + compatible = "qcom,camera"; + reg = <0x02>; + qcom,csiphy-sd-index = <2>; + qcom,csid-sd-index = <2>; + qcom,mount-angle = <90>; + qcom,eeprom-src = <&eeprom2>; + cam_vio-supply = <&L12A>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&camss_top_gdsc>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + qcom,cam-vreg-min-voltage = <1800000 2800000 1200000 0>; + qcom,cam-vreg-max-voltage = <1800000 2800000 1200000 0>; + qcom,cam-vreg-op-mode = <0 80000 105000 0>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 36 0>, + <&tlmm 42 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_gcc GCC_CAMSS_MCLK2_CLK_SRC>, + <&clock_gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + +}; diff --git a/arch/arm/boot/dts/qcom/trinket-camera-sensor-qrd.dtsi b/arch/arm/boot/dts/qcom/trinket-camera-sensor-qrd.dtsi new file mode 100644 index 000000000000..430397e0ff74 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-camera-sensor-qrd.dtsi @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + led_flash0: qcom,camera-flash@0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + qcom,flash-source = <&pmi632_flash0 &pmi632_flash1>; + qcom,torch-source = <&pmi632_torch0 &pmi632_torch1>; + qcom,switch-source = <&pmi632_switch0 &pmi632_switch0>; + status = "ok"; + }; +}; + +&cci { + actuator0: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + cam_vaf-supply = <&L5P>; + qcom,cam-vreg-name = "cam_vaf"; + qcom,cam-vreg-min-voltage = <2800000>; + qcom,cam-vreg-max-voltage = <2800000>; + qcom,cam-vreg-op-mode = <0>; + }; + + eeprom0: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L12A>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&camss_top_gdsc>; + cam_vaf-supply = <&L5P>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + qcom,cam-vreg-min-voltage = <1800000 2800000 1104000 0 2800000>; + qcom,cam-vreg-max-voltage = <1800000 2800000 1104000 0 2800000>; + qcom,cam-vreg-op-mode = <0 80000 105000 0 100000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 34 0>, + <&tlmm 48 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + qcom,sensor-position = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_gcc GCC_CAMSS_MCLK0_CLK_SRC>, + <&clock_gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + eeprom1: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L12A>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&camss_top_gdsc>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + qcom,cam-vreg-min-voltage = <1800000 2800000 1200000 0>; + qcom,cam-vreg-max-voltage = <1800000 2800000 1200000 0>; + qcom,cam-vreg-op-mode = <0 80000 105000 0>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 36 0>, + <&tlmm 42 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_gcc GCC_CAMSS_MCLK2_CLK_SRC>, + <&clock_gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@0 { + cell-index = <0>; + compatible = "qcom,camera"; + reg = <0x0>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <90>; + qcom,actuator-src = <&actuator0>; + qcom,eeprom-src = <&eeprom0>; + qcom,led-flash-src = <&led_flash0>; + cam_vio-supply = <&L12A>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&camss_top_gdsc>; + cam_vaf-supply = <&L5P>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + qcom,cam-vreg-min-voltage = <1800000 2800000 1104000 0 2800000>; + qcom,cam-vreg-max-voltage = <1800000 2800000 1104000 0 2800000>; + qcom,cam-vreg-op-mode = <0 80000 105000 0 100000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 34 0>, + <&tlmm 48 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_gcc GCC_CAMSS_MCLK0_CLK_SRC>, + <&clock_gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@1 { + cell-index = <1>; + compatible = "qcom,camera"; + reg = <0x1>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <1>; + qcom,mount-angle = <90>; + cam_vio-supply = <&L12A>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&camss_top_gdsc>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + qcom,cam-vreg-min-voltage = <1800000 2800000 1200000 0>; + qcom,cam-vreg-max-voltage = <1800000 2800000 1200000 0>; + qcom,cam-vreg-op-mode = <0 80000 105000 0>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 35 0>, + <&tlmm 46 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_gcc GCC_CAMSS_MCLK1_CLK_SRC>, + <&clock_gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@2 { + cell-index = <2>; + compatible = "qcom,camera"; + reg = <0x02>; + qcom,csiphy-sd-index = <2>; + qcom,csid-sd-index = <2>; + qcom,mount-angle = <90>; + qcom,eeprom-src = <&eeprom1>; + cam_vio-supply = <&L12A>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&camss_top_gdsc>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + qcom,cam-vreg-min-voltage = <1800000 2800000 1200000 0>; + qcom,cam-vreg-max-voltage = <1800000 2800000 1200000 0>; + qcom,cam-vreg-op-mode = <0 80000 105000 0>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 36 0>, + <&tlmm 42 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_gcc GCC_CAMSS_MCLK2_CLK_SRC>, + <&clock_gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + +}; diff --git a/arch/arm/boot/dts/qcom/trinket-camera.dtsi b/arch/arm/boot/dts/qcom/trinket-camera.dtsi new file mode 100644 index 000000000000..730381a1b4f3 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-camera.dtsi @@ -0,0 +1,803 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,msm-cam@5c00000 { + compatible = "qcom,msm-cam"; + reg = <0x5c00000 0x4000>; + reg-names = "msm-cam"; + status = "ok"; + bus-vectors = "suspend", "svs", "nominal", "turbo"; + qcom,bus-votes = <0 150000000 320000000 320000000>; + qcom,gpu-limit = <700000000>; + }; + + qcom,csiphy@1628000 { + cell-index = <0>; + compatible = "qcom,csiphy-v3.5", "qcom,csiphy"; + reg = <0x1628000 0x1000>, + <0x5C00120 0x4>; + reg-names = "csiphy", "csiphy_clk_mux"; + interrupts = <0 72 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&camss_top_gdsc>; + qcom,cam-vreg-name = "gdscr"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI0_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI0_CLK>, + <&clock_gcc GCC_CAMSS_CPHY_CSID0_CLK>, + <&clock_gcc GCC_CAMSS_CSI0PHYTIMER_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, + <&clock_gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSIPHY_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSIPHY0_CLK>, + <&clock_gcc GCC_AHB2PHY_CSI_CLK>; + clock-names = "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk", + "csiphy_ahb2crif"; + qcom,clock-rates = <0 0 311000000 0 0 200000000 0 + 0 200000000 0 0>; + status = "ok"; + }; + + qcom,csiphy@1629000 { + cell-index = <1>; + compatible = "qcom,csiphy-v3.5", "qcom,csiphy"; + reg = <0x1629000 0x1000>, + <0x5c00124 0x4>; + reg-names = "csiphy", "csiphy_clk_mux"; + interrupts = <0 73 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&camss_top_gdsc>; + qcom,cam-vreg-name = "gdscr"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI1_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI1_CLK>, + <&clock_gcc GCC_CAMSS_CPHY_CSID1_CLK>, + <&clock_gcc GCC_CAMSS_CSI1PHYTIMER_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, + <&clock_gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSIPHY_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSIPHY1_CLK>, + <&clock_gcc GCC_AHB2PHY_CSI_CLK>; + clock-names = "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk", + "csiphy_ahb2crif"; + qcom,clock-rates = <0 0 311000000 0 0 200000000 0 + 0 200000000 0 0>; + status = "ok"; + }; + + qcom,csiphy@162a000 { + cell-index = <2>; + compatible = "qcom,csiphy-v3.5", "qcom,csiphy"; + reg = <0x162a000 0x1000>, + <0x5c00128 0x4>; + reg-names = "csiphy", "csiphy_clk_mux"; + interrupts = <0 74 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&camss_top_gdsc>; + qcom,cam-vreg-name = "gdscr"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI2_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI2_CLK>, + <&clock_gcc GCC_CAMSS_CPHY_CSID2_CLK>, + <&clock_gcc GCC_CAMSS_CSI2PHYTIMER_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI2PHYTIMER_CLK>, + <&clock_gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSIPHY_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSIPHY2_CLK>, + <&clock_gcc GCC_AHB2PHY_CSI_CLK>; + clock-names = "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk", + "csiphy_ahb2crif"; + qcom,clock-rates = <0 0 311000000 0 0 200000000 0 + 0 200000000 0 0>; + status = "ok"; + }; + + qcom,csid@5c30000 { + cell-index = <0>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0x5c30000 0x400>; + reg-names = "csid"; + interrupts = <0 208 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1232000>; + qcom,mipi-csi-vdd-supply = <&L18A>; + gdscr-supply = <&camss_top_gdsc>; + vdd_sec-supply = <&L18A>; + qcom,cam-vreg-name = "vdd_sec", "gdscr"; + qcom,cam-vreg-min-voltage = <1232000 0>; + qcom,cam-vreg-max-voltage = <1232000 0>; + qcom,cam-vreg-op-mode = <0 0>; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI0_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSIPHY_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI0_CLK>, + <&clock_gcc GCC_CAMSS_CSI0_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI0RDI_CLK>, + <&clock_gcc GCC_CAMSS_CSI0PIX_CLK>, + <&clock_gcc GCC_CAMSS_CPHY_CSID0_CLK>; + clock-names = "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 311000000 200000000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,csid@5c30400 { + cell-index = <1>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0x5c30400 0x400>; + reg-names = "csid"; + interrupts = <0 209 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1232000>; + qcom,mipi-csi-vdd-supply = <&L18A>; + gdscr-supply = <&camss_top_gdsc>; + vdd_sec-supply = <&L18A>; + qcom,cam-vreg-name = "vdd_sec", "gdscr"; + qcom,cam-vreg-min-voltage = <1232000 0>; + qcom,cam-vreg-max-voltage = <1232000 0>; + qcom,cam-vreg-op-mode = <0 0>; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI1_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSIPHY_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI1_CLK>, + <&clock_gcc GCC_CAMSS_CSI1_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI1RDI_CLK>, + <&clock_gcc GCC_CAMSS_CSI1PIX_CLK>, + <&clock_gcc GCC_CAMSS_CPHY_CSID1_CLK>; + clock-names = "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 311000000 200000000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,csid@5c30800 { + cell-index = <2>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0x5c30800 0x400>; + reg-names = "csid"; + interrupts = <0 210 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1232000>; + qcom,mipi-csi-vdd-supply = <&L18A>; + gdscr-supply = <&camss_top_gdsc>; + vdd_sec-supply = <&L18A>; + qcom,cam-vreg-name = "vdd_sec", "gdscr"; + qcom,cam-vreg-min-voltage = <1232000 0>; + qcom,cam-vreg-max-voltage = <1232000 0>; + qcom,cam-vreg-op-mode = <0 0>; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI2_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSIPHY_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI2_CLK>, + <&clock_gcc GCC_CAMSS_CSI2_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI2RDI_CLK>, + <&clock_gcc GCC_CAMSS_CSI2PIX_CLK>, + <&clock_gcc GCC_CAMSS_CPHY_CSID2_CLK>; + clock-names = "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 311000000 200000000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,csid@5c30c00 { + cell-index = <3>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0x5c30c00 0x400>; + reg-names = "csid"; + interrupts = <0 211 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1232000>; + qcom,mipi-csi-vdd-supply = <&L18A>; + gdscr-supply = <&camss_top_gdsc>; + vdd_sec-supply = <&L18A>; + qcom,cam-vreg-name = "vdd_sec", "gdscr"; + qcom,cam-vreg-min-voltage = <1232000 0>; + qcom,cam-vreg-max-voltage = <1232000 0>; + qcom,cam-vreg-op-mode = <0 0>; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI3_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSIPHY_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI3_CLK>, + <&clock_gcc GCC_CAMSS_CSI3_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI3RDI_CLK>, + <&clock_gcc GCC_CAMSS_CSI3PIX_CLK>, + <&clock_gcc GCC_CAMSS_CPHY_CSID3_CLK>; + clock-names = "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 311000000 200000000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu"; + status = "ok"; + qcom,camera-secure-sid; + + msm_cam_smmu_cb1 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x420 0x0000>, + <&apps_smmu 0x421 0x0002>; + label = "vfe"; + qcom,scratch-buf-support; + }; + + msm_cam_smmu_cb2 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x800 0x0000>; + label = "cpp"; + }; + + msm_cam_smmu_cb4 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x820 0x0000>; + label = "jpeg_enc0"; + }; + msm_cam_smmu_cb5 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x821 0x0000>; + label = "jpeg_dma"; + }; + + }; + + qcom,cpp@5c04000 { + cell-index = <0>; + compatible = "qcom,cpp"; + reg = <0x5c04000 0x100>, + <0x5c80000 0x3000>, + <0x5c18000 0x3000>, + <0x014560bc 0x4>; + reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp"; + interrupts = <0 206 0>; + interrupt-names = "cpp"; + camss-vdd-supply = <&camss_top_gdsc>; + vdd-supply = <&camss_cpp_gdsc>; + qcom,vdd-names = "camss-vdd", "vdd"; + clocks =<&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CPP_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CPP_CLK>, + <&clock_gcc GCC_CAMSS_CPP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CPP_AXI_CLK>, + <&clock_gcc GCC_CAMSS_MICRO_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CPP_VBIF_AHB_CLK>, + <&clock_gcc GCC_CAMSS_THROTTLE_NRT_AXI_CLK>; + clock-names = "camss_ahb_clk", "camss_top_ahb_clk", + "cpp_src_clk", + "cpp_core_clk", "camss_cpp_ahb_clk", + "camss_cpp_axi_clk", "micro_iface_clk", + "cpp_vbif_ahb_clk", "mmss_throttle_camss_nrt_axi_clk"; + qcom,clock-rates = <0 0 240000000 240000000 0 0 0 0 0>; + qcom,min-clock-rate = <240000000>; + qcom,bus-master = <1>; + qcom,vbif-qos-setting = <0x550 0x33333333>, + <0x554 0x00333333>, + <0x558 0x33333333>, + <0x55c 0x00333333>, + <0x560 0x33333333>, + <0x564 0x00333333>, + <0x568 0x33333333>, + <0x56c 0x00333333>, + <0x570 0x33333333>, + <0x574 0x00333333>, + <0x578 0x33333333>, + <0x57c 0x00333333>, + <0x580 0x33333333>, + <0x584 0x00333333>, + <0x588 0x33333333>, + <0x58c 0x00333333>; + status = "ok"; + qcom,msm-bus,name = "msm_camera_cpp"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <106 512 0 0>, + <106 512 0 0>; + qcom,msm-bus-vector-dyn-vote; + qcom,cpp-cx-ipeak = <&cx_ipeak_lm 7>; + resets = <&clock_gcc GCC_CAMSS_MICRO_BCR>; + reset-names = "micro_iface_reset"; + qcom,src-clock-rates = <120000000 240000000 320000000 + 480000000 576000000>; + qcom,micro-reset; + qcom,cpp-fw-payload-info { + qcom,stripe-base = <790>; + qcom,plane-base = <715>; + qcom,stripe-size = <63>; + qcom,plane-size = <25>; + qcom,fe-ptr-off = <11>; + qcom,we-ptr-off = <23>; + qcom,ref-fe-ptr-off = <17>; + qcom,ref-we-ptr-off = <36>; + qcom,we-meta-ptr-off = <42>; + qcom,fe-mmu-pf-ptr-off = <7>; + qcom,ref-fe-mmu-pf-ptr-off = <10>; + qcom,we-mmu-pf-ptr-off = <13>; + qcom,dup-we-mmu-pf-ptr-off = <18>; + qcom,ref-we-mmu-pf-ptr-off = <23>; + qcom,set-group-buffer-len = <135>; + qcom,dup-frame-indicator-off = <70>; + }; + }; + + qcom,ispif@5c31000 { + cell-index = <0>; + compatible = "qcom,ispif-v3.0", "qcom,ispif"; + reg = <0x5c31000 0xc00>, + <0x5c00020 0x4>; + reg-names = "ispif", "csi_clk_mux"; + interrupts = <0 212 0>; + interrupt-names = "ispif"; + qcom,num-isps = <0x2>; + camss-vdd-supply = <&camss_top_gdsc>; + vfe0-vdd-supply = <&camss_vfe0_gdsc>; + vfe1-vdd-supply = <&camss_vfe1_gdsc>; + qcom,vdd-names = "camss-vdd", "vfe0-vdd", + "vfe1-vdd"; + qcom,clock-cntl-support; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CSI0_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI1_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI2_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI3_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CSI0RDI_CLK>, + <&clock_gcc GCC_CAMSS_CSI1RDI_CLK>, + <&clock_gcc GCC_CAMSS_CSI2RDI_CLK>, + <&clock_gcc GCC_CAMSS_CSI3RDI_CLK>, + <&clock_gcc GCC_CAMSS_CSI0PIX_CLK>, + <&clock_gcc GCC_CAMSS_CSI1PIX_CLK>, + <&clock_gcc GCC_CAMSS_CSI2PIX_CLK>, + <&clock_gcc GCC_CAMSS_CSI3PIX_CLK>, + <&clock_gcc GCC_CAMSS_CSI0_CLK>, + <&clock_gcc GCC_CAMSS_CSI1_CLK>, + <&clock_gcc GCC_CAMSS_CSI2_CLK>, + <&clock_gcc GCC_CAMSS_CSI3_CLK>, + <&clock_gcc GCC_CAMSS_VFE0_CLK_SRC>, + <&clock_gcc GCC_CAMSS_VFE0_CLK>, + <&clock_gcc GCC_CAMSS_CSI_VFE0_CLK>, + <&clock_gcc GCC_CAMSS_VFE1_CLK_SRC>, + <&clock_gcc GCC_CAMSS_VFE1_CLK>, + <&clock_gcc GCC_CAMSS_CSI_VFE1_CLK>; + clock-names = "camss_ahb_clk", + "camss_top_ahb_clk", "ispif_ahb_clk", + "csi0_src_clk", "csi1_src_clk", + "csi2_src_clk", "csi3_src_clk", + "csi0_rdi_clk", "csi1_rdi_clk", + "csi2_rdi_clk", "csi3_rdi_clk", + "csi0_pix_clk", "csi1_pix_clk", + "csi2_pix_clk", "csi3_pix_clk", + "camss_csi0_clk", "camss_csi1_clk", + "camss_csi2_clk", "camss_csi3_clk", + "vfe0_clk_src", + "camss_vfe_vfe0_clk", + "camss_csi_vfe0_clk", + "vfe1_clk_src", + "camss_vfe_vfe1_clk", + "camss_csi_vfe1_clk"; + qcom,clock-rates = <0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 + 0 0 0>; + qcom,clock-control = "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", + "INIT_RATE", "INIT_RATE", + "INIT_RATE", "INIT_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "INIT_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "INIT_RATE", + "NO_SET_RATE", "NO_SET_RATE"; + status = "ok"; + }; + + vfe0: qcom,vfe0@5c10000 { + cell-index = <0>; + compatible = "qcom,vfe48"; + reg = <0x5c10000 0x4000>, + <0x5c40000 0x3000>, + <0x5C00000 0x40000>; + reg-names = "vfe", "vfe_vbif", "msm-cam"; + interrupts = <0 214 0>, + <0 258 0>; + interrupt-names = "vfe", "dual-vfe-irq"; + camss-vdd-supply = <&camss_top_gdsc>; + vdd-supply = <&camss_vfe0_gdsc>; + qcom,vdd-names = "camss-vdd", "vdd"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_VFE0_CLK_SRC>, + <&clock_gcc GCC_CAMSS_VFE0_CLK>, + <&clock_gcc GCC_CAMSS_VFE0_STREAM_CLK>, + <&clock_gcc GCC_CAMSS_VFE0_AHB_CLK>, + <&clock_gcc GCC_CAMSS_VFE_VBIF_AHB_CLK>, + <&clock_gcc GCC_CAMSS_VFE_VBIF_AXI_CLK>, + <&clock_gcc GCC_CAMSS_THROTTLE_RT_AXI_CLK>, + <&clock_gcc GCC_CAMSS_CSI_VFE0_CLK>; + clock-names = "camss_ahb_clk", + "camss_top_ahb_clk", "vfe_clk_src", + "camss_vfe_clk", "camss_vfe_stream_clk", + "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", + "camss_vfe_vbif_axi_clk", "mmss_throttle_camss_axi_clk", + "camss_csi_vfe_clk"; + qcom,clock-rates = <0 0 403200000 0 0 0 0 0 0 0 + 0 0 480000000 0 0 0 0 0 0 0 + 0 0 576000000 0 0 0 0 0 0 0>; + status = "ok"; + qos-entries = <8>; + qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 + 0x41c 0x420>; + qos-settings = <0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8>; + vbif-entries = <3>; + vbif-regs = <0x124 0xac 0xd0>; + vbif-settings = <0x3 0x40 0x1010>; + ds-entries = <17>; + ds-regs = <0x424 0x428 0x42c 0x430 0x434 + 0x438 0x43c 0x440 0x444 0x448 0x44c + 0x450 0x454 0x458 0x45c 0x460 0x464>; + ds-settings = <0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0x110>; + qcom,msm-bus,name = "msm_camera_vfe"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <29 512 0 0>, + <29 512 100000000 100000000>; + qcom,msm-bus-vector-dyn-vote; + qcom,vfe-cx-ipeak = <&cx_ipeak_lm 7>; + }; + + vfe1: qcom,vfe1@5c14000 { + cell-index = <1>; + compatible = "qcom,vfe48"; + reg = <0x5c14000 0x4000>, + <0x5c40000 0x3000>, + <0x5C00000 0x40000>; + reg-names = "vfe", "vfe_vbif", "msm-cam"; + interrupts = <0 215 0>, + <0 258 0>; + interrupt-names = "vfe", "dual-vfe-irq"; + camss-vdd-supply = <&camss_top_gdsc>; + vdd-supply = <&camss_vfe1_gdsc>; + qcom,vdd-names = "camss-vdd", "vdd"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_VFE1_CLK_SRC>, + <&clock_gcc GCC_CAMSS_VFE1_CLK>, + <&clock_gcc GCC_CAMSS_VFE1_STREAM_CLK>, + <&clock_gcc GCC_CAMSS_VFE1_AHB_CLK>, + <&clock_gcc GCC_CAMSS_VFE_VBIF_AHB_CLK>, + <&clock_gcc GCC_CAMSS_VFE_VBIF_AXI_CLK>, + <&clock_gcc GCC_CAMSS_THROTTLE_RT_AXI_CLK>, + <&clock_gcc GCC_CAMSS_CSI_VFE1_CLK>; + clock-names = "camss_ahb_clk", + "camss_top_ahb_clk", "vfe_clk_src", + "camss_vfe_clk", "camss_vfe_stream_clk", + "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", + "camss_vfe_vbif_axi_clk", "mmss_throttle_camss_axi_clk", + "camss_csi_vfe_clk"; + qcom,clock-rates = <0 0 403200000 0 0 0 0 0 0 0 + 0 0 480000000 0 0 0 0 0 0 0 + 0 0 576000000 0 0 0 0 0 0 0>; + status = "ok"; + qos-entries = <8>; + qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 + 0x41c 0x420>; + qos-settings = <0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8 + 0xFFF8FFF8>; + vbif-entries = <3>; + vbif-regs = <0x124 0xac 0xd0>; + vbif-settings = <0x3 0x40 0x1010>; + ds-entries = <17>; + ds-regs = <0x424 0x428 0x42c 0x430 0x434 + 0x438 0x43c 0x440 0x444 0x448 0x44c + 0x450 0x454 0x458 0x45c 0x460 0x464>; + ds-settings = <0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0xcccc0011 + 0x110>; + qcom,msm-bus,name = "msm_camera_vfe"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <29 512 0 0>, + <29 512 100000000 100000000>; + qcom,msm-bus-vector-dyn-vote; + qcom,vfe-cx-ipeak = <&cx_ipeak_lm 7>; + }; + + qcom,vfe { + compatible = "qcom,vfe"; + num_child = <2>; + }; + + cci: qcom,cci@5c0c000 { + cell-index = <0>; + compatible = "qcom,cci"; + reg = <0x5c0c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "cci"; + interrupts = <0 207 0>; + interrupt-names = "cci"; + status = "ok"; + gdscr-supply = <&camss_top_gdsc>; + qcom,cam-vreg-name = "gdscr"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CCI_CLK_SRC>, + <&clock_gcc GCC_CAMSS_CCI_AHB_CLK>, + <&clock_gcc GCC_CAMSS_CCI_CLK>; + clock-names = "camss_ahb_clk", "camss_top_ahb_clk", + "cci_src_clk", "cci_ahb_clk", "camss_cci_clk"; + qcom,clock-rates = <0 0 19200000 0 0>, + <0 0 37500000 0 0>; + pinctrl-names = "cci_default", "cci_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 37 0>, + <&tlmm 38 0>, + <&tlmm 39 0>, + <&tlmm 40 0>; + qcom,gpio-tbl-num = <0 1 2 3>; + qcom,gpio-tbl-flags = <1 1 1 1>; + qcom,gpio-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + i2c_freq_100Khz: qcom,i2c_standard_mode { + status = "disabled"; + }; + i2c_freq_400Khz: qcom,i2c_fast_mode { + status = "disabled"; + }; + i2c_freq_custom: qcom,i2c_custom_mode { + status = "disabled"; + }; + i2c_freq_1Mhz: qcom,i2c_fast_plus_mode { + status = "disabled"; + }; + }; + + qcom,jpeg@5c1c000 { + cell-index = <0>; + compatible = "qcom,jpeg"; + reg = <0x05c1c000 0x4000>, + <0x5c60000 0x3000>; + reg-names = "jpeg_hw", "jpeg_vbif"; + interrupts = <0 216 0>; + interrupt-names = "jpeg"; + camss-vdd-supply = <&camss_top_gdsc>; + qcom,vdd-names = "camss-vdd"; + clock-names = "mmss_camss_ahb_clk", + "mmss_camss_top_ahb_clk", + "core_src_clk", + "core_clk", + "mmss_camss_jpeg_ahb_clk", + "mmss_camss_jpeg_axi_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_JPEG_CLK_SRC>, + <&clock_gcc GCC_CAMSS_JPEG_CLK>, + <&clock_gcc GCC_CAMSS_JPEG_AHB_CLK>, + <&clock_gcc GCC_CAMSS_JPEG_AXI_CLK>; + qcom,clock-rates = <0 0 480000000 0 0 0>; + qcom,vbif-reg-settings = <0x4 0x1>; + qcom,vbif-qos-setting = <0x550 0x00001111>, + <0x558 0x00001111>, + <0x560 0x00001111>, + <0x568 0x00001111>, + <0x570 0x00001111>, + <0x578 0x00001111>, + <0x580 0x00001111>, + <0x588 0x00001111>; + qcom,prefetch-reg-settings = <0x30c 0x1111>, + <0x318 0x31>, + <0x324 0x31>, + <0x330 0x31>, + <0x33c 0x0>; + qcom,msm-bus,name = "msm_camera_jpeg0"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <62 512 0 0>, + <62 512 1200000 1200000>; + status = "ok"; + }; + + qcom,jpeg@5ca0000 { + cell-index = <3>; + compatible = "qcom,jpegdma"; + reg = <0x5ca0000 0x4000>, + <0x5c60000 0x3000>; + reg-names = "jpeg_hw", "jpeg_vbif"; + interrupts = <0 217 0>; + interrupt-names = "jpeg"; + camss-vdd-supply = <&camss_top_gdsc>; + qcom,vdd-names = "camss-vdd"; + clock-names = "mmss_camss_ahb_clk", + "mmss_camss_top_ahb_clk", + "core_clk_src", + "core_clk", + "mmss_camss_jpeg_ahb_clk", + "mmss_camss_jpeg_axi_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMSS_TOP_AHB_CLK>, + <&clock_gcc GCC_CAMSS_JPEG_CLK_SRC>, + <&clock_gcc GCC_CAMSS_JPEG_CLK>, + <&clock_gcc GCC_CAMSS_JPEG_AHB_CLK>, + <&clock_gcc GCC_CAMSS_JPEG_AXI_CLK>; + qcom,clock-rates = <0 0 480000000 0 0 0>; + qcom,vbif-reg-settings = <0x4 0x1>; + qcom,vbif-qos-setting = <0x550 0x00001111>, + <0x558 0x00001111>, + <0x560 0x00001111>, + <0x568 0x00001111>, + <0x570 0x00001111>, + <0x578 0x00001111>, + <0x580 0x00001111>, + <0x588 0x00001111>; + qcom,prefetch-reg-settings = <0x18c 0x11>, + <0x1a0 0x31>, + <0x1b0 0x31>; + qcom,msm-bus,name = "msm_camera_jpeg_dma"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <62 512 0 0>, + <62 512 1200000 1200000>; + qcom,max-ds-factor = <128>; + status = "ok"; + }; +}; + +&i2c_freq_100Khz { + qcom,hw-thigh = <201>; + qcom,hw-tlow = <174>; + qcom,hw-tsu-sto = <204>; + qcom,hw-tsu-sta = <231>; + qcom,hw-thd-dat = <22>; + qcom,hw-thd-sta = <162>; + qcom,hw-tbuf = <227>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; + +&i2c_freq_400Khz { + qcom,hw-thigh = <38>; + qcom,hw-tlow = <56>; + qcom,hw-tsu-sto = <40>; + qcom,hw-tsu-sta = <40>; + qcom,hw-thd-dat = <22>; + qcom,hw-thd-sta = <35>; + qcom,hw-tbuf = <62>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; + +&i2c_freq_custom { + qcom,hw-thigh = <38>; + qcom,hw-tlow = <56>; + qcom,hw-tsu-sto = <40>; + qcom,hw-tsu-sta = <40>; + qcom,hw-thd-dat = <22>; + qcom,hw-thd-sta = <35>; + qcom,hw-tbuf = <62>; + qcom,hw-scl-stretch-en = <1>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; + +&i2c_freq_1Mhz { + qcom,hw-thigh = <16>; + qcom,hw-tlow = <22>; + qcom,hw-tsu-sto = <17>; + qcom,hw-tsu-sta = <18>; + qcom,hw-thd-dat = <16>; + qcom,hw-thd-sta = <15>; + qcom,hw-tbuf = <24>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <3>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-coresight.dtsi b/arch/arm/boot/dts/qcom/trinket-coresight.dtsi new file mode 100644 index 000000000000..e991d4159b1a --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-coresight.dtsi @@ -0,0 +1,2316 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + csr: csr@8001000 { + compatible = "qcom,coresight-csr"; + reg = <0x8001000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-csr"; + qcom,usb-bam-support; + qcom,hwctrl-set-support; + qcom,set-byte-cntr-support; + + qcom,blk-size = <1>; + }; + + replicator_qdss: replicator@8046000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b909>; + + reg = <0x8046000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator-qdss"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator0_out_tmc_etr: endpoint { + remote-endpoint= + <&tmc_etr_in_replicator0>; + }; + }; + + port@2 { + reg = <0>; + replicator0_in_tmc_etf: endpoint { + slave-mode; + remote-endpoint= + <&tmc_etf_out_replicator0>; + }; + }; + }; + }; + + tmc_etr: tmc@8048000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + reg = <0x8048000 0x1000>, + <0x8064000 0x15000>; + reg-names = "tmc-base", "bam-base"; + + qcom,smmu-s1-bypass; + iommus = <&apps_smmu 0x0c0 0>, + <&apps_smmu 0x0a0 0>; + + arm,buffer-size = <0x400000>; + + coresight-name = "coresight-tmc-etr"; + coresight-ctis = <&cti0>; + coresight-csr = <&csr>; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + interrupts = ; + interrupt-names = "byte-cntr-irq"; + + port { + tmc_etr_in_replicator0: endpoint { + slave-mode; + remote-endpoint = <&replicator0_out_tmc_etr>; + }; + }; + }; + + tmc_etf: tmc@8047000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + + reg = <0x8047000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etf"; + coresight-ctis = <&cti0>; + coresight-csr = <&csr>; + arm,default-sink; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tmc_etf_out_replicator0: endpoint { + remote-endpoint = + <&replicator0_in_tmc_etf>; + }; + }; + + port@1 { + reg = <0>; + tmc_etf_in_funnel_merg: endpoint { + slave-mode; + remote-endpoint = + <&funnel_merg_out_tmc_etf>; + }; + }; + }; + + }; + + funnel_merg: funnel@8045000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x8045000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-merg"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_merg_out_tmc_etf: endpoint { + remote-endpoint = + <&tmc_etf_in_funnel_merg>; + }; + }; + + port@1 { + reg = <0>; + funnel_merg_in_funnel_in0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in0_out_funnel_merg>; + }; + }; + + port@2 { + reg = <1>; + funnel_merg_in_funnel_in1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in1_out_funnel_merg>; + }; + }; + + port@3 { + reg = <2>; + funnel_merg_in_funnel_in2: endpoint { + slave-mode; + remote-endpoint = + <&funnel_in2_out_funnel_merg>; + }; + }; + }; + }; + + funnel_in0: funnel@8041000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x8041000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in0"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in0_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in0>; + }; + }; + + port@1 { + reg = <6>; + funnel_in0_in_funnel_qatb: endpoint { + slave-mode; + remote-endpoint = + <&funnel_qatb_out_funnel_in0>; + }; + }; + + port@2 { + reg = <7>; + funnel_in0_in_stm: endpoint { + slave-mode; + remote-endpoint = <&stm_out_funnel_in0>; + }; + }; + }; + }; + + funnel_in1: funnel@8042000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x8042000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in1"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in1_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in1>; + }; + }; + + port@1 { + reg = <7>; + funnel_in1_in_tpda_mapss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_mapss_out_funnel_in1>; + }; + }; + }; + }; + + stm: stm@8002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b962>; + + reg = <0x8002000 0x1000>, + <0xe280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + coresight-name = "coresight-stm"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + stm_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_stm>; + }; + }; + + }; + + funnel_in2: funnel@8043000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x8043000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in2"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in2_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in2>; + }; + }; + + port@1 { + reg = <2>; + funnel_in2_in_tpdm_wcss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_wcss_out_funnel_in2>; + }; + }; + + port@2 { + reg = <5>; + funnel_in2_in_funnel_apss1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_apss1_out_funnel_in2>; + }; + }; + }; + }; + + tpdm_wcss: tpdm@899c000 { + compatible = "qcom,coresight-dummy"; + + coresight-name = "coresight-tpdm-wcss"; + qcom,dummy-source; + + port { + tpdm_wcss_out_funnel_in2: endpoint { + remote-endpoint = <&funnel_in2_in_tpdm_wcss>; + }; + }; + }; + + funnel_apss1: funnel@9810000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x9810000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss_1"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss1_out_funnel_in2: endpoint { + remote-endpoint = + <&funnel_in2_in_funnel_apss1>; + }; + }; + + port@1 { + reg = <0>; + funnel_apss1_in_funnel_apss0: endpoint { + slave-mode; + remote-endpoint = + <&funnel_apss0_out_funnel_apss1>; + }; + }; + + port@2 { + reg = <2>; + funnel_apss1_in_tpda_actpm: endpoint { + slave-mode; + remote-endpoint = + <&tpda_actpm_out_funnel_apss1>; + }; + }; + + port@3 { + reg = <3>; + funnel_apss1_in_tpda_llm_silver: endpoint { + slave-mode; + remote-endpoint = + <&tpda_llm_silver_out_funnel_apss1>; + }; + }; + + port@4 { + reg = <4>; + funnel_apss1_in_tpda_apss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_apss_out_funnel_apss1>; + }; + }; + }; + }; + + tpda_mapss: tpda@8a04000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x8a04000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-mapss"; + + qcom,tpda-atid = <76>; + qcom,dsb-elem-size = <0 32>; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_mapss_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_tpda_mapss>; + }; + }; + + port@1 { + reg = <0>; + tpda_mapss_in_tpdm_mapss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_mapss_out_tpda_mapss>; + }; + }; + }; + }; + + tpdm_mapss: tpdm@8a01000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x8a01000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-mapss"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_mapss_out_tpda_mapss: endpoint { + remote-endpoint = <&tpda_mapss_in_tpdm_mapss>; + }; + }; + }; + + tpda_apss: tpda@9862000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x9862000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-apss"; + + qcom,tpda-atid = <66>; + qcom,dsb-elem-size = <0 32>; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_apss_out_funnel_apss1: endpoint { + remote-endpoint = + <&funnel_apss1_in_tpda_apss>; + }; + }; + + port@1 { + reg = <0>; + tpda_apss_in_tpdm_apss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_apss_out_tpda_apss>; + }; + }; + }; + }; + + tpdm_apss: tpdm@9860000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x9860000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-apss"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_apss_out_tpda_apss: endpoint { + remote-endpoint = <&tpda_apss_in_tpdm_apss>; + }; + }; + }; + + tpda_actpm: tpda@9832000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x9832000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-actpm"; + + qcom,tpda-atid = <77>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_actpm_out_funnel_apss1: endpoint { + remote-endpoint = + <&funnel_apss1_in_tpda_actpm>; + }; + }; + + port@1 { + reg = <0>; + tpda_actpm_in_tpdm_actpm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_actpm_out_tpda_actpm>; + }; + }; + }; + }; + + tpdm_actpm: tpdm@9830000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x9830000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-actpm"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_actpm_out_tpda_actpm: endpoint { + remote-endpoint = + <&tpda_actpm_in_tpdm_actpm>; + }; + }; + }; + + tpda_llm_silver: tpda@98c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x98c0000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-llm-silver"; + + qcom,tpda-atid = <72>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_llm_silver_out_funnel_apss1: endpoint { + remote-endpoint = + <&funnel_apss1_in_tpda_llm_silver>; + }; + }; + + port@1 { + reg = <0>; + tpda_llm_silver_in_tpdm_llm_silver: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_llm_silver_out_tpda_llm_silver>; + }; + }; + }; + }; + + tpdm_llm_silver: tpdm@98a0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x98a0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-llm-silver"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_llm_silver_out_tpda_llm_silver: endpoint { + remote-endpoint = + <&tpda_llm_silver_in_tpdm_llm_silver>; + }; + }; + }; + + funnel_apss0: funnel@9800000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x9800000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss_0"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss0_out_funnel_apss1: endpoint { + remote-endpoint = + <&funnel_apss1_in_funnel_apss0>; + }; + }; + + port@1 { + reg = <0>; + funnel_apss0_in_etm0: endpoint { + slave-mode; + remote-endpoint = + <&etm0_out_funnel_apss0>; + }; + }; + + port@2 { + reg = <1>; + funnel_apss0_in_etm1: endpoint { + slave-mode; + remote-endpoint = + <&etm1_out_funnel_apss0>; + }; + }; + + port@3 { + reg = <2>; + funnel_apss0_in_etm2: endpoint { + slave-mode; + remote-endpoint = + <&etm2_out_funnel_apss0>; + }; + }; + + port@4 { + reg = <3>; + funnel_apss0_in_etm3: endpoint { + slave-mode; + remote-endpoint = + <&etm3_out_funnel_apss0>; + }; + }; + + port@5 { + reg = <4>; + funnel_apss0_in_etm4: endpoint { + slave-mode; + remote-endpoint = + <&etm4_out_funnel_apss0>; + }; + }; + + port@6 { + reg = <5>; + funnel_apss0_in_etm5: endpoint { + slave-mode; + remote-endpoint = + <&etm5_out_funnel_apss0>; + }; + }; + + port@7 { + reg = <6>; + funnel_apss0_in_etm6: endpoint { + slave-mode; + remote-endpoint = + <&etm6_out_funnel_apss0>; + }; + }; + + port@8 { + reg = <7>; + funnel_apss0_in_etm7: endpoint { + slave-mode; + remote-endpoint = + <&etm7_out_funnel_apss0>; + }; + }; + + }; + }; + + etm0: etm@9040000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x9040000 0x1000>; + cpu = <&CPU0>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm0"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm0_out_funnel_apss0: endpoint { + remote-endpoint = <&funnel_apss0_in_etm0>; + }; + }; + }; + + etm1: etm@9140000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x9140000 0x1000>; + cpu = <&CPU1>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm1"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm1_out_funnel_apss0: endpoint { + remote-endpoint = <&funnel_apss0_in_etm1>; + }; + }; + }; + + etm2: etm@9240000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x9240000 0x1000>; + cpu = <&CPU2>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm2"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm2_out_funnel_apss0: endpoint { + remote-endpoint = <&funnel_apss0_in_etm2>; + }; + }; + }; + + etm3: etm@9340000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x9340000 0x1000>; + cpu = <&CPU3>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm3"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm3_out_funnel_apss0: endpoint { + remote-endpoint = <&funnel_apss0_in_etm3>; + }; + }; + }; + + etm4: etm@9440000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x9440000 0x1000>; + cpu = <&CPU4>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm4"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm4_out_funnel_apss0: endpoint { + remote-endpoint = <&funnel_apss0_in_etm4>; + }; + }; + }; + + etm5: etm@9540000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x9540000 0x1000>; + cpu = <&CPU5>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm5"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm5_out_funnel_apss0: endpoint { + remote-endpoint = <&funnel_apss0_in_etm5>; + }; + }; + }; + + etm6: etm@9640000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x9640000 0x1000>; + cpu = <&CPU6>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm6"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm6_out_funnel_apss0: endpoint { + remote-endpoint = <&funnel_apss0_in_etm6>; + }; + }; + }; + + etm7: etm@9740000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0x9740000 0x1000>; + cpu = <&CPU7>; + + qcom,tupwr-disable; + coresight-name = "coresight-etm7"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + etm7_out_funnel_apss0: endpoint { + remote-endpoint = <&funnel_apss0_in_etm7>; + }; + }; + }; + + funnel_qatb: funnel@8005000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x8005000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-qatb"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_qatb_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_qatb>; + }; + }; + + port@1 { + reg = <0>; + funnel_qatb_in_tpda: endpoint { + slave-mode; + remote-endpoint = + <&tpda_out_funnel_qatb>; + }; + }; + + port@2 { + reg = <4>; + funnel_qatb_in_funnel_monaq_1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_monaq_1_out_funnel_qatb>; + }; + }; + + port@3 { + reg = <5>; + funnel_qatb_in_funnel_lpass: endpoint { + slave-mode; + remote-endpoint = + <&funnel_lpass_out_funnel_qatb>; + }; + }; + + port@4 { + reg = <6>; + funnel_qatb_in_funnel_turing_1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_turing_1_out_funnel_qatb>; + }; + }; + }; + }; + + tpda: tpda@8004000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x8004000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda"; + + qcom,tpda-atid = <65>; + qcom,bc-elem-size = <10 32>, + <13 32>; + qcom,tc-elem-size = <13 32>; + qcom,dsb-elem-size = <0 32>, + <2 32>, + <3 32>, + <5 32>, + <6 32>, + <10 32>, + <11 32>, + <13 32>; + qcom,cmb-elem-size = <3 64>, + <7 64>, + <13 64>; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_tpda>; + }; + + }; + + port@1 { + reg = <0>; + tpda_in_tpdm_center: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_center_out_tpda>; + }; + }; + + port@2 { + reg = <1>; + tpda_in_funnel_gpu: endpoint { + slave-mode; + remote-endpoint = + <&funnel_gpu_out_tpda>; + }; + }; + + port@3 { + reg = <3>; + tpda_in_funnel_monaq: endpoint { + slave-mode; + remote-endpoint = + <&funnel_monaq_out_tpda>; + }; + }; + + port@4 { + reg = <4>; + tpda_in_funnel_lpass_1: endpoint { + slave-mode; + remote-endpoint = + <&funnel_lpass_1_out_tpda>; + }; + }; + + port@5 { + reg = <5>; + tpda_in_funnel_turing: endpoint { + slave-mode; + remote-endpoint = + <&funnel_turing_out_tpda>; + }; + }; + + port@6 { + reg = <7>; + tpda_in_tpdm_vsense: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_vsense_out_tpda>; + }; + }; + + port@7 { + reg = <8>; + tpda_in_tpdm_dcc: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dcc_out_tpda>; + }; + }; + + port@8 { + reg = <10>; + tpda_in_tpdm_prng: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_prng_out_tpda>; + }; + }; + + port@9 { + reg = <12>; + tpda_in_tpdm_qm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_qm_out_tpda>; + }; + }; + + port@10 { + reg = <13>; + tpda_in_tpdm_west: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_west_out_tpda>; + }; + }; + + port@11 { + reg = <14>; + tpda_in_tpdm_pimem: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_pimem_out_tpda>; + }; + }; + + }; + }; + + funnel_gpu: funnel@8944000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x8944000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-gpu"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>, + <&clock_gpucc GPU_CC_CX_APB_CLK>; + clock-names = "apb_pclk", "gpu_apb_clk"; + qcom,proxy-clks = "gpu_apb_clk"; + + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + regulator-names = "vddcx", "vdd"; + qcom,proxy-regs = "vddcx", "vdd"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_gpu_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_funnel_gpu>; + }; + }; + + port@1 { + reg = <0>; + funnel_gpu_in_tpdm_gpu: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_gpu_out_funnel_gpu>; + }; + }; + }; + }; + + tpdm_gpu: tpdm@8940000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x8940000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-gpu"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>, + <&clock_gpucc GPU_CC_CX_APB_CLK>; + clock-names = "apb_pclk", "gpu_apb_clk"; + + qcom,tpdm-clks = "gpu_apb_clk"; + + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + regulator-names = "vddcx", "vdd"; + qcom,tpdm-regs = "vddcx", "vdd"; + + port { + tpdm_gpu_out_funnel_gpu: endpoint { + remote-endpoint = <&funnel_gpu_in_tpdm_gpu>; + }; + }; + }; + + tpdm_vsense: tpdm@8840000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x8840000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-vsense"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port{ + tpdm_vsense_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_vsense>; + }; + }; + }; + + tpdm_west: tpdm@8a58000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x8a58000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-west"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port{ + tpdm_west_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_west>; + }; + }; + }; + + tpdm_dcc: tpdm@8870000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x8870000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dcc"; + + qcom,hw-enable-check; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port{ + tpdm_dcc_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_dcc>; + }; + }; + }; + + tpdm_prng: tpdm@884c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x884c000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-prng"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port{ + tpdm_prng_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_prng>; + }; + }; + }; + + tpdm_qm: tpdm@89d0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x89d0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-qm"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_qm_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_qm>; + }; + }; + }; + + tpdm_pimem: tpdm@8850000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x8850000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-pimem"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_pimem_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_pimem>; + }; + }; + }; + + funnel_monaq1: funnel_1@89c3000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x89c5000 0x1>, + <0x89c3000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + + coresight-name = "coresight-funnel-monaq1"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + qcom,duplicate-funnel; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_monaq_1_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_funnel_monaq_1>; + }; + }; + + port@1 { + reg = <6>; + funnel_monaq_1_in_modem_etm0: endpoint { + slave-mode; + remote-endpoint = + <&modem_etm0_out_funnel_monaq_1>; + }; + }; + + port@2 { + reg = <7>; + funnel_monaq_1_in_funnel_modem: endpoint { + slave-mode; + remote-endpoint = + <&funnel_modem_out_funnel_monaq_1>; + }; + }; + }; + }; + + tpdm_monaq: tpdm@89c0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x89c0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-monaq"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_monaq_out_funnel_monaq: endpoint { + remote-endpoint = + <&funnel_monaq_in_tpdm_monaq>; + }; + }; + }; + + funnel_modem: funnel@8832000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x8832000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-modem"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_modem_out_funnel_monaq_1: endpoint { + remote-endpoint = + <&funnel_monaq_1_in_funnel_modem>; + }; + }; + + port@1 { + reg = <0>; + funnel_modem_in_tpda_modem_0: endpoint { + slave-mode; + remote-endpoint = + <&tpda_modem_0_out_funnel_modem>; + }; + }; + + port@2 { + reg = <1>; + funnel_modem_in_tpda_modem_1: endpoint { + slave-mode; + remote-endpoint = + <&tpda_modem_1_out_funnel_modem>; + }; + }; + }; + }; + + tpda_modem0: tpda@8831000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x8831000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-modem-0"; + + qcom,tpda-atid = <67>; + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_modem_0_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_tpda_modem_0>; + }; + }; + + port@1 { + reg = <0>; + tpda_modem_0_in_tpdm_modem_0: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_modem_0_out_tpda_modem_0>; + }; + }; + }; + }; + + tpda_modem1: tpda@8833000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b969>; + reg = <0x8833000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-modem-1"; + + qcom,tpda-atid = <98>; + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_modem_1_out_funnel_modem: endpoint { + remote-endpoint = + <&funnel_modem_in_tpda_modem_1>; + }; + }; + + port@1 { + reg = <0>; + tpda_modem_1_in_tpdm_modem_1: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_modem_1_out_tpda_modem_1>; + }; + }; + }; + }; + + tpdm_modem1: tpdm@8834000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x8834000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-modem-1"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_modem_1_out_tpda_modem_1: endpoint { + remote-endpoint = + <&tpda_modem_1_in_tpdm_modem_1>; + }; + }; + }; + + tpdm_modem0: tpdm@8830000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x8830000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-modem-0"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + port { + tpdm_modem_0_out_tpda_modem_0: endpoint { + remote-endpoint = + <&tpda_modem_0_in_tpdm_modem_0>; + }; + }; + }; + + funnel_monaq: funnel@89c3000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x89c3000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-monaq"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_monaq_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_funnel_monaq>; + }; + }; + + port@1 { + reg = <0>; + funnel_monaq_in_tpdm_monaq: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_monaq_out_funnel_monaq>; + }; + }; + }; + }; + + funnel_turing: funnel@8861000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x8861000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-turing"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_turing_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_funnel_turing>; + }; + }; + + port@1 { + reg = <0>; + funnel_turing_in_tpdm_turing: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_turing_out_funnel_turing>; + }; + }; + }; + }; + + tpdm_turing: tpdm@8860000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x8860000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-turing"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_turing_out_funnel_turing: endpoint { + remote-endpoint = + <&funnel_turing_in_tpdm_turing>; + }; + }; + }; + + funnel_turing1: funnel_1@8861000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x8868010 0x10>, + <0x8861000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + + coresight-name = "coresight-funnel-turing1"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + qcom,duplicate-funnel; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_turing_1_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_funnel_turing_1>; + }; + }; + + port@1 { + reg = <1>; + funnel_turing_1_in_turing_etm0: endpoint { + slave-mode; + remote-endpoint = + <&turing_etm0_out_funnel_turing_1>; + }; + }; + }; + }; + + funnel_lpass: funnel@8981000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x8981000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-lpass"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_lpass_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_funnel_lpass>; + }; + }; + + port@1 { + reg = <1>; + funnel_lpass_in_audio_etm0: endpoint { + slave-mode; + remote-endpoint = + <&audio_etm0_out_funnel_lpass>; + }; + }; + }; + }; + + funnel_lpass_1: funnel_1@8981000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x8982000 0x1>, + <0x8981000 0x1000>; + reg-names = "funnel-base-dummy", "funnel-base-real"; + + coresight-name = "coresight-funnel-lpass-1"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,duplicate-funnel; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_lpass_1_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_funnel_lpass_1>; + }; + }; + + port@1 { + reg = <0>; + funnel_lpass_1_in_tpdm_lpass: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_lpass_out_funnel_lpass_1>; + }; + }; + }; + }; + + tpdm_center: tpdm@8b58000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x8b58000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-center"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_center_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_center>; + }; + }; + }; + + tpdm_lpass: tpdm@8980000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b968>; + reg = <0x8980000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-lpass"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + qcom,msr-fix-req; + + port { + tpdm_lpass_out_funnel_lpass_1: endpoint { + remote-endpoint = + <&funnel_lpass_1_in_tpdm_lpass>; + }; + }; + }; + + turing_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-turing-etm0"; + qcom,inst-id = <13>; + + port{ + turing_etm0_out_funnel_turing_1: endpoint { + remote-endpoint = + <&funnel_turing_1_in_turing_etm0>; + }; + }; + }; + + modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem-etm0"; + qcom,inst-id = <2>; + + port { + modem_etm0_out_funnel_monaq_1: endpoint { + remote-endpoint = + <&funnel_monaq_1_in_modem_etm0>; + }; + }; + }; + + audio_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-audio-etm0"; + qcom,inst-id = <5>; + + port { + audio_etm0_out_funnel_lpass: endpoint { + remote-endpoint = + <&funnel_lpass_in_audio_etm0>; + }; + }; + }; + + cti0: cti@8010000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x8010000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti0"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti1: cti@8011000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x8011000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti1"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti2: cti@8012000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x8012000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti2"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti3: cti@8013000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x8013000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti3"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti4: cti@8014000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x8014000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti4"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti5: cti@8015000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x8015000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti5"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti6: cti@8016000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x8016000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti6"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti7: cti@8017000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x8017000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti7"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti8: cti@8018000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x8018000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti8"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti9: cti@8019000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x8019000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti9"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti10: cti@801a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x801a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti10"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti11: cti@801b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x801b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti11"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti12: cti@801c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x801c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti12"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti13: cti@801d000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x801d000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti13"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti14: cti@801e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x801e000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti14"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti15: cti@801f000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x801f000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti15"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti_cpu0: cti@9020000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x9020000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu0"; + cpu = <&CPU0>; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + }; + + cti_cpu1: cti@9120000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x9120000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu1"; + cpu = <&CPU1>; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu2: cti@9220000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x9220000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu2"; + cpu = <&CPU2>; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu3: cti@9320000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x9320000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu3"; + cpu = <&CPU3>; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu4: cti@9420000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x9420000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu4"; + cpu = <&CPU4>; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu5: cti@9520000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x9520000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu5"; + cpu = <&CPU5>; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu6: cti@9620000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x9620000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu6"; + cpu = <&CPU6>; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cpu7: cti@9720000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x9720000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu7"; + cpu = <&CPU7>; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + hwevent: hwevent@4506604 { + compatible = "qcom,coresight-hwevent"; + reg = <0x04506604 0x4>; + + reg-names = "ddr-ch0-cfg"; + + coresight-name = "coresight-hwevent"; + coresight-csr = <&csr>; + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + apss_tgu: tgu@9900000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b999>; + reg = <0x09900000 0x1000>; + reg-names = "tgu-base"; + tgu-steps = <3>; + tgu-conditions = <4>; + tgu-regs = <8>; + tgu-timer-counters = <8>; + interrupts = <0 53 1>, <0 54 1>, <0 55 1>, <0 56 1>; + coresight-name = "coresight-tgu-apss"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_apss: cti@98e0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x98e0000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss_cti0"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_apss: cti@98f0000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x98f0000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss_cti1"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti0_dlct: cti@8b59000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x8b59000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct_cti0"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti1_dlct: cti@8b5a000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x8b5a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct_cti1"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti2_dlct: cti@8b5b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x8b5b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct_cti2"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti3_dlct: cti@8b5c000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x8b5c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlct_cti3"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_arm9: cti@8b50000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x8b50000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-arm9_cti"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_cortex_m3: cti@8b30000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x8b30000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cortex_m3"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_dlmt_cti0: cti@89c1000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x89c1000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-dlmt_cti0"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_gpu_isdb_cti: cti@8941000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x8941000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-gpu_isdb_cti"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>, + <&clock_gpucc GPU_CC_CX_APB_CLK>; + clock-names = "apb_pclk", "gpu_apb_clk"; + qcom,proxy-clks = "gpu_apb_clk"; + + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + regulator-names = "vddcx", "vdd"; + qcom,proxy-regs = "vddcx", "vdd"; + }; + + cti_lpass_q6_cti: cti@8987000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x8987000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-lpass_q6_cti"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_mapss_cti: cti@8a02000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x8a02000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-mapss_cti"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_mss_q6_cti: cti@883b000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x883b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-mss_q6_cti"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_turing_q6_cti: cti@8867000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0x8867000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-turing_q6_cti"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_wcss_cti0: cti@cadc000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0xcadc000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-wcss_cti0"; + status = "disabled"; + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_wcss_cti1: cti@cadd000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0xcadd000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-wcss_cti1"; + status = "disabled"; + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; + + cti_wcss_cti2: cti@cade000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b966>; + reg = <0xcade000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-wcss_cti2"; + status = "disabled"; + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-dp-idp-overlay.dts b/arch/arm/boot/dts/qcom/trinket-dp-idp-overlay.dts new file mode 100644 index 000000000000..930307886ea1 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-dp-idp-overlay.dts @@ -0,0 +1,51 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "trinket-idp.dtsi" +#include "trinket-audio-overlay.dtsi" + +/ { + model = "Display Port Enable IDP"; + compatible = "qcom,trinket-idp", "qcom,trinket", "qcom,idp"; + qcom,msm-id = <394 0x10000>; + qcom,board-id = <34 4>; +}; + +&dsi_td4330_truly_cmd_display { + qcom,dsi-display-active; +}; + +&sde_dp { + status = "ok"; + qcom,dp-hpd-gpio = <&tlmm 100 0>; + qcom,dp-low-power-hw-hpd; +}; + +&mdss_dp_pll { + status = "ok"; +}; + +&usb0 { + dwc3@4e00000 { + usb-phy = <&qusb_phy0>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + }; +}; + +&mdss_mdp { + connectors = <&sde_wb &sde_dsi &sde_dp>; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-dp-idp.dts b/arch/arm/boot/dts/qcom/trinket-dp-idp.dts new file mode 100644 index 000000000000..8321f5877c74 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-dp-idp.dts @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "trinket.dtsi" +#include "trinket-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. TRINKET Display Port Enable IDP"; + compatible = "qcom,trinket-idp", "qcom,trinket", "qcom,idp"; + qcom,board-id = <34 4>; +}; + +&sde_dp { + status = "ok"; + qcom,dp-hpd-gpio = <&tlmm 100 0>; + qcom,dp-low-power-hw-hpd; +}; + +&mdss_dp_pll { + status = "ok"; +}; + +&usb0 { + dwc3@4e00000 { + usb-phy = <&qusb_phy0>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + }; +}; + +&mdss_mdp { + connectors = <&sde_wb &sde_dsi &sde_dp>; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-external-codec-idp-overlay.dts b/arch/arm/boot/dts/qcom/trinket-external-codec-idp-overlay.dts new file mode 100644 index 000000000000..ce50ac46f1b9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-external-codec-idp-overlay.dts @@ -0,0 +1,31 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include + +#include "trinket-idp.dtsi" +#include "trinket-tasha-codec-audio-overlay.dtsi" +#include "trinket-tasha-codec.dtsi" + +/ { + model = "Ext Audio Codec IDP"; + compatible = "qcom,trinket-idp", "qcom,trinket", "qcom,idp"; + qcom,msm-id = <394 0x10000>; + qcom,board-id = <34 1>; +}; + +&dsi_td4330_truly_cmd_display { + qcom,dsi-display-active; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-external-codec-idp.dts b/arch/arm/boot/dts/qcom/trinket-external-codec-idp.dts new file mode 100644 index 000000000000..c18f4502ca92 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-external-codec-idp.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "trinket.dtsi" +#include "trinket-idp.dtsi" +#include "trinket-tasha-codec-audio-overlay.dtsi" +#include "trinket-tasha-codec.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Trinket Ext Audio Codec IDP"; + compatible = "qcom,trinket-idp", "qcom,trinket", "qcom,idp"; + qcom,board-id = <34 1>; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-gdsc.dtsi b/arch/arm/boot/dts/qcom/trinket-gdsc.dtsi new file mode 100644 index 000000000000..d8f935d90926 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-gdsc.dtsi @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + /* GDSCs in Global CC */ + camss_cpp_gdsc: qcom,gdsc@14560bc { + compatible = "qcom,gdsc"; + regulator-name = "cam_cpp_gdsc"; + reg = <0x14560bc 0x4>; + status = "disabled"; + }; + + camss_top_gdsc: qcom,gdsc@145607c { + compatible = "qcom,gdsc"; + regulator-name = "camss_top_gdsc"; + reg = <0x145607c 0x4>; + status = "disabled"; + }; + + camss_vfe0_gdsc: qcom,gdsc@1454004 { + compatible = "qcom,gdsc"; + regulator-name = "camss_vfe0_gdsc"; + reg = <0x1454004 0x4>; + status = "disabled"; + }; + + camss_vfe1_gdsc: qcom,gdsc@145403c { + compatible = "qcom,gdsc"; + regulator-name = "camss_vfe1_gdsc"; + reg = <0x145403c 0x4>; + status = "disabled"; + }; + + ufs_phy_gdsc: qcom,gdsc@1445004 { + compatible = "qcom,gdsc"; + regulator-name = "ufs_phy_gdsc"; + reg = <0x1445004 0x4>; + status = "disabled"; + }; + + usb30_prim_gdsc: qcom,gdsc@141a004 { + compatible = "qcom,gdsc"; + regulator-name = "usb30_prim_gdsc"; + reg = <0x141a004 0x4>; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@147d060 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc"; + reg = <0x147d060 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@1480094 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc"; + reg = <0x1480094 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc: qcom,gdsc@1480074 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc"; + reg = <0x1480074 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc: qcom,gdsc@1480084 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc"; + reg = <0x1480084 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + /* GDSCs in Display CC */ + mdss_core_gdsc: qcom,gdsc@5f03000 { + compatible = "qcom,gdsc"; + regulator-name = "mdss_core_gdsc"; + reg = <0x5f03000 0x4>; + qcom,support-hw-trigger; + status = "disabled"; + proxy-supply = <&mdss_core_gdsc>; + qcom,proxy-consumer-enable; + }; + + /* GDSCs in Graphics CC */ + gpu_cx_hw_ctrl: syscon@5991540 { + compatible = "syscon"; + reg = <0x5991540 0x4>; + }; + + gpu_cx_gdsc: qcom,gdsc@599106c { + compatible = "qcom,gdsc"; + regulator-name = "gpu_cx_gdsc"; + reg = <0x599106c 0x4>; + hw-ctrl-addr = <&gpu_cx_hw_ctrl>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + qcom,clk-dis-wait-val = <8>; + status = "disabled"; + }; + + gpu_gx_gdsc: qcom,gdsc@599100c { + compatible = "qcom,gdsc"; + regulator-name = "gpu_gx_gdsc"; + reg = <0x599100c 0x4>; + status = "disabled"; + }; + + /* GDSCs in Video CC */ + vcodec0_gdsc: qcom,gdsc@5b00874 { + compatible = "qcom,gdsc"; + regulator-name = "vcodec0_gdsc"; + reg = <0x5b00874 0x4>; + status = "disabled"; + }; + + venus_gdsc: qcom,gdsc@5b00814 { + compatible = "qcom,gdsc"; + regulator-name = "venus_gdsc"; + reg = <0x5b00814 0x4>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-gpu.dtsi b/arch/arm/boot/dts/qcom/trinket-gpu.dtsi new file mode 100644 index 000000000000..382f052e48e5 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-gpu.dtsi @@ -0,0 +1,279 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + pil_gpu: qcom,kgsl-hyp { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <13>; + qcom,firmware-name = "a610_zap"; + }; + + msm_bus: qcom,kgsl-busmon{ + label = "kgsl-busmon"; + compatible = "qcom,kgsl-busmon"; + }; + + gpu_bw_tbl: gpu-bw-tbl { + compatible = "operating-points-v2"; + opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */ + opp-100 { opp-hz = /bits/ 64 < 762 >; }; /* 1.100 MHz */ + opp-200 { opp-hz = /bits/ 64 < 1525 >; }; /* 2.200 MHz */ + opp-300 { opp-hz = /bits/ 64 < 2288 >; }; /* 3.300 MHz */ + opp-451 { opp-hz = /bits/ 64 < 3440 >; }; /* 4.451 MHz */ + opp-547 { opp-hz = /bits/ 64 < 4173 >; }; /* 5.547 MHz */ + opp-681 { opp-hz = /bits/ 64 < 5195 >; }; /* 6.681 MHz */ + opp-768 { opp-hz = /bits/ 64 < 5859 >; }; /* 7.768 MHz */ + opp-1017 { opp-hz = /bits/ 64 < 7759 >; }; /* 8.1017 MHz */ + opp-1353 { opp-hz = /bits/ 64 < 10322 >; }; /* 9.1353 MHz */ + opp-1555 { opp-hz = /bits/ 64 < 11863 >; }; /* 10.1555 MHz */ + opp-1804 { opp-hz = /bits/ 64 < 13763 >; }; /* 11.1804 MHz */ + }; + + gpubw: qcom,gpubw { + compatible = "qcom,devbw"; + governor = "bw_vbif"; + qcom,src-dst-ports = <26 512>; + operating-points-v2 = <&gpu_bw_tbl>; + }; + + msm_gpu: qcom,kgsl-3d0@5900000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; + status = "ok"; + + reg = <0x5900000 0x90000>, + <0x5961000 0x800>, + <0x1b40000 0x6fff>; + reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", + "qfprom_memory"; + + interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + + qcom,id = <0>; + qcom,chipid = <0x06010000>; + + qcom,initial-pwrlevel = <6>; + qcom,idle-timeout = <80>; + + qcom,ubwc-mode = <1>; + qcom,min-access-length = <64>; + qcom,highest-bank-bit = <14>; + + /* size in bytes */ + qcom,snapshot-size = <1048576>; + + /* base addr, size */ + qcom,gpu-qdss-stm = <0xe1c0000 0x40000>; + #cooling-cells = <2>; + + clocks = <&clock_gpucc GPU_CC_GX_GFX3D_CLK>, + <&clock_gpucc GPU_CC_CXO_CLK>, + <&clock_gcc GCC_BIMC_GPU_AXI_CLK>, + <&clock_gpucc GPU_CC_AHB_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gcc GCC_SYS_NOC_COMPUTE_SF_AXI_CLK>, + <&clock_gpucc GPU_CC_CX_GMU_CLK>, + <&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + + clock-names = "core_clk", "rbbmtimer_clk", "mem_clk", + "iface_clk", "mem_iface_clk", + "alt_mem_iface_clk", "gmu_clk", + "smmu_vote"; + + /* Bus Scale Settings */ + qcom,gpubw-dev = <&gpubw>; + qcom,bus-control; + qcom,msm-bus,name = "grp3d"; + qcom,bus-width = <32>; + qcom,msm-bus,num-cases = <12>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, + <26 512 0 800000>, /* 1 bus=100 (LOW SVS) */ + <26 512 0 1600000>, /* 2 bus=200 (LOW SVS) */ + <26 512 0 2400000>, /* 3 bus=300 (LOW SVS) */ + <26 512 0 3608000>, /* 4 bus=451 (LOW SVS) */ + <26 512 0 4376000>, /* 5 bus=547 (LOW SVS) */ + <26 512 0 5448000>, /* 6 bus=681 (SVS) */ + <26 512 0 6144000>, /* 7 bus=768 (SVS) */ + <26 512 0 8136000>, /* 8 bus=1017 (SVS_L1) */ + <26 512 0 10824000>, /* 9 bus=1353 (NOM) */ + <26 512 0 12440000>, /* 10 bus=1555 (NOM) */ + <26 512 0 14432000>; /* 11 bus=1804 (TURBO) */ + + /* GDSC regulator names */ + regulator-names = "vddcx", "vdd"; + /* GDSC oxili regulators */ + vddcx-supply = <&gpu_cx_gdsc>; + vdd-supply = <&gpu_gx_gdsc>; + + /* CPU latency parameter */ + qcom,pm-qos-active-latency = <422>; + qcom,pm-qos-wakeup-latency = <422>; + + /* Enable context aware freq. scaling */ + qcom,enable-ca-jump; + /* Context aware jump busy penalty in us */ + qcom,ca-busy-penalty = <12000>; + /* Context aware jump target power level */ + qcom,ca-target-pwrlevel = <5>; + + qcom,gpu-gaming-bin = <0x6018 0x80 7>; + + /* CX iPeak limit support */ + qcom,gpu-cx-ipeak = <&cx_ipeak_lm 5>; + + /* GPU Mempools */ + qcom,gpu-mempools { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-allocate; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-allocate; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; + + /* Power levels */ + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + /* TURBO_L1 */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <950000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <11>; + }; + + /* TURBO */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <900000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <820000000>; + qcom,bus-freq = <10>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <745000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <10>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <600000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <7>; + qcom,bus-max = <9>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <465000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <8>; + }; + + /* LOW SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <320000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + }; + + kgsl_msm_iommu: qcom,kgsl-iommu@59a0000 { + compatible = "qcom,kgsl-smmu-v2"; + + reg = <0x59a0000 0x10000>; + qcom,protect = <0xa0000 0x10000>; + + clocks = <&clock_gcc GCC_BIMC_GPU_AXI_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gcc GCC_SYS_NOC_COMPUTE_SF_AXI_CLK>, + <&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + + clock-names = "mem_clk", "mem_iface_clk", + "alt_mem_iface_clk", "smmu_vote"; + + qcom,retention; + qcom,hyp_secure_alloc; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + label = "gfx3d_user"; + iommus = <&kgsl_smmu 0 1>; + qcom,gpu-offset = <0xa8000>; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + label = "gfx3d_secure"; + iommus = <&kgsl_smmu 2 0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-idp-overlay.dts b/arch/arm/boot/dts/qcom/trinket-idp-overlay.dts new file mode 100644 index 000000000000..4fef9da0c768 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-idp-overlay.dts @@ -0,0 +1,30 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "trinket-idp.dtsi" +#include "trinket-audio-overlay.dtsi" + +/ { + model = "IDP"; + compatible = "qcom,trinket-idp", "qcom,trinket", "qcom,idp"; + qcom,msm-id = <394 0x10000>; + qcom,board-id = <34 0>; +}; + +&dsi_td4330_truly_cmd_display { + qcom,dsi-display-active; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-idp.dts b/arch/arm/boot/dts/qcom/trinket-idp.dts new file mode 100644 index 000000000000..279db833334a --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-idp.dts @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "trinket.dtsi" +#include "trinket-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. TRINKET IDP"; + compatible = "qcom,trinket-idp", "qcom,trinket", "qcom,idp"; + qcom,board-id = <34 0>; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-idp.dtsi b/arch/arm/boot/dts/qcom/trinket-idp.dtsi new file mode 100644 index 000000000000..c44510d73cf1 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-idp.dtsi @@ -0,0 +1,383 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include "trinket-thermal-overlay.dtsi" +#include "trinket-sde-display.dtsi" +#include +#include "trinket-camera-sensor-idp.dtsi" + +&qupv3_se1_i2c { + status = "ok"; + #include "smb1355.dtsi" +}; + +&soc { + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-ascent-3450mah.dtsi" + #include "qg-batterydata-mlp356477-2800mah.dtsi" + }; +}; + +&pm6125_vadc { + rf_pa1_therm { + reg = ; + label = "rf_pa1_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm6125_adc_tm { + io-channels = <&pm6125_vadc ADC_AMUX_THM1_PU2>, + <&pm6125_vadc ADC_AMUX_THM2_PU2>, + <&pm6125_vadc ADC_XO_THERM_PU2>, + <&pm6125_vadc ADC_GPIO4_PU2>; + + rf_pa1_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + rf-pa1-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm ADC_GPIO4_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet-therm-step { + status = "disabled"; + }; +}; + +&qupv3_se1_i2c { + status = "ok"; + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 85 0x00>; + qcom,nq-ven = <&tlmm 83 0x00>; + qcom,nq-firm = <&tlmm 84 0x00>; + qcom,nq-clkreq = <&tlmm 95 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <85 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active + &nfc_clk_req_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend + &nfc_clk_req_suspend>; + }; +}; + +&sdhc_1 { + vdd-supply = <&pm6125_l24>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&pm6125_l11>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on + &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off + &sdc1_rclk_off>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm6125_l22>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&pm6125_l5>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&tlmm 98 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; + +&pmi632_qg { + qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <100>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,qg-use-s7-ocv; +}; + +&pmi632_charger { + qcom,battery-data = <&mtp_batterydata>; + qcom,suspend-input-on-debug-batt; + qcom,sw-jeita-enable; + qcom,step-charging-enable; + /* SMB1355 only */ + qcom,sec-charger-config = <2>; + dpdm-supply = <&qusb_phy0>; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,auto-recharge-soc = <98>; + qcom,flash-disable-soc = <10>; + qcom,hw-die-temp-mitigation; + qcom,hw-connector-mitigation; + qcom,connector-internal-pull-kohm = <100>; + qcom,float-option = <1>; + qcom,thermal-mitigation = <3000000 2500000 + 2000000 1500000 1000000 500000>; +}; + +&usb0 { + extcon = <&pmi632_charger>, <&eud>; +}; + +&pmi632_gpios { + smb_en { + smb_en_default: smb_en_default { + pins = "gpio2"; + function = "func1"; + output-enable; + }; + }; + + pmi632_sense { + /* GPIO 7 and 8 are external-sense pins for PMI632 */ + pmi632_sense_default: pmi632_sense_default { + pins = "gpio7", "gpio8"; + bias-high-impedance; /* disable the GPIO */ + bias-disable; /* no-pull */ + }; + }; + + pmi632_ctm { + /* Disable GPIO1 for h/w base mitigation */ + pmi632_ctm_default: pmi632_ctm_default { + pins = "gpio1"; + bias-high-impedance; /* disable the GPIO */ + bias-disable; /* no-pull */ + }; + }; +}; + +&pm6125_gpios { + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio5"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + linux,can-disable; + debounce-interval = <15>; + gpio-key,wakeup; + }; + }; +}; + +&tlmm { + smb_int_default: smb_int_default { + mux { + pins = "gpio130"; + function = "gpio"; + }; + config { + pins = "gpio130"; + bias-pull-up; + input-enable; + }; + }; +}; + +&smb1355 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_int_default>; + interrupt-parent = <&tlmm>; + interrupts = <130 IRQ_TYPE_LEVEL_LOW>; + status = "ok"; +}; + +&smb1355_charger { + pinctrl-names = "default"; + pinctrl-0 = <&smb_en_default &pmi632_sense_default &pmi632_ctm_default>; + qcom,parallel-mode = <1>; + qcom,disable-ctm; + qcom,hw-die-temp-mitigation; + status = "ok"; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v3-660"; + + vdda-phy-supply = <&pm6125_l4>; /* 0.9v */ + vdda-pll-supply = <&pm6125_l10>; /* 1.8v */ + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14200>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm6125_l24>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm6125_l11>; + vcc-max-microamp = <600000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm6125_l18>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vddp-ref-clk-min-uV = <1200000>; + qcom,vddp-ref-clk-max-uV = <1232000>; + + status = "ok"; +}; + +&pm6125_pwm { + status = "ok"; +}; + +&dsi_td4330_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm6125_pwm 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 90 0>; + qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>; +}; + +&dsi_td4330_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm6125_pwm 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-te-gpio = <&tlmm 89 0>; + qcom,platform-reset-gpio = <&tlmm 90 0>; + qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 90 0>; +}; + +&dsi_hx83112a_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm6125_pwm 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 90 0>; + qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>; +}; + +&dsi_nt36672_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + pwms = <&pm6125_pwm 0 0>; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 90 0>; + qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>; +}; + +&qupv3_se2_i2c { + status = "okay"; + qcom,i2c-touch-active="synaptics,tcm-i2c"; + + synaptics_tcm@20 { + compatible = "synaptics,tcm-i2c"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <88 0x2008>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + synaptics,irq-gpio = <&tlmm 88 0x2008>; + synaptics,irq-on-state = <0>; + synaptics,reset-gpio = <&tlmm 87 0x00>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + synaptics,reset-delay-ms = <200>; + synaptics,power-delay-ms = <200>; + synaptics,ubl-i2c-addr = <0x20>; + synaptics,y-flip; + }; + + himax_ts@48 { + compatible = "himax,hxcommon"; + reg = <0x48>; + interrupt-parent = <&tlmm>; + interrupts = <88 0x2008>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + himax,panel-coords = <0 1080 0 2160>; + himax,display-coords = <0 1080 0 2160>; + himax,irq-gpio = <&tlmm 88 0x00>; + himax,rst-gpio = <&tlmm 87 0x00>; + report_type = <1>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-ion.dtsi b/arch/arm/boot/dts/qcom/trinket-ion.dtsi new file mode 100644 index 000000000000..3aec5ffdf4d1 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-ion.dtsi @@ -0,0 +1,62 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = <25>; + qcom,ion-heap-type = "SYSTEM"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = <27>; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@19 { /* QSEECOM TA HEAP */ + reg = <19>; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@9 { + reg = <9>; + qcom,ion-heap-type = "SYSTEM_SECURE"; + }; + + qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ + reg = <10>; + memory-region = <&secure_display_memory>; + qcom,ion-heap-type = "HYP_CMA"; + }; + + qcom,ion-heap@14 { /* SECURE CARVEOUT HEAP */ + reg = <14>; + qcom,ion-heap-type = "SECURE_CARVEOUT"; + cdsp { + memory-region = <&cdsp_sec_mem>; + token = <0x20000000>; + }; + }; + + qcom,ion-heap@22 { /* ADSP HEAP */ + reg = <22>; + memory-region = <&sdsp_mem>; + qcom,ion-heap-type = "DMA"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-pinctrl.dtsi b/arch/arm/boot/dts/qcom/trinket-pinctrl.dtsi new file mode 100644 index 000000000000..19c93d69922b --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-pinctrl.dtsi @@ -0,0 +1,1851 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + tlmm: pinctrl@400000 { + compatible = "qcom,trinket-pinctrl"; + reg = <0x400000 0xc00000>; + reg-names = "pinctrl"; + interrupts-extended = <&wakegic GIC_SPI 227 IRQ_TYPE_NONE>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + interrupt-parent = <&wakegpio>; + #interrupt-cells = <2>; + + /* QUPv3_0 SE mappings */ + /* SE 0 pin mappings */ + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_active: qupv3_se0_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "qup00"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + /* SE 1 pin mappings */ + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_active: qupv3_se1_i2c_active { + mux { + pins = "gpio4", "gpio5"; + function = "qup01"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 85 NFC Read Interrupt */ + pins = "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio85"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 85 NFC Read Interrupt */ + pins = "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio85"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_active: nfc_enable_active { + /* active state */ + mux { + /* 83: Enable 84: Firmware */ + pins = "gpio83", "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio83", "gpio84"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + /* sleep state */ + mux { + /* 83: Enable 84: Firmware */ + pins = "gpio83", "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio83", "gpio84"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_clk_req_active: nfc_clk_req_active { + /* active state */ + mux { + /* GPIO 95: NFC CLOCK REQUEST */ + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_clk_req_suspend: nfc_clk_req_suspend { + /* sleep state */ + mux { + /* GPIO 95: NFC CLOCK REQUEST */ + pins = "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio95"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + + /* SE 2 pin mappings */ + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio6", "gpio7"; + function = "qup02"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + /* SE 3 pin mappings */ + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_active: qupv3_se3_i2c_active { + mux { + pins = "gpio14", "gpio15"; + function = "qup03"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + /* SE 4 pin mappings */ + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_active: qupv3_se4_i2c_active { + mux { + pins = "gpio16", "gpio17"; + function = "qup04"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + /*QUPv3_1 SE mappings */ + /* SE 5 pin mappings */ + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_active: qupv3_se5_i2c_active { + mux { + pins = "gpio22", "gpio23"; + function = "qup10"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio22", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + /* SE 6 pin mappings */ + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_active: qupv3_se6_i2c_active { + mux { + pins = "gpio30", "gpio31"; + function = "qup11"; + }; + + config { + pins = "gpio30", "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio30", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio31"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + /* SE 7 pin mappings */ + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_active: qupv3_se7_i2c_active { + mux { + pins = "gpio28", "gpio29"; + function = "qup12"; + }; + + config { + pins = "gpio28", "gpio29"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio28", "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio29"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + /* SE 8 pin mappings */ + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_active: qupv3_se8_i2c_active { + mux { + pins = "gpio18", "gpio19"; + function = "qup13"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + /* SE 9 pin mappings */ + qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { + qupv3_se9_i2c_active: qupv3_se9_i2c_active { + mux { + pins = "gpio10", "gpio11"; + function = "qup14"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { + mux { + pins = "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se3_4uart_pins: qupv3_se3_4uart_pins { + qupv3_se3_rx: qupv3_se3_rx { + mux { + pins = "gpio15"; + function = "qup03"; + }; + + config { + pins = "gpio15"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + qupv3_se3_tx: qupv3_se6_tx { + mux { + pins = "gpio14"; + function = "qup03"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se4_2uart_pins: qupv3_se4_2uart_pins { + qupv3_se4_2uart_active: qupv3_se4_2uart_active { + mux { + pins = "gpio16", "gpio17"; + function = "qup04"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_2uart_sleep: qupv3_se4_2uart_sleep { + mux { + pins = "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se9_4uart_pins: qupv3_se9_4uart_pins { + qupv3_se9_ctsrx: qupv3_se9_ctsrx { + mux { + pins = "gpio10", "gpio13"; + function = "qup14"; + }; + + config { + pins = "gpio10", "gpio13"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + qupv3_se9_rts: qupv3_se9_rts { + mux { + pins = "gpio11"; + function = "qup14"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se9_tx: qupv3_se9_tx { + mux { + pins = "gpio12"; + function = "qup14"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + /* SPI Instances */ + /* SE 0 pin mappings */ + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_active: qupv3_se0_spi_active { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "qup00"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "gpio"; + }; + + configs { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 2 pin mappings */ + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_active: qupv3_se2_spi_active { + mux { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + function = "qup02"; + }; + + config { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + function = "gpio"; + }; + + configs { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 5 pin mappings */ + qupv3_se5_spi_pins: qupv3_se5_spi_pins { + qupv3_se5_spi_active: qupv3_se5_spi_active { + mux { + pins = "gpio22", "gpio23", "gpio24", + "gpio25"; + function = "qup10"; + }; + + config { + pins = "gpio22", "gpio23", "gpio24", + "gpio25"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { + mux { + pins = "gpio22", "gpio23", "gpio24", + "gpio25"; + function = "gpio"; + }; + + configs { + pins = "gpio22", "gpio23", "gpio24", + "gpio25"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 6 pin mappings */ + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_active: qupv3_se6_spi_active { + mux { + pins = "gpio30", "gpio31", "gpio32", + "gpio33"; + function = "qup11"; + }; + + config { + pins = "gpio30", "gpio31", "gpio32", + "gpio33"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio30", "gpio31", "gpio32", + "gpio33"; + function = "gpio"; + }; + + configs { + pins = "gpio30", "gpio31", "gpio32", + "gpio33"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 8 pin mappings */ + qupv3_se8_spi_pins: qupv3_se8_spi_pins { + qupv3_se8_spi_active: qupv3_se8_spi_active { + mux { + pins = "gpio18", "gpio19", "gpio20", + "gpio21"; + function = "qup13"; + }; + + config { + pins = "gpio18", "gpio19", "gpio20", + "gpio21"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { + mux { + pins = "gpio18", "gpio19", "gpio20", + "gpio21"; + function = "gpio"; + }; + + configs { + pins = "gpio18", "gpio19", "gpio20", + "gpio21"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 9 pin mappings */ + qupv3_se9_spi_pins: qupv3_se9_spi_pins { + qupv3_se9_spi_active: qupv3_se9_spi_active { + mux { + pins = "gpio10", "gpio11", "gpio12", + "gpio13"; + function = "qup_14"; + }; + + config { + pins = "gpio10", "gpio11", "gpio12", + "gpio13"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { + mux { + pins = "gpio10", "gpio11", "gpio12", + "gpio13"; + function = "gpio"; + }; + + configs { + pins = "gpio10", "gpio11", "gpio12", + "gpio13"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + fsa_usbc_ana_en_n@124 { + fsa_usbc_ana_en: fsa_usbc_ana_en { + mux { + pins = "gpio124"; + function = "gpio"; + }; + + config { + pins = "gpio124"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + }; + + wsa_swr_clk_pin { + wsa_swr_clk_sleep: wsa_swr_clk_sleep { + mux { + pins = "gpio18"; + function = "WSA_CLK"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + wsa_swr_clk_active: wsa_swr_clk_active { + mux { + pins = "gpio18"; + function = "WSA_CLK"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + }; + + wsa_swr_data_pin { + wsa_swr_data_sleep: wsa_swr_data_sleep { + mux { + pins = "gpio19"; + function = "WSA_DATA"; + }; + + config { + pins = "gpio19"; + drive-strength = <4>; + bias-bus-hold; + }; + }; + + wsa_swr_data_active: wsa_swr_data_active { + mux { + pins = "gpio19"; + function = "WSA_DATA"; + }; + + config { + pins = "gpio19"; + drive-strength = <4>; + bias-bus-hold; + }; + }; + }; + + /* WSA speaker reset pins */ + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + wcd9xxx_intr { + wcd_intr_default: wcd_intr_default{ + mux { + pins = "gpio110"; + function = "gpio"; + }; + + config { + pins = "gpio110"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + tasha_cdc_reset_active: lpi_cdc_reset_active { + mux { + pins = "gpio120"; + function = "gpio"; + }; + config { + pins = "gpio120"; + drive-strength = <16>; + output-high; + }; + }; + + tasha_cdc_reset_sleep: lpi_cdc_reset_sleep { + mux { + pins = "gpio120"; + function = "gpio"; + }; + + config { + pins = "gpio120"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + + /* Tasha WSA speaker reset pins */ + tasha_spkr_1_sd_n { + tasha_spkr_1_sd_n_sleep: tasha_spkr_1_sd_n_sleep { + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + tasha_spkr_1_sd_n_active: tasha_spkr_1_sd_n_active { + mux { + pins = "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio20"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + tasha_spkr_2_sd_n { + tasha_spkr_2_sd_n_sleep: tasha_spkr_2_sd_n_sleep { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + tasha_spkr_2_sd_n_active: tasha_spkr_2_sd_n_active { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + audio_ref_clk_active: audio_ref_clk_active { + mux { + pins = "gpio112"; + function = "gpio"; + }; + + config { + pins = "gpio112"; + drive-strength = <8>; + bias-disable; + output-low; + }; + }; + + audio_ref_clk_sleep: audio_ref_clk_sleep { + mux { + pins = "gpio112"; + function = "gpio"; + }; + + config { + pins = "gpio112"; + drive-strength = <2>; + bias-disable; + bias-pull-down; + }; + }; + + wcd937x_reset_active: wcd937x_reset_active { + mux { + pins = "gpio120"; + function = "gpio"; + }; + config { + pins = "gpio120"; + drive-strength = <16>; + output-high; + }; + }; + + wcd937x_reset_sleep: wcd937x_reset_sleep { + mux { + pins = "gpio120"; + function = "gpio"; + }; + + config { + pins = "gpio120"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + + cdc_dmic01_clk_active: dmic01_clk_active { + mux { + pins = "gpio125"; + function = "DMIC0_CLK"; + }; + + config { + pins = "gpio125"; + drive-strength = <8>; + output-high; + }; + }; + + cdc_dmic01_clk_sleep: dmic01_clk_sleep { + mux { + pins = "gpio125"; + function = "DMIC0_CLK"; + }; + + config { + pins = "gpio125"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_dmic01_data_active: dmic01_data_active { + mux { + pins = "gpio126"; + function = "DMIC0_DATA"; + }; + + config { + pins = "gpio126"; + drive-strength = <8>; + input-enable; + }; + }; + + cdc_dmic01_data_sleep: dmic01_data_sleep { + mux { + pins = "gpio126"; + function = "DMIC0_DATA"; + }; + + config { + pins = "gpio126"; + drive-strength = <2>; + pull-down; + input-enable; + }; + }; + + cdc_dmic23_clk_active: dmic23_clk_active { + mux { + pins = "gpio127"; + function = "DMIC1_CLK"; + }; + + config { + pins = "gpio127"; + drive-strength = <8>; + output-high; + }; + }; + + cdc_dmic23_clk_sleep: dmic23_clk_sleep { + mux { + pins = "gpio127"; + function = "DMIC1_CLK"; + }; + + config { + pins = "gpio127"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_dmic23_data_active: dmic23_data_active { + mux { + pins = "gpio128"; + function = "DMIC1_DATA"; + }; + + config { + pins = "gpio128"; + drive-strength = <8>; + input-enable; + }; + }; + + cdc_dmic23_data_sleep: dmic23_data_sleep { + mux { + pins = "gpio128"; + function = "DMIC1_DATA"; + }; + + config { + pins = "gpio128"; + drive-strength = <2>; + pull-down; + input-enable; + }; + }; + + tx_swr_clk_sleep: tx_swr_clk_sleep { + mux { + pins = "gpio106"; + function = "swr_tx"; + }; + + config { + pins = "gpio106"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + tx_swr_clk_active: tx_swr_clk_active { + mux { + pins = "gpio106"; + function = "swr_tx"; + }; + + config { + pins = "gpio106"; + drive-strength = <10>; + bias-bus-hold; + }; + }; + + tx_swr_data1_sleep: tx_swr_data1_sleep { + mux { + pins = "gpio107"; + function = "swr_tx"; + }; + + config { + pins = "gpio107"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + tx_swr_data1_active: tx_swr_data1_active { + mux { + pins = "gpio107"; + function = "swr_tx"; + }; + + config { + pins = "gpio107"; + drive-strength = <10>; + bias-bus-hold; + }; + }; + + tx_swr_data2_sleep: tx_swr_data2_sleep { + mux { + pins = "gpio108"; + function = "swr_tx"; + }; + + config { + pins = "gpio108"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + tx_swr_data2_active: tx_swr_data2_active { + mux { + pins = "gpio108"; + function = "swr_tx"; + }; + + config { + pins = "gpio108"; + drive-strength = <10>; + bias-bus-hold; + }; + }; + + rx_swr_clk_sleep: rx_swr_clk_sleep { + mux { + pins = "gpio110"; + function = "swr_rx"; + }; + + config { + pins = "gpio110"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + rx_swr_clk_active: rx_swr_clk_active { + mux { + pins = "gpio110"; + function = "swr_rx"; + }; + + config { + pins = "gpio110"; + drive-strength = <10>; + bias-bus-hold; + }; + }; + + rx_swr_data_sleep: rx_swr_data_sleep { + mux { + pins = "gpio111", "gpio112"; + function = "swr_rx"; + }; + + config { + pins = "gpio111", "gpio112"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + + rx_swr_data_active: rx_swr_data_active { + mux { + pins = "gpio111", "gpio112"; + function = "swr_rx"; + }; + + config { + pins = "gpio111", "gpio112"; + drive-strength = <10>; + bias-bus-hold; + }; + }; + + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio89"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio89"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio89"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio89"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active { + mux { + pins = "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio102"; + bias-disable; + drive-strength = <16>; + }; + }; + + sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend { + mux { + pins = "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio102"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + sde_dp_hotplug_ctrl: sde_dp_hotplug_ctrl { + mux { + pins = "gpio100"; + function = "dp_hot"; + }; + + config { + pins = "gpio100"; + bias-disable; + input-enable; + drive-strength = <2>; + }; + }; + + sde_dp_hotplug_tlmm: sde_dp_hotplug_tlmm { + mux { + pins = "gpio100"; + function = "gpio"; + }; + + config { + pins = "gpio100"; + bias-disable; + input-enable; + drive-strength = <2>; + }; + }; + + /* SDC pin type */ + sdc1_clk_on: sdc1_clk_on { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc1_clk_off: sdc1_clk_off { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_cmd_on: sdc1_cmd_on { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_cmd_off: sdc1_cmd_off { + config { + pins = "sdc1_cmd"; + num-grp-pins = <1>; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_data_on: sdc1_data_on { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_data_off: sdc1_data_off { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_rclk_on: sdc1_rclk_on { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc1_rclk_off: sdc1_rclk_off { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_on: cd_on { + mux { + pins = "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio98"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_cd_off: cd_off { + mux { + pins = "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio98"; + drive-strength = <2>; + bias-disable; + }; + }; + + ufs_dev_reset_assert: ufs_dev_reset_assert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * UFS_RESET driver strengths are having + * different values/steps compared to typical + * GPIO drive strengths. + * + * Following table clarifies: + * + * HDRV value | UFS_RESET | Typical GPIO + * (dec) | (mA) | (mA) + * 0 | 0.8 | 2 + * 1 | 1.55 | 4 + * 2 | 2.35 | 6 + * 3 | 3.1 | 8 + * 4 | 3.9 | 10 + * 5 | 4.65 | 12 + * 6 | 5.4 | 14 + * 7 | 6.15 | 16 + * + * POR value for UFS_RESET HDRV is 3 which means + * 3.1mA and we want to use that. Hence just + * specify 8mA to "drive-strength" binding and + * that should result into writing 3 to HDRV + * field. + */ + drive-strength = <8>; /* default: 3.1 mA */ + output-low; /* active low reset */ + }; + }; + + ufs_dev_reset_deassert: ufs_dev_reset_deassert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * default: 3.1 mA + * check comments under ufs_dev_reset_assert + */ + drive-strength = <8>; + output-high; /* active low reset */ + }; + }; + + pmx_ts_int_active { + ts_int_active: ts_int_active { + mux { + pins = "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio88"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_reset_active { + ts_reset_active: ts_reset_active { + mux { + pins = "gpio87"; + function = "gpio"; + }; + + config { + pins = "gpio87"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio87"; + function = "gpio"; + }; + + config { + pins = "gpio87"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + ts_release: ts_release { + mux { + pins = "gpio88", "gpio87"; + function = "gpio"; + }; + + config { + pins = "gpio88", "gpio87"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + cci0_active: cci0_active { + mux { + /* CLK, DATA */ + pins = "gpio37", "gpio38"; + function = "cci_i2c"; + }; + + config { + pins = "gpio37", "gpio38"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio37", "gpio38"; + function = "cci_i2c"; + }; + + config { + pins = "gpio37", "gpio38"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA */ + pins = "gpio39", "gpio40"; + function = "cci_i2c"; + }; + + config { + pins = "gpio39", "gpio40"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio39", "gpio40"; + function = "cci_i2c"; + }; + + config { + pins = "gpio39", "gpio40"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio34"; + function = "cam_mclk"; + }; + + config { + pins = "gpio34"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio34"; + function = "cam_mclk"; + }; + + config { + pins = "gpio34"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_active: cam_sensor_rear_active { + /* RESET */ + mux { + pins = "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio48"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_suspend: cam_sensor_rear_suspend { + /* RESET */ + mux { + pins = "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio48"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_front_active: cam_sensor_front_active { + /* RESET */ + mux { + pins = "gpio42"; + function = "gpio"; + }; + + config { + pins = "gpio42"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_suspend: cam_sensor_front_suspend { + /* RESET */ + mux { + pins = "gpio42"; + function = "gpio"; + }; + + config { + pins = "gpio42"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_rear2_active: cam_sensor_rear2_active { + /* RESET */ + mux { + pins = "gpio46"; + function = "gpio"; + }; + + config { + pins = "gpio46"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear2_suspend: cam_sensor_rear2_suspend { + /* RESET */ + mux { + pins = "gpio46"; + function = "gpio"; + }; + + config { + pins = "gpio46"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio35"; + function = "cam_mclk"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio35"; + function = "cam_mclk"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio36"; + function = "cam_mclk"; + }; + + config { + pins = "gpio36"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio36"; + function = "cam_mclk"; + }; + + config { + pins = "gpio36"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + fpc_reset_int: fpc_reset_int { + fpc_reset_low: reset_low { + mux { + pins = "gpio93"; + function = "gpio"; + }; + config { + pins = "gpio93"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + fpc_reset_high: reset_high { + mux { + pins = "gpio93"; + function = "gpio"; + }; + config { + pins = "gpio93"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + fpc_int_low: int_low { + mux { + pins = "gpio92"; + function = "gpio"; + }; + config { + pins = "gpio92"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + }; + }; +}; + +&pm6125_gpios { + tasha_mclk { + tasha_mclk_default: tasha_mclk_default{ + pins = "gpio1"; + function = "func1"; + qcom,drive-strength = <2>; + power-source = <0>; + bias-disable; + output-low; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-pm.dtsi b/arch/arm/boot/dts/qcom/trinket-pm.dtsi new file mode 100644 index 000000000000..7c19a94db509 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-pm.dtsi @@ -0,0 +1,224 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,spm@f1d2000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf1d2000 0x1000>; + reg-names = "saw-base"; + qcom,name = "system-cci"; + qcom,saw2-ver-reg = <0xfd0>; + qcom,saw2-cfg = <0x14>; + qcom,saw2-spm-dly= <0x3C102800>; + qcom,saw2-spm-ctl = <0xe>; + qcom,saw2-avs-ctl = <0x10>; + qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3 + &CPU4 &CPU5 &CPU6 &CPU7>; + qcom,vctl-timeout-us = <500>; + qcom,vctl-port = <0x0>; + qcom,phase-port = <0x1>; + qcom,pfm-port = <0x2>; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + qcom,use-psci; + #address-cells = <1>; + #size-cells = <0>; + qcom,pm-cluster@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + label = "system"; + qcom,spm-device-names = "cci"; + qcom,psci-mode-shift = <8>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0{ + reg = <0>; + label = "system-wfi"; + qcom,psci-mode = <0x0>; + qcom,entry-latency-us = <640>; + qcom,exit-latency-us = <1654>; + qcom,min-residency-us = <2294>; + }; + + qcom,pm-cluster-level@1{ /* E3 */ + reg = <1>; + label = "system-pc"; + qcom,psci-mode = <0x3>; + qcom,entry-latency-us = <10831>; + qcom,exit-latency-us = <4506>; + qcom,min-residency-us = <15338>; + qcom,min-child-idx = <2>; + qcom,notify-rpm; + qcom,is-reset; + }; + + qcom,pm-cluster@0{ + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + label = "pwr"; + qcom,spm-device-names = "l2"; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0{ /* D1 */ + reg = <0>; + label = "pwr-l2-wfi"; + qcom,psci-mode = <0x1>; + qcom,entry-latency-us = <38>; + qcom,exit-latency-us = <51>; + qcom,min-residency-us = <89>; + }; + + qcom,pm-cluster-level@1{ /* D3G */ + reg = <1>; + label = "pwr-l2-gdhs"; + qcom,psci-mode = <0x2>; + qcom,entry-latency-us = <360>; + qcom,exit-latency-us = <421>; + qcom,min-residency-us = <782>; + qcom,min-child-idx = <1>; + }; + + qcom,pm-cluster-level@2{ /* D3 */ + reg = <2>; + label = "pwr-l2-pc"; + qcom,psci-mode = <0x4>; + qcom,entry-latency-us = <800>; + qcom,exit-latency-us = <2118>; + qcom,min-residency-us = <7376>; + qcom,min-child-idx = <1>; + qcom,is-reset; + }; + + qcom,pm-cpu { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>; + + qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + label = "wfi"; + qcom,psci-cpu-mode = <0x1>; + qcom,entry-latency-us = <49>; + qcom,exit-latency-us = <42>; + qcom,min-residency-us = <91>; + }; + + qcom,pm-cpu-level@1 { /* C3 */ + reg = <1>; + label = "pc"; + qcom,psci-cpu-mode = <0x3>; + qcom,entry-latency-us = <290>; + qcom,exit-latency-us = <376>; + qcom,min-residency-us = <1182>; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + }; + + qcom,pm-cluster@1{ + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + label = "perf"; + qcom,spm-device-names = "l2"; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0{ /* D1 */ + reg = <0>; + label = "perf-l2-wfi"; + qcom,psci-mode = <0x1>; + qcom,entry-latency-us = <38>; + qcom,exit-latency-us = <51>; + qcom,min-residency-us = <89>; + }; + + qcom,pm-cluster-level@1{ /* D3G*/ + reg = <1>; + label = "perf-l2-gdhs"; + qcom,psci-mode = <2>; + qcom,entry-latency-us = <314>; + qcom,exit-latency-us = <345>; + qcom,min-residency-us = <660>; + qcom,min-child-idx = <1>; + }; + + qcom,pm-cluster-level@2{ /* D3 */ + reg = <2>; + label = "perf-l2-pc"; + qcom,psci-mode = <0x4>; + qcom,entry-latency-us = <640>; + qcom,exit-latency-us = <1654>; + qcom,min-residency-us = <8094>; + qcom,min-child-idx = <1>; + qcom,is-reset; + }; + + qcom,pm-cpu { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>; + + qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + label = "wfi"; + qcom,psci-cpu-mode = <0x1>; + qcom,entry-latency-us = <29>; + qcom,exit-latency-us = <39>; + qcom,min-residency-us = <68>; + }; + + qcom,pm-cpu-level@1 { /* C3 */ + reg = <1>; + label = "pc"; + qcom,psci-cpu-mode = <0x3>; + qcom,entry-latency-us = <297>; + qcom,exit-latency-us = <324>; + qcom,min-residency-us = <1110>; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + }; + }; + }; + + qcom,rpm-stats@4600000 { + compatible = "qcom,rpm-stats"; + reg = <0x04600000 0x1000>, + <0x04690014 0x4>, + <0x0469001c 0x4>; + reg-names = "phys_addr_base", "offset_addr", + "heap_phys_addrbase"; + qcom,sleep-stats-version = <2>; + }; + + qcom,rpm-master-stats@45f0150 { + compatible = "qcom,rpm-master-stats"; + reg = <0x45f0150 0x5000>; + qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ"; + qcom,master-stats-version = <2>; + qcom,master-offset = <4096>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-qrd-overlay.dts b/arch/arm/boot/dts/qcom/trinket-qrd-overlay.dts new file mode 100644 index 000000000000..f60d871e06b2 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-qrd-overlay.dts @@ -0,0 +1,24 @@ +/* Copyright (c) 2018, 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include "trinket-qrd.dtsi" + +/ { + model = "QRD"; + compatible = "qcom,trinket-qrd", "qcom,trinket", "qcom,qrd"; + qcom,msm-id = <394 0x0>; + qcom,board-id = <11 0>; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-qrd.dts b/arch/arm/boot/dts/qcom/trinket-qrd.dts new file mode 100644 index 000000000000..945c10f0b6bf --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-qrd.dts @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "trinket.dtsi" +#include "trinket-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. TRINKET QRD"; + compatible = "qcom,trinket-qrd", "qcom,trinket", "qcom,qrd"; + qcom,board-id = <11 0>; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-qrd.dtsi b/arch/arm/boot/dts/qcom/trinket-qrd.dtsi new file mode 100644 index 000000000000..6a4eecf616a3 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-qrd.dtsi @@ -0,0 +1,392 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include "trinket-thermal-overlay.dtsi" +#include "trinket-sde-display.dtsi" +#include "trinket-audio-overlay.dtsi" +#include + +#include +#include "trinket-camera-sensor-qrd.dtsi" + +&qupv3_se1_i2c { + status = "ok"; + #include "smb1355.dtsi" +}; + +&soc { + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-ascent-3450mah.dtsi" + #include "qg-batterydata-mlp356477-2800mah.dtsi" + }; + + fingerprint: fpc1020 { + compatible = "fpc,fpc1020"; + interrupt-parent = <&tlmm>; + interrupts = <92 0>; + fpc,gpio_rst = <&tlmm 93 0>; + fpc,gpio_irq = <&tlmm 92 0>; + vcc_spi-supply = <&pm6125_l9>; + vdd_io-supply = <&pm6125_l9>; + vdd_ana-supply = <&pm6125_l9>; + fpc,enable-on-boot; + pinctrl-names = "fpc1020_reset_reset", + "fpc1020_reset_active", + "fpc1020_irq_active"; + pinctrl-0 = <&fpc_reset_low>; + pinctrl-1 = <&fpc_reset_high>; + pinctrl-2 = <&fpc_int_low>; + }; +}; + +&pmi632_qg { + qcom,battery-data = <&mtp_batterydata>; + qcom,qg-iterm-ma = <100>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,qg-use-s7-ocv; +}; + +&pmi632_charger { + qcom,battery-data = <&mtp_batterydata>; + qcom,suspend-input-on-debug-batt; + qcom,sw-jeita-enable; + /* SMB1355 only */ + qcom,sec-charger-config = <2>; + dpdm-supply = <&qusb_phy0>; + qcom,charger-temp-max = <800>; + qcom,smb-temp-max = <800>; + qcom,auto-recharge-soc = <98>; + qcom,flash-disable-soc = <10>; + qcom,hw-die-temp-mitigation; + qcom,hw-connector-mitigation; + qcom,connector-internal-pull-kohm = <100>; + qcom,float-option = <1>; + qcom,thermal-mitigation = <4200000 3500000 3000000 + 2500000 2000000 1500000 1000000 500000>; +}; + +&qupv3_se2_i2c { + status = "okay"; + + synaptics_tcm@20 { + compatible = "synaptics,tcm-i2c"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <88 0x2008>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&ts_release>; + synaptics,irq-gpio = <&tlmm 88 0x2008>; + synaptics,irq-on-state = <0>; + synaptics,reset-gpio = <&tlmm 87 0x00>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + synaptics,reset-delay-ms = <200>; + synaptics,power-delay-ms = <200>; + synaptics,ubl-i2c-addr = <0x20>; + synaptics,y-flip; + }; +}; + +&qupv3_se1_i2c { + status = "ok"; + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 85 0x00>; + qcom,nq-ven = <&tlmm 83 0x00>; + qcom,nq-firm = <&tlmm 84 0x00>; + qcom,nq-clkreq = <&tlmm 95 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <85 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active + &nfc_clk_req_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend + &nfc_clk_req_suspend>; + }; +}; + +&sdhc_1 { + vdd-supply = <&pm6125_l24>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&pm6125_l11>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on + &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off + &sdc1_rclk_off>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm6125_l22>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&pm6125_l5>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>; + + status = "ok"; +}; + +&pmi632_gpios { + smb_en { + smb_en_default: smb_en_default { + pins = "gpio2"; + function = "func1"; + output-enable; + }; + }; + + pmi632_sense { + /* GPIO 7 and 8 are external-sense pins for PMI632 */ + pmi632_sense_default: pmi632_sense_default { + pins = "gpio7", "gpio8"; + bias-high-impedance; /* disable the GPIO */ + bias-disable; /* no-pull */ + }; + }; + + pmi632_ctm { + /* Disable GPIO1 for h/w base mitigation */ + pmi632_ctm_default: pmi632_ctm_default { + pins = "gpio1"; + bias-high-impedance; /* disable the GPIO */ + bias-disable; /* no-pull */ + }; + }; +}; + +&pm6125_gpios { + key_vol_up { + key_vol_up_default: key_vol_up_default { + pins = "gpio5"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + vol_up { + label = "volume_up"; + gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + linux,can-disable; + debounce-interval = <15>; + gpio-key,wakeup; + }; + }; +}; + +&tlmm { + smb_int_default: smb_int_default { + mux { + pins = "gpio130"; + function = "gpio"; + }; + config { + pins = "gpio130"; + bias-pull-up; + input-enable; + }; + }; +}; + +&smb1355 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_int_default>; + interrupt-parent = <&tlmm>; + interrupts = <130 IRQ_TYPE_LEVEL_LOW>; + status = "ok"; +}; + +&smb1355_charger { + pinctrl-names = "default"; + pinctrl-0 = <&smb_en_default &pmi632_sense_default &pmi632_ctm_default>; + qcom,parallel-mode = <1>; + qcom,disable-ctm; + qcom,hw-die-temp-mitigation; + status = "ok"; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v3-660"; + + vdda-phy-supply = <&pm6125_l4>; /* 0.9v */ + vdda-pll-supply = <&pm6125_l10>; /* 1.8v */ + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14200>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm6125_l24>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm6125_l11>; + vcc-max-microamp = <600000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm6125_l18>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vddp-ref-clk-min-uV = <1200000>; + qcom,vddp-ref-clk-max-uV = <1232000>; + + status = "ok"; +}; + +&pmi632_vadc { + bat_therm { + qcom,lut-index = <0>; + }; + + bat_therm_30k { + qcom,lut-index = <0>; + }; + + bat_therm_400k { + qcom,lut-index = <0>; + }; +}; + +&usb0 { + extcon = <&pmi632_charger>, <&eud>; +}; + +&dsi_td4330_truly_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + pwms = <&pm6125_pwm 0 0>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-bl-default-level = <102>; + qcom,platform-te-gpio = <&tlmm 89 0>; + qcom,platform-reset-gpio = <&tlmm 90 0>; +}; + +&dsi_td4330_truly_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + pwms = <&pm6125_pwm 0 0>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; + qcom,bl-pmic-pwm-period-usecs = <100>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-bl-default-level = <102>; + qcom,platform-reset-gpio = <&tlmm 90 0>; +}; + +&dsi_td4330_truly_vid_display { + qcom,dsi-display-active; +}; + +&pm6125_pwm { + status = "ok"; +}; + +&sm6150_snd { + status = "okay"; + qcom,model = "trinket-qrd-snd-card"; + qcom,audio-routing = + "AMIC1", "MIC BIAS1", + "MIC BIAS1", "Analog Mic1", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Analog Mic2", + "AMIC3", "MIC BIAS3", + "MIC BIAS3", "Analog Mic3", + "TX_AIF1 CAP", "VA_MCLK", + "TX_AIF2 CAP", "VA_MCLK", + "RX AIF1 PB", "VA_MCLK", + "RX AIF2 PB", "VA_MCLK", + "RX AIF3 PB", "VA_MCLK", + "RX AIF4 PB", "VA_MCLK", + "HPHL_OUT", "VA_MCLK", + "HPHR_OUT", "VA_MCLK", + "AUX_OUT", "VA_MCLK", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "IN3_AUX", "AUX_OUT", + "TX SWR_ADC0", "ADC1_OUTPUT", + "TX SWR_ADC2", "ADC2_OUTPUT", + "WSA SRC0_INP", "SRC0", + "WSA_TX DEC0_INP", "TX DEC0 MUX", + "WSA_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "SpkrLeft IN", "WSA_SPK1 OUT", + "WSA_SPK1 OUT", "VA_MCLK"; + qcom,wsa-max-devs = <1>; + qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0213>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrLeft"; + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + asoc-codec = <&stub_codec>, <&bolero>, <&ext_disp_audio_codec>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec", + "msm-ext-disp-audio-codec-rx"; + qcom,codec-max-aux-devs = <1>; + qcom,codec-aux-devs = <&wcd937x_codec>; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, + <&bolero>; +}; + +&qusb_phy0 { + qcom,qusb-phy-init-seq = <0xc8 0x80 + 0x93 0x84 + 0x83 0x88 + 0xc7 0x8c + 0x30 0x08 + 0x79 0x0c + 0x21 0x10 + 0x14 0x9c + 0x80 0x04 + 0x9f 0x1c + 0x00 0x18>; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-qupv3.dtsi b/arch/arm/boot/dts/qcom/trinket-qupv3.dtsi new file mode 100644 index 000000000000..9a5d68d294de --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-qupv3.dtsi @@ -0,0 +1,462 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + /* + * QUPv3 Instances + * QUPv3_1 0 : SE 5 + * QUPv3_1 1 : SE 6 + * QUPv3_1 2 : SE 7 + * QUPv3_1 3 : SE 8 + * QUPv3_0 4 : SE 9 + * QUPv3_0 0 : SE 0 + * QUPv3_0 1 : SE 1 + * QUPv3_0 2 : SE 2 + * QUPv3_0 3 : SE 3 + * QUPv3_0 4 : SE 4 + */ + + /* QUPv3_0 Instances */ + qupv3_0: qcom,qupv3_0_geni_se@4ac0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x04ac0000 0x2000>; + + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-bus-ids = + , + ; + qcom,vote-for-bw; + + qcom,iommu-s1-bypass; + iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0x123 0x0>; + }; + }; + + /* HSUART with 2-wire mode */ + qupv3_se3_4uart: qcom,qup_uart@0x4a8c000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x4a8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_tx>, <&qupv3_se3_rx>; + pinctrl-1 = <&qupv3_se3_tx>, <&qupv3_se3_rx>; + interrupts-extended = <&intc GIC_SPI 330 0>, + <&tlmm 15 0>; + qcom,wakeup-byte = <0xFD>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* Debug UART Instance for CDP/MTP/RUMI platform */ + qupv3_se4_2uart: qcom,qup_uart@0x4a90000 { + compatible = "qcom,msm-geni-console"; + reg = <0x4a90000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_2uart_active>; + pinctrl-1 = <&qupv3_se4_2uart_sleep>; + interrupts = ; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* I2C */ + qupv3_se0_i2c: i2c@4a80000 { + compatible = "qcom,i2c-geni"; + reg = <0x04a80000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + dmas = <&gpi_dma0 0 0 3 64 0>, + <&gpi_dma0 1 0 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se1_i2c: i2c@4a84000 { + compatible = "qcom,i2c-geni"; + reg = <0x04a84000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + dmas = <&gpi_dma0 0 1 3 64 0>, + <&gpi_dma0 1 1 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se1_i2c_active>; + pinctrl-1 = <&qupv3_se1_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@4a88000 { + compatible = "qcom,i2c-geni"; + reg = <0x04a88000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + dmas = <&gpi_dma0 0 2 3 64 0>, + <&gpi_dma0 1 2 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se3_i2c: i2c@4a8c000 { + compatible = "qcom,i2c-geni"; + reg = <0x04a8c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + dmas = <&gpi_dma0 0 3 3 64 0>, + <&gpi_dma0 1 3 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se3_i2c_active>; + pinctrl-1 = <&qupv3_se3_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se4_i2c: i2c@4a90000 { + compatible = "qcom,i2c-geni"; + reg = <0x04a90000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + dmas = <&gpi_dma0 0 4 3 64 0>, + <&gpi_dma0 1 4 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se4_i2c_active>; + pinctrl-1 = <&qupv3_se4_i2c_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* SPI Instances */ + qupv3_se0_spi: spi@4a80000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x04a80000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + dmas = <&gpi_dma0 0 0 1 64 0>, + <&gpi_dma0 1 0 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se2_spi: spi@4a88000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x04a88000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + dmas = <&gpi_dma0 0 2 1 64 0>, + <&gpi_dma0 1 2 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + /* QUPv3_1 instances */ + qupv3_1: qcom,qupv3_1_geni_se@4cc0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x04cc0000 0x2000>; + + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-bus-ids = + , + ; + qcom,vote-for-bw; + + qcom,iommu-s1-bypass; + iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb { + compatible = "qcom,qupv3-geni-se-cb"; + iommus = <&apps_smmu 0x143 0x0>; + }; + }; + + /* + * HS UART instances. HS UART usecases can be supported on these + * instances only. + */ + qupv3_se9_4uart: qcom,qup_uart@0x4c90000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x4c90000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_ctsrx>, <&qupv3_se9_rts>, + <&qupv3_se9_tx>; + pinctrl-1 = <&qupv3_se9_ctsrx>, <&qupv3_se9_rts>, + <&qupv3_se9_tx>; + interrupts-extended = <&intc GIC_SPI 312 0>, + <&tlmm 13 0>; + qcom,wakeup-byte = <0xFD>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* I2C */ + qupv3_se5_i2c: i2c@4c80000 { + compatible = "qcom,i2c-geni"; + reg = <0x04c80000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + dmas = <&gpi_dma1 0 0 3 64 0>, + <&gpi_dma1 1 0 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_i2c_active>; + pinctrl-1 = <&qupv3_se5_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se6_i2c: i2c@4c84000 { + compatible = "qcom,i2c-geni"; + reg = <0x04c84000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + dmas = <&gpi_dma1 0 1 3 64 0>, + <&gpi_dma1 1 1 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se7_i2c: i2c@4c88000 { + compatible = "qcom,i2c-geni"; + reg = <0x04c88000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + dmas = <&gpi_dma1 0 2 3 64 0>, + <&gpi_dma1 1 2 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se8_i2c: i2c@4c8c000 { + compatible = "qcom,i2c-geni"; + reg = <0x04c8c000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + dmas = <&gpi_dma1 0 3 3 64 0>, + <&gpi_dma1 1 3 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se9_i2c: i2c@4c90000 { + compatible = "qcom,i2c-geni"; + reg = <0x04c90000 0x4000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + dmas = <&gpi_dma1 0 4 3 64 0>, + <&gpi_dma1 1 4 3 64 0>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_i2c_active>; + pinctrl-1 = <&qupv3_se9_i2c_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* SPI Instances */ + qupv3_se5_spi: spi@4c80000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x04c80000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_spi_active>; + pinctrl-1 = <&qupv3_se5_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + dmas = <&gpi_dma1 0 0 1 64 0>, + <&gpi_dma1 1 0 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se6_spi: spi@4c84000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x04c84000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + dmas = <&gpi_dma1 0 1 1 64 0>, + <&gpi_dma1 1 1 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se8_spi: spi@4c8c000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x04c8c000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_spi_active>; + pinctrl-1 = <&qupv3_se8_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + dmas = <&gpi_dma1 0 3 1 64 0>, + <&gpi_dma1 1 3 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + qupv3_se9_spi: spi@4c90000 { + compatible = "qcom,spi-geni"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x04c90000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_spi_active>; + pinctrl-1 = <&qupv3_se9_spi_sleep>; + interrupts = ; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + dmas = <&gpi_dma1 0 4 1 64 0>, + <&gpi_dma1 1 4 1 64 0>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + +}; diff --git a/arch/arm/boot/dts/qcom/trinket-regulator.dtsi b/arch/arm/boot/dts/qcom/trinket-regulator.dtsi new file mode 100644 index 000000000000..15c3eaaa1fb3 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-regulator.dtsi @@ -0,0 +1,372 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&rpm_bus { + /* PM6125 S3/S4 - VDD_CX supply */ + rpm-regulator-smpa3 { + status = "okay"; + VDD_CX_LEVEL: + S3A_LEVEL: pm6125_s3_level: regulator-s3-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s3_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + VDD_CX_FLOOR_LEVEL: + S3A_FLOOR_LEVEL: + pm6125_s3_floor_level: regulator-s3-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s3_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + VDD_CX_LEVEL_AO: + S3A_LEVEL_AO: pm6125_s3_level_ao: regulator-s3-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s3_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + cx_cdev: cx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&VDD_CX_FLOOR_LEVEL>; + regulator-levels = ; + #cooling-cells = <2>; + }; + + }; + + /* PM6125 S5 - VDD_MX/WCSS_MX supply */ + rpm-regulator-smpa5 { + status = "okay"; + VDD_MX_LEVEL: + S5A_LEVEL: pm6125_s5_level: regulator-s5-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s5_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + VDD_MX_FLOOR_LEVEL: + S5A_FLOOR_LEVEL: + pm6125_s5_floor_level: regulator-s5-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s5_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + VDD_MX_LEVEL_AO: + S5A_LEVEL_AO: pm6125_s5_level_ao: regulator-s5-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm6125_s5_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + mx_cdev: mx-cdev-lvl { + compatible = "qcom,regulator-cooling-device"; + regulator-cdev-supply = <&VDD_MX_LEVEL>; + regulator-levels = ; + #cooling-cells = <2>; + }; + + }; + + rpm-regulator-smpa6 { + status = "okay"; + S6A: pm6125_s6: regulator-s6 { + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <1422000>; + qcom,init-voltage = <936000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + L1A: pm6125_l1: regulator-l1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1256000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + L2A: pm6125_l2: regulator-l2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1056000>; + qcom,init-voltage = <1000000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + L3A: pm6125_l3: regulator-l3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1064000>; + qcom,init-voltage = <1000000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa4 { + status = "okay"; + L4A: pm6125_l4: regulator-l4 { + parent-supply = <&pm6125_l7>; + regulator-min-microvolt = <872000>; + regulator-max-microvolt = <976000>; + qcom,init-voltage = <872000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + L5A: pm6125_l5: regulator-l5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3104000>; + qcom,init-voltage = <1648000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + L6A: pm6125_l6: regulator-l6 { + regulator-min-microvolt = <576000>; + regulator-max-microvolt = <656000>; + qcom,init-voltage = <576000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + L7A: pm6125_l7: regulator-l7 { + regulator-min-microvolt = <872000>; + regulator-max-microvolt = <976000>; + qcom,init-voltage = <872000>; + status = "okay"; + }; + }; + + /* WCSS_CX */ + rpm-regulator-ldoa8 { + status = "okay"; + L8A: pm6125_l8: regulator-l8 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + qcom,init-voltage = <400000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa9 { + status = "okay"; + L9A: pm6125_l9: regulator-l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1896000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + L10A: pm6125_l10: regulator-l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1896000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + L11A: pm6125_l11: regulator-l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1952000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + L12A: pm6125_l12: regulator-l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1996000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + L13A: pm6125_l13: regulator-l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1832000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + L14A: pm6125_l14: regulator-l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa15 { + status = "okay"; + L15A: pm6125_l15: regulator-l15 { + parent-supply = <&pm6125_l10>; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3232000>; + qcom,init-voltage = <3104000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa16 { + status = "okay"; + L16A: pm6125_l16: regulator-l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa17 { + status = "okay"; + L17A: pm6125_l17: regulator-l17 { + regulator-min-microvolt = <1248000>; + regulator-max-microvolt = <1304000>; + qcom,init-voltage = <1248000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa18 { + status = "okay"; + L18A: pm6125_l18: regulator-l18 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1264000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa19 { + status = "okay"; + L19A: pm6125_l19: regulator-l19 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + qcom,init-voltage = <1648000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa20 { + status = "okay"; + L20A: pm6125_l20: regulator-l20 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + qcom,init-voltage = <1648000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa21 { + status = "okay"; + L21A: pm6125_l21: regulator-l21 { + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2856000>; + qcom,init-voltage = <2600000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa22 { + status = "okay"; + L22A: pm6125_l22: regulator-l22 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <3304000>; + qcom,init-voltage = <2944000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa23 { + status = "okay"; + L23A: pm6125_l23: regulator-l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + qcom,init-voltage = <3000000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa24 { + status = "okay"; + L24A: pm6125_l24: regulator-l24 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <3304000>; + qcom,init-voltage = <2944000>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm/boot/dts/qcom/trinket-rumi-overlay.dts similarity index 63% rename from arch/arm64/boot/dts/qcom/qcs404.dtsi rename to arch/arm/boot/dts/qcom/trinket-rumi-overlay.dts index bcf08143cbae..43aefda31585 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm/boot/dts/qcom/trinket-rumi-overlay.dts @@ -11,25 +11,15 @@ * GNU General Public License for more details. */ -#include "qcs405.dtsi" +/dts-v1/; +/plugin/; -/ { - model = "Qualcomm Technologies, Inc. QCS404"; - qcom,msm-name = "QCS404"; - qcom,msm-id = <410 0x0>; - -}; - -&adsp_fw_mem { - reg = <0x0 0x87400000 0x0 0x1200000>; -}; - -&reserved_mem { - linux,cma { - size = <0 0x400000>; - }; -}; +#include +#include "trinket-rumi.dtsi" -&qcom_seecom { - /delete-property/ qcom,appsbl-qseecom-support; +/ { + model = "Qualcomm Technologies, Inc. TRINKET RUMI"; + compatible = "qcom,trinket-rumi", "qcom,trinket", "qcom,rumi"; + qcom,msm-id = <394 0x10000>; + qcom,board-id = <15 0>; }; diff --git a/arch/arm/boot/dts/qcom/trinket-rumi.dts b/arch/arm/boot/dts/qcom/trinket-rumi.dts new file mode 100644 index 000000000000..fb74e3e1df9c --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-rumi.dts @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/memreserve/ 0x90000000 0x00000100; + +#include "trinket.dtsi" +#include "trinket-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. TRINKET RUMI"; + compatible = "qcom,trinket-rumi", "qcom,trinket", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-rumi.dtsi b/arch/arm/boot/dts/qcom/trinket-rumi.dtsi new file mode 100644 index 000000000000..491652363199 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-rumi.dtsi @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + usb_emu_phy: usb_emu_phy@4f20000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x04f20000 0x9500>, + <0x04ef8800 0x100>; + reg-names = "base", "qcratch_base"; + + qcom,emu-init-seq = <0xfff0 0x4 + 0xfff3 0x4 + 0x40 0x4 + 0xfff3 0x4 + 0xfff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x1a0 0x20 + 0x100000 0x3c + 0x0 0x3c + 0x10060 0x3c + 0x0 0x4>; + }; + + timer { + clock-frequency = <800000>; + }; + + timer@f120000 { + clock-frequency = <800000>; + }; + + wdog: qcom,wdt@f017000{ + status = "disabled"; + }; +}; + +&usb0 { + dwc3@4e00000 { + usb-phy = <&usb_emu_phy>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; +}; + +&qusb_phy0 { + status = "disabled"; +}; + +&usb_qmp_phy { + status = "disabled"; +}; + +&rpm_bus { + rpm-standalone; + /delete-node/ rpm-regulator-smpa3; + /delete-node/ rpm-regulator-smpa5; + /delete-node/ rpm-regulator-ldoa1; + /delete-node/ rpm-regulator-ldoa2; + /delete-node/ rpm-regulator-ldoa3; + /delete-node/ rpm-regulator-ldoa4; + /delete-node/ rpm-regulator-ldoa5; + /delete-node/ rpm-regulator-ldoa6; + /delete-node/ rpm-regulator-ldoa7; + /delete-node/ rpm-regulator-ldoa8; + /delete-node/ rpm-regulator-ldoa9; + /delete-node/ rpm-regulator-ldoa10; + /delete-node/ rpm-regulator-ldoa11; + /delete-node/ rpm-regulator-ldoa12; + /delete-node/ rpm-regulator-ldoa13; + /delete-node/ rpm-regulator-ldoa14; + /delete-node/ rpm-regulator-ldoa15; + /delete-node/ rpm-regulator-ldoa16; + /delete-node/ rpm-regulator-ldoa17; + /delete-node/ rpm-regulator-ldoa18; + /delete-node/ rpm-regulator-ldoa19; + /delete-node/ rpm-regulator-ldoa20; + /delete-node/ rpm-regulator-ldoa21; + /delete-node/ rpm-regulator-ldoa22; + /delete-node/ rpm-regulator-ldoa23; + /delete-node/ rpm-regulator-ldoa24; +}; + +&thermal_zones { + /delete-node/ aoss0-lowf; + /delete-node/ cdsp-lowf; + /delete-node/ wlan-lowf; + /delete-node/ camera-lowf; + /delete-node/ video-lowf; + /delete-node/ cpu-1-0-lowf; + /delete-node/ cpuss-0-lowf; + /delete-node/ mdm-core-lowf; + /delete-node/ display-lowf; + /delete-node/ gpu-lowf; +}; + +#include "trinket-stub-regulator.dtsi" + +&sdhc_1 { + vdd-supply = <&pm6125_l24>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&pm6125_l11>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on + &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off + &sdc1_rclk_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000>; + qcom,bus-speed-mode = "DDR_1p8v"; + + /delete-property/qcom,devfreq,freq-table; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm6125_l22>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&pm6125_l5>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50"; + + /delete-property/qcom,devfreq,freq-table; + + status = "ok"; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qrbtc-sdm845"; + + vdda-phy-supply = <&pm6125_l4>; /* 0.9v */ + vdda-pll-supply = <&pm6125_l10>; /* 1.8v */ + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14200>; + + status = "ok"; +}; + +&ufshc_mem { + limit-tx-hs-gear = <1>; + limit-rx-hs-gear = <1>; + scsi-cmd-timeout = <300000>; + + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm6125_l24>; + vccq2-supply = <&pm6125_l11>; + vcc-max-microamp = <600000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm6125_l18>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vddp-ref-clk-min-uV = <1232000>; + qcom,vddp-ref-clk-max-uV = <1232000>; + + qcom,disable-lpm; + rpm-level = <0>; + spm-level = <0>; + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-sde-display.dtsi b/arch/arm/boot/dts/qcom/trinket-sde-display.dtsi new file mode 100644 index 000000000000..2fdaf05559ce --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-sde-display.dtsi @@ -0,0 +1,329 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "dsi-panel-td4330-truly-singlemipi-fhd-cmd.dtsi" +#include "dsi-panel-td4330-truly-singlemipi-fhd-video.dtsi" +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi" +#include "dsi-panel-nt36672-truly-fhd-video.dtsi" +#include + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <62000>; + qcom,supply-disable-load = <80>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdda-3p3"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <13200>; + qcom,supply-disable-load = <80>; + }; + }; + + dsi_td4330_truly_vid_display: qcom,dsi-display@0 { + label = "dsi_td4330_truly_vid_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + + qcom,dsi-panel = <&dsi_td4330_truly_video>; + }; + + dsi_td4330_truly_cmd_display: qcom,dsi-display@1 { + label = "dsi_td4330_truly_cmd_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_td4330_truly_cmd>; + }; + + dsi_sim_vid_display: qcom,dsi-display@2 { + label = "dsi_sim_vid_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_sim_vid>; + }; + + dsi_hx83112a_truly_vid_display: qcom,dsi-display@3 { + label = "dsi_hx83112a_truly_vid_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_hx83112a_truly_video>; + }; + + dsi_nt36672_truly_vid_display: qcom,dsi-display@4 { + label = "dsi_nt36672_truly_vid_display"; + qcom,display-type = "primary"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + + qcom,dsi-panel = <&dsi_nt36672_truly_video>; + }; + + sde_dsi: qcom,dsi-display { + compatible = "qcom,dsi-display"; + + qcom,dsi-ctrl = <&mdss_dsi0>; + qcom,dsi-phy = <&mdss_dsi_phy0>; + + clocks = <&mdss_dsi0_pll BYTE0_MUX_CLK>, + <&mdss_dsi0_pll PIX0_MUX_CLK>, + <&mdss_dsi0_pll BYTE0_SRC_CLK>, + <&mdss_dsi0_pll PIX0_SRC_CLK>, + <&mdss_dsi0_pll SHADOW_BYTE0_SRC_CLK>, + <&mdss_dsi0_pll SHADOW_PIX0_SRC_CLK>; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "src_byte_clk0", "src_pixel_clk0", + "shadow_byte_clk0", "shadow_pixel_clk0"; + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 89 0>; + + vddio-supply = <&L9A>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + + qcom,dsi-display-list = + <&dsi_td4330_truly_vid_display + &dsi_td4330_truly_cmd_display + &dsi_sim_vid_display + &dsi_hx83112a_truly_vid_display + &dsi_nt36672_truly_vid_display>; + }; + + sde_wb: qcom,wb-display@0 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display"; + }; + +}; + +&mdss_mdp { + connectors = <&sde_wb &sde_dsi>; +}; + +&dsi_td4330_truly_cmd { + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x36>; + qcom,ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-on-check-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = + <1048269600 1030798440 1035166232 1039534024 1043901816>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = + [26 20 09 0B 06 02 04 a0 + 26 20 09 0B 06 02 04 a0 + 26 20 09 0B 06 02 04 a0 + 26 20 09 0B 06 02 04 a0 + 26 1F 09 0B 06 02 04 a0]; + + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <40 40 40 40 40 40>; + }; + }; +}; + +&dsi_td4330_truly_video { + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x35>; + qcom,dsi-supported-dfps-list = <60 55 48>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = + "dfps_immediate_porch_mode_vfp"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-on-check-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = + <1005903360 989138304 993329568 997520832 1001712096>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = + [25 20 09 0A 06 03 04 a0 + 25 20 09 0A 06 03 04 a0 + 25 20 09 0A 06 03 04 a0 + 25 20 09 0A 06 03 04 a0 + 25 1F 08 0A 06 03 04 a0]; + + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-display-timings { + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x31>; + timing@0{ + qcom,mdss-dsi-panel-phy-timings = + [24 1f 08 09 05 02 04 a0 + 24 1f 08 09 05 02 04 a0 + 24 1f 08 09 05 02 04 a0 + 24 1f 08 09 05 02 04 a0 + 24 1c 08 09 05 02 04 a0]; + + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_hx83112a_truly_video { + qcom,mdss-dsi-t-clk-post = <0x0e>; + qcom,mdss-dsi-t-clk-pre = <0x31>; + qcom,dsi-supported-dfps-list = <60 55 53 43>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = + "dfps_immediate_porch_mode_vfp"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>; + qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>; + qcom,mdss-dsi-panel-status-read-length = <4>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = + [24 1f 08 09 05 02 04 a0 + 24 1f 08 09 05 02 04 a0 + 24 1f 08 09 05 02 04 a0 + 24 1f 08 09 05 02 04 a0 + 24 1c 08 09 05 02 04 a0]; + + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt36672_truly_video { + qcom,mdss-dsi-t-clk-post = <0x0D>; + qcom,mdss-dsi-t-clk-pre = <0x30>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = + [24 1F 08 09 05 02 04 a0 + 24 1F 08 09 05 02 04 a0 + 24 1F 08 09 05 02 04 a0 + 24 1F 08 09 05 02 04 a0 + 24 1B 08 09 05 02 04 a0]; + + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-sde-pll.dtsi b/arch/arm/boot/dts/qcom/trinket-sde-pll.dtsi new file mode 100644 index 000000000000..701bb570f20e --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-sde-pll.dtsi @@ -0,0 +1,85 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + mdss_dsi0_pll: qcom,mdss_dsi_pll@5e94400 { + compatible = "qcom,mdss_dsi_pll_14nm"; + label = "MDSS DSI 0 PLL"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0x5e94400 0x588>, + <0x5f03000 0x8>, + <0x5e94200 0x100>; + reg-names = "pll_base", "gdsc_base", + "dynamic_pll_base"; + clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + clock-rate = <0>; + memory-region = <&dfps_data_memory>; + gdsc-supply = <&mdss_core_gdsc>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dp_pll: qcom,mdss_dp_pll@1616000 { + status = "disabled"; + compatible = "qcom,mdss_dp_pll_14nm"; + label = "MDSS DP PLL"; + cell-index = <0>; + #clock-cells = <1>; + + reg = <0x01616c00 0x1c4>, + <0x01616000 0x17c>, + <0x01616400 0x10c>, + <0x01616800 0x10c>, + <0x05f03000 0xc>; + reg-names = "pll_base", "phy_base", "ln_tx0_base", + "ln_tx1_base", "gdsc_base"; + + clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_rpmcc CXO_SMD_OTG_CLK>, + <&clock_gcc GCC_AHB2PHY_USB_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names = "iface_clk", + "ref_clk_src", + "cfg_ahb_clk", + "gcc_iface", "ref_clk"; + clock-rate = <0>; + + gdsc-supply = <&mdss_core_gdsc>; + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-sde.dtsi b/arch/arm/boot/dts/qcom/trinket-sde.dtsi new file mode 100644 index 000000000000..7419634f0b0d --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-sde.dtsi @@ -0,0 +1,563 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@5e00000 { + compatible = "qcom,sde-kms"; + reg = <0x5e00000 0x84208>, + <0x5eb0000 0x2008>, + <0x5eac000 0x214>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys"; + + clocks = + <&clock_gcc GCC_DISP_AHB_CLK>, + <&clock_gcc GCC_DISP_HF_AXI_CLK>, + <&clock_gcc GCC_DISP_THROTTLE_CORE_CLK>, + <&clock_gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, + <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "throttle_clk", "div_clk", + "iface_clk", "core_clk", "vsync_clk", + "lut_clk", "rot_clk"; + clock-rate = <0 0 0 0 0 256000000 19200000 192000000>; + clock-max-rate = <0 0 0 0 0 307000000 19200000 307000000>; + qcom,dss-cx-ipeak = <&cx_ipeak_lm 1>; + + sde-vdd-supply = <&mdss_core_gdsc>; + + /* interrupt config */ + interrupts = <0 186 0>; + interrupt-controller; + #interrupt-cells = <1>; + iommus = <&apps_smmu 0x400 0x0>; + + #address-cells = <1>; + #size-cells = <0>; + + #power-domain-cells = <0>; + + #list-cells = <1>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x45c>; + + qcom,sde-ctl-off = <0x2000 0x2200 0x2400 + 0x2600 0x2800 0x2a00>; + qcom,sde-ctl-size = <0x1e0>; + qcom,sde-ctl-display-pref = "primary", "none", "none", + "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x0 + 0x0 0x0 0x0>; + qcom,sde-mixer-size = <0x320>; + qcom,sde-mixer-display-pref = "primary", "none", "none", + "none", "none", "none"; + + qcom,sde-mixer-cwb-pref = "none", "cwb", "none", + "none", "none", "none"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x80>; + qcom,sde-dspp-off = <0x55000>; + qcom,sde-dspp-size = <0x1800>; + + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x3b8 24>; + + qcom,sde-intf-off = <0x6b000 0x6b800>; + qcom,sde-intf-size = <0x2b8>; + qcom,sde-intf-type = "dp", "dsi"; + + qcom,sde-pp-off = <0x71000 0x71800>; + qcom,sde-pp-slave = <0x0 0x0>; + qcom,sde-pp-size = <0xd4>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x224>; + + + qcom,sde-qdss-off = <0x81a00>; + + qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 0x30e0>; + qcom,sde-dither-version = <0x00010000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "dma", "dma"; + + qcom,sde-sspp-off = <0x5000 0x25000 0x27000>; + qcom,sde-sspp-src-size = <0x1f0>; + + qcom,sde-sspp-xin-id = <0 1 5>; + qcom,sde-sspp-excl-rect = <1 1 1>; + qcom,sde-sspp-smart-dma-priority = <3 1 2>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 0 0 0 0>; + + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-max-per-pipe-bw-kbps = <4500000 4500000 4500000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x2ac 0>, <0x2ac 8>, <0x2b4 8>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-type = "qseedv3lite"; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <2160>; + qcom,sde-wb-linewidth = <2160>; + qcom,sde-mixer-blendstages = <0x5>; + qcom,sde-highest-bank-bit = <0x1>; + qcom,sde-ubwc-version = <0x100>; + qcom,sde-ubwc-swizzle = <1>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + + qcom,sde-has-dim-layer; + qcom,sde-has-idle-pc; + + qcom,sde-max-bw-low-kbps = <4100000>; + qcom,sde-max-bw-high-kbps = <4100000>; + qcom,sde-min-core-ib-kbps = <2400000>; + qcom,sde-min-llcc-ib-kbps = <800000>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1040>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; + + /* macrotile & macrotile-qseed has the same configs */ + qcom,sde-danger-lut = <0x0000000f 0x0000ffff + 0x00000000 0x00000000 0x0000ffff>; + + qcom,sde-safe-lut-linear = <0 0xfff8>; + qcom,sde-safe-lut-macrotile = <0 0xf000>; + /* same as safe-lut-macrotile */ + qcom,sde-safe-lut-macrotile-qseed = <0 0xf000>; + qcom,sde-safe-lut-nrt = <0 0xffff>; + qcom,sde-safe-lut-cwb = <0 0xffff>; + + qcom,sde-qos-lut-linear = <0 0x00112222 0x22223357>; + qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>; + qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>; + qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>; + qcom,sde-qos-lut-cwb = <0 0x75300000 0x00000000>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + + qcom,sde-reg-dma-off = <0>; + qcom,sde-reg-dma-version = <0x00010001>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + + qcom,sde-secure-sid-mask = <0x0000401>; + qcom,sde-num-mnoc-ports = <1>; + qcom,sde-axi-bus-width = <16>; + + qcom,sde-sspp-vig-blocks { + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xa0>; + qcom,sde-vig-inverse-pma; + }; + + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00030001>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone= <0x900 0x00010007>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "sde-vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x401 0x0>; + }; + + /* data and reg bus scale settings */ + qcom,sde-data-bus { + qcom,msm-bus,name = "mdss_sde"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 4800000>, + <22 512 0 4800000>; + }; + + qcom,sde-reg-bus { + qcom,msm-bus,name = "mdss_reg"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 700 0 0>, + <1 700 0 76800>, + <1 700 0 150000>, + <1 700 0 300000>; + }; + }; + + mdss_rotator: qcom,mdss_rotator@5e00000 { + compatible = "qcom,sde_rotator"; + reg = <0x5e00000 0xac000>, + <0x5eb0000 0x2008>; + reg-names = "mdp_phys", + "rot_vbif_phys"; + + #list-cells = <1>; + + qcom,mdss-rot-mode = <1>; + qcom,mdss-highest-bank-bit = <0x1>; + qcom,sde-ubwc-malsize = <0x1>; + qcom,sde-ubwc_swizzle = <0x1>; + + /* Bus Scale Settings */ + qcom,msm-bus,name = "mdss_rotator"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 6400000>, + <22 512 0 6400000>; + + rot-vdd-supply = <&mdss_core_gdsc>; + qcom,supply-names = "rot-vdd"; + + clocks = + <&clock_gcc GCC_DISP_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, + <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; + clock-names = "gcc_iface", + "iface_clk", "rot_clk"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <2 0>; + + power-domains = <&mdss_mdp>; + + /*Offline rotator RT setting */ + qcom,mdss-rot-parent = <&mdss_mdp 0>; + qcom,mdss-rot-xin-id = <10 11>; + + /* Offline rotator QoS setting */ + qcom,mdss-rot-vbif-qos-setting = <3 3 4 4 5 5 6 6>; + qcom,mdss-rot-cdp-setting = <1 1>; + qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>; + qcom,mdss-rot-danger-lut = <0x0 0x0>; + qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>; + + qcom,mdss-default-ot-rd-limit = <32>; + qcom,mdss-default-ot-wr-limit = <32>; + + qcom,mdss-sbuf-headroom = <20>; + + /* reg bus scale settings */ + rot_reg: qcom,rot-reg-bus { + qcom,msm-bus,name = "mdss_rot_reg"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 700 0 0>, + <1 700 0 76800>; + }; + + smmu_rot_unsec: qcom,smmu_rot_unsec_cb { + compatible = "qcom,smmu_sde_rot_unsec"; + iommus = <&apps_smmu 0x402 0x0>; + }; + + smmu_rot_sec: qcom,smmu_rot_sec_cb { + compatible = "qcom,smmu_sde_rot_sec"; + iommus = <&apps_smmu 0x403 0x0>; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@5e94000 { + compatible = "qcom,dsi-ctrl-hw-v2.3"; + label = "dsi-ctrl-0"; + cell-index = <0>; + reg = <0x5e94000 0x400>, + <0x5f08000 0x4>; + reg-names = "dsi_ctrl", "disp_cc_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + vdda-1p2-supply = <&L18A>; + clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", + "esc_clk"; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1232000>; + qcom,supply-max-voltage = <1232000>; + qcom,supply-enable-load = <21800>; + qcom,supply-disable-load = <0>; + }; + }; + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@5e94400 { + compatible = "qcom,dsi-phy-v2.0"; + label = "dsi-phy-0"; + cell-index = <0>; + reg = <0x5e94400 0x588>, + <0x5e01400 0x100>, + <0x5e94200 0x100>; + reg-names = "dsi_phy", "phy_clamp_base", + "dyn_refresh_base"; + vdda-0p9-supply = <&VDD_MX_LEVEL>; + qcom,platform-strength-ctrl = [ff 06 + ff 06 + ff 06 + ff 06 + ff 00]; + qcom,platform-lane-config = [00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 8f]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,panel-allow-phy-poweroff; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-off-min-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + sde_dp: qcom,dp_display@0{ + status = "disabled"; + cell-index = <0>; + compatible = "qcom,dp-display"; + + vdda-1p8-supply = <&pm6125_l10>; + vdda-0p9-supply = <&pm6125_l7>; + vdda-3p1-supply = <&pm6125_l15>; + hpd-pwr-supply = <&pm6125_l9>; + + reg = <0x05e90000 0xf4>, + <0x05e90200 0xc0>, + <0x05e90400 0x600>, + <0x05e90a00 0x98>, + <0x01616000 0x17c>, + <0x01616400 0x10c>, + <0x01616800 0x10c>, + <0x05f0212c 0x8>, + <0x01b40000 0x7000>, + <0x01616c30 0x10>, + <0x05ee1000 0x2c>, + <0x003cb248 0x4>; + reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", + "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_pixel_mn", "qfprom_physical", "dp_pll", + "hdcp_physical", "dp_tcsr"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&clock_gcc GCC_AHB2PHY_USB_CLK>, + <&clock_rpmcc CXO_SMD_OTG_CLK>, + <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&mdss_dp_pll DP_PHY_PLL_VCO_DIV_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + + clock-names = "core_aux_clk", "core_usb_ahb_clk", + "core_usb_ref_clk_src", + "core_usb_ref_clk", + "core_usb_pipe_clk", "link_clk", "link_iface_clk", + "crypto_clk", "pixel_clk_rcg", "pixel_parent", + "strm0_pixel_clk"; + + qcom,phy-version = <0x200>; + qcom,aux-cfg0-settings = [20 00]; + qcom,aux-cfg1-settings = [24 13 23 1d]; + qcom,aux-cfg2-settings = [28 24]; + qcom,aux-cfg3-settings = [2c 00]; + qcom,aux-cfg4-settings = [30 0a]; + qcom,aux-cfg5-settings = [34 26]; + qcom,aux-cfg6-settings = [38 0a]; + qcom,aux-cfg7-settings = [3c 03]; + qcom,aux-cfg8-settings = [40 bb]; + qcom,aux-cfg9-settings = [44 03]; + + qcom,logical2physical-lane-map = [00 01 02 03]; + + qcom,max-lclk-frequency-khz = <540000>; + qcom,max-pclk-frequency-khz = <200000>; + + qcom,ext-disp = <&ext_disp>; + + qcom,usbplug-cc-gpio = <&tlmm 102 0>; + + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep", + "mdss_dp_hpd_active", "mdss_dp_hpd_tlmm", + "mdss_dp_hpd_ctrl"; + pinctrl-0 = <&sde_dp_usbplug_cc_active>; + pinctrl-1 = <&sde_dp_usbplug_cc_suspend>; + pinctrl-2 = <&sde_dp_hotplug_tlmm>; + pinctrl-3 = <&sde_dp_hotplug_tlmm>; + pinctrl-4 = <&sde_dp_hotplug_ctrl>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p8"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1896000>; + qcom,supply-enable-load = <20000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <872000>; + qcom,supply-max-voltage = <976000>; + qcom,supply-enable-load = <50000>; + qcom,supply-disable-load = <0>; + }; + qcom,phy-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdda-3p1"; + qcom,supply-min-voltage = <3104000>; + qcom,supply-max-voltage = <3232000>; + qcom,supply-enable-load = <5250>; + qcom,supply-disable-load = <0>; + }; + qcom,phy-supply-entry@2 { + reg = <2>; + qcom,supply-name = "hpd-pwr"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1896000>; + qcom,supply-enable-load = <10000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-stub-regulator.dtsi b/arch/arm/boot/dts/qcom/trinket-stub-regulator.dtsi new file mode 100644 index 000000000000..4a8f863c22c2 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-stub-regulator.dtsi @@ -0,0 +1,280 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +/* Stub regulators */ + +/ { + /* PM6125 S3/S4 - VDD_CX supply */ + VDD_CX_LEVEL: + S3A_LEVEL: pm6125_s3_level: regulator-s3-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_s3_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + }; + + VDD_CX_FLOOR_LEVEL: + S3A_FLOOR_LEVEL: pm6125_s3_floor_level: regulator-s3-floor-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_s3_floor_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + }; + + VDD_CX_LEVEL_AO: + S3A_LEVEL_AO: pm6125_s3_level_ao: regulator-s3-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_s3_level_ao"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + }; + + /* PM6125 S5 - VDD_MX/WCSS_MX supply */ + VDD_MX_LEVEL: + S5A_LEVEL: pm6125_s5_level: regulator-s5-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_s5_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + }; + + VDD_MX_FLOOR_LEVEL: + S5A_FLOOR_LEVEL: pm6125_s5_floor_level: regulator-s5-floor-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_s5_floor_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + }; + + VDD_MX_LEVEL_AO: + S5A_LEVEL_AO: pm6125_s5_level_ao: regulator-s5-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_s5_level_ao"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + }; + + L1A: pm6125_l1: regulator-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l1"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1178000>; + regulator-max-microvolt = <1252000>; + }; + + L2A: pm6125_l2: regulator-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l2"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1050000>; + }; + + L3A: pm6125_l3: regulator-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l3"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <970000>; + regulator-max-microvolt = <1060000>; + }; + + L4A: pm6125_l4: regulator-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l4"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <970000>; + }; + + L5A: pm6125_l5: regulator-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l5"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3100000>; + }; + + L6A: pm6125_l6: regulator-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l6"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <650000>; + }; + + L7A: pm6125_l7: regulator-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l7"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + + L8A: pm6125_l8_level: regulator-l8-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l8"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + }; + + L9A: pm6125_l9: regulator-l9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l9"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + L10A: pm6125_l10: regulator-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l10"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + }; + + L11A: pm6125_l11: regulator-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l11"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1950000>; + }; + + L12A: pm6125_l12: regulator-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l12"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + + L13A: pm6125_l13: regulator-l13 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l13"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1721000>; + regulator-max-microvolt = <1850000>; + }; + + L14A: pm6125_l14: regulator-l14 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l14"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + + L15A: pm6125_l15: regulator-l15 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l15"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <2930000>; + regulator-max-microvolt = <3230000>; + }; + + L16A: pm6125_l16: regulator-l16 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l16"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + }; + + L17A: pm6125_l17: regulator-l17 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l17"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1350000>; + }; + + L18A: pm6125_l18: regulator-l18 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l18"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1312500>; + }; + + L19A: pm6125_l19: regulator-l19 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l19"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + }; + + L20A: pm6125_l20: regulator-l20 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l20"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + }; + + L21A: pm6125_l21: regulator-l21 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l21"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3600000>; + }; + + L22A: pm6125_l22: regulator-l22 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l22"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3300000>; + }; + + L23A: pm6125_l23: regulator-l23 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l23"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + }; + + L24A: pm6125_l24: regulator-l24 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6125_l24"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3590000>; + }; + +}; + diff --git a/arch/arm/boot/dts/qcom/trinket-tasha-codec-audio-overlay.dtsi b/arch/arm/boot/dts/qcom/trinket-tasha-codec-audio-overlay.dtsi new file mode 100644 index 000000000000..e0a4420cf8e9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-tasha-codec-audio-overlay.dtsi @@ -0,0 +1,96 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "trinket-audio-overlay.dtsi" + +&bolero { + status = "disabled"; +}; + +&wcd937x_codec { + status = "disabled"; +}; + +&wcd937x_rst_gpio{ + status = "disabled"; +}; + +&cdc_dmic01_gpios { + status = "disabled"; +}; + +&cdc_dmic23_gpios { + status = "disabled"; +}; + +&clock_audio_wsa_1 { + status = "disabled"; +}; + +&clock_audio_wsa_2 { + status = "disabled"; +}; + +&clock_audio_va { + status = "disabled"; +}; + +&clock_audio_rx_1 { + status = "disabled"; +}; + +&clock_audio_rx_2 { + status = "disabled"; +}; + +&clock_audio_tx_1 { + status = "disabled"; +}; + +&clock_audio_tx_2 { + status = "disabled"; +}; + +&wsa_spkr_en1 { + status = "disabled"; +}; + +&rx_swr_gpios { + status = "disabled"; +}; + +&slim_aud { + status = "okay"; +}; + +&dai_slim { + status = "okay"; +}; + +&wcd9335 { + status = "okay"; +}; + +&clock_audio { + status = "okay"; +}; + +&clock_audio_native { + status = "okay"; +}; + +&wcd_rst_gpio { + status = "okay"; +}; + +&wcd9xxx_intc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-tasha-codec.dtsi b/arch/arm/boot/dts/qcom/trinket-tasha-codec.dtsi new file mode 100644 index 000000000000..94c4bba291fb --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-tasha-codec.dtsi @@ -0,0 +1,170 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "trinket-wcd.dtsi" + +&soc { + cpe: qcom,msm-cpe-lsm { + compatible = "qcom,msm-cpe-lsm"; + }; + + cpe3: qcom,msm-cpe-lsm@3 { + compatible = "qcom,msm-cpe-lsm"; + qcom,msm-cpe-lsm-id = <3>; + }; +}; + +&sm6150_snd { + qcom,model = "trinket-tashalite-snd-card"; + qcom,tasha_codec = <1>; + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&compr>, + <&pcm_noirq>, <&cpe>, <&cpe3>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", + "msm-compr-dsp", "msm-pcm-dsp-noirq", + "msm-cpe-lsm", "msm-cpe-lsm.3"; + asoc-cpu = <&dai_dp>, <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, <&dai_mi2s4>, + <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, + <&dai_tert_auxpcm>, <&dai_quat_auxpcm>, + <&dai_quin_auxpcm>, + <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, + <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, + <&sb_4_rx>, <&sb_4_tx>, <&sb_5_rx>, <&sb_5_tx>, + <&sb_6_rx>, <&sb_7_rx>, <&sb_7_tx>, + <&sb_8_rx>, <&sb_8_tx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, + <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, + <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>; + asoc-cpu-names = "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", + "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2", + "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4", + "msm-dai-q6-auxpcm.5", + "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", + "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", + "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", + "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", + "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", + "msm-dai-q6-dev.16394", "msm-dai-q6-dev.16395", + "msm-dai-q6-dev.16396", + "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", + "msm-dai-q6-dev.16400", "msm-dai-q6-dev.16401", + "msm-dai-q6-dev.224", "msm-dai-q6-dev.225", + "msm-dai-q6-dev.241", "msm-dai-q6-dev.240", + "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", + "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", + "msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36929"; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>; + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "hifi amp", "LINEOUT1", + "hifi amp", "LINEOUT2", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC3", "MIC BIAS2", + "MIC BIAS2", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2", + "MIC BIAS2", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS3", + "MIC BIAS3", "Handset Mic", + "DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "DMIC4", "MIC BIAS4", + "MIC BIAS4", "Digital Mic4", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT"; + + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,msm-mclk-freq = <9600000>; + asoc-codec = <&stub_codec>, <&ext_disp_audio_codec>; + asoc-codec-names = "msm-stub-codec.1", "msm-ext-disp-audio-codec-rx"; + qcom,wsa-max-devs = <2>; + qcom,wsa-devs = <&wsa881x_70212>, <&wsa881x_70211>, + <&wsa881x_70214>, <&wsa881x_70213>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", + "SpkrLeft", "SpkrRight"; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&wcd9335>, + <&q6core>; +}; + +&slim_aud { + tasha_codec { + swr3: swr_master { + compatible = "qcom,swr-mstr"; + #address-cells = <2>; + #size-cells = <0>; + qcom,swr-num-ports = <8>; + qcom,swr-port-mapping = <1 SPKR_L 0x1>, + <2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>, + <4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>, + <6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>, + <8 SPKR_R_VI 0x3>; + qcom,swr_master_id = <1>; + wsa881x_70211: wsa881x@70211 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170211>; + qcom,spkr-sd-n-node = <&wsa_spk_wcd_sd1>; + }; + + wsa881x_70212: wsa881x@70212 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170212>; + qcom,spkr-sd-n-node = <&wsa_spk_wcd_sd2>; + }; + + wsa881x_70213: wsa881x@70213 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170213>; + qcom,spkr-sd-n-node = <&wsa_spk_wcd_sd1>; + }; + + wsa881x_70214: wsa881x@70214 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170214>; + qcom,spkr-sd-n-node = <&wsa_spk_wcd_sd2>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-thermal-overlay.dtsi b/arch/arm/boot/dts/qcom/trinket-thermal-overlay.dtsi new file mode 100644 index 000000000000..cc055b4a542d --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-thermal-overlay.dtsi @@ -0,0 +1,449 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include + +&thermal_zones { + pmi632-tz { + cooling-maps { + trip0_bat { + trip = <&pmi632_trip0>; + cooling-device = + <&pmi632_charger (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip1_bat { + trip = <&pmi632_trip1>; + cooling-device = + <&pmi632_charger THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pm6125-tz { + cooling-maps { + trip0_cpu0 { + trip = <&pm6125_trip0>; + cooling-device = + <&CPU0 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu1 { + trip = <&pm6125_trip0>; + cooling-device = + <&CPU1 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu2 { + trip = <&pm6125_trip0>; + cooling-device = + <&CPU2 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu3 { + trip = <&pm6125_trip0>; + cooling-device = + <&CPU3 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu4 { + trip = <&pm6125_trip0>; + cooling-device = + <&CPU4 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu5 { + trip = <&pm6125_trip0>; + cooling-device = + <&CPU5 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu6 { + trip = <&pm6125_trip0>; + cooling-device = + <&CPU6 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip0_cpu7 { + trip = <&pm6125_trip0>; + cooling-device = + <&CPU7 (THERMAL_MAX_LIMIT-1) + (THERMAL_MAX_LIMIT-1)>; + }; + trip1_cpu1 { + trip = <&pm6125_trip1>; + cooling-device = + <&CPU1 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu2 { + trip = <&pm6125_trip1>; + cooling-device = + <&CPU2 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu3 { + trip = <&pm6125_trip1>; + cooling-device = + <&CPU3 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu4 { + trip = <&pm6125_trip1>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu5 { + trip = <&pm6125_trip1>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu6 { + trip = <&pm6125_trip1>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + trip1_cpu7 { + trip = <&pm6125_trip1>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pmi632-vbat-lvl0 { + cooling-maps { + vbat_cpu0 { + trip = <&pmi632_vbat_lvl0>; + cooling-device = + <&CPU0 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + vbat_cpu1 { + trip = <&pmi632_vbat_lvl0>; + cooling-device = + <&CPU1 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + vbat_cpu2 { + trip = <&pmi632_vbat_lvl0>; + cooling-device = + <&CPU2 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + vbat_cpu3 { + trip = <&pmi632_vbat_lvl0>; + cooling-device = + <&CPU3 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + vbat_cpu4 { + trip = <&pmi632_vbat_lvl0>; + cooling-device = + <&CPU4 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + vbat_cpu5 { + trip = <&pmi632_vbat_lvl0>; + cooling-device = + <&CPU5 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + vbat_cpu6 { + trip = <&pmi632_vbat_lvl0>; + cooling-device = + <&CPU6 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + vbat_cpu7 { + trip = <&pmi632_vbat_lvl0>; + cooling-device = + <&CPU7 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + }; + }; + + pmi632-vbat-lvl1 { + cooling-maps { + vbat_cpu0 { + trip = <&pmi632_vbat_lvl1>; + cooling-device = + <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + vbat_cpu1 { + trip = <&pmi632_vbat_lvl1>; + cooling-device = + <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + vbat_cpu2 { + trip = <&pmi632_vbat_lvl1>; + cooling-device = + <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + vbat_cpu3 { + trip = <&pmi632_vbat_lvl1>; + cooling-device = + <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + vbat_cpu4 { + trip = <&pmi632_vbat_lvl1>; + cooling-device = + <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + vbat_cpu5 { + trip = <&pmi632_vbat_lvl1>; + cooling-device = + <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + vbat_cpu6 { + trip = <&pmi632_vbat_lvl1>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + vbat_cpu7 { + trip = <&pmi632_vbat_lvl1>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pmi632-vbat-lvl2 { + cooling-maps { + vbat_cpu0 { + trip = <&pmi632_vbat_lvl2>; + cooling-device = + <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + vbat_cpu1 { + trip = <&pmi632_vbat_lvl2>; + cooling-device = + <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + vbat_cpu2 { + trip = <&pmi632_vbat_lvl2>; + cooling-device = + <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + vbat_cpu3 { + trip = <&pmi632_vbat_lvl2>; + cooling-device = + <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + vbat_cpu4 { + trip = <&pmi632_vbat_lvl2>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + vbat_cpu5 { + trip = <&pmi632_vbat_lvl2>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + vbat_cpu6 { + trip = <&pmi632_vbat_lvl2>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + vbat_cpu7 { + trip = <&pmi632_vbat_lvl2>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pmi632-ibat-lvl0 { + cooling-maps { + ibat_cpu0 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU0 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + ibat_cpu1 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU1 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + ibat_cpu2 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU2 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + ibat_cpu3 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU3 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + ibat_cpu4 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU4 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + ibat_cpu5 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU5 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + ibat_cpu6 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU6 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + ibat_cpu7 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU7 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + }; + }; + + pmi632-ibat-lvl1 { + cooling-maps { + ibat_cpu0 { + trip = <&pmi632_ibat_lvl1>; + cooling-device = + <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + ibat_cpu1 { + trip = <&pmi632_ibat_lvl1>; + cooling-device = + <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + ibat_cpu2 { + trip = <&pmi632_ibat_lvl1>; + cooling-device = + <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + ibat_cpu3 { + trip = <&pmi632_ibat_lvl1>; + cooling-device = + <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + ibat_cpu4 { + trip = <&pmi632_ibat_lvl1>; + cooling-device = + <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + ibat_cpu5 { + trip = <&pmi632_ibat_lvl1>; + cooling-device = + <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + ibat_cpu6 { + trip = <&pmi632_ibat_lvl1>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + ibat_cpu7 { + trip = <&pmi632_ibat_lvl1>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + soc { + cooling-maps { + soc_cpu0 { + trip = <&pmi632_low_soc>; + cooling-device = + <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + soc_cpu1 { + trip = <&pmi632_low_soc>; + cooling-device = + <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + soc_cpu2 { + trip = <&pmi632_low_soc>; + cooling-device = + <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + soc_cpu3 { + trip = <&pmi632_low_soc>; + cooling-device = + <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + soc_cpu4 { + trip = <&pmi632_low_soc>; + cooling-device = + <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + soc_cpu5 { + trip = <&pmi632_low_soc>; + cooling-device = + <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + soc_cpu6 { + trip = <&pmi632_low_soc>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + soc_cpu7 { + trip = <&pmi632_low_soc>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; +}; + +&mdss_mdp { + #cooling-cells = <2>; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-thermal.dtsi b/arch/arm/boot/dts/qcom/trinket-thermal.dtsi new file mode 100644 index 000000000000..bd964c615005 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-thermal.dtsi @@ -0,0 +1,2015 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&clock_cpucc { + #address-cells = <1>; + #size-cells = <1>; + lmh_dcvs0: qcom,limits-dcvs@f521000 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + qcom,affinity = <0>; + reg = <0xf550800 0x1000>, + <0xf521000 0x1000>; + qcom,plat-mitigation-disable; + #thermal-sensor-cells = <0>; + }; + + lmh_dcvs1: qcom,limits-dcvs@f523000 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + qcom,affinity = <1>; + reg = <0xf550800 0x1000>, + <0xf523000 0x1000>; + qcom,plat-mitigation-disable; + #thermal-sensor-cells = <0>; + }; +}; + +&soc { + qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + + modem { + qcom,instance-id = <0x0>; + + modem_pa: modem_pa { + qcom,qmi-dev-name = "pa"; + #cooling-cells = <2>; + }; + + modem_proc: modem_proc { + qcom,qmi-dev-name = "modem"; + #cooling-cells = <2>; + }; + + modem_current: modem_current { + qcom,qmi-dev-name = "modem_current"; + #cooling-cells = <2>; + }; + + modem_skin: modem_skin { + qcom,qmi-dev-name = "modem_skin"; + #cooling-cells = <2>; + }; + + modem_vdd: modem_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + + adsp { + qcom,instance-id = <0x1>; + + adsp_vdd: adsp_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + + cdsp { + qcom,instance-id = <0x43>; + + cdsp_vdd: cdsp_vdd { + qcom,qmi-dev-name = "cpuv_restriction_cold"; + #cooling-cells = <2>; + }; + }; + }; + + cxip_cdev: cxip-cdev@3ed000 { + compatible = "qcom,cxip-lm-cooling-device"; + reg = <0x3ed000 0xc00c>; + qcom,thermal-client-offset = <0x9000>; + /* 2nd and 3rd offsets to bypass VICTIM1 */ + qcom,bypass-client-list = <0xa004 0xc004 0xc008>; + #cooling-cells = <2>; + }; +}; + +&thermal_zones { + rf-pa0-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet-therm-adc { + polling-delay-passive = <0>; + polling-delay = <5000>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm ADC_XO_THERM_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmi632_adc_tm ADC_GPIO1_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-therm-adc { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pmi632_adc_tm ADC_GPIO2_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + camera-ftherm-adc { + polling-delay-passive = <0>; + polling-delay = <5000>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm_iio ADC_GPIO1_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + emmc-ufs-therm-adc { + polling-delay-passive = <0>; + polling-delay = <5000>; + thermal-governor = "user_space"; + thermal-sensors = <&pm6125_adc_tm_iio ADC_GPIO3_PU2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + aoss0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 0>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cdsp-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 1>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + wlan-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 2>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 3>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + video-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 4>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 6>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 7>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 8>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 9>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 10>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 11>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu-1-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 12>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdm-core-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 13>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + display-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 14>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpu-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 15>; + wake-capable-sensor; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + reset-mon-1-cfg { + temperature = <110000>; + hysteresis = <5000>; + type = "passive"; + }; + reset-mon-2-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + lmh-dcvs-00 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&lmh_dcvs0>; + wake-capable-sensor; + + trips { + active-config { + temperature = <95000>; + hysteresis = <30000>; + type = "passive"; + }; + }; + }; + + gpu-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 15>; + wake-capable-sensor; + trips { + gpu_step_trip: gpu-trip { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + gpu_cx_mon: gpu-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + gpu_cdev { + trip = <&gpu_step_trip>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + gpu-cx-cdev0 { + trip = <&gpu_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + gpu-cx-cdev1 { + trip = <&gpu_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + gpu-cx-cdev2 { + trip = <&gpu_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + gpu-cx-cdev3 { + trip = <&gpu_cx_mon>; + cooling-device = <&msm_cdsp_rm 4 4>; + }; + }; + }; + + hepta-cpu-max-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + silver-trip { + temperature = <120000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + cpuss-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 7>; + wake-capable-sensor; + trips { + cpu5_7_config: cpu-5-7-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu5_cdev { + trip = <&cpu5_7_config>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + cpu7_cdev { + trip = <&cpu5_7_config>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpuss-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 8>; + wake-capable-sensor; + trips { + cpu4_6_config: cpu-4-6-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu4_cdev { + trip = <&cpu4_6_config>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + cpu6_cdev { + trip = <&cpu4_6_config>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpuss-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 6>; + wake-capable-sensor; + trips { + silv_cpus_config: silv-cpus-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&silv_cpus_config>; + cooling-device = + <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + cpu1_cdev { + trip = <&silv_cpus_config>; + cooling-device = + <&CPU1 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + cpu2_cdev { + trip = <&silv_cpus_config>; + cooling-device = + <&CPU2 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + cpu3_cdev { + trip = <&silv_cpus_config>; + cooling-device = + <&CPU3 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 9>; + wake-capable-sensor; + trips { + cpu4_config: cpu4-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu4_cdev { + trip = <&cpu4_config>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 10>; + wake-capable-sensor; + trips { + cpu5_config: cpu5-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu5_cdev { + trip = <&cpu5_config>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 11>; + wake-capable-sensor; + trips { + cpu6_config: cpu6-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu6_cdev { + trip = <&cpu6_config>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 12>; + wake-capable-sensor; + trips { + cpu7_config: cpu7-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + cooling-maps { + cpu7_cdev { + trip = <&cpu7_config>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + aoss0-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 0>; + wake-capable-sensor; + tracks-low; + trips { + aoss0_trip: aoss0-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&aoss0_trip>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu1_cdev { + trip = <&aoss0_trip>; + cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu2_cdev { + trip = <&aoss0_trip>; + cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu3_cdev { + trip = <&aoss0_trip>; + cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu4_cdev { + trip = <&aoss0_trip>; + cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu5_cdev { + trip = <&aoss0_trip>; + cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu6_cdev { + trip = <&aoss0_trip>; + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu7_cdev { + trip = <&aoss0_trip>; + cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cx_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&aoss0_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + cdsp-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 1>; + wake-capable-sensor; + tracks-low; + trips { + cdsp_trip: cdsp-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&cdsp_trip>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu1_cdev { + trip = <&cdsp_trip>; + cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu2_cdev { + trip = <&cdsp_trip>; + cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu3_cdev { + trip = <&cdsp_trip>; + cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu4_cdev { + trip = <&cdsp_trip>; + cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu5_cdev { + trip = <&cdsp_trip>; + cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu6_cdev { + trip = <&cdsp_trip>; + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu7_cdev { + trip = <&cdsp_trip>; + cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cx_vdd_cdev { + trip = <&cdsp_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&cdsp_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&cdsp_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&cdsp_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&cdsp_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + wlan-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 2>; + wake-capable-sensor; + tracks-low; + trips { + wlan_trip: wlan-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&wlan_trip>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu1_cdev { + trip = <&wlan_trip>; + cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu2_cdev { + trip = <&wlan_trip>; + cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu3_cdev { + trip = <&wlan_trip>; + cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu4_cdev { + trip = <&wlan_trip>; + cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu5_cdev { + trip = <&wlan_trip>; + cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu6_cdev { + trip = <&wlan_trip>; + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu7_cdev { + trip = <&wlan_trip>; + cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cx_vdd_cdev { + trip = <&wlan_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&wlan_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&wlan_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&wlan_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&wlan_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + camera-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 3>; + wake-capable-sensor; + tracks-low; + trips { + camera_trip: camera-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&camera_trip>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu1_cdev { + trip = <&camera_trip>; + cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu2_cdev { + trip = <&camera_trip>; + cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu3_cdev { + trip = <&camera_trip>; + cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu4_cdev { + trip = <&camera_trip>; + cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu5_cdev { + trip = <&camera_trip>; + cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu6_cdev { + trip = <&camera_trip>; + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu7_cdev { + trip = <&camera_trip>; + cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cx_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&camera_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + video-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 4>; + wake-capable-sensor; + tracks-low; + trips { + video_trip: video-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&video_trip>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu1_cdev { + trip = <&video_trip>; + cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu2_cdev { + trip = <&video_trip>; + cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu3_cdev { + trip = <&video_trip>; + cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu4_cdev { + trip = <&video_trip>; + cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu5_cdev { + trip = <&video_trip>; + cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu6_cdev { + trip = <&video_trip>; + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu7_cdev { + trip = <&video_trip>; + cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cx_vdd_cdev { + trip = <&video_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&video_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&video_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&video_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&video_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + cpu-1-0-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 9>; + wake-capable-sensor; + tracks-low; + trips { + cpu4_lowf_trip: cpu4-lowf-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&cpu4_lowf_trip>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu1_cdev { + trip = <&cpu4_lowf_trip>; + cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu2_cdev { + trip = <&cpu4_lowf_trip>; + cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu3_cdev { + trip = <&cpu4_lowf_trip>; + cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu4_cdev { + trip = <&cpu4_lowf_trip>; + cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu5_cdev { + trip = <&cpu4_lowf_trip>; + cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu6_cdev { + trip = <&cpu4_lowf_trip>; + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu7_cdev { + trip = <&cpu4_lowf_trip>; + cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cx_vdd_cdev { + trip = <&cpu4_lowf_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&cpu4_lowf_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&cpu4_lowf_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&cpu4_lowf_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&cpu4_lowf_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + cpuss-0-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 6>; + wake-capable-sensor; + tracks-low; + trips { + cpu0_lowf_trip: cpu0-lowf-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&cpu0_lowf_trip>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu1_cdev { + trip = <&cpu0_lowf_trip>; + cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu2_cdev { + trip = <&cpu0_lowf_trip>; + cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu3_cdev { + trip = <&cpu0_lowf_trip>; + cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu4_cdev { + trip = <&cpu0_lowf_trip>; + cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu5_cdev { + trip = <&cpu0_lowf_trip>; + cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu6_cdev { + trip = <&cpu0_lowf_trip>; + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu7_cdev { + trip = <&cpu0_lowf_trip>; + cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cx_vdd_cdev { + trip = <&cpu0_lowf_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&cpu0_lowf_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&cpu0_lowf_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&cpu0_lowf_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&cpu0_lowf_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + mdm-core-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 13>; + wake-capable-sensor; + tracks-low; + trips { + mdm_core_trip: mdm-core-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu1_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu2_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu3_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu4_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu5_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu6_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu7_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cx_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&mdm_core_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + display-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 14>; + wake-capable-sensor; + tracks-low; + trips { + display_trip: display-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&display_trip>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu1_cdev { + trip = <&display_trip>; + cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu2_cdev { + trip = <&display_trip>; + cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu3_cdev { + trip = <&display_trip>; + cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu4_cdev { + trip = <&display_trip>; + cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu5_cdev { + trip = <&display_trip>; + cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu6_cdev { + trip = <&display_trip>; + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu7_cdev { + trip = <&display_trip>; + cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cx_vdd_cdev { + trip = <&display_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&display_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&display_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&display_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&display_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + gpu-lowf { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "low_limits_floor"; + thermal-sensors = <&tsens0 15>; + wake-capable-sensor; + tracks-low; + trips { + gpu_trip: gpu-trip { + temperature = <5000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cpu0_cdev { + trip = <&gpu_trip>; + cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu1_cdev { + trip = <&gpu_trip>; + cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu2_cdev { + trip = <&gpu_trip>; + cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu3_cdev { + trip = <&gpu_trip>; + cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu4_cdev { + trip = <&gpu_trip>; + cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu5_cdev { + trip = <&gpu_trip>; + cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu6_cdev { + trip = <&gpu_trip>; + cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cpu7_cdev { + trip = <&gpu_trip>; + cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + cx_vdd_cdev { + trip = <&gpu_trip>; + cooling-device = <&cx_cdev 0 0>; + }; + mx_vdd_cdev { + trip = <&gpu_trip>; + cooling-device = <&mx_cdev 0 0>; + }; + modem_vdd_cdev { + trip = <&gpu_trip>; + cooling-device = <&modem_vdd 0 0>; + }; + adsp_vdd_cdev { + trip = <&gpu_trip>; + cooling-device = <&adsp_vdd 0 0>; + }; + cdsp_vdd_cdev { + trip = <&gpu_trip>; + cooling-device = <&cdsp_vdd 0 0>; + }; + }; + }; + + cdsp-step { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + cdsp_trip0: cdsp-trip0 { + temperature = <95000>; + hysteresis = <20000>; + type = "passive"; + }; + cdsp_trip1: cdsp-trip1 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + cdsp_cx_mon: cdsp-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + cxip-cdev { + trip = <&cdsp_trip0>; + cooling-device = <&cxip_cdev 1 1>; + }; + cdsp-cdev0 { + trip = <&cdsp_trip1>; + cooling-device = <&msm_cdsp_rm + THERMAL_NO_LIMIT 4>; + }; + cdsp-cx-cdev0 { + trip = <&cdsp_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + cdsp-cx-cdev1 { + trip = <&cdsp_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + cdsp-cx-cdev2 { + trip = <&cdsp_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + cdsp-cx-cdev3 { + trip = <&cdsp_cx_mon>; + cooling-device = <&msm_cdsp_rm 4 4>; + }; + }; + }; + + wlan-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 2>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + wlan_cx_mon: wlan-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + wlan-cx-cdev0 { + trip = <&wlan_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + wlan-cx-cdev1 { + trip = <&wlan_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + wlan-cx-cdev2 { + trip = <&wlan_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + wlan-cx-cdev3 { + trip = <&wlan_cx_mon>; + cooling-device = <&msm_cdsp_rm 4 4>; + }; + }; + }; + + camera-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + camera_cx_mon: camera-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + camera-cx-cdev0 { + trip = <&camera_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + camera-cx-cdev1 { + trip = <&camera_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + camera-cx-cdev2 { + trip = <&camera_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + camera-cx-cdev3 { + trip = <&camera_cx_mon>; + cooling-device = <&msm_cdsp_rm 4 4>; + }; + }; + }; + + video-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + video_cx_mon: video-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + video-cx-cdev0 { + trip = <&video_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + video-cx-cdev1 { + trip = <&video_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + video-cx-cdev2 { + trip = <&video_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + video-cx-cdev3 { + trip = <&video_cx_mon>; + cooling-device = <&msm_cdsp_rm 4 4>; + }; + }; + }; + + mdm-core-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + mdm_core_cx_mon: mdm-core-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + mdm-cx-cdev0 { + trip = <&mdm_core_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + mdm-cx-cdev1 { + trip = <&mdm_core_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + mdm-cx-cdev2 { + trip = <&mdm_core_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + mdm-cx-cdev3 { + trip = <&mdm_core_cx_mon>; + cooling-device = <&msm_cdsp_rm 4 4>; + }; + }; + }; + + display-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + thermal-governor = "step_wise"; + wake-capable-sensor; + trips { + dispaly_cx_mon: display-cx-mon { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + cooling-maps { + display-cx-cdev0 { + trip = <&dispaly_cx_mon>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + display-cx-cdev1 { + trip = <&dispaly_cx_mon>; + cooling-device = <&modem_proc 3 3>; + }; + display-cx-cdev2 { + trip = <&dispaly_cx_mon>; + cooling-device = <&modem_pa 3 3>; + }; + display-cx-cdev3 { + trip = <&dispaly_cx_mon>; + cooling-device = <&msm_cdsp_rm 4 4>; + }; + }; + }; + + quiet-therm-step { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6125_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; + trips { + batt_trip0: batt-trip0 { + temperature = <45000>; + hysteresis = <2000>; + type = "passive"; + }; + gold_trip: gold-trip { + temperature = <46000>; + hysteresis = <0>; + type = "passive"; + }; + modem_trip0: modem-trip0 { + temperature = <46000>; + hysteresis = <4000>; + type = "passive"; + }; + batt_trip1: batt-trip1 { + temperature = <47000>; + hysteresis = <2000>; + type = "passive"; + }; + modem_trip1: modem-trip1 { + temperature = <48000>; + hysteresis = <2000>; + type = "passive"; + }; + skin_gpu_trip: skin-gpu-trip { + temperature = <48000>; + hysteresis = <0>; + type = "passive"; + }; + batt_trip2: batt-trip2 { + temperature = <49000>; + hysteresis = <2000>; + type = "passive"; + }; + modem_trip2: modem-trip2 { + temperature = <50000>; + hysteresis = <2000>; + type = "passive"; + }; + batt_trip3: batt-trip3 { + temperature = <51000>; + hysteresis = <2000>; + type = "passive"; + }; + silver_trip: silver-trip { + temperature = <52000>; + hysteresis = <0>; + type = "passive"; + }; + modem_trip3: modem-trip3 { + temperature = <52000>; + hysteresis = <2000>; + type = "passive"; + }; + cx_emer_trip: cx-emer-trip { + temperature = <52000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + cooling-maps { + skin_cpu4 { + trip = <&gold_trip>; + cooling-device = + /* throttle from fmax to 1401600KHz */ + <&CPU4 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-5)>; + }; + skin_cpu5 { + trip = <&gold_trip>; + cooling-device = <&CPU5 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-5)>; + }; + skin_cpu6 { + trip = <&gold_trip>; + cooling-device = <&CPU6 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-5)>; + }; + skin_cpu7 { + trip = <&gold_trip>; + cooling-device = <&CPU7 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-5)>; + }; + skin_cpu0 { + trip = <&silver_trip>; + /* throttle from fmax to 1420800KHz */ + cooling-device = <&CPU0 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-6)>; + }; + skin_cpu1 { + trip = <&silver_trip>; + cooling-device = <&CPU1 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-6)>; + }; + skin_cpu2 { + trip = <&silver_trip>; + cooling-device = <&CPU2 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-6)>; + }; + skin_cpu3 { + trip = <&silver_trip>; + cooling-device = <&CPU3 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-6)>; + }; + skin_gpu { + trip = <&skin_gpu_trip>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-3)>; + }; + modem_lvl1 { + trip = <&modem_trip1>; + cooling-device = <&modem_pa 1 1>; + }; + modem_lvl2 { + trip = <&modem_trip2>; + cooling-device = <&modem_pa 2 2>; + }; + modem_lvl3 { + trip = <&modem_trip3>; + cooling-device = <&modem_pa 3 3>; + }; + modem_proc_lvl1 { + trip = <&modem_trip0>; + cooling-device = <&modem_proc 1 1>; + }; + modem_proc_lvl3 { + trip = <&modem_trip3>; + cooling-device = <&modem_proc 3 3>; + }; + battery_lvl0 { + trip = <&batt_trip0>; + cooling-device = <&pmi632_charger 1 1>; + }; + battery_lvl1 { + trip = <&batt_trip1>; + cooling-device = <&pmi632_charger 2 2>; + }; + battery_lvl2 { + trip = <&batt_trip2>; + cooling-device = <&pmi632_charger 4 4>; + }; + battery_lvl3 { + trip = <&batt_trip3>; + cooling-device = <&pmi632_charger 5 5>; + }; + cx_skin_gpu { + trip = <&cx_emer_trip>; + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + cx-skin-cdsp { + trip = <&cx_emer_trip>; + cooling-device = <&msm_cdsp_rm 4 4>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-usb.dtsi b/arch/arm/boot/dts/qcom/trinket-usb.dtsi new file mode 100644 index 000000000000..5a7c14dd4bb8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-usb.dtsi @@ -0,0 +1,324 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&soc { + /* Primary USB port related controller */ + usb0: ssusb@4e00000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x4e00000 0x100000>; + reg-names = "core_base"; + + iommus = <&apps_smmu 0x100 0x0>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <0 302 0>, <0 422 0>, <0 260 0>; + interrupt-names = "pwr_event_irq", "ss_phy_irq", "hs_phy_irq"; + + USB3_GDSC-supply = <&usb30_prim_gdsc>; + dpdm-supply = <&qusb_phy0>; + clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>, + <&clock_gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "xo", "sleep_clk", "utmi_clk"; + + resets = <&clock_gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <133333333>; + qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + + qcom,msm-bus,name = "usb0"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <3>; + qcom,msm-bus,vectors-KBps = + /* suspend vote */ + , + , + , + + /* nominal vote */ + , + , + , + + /* svs vote */ + , + , + , + + /* min vote */ + , + , + ; + + dwc3@4e00000 { + compatible = "snps,dwc3"; + reg = <0x4e00000 0xcd00>; + interrupt-parent = <&intc>; + interrupts = <0 255 0>; + usb-phy = <&qusb_phy0>, <&usb_qmp_phy>; + tx-fifo-resize; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + usb-core-id = <0>; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + + qcom,usbbam@0x04f04000 { + compatible = "qcom,usb-bam-msm"; + reg = <0x04f04000 0x17000>; + interrupts = <0 253 0>; + + qcom,usb-bam-fifo-baseaddr = <0xc121000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x08064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + /* Primary USB port related High Speed PHY */ + qusb_phy0: qusb@1613000 { + compatible = "qcom,qusb2phy"; + reg = <0x01613000 0x180>, + <0x003cb250 0x4>, + <0x01b44258 0x4>; + reg-names = "qusb_phy_base", + "tcsr_clamp_dig_n_1p8", + "tune2_efuse_addr"; + + vdd-supply = <&pm6125_l7>; + vdda18-supply = <&pm6125_l10>; + vdda33-supply = <&pm6125_l15>; + qcom,vdd-voltage-level = <0 925000 970000>; + qcom,tune2-efuse-bit-pos = <25>; + qcom,tune2-efuse-num-bits = <4>; + qcom,qusb-phy-init-seq = <0xf8 0x80 + 0xb3 0x84 + 0x81 0x88 + 0xc0 0x8c + 0x30 0x08 + 0x79 0x0c + 0x21 0x10 + 0x14 0x9c + 0x80 0x04 + 0x9f 0x1c + 0x00 0x18>; + phy_type = "utmi"; + qcom,phy-clk-scheme = "cmos"; + qcom,major-rev = <1>; + + clocks = <&clock_rpmcc CXO_SMD_OTG_CLK>, + <&clock_gcc GCC_AHB2PHY_USB_CLK>; + clock-names = "ref_clk_src", "cfg_ahb_clk"; + + resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + /* Primary USB port related QMP USB PHY */ + usb_qmp_phy: ssphy@1615000 { + compatible = "qcom,usb-ssphy-qmp-usb3-or-dp"; + reg = <0x01615000 0x1000>, + <0x03cb244 0x4>; + reg-names = "qmp_phy_base", + "vls_clamp_reg"; + + vdd-supply = <&pm6125_l7>; + core-supply = <&pm6125_l10>; + qcom,vdd-voltage-level = <0 925000 970000>; + qcom,core-voltage-level = <0 1800000 1800000>; + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + <0xd74 /* USB3_PHY_PCS_STATUS */ + 0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */ + 0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */ + 0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */ + 0xc00 /* USB3_PHY_SW_RESET */ + 0xc08 /* USB3_PHY_START */ + 0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */ + + clocks = <&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_rpmcc CXO_SMD_OTG_CLK>, + <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&clock_gcc GCC_AHB2PHY_USB_CLK>; + + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk", "cfg_ahb_clk"; + + resets = <&clock_gcc GCC_USB3_PHY_PRIM_SP0_BCR>, + <&clock_gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x04f 0x0>; + qcom,usb-audio-stream-id = <0xf>; + qcom,usb-audio-intr-num = <2>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-usbc-external-codec-idp-overlay.dts b/arch/arm/boot/dts/qcom/trinket-usbc-external-codec-idp-overlay.dts new file mode 100644 index 000000000000..5f83b48f630f --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-usbc-external-codec-idp-overlay.dts @@ -0,0 +1,29 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include + +#include "trinket-idp.dtsi" + +/ { + model = "USB-C Ext Audio Codec IDP"; + compatible = "qcom,trinket-idp", "qcom,trinket", "qcom,idp"; + qcom,msm-id = <394 0x10000>; + qcom,board-id = <34 3>; +}; + +&dsi_td4330_truly_cmd_display { + qcom,dsi-display-active; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-usbc-external-codec-idp.dts b/arch/arm/boot/dts/qcom/trinket-usbc-external-codec-idp.dts new file mode 100644 index 000000000000..0ae4e76e5254 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-usbc-external-codec-idp.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "trinket.dtsi" +#include "trinket-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Trinket USB-C Ext Audio Codec IDP"; + compatible = "qcom,trinket-idp", "qcom,trinket", "qcom,idp"; + qcom,board-id = <34 3>; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-usbc-idp-overlay.dts b/arch/arm/boot/dts/qcom/trinket-usbc-idp-overlay.dts new file mode 100644 index 000000000000..c916b23676c2 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-usbc-idp-overlay.dts @@ -0,0 +1,30 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include + +#include "trinket-idp.dtsi" +#include "trinket-usbc-idp.dtsi" + +/ { + model = "USBC Audio IDP"; + compatible = "qcom,trinket-idp", "qcom,trinket", "qcom,idp"; + qcom,msm-id = <394 0x10000>; + qcom,board-id = <34 2>; +}; + +&dsi_td4330_truly_cmd_display { + qcom,dsi-display-active; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-usbc-idp.dts b/arch/arm/boot/dts/qcom/trinket-usbc-idp.dts new file mode 100644 index 000000000000..22adfd297b2f --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-usbc-idp.dts @@ -0,0 +1,23 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "trinket.dtsi" +#include "trinket-idp.dtsi" +#include "trinket-usbc-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Trinket USBC Audio IDP"; + compatible = "qcom,trinket-idp", "qcom,trinket", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-usbc-idp.dtsi b/arch/arm/boot/dts/qcom/trinket-usbc-idp.dtsi new file mode 100644 index 000000000000..de74ff642f7b --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-usbc-idp.dtsi @@ -0,0 +1,19 @@ +/* Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "trinket-audio-overlay.dtsi" + +&sm6150_snd { + qcom,msm-mbhc-usbc-audio-supported = <1>; + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; +}; diff --git a/arch/arm/boot/dts/qcom/trinket-vidc.dtsi b/arch/arm/boot/dts/qcom/trinket-vidc.dtsi new file mode 100644 index 000000000000..7b159b3f80e4 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket-vidc.dtsi @@ -0,0 +1,110 @@ +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&soc { + msm_vidc: qcom,vidc@5a00000 { + compatible = "qcom,msm-vidc", "qcom,trinket-vidc"; + status = "ok"; + reg = <0x5a00000 0x200000>; + interrupts = ; + + /* Supply */ + venus-supply = <&venus_gdsc>; + venus-core0-supply = <&vcodec0_gdsc>; + + /* Clocks */ + clock-names = "core_clk", "iface_clk", "bus_clk", + "core0_clk", "core0_bus_clk"; + clocks = <&clock_videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, + <&clock_videocc VIDEO_CC_VENUS_AHB_CLK>, + <&clock_videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, + <&clock_videocc VIDEO_CC_VCODEC0_CORE_CLK>, + <&clock_videocc VIDEO_CC_VCODEC0_AXI_CLK>; + qcom,proxy-clock-names = "core_clk", "iface_clk", + "bus_clk", "core0_clk", "core0_bus_clk"; + qcom,clock-configs = <0x1 0x0 0x0 0x1 0x0>; + qcom,allowed-clock-rates = <133330000 240000000 300000000 + 380000000 410000000>; + + /* Buses */ + bus_cnoc { + compatible = "qcom,msm-vidc,bus"; + label = "cnoc"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 1000>; + }; + + venus_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-ddr"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "vidc-ar50-ddr"; + qcom,bus-range-kbps = <1000 2128000>; + }; + + arm9_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-arm9-ddr"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1000 1000>; + }; + + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_ns"; + iommus = + <&apps_smmu 0x840 0x20>; + buffer-types = <0xfff>; + virtual-addr-pool = <0x70800000 0x6f800000>; + }; + + secure_bitstream_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_bitstream"; + iommus = + <&apps_smmu 0x841 0x4>; + buffer-types = <0x241>; + virtual-addr-pool = <0x4b000000 0x25800000>; + qcom,secure-context-bank; + }; + + secure_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_pixel"; + iommus = + <&apps_smmu 0x843 0x0>; + buffer-types = <0x106>; + virtual-addr-pool = <0x25800000 0x25800000>; + qcom,secure-context-bank; + }; + + secure_non_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_non_pixel"; + iommus = + <&apps_smmu 0x844 0x20>; + buffer-types = <0x480>; + virtual-addr-pool = <0x1000000 0x24800000>; + qcom,secure-context-bank; + }; + }; +}; diff --git a/arch/arm/mach-qcom/board-qcs403.c b/arch/arm/boot/dts/qcom/trinket-wcd.dtsi similarity index 53% rename from arch/arm/mach-qcom/board-qcs403.c rename to arch/arm/boot/dts/qcom/trinket-wcd.dtsi index dec88c6f9742..1c6b200e1c7c 100644 --- a/arch/arm/mach-qcom/board-qcs403.c +++ b/arch/arm/boot/dts/qcom/trinket-wcd.dtsi @@ -10,24 +10,20 @@ * GNU General Public License for more details. */ -#include -#include "board-dt.h" -#include -#include +&slim_aud { + tasha_codec { + wsa_spk_wcd_sd1: msm_cdc_pinctrll { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&tasha_spkr_1_sd_n_active>; + pinctrl-1 = <&tasha_spkr_1_sd_n_sleep>; + }; -static const char *qcs403_dt_match[] __initconst = { - "qcom,qcs403", - "qcom,qcs404", - NULL + wsa_spk_wcd_sd2: msm_cdc_pinctrlr { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&tasha_spkr_2_sd_n_active>; + pinctrl-1 = <&tasha_spkr_2_sd_n_sleep>; + }; + }; }; - -static void __init qcs403_init(void) -{ - board_dt_populate(NULL); -} - -DT_MACHINE_START(QCS403_DT, - "Qualcomm Technologies, Inc. QCS403 (Flattened Device Tree)") - .init_machine = qcs403_init, - .dt_compat = qcs403_dt_match, -MACHINE_END diff --git a/arch/arm/boot/dts/qcom/trinket.dts b/arch/arm/boot/dts/qcom/trinket.dts new file mode 100644 index 000000000000..29ece99394ee --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket.dts @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "trinket.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. TRINKET SoC"; + compatible = "qcom,trinket"; + qcom,board-id = <0 0>; +}; diff --git a/arch/arm/boot/dts/qcom/trinket.dtsi b/arch/arm/boot/dts/qcom/trinket.dtsi new file mode 100644 index 000000000000..83ae25fdc9e8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/trinket.dtsi @@ -0,0 +1,3147 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation.All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "skeleton64.dtsi" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) +#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} +#define DDR_TYPE_LPDDR3 5 +#define DDR_TYPE_LPDDR4X 7 + +/ { + model = "Qualcomm Technologies, Inc. TRINKET"; + compatible = "qcom,trinket"; + qcom,msm-id = <394 0x10000>; + qcom,msm-name = "trinket"; + qcom,pmic-name = "pm6125 + pmi632"; + interrupt-parent = <&wakegic>; + + mem-offline { + compatible = "qcom,mem-offline"; + offline-sizes = <0x1 0x40000000 0x0 0x80000000>, + <0x1 0xc0000000 0x0 0xc0000000>, + <0x2 0xc0000000 0x1 0x40000000>; + granule = <512>; + }; + + aliases { + serial0 = &qupv3_se4_2uart; + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ + sdhc2 = &sdhc_2; /* SDC2 SD Card slot */ + ufshc1 = &ufshc_mem; /* Embedded UFS slot */ + swr0 = &swr0; + swr1 = &swr1; + swr2 = &swr2; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + next-level-cache = <&L2_0>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x80000>; + cache-level = <2>; + }; + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + + L1_TLB_0: l1-tlb { + qcom,dump-size = <0x2800>; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + next-level-cache = <&L2_0>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + + L1_I_1: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + + L1_D_1: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + + L1_TLB_1: l1-tlb { + qcom,dump-size = <0x2800>; + }; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + next-level-cache = <&L2_0>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + + L1_I_2: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + + L1_D_2: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + + L1_TLB_2: l1-tlb { + qcom,dump-size = <0x2800>; + }; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; + d-cache-size = <0x8000>; + i-cache-size = <0x8000>; + next-level-cache = <&L2_0>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + #cooling-cells = <2>; + + L1_I_3: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + + L1_D_3: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + + L1_TLB_3: l1-tlb { + qcom,dump-size = <0x2800>; + }; + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; + d-cache-size = <0x10000>; + i-cache-size = <0x10000>; + next-level-cache = <&L2_1>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + #cooling-cells = <2>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x100000>; + cache-level = <2>; + }; + + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + + L1_TLB_100: l1-tlb { + qcom,dump-size = <0x4800>; + }; + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; + d-cache-size = <0x10000>; + i-cache-size = <0x10000>; + next-level-cache = <&L2_1>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + #cooling-cells = <2>; + + L1_I_101: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + + L1_D_101: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + + L1_TLB_101: l1-tlb { + qcom,dump-size = <0x4800>; + }; + }; + + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x102>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; + d-cache-size = <0x10000>; + i-cache-size = <0x10000>; + next-level-cache = <&L2_1>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + #cooling-cells = <2>; + + L1_I_102: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + + L1_D_102: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + + L1_TLB_102: l1-tlb { + qcom,dump-size = <0x4800>; + }; + }; + + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x103>; + enable-method = "psci"; + capacity-dmips-mhz = <1638>; + sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; + d-cache-size = <0x10000>; + i-cache-size = <0x10000>; + next-level-cache = <&L2_1>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + #cooling-cells = <2>; + + L1_I_103: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + + L1_D_103: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + + L1_TLB_103: l1-tlb { + qcom,dump-size = <0x4800>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; + + energy_costs: energy-costs { + compatible = "sched-energy"; + + CPU_COST_0: core-cost0 { + busy-cost-data = < + 300000 12 + 614400 22 + 864000 39 + 1017600 54 + 1305600 83 + 1420800 102 + 1612800 130 + 1804800 172 + >; + idle-cost-data = < + 10 8 6 4 + >; + }; + + CPU_COST_1: core-cost1 { + busy-cost-data = < + 300000 211 + 652800 417 + 902400 722 + 1056000 991 + 1401600 1577 + 1536000 1932 + 1804800 2579 + 2016000 3391 + >; + idle-cost-data = < + 100 60 40 20 + >; + }; + + CLUSTER_COST_0: cluster-cost0 { + busy-cost-data = < + 300000 5 + 614400 8 + 864000 9 + 1017600 12 + 1305600 18 + 1420800 21 + 1612800 27 + 1804800 36 + >; + idle-cost-data = < + 4 3 2 1 + >; + }; + + CLUSTER_COST_1: cluster-cost1 { + busy-cost-data = < + 300000 38 + 652800 46 + 902400 52 + 1056000 68 + 1401600 88 + 1536000 100 + 1804800 108 + 2016000 120 + >; + idle-cost-data = < + 4 3 2 1 + >; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + }; + + soc: soc { }; + + firmware: firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; + }; + fstab { + compatible = "android,fstab"; + vendor { + compatble = "android,vendor"; + dev = "/dev/block/platform/soc/4804000.ufshc/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_region: hyp_region@45700000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x45700000 0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_mem@45e00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x45e00000 0x0 0x140000>; + }; + + sec_apps_mem: sec_apps_region@45fff000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x45fff000 0x0 0x1000>; + }; + + smem_region: smem@46000000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x46000000 0x0 0x200000>; + }; + + removed_region: removed_region@46200000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x46200000 0 0x2d00000>; + }; + + pil_camera_mem: camera_region@4ab00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x4ab00000 0 0x500000>; + }; + + pil_modem_mem: modem_region@4b000000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x4b000000 0 0x7e00000>; + }; + + pil_video_mem: pil_video_region@52e00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x52e00000 0 0x500000>; + }; + + wlan_msa_mem: wlan_msa_region@53300000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x53300000 0 0x200000>; + }; + + pil_cdsp_mem: cdsp_regions@53500000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x53500000 0 0x1e00000>; + }; + + pil_adsp_mem: pil_adsp_region@55300000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x55300000 0 0x1e00000>; + }; + + pil_ipa_fw_mem: ips_fw_region@57100000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x57100000 0 0x10000>; + }; + + pil_ipa_gsi_mem: ipa_gsi_region@57110000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x57110000 0 0x5000>; + }; + + pil_gpu_mem: gpu_region@57115000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x57115000 0 0x2000>; + }; + + cdsp_sec_mem: cdsp_sec_regions@5f800000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x5f800000 0 0x1e00000>; + }; + + qseecom_mem: qseecom_region@5e400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x5e400000 0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x1000000>; + }; + + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x8c00000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + sdsp_mem: sdsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x400000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x400000>; + }; + + cont_splash_memory: cont_splash_region@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + label = "cont_splash_region"; + }; + + dfps_data_memory: dfps_data_region@5cf00000 { + reg = <0x0 0x5cf00000 0x0 0x0100000>; + label = "dfps_data_region"; + }; + + disp_rdump_memory: disp_rdump_region@5c000000 { + reg = <0x0 0x5c000000 0x0 0x01000000>; + label = "disp_rdump_region"; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x2000000>; + linux,cma-default; + }; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0xf200000 0x10000>, /* GICD */ + <0xf300000 0x100000>; /* GICR * 8 */ + interrupts = <1 9 4>; + }; + + jtag_mm0: jtagmm@9040000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9040000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU0>; + }; + + jtag_mm1: jtagmm@9140000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9140000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU1>; + }; + + jtag_mm2: jtagmm@9240000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9240000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU2>; + }; + + jtag_mm3: jtagmm@9340000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9340000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU3>; + }; + + jtag_mm4: jtagmm@9440000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9440000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU4>; + }; + + jtag_mm5: jtagmm@9540000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9540000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU5>; + }; + + jtag_mm6: jtagmm@9640000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9640000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU6>; + }; + + jtag_mm7: jtagmm@9740000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x9740000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU7>; + }; + + wakegic: wake-gic { + compatible = "qcom,mpm-gic-trinket", "qcom,mpm-gic"; + interrupts-extended = <&wakegic GIC_SPI 197 + IRQ_TYPE_EDGE_RISING>; + reg = <0x45f01b8 0x1000>, + <0xf011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + qcom,num-mpm-irqs = <96>; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <3>; + }; + + wakegpio: wake-gpio { + compatible = "qcom,mpm-gpio-trinket", "qcom,mpm-gpio"; + interrupt-controller; + interrupt-parent = <&intc>; + #interrupt-cells = <2>; + }; + + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <2>; + label = "modem"; + }; + + mem_client_3_size: qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x500000>; + qcom,client-id = <1>; + qcom,allocate-on-request; + label = "modem"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 1 0xf08>, + <1 2 0xf08>, + <1 3 0xf08>, + <1 0 0xf08>; + clock-frequency = <19200000>; + }; + + timer@f120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf120000 0x1000>; + clock-frequency = <19200000>; + + frame@f121000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0xf121000 0x1000>, + <0xf122000 0x1000>; + }; + + frame@f123000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0xf123000 0x1000>; + status = "disabled"; + }; + + frame@f124000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0xf124000 0x1000>; + status = "disabled"; + }; + + frame@f125000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0xf125000 0x1000>; + status = "disabled"; + }; + + frame@f126000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0xf126000 0x1000>; + status = "disabled"; + }; + + frame@f127000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0xf127000 0x1000>; + status = "disabled"; + }; + + frame@f128000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0xf128000 0x1000>; + status = "disabled"; + }; + }; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "chip_sleep_clk"; + #clock-cells = <1>; + }; + + xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "xo_board"; + }; + }; + + clock_rpmcc: qcom,rpmcc { + compatible = "qcom,rpmcc-trinket"; + #clock-cells = <1>; + }; + + clock_gcc: qcom,gcc@1400000 { + compatible = "qcom,gcc-trinket", "syscon"; + reg = <0x1400000 0x1f0000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_videocc: qcom,videocc@5b00000 { + compatible = "qcom,videocc-trinket", "syscon"; + reg = <0x5b00000 0x10000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + #clock-cells = <1>; + }; + + clock_dispcc: qcom,dispcc@5f00000 { + compatible = "qcom,dispcc-trinket", "syscon"; + reg = <0x5f00000 0x20000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clock-names = "cfg_ahb_clk"; + clocks = <&clock_gcc GCC_DISP_AHB_CLK>; + #clock-cells = <1>; + }; + + clock_gpucc: qcom,gpupcc@5990000 { + compatible = "qcom,gpucc-trinket", "syscon"; + reg = <0x5990000 0x9000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>; + #clock-cells = <1>; + }; + + mccc_debug: syscon@447d200 { + compatible = "syscon"; + reg = <0x0447d200 0x100>; + }; + + cpucc_debug: syscon@f11101c { + compatible = "syscon"; + reg = <0xf11101c 0x4>; + }; + + clock_cpucc: qcom,cpucc@f521000 { + compatible = "qcom,clk-cpu-osm-trinket"; + reg = <0xf521000 0x1400>, + <0xf523000 0x1400>; + reg-names = "osm_pwrcl_base", "osm_perfcl_base"; + #clock-cells = <1>; + }; + + clock_debugcc: qcom,cc-debug { + compatible = "qcom,debugcc-trinket"; + qcom,gcc = <&clock_gcc>; + qcom,videocc = <&clock_videocc>; + qcom,dispcc = <&clock_dispcc>; + qcom,gpucc = <&clock_gpucc>; + qcom,mccc = <&mccc_debug>; + qcom,cpucc = <&cpucc_debug>; + clock-names = "cxo"; + clocks = <&clock_rpmcc RPM_SMD_XO_CLK_SRC>; + #clock-cells = <1>; + }; + + arm64-cpu-erp { + compatible = "arm,arm64-cpu-erp"; + interrupts = <0 43 4>, + <0 44 4>, + <0 41 4>, + <0 42 4>; + + interrupt-names = "pri-dbe-irq", + "sec-dbe-irq", + "pri-ext-irq", + "sec-ext-irq"; + + poll-delay-ms = <5000>; + }; + + ufs_ice: ufsice@4810000 { + compatible = "qcom,ice"; + reg = <0x4810000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk", "bus_clk", + "iface_clk", "ice_core_clk"; + clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>, + <&clock_gcc GCC_UFS_PHY_AHB_CLK>, + <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>; + qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; + vdd-hba-supply = <&ufs_phy_gdsc>; + qcom,msm-bus,name = "ufs_ice_noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 650 0 0>, /* No vote */ + <1 650 1000 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "ufs"; + }; + + ufsphy_mem: ufsphy_mem@4807000 { + reg = <0x4807000 0xdb8>; /* PHY regs */ + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <1>; + + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&clock_rpmcc RPM_SMD_LN_BB_CLK1>, + <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>, + <&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + status = "disabled"; + }; + + ufshc_mem: ufshc@4804000 { + compatible = "qcom,ufshc"; + reg = <0x4804000 0x3000>; + interrupts = <0 356 0>; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + ufs-qcom-crypto = <&ufs_ice>; + + lanes-per-direction = <1>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + spm-level = <5>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks = + <&clock_gcc GCC_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_UFS_PHY_AHB_CLK>, + <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&clock_rpmcc RPM_SMD_LN_BB_CLK1>, + <&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; + freq-table-hz = + <50000000 240000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + + qcom,msm-bus,name = "ufshc_mem"; + qcom,msm-bus,num-cases = <12>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <123 512 0 0>, <1 757 0 0>, /* No vote */ + <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */ + <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */ + <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */ + <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */ + <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */ + <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */ + <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */ + <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */ + <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */ + <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */ + <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", + "MAX"; + + /* PM QoS */ + qcom,pm-qos-cpu-groups = <0x0f 0xf0>; + qcom,pm-qos-cpu-group-latency-us = <26 26>; + qcom,pm-qos-default-cpu = <0>; + + pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; + pinctrl-0 = <&ufs_dev_reset_assert>; + pinctrl-1 = <&ufs_dev_reset_deassert>; + + resets = <&clock_gcc GCC_UFS_PHY_BCR>; + reset-names = "core_reset"; + non-removable; + + status = "disabled"; + }; + + qcom,msm-imem@c125000 { + compatible = "qcom,msm-imem"; + reg = <0xc125000 0x1000>; + ranges = <0x0 0xc125000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 32>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 12>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 200>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 200>; + }; + }; + + restart@440b000 { + compatible = "qcom,pshold"; + reg = <0x440b000 0x4>, + <0x03d3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + qcom,mpm2-sleep-counter@4403000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x4403000 0x1000>; + clock-frequency = <32768>; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + thermal_zones: thermal-zones {}; + + dcc: dcc_v2@1be2000 { + compatible = "qcom,dcc-v2"; + reg = <0x1be2000 0x1000>, + <0x1bef000 0x1000>; + reg-names = "dcc-base", "dcc-ram-base"; + dcc-ram-offset = <0x1000>; + }; + + tsens0: tsens@4410000 { + compatible = "qcom,sm6150-tsens"; + reg = <0x4410000 0x8>, + <0x4411000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts = <0 275 0>, <0 190 0>; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + #thermal-sensor-cells = <1>; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = <1 6 4>; + }; + + eud: qcom,msm-eud@1610000 { + compatible = "qcom,msm-eud"; + interrupt-names = "eud_irq"; + interrupts = ; + reg = <0x1610000 0x2000>, + <0x1612000 0x1000>; + reg-names = "eud_base", "eud_mode_mgr2"; + qcom,secure-eud-en; + qcom,eud-clock-vote-req; + clocks = <&clock_gcc GCC_AHB2PHY_USB_CLK>; + clock-names = "eud_ahb2phy_clk"; + status = "ok"; + }; + + qcom,msm-gladiator-v2@f100000 { + compatible = "qcom,msm-gladiator-v2"; + reg = <0xf100000 0xdc00>; + reg-names = "gladiator_base"; + interrupts = <0 22 0>; + clock-names = "atb_clk"; + clocks = <&clock_rpmcc RPM_QDSS_CLK>; + }; + + pil_modem: qcom,mss@6080000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x6080000 0x100>; + + clocks = <&clock_rpmcc CXO_SMD_PIL_MSS_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + qcom,mas-crypto = <&mas_crypto_c0>; + qcom,proxy-reg-names = "vdd_cx"; + + qcom,firmware-name = "modem"; + memory-region = <&pil_modem_mem>; + qcom,proxy-timeout-ms = <10000>; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x12>; + qcom,pas-id = <4>; + qcom,smem-id = <421>; + qcom,minidump-id = <3>; + qcom,aux-minidump-ids = <4>; + qcom,complete-ramdump; + + /* Inputs from mss */ + interrupts-extended = <&wakegic 0 307 1>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + /* Outputs to mss */ + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + interrupts = ; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + + wdog: qcom,wdt@f017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf017000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 3 0>, <0 4 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + qcom,scandump-sizes = <0x40000>; + }; + + qcom,chd_silver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0xf1880b0 0xf1980b0 + 0xf1a80b0 0xf1b80b0>; + qcom,config-arr = <0xf1880b8 0xf1980b8 + 0xf1a80b8 0xf1b80b8>; + }; + + qcom,chd_gold { + compatible = "qcom,core-hang-detect"; + label = "gold"; + qcom,threshold-arr = <0xf0880b0 0xf0980b0 + 0xf0a80b0 0xf0b80b0>; + qcom,config-arr = <0xf0880b8 0xf0980b8 + 0xf0a80b8 0xf0b80b8>; + }; + + qcom,ghd { + compatible = "qcom,gladiator-hang-detect"; + qcom,threshold-arr = <0x0f1d141c 0x0f1d1420 + 0x0f1d1424 0x0f1d1428 + 0x0f1d142c 0x0f1d1430>; + qcom,config-reg = <0x0f1d1434>; + }; + + qcom,sps { + compatible = "qcom,msm-sps-4k"; + qcom,pipe-attr-ee; + }; + + gpi_dma0: qcom,gpi-dma@0x04a00000 { + #dma-cells = <5>; + compatible = "qcom,gpi-dma"; + reg = <0x04a00000 0x60000>; + reg-names = "gpi-top"; + interrupts = <0 335 0>, <0 336 0>, <0 337 0>, <0 338 0>, + <0 339 0>, <0 340 0>, <0 341 0>, <0 342 0>; + qcom,ev-factor = <2>; + qcom,max-num-gpii = <8>; + qcom,gpii-mask = <0x1f>; + iommus = <&apps_smmu 0x0136 0x0>; + qcom,smmu-cfg = <0x1>; + qcom,iova-range = <0x0 0x100000 0x0 0x100000>; + status = "ok"; + }; + + gpi_dma1: qcom,gpi-dma@0x04c00000 { + #dma-cells = <5>; + compatible = "qcom,gpi-dma"; + reg = <0x04c00000 0x60000>; + reg-names = "gpi-top"; + interrupts = <0 314 0>, <0 315 0>, <0 316 0>, <0 317 0>, + <0 318 0>, <0 319 0>, <0 320 0>, <0 321 0>; + qcom,ev-factor = <2>; + qcom,max-num-gpii = <8>; + qcom,gpii-mask = <0x0f>; + qcom,smmu-cfg = <0x1>; + qcom,iova-range = <0x0 0x100000 0x0 0x100000>; + iommus = <&apps_smmu 0x0156 0x0>; + status = "ok"; + }; + + qcom,lpass@ab00000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xab00000 0x00100>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + qcom,mas-crypto = <&mas_crypto_c0>; + + clocks = <&clock_rpmcc CXO_SMD_PIL_LPASS_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <1>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,sysmon-id = <1>; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + qcom,complete-ramdump; + + /* Inputs from lpass */ + interrupts-extended = <&wakegic 0 396 1>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + }; + + qcom,turing@b300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xb300000 0x100000>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + qcom,mas-crypto = <&mas_crypto_c0>; + + clocks = <&clock_rpmcc CXO_SMD_PIL_CDSP_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <18>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <601>; + qcom,sysmon-id = <7>; + qcom,ssctl-instance-id = <0x17>; + qcom,firmware-name = "cdsp"; + memory-region = <&pil_cdsp_mem>; + qcom,complete-ramdump; + + /* Inputs from turing */ + interrupts-extended = <&wakegic 0 265 1>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + }; + + cpuss_dump: cpuss_dump { + compatible = "qcom,cpuss-dump"; + qcom,l1_i_cache0 { + qcom,dump-node = <&L1_I_0>; + qcom,dump-id = <0x60>; + }; + qcom,l1_i_cache1 { + qcom,dump-node = <&L1_I_1>; + qcom,dump-id = <0x61>; + }; + qcom,l1_i_cache2 { + qcom,dump-node = <&L1_I_2>; + qcom,dump-id = <0x62>; + }; + qcom,l1_i_cache3 { + qcom,dump-node = <&L1_I_3>; + qcom,dump-id = <0x63>; + }; + qcom,l1_i_cache100 { + qcom,dump-node = <&L1_I_100>; + qcom,dump-id = <0x64>; + }; + qcom,l1_i_cache101 { + qcom,dump-node = <&L1_I_101>; + qcom,dump-id = <0x65>; + }; + qcom,l1_i_cache102 { + qcom,dump-node = <&L1_I_102>; + qcom,dump-id = <0x66>; + }; + qcom,l1_i_cache103 { + qcom,dump-node = <&L1_I_103>; + qcom,dump-id = <0x67>; + }; + qcom,l1_d_cache0 { + qcom,dump-node = <&L1_D_0>; + qcom,dump-id = <0x80>; + }; + qcom,l1_d_cache1 { + qcom,dump-node = <&L1_D_1>; + qcom,dump-id = <0x81>; + }; + qcom,l1_d_cache2 { + qcom,dump-node = <&L1_D_2>; + qcom,dump-id = <0x82>; + }; + qcom,l1_d_cache3 { + qcom,dump-node = <&L1_D_3>; + qcom,dump-id = <0x83>; + }; + qcom,l1_d_cache100 { + qcom,dump-node = <&L1_D_100>; + qcom,dump-id = <0x84>; + }; + qcom,l1_d_cache101 { + qcom,dump-node = <&L1_D_101>; + qcom,dump-id = <0x85>; + }; + qcom,l1_d_cache102 { + qcom,dump-node = <&L1_D_102>; + qcom,dump-id = <0x86>; + }; + qcom,l1_d_cache103 { + qcom,dump-node = <&L1_D_103>; + qcom,dump-id = <0x87>; + }; + qcom,l1_tlb_dump0 { + qcom,dump-node = <&L1_TLB_0>; + qcom,dump-id = <0x20>; + }; + qcom,l1_tlb_dump1 { + qcom,dump-node = <&L1_TLB_1>; + qcom,dump-id = <0x21>; + }; + qcom,l1_tlb_dump2 { + qcom,dump-node = <&L1_TLB_2>; + qcom,dump-id = <0x22>; + }; + qcom,l1_tlb_dump3 { + qcom,dump-node = <&L1_TLB_3>; + qcom,dump-id = <0x23>; + }; + qcom,l1_tlb_dump100 { + qcom,dump-node = <&L1_TLB_100>; + qcom,dump-id = <0x24>; + }; + qcom,l1_tlb_dump101 { + qcom,dump-node = <&L1_TLB_101>; + qcom,dump-id = <0x25>; + }; + qcom,l1_tlb_dump102 { + qcom,dump-node = <&L1_TLB_102>; + qcom,dump-id = <0x26>; + }; + qcom,l1_tlb_dump103 { + qcom,dump-node = <&L1_TLB_103>; + qcom,dump-id = <0x27>; + }; + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + rpm_sw { + qcom,dump-size = <0x28000>; + qcom,dump-id = <0xea>; + }; + + pmic { + qcom,dump-size = <0x10000>; + qcom,dump-id = <0xe4>; + }; + + fcm { + qcom,dump-size = <0x8400>; + qcom,dump-id = <0xee>; + }; + + tmc_etf { + qcom,dump-size = <0x8000>; + qcom,dump-id = <0xf0>; + }; + + etr_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x100>; + }; + + etf_reg { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0x101>; + }; + + misc_data { + qcom,dump-size = <0x1000>; + qcom,dump-id = <0xe8>; + }; + }; + + tcsr_mutex_block: syscon@00340000 { + compatible = "syscon"; + reg = <0x00340000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 3>; + }; + + rpm_msg_ram: memory@045F0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x045f0000 0x7000>; + }; + + apcs_glb: mailbox@0F111000 { + compatible = "qcom,trinket-apcs-hmss-global"; + reg = <0x0F111000 0x1000>; + + #mbox-cells = <1>; + }; + + qcom,msm-cdsp-loader { + compatible = "qcom,cdsp-loader"; + qcom,proc-img-to-load = "cdsp"; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + restrict-access; + }; + + qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-compute"; + qcom,rpc-latency-us = <611>; + qcom,adsp-remoteheap-vmid = <22 37>; + qcom,fastrpc-adsp-audio-pdr; + qcom,fastrpc-adsp-sensors-pdr; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C01 0x0>; + }; + + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C02 0x0>; + }; + + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C03 0x0>; + }; + + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C04 0x0>; + }; + + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C05 0x0>; + }; + + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&apps_smmu 0x0C06 0x0>; + }; + + qcom,msm_fastrpc_compute_cb9 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + qcom,secure-context-bank; + iommus = <&apps_smmu 0x0C09 0x0>; + }; + + qcom,msm_fastrpc_compute_cb10 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&apps_smmu 0x0043 0x0>, + <&apps_smmu 0x0044 0x0>; + shared-sid = <2>; + shared-cb = <5>; + }; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + qcom,rpm_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>, + <&glink_cdsp>; + }; + + }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_modem: modem { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&apcs_glb 12>; + mbox-names = "mpss_smem"; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 2>; + }; + + qcom,modem_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>, + <&glink_cdsp>; + }; + }; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&apcs_glb 8>; + mbox-names = "adsp_smem"; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,apr_tal_rpmsg { + qcom,glink-channels = "apr_audio_svc"; + qcom,intents = <0x200 20>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,adsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_cdsp>; + }; + }; + + glink_cdsp: cdsp { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&apcs_glb 28>; + mbox-names = "cdsp_smem"; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,msm_fastrpc_rpmsg { + compatible = "qcom,msm-fastrpc-rpmsg"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12>; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-latency-us = <44>; + qcom,qos-maxhold-ms = <20>; + #cooling-cells = <2>; + }; + + msm_hvx_rm: qcom,msm_hvx_rm { + compatible = "qcom,msm-hvx-rm"; + #cooling-cells = <2>; + }; + }; + + qcom,cdsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>; + }; + }; + + glink_spi_xprt_wdsp: wdsp { + qcom,remote-pid = <10>; + transport = "spi"; + tx-descriptors = <0x12000 0x12004>; + rx-descriptors = <0x1200c 0x12010>; + + qcom,wdsp_ctrl { + qcom,glink-channels = "g_glink_ctrl"; + qcom,intents = <0x400 1>; + }; + + qcom,wdsp_ild { + qcom,glink-channels = + "g_glink_persistent_data_ild"; + }; + + qcom,wdsp_nild { + qcom,glink-channels = + "g_glink_persistent_data_nild"; + }; + + qcom,wdsp_data { + qcom,glink-channels = "g_glink_audio_data"; + qcom,intents = <0x1000 2>; + }; + + qcom,diag_data { + qcom,glink-channels = "DIAG_DATA"; + qcom,intents = <0x4000 2>; + }; + + qcom,diag_ctrl { + qcom,glink-channels = "DIAG_CTRL"; + qcom,intents = <0x4000 1>; + }; + + qcom,diag_cmd { + qcom,glink-channels = "DIAG_CMD"; + qcom,intents = <0x4000 1 >; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qcom,smp2p_sleepstate { + compatible = "qcom,smp2p-sleepstate"; + qcom,smem-states = <&sleepstate_smp2p_out 0>; + interrupt-parent = <&sleepstate_smp2p_in>; + interrupts = <0 0>; + interrupt-names = "smp2p-sleepstate-in"; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + mboxes = <&apcs_glb 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + /* ipa - inbound entry from mss */ + smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = ; + mboxes = <&apcs_glb 10>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sleepstate_smp2p_out: sleepstate-out { + qcom,entry-name = "sleepstate"; + #qcom,smem-state-cells = <1>; + }; + + sleepstate_smp2p_in: qcom,sleepstate-in { + qcom,entry-name = "sleepstate_see"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts = ; + mboxes = <&apcs_glb 30>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { + qcom,entry-name = "rdbg"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { + qcom,entry-name = "rdbg"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + }; + + qcom_seecom: qseecom@46d00000 { + compatible = "qcom,qseecom"; + reg = <0x46d00000 0x2200000>; + reg-names = "secapp-region"; + memory-region = <&qseecom_mem>; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,fde-key-size; + qcom,appsbl-qseecom-support; + qcom,commonlib64-loaded-by-uefi; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 200000 400000>, + <55 512 300000 800000>, + <55 512 400000 1000000>; + clock-names = + "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = + <&clock_rpmcc QSEECOM_CE1_CLK>, + <&clock_rpmcc QSEECOM_CE1_CLK>, + <&clock_rpmcc QSEECOM_CE1_CLK>, + <&clock_rpmcc QSEECOM_CE1_CLK>; + qcom,ce-opp-freq = <171430000>; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_smcinvoke: smcinvoke@46d00000 { + compatible = "qcom,smcinvoke"; + reg = <0x46d00000 0x2200000>; + reg-names = "secapp-region"; + }; + + qcom_rng: qrng@1b53000 { + compatible = "qcom,msm-rng"; + reg = <0x1b53000 0x1000>; + qcom,msm-rng-iface-clk; + qcom,no-qrng-config; + qcom,msm-bus,name = "msm-rng-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 618 0 0>, /* No vote */ + <1 618 0 300000>; /* 75 MHz */ + clocks = <&clock_gcc GCC_PRNG_AHB_CLK>; + clock-names = "iface_clk"; + }; + + qcom_tzlog: tz-log@0c125720 { + compatible = "qcom,tz-log"; + reg = <0x0c125720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + + spmi_bus: qcom,spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x1c40000 0x1100>, + <0x1e00000 0x2000000>, + <0x3e00000 0x100000>, + <0x3f00000 0xa0000>, + <0x1c0a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x200000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + qcom,guard-memory; + }; + + qcom_cedev: qcedev@1b20000 { + compatible = "qcom,qcedev"; + reg = <0x1b20000 0x20000>, + <0x1b04000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 247 0>; + qcom,bam-pipe-pair = <3>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,bam-ee = <0>; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 393600 393600>; + clock-names = + "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = + <&clock_rpmcc QCEDEV_CE1_CLK>, + <&clock_rpmcc QCEDEV_CE1_CLK>, + <&clock_rpmcc QCEDEV_CE1_CLK>, + <&clock_rpmcc QCEDEV_CE1_CLK>; + qcom,ce-opp-freq = <171430000>; + qcom,smmu-s1-enable; + iommus = <&apps_smmu 0x01A6 0x0011>, + <&apps_smmu 0x01B6 0x0011>; + }; + + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; + + qcom_crypto: qcrypto@1b20000 { + compatible = "qcom,qcrypto"; + reg = <0x1b20000 0x20000>, + <0x1b04000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 247 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + qcom,clk-mgmt-sus-res; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 393600 393600>; + clock-names = + "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = + <&clock_rpmcc QCRYPTO_CE1_CLK>, + <&clock_rpmcc QCRYPTO_CE1_CLK>, + <&clock_rpmcc QCRYPTO_CE1_CLK>, + <&clock_rpmcc QCRYPTO_CE1_CLK>; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-aead-algo; + qcom,use-sw-hmac-algo; + qcom,smmu-s1-enable; + iommus = <&apps_smmu 0x01A4 0x0011>, + <&apps_smmu 0x01B4 0x0011>; + }; + + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-io-supply = <&pm6125_l9>; + qca,bt-vdd-core-supply = <&pm6125_l17>; + qca,bt-vdd-pa-supply = <&pm6125_l23>; + qca,bt-vdd-xtal-supply = <&pm6125_l16>; + + qca,bt-vdd-io-voltage-level = <1700000 1900000>; /* IO */ + qca,bt-vdd-core-voltage-level = <1304000 1304000>; /* RFA */ + qca,bt-vdd-pa-voltage-level = <3000000 3400000>; /*chain0 */ + qca,bt-vdd-xtal-voltage-level = <1700000 1900000>; /* XO */ + + qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ + }; + + slim_aud: slim@a2c0000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0xa2c0000 0x2c000>, + <0xa284000 0x2a000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 397 0>, <0 398 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x7c0000>; + qcom,ea-pc = <0x310>; + status = "disabled"; + qcom,iommu-s1-bypass; + + iommu_slim_aud_ctrl_cb: qcom,iommu_slim_ctrl_cb { + compatible = "qcom,iommu-slim-ctrl-cb"; + iommus = <&apps_smmu 0x66 0x0>, + <&apps_smmu 0x6d 0x0>, + <&apps_smmu 0x6e 0x1>, + <&apps_smmu 0x70 0x1>; + }; + }; + + slim_qca: slim@a340000 { + cell-index = <3>; + compatible = "qcom,slim-ngd"; + reg = <0xa340000 0x2c000>, + <0xa304000 0x20000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 403 0>, <0 404 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + status = "ok"; + qcom,iommu-s1-bypass; + + iommu_slim_qca_ctrl_cb: qcom,iommu_slim_ctrl_cb { + compatible = "qcom,iommu-slim-ctrl-cb"; + iommus = <&apps_smmu 0x73 0x0>; + }; + + /* Slimbus Slave DT for WCN3990 */ + btfmslim_codec: wcn3990 { + compatible = "qcom,btfmslim_slave"; + elemental-addr = [00 01 20 02 17 02]; + qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; + qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; + }; + }; + + sdcc1_ice: sdcc1ice@4748000{ + compatible = "qcom,ice"; + reg = <0x4748000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ice_core_clk_src", "ice_core_clk", + "bus_clk", "iface_clk"; + clocks = <&clock_gcc GCC_SDCC1_ICE_CORE_CLK_SRC>, + <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>, + <&clock_gcc GCC_SDCC1_AHB_CLK>, + <&clock_gcc GCC_SDCC1_APPS_CLK>; + qcom,op-freq-hz = <300000000>, <0>, <0>, <0>; + qcom,msm-bus,name = "sdcc_ice_noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 757 0 0>, /* No vote */ + <1 757 1000 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "sdcc"; + }; + + sdhc_1: sdhci@4744000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x4744000 0x1000>, <0x4745000 0x1000>; + reg-names = "hc_mem", "cmdq_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + sdhc-msm-crypto = <&sdcc1_ice>; + + qcom,bus-width = <8>; + qcom,large-address-bus; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 + 192000000 384000000>; + qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; + + qcom,devfreq,freq-table = <50000000 200000000>; + + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <9>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <78 512 0 0>, <1 606 0 0>, + /* 400 KB/s*/ + <78 512 1046 1600>, + <1 606 1600 1600>, + /* 20 MB/s */ + <78 512 20480 80000>, + <1 606 80000 80000>, + /* 25 MB/s */ + <78 512 25600 100000>, + <1 606 50000 100000>, + /* 50 MB/s */ + <78 512 51200 200000>, + <1 606 65000 100000>, + /* 100 MB/s */ + <78 512 102400 200000>, + <1 606 65000 100000>, + /* 200 MB/s */ + <78 512 204800 400000>, + <1 606 300000 300000>, + /* 400 MB/s */ + <78 512 204800 400000>, + <1 606 300000 300000>, + /* Max. bandwidth */ + <78 512 1338562 4096000>, + <1 606 1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100750000 200000000 400000000 4294967295>; + + /* PM QoS */ + qcom,pm-qos-irq-type = "affine_irq"; + qcom,pm-qos-irq-latency = <40 40>; + qcom,pm-qos-cpu-groups = <0x0f 0xf0>; + qcom,pm-qos-cmdq-latency-us = <40 40>, <40 40>; + qcom,pm-qos-legacy-latency-us = <40 40>, <40 40>; + + qcom,scaling-lower-bus-speed-mode = "DDR52"; + + clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, + <&clock_gcc GCC_SDCC1_APPS_CLK>, + <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface_clk", "core_clk", "ice_core_clk"; + + qcom,ice-clk-rates = <300000000 75000000>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x00010800 0x80040873>; + + qcom,nonremovable; + status = "disabled"; + }; + + sdhc_2: sdhci@4784000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x4784000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <4>; + qcom,large-address-bus; + + qcom,clk-rates = <400000 20000000 25000000 + 50000000 100000000 202000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", + "SDR104"; + + qcom,devfreq,freq-table = <50000000 202000000>; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <81 512 0 0>, <1 608 0 0>, + /* 400 KB/s*/ + <81 512 1046 3200>, + <1 608 1600 1600>, + /* 20 MB/s */ + <81 512 52286 160000>, + <1 608 80000 80000>, + /* 25 MB/s */ + <81 512 65360 200000>, + <1 608 100000 100000>, + /* 50 MB/s */ + <81 512 130718 400000>, + <1 608 133320 133320>, + /* 100 MB/s */ + <81 512 261438 400000>, + <1 608 150000 150000>, + /* 200 MB/s */ + <81 512 261438 800000>, + <1 608 300000 300000>, + /* Max. bandwidth */ + <81 512 1338562 4096000>, + <1 608 1338562 4096000>; + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100750000 200000000 4294967295>; + + /* PM QoS */ + qcom,pm-qos-irq-type = "affine_irq"; + qcom,pm-qos-irq-latency = <40 40>; + qcom,pm-qos-cpu-groups = <0x0f 0xf0>; + qcom,pm-qos-legacy-latency-us = <40 40>, <40 40>; + + clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>, + <&clock_gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface_clk", "core_clk"; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0x0 0x0 0x00010800 0x80040873>; + + status = "disabled"; + }; + + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + qcom,ipa-platform-type-msm; + qcom,ipa-advertise-sg-support; + qcom,ipa-napi-enable; + }; + + ipa_hw: qcom,ipa@5800000 { + compatible = "qcom,ipa"; + reg = <0x5800000 0x34000>, + <0x5804000 0x2c000>; + reg-names = "ipa-base", "gsi-base"; + interrupts = <0 257 0>, <0 259 0>; + interrupt-names = "ipa-irq", "gsi-irq"; + qcom,ipa-hw-ver = <16>; /* IPA core version = IPAv4.2 */ + qcom,ipa-hw-mode = <0>; + qcom,ee = <0>; + qcom,use-ipa-tethering-bridge; + qcom,modem-cfg-emb-pipe-flt; + qcom,ipa-wdi2; + qcom,ipa-wdi2_over_gsi; + qcom,ipa-endp-delay-wa; + qcom,ipa-fltrt-not-hashable; + qcom,use-64-bit-dma-mask; + qcom,arm-smmu; + qcom,smmu-fast-map; + qcom,use-ipa-pm; + clocks = <&clock_rpmcc RPM_SMD_IPA_CLK>; + clock-names = "core_clk"; + qcom,msm-bus,name = "ipa"; + qcom,msm-bus,num-cases = <5>; + qcom,msm-bus,num-paths = <3>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + , + , + , + /* SVS2 */ + , + , + , + /* SVS */ + , + , + , + /* NOMINAL */ + , + , + , + /* TURBO */ + , + , + ; + qcom,bus-vector-names = + "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; + qcom,throughput-threshold = <310 600 1000>; + qcom,scaling-exceptions = <>; + + /* smp2p information */ + qcom,smp2p_map_ipa_1_out { + compatible = "qcom,smp2p-map-ipa-1-out"; + qcom,smem-states = <&smp2p_ipa_1_out 0>; + qcom,smem-state-names = "ipa-smp2p-out"; + }; + + qcom,smp2p_map_ipa_1_in { + compatible = "qcom,smp2p-map-ipa-1-in"; + interrupts-extended = <&smp2p_ipa_1_in 0 0>; + interrupt-names = "ipa-smp2p-in"; + }; + }; + + ipa_smmu_ap: ipa_smmu_ap { + compatible = "qcom,ipa-smmu-ap-cb"; + iommus = <&apps_smmu 0x00E0 0x0>; + qcom,iova-mapping = <0x10000000 0x30000000>; + /* modem tables in IMEM */ + qcom,additional-mapping = <0x0c123000 0x0c123000 0x2000>; + }; + + ipa_smmu_wlan: ipa_smmu_wlan { + compatible = "qcom,ipa-smmu-wlan-cb"; + iommus = <&apps_smmu 0x00E1 0x0>; + /* ipa-uc ram */ + qcom,additional-mapping = <0x5860000 0x5860000 0x80000>; + }; + + ipa_smmu_uc: ipa_smmu_uc { + compatible = "qcom,ipa-smmu-uc-cb"; + iommus = <&apps_smmu 0x00E2 0x0>; + qcom,iova-mapping = <0x40400000 0x1fc00000>; + }; + + qcom,ipa_fws { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0xf>; + qcom,firmware-name = "ipa_fws"; + qcom,pil-force-shutdown; + memory-region = <&pil_ipa_fw_mem>; + }; + + qcom,venus@5ae0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x5ae0000 0x4000>; + + vdd-supply = <&venus_gdsc>; + qcom,proxy-reg-names = "vdd"; + qcom,mas-crypto = <&mas_crypto_c0>; + + clocks = <&clock_videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, + <&clock_videocc VIDEO_CC_VENUS_AHB_CLK>, + <&clock_videocc VIDEO_CC_VENUS_CTL_AXI_CLK>; + clock-names = "core_clk", "iface_clk", "bus_clk"; + qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk"; + + qcom,pas-id = <9>; + qcom,msm-bus,name = "pil-venus"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <63 512 0 0>, + <63 512 0 304000>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&pil_video_mem>; + }; + + cx_ipeak_lm: cx_ipeak@3ed000 { + compatible = "qcom,cx-ipeak-v2"; + reg = <0x3ed000 0xc00c>; + }; + + ssc_sensors: qcom,msm-ssc-sensors { + compatible = "qcom,msm-ssc-sensors"; + status = "ok"; + }; + + ddr4_bw_opp_table: ddr4-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 200, 8); /* 1525 MB/s */ + BW_OPP_ENTRY( 300, 8); /* 2288 MB/s */ + BW_OPP_ENTRY( 451, 8); /* 3440 MB/s */ + BW_OPP_ENTRY( 547, 8); /* 4173 MB/s */ + BW_OPP_ENTRY( 681, 8); /* 5195 MB/s */ + BW_OPP_ENTRY( 768, 8); /* 5859 MB/s */ + BW_OPP_ENTRY(1017, 8); /* 7759 MB/s */ + BW_OPP_ENTRY(1353, 8); /*10322 MB/s */ + BW_OPP_ENTRY(1555, 8); /*11863 MB/s */ + BW_OPP_ENTRY(1804, 8); /*13763 MB/s */ + }; + + suspendable_ddr4_bw_opp_table: suspendable-ddr4-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 0, 8); /* 0 MB/s */ + BW_OPP_ENTRY( 200, 8); /* 1525 MB/s */ + BW_OPP_ENTRY( 300, 8); /* 2288 MB/s */ + BW_OPP_ENTRY( 451, 8); /* 3440 MB/s */ + BW_OPP_ENTRY( 547, 8); /* 4173 MB/s */ + BW_OPP_ENTRY( 681, 8); /* 5195 MB/s */ + BW_OPP_ENTRY( 768, 8); /* 5859 MB/s */ + BW_OPP_ENTRY(1017, 8); /* 7759 MB/s */ + BW_OPP_ENTRY(1353, 8); /*10322 MB/s */ + BW_OPP_ENTRY(1555, 8); /*11863 MB/s */ + BW_OPP_ENTRY(1804, 8); /*13763 MB/s */ + }; + + ddr3_bw_opp_table: ddr3-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 200, 8); /* 1525 MB/s */ + BW_OPP_ENTRY( 300, 8); /* 2288 MB/s */ + BW_OPP_ENTRY( 451, 8); /* 3440 MB/s */ + BW_OPP_ENTRY( 547, 8); /* 4173 MB/s */ + BW_OPP_ENTRY( 681, 8); /* 5195 MB/s */ + BW_OPP_ENTRY( 768, 8); /* 5859 MB/s */ + BW_OPP_ENTRY( 931, 8); /* 7102 MB/s */ + }; + + suspendable_ddr3_bw_opp_table: suspendable-ddr3-bw-opp-table { + compatible = "operating-points-v2"; + BW_OPP_ENTRY( 0, 8); /* 0 MB/s */ + BW_OPP_ENTRY( 200, 8); /* 1525 MB/s */ + BW_OPP_ENTRY( 300, 8); /* 2288 MB/s */ + BW_OPP_ENTRY( 451, 8); /* 3440 MB/s */ + BW_OPP_ENTRY( 547, 8); /* 4173 MB/s */ + BW_OPP_ENTRY( 681, 8); /* 5195 MB/s */ + BW_OPP_ENTRY( 768, 8); /* 5859 MB/s */ + BW_OPP_ENTRY( 931, 8); /* 7102 MB/s */ + }; + + cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + ddr3-opp { + operating-points-v2 = <&ddr3_bw_opp_table>; + qcom,ddr-type = ; + }; + ddr4-opp { + operating-points-v2 = <&ddr4_bw_opp_table>; + qcom,ddr-type = ; + }; + }; + + cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@01b8e200 { + compatible = "qcom,bimc-bwmon4"; + reg = <0x01b8e200 0x100>, <0x01b8e100 0x100>; + reg-names = "base", "global_base"; + interrupts = ; + qcom,mport = <0>; + qcom,hw-timer-hz = <19200000>; + qcom,target-dev = <&cpu_cpu_ddr_bw>; + qcom,count-unit = <0x10000>; + }; + + cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + ddr3-opp { + operating-points-v2 = <&ddr3_bw_opp_table>; + qcom,ddr-type = ; + }; + ddr4-opp { + operating-points-v2 = <&ddr4_bw_opp_table>; + qcom,ddr-type = ; + }; + }; + + cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_cpu_ddr_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,stall-cycle-ev = <0xE7>; + ddr3-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 864000 MHZ_TO_MBPS(200, 8) >, + < 1305600 MHZ_TO_MBPS(451, 8) >, + < 1804800 MHZ_TO_MBPS(768, 8) >; + }; + ddr4-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 864000 MHZ_TO_MBPS( 300, 8) >, + < 1305600 MHZ_TO_MBPS( 547, 8) >, + < 1420000 MHZ_TO_MBPS( 768, 8) >, + < 1804800 MHZ_TO_MBPS(1017, 8) >; + }; + }; + + cpu4_cpu_ddr_lat: qcom,cpu4-cpu-ddr-lat { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + ddr3-opp { + operating-points-v2 = <&ddr3_bw_opp_table>; + qcom,ddr-type = ; + }; + ddr4-opp { + operating-points-v2 = <&ddr4_bw_opp_table>; + qcom,ddr-type = ; + }; + }; + + cpu4_cpu_ddr_latmon: qcom,cpu4-cpu-ddr-latmon { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&cpu4_cpu_ddr_lat>; + qcom,cachemiss-ev = <0x17>; + qcom,stall-cycle-ev = <0x24>; + ddr3-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 1056000 MHZ_TO_MBPS(200, 8) >, + < 1401600 MHZ_TO_MBPS(451, 8) >, + < 1804800 MHZ_TO_MBPS(768, 8) >, + < 2016000 MHZ_TO_MBPS(931, 8) >; + }; + ddr4-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 902400 MHZ_TO_MBPS( 451, 8) >, + < 1401600 MHZ_TO_MBPS(1017, 8) >, + < 1804800 MHZ_TO_MBPS(1555, 8) >, + < 2016000 MHZ_TO_MBPS(1804, 8) >; + }; + }; + + cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + ddr3-opp { + operating-points-v2 = <&ddr3_bw_opp_table>; + qcom,ddr-type = ; + }; + ddr4-opp { + operating-points-v2 = <&ddr4_bw_opp_table>; + qcom,ddr-type = ; + }; + }; + + cpu0_computemon: qcom,cpu0-computemon { + compatible = "qcom,arm-cpu-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; + ddr3-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 614400 MHZ_TO_MBPS( 200, 8) >, + < 1305600 MHZ_TO_MBPS( 451, 8) >, + < 1804800 MHZ_TO_MBPS( 768, 8) >; + }; + ddr4-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 614400 MHZ_TO_MBPS( 300, 8) >, + < 1017600 MHZ_TO_MBPS( 451, 8) >, + < 1420000 MHZ_TO_MBPS( 547, 8) >, + < 1804800 MHZ_TO_MBPS( 768, 8) >; + }; + }; + + cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = + ; + qcom,active-only; + ddr3-opp { + operating-points-v2 = <&ddr3_bw_opp_table>; + qcom,ddr-type = ; + }; + ddr4-opp { + operating-points-v2 = <&ddr4_bw_opp_table>; + qcom,ddr-type = ; + }; + }; + + cpu4_computemon: qcom,cpu4-computemon { + compatible = "qcom,arm-cpu-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&cpu4_cpu_ddr_latfloor>; + ddr3-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 1056000 MHZ_TO_MBPS( 200, 8) >, + < 1401600 MHZ_TO_MBPS( 451, 8) >, + < 1804800 MHZ_TO_MBPS( 768, 8) >, + < 2016000 MHZ_TO_MBPS( 931, 8) >; + }; + ddr4-map { + qcom,ddr-type = ; + qcom,core-dev-table = + < 902400 MHZ_TO_MBPS( 300, 8) >, + < 1056000 MHZ_TO_MBPS( 547, 8) >, + < 1401680 MHZ_TO_MBPS( 768, 8) >, + < 1804800 MHZ_TO_MBPS(1017, 8) >, + < 2016000 MHZ_TO_MBPS(1804, 8) >; + }; + }; + + demux { + compatible = "qcom,demux"; + }; + + qfprom: qfprom@1b46018 { + compatible = "qcom,qfprom"; + reg = <0x1b46018 0x4>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + }; +}; + +#include "pmi632.dtsi" +#include "pm6125.dtsi" +#include "trinket-qupv3.dtsi" +#include "trinket-pinctrl.dtsi" +#include "trinket-ion.dtsi" +#include "pm6125-rpm-regulator.dtsi" +#include "trinket-regulator.dtsi" +#include "trinket-gdsc.dtsi" +#include "trinket-usb.dtsi" +#include "trinket-camera.dtsi" +#include "msm-arm-smmu-trinket.dtsi" +#include "trinket-qupv3.dtsi" +#include "trinket-coresight.dtsi" +#include "trinket-vidc.dtsi" +#include "trinket-pm.dtsi" +#include "trinket-gpu.dtsi" +#include "trinket-bus.dtsi" +#include "trinket-sde-pll.dtsi" +#include "trinket-sde.dtsi" +#include "msm-rdbg.dtsi" + +&pm6125_vadc { + pinctrl-names = "default"; + pinctrl-0 = <&camera_therm_default &emmc_therm_default>; + + rf_pa0_therm { + reg = ; + label = "rf_pa0_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + quiet_therm { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + camera_flash_therm { + reg = ; + label = "camera_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + emmc_ufs_therm { + reg = ; + label = "emmc_ufs_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm6125_gpios { + camera_therm { + camera_therm_default: camera_therm_default { + pins = "gpio3"; + bias-high-impedance; + }; + }; + + emmc_therm { + emmc_therm_default: emmc_therm_default { + pins = "gpio6"; + bias-high-impedance; + }; + }; + +}; + +&spmi_bus { + qcom,pm6125@0 { + pm6125_adc_tm_iio: adc_tm@3400 { + compatible = "qcom,adc-tm5-iio"; + reg = <0x3400 0x100>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + io-channels = <&pm6125_vadc ADC_GPIO1_PU2>, + <&pm6125_vadc ADC_GPIO3_PU2>; + + camera_flash_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + emmc_ufs_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + }; + }; +}; + +&pm6125_adc_tm { + io-channels = <&pm6125_vadc ADC_AMUX_THM1_PU2>, + <&pm6125_vadc ADC_AMUX_THM2_PU2>, + <&pm6125_vadc ADC_XO_THERM_PU2>; + + /* Channel nodes */ + rf_pa0_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + quiet_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pmi632_vadc { + pinctrl-names = "default"; + pinctrl-0 = <&conn_therm_default &skin_therm_default>; + + xo_therm { + status = "disabled"; + }; + + bat_therm { + qcom,lut-index = <1>; + }; + + bat_therm_30k { + qcom,lut-index = <1>; + }; + + bat_therm_400k { + qcom,lut-index = <1>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_therm { + reg = ; + label = "skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pmi632_gpios { + conn_therm { + conn_therm_default: conn_therm_default { + pins = "gpio1"; + bias-high-impedance; + }; + }; + + skin_therm { + skin_therm_default: skin_therm_default { + pins = "gpio3"; + bias-high-impedance; + }; + }; + +}; + +&pmi632_adc_tm { + io-channels = <&pmi632_vadc ADC_GPIO1_PU2>, + <&pmi632_vadc ADC_VBAT_SNS>, + <&pmi632_vadc ADC_GPIO2_PU2>; + + /* Channel nodes */ + conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + vbat_sns { + reg = ; + qcom,kernel-client; + qcom,scale-type = <0>; + qcom,prescaling = <3>; + }; + + skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&ufs_phy_gdsc { + status = "ok"; +}; + +&usb30_prim_gdsc { + status = "ok"; +}; + +&camss_cpp_gdsc { + status = "ok"; +}; + +&camss_top_gdsc { + status = "ok"; +}; + +&camss_vfe0_gdsc { + status = "ok"; +}; + +&camss_vfe1_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu1_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu0_gdsc { + status = "ok"; +}; + +&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc { + status = "ok"; +}; + +&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc { + status = "ok"; +}; + +&mdss_core_gdsc { + status = "ok"; +}; + +&gpu_cx_gdsc { + status = "ok"; +}; + +&gpu_gx_gdsc { + status = "ok"; +}; + +&vcodec0_gdsc { + qcom,support-hw-trigger; + status = "ok"; +}; + +&venus_gdsc { + status = "ok"; +}; + +&qupv3_se4_2uart { + status = "ok"; +}; + +&qupv3_se9_4uart { + status = "ok"; +}; + +&qupv3_se1_i2c { + status = "ok"; + fsa4480: fsa4480@43 { + compatible = "qcom,fsa4480-i2c"; + reg = <0x43>; + pinctrl-names = "default"; + pinctrl-0 = <&fsa_usbc_ana_en>; + }; +}; + +&msm_vidc { + qcom,cx-ipeak-data = <&cx_ipeak_lm 6>; + qcom,clock-freq-threshold = <460000000>; +}; + +#include "trinket-audio.dtsi" +#include "trinket-thermal.dtsi" + +&soc { + icnss: qcom,icnss@C800000 { + compatible = "qcom,icnss"; + reg = <0xC800000 0x800000>, + <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa"; + iommus = <&apps_smmu 0x80 0x1>; + interrupts = <0 358 0 /* CE0 */ >, + <0 359 0 /* CE1 */ >, + <0 360 0 /* CE2 */ >, + <0 361 0 /* CE3 */ >, + <0 362 0 /* CE4 */ >, + <0 363 0 /* CE5 */ >, + <0 364 0 /* CE6 */ >, + <0 365 0 /* CE7 */ >, + <0 366 0 /* CE8 */ >, + <0 367 0 /* CE9 */ >, + <0 368 0 /* CE10 */ >, + <0 369 0 /* CE11 */ >; + qcom,wlan-msa-memory = <0x100000>; + qcom,wlan-msa-fixed-region = <&wlan_msa_mem>; + vdd-cx-mx-supply = <&L8A>; + vdd-1.8-xo-supply = <&L16A>; + vdd-1.3-rfa-supply = <&L17A>; + vdd-3.3-ch0-supply = <&L23A>; + qcom,vdd-cx-mx-config = <640000 640000>; + qcom,vdd-3.3-ch0-config = <3000000 3312000>; + qcom,icnss-adc_tm = <&pmi632_adc_tm>; + io-channels = <&pmi632_vadc ADC_VBAT_SNS>; + io-channel-names = "icnss"; + qcom,smp2p_map_wlan_1_in { + interrupts-extended = <&smp2p_wlan_1_in 0 0>, + <&smp2p_wlan_1_in 1 0>; + interrupt-names = "qcom,smp2p-force-fatal-error", + "qcom,smp2p-early-crash-ind"; + }; + }; +}; + +&qupv3_se1_i2c { + status="ok"; + #include "pm8008.dtsi" +}; + +&tlmm { + pm8008_active: pm8008_active { + mux { + pins = "gpio49"; + function = "gpio"; + }; + + config { + pins = "gpio49"; + bias-pull-up; + output-high; + drive-strength = <2>; + }; + }; +}; + +&pm8008_gpios { + gpio1_active { + pm8008_gpio1_active: pm8008_gpio1_active { + pins = "gpio1"; + function = "normal"; + power-source = <1>; + bias-disable; + input-enable; + }; + }; +}; + +&pm8008_chip { + pinctrl-names = "default"; + pinctrl-0 = <&pm8008_active>; +}; + +&pm8008_regulators { + vdd_l1_l2-supply = <&S6A>; +}; + +&pm8008_9 { + /* GPIO1 pinctrl config */ + pinctrl-names = "default"; + pinctrl-0 = <&pm8008_gpio1_active>; +}; + +&L1P { + regulator-max-microvolt = <1200000>; + qcom,min-dropout-voltage = <100000>; +}; + +&L2P { + regulator-max-microvolt = <1104000>; + qcom,min-dropout-voltage = <100000>; +}; + +&L3P { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&L4P { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&L5P { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&L6P { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; +}; + +&L7P { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; +}; diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts deleted file mode 120000 index c2f22fc33811..000000000000 --- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts +++ /dev/null @@ -1 +0,0 @@ -sun8i-a23-q8-tablet.dts \ No newline at end of file diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts new file mode 100644 index 000000000000..b6958e8f2f01 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts @@ -0,0 +1,63 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a23.dtsi" +#include "sun8i-q8-common.dtsi" + +/ { + model = "Q8 A23 Tablet"; + compatible = "allwinner,q8-a23", "allwinner,sun8i-a23"; +}; + +&codec { + allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ + allwinner,audio-routing = + "Headphone", "HP", + "Headphone", "HPCOM", + "Speaker", "HP", + "MIC1", "Mic", + "MIC2", "Headset Mic", + "Mic", "MBIAS", + "Headset Mic", "HBIAS"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts deleted file mode 120000 index c2f22fc33811..000000000000 --- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts +++ /dev/null @@ -1 +0,0 @@ -sun8i-a23-q8-tablet.dts \ No newline at end of file diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts new file mode 100644 index 000000000000..b6958e8f2f01 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts @@ -0,0 +1,63 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a23.dtsi" +#include "sun8i-q8-common.dtsi" + +/ { + model = "Q8 A23 Tablet"; + compatible = "allwinner,q8-a23", "allwinner,sun8i-a23"; +}; + +&codec { + allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ + allwinner,audio-routing = + "Headphone", "HP", + "Headphone", "HPCOM", + "Speaker", "HP", + "MIC1", "Mic", + "MIC2", "Headset Mic", + "Mic", "MBIAS", + "Headset Mic", "HBIAS"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-a33-et-q8-v1.6.dts b/arch/arm/boot/dts/sun8i-a33-et-q8-v1.6.dts deleted file mode 120000 index 4519fd791a8f..000000000000 --- a/arch/arm/boot/dts/sun8i-a33-et-q8-v1.6.dts +++ /dev/null @@ -1 +0,0 @@ -sun8i-a33-q8-tablet.dts \ No newline at end of file diff --git a/arch/arm/boot/dts/sun8i-a33-et-q8-v1.6.dts b/arch/arm/boot/dts/sun8i-a33-et-q8-v1.6.dts new file mode 100644 index 000000000000..b0bc2360f8c4 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-a33-et-q8-v1.6.dts @@ -0,0 +1,50 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sun8i-q8-common.dtsi" + +/ { + model = "Q8 A33 Tablet"; + compatible = "allwinner,q8-a33", "allwinner,sun8i-a33"; +}; diff --git a/arch/arm/boot/dts/sun8i-a33-ippo-q8h-v1.2.dts b/arch/arm/boot/dts/sun8i-a33-ippo-q8h-v1.2.dts deleted file mode 120000 index 4519fd791a8f..000000000000 --- a/arch/arm/boot/dts/sun8i-a33-ippo-q8h-v1.2.dts +++ /dev/null @@ -1 +0,0 @@ -sun8i-a33-q8-tablet.dts \ No newline at end of file diff --git a/arch/arm/boot/dts/sun8i-a33-ippo-q8h-v1.2.dts b/arch/arm/boot/dts/sun8i-a33-ippo-q8h-v1.2.dts new file mode 100644 index 000000000000..b0bc2360f8c4 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-a33-ippo-q8h-v1.2.dts @@ -0,0 +1,50 @@ +/* + * Copyright 2015 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sun8i-q8-common.dtsi" + +/ { + model = "Q8 A33 Tablet"; + compatible = "allwinner,q8-a33", "allwinner,sun8i-a33"; +}; diff --git a/arch/arm/boot/install.sh b/arch/arm/boot/install.sh old mode 100644 new mode 100755 diff --git a/arch/arm/configs/sa515m-perf_defconfig b/arch/arm/configs/sa515m-perf_defconfig deleted file mode 120000 index f15877fab05a..000000000000 --- a/arch/arm/configs/sa515m-perf_defconfig +++ /dev/null @@ -1 +0,0 @@ -vendor/sa515m-perf_defconfig \ No newline at end of file diff --git a/arch/arm/configs/sa515m_defconfig b/arch/arm/configs/sa515m_defconfig deleted file mode 120000 index 16aa13f59770..000000000000 --- a/arch/arm/configs/sa515m_defconfig +++ /dev/null @@ -1 +0,0 @@ -vendor/sa515m_defconfig \ No newline at end of file diff --git a/arch/arm/configs/vendor/sa515m-perf_defconfig b/arch/arm/configs/sdxprairie-auto-perf_defconfig similarity index 98% rename from arch/arm/configs/vendor/sa515m-perf_defconfig rename to arch/arm/configs/sdxprairie-auto-perf_defconfig index c726917d76cb..489f15ac8fef 100644 --- a/arch/arm/configs/vendor/sa515m-perf_defconfig +++ b/arch/arm/configs/sdxprairie-auto-perf_defconfig @@ -156,10 +156,8 @@ CONFIG_VLAN_8021Q=y CONFIG_NET_SCHED=y CONFIG_NET_SCH_PRIO=y CONFIG_QRTR=y -CONFIG_QRTR_NODE_ID=2 CONFIG_QRTR_SMD=y CONFIG_QRTR_MHI=y -CONFIG_QRTR_MHI_DEV=y CONFIG_CAN=y CONFIG_QTI_CAN=y CONFIG_BT=y @@ -190,7 +188,6 @@ CONFIG_MTD_UBI=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_QSEECOM=y -CONFIG_EEPROM_AT24=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_SG=y @@ -248,8 +245,6 @@ CONFIG_SPI_QUP=y CONFIG_SPI_SPIDEV=m CONFIG_SPMI=y CONFIG_SLIMBUS=y -CONFIG_PPS=y -CONFIG_PPS_CLIENT_GPIO=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_SDXPRAIRIE=y CONFIG_GPIOLIB=y @@ -283,7 +278,6 @@ CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_DYNAMIC_MINORS=y CONFIG_SND_SOC=y -CONFIG_SND_SOC_TLV320AIC3X=y CONFIG_UHID=y CONFIG_HID_APPLE=y CONFIG_HID_ELECOM=y diff --git a/arch/arm/configs/vendor/sa515m_defconfig b/arch/arm/configs/sdxprairie-auto_defconfig similarity index 98% rename from arch/arm/configs/vendor/sa515m_defconfig rename to arch/arm/configs/sdxprairie-auto_defconfig index 5041ddd15f9f..5e5f5756b227 100644 --- a/arch/arm/configs/vendor/sa515m_defconfig +++ b/arch/arm/configs/sdxprairie-auto_defconfig @@ -156,10 +156,8 @@ CONFIG_VLAN_8021Q=y CONFIG_NET_SCHED=y CONFIG_NET_SCH_PRIO=y CONFIG_QRTR=y -CONFIG_QRTR_NODE_ID=2 CONFIG_QRTR_SMD=y CONFIG_QRTR_MHI=y -CONFIG_QRTR_MHI_DEV=y CONFIG_CAN=y CONFIG_QTI_CAN=y CONFIG_BT=y @@ -188,7 +186,6 @@ CONFIG_MTD_UBI=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_QSEECOM=y -CONFIG_EEPROM_AT24=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_SG=y @@ -248,8 +245,6 @@ CONFIG_SPI_QUP=y CONFIG_SPI_SPIDEV=m CONFIG_SPMI=y CONFIG_SLIMBUS=y -CONFIG_PPS=y -CONFIG_PPS_CLIENT_GPIO=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_SDXPRAIRIE=y CONFIG_GPIOLIB=y @@ -284,7 +279,6 @@ CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_DYNAMIC_MINORS=y CONFIG_SND_SOC=y -CONFIG_SND_SOC_TLV320AIC3X=y CONFIG_UHID=y CONFIG_HID_APPLE=y CONFIG_HID_ELECOM=y diff --git a/arch/arm/configs/sdxprairie-perf_defconfig b/arch/arm/configs/sdxprairie-perf_defconfig deleted file mode 120000 index 771ec5304d7d..000000000000 --- a/arch/arm/configs/sdxprairie-perf_defconfig +++ /dev/null @@ -1 +0,0 @@ -vendor/sdxprairie-perf_defconfig \ No newline at end of file diff --git a/arch/arm/configs/sdxprairie-perf_defconfig b/arch/arm/configs/sdxprairie-perf_defconfig new file mode 100644 index 000000000000..d629857a60fe --- /dev/null +++ b/arch/arm/configs/sdxprairie-perf_defconfig @@ -0,0 +1,464 @@ +CONFIG_LOCALVERSION="-perf" +CONFIG_AUDIT=y +# CONFIG_AUDITSYSCALL is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_SCHED=y +# CONFIG_FAIR_GROUP_SCHED is not set +CONFIG_RT_GROUP_SCHED=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_DEBUG=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_PID_NS is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +# CONFIG_SLUB_DEBUG is not set +CONFIG_SLAB_FREELIST_RANDOM=y +CONFIG_SLAB_FREELIST_HARDENED=y +CONFIG_PROFILING=y +CONFIG_CC_STACKPROTECTOR_STRONG=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_ARCH_QCOM=y +CONFIG_ARCH_SDXPRAIRIE=y +# CONFIG_VDSO is not set +CONFIG_PCI_MSM=y +CONFIG_PCI_MSM_MSI=y +CONFIG_PREEMPT=y +CONFIG_CMA=y +CONFIG_SECCOMP=y +CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_MSM=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=0 +# CONFIG_PM_WAKELOCKS_GC is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_SNMP=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SIP=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NF_CT_NETLINK_TIMEOUT=y +CONFIG_NF_CT_NETLINK_HELPER=y +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y +CONFIG_NETFILTER_XT_TARGET_LOG=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_NOTRACK=y +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +CONFIG_NETFILTER_XT_TARGET_SECMARK=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_DSCP=y +CONFIG_NETFILTER_XT_MATCH_ESP=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_IP_SET=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NATTYPE_MODULE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_TARGET_ECN=y +CONFIG_IP_NF_TARGET_TTL=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_SECURITY=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_MATCH_AH=y +CONFIG_IP6_NF_MATCH_FRAG=y +CONFIG_IP6_NF_MATCH_OPTS=y +CONFIG_IP6_NF_MATCH_HL=y +CONFIG_IP6_NF_MATCH_IPV6HEADER=y +CONFIG_IP6_NF_MATCH_MH=y +CONFIG_IP6_NF_MATCH_RT=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_BROUTE=y +CONFIG_BRIDGE_EBT_T_FILTER=y +CONFIG_BRIDGE_EBT_T_NAT=y +CONFIG_BRIDGE_EBT_ARP=y +CONFIG_BRIDGE_EBT_IP=y +CONFIG_BRIDGE_EBT_IP6=y +CONFIG_BRIDGE_EBT_ARPREPLY=y +CONFIG_BRIDGE_EBT_DNAT=y +CONFIG_BRIDGE_EBT_SNAT=y +CONFIG_BRIDGE=y +CONFIG_VLAN_8021Q=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_PRIO=y +CONFIG_QRTR=y +CONFIG_QRTR_SMD=y +CONFIG_QRTR_MHI=y +CONFIG_BT=y +# CONFIG_BT_BREDR is not set +# CONFIG_BT_LE is not set +# CONFIG_BT_DEBUGFS is not set +CONFIG_MSM_BT_POWER=y +# CONFIG_BTFM_SLIM is not set +CONFIG_CFG80211=y +CONFIG_CFG80211_DEBUGFS=y +CONFIG_CFG80211_INTERNAL_REGDB=y +CONFIG_CFG80211_WEXT=y +CONFIG_RFKILL=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=12 +CONFIG_MHI_BUS=y +CONFIG_MHI_UCI=y +CONFIG_MTD=y +CONFIG_MTD_TESTS=m +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_MSM_QPIC_NAND=y +CONFIG_MTD_NAND=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_QSEECOM=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_NETDEVICES=y +CONFIG_TUN=y +CONFIG_AQFWD=y +CONFIG_AQFWD_QCOM_IPA=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +CONFIG_KS8851=y +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_RMNET=y +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_AT803X_PHY=y +CONFIG_PPP=y +CONFIG_PPP_ASYNC=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_SMSC75XX=y +CONFIG_USB_NET_SMSC95XX=y +CONFIG_WCNSS_MEM_PRE_ALLOC=y +CONFIG_CLD_LL_CORE=y +CONFIG_CNSS2=y +CONFIG_CNSS2_QMI=y +CONFIG_CNSS_QCA6390=y +CONFIG_CNSS_UTILS=y +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_QPNP_POWER_ON=y +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_GPIO=m +CONFIG_SERIO_LIBPS2=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_HS=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MSM_LEGACY=y +CONFIG_DIAG_CHAR=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MSM_V2=y +CONFIG_SPI=y +CONFIG_SPI_QUP=y +CONFIG_SPI_SPIDEV=m +CONFIG_SPMI=y +CONFIG_SLIMBUS=y +CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_PINCTRL_SDXPRAIRIE=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_QCOM=y +CONFIG_QCOM_DLOAD_MODE=y +CONFIG_POWER_SUPPLY=y +CONFIG_QPNP_FG_GEN4=y +CONFIG_QPNP_SMB5=y +CONFIG_THERMAL=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_GOV_LOW_LIMITS=y +CONFIG_CPU_THERMAL=y +CONFIG_QCOM_SPMI_TEMP_ALARM=y +CONFIG_THERMAL_TSENS=y +CONFIG_QTI_AOP_REG_COOLING_DEVICE=y +CONFIG_QTI_QMI_COOLING_DEVICE=y +CONFIG_QTI_QMI_SENSOR=y +CONFIG_REGULATOR_COOLING_DEVICE=y +CONFIG_QTI_BCL_PMIC5=y +CONFIG_QTI_ADC_TM=y +CONFIG_MFD_SPMI_PMIC=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_RPMH=y +CONFIG_REGULATOR_STUB=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SOC=y +CONFIG_UHID=y +CONFIG_HID_APPLE=y +CONFIG_HID_ELECOM=y +CONFIG_HID_MAGICMOUSE=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MULTITOUCH=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MSM=y +CONFIG_USB_ACM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DEBUG=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_STORAGE_ALAUDA=y +CONFIG_USB_STORAGE_ONETOUCH=y +CONFIG_USB_STORAGE_KARMA=y +CONFIG_USB_STORAGE_CYPRESS_ATACB=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_MSM=y +CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_USB_LINK_LAYER_TEST=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_QCOM_EMU_PHY=y +CONFIG_USB_MSM_SSPHY_QMP=y +CONFIG_MSM_HSUSB_PHY=y +CONFIG_DUAL_ROLE_USB_INTF=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DEBUG_FILES=y +CONFIG_USB_GADGET_VBUS_DRAW=900 +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_UEVENT=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_DIAG=y +CONFIG_USB_CONFIGFS_F_CDEV=y +CONFIG_USB_CONFIGFS_F_GSI=y +CONFIG_USB_CONFIGFS_F_QDSS=y +CONFIG_USB_PD_POLICY=y +CONFIG_QPNP_USB_PDPHY=y +CONFIG_MMC=y +CONFIG_MMC_PERF_PROFILING=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_BLOCK_DEFERRED_RESUME=y +CONFIG_MMC_TEST=m +CONFIG_MMC_PARANOID_SD_INIT=y +CONFIG_MMC_CLKGATE=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_QPNP=y +CONFIG_DMADEVICES=y +CONFIG_QCOM_SPS_DMA=y +CONFIG_UIO=y +CONFIG_STAGING=y +CONFIG_ION=y +CONFIG_QPNP_REVID=y +CONFIG_SPS=y +CONFIG_SPS_SUPPORT_NDP_BAM=y +CONFIG_EP_PCIE=y +CONFIG_EP_PCIE_HW=y +CONFIG_USB_BAM=y +CONFIG_GSI_REGISTER_VERSION_2=y +CONFIG_MSM_MHI_DEV=y +CONFIG_IPA3=y +CONFIG_IPA_WDI_UNIFIED_API=y +CONFIG_IPA_ETH=y +CONFIG_AQC_IPA=y +CONFIG_AQC_IPA_PROXY_UC=y +CONFIG_RMNET_IPA3=y +CONFIG_ECM_IPA=y +CONFIG_RNDIS_IPA=y +CONFIG_IPA_UT=y +CONFIG_SPMI_PMIC_CLKDIV=y +CONFIG_MSM_CLK_AOP_QMP=y +CONFIG_MSM_CLK_RPMH=y +CONFIG_GCC_SDXPRAIRIE=y +CONFIG_DEBUGCC_SDXPRAIRIE=y +CONFIG_CLOCK_CPU_SDXPRAIRIE=y +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_QCOM=y +CONFIG_QCOM_APCS_IPC=y +CONFIG_MSM_QMP=y +CONFIG_IOMMU_IO_PGTABLE_FAST=y +CONFIG_ARM_SMMU=y +CONFIG_QCOM_LAZY_MAPPING=y +CONFIG_IOMMU_DEBUG=y +CONFIG_IOMMU_DEBUG_TRACKING=y +CONFIG_IOMMU_TESTS=y +CONFIG_RPMSG_CHAR=y +CONFIG_RPMSG_QCOM_GLINK_SMEM=y +CONFIG_QCOM_LLCC=y +CONFIG_QCOM_SDXPRAIRIE_LLCC=y +CONFIG_QCOM_QMI_HELPERS=y +CONFIG_QCOM_SMEM=y +CONFIG_QCOM_SCM=y +CONFIG_QCOM_MEMORY_DUMP_V2=y +CONFIG_QCOM_WATCHDOG_V2=y +CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y +CONFIG_QCOM_SMP2P=y +CONFIG_MSM_SERVICE_LOCATOR=y +CONFIG_MSM_SERVICE_NOTIFIER=y +CONFIG_MSM_SUBSYSTEM_RESTART=y +CONFIG_MSM_PIL=y +CONFIG_MSM_SYSMON_QMI_COMM=y +CONFIG_MSM_PIL_SSR_GENERIC=y +CONFIG_SETUP_SSR_NOTIF_TIMEOUTS=y +CONFIG_SSR_SYSMON_NOTIF_TIMEOUT=20000 +CONFIG_SSR_SUBSYS_NOTIF_TIMEOUT=20000 +CONFIG_PANIC_ON_SSR_NOTIF_TIMEOUT=y +CONFIG_MSM_BOOT_STATS=y +CONFIG_QCOM_DCC_V2=y +CONFIG_QCOM_SECURE_BUFFER=y +CONFIG_QCOM_EUD=y +CONFIG_QCOM_BUS_SCALING=y +CONFIG_QCOM_BUS_CONFIG_RPMH=y +CONFIG_QCOM_COMMAND_DB=y +CONFIG_QTI_RPMH_API=y +CONFIG_QCOM_GLINK=y +CONFIG_QCOM_GLINK_PKT=y +CONFIG_QTI_RPM_STATS_LOG=y +CONFIG_QCOM_SMCINVOKE=y +CONFIG_MSM_PM=y +CONFIG_QMP_DEBUGFS_CLIENT=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_ARM_MEMLAT_MON=y +CONFIG_DEVFREQ_GOV_MEMLAT=y +CONFIG_QCOM_DEVFREQ_DEVBW=y +CONFIG_EXTCON_QCOM_SPMI_MISC=y +CONFIG_IIO=y +CONFIG_QCOM_SPMI_ADC5=y +CONFIG_PWM=y +CONFIG_QCOM_SHOW_RESUME_IRQ=y +CONFIG_ANDROID=y +CONFIG_MSM_TZ_LOG=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_PANIC_ON_RECURSIVE_FAULT=y +CONFIG_PANIC_TIMEOUT=5 +# CONFIG_SCHED_DEBUG is not set +CONFIG_SCHEDSTATS=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_IPC_LOGGING=y +# CONFIG_FTRACE is not set +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y +CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y +CONFIG_CORESIGHT_STM=y +CONFIG_CORESIGHT_CTI=y +CONFIG_CORESIGHT_TPDA=y +CONFIG_CORESIGHT_TPDM=y +CONFIG_CORESIGHT_HWEVENT=y +CONFIG_CORESIGHT_DUMMY=y +CONFIG_CORESIGHT_REMOTE_ETM=y +CONFIG_CORESIGHT_REMOTE_ETM_DEFAULT_ENABLE=0 +CONFIG_CORESIGHT_TGU=y +CONFIG_CORESIGHT_EVENT=y +CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y +CONFIG_SECURITY=y +CONFIG_SECURITY_NETWORK=y +CONFIG_SECURITY_NETWORK_XFRM=y +CONFIG_HARDENED_USERCOPY=y +CONFIG_SECURITY_SELINUX=y +# CONFIG_SECURITY_SELINUX_AVC_STATS is not set +CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y +CONFIG_CRYPTO_DEV_QCRYPTO=y +CONFIG_CRYPTO_DEV_QCEDEV=y diff --git a/arch/arm/configs/sdxprairie_defconfig b/arch/arm/configs/sdxprairie_defconfig deleted file mode 120000 index 744d827b789a..000000000000 --- a/arch/arm/configs/sdxprairie_defconfig +++ /dev/null @@ -1 +0,0 @@ -vendor/sdxprairie_defconfig \ No newline at end of file diff --git a/arch/arm/configs/sdxprairie_defconfig b/arch/arm/configs/sdxprairie_defconfig new file mode 100644 index 000000000000..04b5b0310ce4 --- /dev/null +++ b/arch/arm/configs/sdxprairie_defconfig @@ -0,0 +1,493 @@ +CONFIG_AUDIT=y +# CONFIG_AUDITSYSCALL is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_SCHED=y +# CONFIG_FAIR_GROUP_SCHED is not set +CONFIG_RT_GROUP_SCHED=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_DEBUG=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_PID_NS is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB_FREELIST_RANDOM=y +CONFIG_SLAB_FREELIST_HARDENED=y +CONFIG_PROFILING=y +CONFIG_CC_STACKPROTECTOR_STRONG=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_ARCH_QCOM=y +CONFIG_ARCH_SDXPRAIRIE=y +# CONFIG_VDSO is not set +CONFIG_PCI_MSM=y +CONFIG_PCI_MSM_MSI=y +CONFIG_PREEMPT=y +CONFIG_CMA=y +CONFIG_SECCOMP=y +CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_MSM=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=0 +# CONFIG_PM_WAKELOCKS_GC is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V2=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_SNMP=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SIP=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NF_CT_NETLINK_TIMEOUT=y +CONFIG_NF_CT_NETLINK_HELPER=y +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y +CONFIG_NETFILTER_XT_TARGET_LOG=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_NOTRACK=y +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +CONFIG_NETFILTER_XT_TARGET_SECMARK=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_DSCP=y +CONFIG_NETFILTER_XT_MATCH_ESP=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_IP_SET=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NATTYPE_MODULE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_TARGET_ECN=y +CONFIG_IP_NF_TARGET_TTL=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_SECURITY=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_MATCH_AH=y +CONFIG_IP6_NF_MATCH_FRAG=y +CONFIG_IP6_NF_MATCH_OPTS=y +CONFIG_IP6_NF_MATCH_HL=y +CONFIG_IP6_NF_MATCH_IPV6HEADER=y +CONFIG_IP6_NF_MATCH_MH=y +CONFIG_IP6_NF_MATCH_RT=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_BROUTE=y +CONFIG_BRIDGE_EBT_T_FILTER=y +CONFIG_BRIDGE_EBT_T_NAT=y +CONFIG_BRIDGE_EBT_ARP=y +CONFIG_BRIDGE_EBT_IP=y +CONFIG_BRIDGE_EBT_IP6=y +CONFIG_BRIDGE_EBT_ARPREPLY=y +CONFIG_BRIDGE_EBT_DNAT=y +CONFIG_BRIDGE_EBT_SNAT=y +CONFIG_BRIDGE=y +CONFIG_VLAN_8021Q=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_PRIO=y +CONFIG_QRTR=y +CONFIG_QRTR_SMD=y +CONFIG_QRTR_MHI=y +CONFIG_BT=y +# CONFIG_BT_BREDR is not set +# CONFIG_BT_LE is not set +# CONFIG_BT_DEBUGFS is not set +CONFIG_MSM_BT_POWER=y +# CONFIG_BTFM_SLIM is not set +CONFIG_CFG80211=y +CONFIG_RFKILL=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=12 +CONFIG_MHI_BUS=y +CONFIG_MHI_DEBUG=y +CONFIG_MHI_UCI=y +CONFIG_MTD=y +CONFIG_MTD_TESTS=m +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_MSM_QPIC_NAND=y +CONFIG_MTD_NAND=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_QSEECOM=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_NETDEVICES=y +CONFIG_TUN=y +CONFIG_AQFWD=y +CONFIG_AQFWD_QCOM_IPA=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +CONFIG_KS8851=y +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_RMNET=y +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_AT803X_PHY=y +CONFIG_PPP=y +CONFIG_PPP_ASYNC=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_SMSC75XX=y +CONFIG_USB_NET_SMSC95XX=y +CONFIG_WCNSS_MEM_PRE_ALLOC=y +CONFIG_CLD_LL_CORE=y +CONFIG_CNSS2=y +CONFIG_CNSS2_DEBUG=y +CONFIG_CNSS2_QMI=y +CONFIG_CNSS_QCA6390=y +CONFIG_CNSS_UTILS=y +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_QPNP_POWER_ON=y +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_GPIO=m +CONFIG_SERIO_LIBPS2=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y +CONFIG_SERIAL_MSM_HS=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MSM_LEGACY=y +CONFIG_DIAG_CHAR=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MSM_V2=y +CONFIG_SPI=y +CONFIG_SPI_QUP=y +CONFIG_SPI_SPIDEV=m +CONFIG_SPMI=y +CONFIG_SLIMBUS=y +CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_PINCTRL_SDXPRAIRIE=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_QCOM=y +CONFIG_QCOM_DLOAD_MODE=y +CONFIG_POWER_SUPPLY=y +CONFIG_QPNP_FG_GEN4=y +CONFIG_QPNP_SMB5=y +CONFIG_THERMAL=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_GOV_LOW_LIMITS=y +CONFIG_CPU_THERMAL=y +CONFIG_QCOM_SPMI_TEMP_ALARM=y +CONFIG_THERMAL_TSENS=y +CONFIG_QTI_AOP_REG_COOLING_DEVICE=y +CONFIG_QTI_QMI_COOLING_DEVICE=y +CONFIG_QTI_QMI_SENSOR=y +CONFIG_REGULATOR_COOLING_DEVICE=y +CONFIG_QTI_BCL_PMIC5=y +CONFIG_QTI_ADC_TM=y +CONFIG_MFD_SPMI_PMIC=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_RPMH=y +CONFIG_REGULATOR_STUB=y +CONFIG_FB=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SOC=y +CONFIG_UHID=y +CONFIG_HID_APPLE=y +CONFIG_HID_ELECOM=y +CONFIG_HID_MAGICMOUSE=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MULTITOUCH=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ACM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DEBUG=y +CONFIG_USB_STORAGE_DATAFAB=y +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +CONFIG_USB_STORAGE_JUMPSHOT=y +CONFIG_USB_STORAGE_ALAUDA=y +CONFIG_USB_STORAGE_ONETOUCH=y +CONFIG_USB_STORAGE_KARMA=y +CONFIG_USB_STORAGE_CYPRESS_ATACB=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_MSM=y +CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_USB_LINK_LAYER_TEST=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_QCOM_EMU_PHY=y +CONFIG_USB_MSM_SSPHY_QMP=y +CONFIG_MSM_HSUSB_PHY=y +CONFIG_DUAL_ROLE_USB_INTF=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DEBUG_FILES=y +CONFIG_USB_GADGET_DEBUG_FS=y +CONFIG_USB_GADGET_VBUS_DRAW=900 +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_UEVENT=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_DIAG=y +CONFIG_USB_CONFIGFS_F_CDEV=y +CONFIG_USB_CONFIGFS_F_GSI=y +CONFIG_USB_CONFIGFS_F_QDSS=y +CONFIG_USB_PD_POLICY=y +CONFIG_QPNP_USB_PDPHY=y +CONFIG_MMC=y +CONFIG_MMC_PERF_PROFILING=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_BLOCK_DEFERRED_RESUME=y +CONFIG_MMC_TEST=m +CONFIG_MMC_RING_BUFFER=y +CONFIG_MMC_PARANOID_SD_INIT=y +CONFIG_MMC_CLKGATE=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_QPNP=y +CONFIG_DMADEVICES=y +CONFIG_QCOM_SPS_DMA=y +CONFIG_UIO=y +CONFIG_STAGING=y +CONFIG_ION=y +CONFIG_QPNP_REVID=y +CONFIG_SPS=y +CONFIG_SPS_SUPPORT_NDP_BAM=y +CONFIG_EP_PCIE=y +CONFIG_EP_PCIE_HW=y +CONFIG_USB_BAM=y +CONFIG_GSI_REGISTER_VERSION_2=y +CONFIG_MSM_MHI_DEV=y +CONFIG_IPA3=y +CONFIG_IPA_DEBUG=y +CONFIG_IPA_WDI_UNIFIED_API=y +CONFIG_IPA_ETH=y +CONFIG_IPA_ETH_DEBUG=y +CONFIG_AQC_IPA=y +CONFIG_AQC_IPA_PROXY_UC=y +CONFIG_AQC_IPA_DEBUG=y +CONFIG_RMNET_IPA3=y +CONFIG_ECM_IPA=y +CONFIG_RNDIS_IPA=y +CONFIG_IPA_UT=y +CONFIG_SPMI_PMIC_CLKDIV=y +CONFIG_MSM_CLK_AOP_QMP=y +CONFIG_MSM_CLK_RPMH=y +CONFIG_GCC_SDXPRAIRIE=y +CONFIG_DEBUGCC_SDXPRAIRIE=y +CONFIG_CLOCK_CPU_SDXPRAIRIE=y +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_QCOM=y +CONFIG_QCOM_APCS_IPC=y +CONFIG_MSM_QMP=y +CONFIG_IOMMU_IO_PGTABLE_FAST=y +CONFIG_ARM_SMMU=y +CONFIG_QCOM_LAZY_MAPPING=y +CONFIG_IOMMU_DEBUG=y +CONFIG_IOMMU_DEBUG_TRACKING=y +CONFIG_IOMMU_TESTS=y +CONFIG_RPMSG_CHAR=y +CONFIG_RPMSG_QCOM_GLINK_SMEM=y +CONFIG_QCOM_LLCC=y +CONFIG_QCOM_SDXPRAIRIE_LLCC=y +CONFIG_QCOM_QMI_HELPERS=y +CONFIG_QCOM_SMEM=y +CONFIG_QCOM_SCM=y +CONFIG_QCOM_MEMORY_DUMP_V2=y +CONFIG_QCOM_WATCHDOG_V2=y +CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y +CONFIG_QCOM_SMP2P=y +CONFIG_MSM_SERVICE_LOCATOR=y +CONFIG_MSM_SERVICE_NOTIFIER=y +CONFIG_MSM_SUBSYSTEM_RESTART=y +CONFIG_MSM_PIL=y +CONFIG_MSM_SYSMON_QMI_COMM=y +CONFIG_MSM_PIL_SSR_GENERIC=y +CONFIG_SETUP_SSR_NOTIF_TIMEOUTS=y +CONFIG_SSR_SYSMON_NOTIF_TIMEOUT=20000 +CONFIG_SSR_SUBSYS_NOTIF_TIMEOUT=20000 +CONFIG_PANIC_ON_SSR_NOTIF_TIMEOUT=y +CONFIG_MSM_BOOT_STATS=y +CONFIG_QCOM_DCC_V2=y +CONFIG_QCOM_SECURE_BUFFER=y +CONFIG_QCOM_EUD=y +CONFIG_QCOM_BUS_SCALING=y +CONFIG_QCOM_BUS_CONFIG_RPMH=y +CONFIG_QCOM_COMMAND_DB=y +CONFIG_QTI_RPMH_API=y +CONFIG_QCOM_GLINK=y +CONFIG_QCOM_GLINK_PKT=y +CONFIG_QTI_RPM_STATS_LOG=y +CONFIG_QCOM_SMCINVOKE=y +CONFIG_MSM_PM=y +CONFIG_QMP_DEBUGFS_CLIENT=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_ARM_MEMLAT_MON=y +CONFIG_DEVFREQ_GOV_MEMLAT=y +CONFIG_QCOM_DEVFREQ_DEVBW=y +CONFIG_EXTCON_QCOM_SPMI_MISC=y +CONFIG_IIO=y +CONFIG_QCOM_SPMI_ADC5=y +CONFIG_PWM=y +CONFIG_QCOM_SHOW_RESUME_IRQ=y +CONFIG_ANDROID=y +CONFIG_MSM_TZ_LOG=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_INFO=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_PAGEALLOC=y +CONFIG_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y +CONFIG_DEBUG_STACK_USAGE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_PANIC_ON_RECURSIVE_FAULT=y +CONFIG_PANIC_TIMEOUT=5 +CONFIG_SCHEDSTATS=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_SPINLOCK_PANIC_ON_BUG=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_ATOMIC_SLEEP=y +CONFIG_DEBUG_LIST=y +CONFIG_DEBUG_CREDENTIALS=y +CONFIG_FAULT_INJECTION=y +CONFIG_FAIL_PAGE_ALLOC=y +CONFIG_FAULT_INJECTION_DEBUG_FS=y +CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y +CONFIG_IPC_LOGGING=y +CONFIG_QCOM_RTB=y +CONFIG_FUNCTION_TRACER=y +CONFIG_PREEMPTIRQ_EVENTS=y +CONFIG_IRQSOFF_TRACER=y +CONFIG_PREEMPT_TRACER=y +CONFIG_LKDTM=m +CONFIG_PANIC_ON_DATA_CORRUPTION=y +CONFIG_DEBUG_USER=y +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y +CONFIG_CORESIGHT_SOURCE_ETM3X=y +CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y +CONFIG_CORESIGHT_STM=y +CONFIG_CORESIGHT_CTI=y +CONFIG_CORESIGHT_TPDA=y +CONFIG_CORESIGHT_TPDM=y +CONFIG_CORESIGHT_HWEVENT=y +CONFIG_CORESIGHT_DUMMY=y +CONFIG_CORESIGHT_REMOTE_ETM=y +CONFIG_CORESIGHT_REMOTE_ETM_DEFAULT_ENABLE=0 +CONFIG_CORESIGHT_TGU=y +CONFIG_CORESIGHT_EVENT=y +CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y +CONFIG_SECURITY=y +CONFIG_SECURITY_NETWORK=y +CONFIG_SECURITY_NETWORK_XFRM=y +CONFIG_HARDENED_USERCOPY=y +CONFIG_HARDENED_USERCOPY_PAGESPAN=y +CONFIG_SECURITY_SELINUX=y +# CONFIG_SECURITY_SELINUX_AVC_STATS is not set +CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y +CONFIG_CRYPTO_DEV_QCRYPTO=y +CONFIG_CRYPTO_DEV_QCEDEV=y +CONFIG_XZ_DEC=y diff --git a/arch/arm/configs/vendor/qcs403-perf_defconfig b/arch/arm/configs/vendor/qcs403-perf_defconfig deleted file mode 100644 index 4c5728f6771c..000000000000 --- a/arch/arm/configs/vendor/qcs403-perf_defconfig +++ /dev/null @@ -1,369 +0,0 @@ -CONFIG_POSIX_MQUEUE=y -CONFIG_AUDIT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_SCHED_WALT=y -CONFIG_TASKSTATS=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_RCU_EXPERT=y -CONFIG_RCU_FAST_NO_HZ=y -CONFIG_RCU_NOCB_CPU=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_CGROUPS=y -CONFIG_CGROUP_SCHED=y -CONFIG_RT_GROUP_SCHED=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_NAMESPACES=y -# CONFIG_UTS_NS is not set -# CONFIG_PID_NS is not set -CONFIG_DEFAULT_USE_ENERGY_AWARE=y -CONFIG_RELAY=y -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_KALLSYMS_ALL=y -CONFIG_EMBEDDED=y -# CONFIG_SLUB_DEBUG is not set -CONFIG_PROFILING=y -CONFIG_CC_STACKPROTECTOR_STRONG=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SIG=y -CONFIG_MODULE_SIG_FORCE=y -CONFIG_MODULE_SIG_SHA512=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_ARCH_QCOM=y -CONFIG_ARCH_QCS403=y -# CONFIG_VDSO is not set -CONFIG_SMP=y -CONFIG_ARM_PSCI=y -CONFIG_PREEMPT=y -CONFIG_CMA=y -CONFIG_ZSMALLOC=y -CONFIG_SECCOMP=y -CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_IDLE=y -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_KERNEL_MODE_NEON=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_PM_AUTOSLEEP=y -CONFIG_PM_WAKELOCKS=y -CONFIG_PM_WAKELOCKS_LIMIT=0 -# CONFIG_PM_WAKELOCKS_GC is not set -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET6_XFRM_MODE_TUNNEL is not set -# CONFIG_INET6_XFRM_MODE_BEET is not set -# CONFIG_IPV6_SIT is not set -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_NETFILTER=y -CONFIG_NETFILTER_NETLINK_QUEUE=y -CONFIG_NETFILTER_NETLINK_LOG=y -CONFIG_NF_CONNTRACK=y -# CONFIG_NF_CONNTRACK_PROCFS is not set -CONFIG_NF_CONNTRACK_EVENTS=y -# CONFIG_NF_CT_PROTO_DCCP is not set -# CONFIG_NF_CT_PROTO_SCTP is not set -CONFIG_NF_CONNTRACK_FTP=y -CONFIG_NF_CONNTRACK_TFTP=y -CONFIG_NF_CT_NETLINK=y -CONFIG_NF_CONNTRACK_IPV4=y -CONFIG_NF_LOG_IPV4=y -CONFIG_IP_NF_IPTABLES=y -CONFIG_IP_NF_FILTER=y -CONFIG_IP_NF_TARGET_REJECT=y -CONFIG_IP_NF_NAT=y -CONFIG_IP_NF_TARGET_MASQUERADE=y -CONFIG_IP_NF_TARGET_NETMAP=y -CONFIG_IP_NF_TARGET_REDIRECT=y -CONFIG_IP_NF_MANGLE=y -CONFIG_IP_NF_RAW=y -CONFIG_IP_NF_SECURITY=y -CONFIG_IP_NF_ARPTABLES=y -CONFIG_IP_NF_ARPFILTER=y -CONFIG_IP_NF_ARP_MANGLE=y -CONFIG_NF_CONNTRACK_IPV6=y -CONFIG_NF_LOG_IPV6=y -CONFIG_IP6_NF_IPTABLES=y -CONFIG_IP6_NF_FILTER=y -CONFIG_IP6_NF_TARGET_REJECT=y -CONFIG_IP6_NF_MANGLE=y -CONFIG_IP6_NF_RAW=y -CONFIG_BRIDGE_NF_EBTABLES=y -CONFIG_BRIDGE_EBT_BROUTE=y -CONFIG_BRIDGE=y -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_PRIO=y -CONFIG_NET_EMATCH=y -CONFIG_NET_CLS_ACT=y -CONFIG_QRTR=y -CONFIG_QRTR_SMD=y -CONFIG_BT=y -# CONFIG_BT_BREDR is not set -# CONFIG_BT_LE is not set -# CONFIG_BT_DEBUGFS is not set -CONFIG_MSM_BT_POWER=y -CONFIG_CFG80211=y -CONFIG_CFG80211_INTERNAL_REGDB=y -CONFIG_RFKILL=y -CONFIG_NTAG_NQ=y -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_DMA_CMA=y -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_MSM_QPIC_NAND=y -CONFIG_MTD_NAND=y -CONFIG_MTD_UBI=y -CONFIG_ZRAM=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_QSEECOM=y -CONFIG_UID_SYS_STATS=y -CONFIG_QPNP_MISC=y -CONFIG_NETDEVICES=y -CONFIG_DUMMY=y -CONFIG_PHYLIB=y -CONFIG_AT803X_PHY=y -CONFIG_PPP=y -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_ASYNC=y -CONFIG_WCNSS_MEM_PRE_ALLOC=y -CONFIG_CLD_LL_CORE=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_KEYRESET=y -CONFIG_KEYBOARD_GPIO=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_MISC=y -CONFIG_INPUT_QPNP_POWER_ON=y -CONFIG_INPUT_UINPUT=y -CONFIG_INPUT_GPIO=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_DEVMEM is not set -CONFIG_SERIAL_MSM_HS=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MSM_LEGACY=y -CONFIG_DIAG_CHAR=y -CONFIG_MSM_ADSPRPC=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MUX=y -CONFIG_I2C_MSM_V2=y -CONFIG_SPI=y -CONFIG_SPI_QUP=y -CONFIG_SPI_SPIDEV=y -CONFIG_SPMI=y -CONFIG_SLIMBUS_MSM_NGD=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PINCTRL_QCS405=y -CONFIG_FRAGMENTED_GPIO_ADDRESS_SPACE=y -CONFIG_PINCTRL_QCOM_SPMI_PMIC=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_QCOM=y -CONFIG_QCOM_DLOAD_MODE=y -CONFIG_POWER_SUPPLY=y -CONFIG_SMB1351_USB_CHARGER=y -CONFIG_THERMAL=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_GOV_LOW_LIMITS=y -CONFIG_CPU_THERMAL=y -CONFIG_DEVFREQ_THERMAL=y -CONFIG_THERMAL_TSENS=y -CONFIG_QTI_VIRTUAL_SENSOR=y -CONFIG_QTI_QMI_COOLING_DEVICE=y -CONFIG_REGULATOR_COOLING_DEVICE=y -CONFIG_QTI_ADC_TM=y -CONFIG_QTI_RPM_SMD_COOLING_DEVICE=y -CONFIG_MFD_SPMI_PMIC=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_FAN53555=y -CONFIG_REGULATOR_CPR=y -CONFIG_REGULATOR_MEM_ACC=y -CONFIG_REGULATOR_RPM_SMD=y -CONFIG_REGULATOR_SPM=y -CONFIG_REGULATOR_STUB=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_DYNAMIC_MINORS=y -CONFIG_SND_USB_AUDIO=y -CONFIG_SND_SOC=y -CONFIG_HIDRAW=y -# CONFIG_USB_HID is not set -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_MSM=y -CONFIG_USB_EHSET_TEST_FIXTURE=y -CONFIG_USB_LINK_LAYER_TEST=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_MSM_SNPS_FEMTO_PHY=y -CONFIG_USB_MSM_SSPHY=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_VBUS_DRAW=900 -CONFIG_USB_CONFIGFS=y -CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_USB_CONFIGFS_UEVENT=y -CONFIG_USB_CONFIGFS_F_DIAG=y -CONFIG_MMC=y -CONFIG_MMC_PERF_PROFILING=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_BLOCK_DEFERRED_RESUME=y -CONFIG_MMC_TEST=m -CONFIG_MMC_PARANOID_SD_INIT=y -CONFIG_MMC_CLKGATE=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_MSM=y -CONFIG_MMC_CQ_HCI=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_PCA9956B=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_QPNP=y -CONFIG_DMADEVICES=y -CONFIG_QCOM_SPS_DMA=y -CONFIG_SYNC_FILE=y -CONFIG_UIO=y -CONFIG_STAGING=y -CONFIG_ASHMEM=y -CONFIG_ION=y -CONFIG_QPNP_REVID=y -CONFIG_SPS=y -CONFIG_SPS_SUPPORT_NDP_BAM=y -CONFIG_COMMON_CLK_QCOM=y -CONFIG_QCOM_CLK_SMD_RPM=y -CONFIG_SPMI_PMIC_CLKDIV=y -CONFIG_MDM_DEBUGCC_QCS405=y -CONFIG_CLOCK_CPU_QCS405=y -CONFIG_QCS_CMN_BLK_PLL=y -CONFIG_HWSPINLOCK=y -CONFIG_HWSPINLOCK_QCOM=y -CONFIG_MAILBOX=y -CONFIG_QCOM_APCS_IPC=y -CONFIG_ARM_SMMU=y -CONFIG_QCOM_LAZY_MAPPING=y -CONFIG_RPMSG_CHAR=y -CONFIG_RPMSG_QCOM_GLINK_RPM=y -CONFIG_RPMSG_QCOM_GLINK_SMEM=y -CONFIG_RPMSG_QCOM_SMD=y -CONFIG_QCOM_QMI_HELPERS=y -CONFIG_QCOM_SMEM=y -CONFIG_QCOM_SMD_RPM=y -CONFIG_MSM_SPM=y -CONFIG_MSM_L2_SPM=y -CONFIG_QCOM_SCM=y -CONFIG_QCOM_MEMORY_DUMP_V2=y -CONFIG_QCOM_WATCHDOG_V2=y -CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y -CONFIG_QCOM_WDOG_IPI_ENABLE=y -CONFIG_QCOM_SMP2P=y -CONFIG_MSM_SERVICE_LOCATOR=y -CONFIG_MSM_SERVICE_NOTIFIER=y -CONFIG_MSM_SUBSYSTEM_RESTART=y -CONFIG_MSM_PIL=y -CONFIG_MSM_SYSMON_QMI_COMM=y -CONFIG_MSM_PIL_SSR_GENERIC=y -CONFIG_MSM_BOOT_STATS=y -CONFIG_QCOM_DCC_V2=y -CONFIG_ICNSS=y -CONFIG_ICNSS_QMI=y -CONFIG_QCOM_BUS_SCALING=y -CONFIG_QCOM_EARLY_RANDOM=y -CONFIG_MSM_TZ_SMMU=y -CONFIG_QCOM_GLINK=y -CONFIG_QCOM_GLINK_PKT=y -CONFIG_QTI_RPM_STATS_LOG=y -CONFIG_MSM_CDSP_LOADER=y -CONFIG_QCOM_SMCINVOKE=y -CONFIG_QCOM_SMP2P_SLEEPSTATE=y -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -CONFIG_QCOM_BIMC_BWMON=y -CONFIG_ARM_MEMLAT_MON=y -CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y -CONFIG_DEVFREQ_GOV_MEMLAT=y -CONFIG_QCOM_DEVFREQ_DEVBW=y -CONFIG_EXTCON_USB_GPIO=y -CONFIG_IIO=y -CONFIG_QCOM_SPMI_ADC5=y -CONFIG_PWM=y -CONFIG_PWM_QTI_LPG=y -CONFIG_QTI_MPM=y -CONFIG_PHY_QCOM_UFS=y -CONFIG_ANDROID=y -CONFIG_ANDROID_BINDER_IPC=y -CONFIG_DAX=y -CONFIG_MSM_TZ_LOG=y -CONFIG_QUOTA=y -CONFIG_QUOTA_NETLINK_INTERFACE=y -# CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_QFMT_V2=y -CONFIG_FUSE_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_SQUASHFS=y -CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y -CONFIG_SQUASHFS_XATTR=y -# CONFIG_SQUASHFS_ZLIB is not set -CONFIG_SQUASHFS_XZ=y -CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y -# CONFIG_NETWORK_FILESYSTEMS is not set -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_FS=y -CONFIG_PANIC_ON_RECURSIVE_FAULT=y -CONFIG_PANIC_ON_OOPS=y -CONFIG_PANIC_TIMEOUT=5 -CONFIG_STACKTRACE=y -# CONFIG_FTRACE is not set -CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y -CONFIG_SECURITY=y -CONFIG_SECURITY_NETWORK=y -CONFIG_LSM_MMAP_MIN_ADDR=4096 -CONFIG_HARDENED_USERCOPY=y -CONFIG_SECURITY_SELINUX=y -CONFIG_CRYPTO_AUTHENC=y -CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CTR=y -CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/vendor/qcs405-perf_defconfig b/arch/arm/configs/vendor/qcs405-perf_defconfig index 8042c3000e0d..1ab1d99cd67d 100644 --- a/arch/arm/configs/vendor/qcs405-perf_defconfig +++ b/arch/arm/configs/vendor/qcs405-perf_defconfig @@ -37,7 +37,6 @@ CONFIG_MODULE_SIG_SHA512=y CONFIG_PARTITION_ADVANCED=y CONFIG_ARCH_QCOM=y CONFIG_ARCH_QCS405=y -CONFIG_ARCH_QCS403=y # CONFIG_VDSO is not set CONFIG_SMP=y CONFIG_ARM_PSCI=y diff --git a/arch/arm/configs/vendor/qcs405_defconfig b/arch/arm/configs/vendor/qcs405_defconfig index 4a06454d8699..f8fcf714bd37 100644 --- a/arch/arm/configs/vendor/qcs405_defconfig +++ b/arch/arm/configs/vendor/qcs405_defconfig @@ -39,7 +39,6 @@ CONFIG_MODULE_SIG_SHA512=y CONFIG_PARTITION_ADVANCED=y CONFIG_ARCH_QCOM=y CONFIG_ARCH_QCS405=y -CONFIG_ARCH_QCS403=y # CONFIG_VDSO is not set CONFIG_SMP=y CONFIG_ARM_PSCI=y diff --git a/arch/arm64/configs/vendor/qcs403-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-auto-perf_defconfig similarity index 56% rename from arch/arm64/configs/vendor/qcs403-perf_defconfig rename to arch/arm/configs/vendor/sdxprairie-auto-perf_defconfig index cf04736e1c47..489f15ac8fef 100644 --- a/arch/arm64/configs/vendor/qcs403-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-auto-perf_defconfig @@ -1,162 +1,128 @@ -CONFIG_POSIX_MQUEUE=y +CONFIG_LOCALVERSION="-perf" CONFIG_AUDIT=y +# CONFIG_AUDITSYSCALL is not set CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_SCHED_WALT=y -CONFIG_TASKSTATS=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_RCU_EXPERT=y -CONFIG_RCU_FAST_NO_HZ=y -CONFIG_RCU_NOCB_CPU=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_CGROUPS=y CONFIG_CGROUP_SCHED=y +# CONFIG_FAIR_GROUP_SCHED is not set CONFIG_RT_GROUP_SCHED=y CONFIG_CGROUP_FREEZER=y CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_DEBUG=y CONFIG_NAMESPACES=y # CONFIG_UTS_NS is not set # CONFIG_PID_NS is not set -CONFIG_DEFAULT_USE_ENERGY_AWARE=y +CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_KALLSYMS_ALL=y CONFIG_EMBEDDED=y +# CONFIG_SLUB_DEBUG is not set +CONFIG_SLAB_FREELIST_RANDOM=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_PROFILING=y CONFIG_CC_STACKPROTECTOR_STRONG=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SIG=y -CONFIG_MODULE_SIG_FORCE=y -CONFIG_MODULE_SIG_SHA512=y CONFIG_PARTITION_ADVANCED=y CONFIG_ARCH_QCOM=y -CONFIG_ARCH_QCS403=y -CONFIG_PCI=y +CONFIG_ARCH_SDXPRAIRIE=y +# CONFIG_VDSO is not set CONFIG_PCI_MSM=y CONFIG_PCI_MSM_MSI=y -CONFIG_NR_CPUS=4 CONFIG_PREEMPT=y CONFIG_CMA=y -CONFIG_ZSMALLOC=y CONFIG_SECCOMP=y -# CONFIG_HARDEN_BRANCH_PREDICTOR is not set -CONFIG_ARMV8_DEPRECATED=y -CONFIG_SWP_EMULATION=y -CONFIG_CP15_BARRIER_EMULATION=y -CONFIG_SETEND_EMULATION=y -CONFIG_ARM64_SW_TTBR0_PAN=y -CONFIG_RANDOMIZE_BASE=y -CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y +CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_MSM=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_COMPAT=y CONFIG_PM_AUTOSLEEP=y CONFIG_PM_WAKELOCKS=y CONFIG_PM_WAKELOCKS_LIMIT=0 # CONFIG_PM_WAKELOCKS_GC is not set -CONFIG_CPU_IDLE=y -CONFIG_ARM_CPUIDLE=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_MSM=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y -CONFIG_XFRM_USER=y -CONFIG_XFRM_STATISTICS=y -CONFIG_NET_KEY=y CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_INET_AH=y -CONFIG_INET_ESP=y -CONFIG_INET_IPCOMP=y -# CONFIG_INET_XFRM_MODE_BEET is not set -CONFIG_INET_DIAG_DESTROY=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -CONFIG_IPV6_OPTIMISTIC_DAD=y -CONFIG_INET6_AH=y -CONFIG_INET6_ESP=y -CONFIG_INET6_IPCOMP=y -CONFIG_IPV6_MIP6=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V2=y CONFIG_IPV6_MULTIPLE_TABLES=y CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y CONFIG_NETFILTER=y CONFIG_NF_CONNTRACK=y CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y CONFIG_NF_CONNTRACK_AMANDA=y CONFIG_NF_CONNTRACK_FTP=y CONFIG_NF_CONNTRACK_H323=y CONFIG_NF_CONNTRACK_IRC=y CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_SNMP=y CONFIG_NF_CONNTRACK_PPTP=y -CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_SIP=y CONFIG_NF_CONNTRACK_TFTP=y CONFIG_NF_CT_NETLINK=y -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y -CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NF_CT_NETLINK_TIMEOUT=y +CONFIG_NF_CT_NETLINK_HELPER=y +CONFIG_NETFILTER_NETLINK_GLUE_CT=y CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y -CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y CONFIG_NETFILTER_XT_TARGET_LOG=y CONFIG_NETFILTER_XT_TARGET_MARK=y CONFIG_NETFILTER_XT_TARGET_NFLOG=y CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y CONFIG_NETFILTER_XT_TARGET_NOTRACK=y -CONFIG_NETFILTER_XT_TARGET_TEE=y CONFIG_NETFILTER_XT_TARGET_TPROXY=y CONFIG_NETFILTER_XT_TARGET_TRACE=y CONFIG_NETFILTER_XT_TARGET_SECMARK=y CONFIG_NETFILTER_XT_TARGET_TCPMSS=y -CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=y CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y CONFIG_NETFILTER_XT_MATCH_CONNMARK=y CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y CONFIG_NETFILTER_XT_MATCH_DSCP=y CONFIG_NETFILTER_XT_MATCH_ESP=y -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y -CONFIG_NETFILTER_XT_MATCH_HELPER=y CONFIG_NETFILTER_XT_MATCH_IPRANGE=y -CONFIG_NETFILTER_XT_MATCH_LENGTH=y CONFIG_NETFILTER_XT_MATCH_LIMIT=y -CONFIG_NETFILTER_XT_MATCH_MAC=y -CONFIG_NETFILTER_XT_MATCH_MARK=y CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y -CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y -CONFIG_NETFILTER_XT_MATCH_QUOTA=y -CONFIG_NETFILTER_XT_MATCH_QUOTA2=y CONFIG_NETFILTER_XT_MATCH_STATE=y -CONFIG_NETFILTER_XT_MATCH_STATISTIC=y -CONFIG_NETFILTER_XT_MATCH_STRING=y -CONFIG_NETFILTER_XT_MATCH_TIME=y -CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_IP_SET=y CONFIG_NF_CONNTRACK_IPV4=y CONFIG_IP_NF_IPTABLES=y CONFIG_IP_NF_MATCH_AH=y CONFIG_IP_NF_MATCH_ECN=y -CONFIG_IP_NF_MATCH_RPFILTER=y CONFIG_IP_NF_MATCH_TTL=y CONFIG_IP_NF_FILTER=y CONFIG_IP_NF_TARGET_REJECT=y CONFIG_IP_NF_NAT=y CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NATTYPE_MODULE=y CONFIG_IP_NF_TARGET_NETMAP=y CONFIG_IP_NF_TARGET_REDIRECT=y CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_TARGET_ECN=y +CONFIG_IP_NF_TARGET_TTL=y CONFIG_IP_NF_RAW=y CONFIG_IP_NF_SECURITY=y CONFIG_IP_NF_ARPTABLES=y @@ -164,7 +130,13 @@ CONFIG_IP_NF_ARPFILTER=y CONFIG_IP_NF_ARP_MANGLE=y CONFIG_NF_CONNTRACK_IPV6=y CONFIG_IP6_NF_IPTABLES=y -CONFIG_IP6_NF_MATCH_RPFILTER=y +CONFIG_IP6_NF_MATCH_AH=y +CONFIG_IP6_NF_MATCH_FRAG=y +CONFIG_IP6_NF_MATCH_OPTS=y +CONFIG_IP6_NF_MATCH_HL=y +CONFIG_IP6_NF_MATCH_IPV6HEADER=y +CONFIG_IP6_NF_MATCH_MH=y +CONFIG_IP6_NF_MATCH_RT=y CONFIG_IP6_NF_FILTER=y CONFIG_IP6_NF_TARGET_REJECT=y CONFIG_IP6_NF_MANGLE=y @@ -179,60 +151,43 @@ CONFIG_BRIDGE_EBT_IP6=y CONFIG_BRIDGE_EBT_ARPREPLY=y CONFIG_BRIDGE_EBT_DNAT=y CONFIG_BRIDGE_EBT_SNAT=y -CONFIG_L2TP=y -CONFIG_L2TP_V3=y -CONFIG_L2TP_IP=y -CONFIG_L2TP_ETH=y CONFIG_BRIDGE=y +CONFIG_VLAN_8021Q=y CONFIG_NET_SCHED=y -CONFIG_NET_SCH_HTB=y CONFIG_NET_SCH_PRIO=y -CONFIG_NET_CLS_FW=y -CONFIG_NET_CLS_U32=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_FLOW=y -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=y -CONFIG_NET_EMATCH_NBYTE=y -CONFIG_NET_EMATCH_U32=y -CONFIG_NET_EMATCH_META=y -CONFIG_NET_EMATCH_TEXT=y -CONFIG_NET_CLS_ACT=y CONFIG_QRTR=y CONFIG_QRTR_SMD=y -CONFIG_QRTR_USB=y -CONFIG_RMNET_USB=y +CONFIG_QRTR_MHI=y +CONFIG_CAN=y +CONFIG_QTI_CAN=y CONFIG_BT=y # CONFIG_BT_BREDR is not set # CONFIG_BT_LE is not set # CONFIG_BT_DEBUGFS is not set CONFIG_MSM_BT_POWER=y +# CONFIG_BTFM_SLIM is not set CONFIG_CFG80211=y +CONFIG_CFG80211_DEBUGFS=y CONFIG_CFG80211_INTERNAL_REGDB=y -CONFIG_MAC80211=m -CONFIG_MAC80211_RC_MINSTREL_VHT=y -CONFIG_MAC80211_DEBUGFS=y +CONFIG_CFG80211_WEXT=y CONFIG_RFKILL=y -CONFIG_NTAG_NQ=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=12 CONFIG_MHI_BUS=y -CONFIG_MHI_QCOM=y -CONFIG_MHI_NETDEV=y CONFIG_MHI_UCI=y CONFIG_MTD=y +CONFIG_MTD_TESTS=m CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y CONFIG_MTD_MSM_QPIC_NAND=y CONFIG_MTD_NAND=y CONFIG_MTD_UBI=y -CONFIG_ZRAM=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_QSEECOM=y -CONFIG_UID_SYS_STATS=y -CONFIG_QPNP_MISC=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_SG=y @@ -240,137 +195,103 @@ CONFIG_CHR_DEV_SCH=y CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_SCSI_UFSHCD=y -CONFIG_SCSI_UFSHCD_PLATFORM=y -CONFIG_SCSI_UFS_QCOM=y -CONFIG_SCSI_UFSHCD_CMD_LOGGING=y -CONFIG_MD=y -CONFIG_BLK_DEV_DM=y -CONFIG_DM_CRYPT=y -CONFIG_DM_VERITY=y -CONFIG_DM_VERITY_FEC=y CONFIG_NETDEVICES=y -CONFIG_DUMMY=y CONFIG_TUN=y +CONFIG_AQFWD=y +CONFIG_AQFWD_QCOM_IPA=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +CONFIG_KS8851=y +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_RMNET=y +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set CONFIG_AT803X_PHY=y +CONFIG_MICREL_PHY=y CONFIG_PPP=y -CONFIG_PPP_BSDCOMP=y -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=y -CONFIG_PPP_MULTILINK=y -CONFIG_PPPOE=y -CONFIG_PPPOL2TP=y -CONFIG_PPPOLAC=y -CONFIG_PPPOPNS=y CONFIG_PPP_ASYNC=y -CONFIG_PPP_SYNC_TTY=y CONFIG_USB_USBNET=y CONFIG_USB_NET_SMSC75XX=y -CONFIG_ATH10K=m -CONFIG_ATH10K_PCI=m -CONFIG_ATH10K_DEBUG=y -CONFIG_ATH10K_DEBUGFS=y +CONFIG_USB_NET_SMSC95XX=y CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_CLD_LL_CORE=y +CONFIG_CNSS2=y +CONFIG_CNSS2_QMI=y +CONFIG_CNSS_QCA6390=y +CONFIG_CNSS_UTILS=y CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_EVBUG=m -CONFIG_INPUT_KEYRESET=y -CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_JOYSTICK=y -CONFIG_JOYSTICK_XPAD=y -CONFIG_INPUT_TABLET=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ATMEL_MXT=y CONFIG_INPUT_MISC=y -CONFIG_INPUT_HBTP_INPUT=y CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_UINPUT=y -CONFIG_INPUT_GPIO=y +CONFIG_INPUT_GPIO=m +CONFIG_SERIO_LIBPS2=y # CONFIG_LEGACY_PTYS is not set -# CONFIG_DEVMEM is not set +CONFIG_SERIAL_MSM=y CONFIG_SERIAL_MSM_HS=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_MSM_LEGACY=y CONFIG_DIAG_CHAR=y -CONFIG_MSM_ADSPRPC=y +CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MSM_V2=y CONFIG_SPI=y CONFIG_SPI_QUP=y -CONFIG_SPI_SPIDEV=y +CONFIG_SPI_SPIDEV=m CONFIG_SPMI=y -CONFIG_SLIMBUS_MSM_NGD=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PINCTRL_QCS405=y -CONFIG_FRAGMENTED_GPIO_ADDRESS_SPACE=y +CONFIG_SLIMBUS=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_PINCTRL_SDXPRAIRIE=y +CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y +CONFIG_POWER_RESET=y CONFIG_POWER_RESET_QCOM=y CONFIG_QCOM_DLOAD_MODE=y -CONFIG_SMB1351_USB_CHARGER=y +CONFIG_POWER_SUPPLY=y +CONFIG_QPNP_FG_GEN4=y +CONFIG_QPNP_SMB5=y CONFIG_THERMAL=y CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THERMAL_GOV_USER_SPACE=y CONFIG_THERMAL_GOV_LOW_LIMITS=y CONFIG_CPU_THERMAL=y -CONFIG_DEVFREQ_THERMAL=y CONFIG_QCOM_SPMI_TEMP_ALARM=y CONFIG_THERMAL_TSENS=y -CONFIG_QTI_VIRTUAL_SENSOR=y +CONFIG_QTI_AOP_REG_COOLING_DEVICE=y CONFIG_QTI_QMI_COOLING_DEVICE=y +CONFIG_QTI_QMI_SENSOR=y CONFIG_REGULATOR_COOLING_DEVICE=y +CONFIG_QTI_BCL_PMIC5=y CONFIG_QTI_ADC_TM=y -CONFIG_QTI_RPM_SMD_COOLING_DEVICE=y CONFIG_MFD_SPMI_PMIC=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_FAN53555=y -CONFIG_REGULATOR_CPR=y -CONFIG_REGULATOR_MEM_ACC=y -CONFIG_REGULATOR_RPM_SMD=y -CONFIG_REGULATOR_SPM=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_RPMH=y CONFIG_REGULATOR_STUB=y -CONFIG_RC_DEVICES=y -CONFIG_IR_MSM_GENI=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_RADIO_SUPPORT=y -CONFIG_MEDIA_CONTROLLER=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_SOC_CAMERA=y -CONFIG_SOC_CAMERA_PLATFORM=y -CONFIG_FB=y -CONFIG_FB_MSM=y -CONFIG_FB_MSM_MDSS=y -CONFIG_FB_MSM_MDSS_WRITEBACK=y -CONFIG_FB_MSM_MDSS_HDMI_PANEL=y -CONFIG_FB_MSM_MDSS_SPI_PANEL=y -CONFIG_FB_MSM_MDSS_RGB_PANEL=y -CONFIG_FB_MSM_MDSS_DSI_CTRL_STATUS=y -CONFIG_FB_MSM_MDSS_XLOG_DEBUG=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_DYNAMIC_MINORS=y -CONFIG_SND_USB_AUDIO=y CONFIG_SND_SOC=y -CONFIG_HIDRAW=y CONFIG_UHID=y CONFIG_HID_APPLE=y CONFIG_HID_ELECOM=y CONFIG_HID_MAGICMOUSE=y CONFIG_HID_MICROSOFT=y CONFIG_HID_MULTITOUCH=y -CONFIG_USB_HIDDEV=y +CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_MON=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MSM=y CONFIG_USB_ACM=y CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DEBUG=y CONFIG_USB_STORAGE_DATAFAB=y CONFIG_USB_STORAGE_FREECOM=y CONFIG_USB_STORAGE_ISD200=y @@ -379,26 +300,31 @@ CONFIG_USB_STORAGE_SDDR09=y CONFIG_USB_STORAGE_SDDR55=y CONFIG_USB_STORAGE_JUMPSHOT=y CONFIG_USB_STORAGE_ALAUDA=y +CONFIG_USB_STORAGE_ONETOUCH=y CONFIG_USB_STORAGE_KARMA=y CONFIG_USB_STORAGE_CYPRESS_ATACB=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_MSM=y -CONFIG_USB_SERIAL=y -CONFIG_USB_EHSET_TEST_FIXTURE=y -CONFIG_USB_LINK_LAYER_TEST=y -CONFIG_USB_TYPEC_MUX_NXP5150A=y -CONFIG_USB_QCOM_DIAG_BRIDGE=y CONFIG_NOP_USB_XCEIV=y -CONFIG_MSM_SNPS_FEMTO_PHY=y -CONFIG_USB_MSM_SSPHY=y CONFIG_USB_QCOM_EMU_PHY=y +CONFIG_USB_MSM_SSPHY_QMP=y +CONFIG_MSM_HSUSB_PHY=y CONFIG_DUAL_ROLE_USB_INTF=y CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DEBUG_FILES=y CONFIG_USB_GADGET_VBUS_DRAW=900 CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y CONFIG_USB_CONFIGFS_F_FS=y CONFIG_USB_CONFIGFS_UEVENT=y +CONFIG_USB_CONFIGFS_F_UAC1=y CONFIG_USB_CONFIGFS_F_DIAG=y +CONFIG_USB_CONFIGFS_F_CDEV=y +CONFIG_USB_CONFIGFS_F_GSI=y +CONFIG_USB_CONFIGFS_F_QDSS=y +CONFIG_USB_PD_POLICY=y +CONFIG_QPNP_USB_PDPHY=y CONFIG_MMC=y CONFIG_MMC_PERF_PROFILING=y CONFIG_MMC_BLOCK_MINORS=32 @@ -409,52 +335,56 @@ CONFIG_MMC_CLKGATE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_MSM=y -CONFIG_MMC_SDHCI_MSM_ICE=y -CONFIG_MMC_CQ_HCI=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_PCA9956B=y -CONFIG_LEDS_TRIGGERS=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_QPNP=y CONFIG_DMADEVICES=y CONFIG_QCOM_SPS_DMA=y CONFIG_UIO=y CONFIG_STAGING=y -CONFIG_ASHMEM=y CONFIG_ION=y CONFIG_QPNP_REVID=y CONFIG_SPS=y CONFIG_SPS_SUPPORT_NDP_BAM=y -CONFIG_QCOM_MDSS_PLL=y -CONFIG_QCOM_CLK_SMD_RPM=y +CONFIG_EP_PCIE=y +CONFIG_EP_PCIE_HW=y +CONFIG_USB_BAM=y +CONFIG_GSI_REGISTER_VERSION_2=y +CONFIG_MSM_MHI_DEV=y +CONFIG_IPA3=y +CONFIG_IPA_WDI_UNIFIED_API=y +CONFIG_IPA_ETH=y +CONFIG_AQC_IPA=y +CONFIG_AQC_IPA_PROXY_UC=y +CONFIG_RMNET_IPA3=y +CONFIG_ECM_IPA=y +CONFIG_RNDIS_IPA=y +CONFIG_IPA_UT=y CONFIG_SPMI_PMIC_CLKDIV=y -CONFIG_MDM_DEBUGCC_QCS405=y -CONFIG_CLOCK_CPU_QCS405=y -CONFIG_QCS_CMN_BLK_PLL=y +CONFIG_MSM_CLK_AOP_QMP=y +CONFIG_MSM_CLK_RPMH=y +CONFIG_GCC_SDXPRAIRIE=y +CONFIG_DEBUGCC_SDXPRAIRIE=y +CONFIG_CLOCK_CPU_SDXPRAIRIE=y CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y -CONFIG_ARM_ARCH_TIMER_VCT_ACCESS=y -CONFIG_MAILBOX=y CONFIG_QCOM_APCS_IPC=y +CONFIG_MSM_QMP=y +CONFIG_IOMMU_IO_PGTABLE_FAST=y CONFIG_ARM_SMMU=y CONFIG_QCOM_LAZY_MAPPING=y CONFIG_IOMMU_DEBUG=y CONFIG_IOMMU_DEBUG_TRACKING=y +CONFIG_IOMMU_TESTS=y CONFIG_RPMSG_CHAR=y -CONFIG_RPMSG_QCOM_GLINK_RPM=y CONFIG_RPMSG_QCOM_GLINK_SMEM=y -CONFIG_MSM_RPM_SMD=y +CONFIG_QCOM_LLCC=y +CONFIG_QCOM_SDXPRAIRIE_LLCC=y CONFIG_QCOM_QMI_HELPERS=y CONFIG_QCOM_SMEM=y -CONFIG_QCOM_SMD_RPM=y -CONFIG_MSM_SPM=y -CONFIG_MSM_L2_SPM=y CONFIG_QCOM_SCM=y CONFIG_QCOM_MEMORY_DUMP_V2=y CONFIG_QCOM_WATCHDOG_V2=y CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y -CONFIG_QCOM_WDOG_IPI_ENABLE=y CONFIG_QCOM_SMP2P=y CONFIG_MSM_SERVICE_LOCATOR=y CONFIG_MSM_SERVICE_NOTIFIER=y @@ -462,70 +392,54 @@ CONFIG_MSM_SUBSYSTEM_RESTART=y CONFIG_MSM_PIL=y CONFIG_MSM_SYSMON_QMI_COMM=y CONFIG_MSM_PIL_SSR_GENERIC=y +CONFIG_SETUP_SSR_NOTIF_TIMEOUTS=y +CONFIG_SSR_SYSMON_NOTIF_TIMEOUT=20000 +CONFIG_SSR_SUBSYS_NOTIF_TIMEOUT=20000 +CONFIG_PANIC_ON_SSR_NOTIF_TIMEOUT=y CONFIG_MSM_BOOT_STATS=y CONFIG_QCOM_DCC_V2=y -CONFIG_ICNSS=y -CONFIG_ICNSS_QMI=y +CONFIG_QCOM_SECURE_BUFFER=y +CONFIG_QCOM_EUD=y CONFIG_QCOM_BUS_SCALING=y -CONFIG_MSM_TZ_SMMU=y +CONFIG_QCOM_BUS_CONFIG_RPMH=y +CONFIG_QCOM_COMMAND_DB=y +CONFIG_QTI_RPMH_API=y CONFIG_QCOM_GLINK=y CONFIG_QCOM_GLINK_PKT=y -CONFIG_MSM_JTAGV8=y CONFIG_QTI_RPM_STATS_LOG=y -CONFIG_MSM_CDSP_LOADER=y CONFIG_QCOM_SMCINVOKE=y CONFIG_MSM_PM=y -CONFIG_QCOM_SMP2P_SLEEPSTATE=y -CONFIG_QCOM_BIMC_BWMON=y +CONFIG_QMP_DEBUGFS_CLIENT=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y CONFIG_ARM_MEMLAT_MON=y -CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y CONFIG_DEVFREQ_GOV_MEMLAT=y CONFIG_QCOM_DEVFREQ_DEVBW=y -CONFIG_EXTCON_USB_GPIO=y +CONFIG_EXTCON_QCOM_SPMI_MISC=y CONFIG_IIO=y CONFIG_QCOM_SPMI_ADC5=y CONFIG_PWM=y -CONFIG_PWM_QTI_LPG=y -CONFIG_QCOM_KGSL=y -CONFIG_QTI_MPM=y +CONFIG_QCOM_SHOW_RESUME_IRQ=y CONFIG_ANDROID=y -CONFIG_ANDROID_BINDER_IPC=y CONFIG_MSM_TZ_LOG=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y CONFIG_EXT3_FS=y CONFIG_EXT4_FS_SECURITY=y -CONFIG_QUOTA=y -CONFIG_QUOTA_NETLINK_INTERFACE=y -# CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_QFMT_V2=y -CONFIG_FUSE_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y CONFIG_UBIFS_FS=y CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_SQUASHFS=y -CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y -CONFIG_SQUASHFS_XATTR=y -# CONFIG_SQUASHFS_ZLIB is not set -CONFIG_SQUASHFS_XZ=y -CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_PRINTK_TIME=y CONFIG_DEBUG_INFO=y -CONFIG_PAGE_OWNER=y CONFIG_MAGIC_SYSRQ=y -CONFIG_PAGE_POISONING=y -CONFIG_PAGE_POISONING_ENABLE_DEFAULT=y CONFIG_PANIC_ON_RECURSIVE_FAULT=y -CONFIG_PANIC_ON_OOPS=y CONFIG_PANIC_TIMEOUT=5 +# CONFIG_SCHED_DEBUG is not set CONFIG_SCHEDSTATS=y +# CONFIG_DEBUG_PREEMPT is not set CONFIG_IPC_LOGGING=y -CONFIG_BUG_ON_DATA_CORRUPTION=y +# CONFIG_FTRACE is not set CONFIG_CORESIGHT=y CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y @@ -535,20 +449,17 @@ CONFIG_CORESIGHT_TPDA=y CONFIG_CORESIGHT_TPDM=y CONFIG_CORESIGHT_HWEVENT=y CONFIG_CORESIGHT_DUMMY=y +CONFIG_CORESIGHT_REMOTE_ETM=y +CONFIG_CORESIGHT_REMOTE_ETM_DEFAULT_ENABLE=0 +CONFIG_CORESIGHT_TGU=y CONFIG_CORESIGHT_EVENT=y CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y CONFIG_SECURITY=y CONFIG_SECURITY_NETWORK=y -CONFIG_LSM_MMAP_MIN_ADDR=4096 +CONFIG_SECURITY_NETWORK_XFRM=y CONFIG_HARDENED_USERCOPY=y -CONFIG_HARDENED_USERCOPY_PAGESPAN=y CONFIG_SECURITY_SELINUX=y -CONFIG_CRYPTO_CTR=y -CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_TWOFISH=y +# CONFIG_SECURITY_SELINUX_AVC_STATS is not set CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y CONFIG_CRYPTO_DEV_QCRYPTO=y CONFIG_CRYPTO_DEV_QCEDEV=y -CONFIG_CRYPTO_DEV_QCOM_ICE=y -CONFIG_STACK_HASH_ORDER_SHIFT=12 diff --git a/arch/arm/configs/vendor/qcs403_defconfig b/arch/arm/configs/vendor/sdxprairie-auto_defconfig similarity index 58% rename from arch/arm/configs/vendor/qcs403_defconfig rename to arch/arm/configs/vendor/sdxprairie-auto_defconfig index ac217a92deb3..5e5f5756b227 100644 --- a/arch/arm/configs/vendor/qcs403_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-auto_defconfig @@ -1,20 +1,12 @@ -CONFIG_POSIX_MQUEUE=y CONFIG_AUDIT=y +# CONFIG_AUDITSYSCALL is not set CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_SCHED_WALT=y -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_RCU_EXPERT=y -CONFIG_RCU_FAST_NO_HZ=y -CONFIG_RCU_NOCB_CPU=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_CGROUPS=y CONFIG_CGROUP_SCHED=y +# CONFIG_FAIR_GROUP_SCHED is not set CONFIG_RT_GROUP_SCHED=y CONFIG_CGROUP_FREEZER=y CONFIG_CGROUP_CPUACCT=y @@ -22,137 +14,115 @@ CONFIG_CGROUP_DEBUG=y CONFIG_NAMESPACES=y # CONFIG_UTS_NS is not set # CONFIG_PID_NS is not set -CONFIG_DEFAULT_USE_ENERGY_AWARE=y +CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZ4 is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_KALLSYMS_ALL=y CONFIG_EMBEDDED=y +CONFIG_SLAB_FREELIST_RANDOM=y +CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_PROFILING=y CONFIG_CC_STACKPROTECTOR_STRONG=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SIG=y -CONFIG_MODULE_SIG_FORCE=y -CONFIG_MODULE_SIG_SHA512=y CONFIG_PARTITION_ADVANCED=y CONFIG_ARCH_QCOM=y -CONFIG_ARCH_QCS403=y +CONFIG_ARCH_SDXPRAIRIE=y # CONFIG_VDSO is not set -CONFIG_SMP=y -CONFIG_ARM_PSCI=y +CONFIG_PCI_MSM=y +CONFIG_PCI_MSM_MSI=y CONFIG_PREEMPT=y -CONFIG_HIGHMEM=y -CONFIG_CLEANCACHE=y CONFIG_CMA=y -CONFIG_CMA_DEBUGFS=y -CONFIG_ZSMALLOC=y CONFIG_SECCOMP=y CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=y +CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_MSM=y CONFIG_CPU_IDLE=y CONFIG_VFP=y CONFIG_NEON=y -CONFIG_KERNEL_MODE_NEON=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_PM_AUTOSLEEP=y CONFIG_PM_WAKELOCKS=y CONFIG_PM_WAKELOCKS_LIMIT=0 # CONFIG_PM_WAKELOCKS_GC is not set -CONFIG_PM_DEBUG=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y -CONFIG_XFRM_USER=y -CONFIG_XFRM_STATISTICS=y -CONFIG_NET_KEY=y CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_INET_AH=y -CONFIG_INET_ESP=y -CONFIG_INET_IPCOMP=y -# CONFIG_INET_XFRM_MODE_BEET is not set -CONFIG_INET_DIAG_DESTROY=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -CONFIG_IPV6_OPTIMISTIC_DAD=y -CONFIG_INET6_AH=y -CONFIG_INET6_ESP=y -CONFIG_INET6_IPCOMP=y -CONFIG_IPV6_MIP6=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V2=y CONFIG_IPV6_MULTIPLE_TABLES=y CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y CONFIG_NETFILTER=y CONFIG_NF_CONNTRACK=y CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y CONFIG_NF_CONNTRACK_AMANDA=y CONFIG_NF_CONNTRACK_FTP=y CONFIG_NF_CONNTRACK_H323=y CONFIG_NF_CONNTRACK_IRC=y CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_SNMP=y CONFIG_NF_CONNTRACK_PPTP=y -CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_SIP=y CONFIG_NF_CONNTRACK_TFTP=y CONFIG_NF_CT_NETLINK=y -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y -CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NF_CT_NETLINK_TIMEOUT=y +CONFIG_NF_CT_NETLINK_HELPER=y +CONFIG_NETFILTER_NETLINK_GLUE_CT=y CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y -CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y CONFIG_NETFILTER_XT_TARGET_LOG=y CONFIG_NETFILTER_XT_TARGET_MARK=y CONFIG_NETFILTER_XT_TARGET_NFLOG=y CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y CONFIG_NETFILTER_XT_TARGET_NOTRACK=y -CONFIG_NETFILTER_XT_TARGET_TEE=y CONFIG_NETFILTER_XT_TARGET_TPROXY=y CONFIG_NETFILTER_XT_TARGET_TRACE=y CONFIG_NETFILTER_XT_TARGET_SECMARK=y CONFIG_NETFILTER_XT_TARGET_TCPMSS=y -CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=y CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y CONFIG_NETFILTER_XT_MATCH_CONNMARK=y CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y CONFIG_NETFILTER_XT_MATCH_DSCP=y CONFIG_NETFILTER_XT_MATCH_ESP=y -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y -CONFIG_NETFILTER_XT_MATCH_HELPER=y CONFIG_NETFILTER_XT_MATCH_IPRANGE=y -CONFIG_NETFILTER_XT_MATCH_LENGTH=y CONFIG_NETFILTER_XT_MATCH_LIMIT=y -CONFIG_NETFILTER_XT_MATCH_MAC=y -CONFIG_NETFILTER_XT_MATCH_MARK=y CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y -CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y -CONFIG_NETFILTER_XT_MATCH_QUOTA=y -CONFIG_NETFILTER_XT_MATCH_QUOTA2=y CONFIG_NETFILTER_XT_MATCH_STATE=y -CONFIG_NETFILTER_XT_MATCH_STATISTIC=y -CONFIG_NETFILTER_XT_MATCH_STRING=y -CONFIG_NETFILTER_XT_MATCH_TIME=y -CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_IP_SET=y CONFIG_NF_CONNTRACK_IPV4=y CONFIG_IP_NF_IPTABLES=y CONFIG_IP_NF_MATCH_AH=y CONFIG_IP_NF_MATCH_ECN=y -CONFIG_IP_NF_MATCH_RPFILTER=y CONFIG_IP_NF_MATCH_TTL=y CONFIG_IP_NF_FILTER=y CONFIG_IP_NF_TARGET_REJECT=y CONFIG_IP_NF_NAT=y CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NATTYPE_MODULE=y CONFIG_IP_NF_TARGET_NETMAP=y CONFIG_IP_NF_TARGET_REDIRECT=y CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_TARGET_ECN=y +CONFIG_IP_NF_TARGET_TTL=y CONFIG_IP_NF_RAW=y CONFIG_IP_NF_SECURITY=y CONFIG_IP_NF_ARPTABLES=y @@ -160,7 +130,13 @@ CONFIG_IP_NF_ARPFILTER=y CONFIG_IP_NF_ARP_MANGLE=y CONFIG_NF_CONNTRACK_IPV6=y CONFIG_IP6_NF_IPTABLES=y -CONFIG_IP6_NF_MATCH_RPFILTER=y +CONFIG_IP6_NF_MATCH_AH=y +CONFIG_IP6_NF_MATCH_FRAG=y +CONFIG_IP6_NF_MATCH_OPTS=y +CONFIG_IP6_NF_MATCH_HL=y +CONFIG_IP6_NF_MATCH_IPV6HEADER=y +CONFIG_IP6_NF_MATCH_MH=y +CONFIG_IP6_NF_MATCH_RT=y CONFIG_IP6_NF_FILTER=y CONFIG_IP6_NF_TARGET_REJECT=y CONFIG_IP6_NF_MANGLE=y @@ -175,55 +151,41 @@ CONFIG_BRIDGE_EBT_IP6=y CONFIG_BRIDGE_EBT_ARPREPLY=y CONFIG_BRIDGE_EBT_DNAT=y CONFIG_BRIDGE_EBT_SNAT=y -CONFIG_L2TP=y -CONFIG_L2TP_DEBUGFS=y -CONFIG_L2TP_V3=y -CONFIG_L2TP_IP=y -CONFIG_L2TP_ETH=y CONFIG_BRIDGE=y +CONFIG_VLAN_8021Q=y CONFIG_NET_SCHED=y -CONFIG_NET_SCH_HTB=y CONFIG_NET_SCH_PRIO=y -CONFIG_NET_CLS_FW=y -CONFIG_NET_CLS_U32=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_FLOW=y -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=y -CONFIG_NET_EMATCH_NBYTE=y -CONFIG_NET_EMATCH_U32=y -CONFIG_NET_EMATCH_META=y -CONFIG_NET_EMATCH_TEXT=y -CONFIG_NET_CLS_ACT=y CONFIG_QRTR=y CONFIG_QRTR_SMD=y +CONFIG_QRTR_MHI=y +CONFIG_CAN=y +CONFIG_QTI_CAN=y CONFIG_BT=y # CONFIG_BT_BREDR is not set # CONFIG_BT_LE is not set # CONFIG_BT_DEBUGFS is not set CONFIG_MSM_BT_POWER=y +# CONFIG_BTFM_SLIM is not set CONFIG_CFG80211=y -CONFIG_CFG80211_INTERNAL_REGDB=y CONFIG_RFKILL=y -CONFIG_NTAG_NQ=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y -CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=12 +CONFIG_MHI_BUS=y +CONFIG_MHI_DEBUG=y +CONFIG_MHI_UCI=y CONFIG_MTD=y +CONFIG_MTD_TESTS=m CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y CONFIG_MTD_MSM_QPIC_NAND=y CONFIG_MTD_NAND=y CONFIG_MTD_UBI=y -CONFIG_ZRAM=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_QSEECOM=y -CONFIG_UID_SYS_STATS=y -CONFIG_QPNP_MISC=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_CHR_DEV_SG=y @@ -231,133 +193,105 @@ CONFIG_CHR_DEV_SCH=y CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_SCSI_UFSHCD=y -CONFIG_SCSI_UFSHCD_PLATFORM=y -CONFIG_SCSI_UFS_QCOM=y -CONFIG_MD=y -CONFIG_BLK_DEV_DM=y -CONFIG_DM_CRYPT=y -CONFIG_DM_VERITY=y -CONFIG_DM_VERITY_FEC=y CONFIG_NETDEVICES=y -CONFIG_DUMMY=y CONFIG_TUN=y +CONFIG_AQFWD=y +CONFIG_AQFWD_QCOM_IPA=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +CONFIG_KS8851=y +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_RMNET=y +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set CONFIG_AT803X_PHY=y +CONFIG_MICREL_PHY=y CONFIG_PPP=y -CONFIG_PPP_BSDCOMP=y -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=y -CONFIG_PPP_MULTILINK=y -CONFIG_PPPOE=y -CONFIG_PPPOL2TP=y -CONFIG_PPPOLAC=y -CONFIG_PPPOPNS=y CONFIG_PPP_ASYNC=y -CONFIG_PPP_SYNC_TTY=y CONFIG_USB_USBNET=y CONFIG_USB_NET_SMSC75XX=y +CONFIG_USB_NET_SMSC95XX=y CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_CLD_LL_CORE=y +CONFIG_CNSS2=y +CONFIG_CNSS2_DEBUG=y +CONFIG_CNSS2_QMI=y +CONFIG_CNSS_QCA6390=y +CONFIG_CNSS_UTILS=y CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_EVBUG=m -CONFIG_INPUT_KEYRESET=y -CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_JOYSTICK=y -CONFIG_JOYSTICK_XPAD=y -CONFIG_INPUT_TABLET=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ATMEL_MXT=y CONFIG_INPUT_MISC=y -CONFIG_INPUT_HBTP_INPUT=y CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_UINPUT=y -CONFIG_INPUT_GPIO=y +CONFIG_INPUT_GPIO=m +CONFIG_SERIO_LIBPS2=y # CONFIG_LEGACY_PTYS is not set -# CONFIG_DEVMEM is not set CONFIG_SERIAL_MSM=y CONFIG_SERIAL_MSM_CONSOLE=y CONFIG_SERIAL_MSM_HS=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_MSM_LEGACY=y CONFIG_DIAG_CHAR=y -CONFIG_MSM_ADSPRPC=y +CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MSM_V2=y CONFIG_SPI=y -CONFIG_SPI_DEBUG=y CONFIG_SPI_QUP=y -CONFIG_SPI_SPIDEV=y +CONFIG_SPI_SPIDEV=m CONFIG_SPMI=y -CONFIG_SPMI_MSM_PMIC_ARB_DEBUG=y -CONFIG_SLIMBUS_MSM_NGD=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PINCTRL_QCS405=y -CONFIG_FRAGMENTED_GPIO_ADDRESS_SPACE=y +CONFIG_SLIMBUS=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_PINCTRL_SDXPRAIRIE=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_QCOM=y CONFIG_QCOM_DLOAD_MODE=y CONFIG_POWER_SUPPLY=y -CONFIG_SMB1351_USB_CHARGER=y +CONFIG_QPNP_FG_GEN4=y +CONFIG_QPNP_SMB5=y CONFIG_THERMAL=y +CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THERMAL_GOV_USER_SPACE=y CONFIG_THERMAL_GOV_LOW_LIMITS=y CONFIG_CPU_THERMAL=y -CONFIG_DEVFREQ_THERMAL=y CONFIG_QCOM_SPMI_TEMP_ALARM=y CONFIG_THERMAL_TSENS=y -CONFIG_QTI_VIRTUAL_SENSOR=y +CONFIG_QTI_AOP_REG_COOLING_DEVICE=y CONFIG_QTI_QMI_COOLING_DEVICE=y +CONFIG_QTI_QMI_SENSOR=y CONFIG_REGULATOR_COOLING_DEVICE=y +CONFIG_QTI_BCL_PMIC5=y CONFIG_QTI_ADC_TM=y -CONFIG_QTI_RPM_SMD_COOLING_DEVICE=y CONFIG_MFD_SPMI_PMIC=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_FAN53555=y -CONFIG_REGULATOR_CPR=y -CONFIG_REGULATOR_MEM_ACC=y -CONFIG_REGULATOR_RPM_SMD=y -CONFIG_REGULATOR_SPM=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_RPMH=y CONFIG_REGULATOR_STUB=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_RADIO_SUPPORT=y -CONFIG_MEDIA_CONTROLLER=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_SOC_CAMERA=y -CONFIG_SOC_CAMERA_PLATFORM=y CONFIG_FB=y -CONFIG_FB_MSM=y -CONFIG_FB_MSM_MDSS=y -CONFIG_FB_MSM_MDSS_WRITEBACK=y -CONFIG_FB_MSM_MDSS_DSI_CTRL_STATUS=y -CONFIG_FB_MSM_MDSS_XLOG_DEBUG=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_DYNAMIC_MINORS=y -CONFIG_SND_USB_AUDIO=y CONFIG_SND_SOC=y -CONFIG_HIDRAW=y CONFIG_UHID=y CONFIG_HID_APPLE=y CONFIG_HID_ELECOM=y CONFIG_HID_MAGICMOUSE=y CONFIG_HID_MICROSOFT=y CONFIG_HID_MULTITOUCH=y -CONFIG_USB_HIDDEV=y +CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_MON=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_ACM=y CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_DEBUG=y CONFIG_USB_STORAGE_DATAFAB=y CONFIG_USB_STORAGE_FREECOM=y CONFIG_USB_STORAGE_ISD200=y @@ -366,26 +300,32 @@ CONFIG_USB_STORAGE_SDDR09=y CONFIG_USB_STORAGE_SDDR55=y CONFIG_USB_STORAGE_JUMPSHOT=y CONFIG_USB_STORAGE_ALAUDA=y +CONFIG_USB_STORAGE_ONETOUCH=y CONFIG_USB_STORAGE_KARMA=y CONFIG_USB_STORAGE_CYPRESS_ATACB=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_MSM=y -CONFIG_USB_SERIAL=y -CONFIG_USB_EHSET_TEST_FIXTURE=y -CONFIG_USB_LINK_LAYER_TEST=y CONFIG_NOP_USB_XCEIV=y -CONFIG_MSM_SNPS_FEMTO_PHY=y -CONFIG_USB_MSM_SSPHY=y CONFIG_USB_QCOM_EMU_PHY=y +CONFIG_USB_MSM_SSPHY_QMP=y +CONFIG_MSM_HSUSB_PHY=y CONFIG_DUAL_ROLE_USB_INTF=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DEBUG_FILES=y CONFIG_USB_GADGET_DEBUG_FS=y CONFIG_USB_GADGET_VBUS_DRAW=900 CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y CONFIG_USB_CONFIGFS_F_FS=y CONFIG_USB_CONFIGFS_UEVENT=y +CONFIG_USB_CONFIGFS_F_UAC1=y CONFIG_USB_CONFIGFS_F_DIAG=y +CONFIG_USB_CONFIGFS_F_CDEV=y +CONFIG_USB_CONFIGFS_F_GSI=y +CONFIG_USB_CONFIGFS_F_QDSS=y +CONFIG_USB_PD_POLICY=y +CONFIG_QPNP_USB_PDPHY=y CONFIG_MMC=y CONFIG_MMC_PERF_PROFILING=y CONFIG_MMC_BLOCK_MINORS=32 @@ -397,54 +337,59 @@ CONFIG_MMC_CLKGATE=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_MSM=y -CONFIG_MMC_CQ_HCI=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_PCA9956B=y -CONFIG_LEDS_TRIGGERS=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_QPNP=y CONFIG_DMADEVICES=y CONFIG_QCOM_SPS_DMA=y CONFIG_UIO=y CONFIG_STAGING=y -CONFIG_ASHMEM=y CONFIG_ION=y CONFIG_QPNP_REVID=y CONFIG_SPS=y CONFIG_SPS_SUPPORT_NDP_BAM=y -CONFIG_QCOM_MDSS_PLL=y -CONFIG_COMMON_CLK_QCOM=y -CONFIG_QCOM_CLK_SMD_RPM=y +CONFIG_EP_PCIE=y +CONFIG_EP_PCIE_HW=y +CONFIG_USB_BAM=y +CONFIG_GSI_REGISTER_VERSION_2=y +CONFIG_MSM_MHI_DEV=y +CONFIG_IPA3=y +CONFIG_IPA_DEBUG=y +CONFIG_IPA_WDI_UNIFIED_API=y +CONFIG_IPA_ETH=y +CONFIG_IPA_ETH_DEBUG=y +CONFIG_AQC_IPA=y +CONFIG_AQC_IPA_PROXY_UC=y +CONFIG_AQC_IPA_DEBUG=y +CONFIG_RMNET_IPA3=y +CONFIG_ECM_IPA=y +CONFIG_RNDIS_IPA=y +CONFIG_IPA_UT=y CONFIG_SPMI_PMIC_CLKDIV=y -CONFIG_MDM_DEBUGCC_QCS405=y -CONFIG_CLOCK_CPU_QCS405=y -CONFIG_QCS_CMN_BLK_PLL=y +CONFIG_MSM_CLK_AOP_QMP=y +CONFIG_MSM_CLK_RPMH=y +CONFIG_GCC_SDXPRAIRIE=y +CONFIG_DEBUGCC_SDXPRAIRIE=y +CONFIG_CLOCK_CPU_SDXPRAIRIE=y CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y -CONFIG_MAILBOX=y CONFIG_QCOM_APCS_IPC=y +CONFIG_MSM_QMP=y +CONFIG_IOMMU_IO_PGTABLE_FAST=y CONFIG_ARM_SMMU=y CONFIG_QCOM_LAZY_MAPPING=y CONFIG_IOMMU_DEBUG=y CONFIG_IOMMU_DEBUG_TRACKING=y CONFIG_IOMMU_TESTS=y -CONFIG_QCOM_IOMMU=y CONFIG_RPMSG_CHAR=y -CONFIG_RPMSG_QCOM_GLINK_RPM=y CONFIG_RPMSG_QCOM_GLINK_SMEM=y -CONFIG_RPMSG_QCOM_SMD=y -CONFIG_QCOM_CPUSS_DUMP=y +CONFIG_QCOM_LLCC=y +CONFIG_QCOM_SDXPRAIRIE_LLCC=y CONFIG_QCOM_QMI_HELPERS=y CONFIG_QCOM_SMEM=y -CONFIG_QCOM_SMD_RPM=y -CONFIG_MSM_SPM=y -CONFIG_MSM_L2_SPM=y CONFIG_QCOM_SCM=y CONFIG_QCOM_MEMORY_DUMP_V2=y CONFIG_QCOM_WATCHDOG_V2=y CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y -CONFIG_QCOM_WDOG_IPI_ENABLE=y CONFIG_QCOM_SMP2P=y CONFIG_MSM_SERVICE_LOCATOR=y CONFIG_MSM_SERVICE_NOTIFIER=y @@ -452,103 +397,78 @@ CONFIG_MSM_SUBSYSTEM_RESTART=y CONFIG_MSM_PIL=y CONFIG_MSM_SYSMON_QMI_COMM=y CONFIG_MSM_PIL_SSR_GENERIC=y +CONFIG_SETUP_SSR_NOTIF_TIMEOUTS=y +CONFIG_SSR_SYSMON_NOTIF_TIMEOUT=20000 +CONFIG_SSR_SUBSYS_NOTIF_TIMEOUT=20000 +CONFIG_PANIC_ON_SSR_NOTIF_TIMEOUT=y CONFIG_MSM_BOOT_STATS=y -CONFIG_MSM_CORE_HANG_DETECT=y CONFIG_QCOM_DCC_V2=y -CONFIG_ICNSS=y -CONFIG_ICNSS_DEBUG=y -CONFIG_ICNSS_QMI=y +CONFIG_QCOM_SECURE_BUFFER=y +CONFIG_QCOM_EUD=y CONFIG_QCOM_BUS_SCALING=y -CONFIG_QCOM_EARLY_RANDOM=y -CONFIG_MSM_TZ_SMMU=y +CONFIG_QCOM_BUS_CONFIG_RPMH=y +CONFIG_QCOM_COMMAND_DB=y +CONFIG_QTI_RPMH_API=y CONFIG_QCOM_GLINK=y CONFIG_QCOM_GLINK_PKT=y -# CONFIG_MSM_JTAGV8 is not set CONFIG_QTI_RPM_STATS_LOG=y -CONFIG_MSM_CDSP_LOADER=y CONFIG_QCOM_SMCINVOKE=y -CONFIG_QCOM_SMP2P_SLEEPSTATE=y -CONFIG_QCOM_BIMC_BWMON=y +CONFIG_MSM_PM=y +CONFIG_QMP_DEBUGFS_CLIENT=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y CONFIG_ARM_MEMLAT_MON=y -CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y CONFIG_DEVFREQ_GOV_MEMLAT=y CONFIG_QCOM_DEVFREQ_DEVBW=y -CONFIG_EXTCON_USB_GPIO=y +CONFIG_EXTCON_QCOM_SPMI_MISC=y CONFIG_IIO=y CONFIG_QCOM_SPMI_ADC5=y CONFIG_PWM=y -CONFIG_PWM_QTI_LPG=y -CONFIG_QTI_MPM=y +CONFIG_QCOM_SHOW_RESUME_IRQ=y CONFIG_ANDROID=y -CONFIG_ANDROID_BINDER_IPC=y CONFIG_MSM_TZ_LOG=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y CONFIG_EXT3_FS=y CONFIG_EXT4_FS_SECURITY=y -CONFIG_QUOTA=y -CONFIG_QUOTA_NETLINK_INTERFACE=y -# CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_QFMT_V2=y -CONFIG_FUSE_FS=y -CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y CONFIG_UBIFS_FS=y CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_SQUASHFS=y -CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y -CONFIG_SQUASHFS_XATTR=y -# CONFIG_SQUASHFS_ZLIB is not set -CONFIG_SQUASHFS_XZ=y -CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_PRINTK_TIME=y CONFIG_DYNAMIC_DEBUG=y CONFIG_DEBUG_INFO=y -CONFIG_PAGE_OWNER=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_PAGEALLOC=y -CONFIG_SLUB_DEBUG_PANIC_ON=y -CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y -CONFIG_PAGE_POISONING_ENABLE_DEFAULT=y -CONFIG_DEBUG_OBJECTS=y -CONFIG_DEBUG_OBJECTS_FREE=y -CONFIG_DEBUG_OBJECTS_TIMERS=y -CONFIG_DEBUG_OBJECTS_WORK=y -CONFIG_DEBUG_OBJECTS_RCU_HEAD=y -CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y -CONFIG_SLUB_DEBUG_ON=y CONFIG_DEBUG_KMEMLEAK=y -CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=4000 CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y CONFIG_DEBUG_STACK_USAGE=y CONFIG_DEBUG_MEMORY_INIT=y CONFIG_PANIC_ON_RECURSIVE_FAULT=y -CONFIG_PANIC_ON_OOPS=y CONFIG_PANIC_TIMEOUT=5 CONFIG_SCHEDSTATS=y -CONFIG_SCHED_STACK_END_CHECK=y CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_SPINLOCK_PANIC_ON_BUG=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_ATOMIC_SLEEP=y CONFIG_DEBUG_LIST=y +CONFIG_DEBUG_CREDENTIALS=y CONFIG_FAULT_INJECTION=y CONFIG_FAIL_PAGE_ALLOC=y -CONFIG_UFS_FAULT_INJECTION=y CONFIG_FAULT_INJECTION_DEBUG_FS=y CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y CONFIG_IPC_LOGGING=y CONFIG_QCOM_RTB=y -CONFIG_QCOM_RTB_SEPARATE_CPUS=y -CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_LKDTM=y +CONFIG_FUNCTION_TRACER=y +CONFIG_PREEMPTIRQ_EVENTS=y +CONFIG_IRQSOFF_TRACER=y +CONFIG_PREEMPT_TRACER=y +CONFIG_LKDTM=m +CONFIG_PANIC_ON_DATA_CORRUPTION=y +CONFIG_DEBUG_USER=y CONFIG_CORESIGHT=y CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y -CONFIG_CORESIGHT_SOURCE_ETM4X=y +CONFIG_CORESIGHT_SOURCE_ETM3X=y CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y CONFIG_CORESIGHT_STM=y CONFIG_CORESIGHT_CTI=y @@ -558,14 +478,17 @@ CONFIG_CORESIGHT_HWEVENT=y CONFIG_CORESIGHT_DUMMY=y CONFIG_CORESIGHT_REMOTE_ETM=y CONFIG_CORESIGHT_REMOTE_ETM_DEFAULT_ENABLE=0 +CONFIG_CORESIGHT_TGU=y CONFIG_CORESIGHT_EVENT=y CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y CONFIG_SECURITY=y CONFIG_SECURITY_NETWORK=y -CONFIG_LSM_MMAP_MIN_ADDR=4096 +CONFIG_SECURITY_NETWORK_XFRM=y CONFIG_HARDENED_USERCOPY=y +CONFIG_HARDENED_USERCOPY_PAGESPAN=y CONFIG_SECURITY_SELINUX=y -CONFIG_CRYPTO_CTR=y -CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_TWOFISH=y +# CONFIG_SECURITY_SELINUX_AVC_STATS is not set +CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y +CONFIG_CRYPTO_DEV_QCRYPTO=y +CONFIG_CRYPTO_DEV_QCEDEV=y +CONFIG_XZ_DEC=y diff --git a/arch/arm/configs/vendor/sdxprairie-perf_defconfig b/arch/arm/configs/vendor/sdxprairie-perf_defconfig index ccd851bd5dca..d629857a60fe 100644 --- a/arch/arm/configs/vendor/sdxprairie-perf_defconfig +++ b/arch/arm/configs/vendor/sdxprairie-perf_defconfig @@ -156,10 +156,8 @@ CONFIG_VLAN_8021Q=y CONFIG_NET_SCHED=y CONFIG_NET_SCH_PRIO=y CONFIG_QRTR=y -CONFIG_QRTR_NODE_ID=2 CONFIG_QRTR_SMD=y CONFIG_QRTR_MHI=y -CONFIG_QRTR_MHI_DEV=y CONFIG_BT=y # CONFIG_BT_BREDR is not set # CONFIG_BT_LE is not set @@ -381,9 +379,6 @@ CONFIG_RPMSG_QCOM_GLINK_SMEM=y CONFIG_QCOM_LLCC=y CONFIG_QCOM_SDXPRAIRIE_LLCC=y CONFIG_QCOM_QMI_HELPERS=y -CONFIG_QCOM_QMI_RMNET=y -CONFIG_QCOM_QMI_DFC=y -CONFIG_QCOM_QMI_POWER_COLLAPSE=y CONFIG_QCOM_SMEM=y CONFIG_QCOM_SCM=y CONFIG_QCOM_MEMORY_DUMP_V2=y diff --git a/arch/arm/configs/vendor/sdxprairie_defconfig b/arch/arm/configs/vendor/sdxprairie_defconfig index 994ee3ad74b9..04b5b0310ce4 100644 --- a/arch/arm/configs/vendor/sdxprairie_defconfig +++ b/arch/arm/configs/vendor/sdxprairie_defconfig @@ -156,10 +156,8 @@ CONFIG_VLAN_8021Q=y CONFIG_NET_SCHED=y CONFIG_NET_SCH_PRIO=y CONFIG_QRTR=y -CONFIG_QRTR_NODE_ID=2 CONFIG_QRTR_SMD=y CONFIG_QRTR_MHI=y -CONFIG_QRTR_MHI_DEV=y CONFIG_BT=y # CONFIG_BT_BREDR is not set # CONFIG_BT_LE is not set @@ -386,9 +384,6 @@ CONFIG_RPMSG_QCOM_GLINK_SMEM=y CONFIG_QCOM_LLCC=y CONFIG_QCOM_SDXPRAIRIE_LLCC=y CONFIG_QCOM_QMI_HELPERS=y -CONFIG_QCOM_QMI_RMNET=y -CONFIG_QCOM_QMI_DFC=y -CONFIG_QCOM_QMI_POWER_COLLAPSE=y CONFIG_QCOM_SMEM=y CONFIG_QCOM_SCM=y CONFIG_QCOM_MEMORY_DUMP_V2=y diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig index 8b77bab0f179..fc17977d52a2 100644 --- a/arch/arm/mach-qcom/Kconfig +++ b/arch/arm/mach-qcom/Kconfig @@ -2,7 +2,7 @@ if ARCH_QCOM menu "QCOM SoC Type" config ARCH_QCS405 - bool "Enable Support for QCS405" + bool "Enable Support for QCS405" select CLKDEV_LOOKUP select HAVE_CLK select HAVE_CLK_PREPARE @@ -37,42 +37,6 @@ config ARCH_QCS405 This enables support for the QCS405 chipset. If you do not wish to build a kernel that runs on this chipset, say 'N' here. -config ARCH_QCS403 - bool "Enable Support for QCS403" - select CLKDEV_LOOKUP - select HAVE_CLK - select HAVE_CLK_PREPARE - select PM_OPP - select SOC_BUS - select MSM_IRQ - select THERMAL_WRITABLE_TRIPS - select ARM_GIC - select ARM_AMBA - select SPARSE_IRQ - select MULTI_IRQ_HANDLER - select HAVE_ARM_ARCH_TIMER - select MAY_HAVE_SPARSE_IRQ - select COMMON_CLK - select QCOM_GDSC - select PINCTRL_MSM - select USE_PINCTRL_IRQ - select MSM_PM if PM - select QMI_ENCDEC - select CPU_FREQ - select CPU_FREQ_MSM - select PM_DEVFREQ - select MSM_DEVFREQ_DEVBW - select DEVFREQ_SIMPLE_DEV - select DEVFREQ_GOV_MSM_BW_HWMON - select MSM_BIMC_BWMON - select MSM_QDSP6V2_CODECS - select MSM_AUDIO_QDSP6V2 if SND_SOC - select MSM_RPM_SMD - select MSM_JTAGV8 if CORESIGHT_ETMV4 - help - This enables support for the QCS403 chipset. If you do not - wish to build a kernel that runs on this chipset, say 'N' here. - config ARCH_MSM8X60 bool "Enable support for MSM8X60" select ARCH_SUPPORTS_BIG_ENDIAN diff --git a/arch/arm/mach-qcom/Makefile b/arch/arm/mach-qcom/Makefile index 27a323e0bee7..23af561084b8 100644 --- a/arch/arm/mach-qcom/Makefile +++ b/arch/arm/mach-qcom/Makefile @@ -1,5 +1,4 @@ obj-$(CONFIG_USE_OF) += board-dt.o obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_ARCH_QCS405) += board-qcs405.o -obj-$(CONFIG_ARCH_QCS403) += board-qcs403.o obj-$(CONFIG_ARCH_SDXPRAIRIE) += board-sdxprairie.o diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 1a4d48a38416..204a63061aa6 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -2718,13 +2718,10 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, if (dev->dma_ops) return; - if (arm_setup_iommu_dma_ops(dev, dma_base, size, iommu)) { + if (arm_setup_iommu_dma_ops(dev, dma_base, size, iommu)) dma_ops = arm_get_iommu_dma_map_ops(coherent); - dev->archdata.dma_ops_setup = true; - } else { + else dma_ops = arm_get_dma_map_ops(coherent); - dev->archdata.dma_ops_setup = false; - } set_dma_ops(dev, dma_ops); @@ -2734,6 +2731,7 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, dev->dma_ops = xen_dma_ops; } #endif + dev->archdata.dma_ops_setup = true; } EXPORT_SYMBOL(arch_setup_dma_ops); diff --git a/arch/arm/tools/syscallhdr.sh b/arch/arm/tools/syscallhdr.sh old mode 100644 new mode 100755 diff --git a/arch/arm/tools/syscallnr.sh b/arch/arm/tools/syscallnr.sh old mode 100644 new mode 100755 diff --git a/arch/arm/tools/syscalltbl.sh b/arch/arm/tools/syscalltbl.sh old mode 100644 new mode 100755 diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 0668ea29ca9c..7457f0e57125 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -522,16 +522,6 @@ config ARM64_ERRATUM_1286807 invalidated has been observed by other observers. The workaround repeats the TLBI+DSB operation. -config ARM64_ERRATUM_1188873 - bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" - default y - help - This option adds work arounds for ARM Cortex-A76 erratum 1188873 - - Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause - register corruption when accessing the timer registers from - AArch32 userspace. - If unsure, say Y. config CAVIUM_ERRATUM_22375 @@ -1465,3 +1455,4 @@ source "arch/arm64/crypto/Kconfig" endif source "lib/Kconfig" +source "coretech/Kconfig" diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 1b524f2c0433..6ce416f15959 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -186,16 +186,6 @@ config ARCH_QCS405 If you do not wish to build a kernel that runs on this chipset, say 'N' here. -config ARCH_QCS403 - bool "Enable Support for Qualcomm Technologies, Inc. QCS403" - depends on ARCH_QCOM - select COMMON_CLK_QCOM - help - This configuration option enables support to build kernel for - QCS403 SoC. - If you do not wish to build a kernel that runs on this chipset, - say 'N' here. - config ARCH_SDMMAGPIE bool "Enable Support for Qualcomm Technologies, Inc. SDMMAGPIE" depends on ARCH_QCOM diff --git a/arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi b/arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi deleted file mode 120000 index 68fd0f8f1dee..000000000000 --- a/arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi +++ /dev/null @@ -1 +0,0 @@ -../../../../arm/boot/dts/vexpress-v2m-rs1.dtsi \ No newline at end of file diff --git a/arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi b/arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi new file mode 100644 index 000000000000..35714ff6f467 --- /dev/null +++ b/arch/arm64/boot/dts/arm/vexpress-v2m-rs1.dtsi @@ -0,0 +1,442 @@ +/* + * ARM Ltd. Versatile Express + * + * Motherboard Express uATX + * V2M-P1 + * + * HBI-0190D + * + * RS1 memory map ("ARM Cortex-A Series memory map" in the board's + * Technical Reference Manual) + * + * WARNING! The hardware described in this file is independent from the + * original variant (vexpress-v2m.dtsi), but there is a strong + * correspondence between the two configurations. + * + * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT + * CHANGES TO vexpress-v2m.dtsi! + */ + + motherboard { + model = "V2M-P1"; + arm,hbi = <0x190>; + arm,vexpress,site = <0>; + arm,v2m-memory-map = "rs1"; + compatible = "arm,vexpress,v2m-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + flash@0,00000000 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <4 0x00000000 0x04000000>; + bank-width = <4>; + }; + + psram@1,00000000 { + compatible = "arm,vexpress-psram", "mtd-ram"; + reg = <1 0x00000000 0x02000000>; + bank-width = <4>; + }; + + v2m_video_ram: vram@2,00000000 { + compatible = "arm,vexpress-vram"; + reg = <2 0x00000000 0x00800000>; + }; + + ethernet@2,02000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <2 0x02000000 0x10000>; + interrupts = <15>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vdd33a-supply = <&v2m_fixed_3v3>; + vddvario-supply = <&v2m_fixed_3v3>; + }; + + usb@2,03000000 { + compatible = "nxp,usb-isp1761"; + reg = <2 0x03000000 0x20000>; + interrupts = <16>; + port1-otg; + }; + + iofpga@3,00000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + + v2m_sysreg: sysreg@10000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + + v2m_led_gpios: sys_led { + compatible = "arm,vexpress-sysreg,sys_led"; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_mmc_gpios: sys_mci { + compatible = "arm,vexpress-sysreg,sys_mci"; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_flash_gpios: sys_flash { + compatible = "arm,vexpress-sysreg,sys_flash"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + v2m_sysctl: sysctl@20000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; + assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; + }; + + /* PCI-E I2C bus */ + v2m_i2c_pcie: i2c@30000 { + compatible = "arm,versatile-i2c"; + reg = <0x030000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + pcie-switch@60 { + compatible = "idt,89hpes32h8"; + reg = <0x60>; + }; + }; + + aaci@40000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x040000 0x1000>; + interrupts = <11>; + clocks = <&smbclk>; + clock-names = "apb_pclk"; + }; + + mmci@50000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x050000 0x1000>; + interrupts = <9 10>; + cd-gpios = <&v2m_mmc_gpios 0 0>; + wp-gpios = <&v2m_mmc_gpios 1 0>; + max-frequency = <12000000>; + vmmc-supply = <&v2m_fixed_3v3>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "mclk", "apb_pclk"; + }; + + kmi@60000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x060000 0x1000>; + interrupts = <12>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@70000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x070000 0x1000>; + interrupts = <13>; + clocks = <&v2m_clk24mhz>, <&smbclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + v2m_serial0: uart@90000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x090000 0x1000>; + interrupts = <5>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial1: uart@a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a0000 0x1000>; + interrupts = <6>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial2: uart@b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b0000 0x1000>; + interrupts = <7>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial3: uart@c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c0000 0x1000>; + interrupts = <8>; + clocks = <&v2m_oscclk2>, <&smbclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + wdt@f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x1000>; + interrupts = <0>; + clocks = <&v2m_refclk32khz>, <&smbclk>; + clock-names = "wdogclk", "apb_pclk"; + }; + + v2m_timer01: timer@110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x1000>; + interrupts = <2>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x1000>; + interrupts = <3>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + /* DVI I2C bus */ + v2m_i2c_dvi: i2c@160000 { + compatible = "arm,versatile-i2c"; + reg = <0x160000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + dvi-transmitter@39 { + compatible = "sil,sii9022-tpi", "sil,sii9022"; + reg = <0x39>; + }; + + dvi-transmitter@60 { + compatible = "sil,sii9022-cpi", "sil,sii9022"; + reg = <0x60>; + }; + }; + + rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x1000>; + interrupts = <4>; + clocks = <&smbclk>; + clock-names = "apb_pclk"; + }; + + compact-flash@1a0000 { + compatible = "arm,vexpress-cf", "ata-generic"; + reg = <0x1a0000 0x100 + 0x1a0100 0xf00>; + reg-shift = <2>; + }; + + clcd@1f0000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f0000 0x1000>; + interrupt-names = "combined"; + interrupts = <14>; + clocks = <&v2m_oscclk1>, <&smbclk>; + clock-names = "clcdclk", "apb_pclk"; + memory-region = <&v2m_video_ram>; + max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */ + + port { + v2m_clcd_pads: endpoint { + remote-endpoint = <&v2m_clcd_panel>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + + panel { + compatible = "panel-dpi"; + + port { + v2m_clcd_panel: endpoint { + remote-endpoint = <&v2m_clcd_pads>; + }; + }; + + panel-timing { + clock-frequency = <25175000>; + hactive = <640>; + hback-porch = <40>; + hfront-porch = <24>; + hsync-len = <96>; + vactive = <480>; + vback-porch = <32>; + vfront-porch = <11>; + vsync-len = <2>; + }; + }; + }; + }; + + v2m_fixed_3v3: fixed-regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + leds { + compatible = "gpio-leds"; + + user1 { + label = "v2m:green:user1"; + gpios = <&v2m_led_gpios 0 0>; + linux,default-trigger = "heartbeat"; + }; + + user2 { + label = "v2m:green:user2"; + gpios = <&v2m_led_gpios 1 0>; + linux,default-trigger = "mmc0"; + }; + + user3 { + label = "v2m:green:user3"; + gpios = <&v2m_led_gpios 2 0>; + linux,default-trigger = "cpu0"; + }; + + user4 { + label = "v2m:green:user4"; + gpios = <&v2m_led_gpios 3 0>; + linux,default-trigger = "cpu1"; + }; + + user5 { + label = "v2m:green:user5"; + gpios = <&v2m_led_gpios 4 0>; + linux,default-trigger = "cpu2"; + }; + + user6 { + label = "v2m:green:user6"; + gpios = <&v2m_led_gpios 5 0>; + linux,default-trigger = "cpu3"; + }; + + user7 { + label = "v2m:green:user7"; + gpios = <&v2m_led_gpios 6 0>; + linux,default-trigger = "cpu4"; + }; + + user8 { + label = "v2m:green:user8"; + gpios = <&v2m_led_gpios 7 0>; + linux,default-trigger = "cpu5"; + }; + }; + + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + oscclk0 { + /* MCC static memory clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <25000000 60000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk0"; + }; + + v2m_oscclk1: oscclk1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 65000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; + + v2m_oscclk2: oscclk2 { + /* IO FPGA peripheral clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <24000000 24000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk2"; + }; + + volt-vio { + /* Logic level voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "VIO"; + regulator-always-on; + label = "VIO"; + }; + + temp-mcc { + /* MCC internal operating temperature */ + compatible = "arm,vexpress-temp"; + arm,vexpress-sysreg,func = <4 0>; + label = "MCC"; + }; + + reset { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; + + muxfpga { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + shutdown { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; + + reboot { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; + + dvimode { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + }; diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index e7157c9d7534..7480090de710 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY_QCOM),y) dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb @@ -6,26 +7,27 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb - -dtb-$(CONFIG_ARCH_QCS403) += qcs403-iot-sku1.dtb \ - qcs403-iot-sku3.dtb \ - qcs403-iot-sku5.dtb \ - qcs401-iot-sku5.dtb \ - qcs404-iot-sku3.dtb \ - qcs404-iot-sku5.dtb \ - qcs404-iot-sku6.dtb - -dtb-$(CONFIG_ARCH_QCS405) += qcs405-iot-sku1.dtb \ - qcs407-iot-sku1.dtb \ +ifeq ($(CONFIG_ARM64),y) +dtb-$(CONFIG_ARCH_QCS405) += qcs405-rumi.dtb \ + qcs405-iot-sku1.dtb \ + qcs405-iot-sku2.dtb \ qcs405-iot-sku3.dtb \ - qcs407-iot-sku3.dtb \ qcs405-iot-sku4.dtb \ - qcs407-iot-sku4.dtb \ + qcs405-iot-sku5.dtb \ qcs405-iot-sku6.dtb \ - qcs407-iot-sku6.dtb \ - qcs407-iot-sku9.dtb \ + qcs405-iot-sku7.dtb \ + qcs405-iot-sku8.dtb \ + qcs405-iot-sku9.dtb \ + qcs405-iot-sku10.dtb \ + qcs405-iot-sku11.dtb \ qcs405-iot-sku12.dtb \ - qcs407-iot-sku12.dtb + qcs401-iot-sku1.dtb +else +dtb-$(CONFIG_ARCH_QCS405) += qcs403-iot-sku1.dtb \ + qcs403-iot-sku2.dtb \ + qcs403-iot-sku3.dtb \ + qcs403-iot-sku4.dtb +endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_SM8150) += \ @@ -68,6 +70,58 @@ sm8150-sdx50m-mtp-2.5k-panel-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm815 sm8150-sdx50m-qrd-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb sm8150-sdxprairie-cdp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb sm8150-sdxprairie-mtp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +endif +endif + +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) + dtbo-$(CONFIG_ARCH_SM8150) += \ + sm8150-mtp-overlay.dtbo \ + sm8150-sdxprairie-mtp-overlay.dtbo \ + guacamole-overlay-t0.dtbo \ + guacamole-overlay-evt1.dtbo \ + guacamole-overlay-evt2.dtbo \ + guacamole-overlay-evt2-second.dtbo \ + guacamole-overlay-evt3.dtbo \ + guacamole-overlay-dvt.dtbo \ + guacamole-overlay-pvt.dtbo \ + guacamoleb-overlay-t0.dtbo \ + guacamoleb-overlay-evt.dtbo \ + guacamoleb-overlay-dvt.dtbo \ + guacamoleb-overlay-pvt.dtbo \ + sm8150-sdx50m-mtp-overlay.dtbo \ + guacamole-sdx50m-overlay-t0.dtbo \ + guacamole-sdx50m-overlay-evt1.dtbo \ + guacamole-sdx50m-overlay-evt2.dtbo \ + guacamole-sdx50m-overlay-dvt.dtbo \ + guacamole-sdx50m-overlay-pvt.dtbo \ + guacamoles-sdx50m-overlay-t0.dtbo \ + guacamoles-sdx50m-overlay-evt.dtbo \ + guacamoles-sdx50m-overlay-dvt.dtbo \ + guacamoles-sdx50m-overlay-pvt.dtbo + +sm8150-mtp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +sm8150-sdxprairie-mtp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-t0.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-evt1.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-evt2.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-evt2-second.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-evt3.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-dvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-pvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoleb-overlay-t0.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoleb-overlay-evt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoleb-overlay-dvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoleb-overlay-pvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +sm8150-sdx50m-mtp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-sdx50m-overlay-t0.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-sdx50m-overlay-evt1.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-sdx50m-overlay-evt2.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-sdx50m-overlay-dvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-sdx50m-overlay-pvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoles-sdx50m-overlay-t0.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoles-sdx50m-overlay-evt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoles-sdx50m-overlay-dvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamoles-sdx50m-overlay-pvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb sm8150-sdxprairie-v2-cdp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb sm8150-sdxprairie-v2-mtp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb else @@ -246,24 +300,15 @@ endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_ATOLL) += \ atoll-idp-overlay.dtbo\ - atoll-atp-overlay.dtbo\ atoll-qrd-overlay.dtbo\ - atoll-wcd937x-idp-overlay.dtbo\ - atoll-usbc-idp-overlay.dtbo\ atoll-rumi-overlay.dtbo atoll-idp-overlay.dtbo-base := atoll.dtb -atoll-atp-overlay.dtbo-base := atoll.dtb atoll-qrd-overlay.dtbo-base := atoll.dtb atoll-rumi-overlay.dtbo-base := atoll.dtb -atoll-wcd937x-idp-overlay.dtbo-base := atoll.dtb -atoll-usbc-idp-overlay.dtbo-base := atoll.dtb else dtb-$(CONFIG_ARCH_ATOLL) += atoll-idp.dtb\ - atoll-atp.dtb\ atoll-qrd.dtb\ - atoll-wcd937x-idp.dtb\ - atoll-usbc-idp.dtb\ atoll-rumi.dtb endif diff --git a/arch/arm64/boot/dts/qcom/OP-fg-batterydata-3700mah.dtsi b/arch/arm64/boot/dts/qcom/OP-fg-batterydata-3700mah.dtsi new file mode 100644 index 000000000000..131fb2dc9e0d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/OP-fg-batterydata-3700mah.dtsi @@ -0,0 +1,144 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,OP_3700mAh { + qcom,max-voltage-uv = <4370000>; + qcom,fastchg-current-ma = <3000>; + qcom,jeita-fcc-ranges = <0 100 2500000 + 110 400 5400000 + 410 450 2500000>; + qcom,jeita-fv-ranges = <0 100 4250000 + 110 400 4350000 + 410 450 4250000>; + qcom,step-chg-ranges = <3600000 3800000 5400000 + 3801000 4300000 3600000 + 4301000 4350000 2500000>; + qcom,ocv-based-step-chg; + qcom,batt-id-kohm = <200>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,fg-cc-cv-threshold-mv = <4340>; + qcom,battery-type = "OP_3700mAh"; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0xdf 0x02 0x77 0x1a>; + qcom,rslow-low-coeffs = <0x51 0x04 0xd0 0x13>; + qcom,checksum = <0x1538>; + qcom,gui-version = "PM855GUI - 1.0.0.10"; + qcom,fg-profile-data = [ + 09 00 C7 EA + C4 DC 8E E2 + 3A DD 00 00 + 15 BC A5 8A + 02 80 D1 92 + AB 9D 47 80 + 10 00 DF 02 + 77 1A 85 EC + E1 FD CE 07 + 32 00 75 EB + AA ED F3 CD + 0C 0A 7A E4 + ED C5 40 1B + D0 02 1F CA + FF 00 52 00 + 4D 00 4A 00 + 3C 00 35 00 + 38 00 39 00 + 48 00 43 00 + 3F 00 FF 00 + 38 00 40 00 + 46 00 50 00 + 45 00 5C 00 + 7E 64 60 00 + 50 08 50 10 + FF 00 6A 00 + 5F 00 63 00 + 6E 00 60 00 + 7D 20 96 40 + 75 50 6B 13 + 63 00 D8 00 + 14 22 7E 0D + 21 02 AA 04 + ED 1C D4 09 + 64 0C D3 23 + A4 18 D3 42 + B5 55 91 02 + 90 12 2A 1F + 02 06 1F 0A + A3 06 AE 1C + 8D 02 96 04 + D2 03 D1 17 + 51 23 3F 45 + 28 53 69 14 + 93 20 8E EC + 18 CB C8 C5 + DB 1C 7B C9 + 7C 05 E6 C2 + B9 17 2C 93 + 87 85 A2 92 + 91 A8 09 80 + 92 F2 1A 0D + F4 FC 5E EB + 00 F8 FB ED + 15 E2 F6 0F + 75 02 72 05 + 49 01 10 00 + FA E5 E2 03 + 8D 05 85 02 + CE 07 32 00 + 23 03 46 02 + 9C 04 03 02 + 48 07 0A 00 + BA 03 97 02 + 65 05 50 00 + 3A 00 41 00 + 43 64 45 00 + 45 10 45 18 + 46 08 44 00 + 47 00 3A 08 + 4B 08 37 00 + 47 20 4E 40 + 54 58 60 10 + 57 00 5F 00 + 57 08 55 00 + 4B 00 50 00 + 3E 08 52 08 + 52 00 5C 20 + 6F 40 7D 58 + 67 10 63 00 + 69 08 4F 10 + D8 00 8C 2A + DB 04 28 02 + AD 04 0B 1D + 50 22 A7 45 + 0D 52 A2 18 + 74 03 AD 04 + 35 02 AE 13 + 3F 0A 5A 20 + DD 04 F1 02 + D8 05 C7 1C + DD 02 3D 04 + EB 03 97 18 + 52 03 D5 04 + 19 02 72 00 + 14 22 7E 05 + 21 02 AA 04 + ED 1C D4 01 + 64 04 D3 03 + A4 18 D3 02 + B5 05 91 02 + 90 00 7C 01 + C0 00 FA 00 + 04 0E 00 00 + ]; +}; diff --git a/arch/arm64/boot/dts/qcom/OP-fg-batterydata-3800mah.dtsi b/arch/arm64/boot/dts/qcom/OP-fg-batterydata-3800mah.dtsi new file mode 100644 index 000000000000..f24c758591f2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/OP-fg-batterydata-3800mah.dtsi @@ -0,0 +1,144 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,OP_3800mAh { + qcom,max-voltage-uv = <4370000>; + qcom,fastchg-current-ma = <3000>; + qcom,jeita-fcc-ranges = <0 100 2500000 + 110 400 5400000 + 410 450 2500000>; + qcom,jeita-fv-ranges = <0 100 4250000 + 110 400 4350000 + 410 450 4250000>; + qcom,step-chg-ranges = <3600000 3800000 5400000 + 3801000 4300000 3600000 + 4301000 4350000 2500000>; + qcom,ocv-based-step-chg; + qcom,batt-id-kohm = <200>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,fg-cc-cv-threshold-mv = <4340>; + qcom,battery-type = "OP_3800mAh"; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0xdf 0x02 0x77 0x1a>; + qcom,rslow-low-coeffs = <0x51 0x04 0xd0 0x13>; + qcom,checksum = <0x1538>; + qcom,gui-version = "PM855GUI - 1.0.0.10"; + qcom,fg-profile-data = [ + 09 00 C7 EA + C4 DC 8E E2 + 3A DD 00 00 + 15 BC A5 8A + 02 80 D1 92 + AB 9D 47 80 + 10 00 DF 02 + 77 1A 85 EC + E1 FD CE 07 + 32 00 75 EB + AA ED F3 CD + 0C 0A 7A E4 + ED C5 40 1B + D0 02 1F CA + FF 00 52 00 + 4D 00 4A 00 + 3C 00 35 00 + 38 00 39 00 + 48 00 43 00 + 3F 00 FF 00 + 38 00 40 00 + 46 00 50 00 + 45 00 5C 00 + 7E 64 60 00 + 50 08 50 10 + FF 00 6A 00 + 5F 00 63 00 + 6E 00 60 00 + 7D 20 96 40 + 75 50 6B 13 + 63 00 D8 00 + 14 22 7E 0D + 21 02 AA 04 + ED 1C D4 09 + 64 0C D3 23 + A4 18 D3 42 + B5 55 91 02 + 90 12 2A 1F + 02 06 1F 0A + A3 06 AE 1C + 8D 02 96 04 + D2 03 D1 17 + 51 23 3F 45 + 28 53 69 14 + 93 20 8E EC + 18 CB C8 C5 + DB 1C 7B C9 + 7C 05 E6 C2 + B9 17 2C 93 + 87 85 A2 92 + 91 A8 09 80 + 92 F2 1A 0D + F4 FC 5E EB + 00 F8 FB ED + 15 E2 F6 0F + 75 02 72 05 + 49 01 10 00 + FA E5 E2 03 + 8D 05 85 02 + CE 07 32 00 + 23 03 46 02 + 9C 04 03 02 + 48 07 0A 00 + BA 03 97 02 + 65 05 50 00 + 3A 00 41 00 + 43 64 45 00 + 45 10 45 18 + 46 08 44 00 + 47 00 3A 08 + 4B 08 37 00 + 47 20 4E 40 + 54 58 60 10 + 57 00 5F 00 + 57 08 55 00 + 4B 00 50 00 + 3E 08 52 08 + 52 00 5C 20 + 6F 40 7D 58 + 67 10 63 00 + 69 08 4F 10 + D8 00 8C 2A + DB 04 28 02 + AD 04 0B 1D + 50 22 A7 45 + 0D 52 A2 18 + 74 03 AD 04 + 35 02 AE 13 + 3F 0A 5A 20 + DD 04 F1 02 + D8 05 C7 1C + DD 02 3D 04 + EB 03 97 18 + 52 03 D5 04 + 19 02 72 00 + 14 22 7E 05 + 21 02 AA 04 + ED 1C D4 01 + 64 04 D3 03 + A4 18 D3 02 + B5 05 91 02 + 90 00 7C 01 + C0 00 FA 00 + 04 0E 00 00 + ]; +}; diff --git a/arch/arm64/boot/dts/qcom/OP-fg-batterydata-4000mah.dtsi b/arch/arm64/boot/dts/qcom/OP-fg-batterydata-4000mah.dtsi new file mode 100644 index 000000000000..3f0116c033ba --- /dev/null +++ b/arch/arm64/boot/dts/qcom/OP-fg-batterydata-4000mah.dtsi @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,OP_4000mAh { + qcom,max-voltage-uv = <4370000>; + qcom,fastchg-current-ma = <3000>; + qcom,jeita-fcc-ranges = <0 100 2500000 + 110 400 5400000 + 410 450 2500000>; + qcom,jeita-fv-ranges = <0 100 4250000 + 110 400 4350000 + 410 450 4250000>; + qcom,step-chg-ranges = <3600000 3800000 5400000 + 3801000 4300000 3600000 + 4301000 4350000 2500000>; + qcom,ocv-based-step-chg; + qcom,batt-id-kohm = <200>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,fg-cc-cv-threshold-mv = <4340>; + qcom,battery-type = "OP_4000mAh "; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0xdf 0x02 0x77 0x1a>; + qcom,rslow-low-coeffs = <0x51 0x04 0xd0 0x13>; + qcom,checksum = <0x1538>; + qcom,gui-version = "PM855GUI - 1.0.0.10"; + qcom,fg-profile-data = [ + 09 00 C7 EA + C4 DC 8E E2 + 3A DD 00 00 + 15 BC A5 8A + 02 80 D1 92 + AB 9D 47 80 + 10 00 DF 02 + 77 1A 85 EC + E1 FD CE 07 + 32 00 75 EB + AA ED F3 CD + 0C 0A 7A E4 + ED C5 40 1B + D0 02 1F CA + FF 00 52 00 + 4D 00 4A 00 + 3C 00 35 00 + 38 00 39 00 + 48 00 43 00 + 3F 00 FF 00 + 38 00 40 00 + 46 00 50 00 + 45 00 5C 00 + 7E 64 60 00 + 50 08 50 10 + FF 00 6A 00 + 5F 00 63 00 + 6E 00 60 00 + 7D 20 96 40 + 75 50 6B 13 + 63 00 D8 00 + 14 22 7E 0D + 21 02 AA 04 + ED 1C D4 09 + 64 0C D3 23 + A4 18 D3 42 + B5 55 91 02 + 90 12 2A 1F + 02 06 1F 0A + A3 06 AE 1C + 8D 02 96 04 + D2 03 D1 17 + 51 23 3F 45 + 28 53 69 14 + 93 20 8E EC + 18 CB C8 C5 + DB 1C 7B C9 + 7C 05 E6 C2 + B9 17 2C 93 + 87 85 A2 92 + 91 A8 09 80 + 92 F2 1A 0D + F4 FC 5E EB + 00 F8 FB ED + 15 E2 F6 0F + 75 02 72 05 + 49 01 10 00 + FA E5 E2 03 + 8D 05 85 02 + CE 07 32 00 + 23 03 46 02 + 9C 04 03 02 + 48 07 0A 00 + BA 03 97 02 + 65 05 50 00 + 3A 00 41 00 + 43 64 45 00 + 45 10 45 18 + 46 08 44 00 + 47 00 3A 08 + 4B 08 37 00 + 47 20 4E 40 + 54 58 60 10 + 57 00 5F 00 + 57 08 55 00 + 4B 00 50 00 + 3E 08 52 08 + 52 00 5C 20 + 6F 40 7D 58 + 67 10 63 00 + 69 08 4F 10 + D8 00 8C 2A + DB 04 28 02 + AD 04 0B 1D + 50 22 A7 45 + 0D 52 A2 18 + 74 03 AD 04 + 35 02 AE 13 + 3F 0A 5A 20 + DD 04 F1 02 + D8 05 C7 1C + DD 02 3D 04 + EB 03 97 18 + 52 03 D5 04 + 19 02 72 00 + 14 22 7E 05 + 21 02 AA 04 + ED 1C D4 01 + 64 04 D3 03 + A4 18 D3 02 + B5 05 91 02 + 90 00 7C 01 + C0 00 FA 00 + 04 0E 00 00 + ]; +}; diff --git a/arch/arm64/boot/dts/qcom/OP-fg-batterydata-4085mah.dtsi b/arch/arm64/boot/dts/qcom/OP-fg-batterydata-4085mah.dtsi new file mode 100644 index 000000000000..c6c284df1b9b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/OP-fg-batterydata-4085mah.dtsi @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,OP_4085mAh { + qcom,max-voltage-uv = <4370000>; + qcom,fastchg-current-ma = <3000>; + qcom,jeita-fcc-ranges = <0 100 2500000 + 110 400 5400000 + 410 450 2500000>; + qcom,jeita-fv-ranges = <0 100 4250000 + 110 400 4350000 + 410 450 4250000>; + qcom,step-chg-ranges = <3600000 3800000 5400000 + 3801000 4300000 3600000 + 4301000 4350000 2500000>; + qcom,ocv-based-step-chg; + qcom,batt-id-kohm = <200>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,fg-cc-cv-threshold-mv = <4340>; + qcom,battery-type = "OP_4085mAh "; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0xdf 0x02 0x77 0x1a>; + qcom,rslow-low-coeffs = <0x51 0x04 0xd0 0x13>; + qcom,checksum = <0x1538>; + qcom,gui-version = "PM855GUI - 1.0.0.10"; + qcom,fg-profile-data = [ + 09 00 C7 EA + C4 DC 8E E2 + 3A DD 00 00 + 15 BC A5 8A + 02 80 D1 92 + AB 9D 47 80 + 10 00 DF 02 + 77 1A 85 EC + E1 FD CE 07 + 32 00 75 EB + AA ED F3 CD + 0C 0A 7A E4 + ED C5 40 1B + D0 02 1F CA + FF 00 52 00 + 4D 00 4A 00 + 3C 00 35 00 + 38 00 39 00 + 48 00 43 00 + 3F 00 FF 00 + 38 00 40 00 + 46 00 50 00 + 45 00 5C 00 + 7E 64 60 00 + 50 08 50 10 + FF 00 6A 00 + 5F 00 63 00 + 6E 00 60 00 + 7D 20 96 40 + 75 50 6B 13 + 63 00 D8 00 + 14 22 7E 0D + 21 02 AA 04 + ED 1C D4 09 + 64 0C D3 23 + A4 18 D3 42 + B5 55 91 02 + 90 12 2A 1F + 02 06 1F 0A + A3 06 AE 1C + 8D 02 96 04 + D2 03 D1 17 + 51 23 3F 45 + 28 53 69 14 + 93 20 8E EC + 18 CB C8 C5 + DB 1C 7B C9 + 7C 05 E6 C2 + B9 17 2C 93 + 87 85 A2 92 + 91 A8 09 80 + 92 F2 1A 0D + F4 FC 5E EB + 00 F8 FB ED + 15 E2 F6 0F + 75 02 72 05 + 49 01 10 00 + FA E5 E2 03 + 8D 05 85 02 + CE 07 32 00 + 23 03 46 02 + 9C 04 03 02 + 48 07 0A 00 + BA 03 97 02 + 65 05 50 00 + 3A 00 41 00 + 43 64 45 00 + 45 10 45 18 + 46 08 44 00 + 47 00 3A 08 + 4B 08 37 00 + 47 20 4E 40 + 54 58 60 10 + 57 00 5F 00 + 57 08 55 00 + 4B 00 50 00 + 3E 08 52 08 + 52 00 5C 20 + 6F 40 7D 58 + 67 10 63 00 + 69 08 4F 10 + D8 00 8C 2A + DB 04 28 02 + AD 04 0B 1D + 50 22 A7 45 + 0D 52 A2 18 + 74 03 AD 04 + 35 02 AE 13 + 3F 0A 5A 20 + DD 04 F1 02 + D8 05 C7 1C + DD 02 3D 04 + EB 03 97 18 + 52 03 D5 04 + 19 02 72 00 + 14 22 7E 05 + 21 02 AA 04 + ED 1C D4 01 + 64 04 D3 03 + A4 18 D3 02 + B5 05 91 02 + 90 00 7C 01 + C0 00 FA 00 + 04 0E 00 00 + ]; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll-coresight.dtsi b/arch/arm64/boot/dts/qcom/atoll-coresight.dtsi index 30469db9e54b..1cd3070a7918 100644 --- a/arch/arm64/boot/dts/qcom/atoll-coresight.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-coresight.dtsi @@ -240,7 +240,7 @@ compatible = "qcom,coresight-remote-etm"; coresight-name = "coresight-npu-etm0"; - qcom,inst-id = <14>; + qcom,inst-id = <2>; port { npu_etm0_out_funnel_npu: endpoint { diff --git a/arch/arm64/boot/dts/qcom/atoll-gdsc.dtsi b/arch/arm64/boot/dts/qcom/atoll-gdsc.dtsi index 0eba4a21ff28..723bdb0495c8 100644 --- a/arch/arm64/boot/dts/qcom/atoll-gdsc.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-gdsc.dtsi @@ -14,7 +14,7 @@ &soc { /* GDSCs in Global CC */ ufs_phy_gdsc: qcom,gdsc@177004 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "ufs_phy_gdsc"; reg = <0x177004 0x4>; qcom,poll-cfg-gdscr; @@ -22,7 +22,7 @@ }; usb30_prim_gdsc: qcom,gdsc@10f004 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "usb30_prim_gdsc"; reg = <0x10f004 0x4>; qcom,poll-cfg-gdscr; @@ -30,7 +30,7 @@ }; hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d040 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; reg = <0x17d040 0x4>; qcom,no-status-check-on-disable; @@ -39,7 +39,7 @@ }; hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@17d044 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc"; reg = <0x17d044 0x4>; qcom,no-status-check-on-disable; @@ -49,7 +49,7 @@ /* GDSCs in Camera CC */ bps_gdsc: qcom,gdsc@ad06004 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "bps_gdsc"; reg = <0xad06004 0x4>; qcom,poll-cfg-gdscr; @@ -57,7 +57,7 @@ }; ipe_0_gdsc: qcom,gdsc@ad07004 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "ipe_0_gdsc"; reg = <0xad07004 0x4>; qcom,poll-cfg-gdscr; @@ -65,7 +65,7 @@ }; ife_0_gdsc: qcom,gdsc@ad09004 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "ife_0_gdsc"; reg = <0xad09004 0x4>; qcom,poll-cfg-gdscr; @@ -73,7 +73,7 @@ }; ife_1_gdsc: qcom,gdsc@ad0a004 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "ife_1_gdsc"; reg = <0xad0a004 0x4>; qcom,poll-cfg-gdscr; @@ -81,7 +81,7 @@ }; titan_top_gdsc: qcom,gdsc@ad0b134 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "titan_top_gdsc"; reg = <0xad0b134 0x4>; qcom,poll-cfg-gdscr; @@ -90,7 +90,7 @@ /* GDSCs in Display CC */ mdss_core_gdsc: qcom,gdsc@af03000 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "mdss_core_gdsc"; reg = <0xaf03000 0x4>; qcom,poll-cfg-gdscr; @@ -117,7 +117,7 @@ }; gpu_cx_gdsc: qcom,gdsc@509106c { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "gpu_cx_gdsc"; reg = <0x509106c 0x4>; hw-ctrl-addr = <&gpu_cx_hw_ctrl>; @@ -128,7 +128,7 @@ }; gpu_gx_gdsc: qcom,gdsc@509100c { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "gpu_gx_gdsc"; reg = <0x509100c 0x4>; qcom,poll-cfg-gdscr; @@ -139,14 +139,14 @@ /* GDSCs in Video CC */ vcodec0_gdsc: qcom,gdsc@ab00874 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "vcodec0_gdsc"; reg = <0xab00874 0x4>; status = "disabled"; }; venus_gdsc: qcom,gdsc@ab00814 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "venus_gdsc"; reg = <0xab00814 0x4>; status = "disabled"; @@ -154,7 +154,7 @@ /* GDSCs in NPU CC */ npu_core_gdsc: qcom,gdsc@9981004 { - compatible = "qcom,gdsc"; + compatible = "regulator-fixed"; regulator-name = "npu_core_gdsc"; reg = <0x9981004 0x4>; status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/atoll-idp-overlay.dts b/arch/arm64/boot/dts/qcom/atoll-idp-overlay.dts index aec924073293..46b35d146ce3 100644 --- a/arch/arm64/boot/dts/qcom/atoll-idp-overlay.dts +++ b/arch/arm64/boot/dts/qcom/atoll-idp-overlay.dts @@ -16,7 +16,6 @@ #include #include "atoll-idp.dtsi" -#include "atoll-audio-overlay.dtsi" / { model = "IDP"; @@ -24,7 +23,3 @@ qcom,msm-id = <407 0x0>; qcom,board-id = <34 0>; }; - -&dsi_rm69299_visionox_amoled_vid_display { - qcom,dsi-display-active; -}; diff --git a/arch/arm64/boot/dts/qcom/atoll-idp.dts b/arch/arm64/boot/dts/qcom/atoll-idp.dts index dcd5edb3d055..ff2b4c4266c9 100644 --- a/arch/arm64/boot/dts/qcom/atoll-idp.dts +++ b/arch/arm64/boot/dts/qcom/atoll-idp.dts @@ -20,7 +20,3 @@ compatible = "qcom,atoll-idp", "qcom,atoll", "qcom,idp"; qcom,board-id = <34 0>; }; - -&dsi_rm69299_visionox_amoled_vid_display { - qcom,dsi-display-active; -}; diff --git a/arch/arm64/boot/dts/qcom/atoll-idp.dtsi b/arch/arm64/boot/dts/qcom/atoll-idp.dtsi index 56ae442900f0..a9c5ba4e4177 100644 --- a/arch/arm64/boot/dts/qcom/atoll-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-idp.dtsi @@ -10,18 +10,9 @@ * GNU General Public License for more details. */ -#include -#include #include -#include -#include "atoll-sde-display.dtsi" -#include "atoll-camera-sensor-idp.dtsi" &soc { - mtp_batterydata: qcom,battery-data { - qcom,batt-id-range-pct = <15>; - #include "qg-batterydata-alium-3600mah.dtsi" - }; }; &pm6150l_vadc { @@ -66,77 +57,6 @@ }; }; -&usb0 { - extcon = <&pm6150_pdphy>, <&pm6150_charger>, <&eud>; -}; - -&usb_qmp_dp_phy { - extcon = <&pm6150_pdphy>; -}; - -&ufsphy_mem { - compatible = "qcom,ufs-phy-qmp-v3"; - - vdda-phy-supply = <&pm6150_l4>; /* 0.9v */ - vdda-pll-supply = <&pm6150l_l3>; /* 1.2v */ - vdda-phy-max-microamp = <62900>; - vdda-pll-max-microamp = <18300>; - - status = "ok"; -}; - -&ufshc_mem { - vdd-hba-supply = <&ufs_phy_gdsc>; - vdd-hba-fixed-regulator; - vcc-supply = <&pm6150_l19>; - vcc-voltage-level = <2950000 2960000>; - vcc-max-microamp = <600000>; - vccq2-supply = <&pm6150_l12>; - vccq2-voltage-level = <1750000 1950000>; - vccq2-max-microamp = <600000>; - - qcom,vddp-ref-clk-supply = <&pm6150l_l3>; /* PX10 */ - qcom,vddp-ref-clk-max-microamp = <100>; - - status = "ok"; -}; - -&sdhc_1 { - vdd-supply = <&pm6150_l19>; - qcom,vdd-voltage-level = <2950000 2950000>; - qcom,vdd-current-level = <0 570000>; - - vdd-io-supply = <&pm6150_l12>; - qcom,vdd-io-always-on; - qcom,vdd-io-lpm-sup; - qcom,vdd-io-voltage-level = <1800000 1800000>; - qcom,vdd-io-current-level = <0 325000>; - - pinctrl-names = "active", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; - - status = "ok"; -}; - -&sdhc_2 { - vdd-supply = <&pm6150l_l9>; - qcom,vdd-voltage-level = <2950000 2950000>; - qcom,vdd-current-level = <0 800000>; - - vdd-io-supply = <&pm6150l_l6>; - qcom,vdd-io-voltage-level = <1800000 2950000>; - qcom,vdd-io-current-level = <0 22000>; - - pinctrl-names = "active", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - - cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>; - - status = "ok"; -}; - &spmi_bus { qcom,pm6150l@4 { pm6150l_adc_tm_iio: adc_tm@3400 { @@ -185,113 +105,3 @@ }; }; }; - -&pm6150a_amoled { - status = "ok"; -}; - -&pm6150_qg { - qcom,battery-data = <&mtp_batterydata>; - qcom,qg-iterm-ma = <100>; - qcom,hold-soc-while-full; - qcom,linearize-soc; - qcom,cl-feedback-on; -}; - -&pm6150_charger { - io-channels = <&pm6150_vadc ADC_USB_IN_V_16>, - <&pm6150_vadc ADC_USB_IN_I>, - <&pm6150_vadc ADC_CHG_TEMP>, - <&pm6150_vadc ADC_DIE_TEMP>, - <&pm6150_vadc ADC_AMUX_THM3_PU2>, - <&pm6150_vadc ADC_SBUx>, - <&pm6150_vadc ADC_VPH_PWR>; - io-channel-names = "usb_in_voltage", - "usb_in_current", - "chg_temp", - "die_temp", - "conn_temp", - "sbux_res", - "vph_voltage"; - qcom,battery-data = <&mtp_batterydata>; - qcom,auto-recharge-soc = <98>; - qcom,step-charging-enable; - qcom,sw-jeita-enable; - qcom,fcc-stepping-enable; - qcom,suspend-input-on-debug-batt; - qcom,sec-charger-config = <3>; - qcom,thermal-mitigation = <4200000 3500000 3000000 - 2500000 2000000 1500000 1000000 500000>; - dpdm-supply = <&qusb_phy0>; - qcom,charger-temp-max = <800>; - qcom,smb-temp-max = <800>; -}; - -&pm6150l_gpios { - key_vol_up { - key_vol_up_default: key_vol_up_default { - pins = "gpio2"; - function = "normal"; - input-enable; - bias-pull-up; - power-source = <0>; - }; - }; -}; - -&soc { - gpio_keys { - compatible = "gpio-keys"; - label = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&key_vol_up_default>; - - vol_up { - label = "volume_up"; - gpios = <&pm6150l_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - linux,can-disable; - debounce-interval = <15>; - gpio-key,wakeup; - }; - }; -}; - -&qupv3_se7_i2c { - status = "ok"; - - synaptics_tcm@20 { - compatible = "synaptics,tcm-i2c"; - reg = <0x20>; - interrupt-parent = <&tlmm>; - interrupts = <9 0x2008>; - pinctrl-names = "pmx_ts_active","pmx_ts_suspend", - "pmx_ts_release"; - pinctrl-0 = <&ts_active>; - pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; - pinctrl-2 = <&ts_release>; - vdd-supply = <&pm6150_l10>; - avdd-supply = <&pm6150l_l7>; - synaptics,pwr-reg-name = "avdd"; - synaptics,bus-reg-name = "vdd"; - synaptics,irq-gpio = <&tlmm 9 0x2008>; - synaptics,irq-on-state = <0>; - synaptics,reset-gpio = <&tlmm 8 0x00>; - synaptics,reset-on-state = <0>; - synaptics,reset-active-ms = <20>; - synaptics,reset-delay-ms = <200>; - synaptics,power-delay-ms = <200>; - synaptics,ubl-i2c-addr = <0x20>; - }; -}; - -&dsi_rm69299_visionox_amoled_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <255>; - qcom,platform-te-gpio = <&tlmm 10 0>; - qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>; -}; diff --git a/arch/arm64/boot/dts/qcom/atoll-ion.dtsi b/arch/arm64/boot/dts/qcom/atoll-ion.dtsi index 533574d8ff04..fa7262d64552 100644 --- a/arch/arm64/boot/dts/qcom/atoll-ion.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-ion.dtsi @@ -27,12 +27,6 @@ qcom,ion-heap-type = "DMA"; }; - qcom,ion-heap@19 { /* QSEECOM TA HEAP */ - reg = <19>; - memory-region = <&qseecom_ta_mem>; - qcom,ion-heap-type = "DMA"; - }; - qcom,ion-heap@9 { reg = <9>; qcom,ion-heap-type = "SYSTEM_SECURE"; @@ -43,14 +37,5 @@ memory-region = <&secure_display_memory>; qcom,ion-heap-type = "HYP_CMA"; }; - - qcom,ion-heap@14 { /* SECURE CARVEOUT HEAP */ - reg = <14>; - qcom,ion-heap-type = "SECURE_CARVEOUT"; - cdsp { - memory-region = <&cdsp_sec_mem>; - token = <0x20000000>; - }; - }; }; }; diff --git a/arch/arm64/boot/dts/qcom/atoll-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/atoll-pinctrl.dtsi index 46589b2972c8..328f975d136b 100644 --- a/arch/arm64/boot/dts/qcom/atoll-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-pinctrl.dtsi @@ -218,772 +218,6 @@ }; }; - qupv3_se0_spi_pins: qupv3_se0_spi_pins { - qupv3_se0_spi_active: qupv3_se0_spi_active { - mux { - pins = "gpio34", "gpio35", - "gpio36", "gpio37"; - function = "qup00"; - }; - - config { - pins = "gpio34", "gpio35", - "gpio36", "gpio37"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { - mux { - pins = "gpio34", "gpio35", - "gpio36", "gpio37"; - function = "gpio"; - }; - - config { - pins = "gpio34", "gpio35", - "gpio36", "gpio37"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - qupv3_se1_spi_pins: qupv3_se1_spi_pins { - qupv3_se1_spi_active: qupv3_se1_spi_active { - mux { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - function = "qup01"; - }; - - config { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { - mux { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - function = "gpio"; - }; - - config { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - qupv3_se3_spi_pins: qupv3_se3_spi_pins { - qupv3_se3_spi_active: qupv3_se3_spi_active { - mux { - pins = "gpio38", "gpio39", - "gpio40 ", "gpio41"; - function = "qup03"; - }; - - config { - pins = "gpio38", "gpio39", - "gpio40 ", "gpio41"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { - mux { - pins = "gpio38", "gpio39", - "gpio40 ", "gpio41"; - function = "gpio"; - }; - - config { - pins = "gpio38", "gpio39", - "gpio40 ", "gpio41"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - qupv3_se5_spi_pins: qupv3_se5_spi_pins { - qupv3_se5_spi_active: qupv3_se5_spi_active { - mux { - pins = "gpio25", "gpio26", - "gpio27", "gpio28"; - function = "qup05"; - }; - - config { - pins = "gpio25", "gpio26", - "gpio27", "gpio28"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { - mux { - pins = "gpio25", "gpio26", - "gpio27", "gpio28"; - function = "gpio"; - }; - - config { - pins = "gpio25", "gpio26", - "gpio27", "gpio28"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { - qupv3_se0_i2c_active: qupv3_se0_i2c_active { - mux { - pins = "gpio34", "gpio35"; - function = "qup00"; - }; - - config { - pins = "gpio34", "gpio35"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { - mux { - pins = "gpio34", "gpio35"; - function = "gpio"; - }; - - config { - pins = "gpio34", "gpio35"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { - qupv3_se1_i2c_active: qupv3_se1_i2c_active { - mux { - pins = "gpio0", "gpio1"; - function = "qup01"; - }; - - config { - pins = "gpio0", "gpio1"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { - mux { - pins = "gpio0", "gpio1"; - function = "gpio"; - }; - - config { - pins = "gpio0", "gpio1"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { - qupv3_se2_i2c_active: qupv3_se2_i2c_active { - mux { - pins = "gpio15", "gpio16"; - function = "qup02"; - }; - - config { - pins = "gpio15", "gpio16"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { - mux { - pins = "gpio15", "gpio16"; - function = "gpio"; - }; - - config { - pins = "gpio15", "gpio16"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { - qupv3_se3_i2c_active: qupv3_se3_i2c_active { - mux { - pins = "gpio38", "gpio39"; - function = "qup03"; - }; - - config { - pins = "gpio38", "gpio39"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { - mux { - pins = "gpio38", "gpio39"; - function = "gpio"; - }; - - config { - pins = "gpio38", "gpio39"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { - qupv3_se4_i2c_active: qupv3_se4_i2c_active { - mux { - pins = "gpio115", "gpio116"; - function = "qup04"; - }; - - config { - pins = "gpio115", "gpio116"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { - mux { - pins = "gpio115", "gpio116"; - function = "gpio"; - }; - - config { - pins = "gpio115", "gpio116"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { - qupv3_se5_i2c_active: qupv3_se5_i2c_active { - mux { - pins = "gpio25", "gpio26"; - function = "qup05"; - }; - - config { - pins = "gpio25", "gpio26"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { - mux { - pins = "gpio25", "gpio26"; - function = "gpio"; - }; - - config { - pins = "gpio25", "gpio26"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se3_4uart_pins: qupv3_se3_4uart_pins { - qupv3_se3_default_ctsrtsrx: - qupv3_se3_default_ctsrtsrx { - mux { - pins = "gpio38", "gpio39", - "gpio41"; - function = "gpio"; - }; - - config { - pins = "gpio38", "gpio39", - "gpio41"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - qupv3_se3_default_tx: qupv3_se3_default_tx { - mux { - pins = "gpio40"; - function = "gpio"; - }; - - config { - pins = "gpio40"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - qupv3_se3_ctsrx: qupv3_se3_ctsrx { - mux { - pins = "gpio38", "gpio41"; - function = "qup03"; - }; - - config { - pins = "gpio38", "gpio41"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se3_rts: qupv3_se3_rts { - mux { - pins = "gpio39"; - function = "qup03"; - }; - - config { - pins = "gpio39"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - qupv3_se3_tx: qupv3_se3_tx { - mux { - pins = "gpio40"; - function = "qup03"; - }; - - config { - pins = "gpio40"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se6_spi_pins: qupv3_se6_spi_pins { - qupv3_se6_spi_active: qupv3_se6_spi_active { - mux { - pins = "gpio59", "gpio60", - "gpio61", "gpio62"; - function = "qup10"; - }; - - config { - pins = "gpio59", "gpio60", - "gpio61", "gpio62"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { - mux { - pins = "gpio59", "gpio60", - "gpio61", "gpio62"; - function = "gpio"; - }; - - config { - pins = "gpio59", "gpio60", - "gpio61", "gpio62"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - qupv3_se8_spi_pins: qupv3_se8_spi_pins { - qupv3_se8_spi_active: qupv3_se8_spi_active { - mux { - pins = "gpio42", "gpio43", - "gpio44", "gpio45"; - function = "qup12"; - }; - - config { - pins = "gpio42", "gpio43", - "gpio44", "gpio45"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { - mux { - pins = "gpio42", "gpio43", - "gpio44", "gpio45"; - function = "gpio"; - }; - - config { - pins = "gpio42", "gpio43", - "gpio44", "gpio45"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - qupv3_se10_spi_pins: qupv3_se10_spi_pins { - qupv3_se10_spi_active: qupv3_se10_spi_active { - mux { - pins = "gpio86", "gpio87", - "gpio88 ", "gpio89"; - function = "qup14"; - }; - - config { - pins = "gpio86", "gpio87", - "gpio88 ", "gpio89"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { - mux { - pins = "gpio86", "gpio87", - "gpio88 ", "gpio89"; - function = "gpio"; - }; - - config { - pins = "gpio86", "gpio87", - "gpio88 ", "gpio89"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - qupv3_se11_spi_pins: qupv3_se11_spi_pins { - qupv3_se11_spi_active: qupv3_se11_spi_active { - mux { - pins = "gpio53", "gpio54", - "gpio55", "gpio56"; - function = "qup15"; - }; - - config { - pins = "gpio53", "gpio54", - "gpio55", "gpio56"; - drive-strength = <6>; - bias-disable; - }; - }; - - qupv3_se11_spi_sleep: qupv3_se11_spi_sleep { - mux { - pins = "gpio53", "gpio54", - "gpio55", "gpio56"; - function = "gpio"; - }; - - config { - pins = "gpio53", "gpio54", - "gpio55", "gpio56"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { - qupv3_se6_i2c_active: qupv3_se6_i2c_active { - mux { - pins = "gpio59", "gpio60"; - function = "qup10"; - }; - - config { - pins = "gpio59", "gpio60"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { - mux { - pins = "gpio59", "gpio60"; - function = "gpio"; - }; - - config { - pins = "gpio59", "gpio60"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { - qupv3_se7_i2c_active: qupv3_se7_i2c_active { - mux { - pins = "gpio6", "gpio7"; - function = "qup11"; - }; - - config { - pins = "gpio6", "gpio7"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { - mux { - pins = "gpio6", "gpio7"; - function = "gpio"; - }; - - config { - pins = "gpio6", "gpio7"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { - qupv3_se8_i2c_active: qupv3_se8_i2c_active { - mux { - pins = "gpio42", "gpio43"; - function = "qup12"; - }; - - config { - pins = "gpio42", "gpio43"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { - mux { - pins = "gpio42", "gpio43"; - function = "gpio"; - }; - - config { - pins = "gpio42", "gpio43"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { - qupv3_se9_i2c_active: qupv3_se9_i2c_active { - mux { - pins = "gpio46", "gpio47"; - function = "qup13"; - }; - - config { - pins = "gpio46", "gpio47"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { - mux { - pins = "gpio46", "gpio47"; - function = "gpio"; - }; - - config { - pins = "gpio46", "gpio47"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { - qupv3_se10_i2c_active: qupv3_se10_i2c_active { - mux { - pins = "gpio86", "gpio87"; - function = "qup14"; - }; - - config { - pins = "gpio86", "gpio87"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { - mux { - pins = "gpio86", "gpio87"; - function = "gpio"; - }; - - config { - pins = "gpio86", "gpio87"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - qupv3_se11_i2c_pins: qupv3_se11_i2c_pins { - qupv3_se11_i2c_active: qupv3_se11_i2c_active { - mux { - pins = "gpio53", "gpio54"; - function = "qup15"; - }; - - config { - pins = "gpio53", "gpio54"; - drive-strength = <2>; - bias-disable; - }; - }; - - qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep { - mux { - pins = "gpio53", "gpio54"; - function = "gpio"; - }; - - config { - pins = "gpio53", "gpio54"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - fsa_usbc_ana_en_n@33 { - fsa_usbc_ana_en: fsa_usbc_ana_en { - mux { - pins = "gpio33"; - function = "gpio"; - }; - - config { - pins = "gpio33"; - drive-strength = <2>; - bias-disable; - output-low; - }; - }; - }; - - /* WSA speaker reset pins */ - spkr_1_sd_n { - spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { - mux { - pins = "gpio51"; - function = "gpio"; - }; - - config { - pins = "gpio51"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; - input-enable; - }; - }; - - spkr_1_sd_n_active: spkr_1_sd_n_active { - mux { - pins = "gpio51"; - function = "gpio"; - }; - - config { - pins = "gpio51"; - drive-strength = <16>; /* 16 mA */ - bias-disable; - output-high; - }; - }; - }; - - spkr_2_sd_n { - spkr_2_sd_n_sleep: spkr_2_sd_n_sleep { - mux { - pins = "gpio52"; - function = "gpio"; - }; - - config { - pins = "gpio52"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; - input-enable; - }; - }; - - spkr_2_sd_n_active: spkr_2_sd_n_active { - mux { - pins = "gpio52"; - function = "gpio"; - }; - - config { - pins = "gpio52"; - drive-strength = <16>; /* 16 mA */ - bias-disable; - output-high; - }; - }; - }; - - wcd_reset_active: wcd_reset_active { - mux { - pins = "gpio58"; - function = "gpio"; - }; - - config { - pins = "gpio58"; - drive-strength = <16>; - output-high; - }; - }; - - wcd_reset_sleep: wcd_reset_sleep { - mux { - pins = "gpio58"; - function = "gpio"; - }; - - config { - pins = "gpio58"; - drive-strength = <16>; - bias-disable; - output-low; - }; - }; - qupv3_se8_2uart_pins: qupv3_se8_2uart_pins { qupv3_se8_2uart_active: qupv3_se8_2uart_active { mux { @@ -1012,445 +246,5 @@ }; }; - cci0_active: cci0_active { - mux { - /* CLK, DATA */ - pins = "gpio17", "gpio18"; - function = "cci_i2c"; - }; - - config { - pins = "gpio17", "gpio18"; - bias-pull-up; /* PULL UP*/ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cci0_suspend: cci0_suspend { - mux { - /* CLK, DATA */ - pins = "gpio17", "gpio18"; - function = "cci_i2c"; - }; - - config { - pins = "gpio17", "gpio18"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cci1_active: cci1_active { - mux { - /* CLK, DATA */ - pins = "gpio19", "gpio20"; - function = "cci_i2c"; - }; - - config { - pins = "gpio19", "gpio20"; - bias-pull-up; /* PULL UP*/ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cci1_suspend: cci1_suspend { - mux { - /* CLK, DATA */ - pins = "gpio19", "gpio20"; - function = "cci_i2c"; - }; - - config { - pins = "gpio19", "gpio20"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cci2_active: cci2_active { - mux { - /* CLK, DATA */ - pins = "gpio27", "gpio28"; - function = "cci_i2c"; - }; - - config { - pins = "gpio27", "gpio28"; - bias-pull-up; /* PULL UP*/ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cci2_suspend: cci2_suspend { - mux { - /* CLK, DATA */ - pins = "gpio27", "gpio28"; - function = "cci_i2c"; - }; - - config { - pins = "gpio27", "gpio28"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk0_active: cam_sensor_mclk0_active { - /* MCLK0 */ - mux { - pins = "gpio13"; - function = "cam_mclk"; - }; - - config { - pins = "gpio13"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { - /* MCLK0 */ - mux { - pins = "gpio13"; - function = "cam_mclk"; - }; - - config { - pins = "gpio13"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_rear_active: cam_sensor_rear_active { - /* RESET */ - mux { - pins = "gpio30"; - function = "gpio"; - }; - - config { - pins = "gpio30"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_rear_suspend: cam_sensor_rear_suspend { - /* RESET */ - mux { - pins = "gpio30"; - function = "gpio"; - }; - - config { - pins = "gpio30"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - output-low; - }; - }; - - cam_sensor_front_active: cam_sensor_front_active { - /* RESET */ - mux { - pins = "gpio29"; - function = "gpio"; - }; - - config { - pins = "gpio29"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_front_suspend: cam_sensor_front_suspend { - /* RESET */ - mux { - pins = "gpio29"; - function = "gpio"; - }; - - config { - pins = "gpio29"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - output-low; - }; - }; - - cam_sensor_rear2_active: cam_sensor_rear2_active { - /* RESET */ - mux { - pins = "gpio25"; - function = "gpio"; - }; - - config { - pins = "gpio25"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_rear2_suspend: cam_sensor_rear2_suspend { - /* RESET */ - mux { - pins = "gpioi25"; - function = "gpio"; - }; - - config { - pins = "gpio25"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - output-low; - }; - }; - - cam_sensor_tof_active: cam_sensor_tof_active { - /* RESET */ - mux { - pins = "gpio24"; - function = "gpio"; - }; - - config { - pins = "gpio24"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_tof_suspend: cam_sensor_tof_suspend { - /* RESET */ - mux { - pins = "gpio24"; - function = "gpio"; - }; - - config { - pins = "gpio24"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - output-low; - }; - }; - - cam_sensor_mclk1_active: cam_sensor_mclk1_active { - /* MCLK1 */ - mux { - pins = "gpio14"; - function = "cam_mclk"; - }; - - config { - pins = "gpio14"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { - /* MCLK1 */ - mux { - pins = "gpio14"; - function = "cam_mclk"; - }; - - config { - pins = "gpio14"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk2_active: cam_sensor_mclk2_active { - /* MCLK2 */ - mux { - pins = "gpio15"; - function = "cam_mclk"; - }; - - config { - pins = "gpio15"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { - /* MCLK2 */ - mux { - pins = "gpio15"; - function = "cam_mclk"; - }; - - config { - pins = "gpio15"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk3_active: cam_sensor_mclk3_active { - /* MCLK3 */ - mux { - pins = "gpio16"; - function = "cam_mclk"; - }; - - config { - pins = "gpio16"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { - /* MCLK3 */ - mux { - pins = "gpio16"; - function = "cam_mclk"; - }; - - config { - pins = "gpio16"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk4_active: cam_sensor_mclk4_active { - /* MCLK4 */ - mux { - pins = "gpio23"; - function = "cam_mclk"; - }; - - config { - pins = "gpio23"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk4_suspend: cam_sensor_mclk4_suspend { - /* MCLK4 */ - mux { - pins = "gpio23"; - function = "cam_mclk"; - }; - - config { - pins = "gpio23"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - pmx_sde_te { - sde_te_active: sde_te_active { - mux { - pins = "gpio10"; - function = "mdp_vsync"; - }; - - config { - pins = "gpio10"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - }; - }; - - sde_te_suspend: sde_te_suspend { - mux { - pins = "gpio10"; - function = "mdp_vsync"; - }; - - config { - pins = "gpio10"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - }; - }; - }; - - pmx_ts_active { - ts_active: ts_active { - mux { - pins = "gpio8", "gpio9"; - function = "gpio"; - }; - - config { - pins = "gpio8", "gpio9"; - drive-strength = <8>; - bias-pull-up; - }; - }; - }; - - pmx_ts_int_suspend { - ts_int_suspend: ts_int_suspend { - mux { - pins = "gpio9"; - function = "gpio"; - }; - - config { - pins = "gpio9"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - - pmx_ts_reset_suspend { - ts_reset_suspend: ts_reset_suspend { - mux { - pins = "gpio8"; - function = "gpio"; - }; - - config { - pins = "gpio8"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - - pmx_ts_release { - ts_release: ts_release { - mux { - pins = "gpio9", "gpio8"; - function = "gpio"; - }; - - config { - pins = "gpio9", "gpio8"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - }; -}; - -&pm6150l_gpios { - disp_pins { - disp_pins_default: disp_pins_default{ - pins = "gpio3"; - function = "func1"; - qcom,drive-strength = <2>; - power-source = <0>; - bias-disable; - output-low; - }; }; }; diff --git a/arch/arm64/boot/dts/qcom/atoll-qrd.dtsi b/arch/arm64/boot/dts/qcom/atoll-qrd.dtsi index b582b02da5a7..9132ac26e635 100644 --- a/arch/arm64/boot/dts/qcom/atoll-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-qrd.dtsi @@ -10,181 +10,5 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include - -#include "atoll-camera-sensor-qrd.dtsi" - &soc { - qrd_batterydata: qcom,battery-data { - qcom,batt-id-range-pct = <15>; - #include "qg-batterydata-atl466271_3300mAh.dtsi" - }; -}; - -&pm6150a_amoled { - status = "ok"; -}; - -&pm6150_qg { - qcom,battery-data = <&qrd_batterydata>; - qcom,qg-iterm-ma = <100>; - qcom,hold-soc-while-full; - qcom,linearize-soc; - qcom,cl-feedback-on; -}; - -&pm6150_charger { - io-channels = <&pm6150_vadc ADC_USB_IN_V_16>, - <&pm6150_vadc ADC_USB_IN_I>, - <&pm6150_vadc ADC_CHG_TEMP>, - <&pm6150_vadc ADC_DIE_TEMP>, - <&pm6150_vadc ADC_AMUX_THM3_PU2>, - <&pm6150_vadc ADC_SBUx>, - <&pm6150_vadc ADC_VPH_PWR>; - io-channel-names = "usb_in_voltage", - "usb_in_current", - "chg_temp", - "die_temp", - "conn_temp", - "sbux_res", - "vph_voltage"; - qcom,battery-data = <&qrd_batterydata>; - qcom,auto-recharge-soc = <98>; - qcom,step-charging-enable; - qcom,sw-jeita-enable; - qcom,fcc-stepping-enable; - qcom,suspend-input-on-debug-batt; - qcom,sec-charger-config = <3>; - qcom,thermal-mitigation = <4200000 3500000 3000000 - 2500000 2000000 1500000 1000000 500000>; - dpdm-supply = <&qusb_phy0>; - qcom,charger-temp-max = <800>; - qcom,smb-temp-max = <800>; -}; - -&pm6150l_gpios { - key_vol_up { - key_vol_up_default: key_vol_up_default { - pins = "gpio2"; - function = "normal"; - input-enable; - bias-pull-up; - power-source = <0>; - }; - }; -}; - -&soc { - gpio_keys { - compatible = "gpio-keys"; - label = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&key_vol_up_default>; - - vol_up { - label = "volume_up"; - gpios = <&pm6150l_gpios 2 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - linux,code = ; - linux,can-disable; - debounce-interval = <15>; - gpio-key,wakeup; - }; - - }; -}; - -&qupv3_se7_i2c { - status = "ok"; - - synaptics_tcm@20 { - compatible = "synaptics,tcm-i2c"; - reg = <0x20>; - interrupt-parent = <&tlmm>; - interrupts = <9 0x2008>; - pinctrl-names = "pmx_ts_active","pmx_ts_suspend", - "pmx_ts_release"; - pinctrl-0 = <&ts_active>; - pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; - pinctrl-2 = <&ts_release>; - vdd-supply = <&pm6150_l10>; - avdd-supply = <&pm6150l_l7>; - synaptics,pwr-reg-name = "avdd"; - synaptics,bus-reg-name = "vdd"; - synaptics,irq-gpio = <&tlmm 9 0x2008>; - synaptics,irq-on-state = <0>; - synaptics,reset-gpio = <&tlmm 8 0x00>; - synaptics,reset-on-state = <0>; - synaptics,reset-active-ms = <20>; - synaptics,reset-delay-ms = <200>; - synaptics,power-delay-ms = <200>; - synaptics,ubl-i2c-addr = <0x20>; - }; -}; - -&ufsphy_mem { - compatible = "qcom,ufs-phy-qmp-v3"; - - vdda-phy-supply = <&pm6150_l4>; /* 0.9v */ - vdda-pll-supply = <&pm6150l_l3>; /* 1.2v */ - vdda-phy-max-microamp = <62900>; - vdda-pll-max-microamp = <18300>; - - status = "ok"; -}; - -&ufshc_mem { - vdd-hba-supply = <&ufs_phy_gdsc>; - vdd-hba-fixed-regulator; - vcc-supply = <&pm6150_l19>; - vcc-voltage-level = <2950000 2960000>; - vcc-max-microamp = <600000>; - vccq2-supply = <&pm6150_l12>; - vccq2-voltage-level = <1750000 1950000>; - vccq2-max-microamp = <600000>; - - qcom,vddp-ref-clk-supply = <&pm6150l_l3>; /* PX10 */ - qcom,vddp-ref-clk-max-microamp = <100>; - - status = "ok"; -}; - -&sdhc_1 { - vdd-supply = <&pm6150_l19>; - qcom,vdd-voltage-level = <2950000 2950000>; - qcom,vdd-current-level = <0 570000>; - - vdd-io-supply = <&pm6150_l12>; - qcom,vdd-io-always-on; - qcom,vdd-io-lpm-sup; - qcom,vdd-io-voltage-level = <1800000 1800000>; - qcom,vdd-io-current-level = <0 325000>; - - pinctrl-names = "active", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; - - status = "ok"; -}; - -&sdhc_2 { - vdd-supply = <&pm6150l_l9>; - qcom,vdd-voltage-level = <2950000 2950000>; - qcom,vdd-current-level = <0 800000>; - - vdd-io-supply = <&pm6150l_l6>; - qcom,vdd-io-voltage-level = <1800000 2950000>; - qcom,vdd-io-current-level = <0 22000>; - - pinctrl-names = "active", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - - cd-gpios = <&tlmm 69 GPIO_ACTIVE_HIGH>; - - status = "ok"; }; diff --git a/arch/arm64/boot/dts/qcom/atoll-qupv3.dtsi b/arch/arm64/boot/dts/qcom/atoll-qupv3.dtsi index a5075a5bc40b..a79cdac7c492 100644 --- a/arch/arm64/boot/dts/qcom/atoll-qupv3.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-qupv3.dtsi @@ -13,298 +13,27 @@ #include &soc { - /* QUPv3 North Instances - * North 0 : SE 0 - * North 1 : SE 1 - * North 2 : SE 2 - * North 3 : SE 3 - * North 4 : SE 4 - * North 5 : SE 5 - */ - qupv3_0: qcom,qupv3_0_geni_se@8c0000 { + /* QUPv3 North instances */ + qupv3_0: qcom,qupv3_0_geni_se@0x8c0000 { compatible = "qcom,qupv3-geni-se"; reg = <0x8c0000 0x2000>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-bus-ids = - , - ; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; qcom,iommu-s1-bypass; iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb { compatible = "qcom,qupv3-geni-se-cb"; - iommus = <&apps_smmu 0x43 0x0>; + iommus = <&apps_smmu 0x043 0x0>; }; }; - /* GPI */ - gpi_dma0: qcom,gpi-dma@800000 { - #dma-cells = <5>; - compatible = "qcom,gpi-dma"; - reg = <0x800000 0x60000>; - reg-names = "gpi-top"; - interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>, - <0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>, - <0 252 0>, <0 253 0>; - qcom,max-num-gpii = <10>; - qcom,gpii-mask = <0x1f>; - qcom,ev-factor = <2>; - iommus = <&apps_smmu 0x56 0x0>; - qcom,smmu-cfg = <0x1>; - qcom,gpi-ee-offset = <0x10000>; - qcom,iova-range = <0x0 0x100000 0x0 0x100000>; - status = "ok"; - }; - - /* SPI */ - qupv3_se0_spi: spi@880000 { - compatible = "qcom,spi-geni"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x880000 0x4000>; - reg-names = "se_phys"; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se0_spi_active>; - pinctrl-1 = <&qupv3_se0_spi_sleep>; - interrupts = ; - spi-max-frequency = <50000000>; - qcom,wrapper-core = <&qupv3_0>; - dmas = <&gpi_dma0 0 0 1 64 0>, - <&gpi_dma0 1 0 1 64 0>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - qupv3_se1_spi: spi@884000 { - compatible = "qcom,spi-geni"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x884000 0x4000>; - reg-names = "se_phys"; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se1_spi_active>; - pinctrl-1 = <&qupv3_se1_spi_sleep>; - interrupts = ; - spi-max-frequency = <50000000>; - qcom,wrapper-core = <&qupv3_0>; - dmas = <&gpi_dma0 0 1 1 64 0>, - <&gpi_dma0 1 1 1 64 0>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - qupv3_se3_spi: spi@88c000 { - compatible = "qcom,spi-geni"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x88c000 0x4000>; - reg-names = "se_phys"; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se3_spi_active>; - pinctrl-1 = <&qupv3_se3_spi_sleep>; - interrupts = ; - spi-max-frequency = <50000000>; - qcom,wrapper-core = <&qupv3_0>; - dmas = <&gpi_dma0 0 3 1 64 0>, - <&gpi_dma0 1 3 1 64 0>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - qupv3_se5_spi: spi@894000 { - compatible = "qcom,spi-geni"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x894000 0x4000>; - reg-names = "se_phys"; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se5_spi_active>; - pinctrl-1 = <&qupv3_se5_spi_sleep>; - interrupts = ; - spi-max-frequency = <50000000>; - qcom,wrapper-core = <&qupv3_0>; - dmas = <&gpi_dma0 0 5 1 64 0>, - <&gpi_dma0 1 5 1 64 0>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - /* I2C */ - qupv3_se0_i2c: i2c@880000 { - compatible = "qcom,i2c-geni"; - reg = <0x880000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - dmas = <&gpi_dma0 0 0 3 64 0>, - <&gpi_dma0 1 0 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se0_i2c_active>; - pinctrl-1 = <&qupv3_se0_i2c_sleep>; - qcom,wrapper-core = <&qupv3_0>; - status = "disabled"; - }; - - qupv3_se1_i2c: i2c@884000 { - compatible = "qcom,i2c-geni"; - reg = <0x884000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - dmas = <&gpi_dma0 0 1 3 64 0>, - <&gpi_dma0 1 1 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se1_i2c_active>; - pinctrl-1 = <&qupv3_se1_i2c_sleep>; - qcom,wrapper-core = <&qupv3_0>; - status = "disabled"; - }; - - qupv3_se2_i2c: i2c@888000 { - compatible = "qcom,i2c-geni"; - reg = <0x888000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - dmas = <&gpi_dma0 0 2 3 64 0>, - <&gpi_dma0 1 2 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se2_i2c_active>; - pinctrl-1 = <&qupv3_se2_i2c_sleep>; - qcom,wrapper-core = <&qupv3_0>; - status = "disabled"; - }; - - qupv3_se3_i2c: i2c@88c000 { - compatible = "qcom,i2c-geni"; - reg = <0x88c000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - dmas = <&gpi_dma0 0 3 3 64 0>, - <&gpi_dma0 1 3 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se3_i2c_active>; - pinctrl-1 = <&qupv3_se3_i2c_sleep>; - qcom,wrapper-core = <&qupv3_0>; - status = "disabled"; - }; - - qupv3_se4_i2c: i2c@890000 { - compatible = "qcom,i2c-geni"; - reg = <0x890000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - dmas = <&gpi_dma0 0 4 3 64 0>, - <&gpi_dma0 1 4 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se4_i2c_active>; - pinctrl-1 = <&qupv3_se4_i2c_sleep>; - qcom,wrapper-core = <&qupv3_0>; - status = "disabled"; - }; - - qupv3_se5_i2c: i2c@894000 { - compatible = "qcom,i2c-geni"; - reg = <0x894000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - dmas = <&gpi_dma0 0 5 3 64 0>, - <&gpi_dma0 1 5 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se5_i2c_active>; - pinctrl-1 = <&qupv3_se5_i2c_sleep>; - qcom,wrapper-core = <&qupv3_0>; - status = "disabled"; - }; - - /* HSUART: BT used instance */ - qupv3_se3_4uart: qcom,qup_uart@88c000 { - compatible = "qcom,msm-geni-serial-hs"; - reg = <0x88c000 0x4000>; - reg-names = "se_phys"; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - pinctrl-names = "default", "active", "sleep"; - pinctrl-0 = <&qupv3_se3_default_ctsrtsrx>, - <&qupv3_se3_default_tx>; - pinctrl-1 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>, - <&qupv3_se3_tx>; - pinctrl-2 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>, - <&qupv3_se3_tx>; - interrupts-extended = <&intc GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, - <&tlmm 41 IRQ_TYPE_LEVEL_HIGH>; - qcom,wrapper-core = <&qupv3_0>; - qcom,wakeup-byte = <0xFD>; - status = "disabled"; - }; - - /* QUPv3 South Instances - * South 0 : SE 6 - * South 1 : SE 7 - * South 2 : SE 8 - * South 3 : SE 9 - * South 4 : SE 10 - * South 5 : SE 11 - */ - - qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + /* QUPv3 South Instances */ + qupv3_1: qcom,qupv3_1_geni_se@0xac0000 { compatible = "qcom,qupv3-geni-se"; reg = <0xac0000 0x2000>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-bus-ids = - , - ; + qcom,bus-mas-id = ; + qcom,bus-slv-id = ; qcom,iommu-s1-bypass; iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb { @@ -313,236 +42,8 @@ }; }; - /* GPI */ - gpi_dma1: qcom,gpi-dma@a00000 { - #dma-cells = <5>; - compatible = "qcom,gpi-dma"; - reg = <0xa00000 0x60000>; - reg-names = "gpi-top"; - interrupts = <0 646 0>, <0 647 0>, <0 648 0>, <0 649 0>, - <0 650 0>, <0 651 0>, <0 652 0>, <0 653 0>, - <0 654 0>, <0 655 0>; - qcom,max-num-gpii = <10>; - qcom,gpii-mask = <0x3f>; - qcom,ev-factor = <2>; - iommus = <&apps_smmu 0x4d6 0x0>; - qcom,smmu-cfg = <0x1>; - qcom,gpi-ee-offset = <0x10000>; - qcom,iova-range = <0x0 0x100000 0x0 0x100000>; - status = "ok"; - }; - - /* SPI */ - qupv3_se6_spi: spi@a80000 { - compatible = "qcom,spi-geni"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xa80000 0x4000>; - reg-names = "se_phys"; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se6_spi_active>; - pinctrl-1 = <&qupv3_se6_spi_sleep>; - interrupts = ; - spi-max-frequency = <50000000>; - qcom,wrapper-core = <&qupv3_1>; - dmas = <&gpi_dma1 0 0 1 64 0>, - <&gpi_dma1 1 0 1 64 0>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - qupv3_se8_spi: spi@a88000 { - compatible = "qcom,spi-geni"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xa88000 0x4000>; - reg-names = "se_phys"; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se8_spi_active>; - pinctrl-1 = <&qupv3_se8_spi_sleep>; - interrupts = ; - spi-max-frequency = <50000000>; - qcom,wrapper-core = <&qupv3_1>; - dmas = <&gpi_dma1 0 2 1 64 0>, - <&gpi_dma1 1 2 1 64 0>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - qupv3_se10_spi: spi@a90000 { - compatible = "qcom,spi-geni"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xa90000 0x4000>; - reg-names = "se_phys"; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se10_spi_active>; - pinctrl-1 = <&qupv3_se10_spi_sleep>; - interrupts = ; - spi-max-frequency = <50000000>; - qcom,wrapper-core = <&qupv3_1>; - dmas = <&gpi_dma1 0 4 1 64 0>, - <&gpi_dma1 1 4 1 64 0>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - qupv3_se11_spi: spi@a94000 { - compatible = "qcom,spi-geni"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xa94000 0x4000>; - reg-names = "se_phys"; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se11_spi_active>; - pinctrl-1 = <&qupv3_se11_spi_sleep>; - interrupts = ; - spi-max-frequency = <50000000>; - qcom,wrapper-core = <&qupv3_1>; - dmas = <&gpi_dma1 0 5 1 64 0>, - <&gpi_dma1 1 5 1 64 0>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - /* I2C */ - qupv3_se6_i2c: i2c@a80000 { - compatible = "qcom,i2c-geni"; - reg = <0xa80000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - dmas = <&gpi_dma1 0 0 3 64 0>, - <&gpi_dma1 1 0 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se6_i2c_active>; - pinctrl-1 = <&qupv3_se6_i2c_sleep>; - qcom,wrapper-core = <&qupv3_1>; - status = "disabled"; - }; - - qupv3_se7_i2c: i2c@a84000 { - compatible = "qcom,i2c-geni"; - reg = <0xa84000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - dmas = <&gpi_dma1 0 1 3 64 0>, - <&gpi_dma1 1 1 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se7_i2c_active>; - pinctrl-1 = <&qupv3_se7_i2c_sleep>; - qcom,wrapper-core = <&qupv3_1>; - status = "disabled"; - }; - - qupv3_se8_i2c: i2c@a88000 { - compatible = "qcom,i2c-geni"; - reg = <0xa88000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - dmas = <&gpi_dma1 0 2 3 64 0>, - <&gpi_dma1 1 2 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se8_i2c_active>; - pinctrl-1 = <&qupv3_se8_i2c_sleep>; - qcom,wrapper-core = <&qupv3_1>; - status = "disabled"; - }; - - qupv3_se9_i2c: i2c@a8c000 { - compatible = "qcom,i2c-geni"; - reg = <0xa8c000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - dmas = <&gpi_dma1 0 3 3 64 0>, - <&gpi_dma1 1 3 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se9_i2c_active>; - pinctrl-1 = <&qupv3_se9_i2c_sleep>; - qcom,wrapper-core = <&qupv3_1>; - status = "disabled"; - }; - - qupv3_se10_i2c: i2c@a90000 { - compatible = "qcom,i2c-geni"; - reg = <0xa90000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - dmas = <&gpi_dma1 0 4 3 64 0>, - <&gpi_dma1 1 4 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se10_i2c_active>; - pinctrl-1 = <&qupv3_se10_i2c_sleep>; - qcom,wrapper-core = <&qupv3_1>; - status = "disabled"; - }; - - qupv3_se11_i2c: i2c@a94000 { - compatible = "qcom,i2c-geni"; - reg = <0xa94000 0x4000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "se-clk", "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - dmas = <&gpi_dma1 0 5 3 64 0>, - <&gpi_dma1 1 5 3 64 0>; - dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qupv3_se11_i2c_active>; - pinctrl-1 = <&qupv3_se11_i2c_sleep>; - qcom,wrapper-core = <&qupv3_1>; - status = "disabled"; - }; - - qupv3_se8_2uart: qcom,qup_uart@a88000 { + /* Debug UART Instance for CDP/MTP/RUMI platform: QUPV3_1_SE2 */ + qupv3_se8_2uart: qcom,qup_uart@0xa88000 { compatible = "qcom,msm-geni-console"; reg = <0xa88000 0x4000>; reg-names = "se_phys"; @@ -553,9 +54,9 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se8_2uart_active>; pinctrl-1 = <&qupv3_se8_2uart_sleep>; - interrupts = ; + interrupts = ; qcom,wrapper-core = <&qupv3_1>; status = "disabled"; }; - }; + diff --git a/arch/arm64/boot/dts/qcom/atoll-rumi.dtsi b/arch/arm64/boot/dts/qcom/atoll-rumi.dtsi index 4ac010263b72..1d0c58235836 100644 --- a/arch/arm64/boot/dts/qcom/atoll-rumi.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-rumi.dtsi @@ -53,6 +53,8 @@ }; }; +#include "atoll-stub-regulator.dtsi" + &sdhc_1 { vdd-supply = <&pm6150_l19>; qcom,vdd-voltage-level = <2950000 2950000>; @@ -134,32 +136,9 @@ status = "ok"; }; -&thermal_zones { - /delete-node/ aoss-0-lowf; -}; - &usb0 { dwc3@a600000 { usb-phy = <&usb_emu_phy>, <&usb_nop_phy>; maximum-speed = "high-speed"; }; - qcom,usbbam@a704000 { - status = "disabled"; - }; -}; - -&qusb_phy0 { - status = "disabled"; -}; - -&usb_qmp_dp_phy { - status = "disabled"; -}; - -&pm6150_pdphy { - status = "disabled"; -}; - -&qupv3_se9_i2c { - status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/atoll-sde-display.dtsi b/arch/arm64/boot/dts/qcom/atoll-sde-display.dtsi deleted file mode 100644 index ee2bb89b1de9..000000000000 --- a/arch/arm64/boot/dts/qcom/atoll-sde-display.dtsi +++ /dev/null @@ -1,152 +0,0 @@ -/* Copyright (c) 2019, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "dsi-panel-rm69299-visionox-amoled-fhd-plus-video.dtsi" -#include - -&soc { - dsi_panel_pwr_supply: dsi_panel_pwr_supply { - #address-cells = <1>; - #size-cells = <0>; - - qcom,panel-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1904000>; - qcom,supply-enable-load = <32000>; - qcom,supply-disable-load = <80>; - }; - - qcom,panel-supply-entry@1 { - reg = <1>; - qcom,supply-name = "lab"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <100000>; - qcom,supply-disable-load = <100>; - }; - - qcom,panel-supply-entry@2 { - reg = <2>; - qcom,supply-name = "ibb"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <100000>; - qcom,supply-disable-load = <100>; - qcom,supply-post-on-sleep = <20>; - }; - }; - - dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { - #address-cells = <1>; - #size-cells = <0>; - - qcom,panel-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1904000>; - qcom,supply-enable-load = <32000>; - qcom,supply-disable-load = <80>; - }; - }; - - dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled { - #address-cells = <1>; - #size-cells = <0>; - - qcom,panel-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1904000>; - qcom,supply-enable-load = <32000>; - qcom,supply-disable-load = <80>; - }; - - qcom,panel-supply-entry@1 { - reg = <1>; - qcom,supply-name = "vdda-3p3"; - qcom,supply-min-voltage = <3000000>; - qcom,supply-max-voltage = <3000000>; - qcom,supply-enable-load = <13200>; - qcom,supply-disable-load = <80>; - }; - }; - - dsi_rm69299_visionox_amoled_vid_display: qcom,dsi-display@0 { - label = "dsi_rm69299_visionox_amoled_vid_display"; - qcom,display-type = "primary"; - - qcom,dsi-ctrl-num = <0>; - qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - - qcom,dsi-panel = <&dsi_rm69299_visionox_amoled_video>; - }; - - sde_dsi: qcom,dsi-display { - compatible = "qcom,dsi-display"; - - qcom,dsi-ctrl = <&mdss_dsi0>; - qcom,dsi-phy = <&mdss_dsi_phy0>; - - clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, - <&mdss_dsi0_pll PCLK_MUX_0_CLK>, - <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>, - <&mdss_dsi0_pll PCLK_SRC_0_CLK>, - <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>, - <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>; - clock-names = "mux_byte_clk0", "mux_pixel_clk0", - "src_byte_clk0", "src_pixel_clk0", - "shadow_byte_clk0", "shadow_pixel_clk0"; - - pinctrl-names = "panel_active", "panel_suspend"; - pinctrl-0 = <&sde_te_active &disp_pins_default>; - pinctrl-1 = <&sde_te_suspend>; - - qcom,platform-te-gpio = <&tlmm 10 0>; - qcom,platform-reset-gpio = <&pm6150l_gpios 3 0>; - qcom,panel-te-source = <0>; - - vddio-supply = <&L13A>; - vdda-3p3-supply = <&L18A>; - lab-supply = <&lcdb_ldo_vreg>; - ibb-supply = <&lcdb_ncp_vreg>; - - qcom,dsi-display-list = - <&dsi_rm69299_visionox_amoled_vid_display>; - }; - - sde_wb: qcom,wb-display@0 { - compatible = "qcom,wb-display"; - cell-index = <0>; - label = "wb_display"; - }; -}; - -&mdss_mdp { - connectors = <&sde_wb &sde_dsi>; -}; - -&dsi_rm69299_visionox_amoled_video { - qcom,mdss-dsi-t-clk-post = <0x0E>; - qcom,mdss-dsi-t-clk-pre = <0x31>; - qcom,mdss-dsi-display-timings { - timing@0{ - qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 - 08 05 02 04 00]; - qcom,display-topology = <1 0 1>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/atoll-thermal.dtsi b/arch/arm64/boot/dts/qcom/atoll-thermal.dtsi index fdd8d09839fb..3397ad51b4b2 100644 --- a/arch/arm64/boot/dts/qcom/atoll-thermal.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-thermal.dtsi @@ -13,81 +13,6 @@ #include -&clock_cpucc { - #address-cells = <1>; - #size-cells = <1>; - lmh_dcvs0: qcom,limits-dcvs@18358800 { - compatible = "qcom,msm-hw-limits"; - interrupts = ; - qcom,affinity = <0>; - reg = <0x18358800 0x1000>, - <0x18323000 0x1000>; - #thermal-sensor-cells = <0>; - }; - - lmh_dcvs1: qcom,limits-dcvs@18350800 { - compatible = "qcom,msm-hw-limits"; - interrupts = ; - qcom,affinity = <1>; - reg = <0x18350800 0x1000>, - <0x18325800 0x1000>; - #thermal-sensor-cells = <0>; - }; -}; - -&soc { - qmi-tmd-devices { - compatible = "qcom,qmi-cooling-devices"; - - modem { - qcom,instance-id = <0x0>; - - modem_pa: modem_pa { - qcom,qmi-dev-name = "pa"; - #cooling-cells = <2>; - }; - - modem_proc: modem_proc { - qcom,qmi-dev-name = "modem"; - #cooling-cells = <2>; - }; - - modem_current: modem_current { - qcom,qmi-dev-name = "modem_current"; - #cooling-cells = <2>; - }; - - modem_skin: modem_skin { - qcom,qmi-dev-name = "modem_skin"; - #cooling-cells = <2>; - }; - - modem_vdd: modem_vdd { - qcom,qmi-dev-name = "cpuv_restriction_cold"; - #cooling-cells = <2>; - }; - }; - - adsp { - qcom,instance-id = <0x1>; - - adsp_vdd: adsp_vdd { - qcom,qmi-dev-name = "cpuv_restriction_cold"; - #cooling-cells = <2>; - }; - }; - - cdsp { - qcom,instance-id = <0x43>; - - cdsp_vdd: cdsp_vdd { - qcom,qmi-dev-name = "cpuv_restriction_cold"; - #cooling-cells = <2>; - }; - }; - }; -}; - &thermal_zones { aoss-0-usr { polling-delay-passive = <0>; @@ -693,335 +618,4 @@ }; }; }; - - gpuss-max-step { - polling-delay-passive = <10>; - polling-delay = <100>; - thermal-governor = "step_wise"; - wake-capable-sensor; - trips { - gpu_trip: gpu-trip { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - }; - - cooling-maps { - gpu_cdev { - trip = <&gpu_trip>; - cooling-device = <&msm_gpu THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu-0-max-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - wake-capable-sensor; - trips { - silver-trip { - temperature = <120000>; - hysteresis = <0>; - type = "passive"; - }; - }; - }; - - cpu-1-max-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - wake-capable-sensor; - trips { - gold-trip { - temperature = <120000>; - hysteresis = <0>; - type = "passive"; - }; - }; - }; - - cpu-0-0-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 1>; - wake-capable-sensor; - trips { - cpu0_config: cpu0-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - cpu0_cdev { - trip = <&cpu0_config>; - cooling-device = - <&CPU0 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - cpu-0-1-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 2>; - wake-capable-sensor; - trips { - cpu1_config: cpu1-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - cpu1_cdev { - trip = <&cpu1_config>; - cooling-device = - <&CPU1 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - cpu-0-2-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 3>; - wake-capable-sensor; - trips { - cpu2_config: cpu2-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - cpu2_cdev { - trip = <&cpu2_config>; - cooling-device = - <&CPU2 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - cpu-0-3-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 4>; - wake-capable-sensor; - trips { - cpu3_config: cpu3-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - cpu3_cdev { - trip = <&cpu3_config>; - cooling-device = - <&CPU3 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - cpu-0-4-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 5>; - wake-capable-sensor; - trips { - cpu4_config: cpu4-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - cpu4_cdev { - trip = <&cpu4_config>; - cooling-device = - <&CPU4 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - cpu-0-5-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 6>; - wake-capable-sensor; - trips { - cpu5_config: cpu5-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - cpu5_cdev { - trip = <&cpu5_config>; - cooling-device = - <&CPU5 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - cpu-1-0-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 9>; - wake-capable-sensor; - trips { - cpu6_0_config: cpu6-0-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - cpu6_cdev { - trip = <&cpu6_0_config>; - cooling-device = - <&CPU6 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - cpu-1-1-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 10>; - wake-capable-sensor; - trips { - cpu6_1_config: cpu6-1-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - cpu6_cdev { - trip = <&cpu6_1_config>; - cooling-device = - <&CPU6 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - cpu-1-2-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 11>; - wake-capable-sensor; - trips { - cpu7_0_config: cpu7-0-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - cpu7_cdev { - trip = <&cpu7_0_config>; - cooling-device = - <&CPU7 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - cpu-1-3-step { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&tsens0 12>; - wake-capable-sensor; - trips { - cpu7_1_config: cpu7-1-config { - temperature = <110000>; - hysteresis = <10000>; - type = "passive"; - }; - }; - cooling-maps { - cpu7_cdev { - trip = <&cpu7_1_config>; - cooling-device = - <&CPU7 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - aoss-0-lowf { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "low_limits_floor"; - thermal-sensors = <&tsens0 0>; - wake-capable-sensor; - tracks-low; - trips { - aoss0_trip: aoss0-trip { - temperature = <5000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - cooling-maps { - cpu0_cdev { - trip = <&aoss0_trip>; - cooling-device = <&CPU0 2 2>; - }; - cpu1_cdev { - trip = <&aoss0_trip>; - cooling-device = <&CPU6 4 4>; - }; - gpu_vdd_cdev { - trip = <&aoss0_trip>; - cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) - (THERMAL_MAX_LIMIT-3)>; - }; - cx_vdd_cdev { - trip = <&aoss0_trip>; - cooling-device = <&cx_cdev 0 0>; - }; - mx_vdd_cdev { - trip = <&aoss0_trip>; - cooling-device = <&mx_cdev 0 0>; - }; - modem_vdd_cdev { - trip = <&aoss0_trip>; - cooling-device = <&modem_vdd 0 0>; - }; - adsp_vdd_cdev { - trip = <&aoss0_trip>; - cooling-device = <&adsp_vdd 0 0>; - }; - cdsp_vdd_cdev { - trip = <&aoss0_trip>; - cooling-device = <&cdsp_vdd 0 0>; - }; - }; - }; }; diff --git a/arch/arm64/boot/dts/qcom/atoll-usb.dtsi b/arch/arm64/boot/dts/qcom/atoll-usb.dtsi index 1552d109b652..90b79a03bf55 100644 --- a/arch/arm64/boot/dts/qcom/atoll-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-usb.dtsi @@ -54,8 +54,8 @@ 0x130 /* GSI_RING_BASE_ADDR_L */ 0x144 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ - qcom,gsi-disable-io-coherency; qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + qcom,pm-qos-latency = <62>; qcom,msm-bus,name = "usb0"; qcom,msm-bus,num-cases = <4>; @@ -136,7 +136,7 @@ qusb_phy0: qusb@88e2000 { compatible = "qcom,qusb2phy-v2"; reg = <0x088e2000 0x400>, - <0x00780258 0x4>, + <0x00780200 0x4>, <0x088e7014 0x4>; reg-names = "qusb_phy_base", "efuse_addr", "refgen_north_bg_reg_addr"; @@ -365,7 +365,7 @@ usb_audio_qmi_dev { compatible = "qcom,usb-audio-qmi-dev"; - iommus = <&apps_smmu 0x100f 0x0>; + iommus = <&apps_smmu 0x1b2f 0x0>; qcom,usb-audio-stream-id = <0xf>; qcom,usb-audio-intr-num = <2>; }; diff --git a/arch/arm64/boot/dts/qcom/atoll-vidc.dtsi b/arch/arm64/boot/dts/qcom/atoll-vidc.dtsi index ec3b77ba77f2..24e21d0080ca 100644 --- a/arch/arm64/boot/dts/qcom/atoll-vidc.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-vidc.dtsi @@ -16,7 +16,7 @@ &soc { msm_vidc: qcom,vidc@aa00000 { - compatible = "qcom,msm-vidc", "qcom,atoll-vidc"; + compatible = "qcom,msm-vidc", "qcom,atoll"; status = "ok"; reg = <0xaa00000 0x200000>; interrupts = ; diff --git a/arch/arm64/boot/dts/qcom/atoll-wcd937x-idp-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/atoll-wcd937x-idp-audio-overlay.dtsi deleted file mode 100644 index addfd52ea758..000000000000 --- a/arch/arm64/boot/dts/qcom/atoll-wcd937x-idp-audio-overlay.dtsi +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "atoll-audio-overlay.dtsi" - -&wcd937x_codec { - status = "ok"; -}; - -&wcd938x_codec { - status = "disabled"; -}; - -&wcd937x_rx_slave { - status = "ok"; -}; - -&wcd937x_tx_slave { - status = "ok"; -}; - -&wcd938x_rx_slave { - status = "disabled"; -}; - -&wcd938x_tx_slave { - status = "disabled"; -}; - - -&atoll_snd { - qcom,model = "atoll-wcd937x-snd-card"; - qcom,audio-routing = - "AMIC1", "MIC BIAS1", - "MIC BIAS1", "Analog Mic1", - "AMIC2", "MIC BIAS2", - "MIC BIAS2", "Analog Mic2", - "AMIC3", "MIC BIAS3", - "MIC BIAS3", "Analog Mic3", - "TX DMIC0", "MIC BIAS1", - "MIC BIAS1", "Digital Mic0", - "TX DMIC1", "MIC BIAS1", - "MIC BIAS1", "Digital Mic1", - "TX DMIC2", "MIC BIAS3", - "MIC BIAS3", "Digital Mic2", - "TX DMIC3", "MIC BIAS3", - "MIC BIAS3", "Digital Mic3", - "IN1_HPHL", "HPHL_OUT", - "IN2_HPHR", "HPHR_OUT", - "IN3_AUX", "AUX_OUT", - "TX SWR_ADC0", "ADC1_OUTPUT", - "TX SWR_ADC2", "ADC2_OUTPUT", - "TX SWR_DMIC0", "DMIC1_OUTPUT", - "TX SWR_DMIC1", "DMIC2_OUTPUT", - "TX SWR_DMIC2", "DMIC3_OUTPUT", - "TX SWR_DMIC3", "DMIC4_OUTPUT", - "TX SWR_DMIC4", "DMIC5_OUTPUT", - "TX SWR_DMIC5", "DMIC6_OUTPUT", - "TX SWR_DMIC6", "DMIC7_OUTPUT", - "TX SWR_DMIC7", "DMIC8_OUTPUT", - "WSA SRC0_INP", "SRC0", - "WSA_TX DEC0_INP", "TX DEC0 MUX", - "WSA_TX DEC1_INP", "TX DEC1 MUX", - "RX_TX DEC0_INP", "TX DEC0 MUX", - "RX_TX DEC1_INP", "TX DEC1 MUX", - "RX_TX DEC2_INP", "TX DEC2 MUX", - "RX_TX DEC3_INP", "TX DEC3 MUX", - "SpkrLeft IN", "WSA_SPK1 OUT", - "SpkrRight IN", "WSA_SPK2 OUT", - "VA MIC BIAS3", "Digital Mic0", - "VA MIC BIAS3", "Digital Mic1", - "VA MIC BIAS1", "Digital Mic2", - "VA MIC BIAS1", "Digital Mic3", - "VA MIC BIAS4", "Digital Mic4", - "VA MIC BIAS4", "Digital Mic5", - "VA DMIC0", "VA MIC BIAS3", - "VA DMIC1", "VA MIC BIAS3", - "VA DMIC2", "VA MIC BIAS1", - "VA DMIC3", "VA MIC BIAS1", - "VA DMIC4", "VA MIC BIAS4", - "VA DMIC5", "VA MIC BIAS4", - "VA SWR_ADC0", "VA_SWR_CLK", - "VA SWR_ADC1", "VA_SWR_CLK", - "VA SWR_ADC2", "VA_SWR_CLK", - "VA SWR_ADC3", "VA_SWR_CLK", - "VA SWR_MIC0", "VA_SWR_CLK", - "VA SWR_MIC1", "VA_SWR_CLK", - "VA SWR_MIC2", "VA_SWR_CLK", - "VA SWR_MIC3", "VA_SWR_CLK", - "VA SWR_MIC4", "VA_SWR_CLK", - "VA SWR_MIC5", "VA_SWR_CLK", - "VA SWR_MIC6", "VA_SWR_CLK", - "VA SWR_MIC7", "VA_SWR_CLK", - "VA SWR_ADC0", "ADC1_OUTPUT", - "VA SWR_ADC1", "ADC2_OUTPUT", - "VA SWR_ADC2", "ADC3_OUTPUT", - "VA SWR_ADC3", "ADC4_OUTPUT", - "VA SWR_MIC0", "DMIC1_OUTPUT", - "VA SWR_MIC1", "DMIC2_OUTPUT", - "VA SWR_MIC2", "DMIC3_OUTPUT", - "VA SWR_MIC3", "DMIC4_OUTPUT", - "VA SWR_MIC4", "DMIC5_OUTPUT", - "VA SWR_MIC5", "DMIC6_OUTPUT", - "VA SWR_MIC6", "DMIC7_OUTPUT", - "VA SWR_MIC7", "DMIC8_OUTPUT"; - qcom,codec-aux-devs = <&wcd937x_codec>; -}; - diff --git a/arch/arm64/boot/dts/qcom/atoll.dtsi b/arch/arm64/boot/dts/qcom/atoll.dtsi index f570ca76490d..ef8f9ebafa09 100644 --- a/arch/arm64/boot/dts/qcom/atoll.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll.dtsi @@ -13,22 +13,16 @@ #include "skeleton64.dtsi" #include #include -#include #include #include -#include +#include #include #include -#include #include -#include #include #include -#include #include -#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) -#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 ;} / { model = "Qualcomm Technologies, Inc. ATOLL"; compatible = "qcom,atoll"; @@ -57,8 +51,6 @@ d-cache-size = <0x8000>; i-cache-size = <0x8000>; next-level-cache = <&L2_0>; - qcom,lmh-dcvs = <&lmh_dcvs0>; - #cooling-cells = <2>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -74,7 +66,7 @@ L1_I_0: l1-icache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x8800>; }; L1_D_0: l1-dcache { @@ -83,7 +75,7 @@ }; L2_TLB_0: l2-tlb { - qcom,dump-size = <0x5a00>; + qcom,dump-size = <0x5000>; }; }; @@ -97,8 +89,6 @@ d-cache-size = <0x8000>; i-cache-size = <0x8000>; next-level-cache = <&L2_100>; - qcom,lmh-dcvs = <&lmh_dcvs0>; - #cooling-cells = <2>; L2_100: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -108,7 +98,7 @@ L1_I_100: l1-icache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x8800>; }; L1_D_100: l1-dcache { @@ -117,7 +107,7 @@ }; L2_TLB_100: l2-tlb { - qcom,dump-size = <0x5a00>; + qcom,dump-size = <0x5000>; }; }; @@ -132,8 +122,6 @@ d-cache-size = <0x8000>; i-cache-size = <0x8000>; next-level-cache = <&L2_200>; - qcom,lmh-dcvs = <&lmh_dcvs0>; - #cooling-cells = <2>; L2_200: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -143,7 +131,7 @@ L1_I_200: l1-icache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x8800>; }; L1_D_200: l1-dcache { @@ -152,7 +140,7 @@ }; L2_TLB_200: l2-tlb { - qcom,dump-size = <0x5a00>; + qcom,dump-size = <0x5000>; }; }; @@ -166,8 +154,6 @@ d-cache-size = <0x8000>; i-cache-size = <0x8000>; next-level-cache = <&L2_300>; - qcom,lmh-dcvs = <&lmh_dcvs0>; - #cooling-cells = <2>; L2_300: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -177,7 +163,7 @@ L1_I_300: l1-icache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x8800>; }; L1_D_300: l1-dcache { @@ -186,7 +172,7 @@ }; L2_TLB_300: l2-tlb { - qcom,dump-size = <0x5a00>; + qcom,dump-size = <0x5000>; }; }; @@ -200,8 +186,6 @@ d-cache-size = <0x8000>; i-cache-size = <0x8000>; next-level-cache = <&L2_400>; - qcom,lmh-dcvs = <&lmh_dcvs0>; - #cooling-cells = <2>; L2_400: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -211,7 +195,7 @@ L1_I_400: l1-icache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x8800>; }; L1_D_400: l1-dcache { @@ -220,7 +204,7 @@ }; L2_TLB_400: l2-tlb { - qcom,dump-size = <0x5a00>; + qcom,dump-size = <0x5000>; }; }; @@ -234,8 +218,6 @@ d-cache-size = <0x8000>; i-cache-size = <0x8000>; next-level-cache = <&L2_500>; - qcom,lmh-dcvs = <&lmh_dcvs0>; - #cooling-cells = <2>; L2_500: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x10000>; @@ -245,7 +227,7 @@ L1_I_500: l1-icache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x10800>; + qcom,dump-size = <0x8800>; }; L1_D_500: l1-dcache { @@ -254,7 +236,7 @@ }; L2_TLB_500: l2-tlb { - qcom,dump-size = <0x5a00>; + qcom,dump-size = <0x5000>; }; }; @@ -268,8 +250,6 @@ d-cache-size = <0x10000>; i-cache-size = <0x10000>; next-level-cache = <&L2_600>; - qcom,lmh-dcvs = <&lmh_dcvs1>; - #cooling-cells = <2>; L2_600: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x40000>; @@ -280,7 +260,7 @@ L1_I_600: l1-icache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x22000>; + qcom,dump-size = <0x11000>; }; L1_D_600: l1-dcache { @@ -311,8 +291,6 @@ d-cache-size = <0x10000>; i-cache-size = <0x10000>; next-level-cache = <&L2_700>; - qcom,lmh-dcvs = <&lmh_dcvs1>; - #cooling-cells = <2>; L2_700: l2-cache { compatible = "arm,arch-cache"; cache-size = <0x40000>; @@ -323,7 +301,7 @@ L1_I_700: l1-icache { compatible = "arm,arch-cache"; - qcom,dump-size = <0x22000>; + qcom,dump-size = <0x11000>; }; L1_D_700: l1-dcache { @@ -532,61 +510,61 @@ pil_camera_mem: camera_region@8e000000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x8e400000 0 0x500000>; + reg = <0 0x8e000000 0 0x500000>; }; pil_modem_mem: modem_region@86000000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x86000000 0 0x8400000>; + reg = <0 0x86000000 0 0x8000000>; }; pil_video_mem: pil_video_region@8ea00000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x8ee00000 0 0x500000>; + reg = <0 0x8ea00000 0 0x500000>; }; pil_cdsp_mem: cdsp_regions@8ef00000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x8f300000 0 0x1e00000>; + reg = <0 0x8ef00000 0 0x1e00000>; }; pil_adsp_mem: pil_adsp_region@90d00000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x91100000 0 0x2800000>; + reg = <0 0x90d00000 0 0x2800000>; }; wlan_fw_mem: wlan_fw_region@93500000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x93900000 0 0x200000>; + reg = <0 0x93500000 0 0x200000>; }; npu_mem: npu_region@8e500000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x8e900000 0 0x500000>; + reg = <0 0x8e500000 0 0x500000>; }; pil_ipa_fw_mem: ipa_fw_region@93700000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x93b00000 0 0x10000>; + reg = <0 0x93700000 0 0x10000>; }; pil_ipa_gsi_mem: ipa_gsi_region@93710000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x93b10000 0 0x5000>; + reg = <0 0x93710000 0 0x5000>; }; pil_gpu_mem: gpu_region@93715000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x93b15000 0 0x2000>; + reg = <0 0x93715000 0 0x2000>; }; qseecom_mem: qseecom_region@9e000000 { @@ -595,18 +573,10 @@ reg = <0 0x9e000000 0 0x1400000>; }; - qseecom_ta_mem: qseecom_ta_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0 0x00000000 0 0xffffffff>; - reusable; - alignment = <0 0x400000>; - size = <0 0x1000000>; - }; - cdsp_sec_mem: cdsp_sec_regions@0x9f400000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x9f400000 0 0x1e00000>; + reg = <0 0x9f400000 0 0xc00000>; }; secure_display_memory: secure_display_region { @@ -897,161 +867,17 @@ reg-names = "pshold-base", "tcsr-boot-misc-detect"; }; - qcom_seecom: qseecom@82200000 { - compatible = "qcom,qseecom"; - reg = <0x82200000 0x2200000>; - reg-names = "secapp-region"; - memory-region = <&qseecom_mem>; - qcom,hlos-num-ce-hw-instances = <1>; - qcom,hlos-ce-hw-instance = <0>; - qcom,qsee-ce-hw-instance = <0>; - qcom,disk-encrypt-pipe-pair = <2>; - qcom,support-fde; - qcom,no-clock-support; - qcom,fde-key-size; - qcom,appsbl-qseecom-support; - qcom,commonlib64-loaded-by-uefi; - qcom,qsee-reentrancy-support = <2>; - }; - - qcom_smcinvoke: smcinvoke@82200000 { - compatible = "qcom,smcinvoke"; - reg = <0x82200000 0x2200000>; - reg-names = "secapp-region"; - }; - aop-msg-client { compatible = "qcom,debugfs-qmp-client"; mboxes = <&qmp_aop 0>; mbox-names = "aop"; }; - qcom_tzlog: tz-log@146aa720 { - compatible = "qcom,tz-log"; - reg = <0x146aa720 0x3000>; - qcom,hyplog-enabled; - hyplog-address-offset = <0x410>; - hyplog-size-offset = <0x414>; - }; - - qcom_rng: qrng@793000 { - compatible = "qcom,msm-rng"; - reg = <0x793000 0x1000>; - qcom,msm-rng-iface-clk; - qcom,no-qrng-config; - qcom,msm-bus,name = "msm-rng-noc"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <1 618 0 0>, /* No vote */ - <1 618 0 300000>; /* 75 MHz */ - clocks = <&clock_gcc GCC_PRNG_AHB_CLK>; - clock-names = "iface_clk"; - }; - - qcom_crypto: qcrypto@1de0000 { - compatible = "qcom,qcrypto"; - reg = <0x1de0000 0x20000>, - <0x1dc4000 0x24000>; - reg-names = "crypto-base","crypto-bam-base"; - interrupts = ; - qcom,bam-pipe-pair = <2>; - qcom,ce-hw-instance = <0>; - qcom,ce-device = <0>; - qcom,bam-ee = <0>; - qcom,ce-hw-shared; - qcom,clk-mgmt-sus-res; - qcom,msm-bus,name = "qcrypto-noc"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <125 512 0 0>, - <125 512 393600 393600>; - qcom,use-sw-aes-cbc-ecb-ctr-algo; - qcom,use-sw-aes-xts-algo; - qcom,use-sw-aes-ccm-algo; - qcom,use-sw-ahash-algo; - qcom,use-sw-aead-algo; - qcom,use-sw-hmac-algo; - qcom,smmu-s1-enable; - qcom,no-clock-support; - iommus = <&apps_smmu 0x0424 0x0011>, - <&apps_smmu 0x0434 0x0011>; - }; - - qcom_cedev: qcedev@1de0000 { - compatible = "qcom,qcedev"; - reg = <0x1de0000 0x20000>, - <0x1dc4000 0x24000>; - reg-names = "crypto-base","crypto-bam-base"; - interrupts = ; - qcom,bam-pipe-pair = <3>; - qcom,ce-hw-instance = <0>; - qcom,ce-device = <0>; - qcom,ce-hw-shared; - qcom,bam-ee = <0>; - qcom,msm-bus,name = "qcedev-noc"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <125 512 0 0>, - <125 512 393600 393600>; - qcom,smmu-s1-enable; - qcom,no-clock-support; - iommus = <&apps_smmu 0x0426 0x0011>, - <&apps_smmu 0x0436 0x0011>; - }; - qcom,msm-rtb { compatible = "qcom,msm-rtb"; qcom,rtb-size = <0x100000>; }; - ufs_ice: ufsice@1d90000 { - compatible = "qcom,ice"; - reg = <0x1d90000 0x8000>; - qcom,enable-ice-clk; - clock-names = "ufs_core_clk", "bus_clk", - "iface_clk", "ice_core_clk"; - clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>, - <&clock_gcc GCC_UFS_MEM_CLKREF_CLK>, - <&clock_gcc GCC_UFS_PHY_AHB_CLK>, - <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>; - qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; - vdd-hba-supply = <&ufs_phy_gdsc>; - qcom,msm-bus,name = "ufs_ice_noc"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <1 757 0 0>, /* No vote */ - <1 757 1000 0>; /* Max. bandwidth */ - qcom,bus-vector-names = "MIN", - "MAX"; - qcom,instance-type = "ufs"; - }; - - sdcc1_ice: sdcc1ice@7c8000{ - compatible = "qcom,ice"; - reg = <0x7c8000 0x8000>; - qcom,enable-ice-clk; - clock-names = "ice_core_clk_src", "ice_core_clk", - "bus_clk", "iface_clk"; - clocks = <&clock_gcc GCC_SDCC1_ICE_CORE_CLK_SRC>, - <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>, - <&clock_gcc GCC_SDCC1_AHB_CLK>, - <&clock_gcc GCC_SDCC1_APPS_CLK>; - qcom,op-freq-hz = <300000000>, <0>, <0>, <0>; - qcom,msm-bus,name = "sdcc_ice_noc"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <1 608 0 0>, /* No vote */ - <1 608 1000 0>; /* Max. bandwidth */ - qcom,bus-vector-names = "MIN", - "MAX"; - qcom,instance-type = "sdcc"; - }; - wdog: qcom,wdt@17c10000{ compatible = "qcom,msm-watchdog"; reg = <0x17c10000 0x1000>; @@ -1066,20 +892,6 @@ 0x10100 0x10100 0x25900 0x25900>; }; - eud: qcom,msm-eud@88e0000 { - compatible = "qcom,msm-eud"; - interrupt-names = "eud_irq"; - interrupts = ; - reg = <0x88e0000 0x2000>, - <0x88e2000 0x1000>; - reg-names = "eud_base", "eud_mode_mgr2"; - qcom,secure-eud-en; - qcom,eud-clock-vote-req; - clocks = <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; - clock-names = "eud_ahb2phy_clk"; - status = "ok"; - }; - qcom,chd_sliver { compatible = "qcom,core-hang-detect"; label = "silver"; @@ -1125,16 +937,6 @@ compatible = "qcom,pil-tz-generic"; reg = <0x4080000 0x100>; - clocks = <&clock_rpmh RPMH_CXO_CLK>; - clock-names = "xo"; - qcom,proxy-clock-names = "xo"; - - vdd_cx-supply = <&VDD_CX_LEVEL>; - qcom,vdd_cx-uV-uA = ; - vdd_mss-supply = <&VDD_MSS_LEVEL>; - qcom,vdd_mss-uV-uA = ; - qcom,proxy-reg-names = "vdd_cx", "vdd_mss"; - qcom,firmware-name = "modem"; memory-region = <&pil_modem_mem>; qcom,proxy-timeout-ms = <10000>; @@ -1172,16 +974,6 @@ compatible = "qcom,pil-tz-generic"; reg = <0x8300000 0x100000>; - vdd_cx-supply = <&VDD_CX_LEVEL>; - qcom,vdd_cx-uV-uA = ; - vdd_mx-supply = <&VDD_MX_LEVEL>; - qcom,vdd_mx-uV-uA = ; - qcom,proxy-reg-names = "vdd_cx", "vdd_mx"; - - clocks = <&clock_rpmh RPMH_CXO_CLK>; - clock-names = "xo"; - qcom,proxy-clock-names = "xo"; - qcom,pas-id = <18>; qcom,proxy-timeout-ms = <10000>; qcom,smem-id = <601>; @@ -1322,16 +1114,6 @@ compatible = "qcom,pil-tz-generic"; reg = <0x62400000 0x00100>; - vdd_lpi_cx-supply = <&L8A_LEVEL>; - qcom,vdd_cx-uV-uA = ; - vdd_lpi_mx-supply = <&L7A_LEVEL>; - qcom,vdd_mx-uV-uA = ; - qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx"; - - clocks = <&clock_rpmh RPMH_CXO_CLK>; - clock-names = "xo"; - qcom,proxy-clock-names = "xo"; - qcom,pas-id = <1>; qcom,proxy-timeout-ms = <10000>; qcom,smem-id = <423>; @@ -1542,11 +1324,6 @@ qcom,dump-node = <&L2_TLB_700>; qcom,dump-id = <0x127>; }; - - qcom,llcc1_d_cache { - qcom,dump-node = <&LLCC_1>; - qcom,dump-id = <0x140>; - }; }; mem_dump { @@ -1604,129 +1381,60 @@ }; }; - clocks { - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - clock-frequency = <32000>; - clock-output-names = "chip_sleep_clk"; - #clock-cells = <1>; - }; - }; - clock_rpmh: qcom,rpmh { - compatible = "qcom,rpmh-clk-atoll"; - mboxes = <&apps_rsc 0>; - mbox-names = "apps"; + compatible = "qcom,dummycc"; + clock-output-names = "rpm_clocks"; #clock-cells = <1>; }; clock_aop: qcom,aopclk { - compatible = "qcom,aop-qmp-clk"; + compatible = "qcom,dummycc"; + clock-output-names = "aop_clocks"; #clock-cells = <1>; - mboxes = <&qmp_aop 0>; - mbox-names = "qdss_clk"; }; - clock_gcc: qcom,gcc@100000 { - compatible = "qcom,atoll-gcc", "syscon"; - reg = <0x100000 0x1f0000>; - reg-names = "cc_base"; - vdd_cx-supply = <&VDD_CX_LEVEL>; - vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; + clock_gcc: qcom,gcc { + compatible = "qcom,dummycc"; + clock-output-names = "gcc_clocks"; #clock-cells = <1>; #reset-cells = <1>; }; - clock_camcc: qcom,camcc@ad00000 { - compatible = "qcom,atoll-camcc", "syscon"; - reg = <0xad00000 0x10000>; - reg-names = "cc_base"; - vdd_cx-supply = <&VDD_CX_LEVEL>; - vdd_mx-supply = <&VDD_MX_LEVEL>; + clock_camcc: qcom,camcc { + compatible = "qcom,dummycc"; + clock-output-names = "camcc_clocks"; #clock-cells = <1>; #reset-cells = <1>; }; - clock_dispcc: qcom,dispcc@af00000 { - compatible = "qcom,atoll-dispcc", "syscon"; - reg = <0xaf00000 0x20000>; - reg-names = "cc_base"; - vdd_cx-supply = <&VDD_CX_LEVEL>; + clock_dispcc: qcom,dispcc { + compatible = "qcom,dummycc"; + clock-output-names = "dispcc_clocks"; #clock-cells = <1>; #reset-cells = <1>; }; - clock_gpucc: qcom,gpucc@5090000 { - compatible = "qcom,atoll-gpucc", "syscon"; - reg = <0x5090000 0x9000>; - reg-names = "cc_base"; - vdd_cx-supply = <&VDD_CX_LEVEL>; - vdd_mx-supply = <&VDD_MX_LEVEL>; - vdd_gfx-supply = <&VDD_GFX_LEVEL>; - qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>; - qcom,gpu_cc_gmu_clk_src-opp-handle = <&gmu>; + clock_gpucc: qcom,gpucc { + compatible = "qcom,dummycc"; + clock-output-names = "gpucc_clocks"; #clock-cells = <1>; #reset-cells = <1>; }; - clock_npucc: qcom,npucc@9980000 { - compatible = "qcom,atoll-npucc", "syscon"; - reg = <0x9980000 0x10000>, - <0x9800000 0x10000>, - <0x9810000 0x10000>; - reg-names = "cc", "qdsp6ss", "qdsp6ss_pll"; - npu_gdsc-supply = <&npu_core_gdsc>; - vdd_cx-supply = <&VDD_CX_LEVEL>; + clock_npucc: qcom,npucc { + compatible = "qcom,dummycc"; + clock-output-names = "npucc_clocks"; #clock-cells = <1>; #reset-cells = <1>; }; - clock_videocc: qcom,videocc@ab00000 { - compatible = "qcom,atoll-videocc", "syscon"; - reg = <0xab00000 0x10000>; - reg-names = "cc_base"; - vdd_cx-supply = <&VDD_CX_LEVEL>; + clock_videocc: qcom,videocc { + compatible = "qcom,dummycc"; + clock-output-names = "videocc_clocks"; #clock-cells = <1>; #reset-cells = <1>; }; - clock_cpucc: qcom,cpucc@18321000 { - compatible = "qcom,clk-cpu-osm-atoll"; - reg = <0x18321000 0x1400>, - <0x18323000 0x1400>, - <0x18325800 0x1400>; - reg-names = "osm_l3_base", "osm_pwrcl_base", - "osm_perfcl_base"; - #clock-cells = <1>; - status = "disabled"; - }; - - cpucc_debug: syscon@182a0018 { - compatible = "syscon"; - reg = <0x182a0018 0x4>; - }; - - mccc_debug: syscon@90b0000 { - compatible = "syscon"; - reg = <0x090b0000 0x100>; - }; - - clock_debug: qcom,cc-debug { - compatible = "qcom,atoll-debugcc"; - qcom,cc-count = <8>; - qcom,gcc = <&clock_gcc>; - qcom,gpucc = <&clock_gpucc>; - qcom,camcc = <&clock_camcc>; - qcom,videocc = <&clock_videocc>; - qcom,dispcc = <&clock_dispcc>; - qcom,npucc = <&clock_npucc>; - qcom,cpucc = <&cpucc_debug>; - qcom,mccc = <&mccc_debug>; - clocks = <&clock_rpmh RPMH_CXO_CLK>; - clock-names = "xo_clk_src"; - #clock-cells = <1>; - }; - tcsr_mutex_block: syscon@01F40000 { compatible = "syscon"; reg = <0x01F40000 0x20000>; @@ -2252,6 +1960,7 @@ ipa_smmu_ap: ipa_smmu_ap { compatible = "qcom,ipa-smmu-ap-cb"; + qcom,smmu-s1-bypass; iommus = <&apps_smmu 0x0440 0x0>; qcom,iova-mapping = <0x20000000 0x40000000>; /* modem tables in IMEM */ @@ -2260,6 +1969,7 @@ ipa_smmu_wlan: ipa_smmu_wlan { compatible = "qcom,ipa-smmu-wlan-cb"; + qcom,smmu-s1-bypass; iommus = <&apps_smmu 0x0441 0x0>; /* ipa-uc ram */ qcom,additional-mapping = <0x1e60000 0x1e60000 0x80000>; @@ -2267,6 +1977,7 @@ ipa_smmu_uc: ipa_smmu_uc { compatible = "qcom,ipa-smmu-uc-cb"; + qcom,smmu-s1-bypass; iommus = <&apps_smmu 0x0442 0x0>; qcom,iova-mapping = <0x40400000 0x1fc00000>; }; @@ -2300,7 +2011,6 @@ interrupts = , ; interrupt-names = "hc_irq", "pwr_irq"; - sdhc-msm-crypto = <&sdcc1_ice>; qcom,bus-width = <8>; qcom,large-address-bus; @@ -2311,45 +2021,6 @@ qcom,devfreq,freq-table = <50000000 200000000>; - qcom,msm-bus,name = "sdhc1"; - qcom,msm-bus,num-cases = <9>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - /* No vote */ - <150 512 0 0>, <1 806 0 0>, - /* 400 KB/s*/ - <150 512 1000 2000>, - <1 806 2000 4000>, - /* 20 MB/s */ - <150 512 25000 50000>, - <1 806 20000 40000>, - /* 25 MB/s */ - <150 512 50000 100000>, - <1 806 30000 60000>, - /* 50 MB/s */ - <150 512 80000 150000>, - <1 806 40000 80000>, - /* 100 MB/s */ - <150 512 100000 200000>, - <1 806 50000 100000>, - /* 200 MB/s */ - <150 512 150000 250000>, - <1 806 80000 120000>, - /* 400 MB/s */ - <150 512 261438 2718822>, - <1 806 300000 1359411>, - /* Max. bandwidth */ - <150 512 1338562 4096000>, - <1 806 1338562 4096000>; - qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 - 100750000 200000000 400000000 4294967295>; - - /* PM QoS */ - qcom,pm-qos-irq-type = "affine_irq"; - qcom,pm-qos-irq-latency = <67 67>; - qcom,pm-qos-cpu-groups = <0x3f 0xc0>; - qcom,pm-qos-cmdq-latency-us = <67 67>, <67 67>; - qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>; clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, <&clock_gcc GCC_SDCC1_APPS_CLK>, <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>; @@ -2385,42 +2056,6 @@ qcom,devfreq,freq-table = <50000000 202000000>; - qcom,msm-bus,name = "sdhc2"; - qcom,msm-bus,num-cases = <8>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - /* No vote */ - <81 512 0 0>, <1 608 0 0>, - /* 400 KB/s*/ - <81 512 1000 2000>, - <1 608 1600 20000>, - /* 20 MB/s */ - <81 512 20000 40000>, - <1 608 20000 40000>, - /* 25 MB/s */ - <81 512 40000 80000>, - <1 608 30000 60000>, - /* 50 MB/s */ - <81 512 60000 120000>, - <1 608 40000 80000>, - /* 100 MB/s */ - <81 512 80000 160000>, - <1 608 50000 100000>, - /* 200 MB/s */ - <81 512 100000 200000>, - <1 608 60000 120000>, - /* Max. bandwidth */ - <81 512 1338562 4096000>, - <1 608 1338562 4096000>; - qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 - 100750000 200000000 4294967295>; - - /* PM QoS */ - qcom,pm-qos-irq-type = "affine_irq"; - qcom,pm-qos-irq-latency = <67 67>; - qcom,pm-qos-cpu-groups = <0x3f 0xc0>; - qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>; - clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>, <&clock_gcc GCC_SDCC2_APPS_CLK>; clock-names = "iface_clk", "core_clk"; @@ -2454,7 +2089,6 @@ interrupts = <0 265 0>; phys = <&ufsphy_mem>; phy-names = "ufsphy"; - ufs-qcom-crypto = <&ufs_ice>; lanes-per-direction = <1>; dev-ref-clk-freq = <0>; /* 19.2 MHz */ @@ -2584,27 +2218,6 @@ #thermal-sensor-cells = <1>; }; - icnss: qcom,icnss@18800000 { - status = "disabled"; - compatible = "qcom,icnss"; - reg = <0x18800000 0x800000>; - reg-names = "membase"; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; - qcom,smmu-s1-bypass; - qcom,wlan-msa-fixed-region = <&wlan_fw_mem>; - }; - qcom,venus@aae0000 { compatible = "qcom,pil-tz-generic"; reg = <0xaae0000 0x4000>; @@ -2629,412 +2242,6 @@ qcom,firmware-name = "venus"; memory-region = <&pil_video_mem>; }; - - qfprom: qfprom@780000 { - compatible = "qcom,qfprom"; - reg = <0x00786018 0x4>; - #address-cells = <1>; - #size-cells = <1>; - read-only; - ranges; - }; - - slim_aud: slim@62ec0000 { - cell-index = <1>; - compatible = "qcom,slim-ngd"; - reg = <0x62ec0000 0x2c000>, - <0x62e84000 0x2a000>; - reg-names = "slimbus_physical", "slimbus_bam_physical"; - interrupts = , - ; - interrupt-names = "slimbus_irq", "slimbus_bam_irq"; - qcom,apps-ch-pipes = <0x700000>; - qcom,ea-pc = <0x340>; - qcom,iommu-s1-bypass; - status = "ok"; - - iommu_slim_aud_ctrl_cb: qcom,iommu_slim_ctrl_cb { - compatible = "qcom,iommu-slim-ctrl-cb"; - iommus = <&apps_smmu 0x1026 0x0>, - <&apps_smmu 0x102f 0x0>, - <&apps_smmu 0x1030 0x1>; - }; - - btfmslim_codec: wcn3990 { - compatible = "qcom,btfmslim_slave"; - elemental-addr = [00 01 20 02 17 02]; - qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; - qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; - }; - }; - - bluetooth: bt_wcn3990 { - compatible = "qca,wcn3990"; - qca,bt-vdd-io-supply = <&pm6150_l10>; /* IO */ - qca,bt-vdd-core-supply = <&pm6150l_l2>; /* RFA */ - qca,bt-vdd-pa-supply = <&pm6150l_l10>; /* CH0 */ - qca,bt-vdd-xtal-supply = <&pm6150l_l1>;/* X0 */ - - qca,bt-vdd-io-voltage-level = <1721000 1829000>; - qca,bt-vdd-core-voltage-level = <1200000 1350000>; - qca,bt-vdd-pa-voltage-level = <3300000 3400000>; - qca,bt-vdd-xtal-voltage-level = <1620000 1980000>; - - qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ - }; - - keepalive_opp_table: keepalive-opp-table { - compatible = "operating-points-v2"; - opp-1 { - opp-hz = /bits/ 64 < 1 >; - }; - }; - - snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive { - compatible = "qcom,devbw"; - governor = "powersave"; - qcom,src-dst-ports = <1 627>; - qcom,active-only; - status = "ok"; - operating-points-v2 = <&keepalive_opp_table>; - }; - - bus_proxy_client: qcom,bus_proxy_client { - compatible = "qcom,bus-proxy-client"; - qcom,msm-bus,name = "bus-proxy-client"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - ; - qcom,msm-bus,active-only; - status = "ok"; - }; - - llcc_bw_opp_table: llcc-bw-opp-table { - compatible = "operating-points-v2"; - BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ - BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */ - BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */ - BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */ - BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */ - BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */ - }; - - cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw { - compatible = "qcom,devbw"; - governor = "performance"; - qcom,src-dst-ports = - ; - qcom,active-only; - operating-points-v2 = <&llcc_bw_opp_table>; - }; - - cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6300 { - compatible = "qcom,bimc-bwmon4"; - reg = <0x90b6300 0x300>, <0x90b6200 0x200>; - reg-names = "base", "global_base"; - interrupts = ; - qcom,mport = <0>; - qcom,hw-timer-hz = <19200000>; - qcom,target-dev = <&cpu_cpu_llcc_bw>; - qcom,count-unit = <0x10000>; - }; - - ddr_bw_opp_table: ddr-bw-opp-table { - compatible = "operating-points-v2"; - BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ - BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ - BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ - BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ - BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ - BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ - BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ - BW_OPP_ENTRY(2133, 4); /* 8137 MB/s */ - }; - - cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw { - compatible = "qcom,devbw"; - governor = "performance"; - qcom,src-dst-ports = - ; - qcom,active-only; - operating-points-v2 = <&ddr_bw_opp_table>; - }; - - cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@90cd000 { - compatible = "qcom,bimc-bwmon5"; - reg = <0x90cd000 0x1000>; - reg-names = "base"; - interrupts = ; - qcom,hw-timer-hz = <19200000>; - qcom,target-dev = <&cpu_llcc_ddr_bw>; - qcom,count-unit = <0x10000>; - }; - - cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { - compatible = "devfreq-simple-dev"; - clock-names = "devfreq_clk"; - clocks = <&clock_cpucc L3_CLUSTER0_VOTE_CLK>; - governor = "performance"; - }; - - cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; - qcom,target-dev = <&cpu0_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,core-dev-table = - < 768000 300000000 >, - < 1017600 556800000 >, - < 1248000 806400000 >, - < 1516800 940800000 >, - < 1804800 1401000000 >; - }; - - cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat { - compatible = "devfreq-simple-dev"; - clock-names = "devfreq_clk"; - clocks = <&clock_cpucc L3_CLUSTER1_VOTE_CLK>; - governor = "performance"; - }; - - cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU6 &CPU7>; - qcom,target-dev = <&cpu6_cpu_l3_lat>; - qcom,cachemiss-ev = <0x17>; - qcom,core-dev-table = - < 1113600 556800000 >, - < 1267200 806400000 >, - < 1555200 940800000 >, - < 1708800 1209600000 >, - < 1900800 1401000000 >, - < 2400000 1459000000 >; - }; - - cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat { - compatible = "qcom,devbw"; - governor = "performance"; - qcom,src-dst-ports = - ; - qcom,active-only; - operating-points-v2 = <&llcc_bw_opp_table>; - }; - - cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; - qcom,target-dev = <&cpu0_cpu_llcc_lat>; - qcom,cachemiss-ev = <0x2A>; - qcom,core-dev-table = - < 1248000 MHZ_TO_MBPS(300, 16) >, - < 1516800 MHZ_TO_MBPS(466, 16) >, - < 1804800 MHZ_TO_MBPS(600, 16) >; - }; - - cpu6_cpu_llcc_lat: qcom,cpu6-cpu-llcc-lat { - compatible = "qcom,devbw"; - governor = "performance"; - qcom,src-dst-ports = - ; - qcom,active-only; - operating-points-v2 = <&llcc_bw_opp_table>; - }; - - cpu6_cpu_llcc_latmon: qcom,cpu6-cpu-llcc-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU6 &CPU7>; - qcom,target-dev = <&cpu6_cpu_llcc_lat>; - qcom,cachemiss-ev = <0x2A>; - qcom,core-dev-table = - < 825600 MHZ_TO_MBPS(300, 16) >, - < 1113600 MHZ_TO_MBPS(466, 16) >, - < 1267200 MHZ_TO_MBPS(600, 16) >, - < 1708800 MHZ_TO_MBPS(806, 16) >, - < 2400000 MHZ_TO_MBPS(933, 16) >; - }; - - cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat { - compatible = "qcom,devbw"; - governor = "performance"; - qcom,src-dst-ports = - ; - qcom,active-only; - operating-points-v2 = <&ddr_bw_opp_table>; - }; - - cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; - qcom,target-dev = <&cpu0_llcc_ddr_lat>; - qcom,cachemiss-ev = <0x1000>; - qcom,core-dev-table = - < 768000 MHZ_TO_MBPS( 300, 4) >, - < 1017600 MHZ_TO_MBPS( 451, 4) >, - < 1248000 MHZ_TO_MBPS( 547, 4) >, - < 1516800 MHZ_TO_MBPS( 768, 4) >, - < 1804800 MHZ_TO_MBPS(1017, 4) >; - }; - - cpu6_llcc_ddr_lat: qcom,cpu6-llcc-ddr-lat { - compatible = "qcom,devbw"; - governor = "performance"; - qcom,src-dst-ports = - ; - qcom,active-only; - operating-points-v2 = <&ddr_bw_opp_table>; - }; - - cpu6_llcc_ddr_latmon: qcom,cpu6-llcc-ddr-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU6 &CPU7>; - qcom,target-dev = <&cpu6_llcc_ddr_lat>; - qcom,cachemiss-ev = <0x1000>; - qcom,core-dev-table = - < 1113600 MHZ_TO_MBPS( 547, 4) >, - < 1267200 MHZ_TO_MBPS(1017, 4) >, - < 1708800 MHZ_TO_MBPS(1555, 4) >, - < 2400000 MHZ_TO_MBPS(1804, 4) >; - }; - - cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { - compatible = "qcom,devbw"; - governor = "performance"; - qcom,src-dst-ports = - ; - qcom,active-only; - operating-points-v2 = <&ddr_bw_opp_table>; - }; - - cpu0_computemon: qcom,cpu0-computemon { - compatible = "qcom,arm-cpu-mon"; - qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>; - qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; - qcom,core-dev-table = - < 768000 MHZ_TO_MBPS( 300, 4) >, - < 1248000 MHZ_TO_MBPS( 451, 4) >, - < 1516800 MHZ_TO_MBPS( 547, 4) >, - < 1804800 MHZ_TO_MBPS( 768, 4) >; - }; - - cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor { - compatible = "qcom,devbw"; - governor = "performance"; - qcom,src-dst-ports = - ; - qcom,active-only; - operating-points-v2 = <&ddr_bw_opp_table>; - }; - - cpu6_computemon: qcom,cpu6-computemon { - compatible = "qcom,arm-cpu-mon"; - qcom,cpulist = <&CPU6 &CPU7>; - qcom,target-dev = <&cpu6_cpu_ddr_latfloor>; - qcom,core-dev-table = - < 1267200 MHZ_TO_MBPS( 547, 4) >, - < 1555200 MHZ_TO_MBPS( 768, 4) >, - < 1708800 MHZ_TO_MBPS(1017, 4) >, - < 1900800 MHZ_TO_MBPS(1555, 4) >, - < 2208000 MHZ_TO_MBPS(1804, 4) >, - < 2400000 MHZ_TO_MBPS(2133, 4) >; - }; - - suspendable_ddr_bw_opp_table: suspendable-ddr-bw-opp-table { - compatible = "operating-points-v2"; - BW_OPP_ENTRY( 0, 4); /* 0 MB/s */ - BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ - BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ - BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ - BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ - BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ - BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ - BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ - BW_OPP_ENTRY(2133, 4); /* 8137 MB/s */ - }; - - npu_npu_ddr_bw: qcom,npu-npu-ddr-bw { - compatible = "qcom,devbw"; - governor = "performance"; - qcom,src-dst-ports = ; - operating-points-v2 = <&suspendable_ddr_bw_opp_table>; - status = "disabled"; - }; - - npu_npu_ddr_bwmon: qcom,npu-npu-ddr-bwmon@00060300 { - compatible = "qcom,bimc-bwmon4"; - reg = <0x00060300 0x300>, <0x00060200 0x200>; - reg-names = "base", "global_base"; - clocks = <&clock_gcc GCC_NPU_BWMON_DMA_CFG_AHB_CLK>, - <&clock_gcc GCC_NPU_BWMON_AXI_CLK>; - clock-names = "gcc_npu_bwmon_dma_cfg_ahb_clk", - "gcc_npu_bwmon_axi_clk"; - qcom,bwmon_clks = "gcc_npu_bwmon_dma_cfg_ahb_clk", - "gcc_npu_bwmon_axi_clk"; - interrupts = ; - qcom,mport = <0>; - qcom,hw-timer-hz = <19200000>; - qcom,target-dev = <&npu_npu_ddr_bw>; - qcom,count-unit = <0x10000>; - status = "disabled"; - }; - - npudsp_npu_ddr_bw: qcom,npudsp-npu-ddr-bw { - compatible = "qcom,devbw"; - governor = "performance"; - qcom,src-dst-ports = ; - operating-points-v2 = <&suspendable_ddr_bw_opp_table>; - status = "disabled"; - }; - - npudsp_npu_ddr_bwmon: qcom,npudsp-npu-ddr-bwmon@70200 { - compatible = "qcom,bimc-bwmon4"; - reg = <0x00070200 0x300>, <0x00070000 0x200>; - reg-names = "base", "global_base"; - clocks = <&clock_gcc GCC_NPU_BWMON_DSP_CFG_AHB_CLK>, - <&clock_gcc GCC_NPU_BWMON_AXI_CLK>; - clock-names = "gcc_npu_bwmon_dsp_cfg_ahb_clk", - "gcc_npu_bwmon_axi_clk"; - qcom,bwmon_clks = "gcc_npu_bwmon_dsp_cfg_ahb_clk", - "gcc_npu_bwmon_axi_clk"; - interrupts = ; - qcom,mport = <0>; - qcom,hw-timer-hz = <19200000>; - qcom,target-dev = <&npudsp_npu_ddr_bw>; - qcom,count-unit = <0x10000>; - status = "disabled"; - }; - - /delete-node/gpu-bw-tbl; - /delete-node/qcom,gpubw; - - gpu_bw_tbl: gpu-bw-tbl { - compatible = "operating-points-v2"; - opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */ - opp-100 { opp-hz = /bits/ 64 < 381 >; }; /* 1.DDR:100 MHz */ - opp-200 { opp-hz = /bits/ 64 < 762 >; }; /* 2.DDR:200 MHz */ - opp-300 { opp-hz = /bits/ 64 < 1144 >; }; /* 3.DDR:300 MHz */ - opp-451 { opp-hz = /bits/ 64 < 1720 >; }; /* 4.DDR:451 MHz */ - opp-547 { opp-hz = /bits/ 64 < 2086 >; }; /* 5.DDR:547 MHz */ - opp-681 { opp-hz = /bits/ 64 < 2597 >; }; /* 6.DDR:681 MHz */ - opp-825 { opp-hz = /bits/ 64 < 3147 >; }; /* 7.DDR:825 MHz */ - opp-1017 { opp-hz = /bits/ 64 < 3879 >; }; /* 8.DDR:1017 MHz */ - opp-1353 { opp-hz = /bits/ 64 < 5161 >; }; /* 9.DDR:1353 MHz */ - opp-1555 { opp-hz = /bits/ 64 < 5931 >; }; /* 10.DDR:1555 MHz */ - opp-1804 { opp-hz = /bits/ 64 < 6881 >; }; /* 11.DDR:1804 MHz */ - opp-2133 { opp-hz = /bits/ 64 < 8137 >; }; /* 12.DDR:2133 MHz */ - }; - - gpubw: qcom,gpubw { - compatible = "qcom,devbw"; - governor = "bw_vbif"; - qcom,src-dst-ports = <26 512>; - operating-points-v2 = <&gpu_bw_tbl>; - }; }; #include "atoll-gdsc.dtsi" @@ -3042,123 +2249,9 @@ #include "msm-arm-smmu-atoll.dtsi" #include "atoll-qupv3.dtsi" #include "sdmmagpie-gpu.dtsi" -#include "atoll-bus.dtsi" &msm_gpu { - /delete-property/ qcom,gpu-speed-bin; - /delete-property/ qcom,msm-bus,num-cases; - /delete-property/ qcom,msm-bus,vectors-KBps; - /delete-property/ qcom,initial-pwrlevel; - /delete-property/ qcom,ca-target-pwrlevel; - - qcom,msm-bus,num-cases = <13>; - qcom,msm-bus,vectors-KBps = - <26 512 0 0>, - <26 512 0 400000>, /* 1 bus=100 */ - <26 512 0 800000>, /* 2 bus=200 */ - <26 512 0 1200000>, /* 3 bus=300 */ - <26 512 0 1804000>, /* 4 bus=451 */ - <26 512 0 2188000>, /* 5 bus=547 */ - <26 512 0 2724000>, /* 6 bus=681 */ - <26 512 0 3300000>, /* 7 bus=825 */ - <26 512 0 4068000>, /* 8 bus=1017 */ - <26 512 0 5412000>, /* 9 bus=1353 */ - <26 512 0 6220000>, /* 10 bus=1555 */ - <26 512 0 7216000>, /* 11 bus=1804 */ - <26 512 0 8532000>; /* 12 bus=2133 */ - - qcom,initial-pwrlevel = <7>; - qcom,ca-target-pwrlevel = <5>; - - /delete-node/ qcom,gpu-pwrlevel-bins; - - qcom,gpu-pwrlevels { - #address-cells = <1>; - #size-cells = <0>; - - compatible = "qcom,gpu-pwrlevels"; - - /* TURBO_L1 */ - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <825000000>; - qcom,bus-freq = <11>; - qcom,bus-min = <10>; - qcom,bus-max = <12>; - }; - - /* TURBO */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <800000000>; - qcom,bus-freq = <11>; - qcom,bus-min = <10>; - qcom,bus-max = <11>; - }; - - /* NOM_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <650000000>; - qcom,bus-freq = <10>; - qcom,bus-min = <8>; - qcom,bus-max = <11>; - }; - - /* NOM */ - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <565000000>; - qcom,bus-freq = <9>; - qcom,bus-min = <8>; - qcom,bus-max = <10>; - }; - - /* SVS_L1 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <430000000>; - qcom,bus-freq = <8>; - qcom,bus-min = <7>; - qcom,bus-max = <10>; - }; - - /* SVS */ - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <355000000>; - qcom,bus-freq = <7>; - qcom,bus-min = <5>; - qcom,bus-max = <8>; - }; - - /* LOW SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <267000000>; - qcom,bus-freq = <6>; - qcom,bus-min = <4>; - qcom,bus-max = <7>; - }; - - /* LOW SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <180000000>; - qcom,bus-freq = <4>; - qcom,bus-min = <3>; - qcom,bus-max = <4>; - }; - - /* XO */ - qcom,gpu-pwrlevel@8 { - reg = <8>; - qcom,gpu-freq = <0>; - qcom,bus-freq = <0>; - qcom,bus-min = <0>; - qcom,bus-max = <0>; - }; - }; + /delete-property/qcom,gpu-speed-bin; }; &ufs_phy_gdsc { @@ -3225,19 +2318,23 @@ status = "ok"; }; -&qupv3_se3_4uart { - status = "ok"; -}; - #include "pm6150.dtsi" #include "pm6150l.dtsi" #include "atoll-pinctrl.dtsi" #include "atoll-pm.dtsi" #include "atoll-coresight.dtsi" -#include "atoll-regulator.dtsi" +#include "atoll-stub-regulator.dtsi" #include "atoll-usb.dtsi" #include "atoll-vidc.dtsi" +&usb0 { + extcon = <&pm6150_pdphy>, <&pm6150_charger>; +}; + +&usb_qmp_dp_phy { + extcon = <&pm6150_pdphy>; +}; + &pm6150_vadc { pinctrl-names = "default"; pinctrl-0 = <&nvm_therm_default &sdm_skin_therm_default>; @@ -3386,92 +2483,4 @@ }; }; -#include "atoll-audio.dtsi" #include "atoll-thermal.dtsi" -#include "atoll-camera.dtsi" -#include "atoll-sde-pll.dtsi" -#include "atoll-sde.dtsi" - -&qupv3_se9_i2c { - status = "ok"; - #include "pm8008.dtsi" -}; - -&tlmm { - pm8008_active: pm8008_active { - mux { - pins = "gpio42"; - function = "gpio"; - }; - - config { - pins = "gpio42"; - bias-pull-up; - output-high; - drive-strength = <2>; - }; - }; -}; - -&pm8008_gpios { - gpio1_active { - pm8008_gpio1_active: pm8008_gpio1_active { - pins = "gpio1"; - function = "normal"; - power-source = <1>; - bias-disable; - input-enable; - }; - }; -}; - -&pm8008_chip { - pinctrl-names = "default"; - pinctrl-0 = <&pm8008_active>; -}; - -&pm8008_regulators { - vdd_l1_l2-supply = <&S8C>; - vdd_l3_l4-supply = <&BOB>; - vdd_l5-supply = <&S5A>; - vdd_l6-supply = <&BOB>; - vdd_l7-supply = <&BOB>; -}; - -&pm8008_9 { - /* GPIO1 pinctrl config */ - pinctrl-names = "default"; - pinctrl-0 = <&pm8008_gpio1_active>; -}; - -&L1P { - regulator-max-microvolt = <1104000>; - qcom,min-dropout-voltage = <225000>; -}; - -&L2P { - regulator-max-microvolt = <1200000>; - qcom,min-dropout-voltage = <75000>; -}; - -&L3P { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - qcom,min-dropout-voltage = <200000>; -}; - -&L4P { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - qcom,min-dropout-voltage = <200000>; -}; - -&L5P { - regulator-max-microvolt = <1800000>; - qcom,min-dropout-voltage = <200000>; -}; - -&L6P { - regulator-max-microvolt = <2800000>; - qcom,min-dropout-voltage = <300000>; -}; diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-samsung_oneplus_dsc.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-samsung_oneplus_dsc.dtsi new file mode 100644 index 000000000000..d52ead622a0e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/dsi-panel-samsung_oneplus_dsc.dtsi @@ -0,0 +1,2665 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_samsung_oneplus_dsc_cmd: qcom,mdss_dsi_samsung_oneplus_dsc_cmd { + qcom,mdss-dsi-panel-name = "samsung dsc cmd mode oneplus dsi panel"; + qcom,mdss-dsi-panel-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-version = "DSC"; + qcom,mdss-dsi-backlight-version = "SAMSUNG"; + qcom,mdss-dsi-backlight-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-reset-sequence = <1 8>, <0 1>, <1 5>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-default-val = <200>; + qcom,mdss-brightness-max-level = <1023>; + qcom,mdss-pan-physical-width-dimension = <71>; + qcom,mdss-pan-physical-height-dimension = <154>; + qcom,mdss-dsi-init-delay-us = <1000>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-high-brightness-panel; + qcom,mdss-dsi-acl-cmd-index = <0>; + qcom,mdss-dsi-acl-mode-index = <1>; + qcom,mdss-bl-high2bit; + qcom,mdss-loading-effect; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,dynamic-mode-switch-enabled; + qcom,dynamic-mode-switch-type = "dynamic-resolution-switch-immediate"; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + /* HDR Setting */ + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15635 16450 34000 16000 13250 34500 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <5400000>; + qcom,mdss-dsi-panel-average-brightness = <2000000>; + qcom,mdss-dsi-panel-blackness-level = <2000>; + qcom,mdss-dsi-panel-seria-num-year-index = <12>; + qcom,mdss-dsi-panel-seria-num-mon-index = <12>; + qcom,mdss-dsi-panel-seria-num-day-index = <13>; + qcom,mdss-dsi-panel-seria-num-hour-index = <14>; + qcom,mdss-dsi-panel-seria-num-min-index = <15>; + qcom,mdss-dsi-panel-seria-num-sec-index = <16>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 00]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-id1-command = [06 01 00 00 00 00 02 0A 00]; + qcom,mdss-dsi-panel-id2-command = [06 01 00 00 00 00 02 0E 00]; + qcom,mdss-dsi-panel-id3-command = [06 01 00 00 00 00 02 0F 00]; + qcom,mdss-dsi-panel-id4-command = [06 01 00 00 00 00 02 C4 00]; + qcom,mdss-dsi-panel-id5-command = [06 01 00 00 00 00 02 E7 00]; + qcom,mdss-dsi-panel-id6-command = [06 01 00 00 00 00 02 EA 00]; + qcom,mdss-dsi-panel-id7-command = [06 01 00 00 00 00 02 FB 00]; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-read-esd-registed-longread-command = [ + 37 01 00 00 05 00 02 22 00 + ]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-esd-registed-longread-command-state = "dsi_lp_mode"; + + /* + * ************************************************************************************************************************ + * DMS (Dynamic Mode Switch) + * ************************************************************************************************************************ + */ + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,mdss-mdp-transfer-time-us = <8000>; //for 60fps + qcom,mdss-dsi-timing-default; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3120>; + qcom,mdss-dsi-h-front-porch = <16>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <1156>; + qcom,mdss-dsi-v-front-porch = <400>; + qcom,mdss-dsi-v-pulse-width = <28>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 00]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-id1-command = [06 01 00 00 00 00 02 0A 00]; + qcom,mdss-dsi-panel-id2-command = [06 01 00 00 00 00 02 0E 00]; + qcom,mdss-dsi-panel-id3-command = [06 01 00 00 00 00 02 0F 00]; + qcom,mdss-dsi-panel-id4-command = [06 01 00 00 00 00 02 C4 00]; + qcom,mdss-dsi-panel-id5-command = [06 01 00 00 00 00 02 E7 00]; + qcom,mdss-dsi-panel-id6-command = [06 01 00 00 00 00 02 EA 00]; + qcom,mdss-dsi-panel-id7-command = [06 01 00 00 00 00 02 FB 00]; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-read-esd-registed-longread-command = [ + 37 01 00 00 05 00 02 22 00 + ]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-esd-registed-longread-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-timing-switch-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + //29 01 00 00 00 00 03 9F A5 A5 + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 29 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + //29 01 00 00 00 00 03 9F 5A 5A + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-on-command = [ + /* DSC Setting */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 39 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 39 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 09 10 B4 24 FB /* FFC Setting; 0x09 : Enable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame*/ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-113mhz-osc-dsi-on-command = [ + /* DSC Setting */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 39 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 39 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 08 10 B4 24 FB /* FFC Setting; 0x08 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame*/ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-113mhz-osc-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-off-command=[ + 05 01 00 00 0A 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-panel-hbm-brightness-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 53 /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM Mode ON */ + 15 01 00 00 11 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-brightness-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 53 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 11 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-hbm-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-3 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-4 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 14 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 29 01 00 00 0D 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 11 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + ]; + qcom,mdss-dsi-panel-serial-num-pre-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 37 01 00 00 05 00 02 10 00 + ]; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 00 + ]; + qcom,mdss-dsi-panel-code-info-command = [ + 06 01 00 00 00 00 01 DA 00 + ]; + qcom,mdss-dsi-panel-stage-info-command = [ + 06 01 00 00 00 00 01 DB 00 + ]; + qcom,mdss-dsi-panel-production-info-command = [ + 06 01 00 00 00 00 01 DC 00 + ]; + qcom,mdss-dsi-panel-serial-num-post-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-aod-off-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 29 01 00 00 00 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command = [ + /*Level2 key Enable*/ + 29 01 00 00 00 00 03 F0 5A 5A + //07 01 00 00 00 00 01 01 + //29 00 00 00 00 00 05 2A 00 00 05 9F + //29 00 00 00 00 00 05 2B 00 00 0C 2F + /*OTP key Enable*/ + 29 01 00 00 00 00 03 F1 F1 A2 + 29 01 00 00 00 00 0D C1 00 00 00 06 00 00 00 00 00 00 00 05 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0C C1 00 00 00 01 40 02 00 00 00 00 10 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0E C1 00 00 00 6B 00 00 00 0A 00 00 00 05 01 + 15 01 00 00 00 00 02 B0 07 + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command = [ + 15 01 00 00 00 00 02 C0 03 + 15 01 00 00 00 00 02 B0 08 + ]; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command = [ + /*13th Parameter : 1byte Read value*/ + 06 01 00 00 00 00 02 FB 00 + ]; + qcom,mdss-dsi-panel-level2-key-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command = [ + 37 01 00 00 05 00 02 87 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command = [ + 06 01 00 00 00 00 02 C8 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command = [ + 37 01 00 00 00 00 02 B4 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command = [ + 06 01 00 00 00 00 02 C9 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command = [ + 37 01 00 00 00 00 02 2F 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command = [ + 06 01 00 00 00 00 02 B3 00 + ]; + qcom,mdss-dsi-panel-level2-key-disable-command = [ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-night-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 39 01 00 0A 00 00 16 67 BB 0E 04 3E D8 12 09 05 EA 41 E2 D0 E5 09 F6 D0 D0 11 F8 FE DC + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-p3-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 E0 03 00 11 E2 01 0D 08 E5 1A FA FC E5 09 F6 EA F3 01 FE FF F7 + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 03 67 00 01 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 81 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 FF 6D + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-disable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 A1 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 28 28 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-srgb-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command = [ + 15 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 0A 00 02 B0 02 + 29 01 00 00 0A 00 16 67 FF 05 00 0B EB 00 07 00 FF 14 F8 EA F0 03 F5 DE F5 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-seed-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 D3 03 00 11 E4 01 0B 06 F0 1A FA FC E5 09 F6 EA F3 01 FC FF EA + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-seed-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-customer-p3-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-customer-srgb-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-loading-effect-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-loading-effect-disable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-p3-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-night-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-dci-p3-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-aod-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-pre-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-code-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-state-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-production-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-post-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-brightness-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-brightness-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-3-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-4-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-disable-command-state = "dsi_lp_mode"; + qcom,panel-roi-alignment=<720 65 720 65 720 65>; + qcom,compression-mode = "dsc"; + qcom,lm-split = <720 720>; + qcom,mdss-dsc-encoders = <2>; + qcom,mdss-dsc-slice-height = <65>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1{ + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,mdss-mdp-transfer-time-us = <8000>; //for 90fps + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <16>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <4>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 00]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-id1-command = [06 01 00 00 00 00 02 0A 00]; + qcom,mdss-dsi-panel-id2-command = [06 01 00 00 00 00 02 0E 00]; + qcom,mdss-dsi-panel-id3-command = [06 01 00 00 00 00 02 0F 00]; + qcom,mdss-dsi-panel-id4-command = [06 01 00 00 00 00 02 C4 00]; + qcom,mdss-dsi-panel-id5-command = [06 01 00 00 00 00 02 E7 00]; + qcom,mdss-dsi-panel-id6-command = [06 01 00 00 00 00 02 EA 00]; + qcom,mdss-dsi-panel-id7-command = [06 01 00 00 00 00 02 FB 00]; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 F0 5A 5A]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-panel-read-esd-registed-longread-command = [ + 37 01 00 00 05 00 02 22 00 + ]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-esd-registed-longread-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-timing-switch-command = [ + 29 01 00 00 00 00 03 F0 5A 5A /* Level2 key Access Enable */ + //29 01 00 00 00 00 03 9F A5 A5 /* Level1 key Access Enable */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 23 /* PASET */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2340) */ + 11 00 00 89 30 80 09 24 + 04 38 00 1E 02 1C 02 1C + 02 00 02 0E 00 20 02 E3 + 00 07 00 0C 03 50 03 64 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + //29 01 00 00 00 00 03 9F 5A 5A + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-on-command = [ + /* DSC Setting */ + 29 01 00 00 00 00 03 F0 5A 5A + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2340) */ + 11 00 00 89 30 80 09 24 + 04 38 00 1E 02 1C 02 1C + 02 00 02 0E 00 20 02 E3 + 00 07 00 0C 03 50 03 64 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 29 01 00 00 00 00 03 F0 A5 A5 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 23 /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 09 10 B4 24 FB /* FFC Setting; 0x09 : Enable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame */ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-113mhz-osc-dsi-on-command = [ + /* DSC Setting */ + 29 01 00 00 00 00 03 F0 5A 5A + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2340) */ + 11 00 00 89 30 80 09 24 + 04 38 00 1E 02 1C 02 1C + 02 00 02 0E 00 20 02 E3 + 00 07 00 0C 03 50 03 64 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 29 01 00 00 00 00 03 F0 A5 A5 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 23 /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 08 10 B4 24 FB /* FFC Setting; 0x08 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame */ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-113mhz-osc-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-off-command=[ + 05 01 00 00 0A 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-panel-hbm-brightness-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 53 /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM Mode ON */ + 15 01 00 00 0C 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-brightness-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 53 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 0C 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-hbm-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-3 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-4 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 10 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 29 01 00 00 0C 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-serial-num-pre-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 37 01 00 00 05 00 02 10 00 + ]; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 00 + ]; + qcom,mdss-dsi-panel-code-info-command = [ + 06 01 00 00 00 00 01 DA 00 + ]; + qcom,mdss-dsi-panel-stage-info-command = [ + 06 01 00 00 00 00 01 DB 00 + ]; + qcom,mdss-dsi-panel-production-info-command = [ + 06 01 00 00 00 00 01 DC 00 + ]; + qcom,mdss-dsi-panel-serial-num-post-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-aod-off-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 29 01 00 00 00 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command = [ + /*Level2 key Enable*/ + 29 01 00 00 00 00 03 F0 5A 5A + //07 01 00 00 00 00 01 01 + //29 00 00 00 00 00 05 2A 00 00 05 9F + //29 00 00 00 00 00 05 2B 00 00 0C 2F + /*OTP key Enable*/ + 29 01 00 00 00 00 03 F1 F1 A2 + 29 01 00 00 00 00 0D C1 00 00 00 06 00 00 00 00 00 00 00 05 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0C C1 00 00 00 01 40 02 00 00 00 00 10 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0E C1 00 00 00 6B 00 00 00 0A 00 00 00 05 01 + 15 01 00 00 00 00 02 B0 07 + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command = [ + 15 01 00 00 00 00 02 C0 03 + 15 01 00 00 00 00 02 B0 08 + ]; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command = [ + /*13th Parameter : 1byte Read value*/ + 06 01 00 00 00 00 02 FB 00 + ]; + qcom,mdss-dsi-panel-level2-key-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command = [ + 37 01 00 00 00 00 02 87 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command = [ + 06 01 00 00 00 00 02 C8 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command = [ + 37 01 00 00 00 00 02 B4 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command = [ + 06 01 00 00 00 00 02 C9 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command = [ + 37 01 00 00 00 00 02 2F 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command = [ + 06 01 00 00 00 00 02 B3 00 + ]; + qcom,mdss-dsi-panel-level2-key-disable-command = [ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-night-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 39 01 00 0A 00 00 16 67 BB 0E 04 3E D8 12 09 05 EA 41 E2 D0 E5 09 F6 D0 D0 11 F8 FE DC + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-p3-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 E0 03 00 11 E2 01 0D 08 E5 1A FA FC E5 09 F6 EA F3 01 FE FF F7 + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 03 67 00 01 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 81 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 FF 6D + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-disable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 A1 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 28 28 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-srgb-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command = [ + 15 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 0A 00 02 B0 02 + 29 01 00 00 0A 00 16 67 FF 05 00 0B EB 00 07 00 FF 14 F8 EA F0 03 F5 DE F5 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-seed-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 D3 03 00 11 E4 01 0B 06 F0 1A FA FC E5 09 F6 EA F3 01 FC FF EA + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-seed-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-customer-p3-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-customer-srgb-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-loading-effect-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-loading-effect-disable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-p3-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-night-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-dci-p3-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-aod-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-pre-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-code-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-state-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-production-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-post-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-brightness-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-brightness-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-3-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-4-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-disable-command-state = "dsi_lp_mode"; + qcom,panel-roi-alignment=<540 60 540 60 540 60>; + qcom,compression-mode = "dsc"; + qcom,lm-split = <540 540>; + qcom,mdss-dsc-encoders = <2>; + qcom,mdss-dsc-slice-height = <60>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2{ + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,mdss-mdp-transfer-time-us = <8000>; //for 60fps + qcom,mdss-dsi-timing-default; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <16>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <1156>; + qcom,mdss-dsi-v-front-porch = <400>; + qcom,mdss-dsi-v-pulse-width = <28>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 00]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-id1-command = [06 01 00 00 00 00 02 0A 00]; + qcom,mdss-dsi-panel-id2-command = [06 01 00 00 00 00 02 0E 00]; + qcom,mdss-dsi-panel-id3-command = [06 01 00 00 00 00 02 0F 00]; + qcom,mdss-dsi-panel-id4-command = [06 01 00 00 00 00 02 C4 00]; + qcom,mdss-dsi-panel-id5-command = [06 01 00 00 00 00 02 E7 00]; + qcom,mdss-dsi-panel-id6-command = [06 01 00 00 00 00 02 EA 00]; + qcom,mdss-dsi-panel-id7-command = [06 01 00 00 00 00 02 FB 00]; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-read-esd-registed-longread-command = [ + 37 01 00 00 05 00 02 22 00 + ]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-esd-registed-longread-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-timing-switch-command = [ + 29 01 00 00 00 00 03 F0 5A 5A /* Level2 key Access Enable */ + //29 01 00 00 00 00 03 9F A5 A5 /* Level1 key Access Enable */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 23 /* PASET */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2340) */ + 11 00 00 89 30 80 09 24 + 04 38 00 1E 02 1C 02 1C + 02 00 02 0E 00 20 02 E3 + 00 07 00 0C 03 50 03 64 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + //29 01 00 00 00 00 03 9F 5A 5A + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-on-command = [ + /* DSC Setting */ + 29 01 00 00 00 00 03 F0 5A 5A + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2340) */ + 11 00 00 89 30 80 09 24 + 04 38 00 1E 02 1C 02 1C + 02 00 02 0E 00 20 02 E3 + 00 07 00 0C 03 50 03 64 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 29 01 00 00 00 00 03 F0 A5 A5 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 23 /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 09 10 B4 24 FB /* FFC Setting; 0x09 : Enable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame */ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-113mhz-osc-dsi-on-command = [ + /* DSC Setting */ + 29 01 00 00 00 00 03 F0 5A 5A + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2340) */ + 11 00 00 89 30 80 09 24 + 04 38 00 1E 02 1C 02 1C + 02 00 02 0E 00 20 02 E3 + 00 07 00 0C 03 50 03 64 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 29 01 00 00 00 00 03 F0 A5 A5 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 23 /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 08 10 B4 24 FB /* FFC Setting; 0x08 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame */ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-113mhz-osc-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-off-command=[ + 05 01 00 00 0A 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-panel-hbm-brightness-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 53 /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM Mode ON */ + 15 01 00 00 11 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-brightness-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 53 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 11 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-hbm-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-3 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-4 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 14 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 29 01 00 00 0D 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 11 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + ]; + qcom,mdss-dsi-panel-serial-num-pre-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 37 01 00 00 05 00 02 10 00 + ]; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 00 + ]; + qcom,mdss-dsi-panel-code-info-command = [ + 06 01 00 00 00 00 01 DA 00 + ]; + qcom,mdss-dsi-panel-stage-info-command = [ + 06 01 00 00 00 00 01 DB 00 + ]; + qcom,mdss-dsi-panel-production-info-command = [ + 06 01 00 00 00 00 01 DC 00 + ]; + qcom,mdss-dsi-panel-serial-num-post-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-aod-off-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 29 01 00 00 00 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command = [ + /*Level2 key Enable*/ + 29 01 00 00 00 00 03 F0 5A 5A + //07 01 00 00 00 00 01 01 + //29 00 00 00 00 00 05 2A 00 00 05 9F + //29 00 00 00 00 00 05 2B 00 00 0C 2F + /*OTP key Enable*/ + 29 01 00 00 00 00 03 F1 F1 A2 + 29 01 00 00 00 00 0D C1 00 00 00 06 00 00 00 00 00 00 00 05 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0C C1 00 00 00 01 40 02 00 00 00 00 10 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0E C1 00 00 00 6B 00 00 00 0A 00 00 00 05 01 + 15 01 00 00 00 00 02 B0 07 + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command = [ + 15 01 00 00 00 00 02 C0 03 + 15 01 00 00 00 00 02 B0 08 + ]; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command = [ + /*13th Parameter : 1byte Read value*/ + 06 01 00 00 00 00 02 FB 00 + ]; + qcom,mdss-dsi-panel-level2-key-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command = [ + 37 01 00 00 05 00 02 87 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command = [ + 06 01 00 00 00 00 02 C8 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command = [ + 37 01 00 00 00 00 02 B4 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command = [ + 06 01 00 00 00 00 02 C9 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command = [ + 37 01 00 00 00 00 02 2F 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command = [ + 06 01 00 00 00 00 02 B3 00 + ]; + qcom,mdss-dsi-panel-level2-key-disable-command = [ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-night-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 39 01 00 0A 00 00 16 67 BB 0E 04 3E D8 12 09 05 EA 41 E2 D0 E5 09 F6 D0 D0 11 F8 FE DC + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-p3-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 E0 03 00 11 E2 01 0D 08 E5 1A FA FC E5 09 F6 EA F3 01 FE FF F7 + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 03 67 00 01 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 81 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 FF 6D + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-disable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 A1 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 28 28 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-srgb-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command = [ + 15 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 0A 00 02 B0 02 + 29 01 00 00 0A 00 16 67 FF 05 00 0B EB 00 07 00 FF 14 F8 EA F0 03 F5 DE F5 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-seed-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 D3 03 00 11 E4 01 0B 06 F0 1A FA FC E5 09 F6 EA F3 01 FC FF EA + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-seed-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-customer-p3-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-customer-srgb-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-loading-effect-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-loading-effect-disable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-p3-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-night-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-dci-p3-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-aod-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-pre-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-code-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-state-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-production-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-post-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-brightness-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-brightness-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-3-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-4-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-disable-command-state = "dsi_lp_mode"; + qcom,panel-roi-alignment=<540 60 540 60 540 60>; + qcom,compression-mode = "dsc"; + qcom,lm-split = <540 540>; + qcom,mdss-dsc-encoders = <2>; + qcom,mdss-dsc-slice-height = <60>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@3{ + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,mdss-mdp-transfer-time-us = <8000>; //for 90fps + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3120>; + qcom,mdss-dsi-h-front-porch = <16>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <4>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 00]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-id1-command = [06 01 00 00 00 00 02 0A 00]; + qcom,mdss-dsi-panel-id2-command = [06 01 00 00 00 00 02 0E 00]; + qcom,mdss-dsi-panel-id3-command = [06 01 00 00 00 00 02 0F 00]; + qcom,mdss-dsi-panel-id4-command = [06 01 00 00 00 00 02 C4 00]; + qcom,mdss-dsi-panel-id5-command = [06 01 00 00 00 00 02 E7 00]; + qcom,mdss-dsi-panel-id6-command = [06 01 00 00 00 00 02 EA 00]; + qcom,mdss-dsi-panel-id7-command = [06 01 00 00 00 00 02 FB 00]; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 F0 5A 5A]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-panel-read-esd-registed-longread-command = [ + 37 01 00 00 05 00 02 22 00 + ]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-esd-registed-longread-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-timing-switch-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + //29 01 00 00 00 00 03 9F A5 A5 + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 29 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + //29 01 00 00 00 00 03 9F 5A 5A + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-on-command = [ + /* DSC Setting */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 39 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 39 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 09 10 B4 24 FB /* FFC Setting; 0x09 : Enable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame*/ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-113mhz-osc-dsi-on-command = [ + /* DSC Setting */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 39 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 39 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 08 10 B4 24 FB /* FFC Setting; 0x08 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame*/ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-113mhz-osc-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-off-command=[ + 05 01 00 00 0A 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-panel-hbm-brightness-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 53 /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM Mode ON */ + 15 01 00 00 0C 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-brightness-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 53 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 0C 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-hbm-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-3 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-4 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 10 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 29 01 00 00 0C 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-serial-num-pre-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 37 01 00 00 05 00 02 10 00 + ]; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 00 + ]; + qcom,mdss-dsi-panel-code-info-command = [ + 06 01 00 00 00 00 01 DA 00 + ]; + qcom,mdss-dsi-panel-stage-info-command = [ + 06 01 00 00 00 00 01 DB 00 + ]; + qcom,mdss-dsi-panel-production-info-command = [ + 06 01 00 00 00 00 01 DC 00 + ]; + qcom,mdss-dsi-panel-serial-num-post-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-aod-off-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 29 01 00 00 00 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command = [ + /*Level2 key Enable*/ + 29 01 00 00 00 00 03 F0 5A 5A + //07 01 00 00 00 00 01 01 + //29 00 00 00 00 00 05 2A 00 00 05 9F + //29 00 00 00 00 00 05 2B 00 00 0C 2F + /*OTP key Enable*/ + 29 01 00 00 00 00 03 F1 F1 A2 + 29 01 00 00 00 00 0D C1 00 00 00 06 00 00 00 00 00 00 00 05 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0C C1 00 00 00 01 40 02 00 00 00 00 10 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0E C1 00 00 00 6B 00 00 00 0A 00 00 00 05 01 + 15 01 00 00 00 00 02 B0 07 + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command = [ + 15 01 00 00 00 00 02 C0 03 + 15 01 00 00 00 00 02 B0 08 + ]; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command = [ + /*13th Parameter : 1byte Read value*/ + 06 01 00 00 00 00 02 FB 00 + ]; + qcom,mdss-dsi-panel-level2-key-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command = [ + 37 01 00 00 00 00 02 87 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command = [ + 06 01 00 00 00 00 02 C8 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command = [ + 37 01 00 00 00 00 02 B4 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command = [ + 06 01 00 00 00 00 02 C9 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command = [ + 37 01 00 00 00 00 02 2F 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command = [ + 06 01 00 00 00 00 02 B3 00 + ]; + qcom,mdss-dsi-panel-level2-key-disable-command = [ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-night-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 39 01 00 0A 00 00 16 67 BB 0E 04 3E D8 12 09 05 EA 41 E2 D0 E5 09 F6 D0 D0 11 F8 FE DC + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-p3-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 E0 03 00 11 E2 01 0D 08 E5 1A FA FC E5 09 F6 EA F3 01 FE FF F7 + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 03 67 00 01 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 81 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 FF 6D + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-loading-effect-disable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 A1 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 28 28 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-srgb-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 10 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command = [ + 15 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 0A 00 02 B0 02 + 29 01 00 00 0A 00 16 67 FF 05 00 0B EB 00 07 00 FF 14 F8 EA F0 03 F5 DE F5 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-seed-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 D3 03 00 11 E4 01 0B 06 F0 1A FA FC E5 09 F6 EA F3 01 FC FF EA + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-seed-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-customer-p3-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-customer-srgb-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-loading-effect-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-loading-effect-disable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-p3-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-night-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-dci-p3-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-aod-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-pre-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-code-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-state-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-production-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-post-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-brightness-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-brightness-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-3-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-4-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-disable-command-state = "dsi_lp_mode"; + qcom,panel-roi-alignment=<720 65 720 65 720 65>; + qcom,compression-mode = "dsc"; + qcom,lm-split = <720 720>; + qcom,mdss-dsc-encoders = <2>; + qcom,mdss-dsc-slice-height = <65>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + }; + }; +}; + +&dsi_samsung_oneplus_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; + qcom,platform-reset-gpio-tmo = <&tlmm 78 0>; + qcom,platform-poc-gpio = <&tlmm 130 0>; + qcom,tp1v8-gpio = <&tlmm 119 0>; +}; + +&soc { + dsi_samsung_oneplus_dsc_cmd_display { + qcom,dsi-display-active; + }; +}; + +&dsi_samsung_oneplus_dsc_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { /* wqhd 60hz */ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment=<720 65 720 65 720 65>; + }; + timing@1 { /* fhd 90hz */ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment=<540 60 540 60 540 60>; + }; + timing@2 { /* fhd 60hz */ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment=<540 60 540 60 540 60>; + }; + timing@3 { /* wqhd 90hz */ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 25 09 0A 06 02 04 00 1E 1A]; + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment=<720 65 720 65 720 65>; + }; + }; +}; + + diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-samsung_s6e3fc2x01.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-samsung_s6e3fc2x01.dtsi new file mode 100644 index 000000000000..bd7245490744 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/dsi-panel-samsung_s6e3fc2x01.dtsi @@ -0,0 +1,435 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_samsung_s6e3fc2x01_cmd: qcom,mdss_dsi_samsung_s6e3fc2x01_cmd { + qcom,mdss-dsi-panel-name = "samsung s6e3fc2x01 cmd mode dsi panel"; + qcom,mdss-dsi-panel-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-version = "S6E3FC2X01"; + qcom,mdss-dsi-backlight-version = "SAMSUNG"; + qcom,mdss-dsi-backlight-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-reset-sequence = <1 7>, <0 1>, <1 5>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <145>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + //qcom,mdss-dsi-te-check-enable; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 08]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-high-brightness-panel; + qcom,mdss-dsi-acl-cmd-index = <0>; + qcom,mdss-dsi-acl-mode-index = <1>; + qcom,mdss-bl-high2bit; + //qcom,mdss-dsi-panel-status-check-mode = "te_signal_check"; + qcom,mdss-dsi-panel-seria-num-year-index = <12>; + qcom,mdss-dsi-panel-seria-num-mon-index = <12>; + qcom,mdss-dsi-panel-seria-num-day-index = <13>; + qcom,mdss-dsi-panel-seria-num-hour-index = <14>; + qcom,mdss-dsi-panel-seria-num-min-index = <15>; + qcom,mdss-dsi-panel-seria-num-sec-index = <16>; + qcom,ulps-enabled; + qcom,mdss-brightness-max-level = <1023>; + /* HDR Setting */ + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15635 16450 34000 16000 13250 34500 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <8000000>; + qcom,mdss-dsi-panel-average-brightness = <2000000>; + qcom,mdss-dsi-panel-blackness-level = <5>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <72>; + qcom,mdss-dsi-h-back-porch = <36>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <32>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <1037000000>;// 518.5MHZ + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 05 00 02 11 00 + 39 01 00 00 00 00 03 9F 5A 5A + /*FD setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 01 + 15 01 00 00 00 00 02 CD 01 + 39 01 00 00 0F 00 03 F0 A5 A5 + /*TE ON*/ + 39 01 00 00 00 00 03 9F A5 A5 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 9F 5A 5A + /*MIC Setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 08 EB 17 41 92 0E 10 82 5A + 39 01 00 00 00 00 03 F0 A5 A5 + /*CASET/PASET*/ + 39 01 00 00 00 00 05 2A 00 00 04 37 + 39 01 00 00 00 00 05 2B 00 00 09 23 + /*TSP H_sync Setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 09 + 39 01 00 00 00 00 03 E8 10 30 + 39 01 00 00 00 00 03 F0 A5 A5 + /*Dimming Setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B7 01 + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 00 00 02 B7 12 + 39 01 00 00 00 00 03 F0 A5 A5 + /*ESD improvement Setting*/ + 39 01 00 00 00 00 03 FC 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 02 E3 88 + 39 01 00 00 00 00 02 B0 07 + 39 01 00 00 00 00 02 ED 67 + 39 01 00 00 00 00 03 FC A5 A5 + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 F0 A5 A5 + /*ACL off*/ + 39 01 00 00 01 00 02 55 00 + /*SEED OFF*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 B1 00 01 + 39 01 00 00 00 00 03 F0 A5 A5 + /*SEED TCS OFF*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 B3 00 C1 + 39 01 00 00 00 00 03 F0 A5 A5 + /*Display on*/ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 00 00 02 29 00 + 39 01 00 00 00 00 03 9F 5A 5A + ]; + qcom,mdss-dsi-off-command = [ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 0A 00 01 28 + 05 01 00 00 00 00 01 10 + 39 01 00 00 00 00 03 9F 5A 5A + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 F4 01 + 39 01 00 00 96 00 03 F0 A5 A5 + ]; + //qcom,mdss-dsi-post-on-backlight=[ + // 39 01 00 00 00 00 03 9F A5 A5 + // 05 01 00 00 00 00 01 29 + // 39 01 00 00 00 00 03 9F 5A 5A + //]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + /**************************************************************/ + qcom,mdss-dsi-panel-hbm-brightness-on-command = [ + /*HBM ON */ + 39 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 53 E0 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-brightness-off-command = [ + /* DLY ON */ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 04 B7 00 01 5B + 39 00 00 00 00 00 03 F0 A5 A5 + + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /*ELVSS OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 08 + 15 00 00 00 00 00 02 B7 12 + 39 01 00 00 10 00 03 F0 A5 A5 + /*DLY OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 04 B7 00 01 5B + 39 00 00 00 00 00 03 F0 A5 A5 + /*HBM ON */ + 15 00 00 00 00 00 02 53 E0 + 39 01 00 00 0E 00 03 51 03 FF + /*HBM 670nit*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 BD 00 00 + 39 00 00 00 00 00 03 F0 A5 A5 + /*DLY OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 04 B7 00 01 53 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /*HBM 670nit off*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 BD 00 02 + 39 00 00 00 00 00 03 F0 A5 A5 + /*HBM off */ + 15 01 00 00 00 00 02 53 20 + ]; + qcom,mdss-dsi-panel-hbm-max-brightness-command-on = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B7 7F + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 80 00 02 B7 92 + 39 01 00 00 40 00 02 53 E8 + 39 01 00 00 80 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 51 03 FF + ]; + qcom,mdss-dsi-panel-hbm-max-brightness-command-off = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 40 00 02 B7 7F + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 40 00 02 B7 92 + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 10 00 02 53 28 + ]; + qcom,mdss-dsi-panel-hbm-brightness-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-brightness-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-max-brightness-command-on-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-max-brightness-command-off-state = "dsi_lp_mode"; + qcom,mdss-dsi-hbm-off-command-state = "dsi_hs_mode"; + + qcom,mdss-dsi-panel-aod-on-command-1 = [ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 0A 00 01 28 + 05 01 00 00 78 00 01 10 + 05 01 00 00 05 00 01 11 + 39 01 00 00 00 00 03 9F 5A 5A + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 01 + 15 01 00 00 64 00 02 CD 02 + 15 01 00 00 00 00 02 53 23 + 15 01 00 00 00 00 02 B0 A5 + 15 01 00 00 00 00 02 C7 00 + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 00 00 01 29 + 39 01 00 00 00 00 03 9F 5A 5A + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + + ]; + + qcom,mdss-dsi-panel-aod-off-command = [ + /*ELVSS OFF*/ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 08 + /*DLY OFF*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 04 B7 00 01 5B + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 01 + 15 01 00 00 00 00 02 CD 01 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 F0 A5 A5 + /*DLY ON*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 04 B7 00 01 53 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + + ]; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + /*ELVSS OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 08 + 15 00 00 00 00 00 02 B7 12 + 39 00 00 00 00 00 03 F0 A5 A5 + /*DL0 OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 04 B7 00 01 5B + 39 00 00 00 00 00 03 F0 A5 A5 + /*HB0 ON */ + 15 00 00 00 00 00 02 53 E0 + 39 01 00 00 00 00 03 51 03 FF + /*HB0 670nit*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 BD 00 00 + 39 01 00 00 00 00 03 F0 A5 A5 + /*DL0 OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 04 B7 00 01 53 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + /*HBM 670nit off*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 BD 00 02 + 39 00 00 00 00 00 03 F0 A5 A5 + /*HBM off */ + 15 01 00 00 00 00 02 53 20 + ]; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command = [ + + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 CE 01 02 1D E3 00 07 0D E9 28 FD F0 D3 0A E2 EA EA 01 FF FF F2 + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + + ]; + qcom,mdss-dsi-panel-display-p3-mode-on-command = [ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 CE 01 02 1D E3 00 07 0D E9 28 FD F0 D3 0A E2 EA EA 01 FF FF F2 + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command = [ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + + ]; + qcom,mdss-dsi-customer-srgb-enable-command = [ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 CE 01 02 1D E3 00 07 0D E9 28 FD F0 D3 0A E2 EA EA 01 FF FF F2 + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command = [ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF F2 + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-customer-srgb-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-p3-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-aod-mode-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 + ]; + + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0E 08]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id-command = [06 01 00 01 05 00 02 DC 08]; + qcom,mdss-dsi-panel-id-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id1-command = [06 01 00 01 05 00 02 0A 08]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command = [06 01 00 01 05 00 02 0E 08]; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command = [06 01 00 01 05 00 02 E0 08]; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command = [06 01 00 01 05 00 02 0F 08]; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command = [06 01 00 01 05 00 02 E3 08]; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command = [06 01 00 01 05 00 02 E5 08]; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command = [06 01 00 01 05 00 02 FB 08]; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-level1-command = [15 01 00 00 00 00 02 B0 08]; + qcom,mdss-dsi-panel-hbm-level1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-read-command = [06 01 00 01 05 00 02 B7 08]; + qcom,mdss-dsi-panel-hbm-read-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 FC 5A 5A]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 FC A5 A5]; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + }; + }; + }; +}; + +&dsi_samsung_s6e3fc2x01_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; + qcom,platform-poc-gpio = <&tlmm 130 0>; + qcom,tp1v8-gpio = <&tlmm 119 0>; +}; + +&soc { + dsi_samsung_s6e3fc2x01_cmd_display { + qcom,dsi-display-active; + }; +}; + +&dsi_samsung_s6e3fc2x01_cmd { + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 25 23 + 09 09 06 03 04 00 1C 19]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + + diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-samsung_sofef00_m_video.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-samsung_sofef00_m_video.dtsi new file mode 100644 index 000000000000..15a81d8158d4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/dsi-panel-samsung_sofef00_m_video.dtsi @@ -0,0 +1,103 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_samsung_sofef00_m_video: qcom,mdss_dsi_samsung_sofef00_m_video { + qcom,mdss-dsi-panel-name = + "samsung sofef00_m video mode dsi panel"; + qcom,mdss-dsi-panel-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-version = "SOFEF00_M"; + qcom,mdss-dsi-backlight-version = "SAMSUNG"; + qcom,mdss-dsi-backlight-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-reset-sequence = <1 5>, <0 2>, <1 12>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <145>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-high-brightness-panel; + qcom,mdss-bl-high2bit; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2280>; + qcom,mdss-dsi-h-front-porch = <112>; + qcom,mdss-dsi-h-back-porch = <36>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <12>; + qcom,mdss-dsi-v-front-porch = <36>; + qcom,mdss-dsi-v-pulse-width = <8>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + 05 01 00 00 0A 00 02 11 00 + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 F0 A5 A5 + 15 01 00 00 00 00 02 53 20 + 15 01 00 00 00 00 02 55 00 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 28 00 02 28 00 + 05 01 00 00 A0 00 02 10 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; + +&dsi_samsung_sofef00_m_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; + qcom,platform-reset-gpio-tmo = <&tlmm 78 0>; +}; + +&soc { + dsi_samsung_sofef00_m_video_display { + qcom,dsi-display-active; + }; +}; + +&dsi_samsung_sofef00_m_video { + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 20 07 07 0c 12 06 + 08 06 03 04 00]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-sharp-qsync-fhd-cmd.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-sharp-qsync-fhd-cmd.dtsi deleted file mode 100644 index 3d02299dacfb..000000000000 --- a/arch/arm64/boot/dts/qcom/dsi-panel-sharp-qsync-fhd-cmd.dtsi +++ /dev/null @@ -1,367 +0,0 @@ -/* Copyright (c) 2019, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -&mdss_mdp { - dsi_sharp_qsync_fhd_cmd: qcom,mdss_dsi_sharp_qsync_fhd_cmd { - qcom,mdss-dsi-panel-name = "Sharp fhd cmd mode qsync dsi panel"; - qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-traffic-mode = "burst_mode"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - qcom,mdss-pan-physical-width-dimension = <74>; - qcom,mdss-pan-physical-height-dimension = <134>; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-wr-mem-start = <0x2c>; - qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-te-pin; - qcom,mdss-dsi-tx-eot-append; - qcom,adjust-timer-wakeup-ms = <1>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750 - 15800 13250 34450 7500 3000>; - qcom,mdss-dsi-panel-peak-brightness = <6450000>; - qcom,mdss-dsi-panel-blackness-level = <4961>; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <540>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <20>; - qcom,mdss-dsi-h-back-porch = <12>; - qcom,mdss-dsi-h-pulse-width = <8>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <14>; - qcom,mdss-dsi-v-front-porch = <16>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-jitter = <0x3 0x1>; - qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 c0 85 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 - 00 02 0e 00 bb 00 07 0d b7 0c b7 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 16 0a - 39 01 00 00 00 00 02 17 30 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 01 - ]; - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 02 ff d0 - 39 01 00 00 00 00 02 75 40 - 39 01 00 00 10 00 02 f1 40 - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 10 00 06 2c 01 02 04 08 10 - 39 01 00 00 00 00 02 ff d0 - 39 01 00 00 00 00 02 75 00 - 39 01 00 00 10 00 02 f1 00 - /* Initial Setting */ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 ba 03 - 39 01 00 00 00 00 02 bc 08 - 39 01 00 00 00 00 02 c0 85 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 - 00 02 0e 00 bb 00 07 0d b7 0c b7 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 d5 00 - 39 01 00 00 00 00 02 d6 00 - 39 01 00 00 00 00 02 de 00 - 39 01 00 00 00 00 02 e1 00 - 39 01 00 00 00 00 02 e5 01 - 39 01 00 00 00 00 02 bb 10 - 39 01 00 00 00 00 02 f6 70 - 39 01 00 00 00 00 02 f7 80 - 39 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 02 44 00 - 39 01 00 00 00 00 02 ff 20 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 87 02 - 39 01 00 00 00 00 02 5d 00 - 39 01 00 00 00 00 02 5e 14 - 39 01 00 00 00 00 02 5f eb - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 14 00 - 39 01 00 00 00 00 02 15 10 - 39 01 00 00 00 00 02 16 0a - 39 01 00 00 00 00 02 17 30 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 01 - 39 01 00 00 00 00 02 40 00 - 39 01 00 00 00 00 02 ff 28 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 91 02 - 39 01 00 00 00 00 02 ff e0 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 48 81 - 39 01 00 00 00 00 02 8e 09 - 39 01 00 00 00 00 02 ff f0 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 33 20 - 39 01 00 00 00 00 02 34 35 - 39 01 00 00 00 00 02 ff 10 - 05 01 00 00 78 00 01 11 - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = [ - 15 01 00 00 00 00 02 ff 10 - 15 01 00 00 00 00 02 bc 00 - 05 01 00 00 10 00 01 28 - 05 01 00 00 32 00 01 10 - ]; - qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <8>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@1 { - qcom,mdss-dsi-panel-width = <540>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <20>; - qcom,mdss-dsi-h-back-porch = <12>; - qcom,mdss-dsi-h-pulse-width = <8>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <14>; - qcom,mdss-dsi-v-front-porch = <16>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-panel-framerate = <90>; - qcom,mdss-dsi-panel-jitter = <0x3 0x1>; - qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 c0 85 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 - 00 02 0e 00 bb 00 07 0d b7 0c b7 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 16 03 - 39 01 00 00 00 00 02 17 70 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 02 - ]; - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 02 ff d0 - 39 01 00 00 00 00 02 75 40 - 39 01 00 00 10 00 02 f1 40 - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 10 00 06 2c 01 02 04 08 10 - 39 01 00 00 00 00 02 ff d0 - 39 01 00 00 00 00 02 75 00 - 39 01 00 00 10 00 02 f1 00 - /* Initial Setting */ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 ba 03 - 39 01 00 00 00 00 02 bc 08 - 39 01 00 00 00 00 02 c0 85 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 - 00 02 0e 00 bb 00 07 0d b7 0c b7 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 d5 00 - 39 01 00 00 00 00 02 d6 00 - 39 01 00 00 00 00 02 de 00 - 39 01 00 00 00 00 02 e1 00 - 39 01 00 00 00 00 02 e5 01 - 39 01 00 00 00 00 02 bb 10 - 39 01 00 00 00 00 02 f6 70 - 39 01 00 00 00 00 02 f7 80 - 39 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 02 44 00 - 39 01 00 00 00 00 02 ff 20 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 87 02 - 39 01 00 00 00 00 02 5d 00 - 39 01 00 00 00 00 02 5e 14 - 39 01 00 00 00 00 02 5f eb - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 14 00 - 39 01 00 00 00 00 02 15 10 - 39 01 00 00 00 00 02 16 03 - 39 01 00 00 00 00 02 17 70 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 01 - 39 01 00 00 00 00 02 40 00 - 39 01 00 00 00 00 02 ff 28 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 91 02 - 39 01 00 00 00 00 02 ff e0 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 48 81 - 39 01 00 00 00 00 02 8e 09 - 39 01 00 00 00 00 02 ff f0 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 33 20 - 39 01 00 00 00 00 02 34 35 - 39 01 00 00 00 00 02 ff 10 - 05 01 00 00 78 00 01 11 - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = [ - 15 01 00 00 00 00 02 ff 10 - 15 01 00 00 00 00 02 bc 00 - 05 01 00 00 10 00 01 28 - 05 01 00 00 32 00 01 10 - ]; - qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <8>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@2 { - qcom,mdss-dsi-panel-width = <540>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <20>; - qcom,mdss-dsi-h-back-porch = <12>; - qcom,mdss-dsi-h-pulse-width = <8>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <14>; - qcom,mdss-dsi-v-front-porch = <16>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-panel-framerate = <120>; - qcom,mdss-dsi-panel-jitter = <0x3 0x1>; - qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 c0 85 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 - 00 02 0e 00 bb 00 07 0d b7 0c b7 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 16 00 - 39 01 00 00 00 00 02 17 10 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 03 - ]; - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 02 ff d0 - 39 01 00 00 00 00 02 75 40 - 39 01 00 00 10 00 02 f1 40 - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 10 00 06 2c 01 02 04 08 10 - 39 01 00 00 00 00 02 ff d0 - 39 01 00 00 00 00 02 75 00 - 39 01 00 00 10 00 02 f1 00 - /* Initial Setting */ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 ba 03 - 39 01 00 00 00 00 02 bc 08 - 39 01 00 00 00 00 02 c0 85 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 - 00 02 0e 00 bb 00 07 0d b7 0c b7 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 d5 00 - 39 01 00 00 00 00 02 d6 00 - 39 01 00 00 00 00 02 de 00 - 39 01 00 00 00 00 02 e1 00 - 39 01 00 00 00 00 02 e5 01 - 39 01 00 00 00 00 02 bb 10 - 39 01 00 00 00 00 02 f6 70 - 39 01 00 00 00 00 02 f7 80 - 39 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 02 44 00 - 39 01 00 00 00 00 02 ff 20 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 87 02 - 39 01 00 00 00 00 02 5d 00 - 39 01 00 00 00 00 02 5e 14 - 39 01 00 00 00 00 02 5f eb - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 14 00 - 39 01 00 00 00 00 02 15 10 - 39 01 00 00 00 00 02 16 00 - 39 01 00 00 00 00 02 17 10 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 01 - 39 01 00 00 00 00 02 40 00 - 39 01 00 00 00 00 02 ff 28 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 91 02 - 39 01 00 00 00 00 02 ff e0 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 48 81 - 39 01 00 00 00 00 02 8e 09 - 39 01 00 00 00 00 02 ff f0 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 33 20 - 39 01 00 00 00 00 02 34 35 - 39 01 00 00 00 00 02 ff 10 - 05 01 00 00 78 00 01 11 - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = [ - 15 01 00 00 00 00 02 ff 10 - 15 01 00 00 00 00 02 bc 00 - 05 01 00 00 10 00 01 28 - 05 01 00 00 32 00 01 10 - ]; - qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <8>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-sharp-qsync-fhd-video.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-sharp-qsync-fhd-video.dtsi deleted file mode 100644 index 0d3f1bcded7b..000000000000 --- a/arch/arm64/boot/dts/qcom/dsi-panel-sharp-qsync-fhd-video.dtsi +++ /dev/null @@ -1,128 +0,0 @@ -/* Copyright (c) 2019, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -&mdss_mdp { - dsi_sharp_qsync_fhd_video: qcom,mdss_dsi_sharp_qsync_fhd_video { - qcom,mdss-dsi-panel-name = - "Sharp fhd video mode qsync dsi panel"; - qcom,mdss-dsi-panel-type = "dsi_video_mode"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-traffic-mode = "burst_mode"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - qcom,mdss-pan-physical-width-dimension = <74>; - qcom,mdss-pan-physical-height-dimension = <134>; - qcom,mdss-dsi-tx-eot-append; - qcom,adjust-timer-wakeup-ms = <1>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750 - 15800 13250 34450 7500 3000>; - qcom,mdss-dsi-panel-peak-brightness = <6450000>; - qcom,mdss-dsi-panel-blackness-level = <4961>; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <540>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <124>; - qcom,mdss-dsi-h-back-porch = <20>; - qcom,mdss-dsi-h-pulse-width = <20>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <14>; - qcom,mdss-dsi-v-front-porch = <1968>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 02 ff d0 - 39 01 00 00 00 00 02 75 40 - 39 01 00 00 10 00 02 f1 40 - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 10 00 06 2c 01 02 04 08 10 - 39 01 00 00 00 00 02 ff d0 - 39 01 00 00 00 00 02 75 00 - 39 01 00 00 10 00 02 f1 00 - /* Initial Setting */ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 ba 03 - 39 01 00 00 00 00 02 bc 08 - 39 01 00 00 00 00 02 c0 85 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 - 00 02 0e 00 bb 00 07 0d b7 0c b7 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 d5 00 - 39 01 00 00 00 00 02 d6 00 - 39 01 00 00 00 00 02 de 00 - 39 01 00 00 00 00 02 e1 00 - 39 01 00 00 00 00 02 e5 01 - 39 01 00 00 00 00 02 bb 03 - 39 01 00 00 00 00 02 f6 70 - 39 01 00 00 00 00 02 f7 80 - 39 01 00 00 00 00 05 be 00 10 00 10 - 39 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 02 44 00 - 39 01 00 00 00 00 02 ff 20 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 87 02 - 39 01 00 00 00 00 02 5d 00 - 39 01 00 00 00 00 02 5e 14 - 39 01 00 00 00 00 02 5f eb - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 01 - 39 01 00 00 00 00 02 40 00 - 39 01 00 00 00 00 02 ff 28 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 91 02 - 39 01 00 00 00 00 02 ff e0 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 48 81 - 39 01 00 00 00 00 02 8e 09 - 39 01 00 00 00 00 02 ff f0 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 33 20 - 39 01 00 00 00 00 02 34 35 - 39 01 00 00 00 00 02 ff 10 - 05 01 00 00 78 00 01 11 - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = [ - 15 01 00 00 00 00 02 ff 10 - 15 01 00 00 00 00 02 bc 00 - 05 01 00 00 10 00 01 28 - 05 01 00 00 32 00 01 10 - ]; - qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <8>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - }; - }; -}; - diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-sharp-qsync-wqhd-cmd.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-sharp-qsync-wqhd-cmd.dtsi deleted file mode 100644 index ba8c84dafe0c..000000000000 --- a/arch/arm64/boot/dts/qcom/dsi-panel-sharp-qsync-wqhd-cmd.dtsi +++ /dev/null @@ -1,470 +0,0 @@ -/* Copyright (c) 2019, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -&mdss_mdp { - dsi_sharp_qsync_wqhd_cmd: qcom,mdss_dsi_sharp_qsync_wqhd_cmd { - qcom,mdss-dsi-panel-name = "Sharp 2k cmd mode qsync dsi panel"; - qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-traffic-mode = "burst_mode"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - qcom,mdss-pan-physical-width-dimension = <74>; - qcom,mdss-pan-physical-height-dimension = <134>; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-wr-mem-start = <0x2c>; - qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-te-pin; - qcom,mdss-dsi-tx-eot-append; - qcom,adjust-timer-wakeup-ms = <1>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750 - 15800 13250 34450 7500 3000>; - qcom,mdss-dsi-panel-peak-brightness = <6450000>; - qcom,mdss-dsi-panel-blackness-level = <4961>; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <20>; - qcom,mdss-dsi-h-back-porch = <12>; - qcom,mdss-dsi-h-pulse-width = <8>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <14>; - qcom,mdss-dsi-v-front-porch = <16>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-jitter = <0x3 0x1>; - qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 c0 83 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 - 00 02 68 00 d5 00 0a 0d b7 09 89 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 16 0a - 39 01 00 00 00 00 02 17 30 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 01 - ]; - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 02 ff d0 - 39 01 00 00 00 00 02 75 40 - 39 01 00 00 10 00 02 f1 40 - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 10 00 06 2c 01 02 04 08 10 - 39 01 00 00 00 00 02 ff d0 - 39 01 00 00 00 00 02 75 00 - 39 01 00 00 10 00 02 f1 00 - /* Initial Setting */ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 ba 03 - 39 01 00 00 00 00 02 bc 08 - 39 01 00 00 00 00 02 c0 83 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 - 00 02 68 00 d5 00 0a 0d b7 09 89 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 d5 00 - 39 01 00 00 00 00 02 d6 00 - 39 01 00 00 00 00 02 de 00 - 39 01 00 00 00 00 02 e1 00 - 39 01 00 00 00 00 02 e5 01 - 39 01 00 00 00 00 02 bb 10 - 39 01 00 00 00 00 02 f6 70 - 39 01 00 00 00 00 02 f7 80 - 39 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 02 44 00 - 39 01 00 00 00 00 02 ff 20 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 87 02 - 39 01 00 00 00 00 02 5d 00 - 39 01 00 00 00 00 02 5e 14 - 39 01 00 00 00 00 02 5f eb - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 14 00 - 39 01 00 00 00 00 02 15 10 - 39 01 00 00 00 00 02 16 0a - 39 01 00 00 00 00 02 17 30 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 01 - 39 01 00 00 00 00 02 40 00 - 39 01 00 00 00 00 02 ff 28 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 91 02 - 39 01 00 00 00 00 02 ff e0 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 48 81 - 39 01 00 00 00 00 02 8e 09 - 39 01 00 00 00 00 02 ff f0 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 33 20 - 39 01 00 00 00 00 02 34 35 - 39 01 00 00 00 00 02 ff 10 - 05 01 00 00 78 00 01 11 - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = [ - 15 01 00 00 00 00 02 ff 10 - 15 01 00 00 00 00 02 bc 00 - 05 01 00 00 10 00 01 28 - 05 01 00 00 32 00 01 10 - ]; - qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <8>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@1 { - qcom,mdss-dsi-panel-width = <540>; - qcom,mdss-dsi-panel-height = <1920>; - qcom,mdss-dsi-h-front-porch = <20>; - qcom,mdss-dsi-h-back-porch = <12>; - qcom,mdss-dsi-h-pulse-width = <8>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <14>; - qcom,mdss-dsi-v-front-porch = <16>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-jitter = <0x3 0x1>; - qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 c0 85 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 - 00 02 0e 00 bb 00 07 0d b7 0c b7 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 16 0a - 39 01 00 00 00 00 02 17 30 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 01 - ]; - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 02 ff d0 - 39 01 00 00 00 00 02 75 40 - 39 01 00 00 10 00 02 f1 40 - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 10 00 06 2c 01 02 04 08 10 - 39 01 00 00 00 00 02 ff d0 - 39 01 00 00 00 00 02 75 00 - 39 01 00 00 10 00 02 f1 00 - /* Initial Setting */ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 ba 03 - 39 01 00 00 00 00 02 bc 08 - 39 01 00 00 00 00 02 c0 85 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 - 00 02 0e 00 bb 00 07 0d b7 0c b7 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 d5 00 - 39 01 00 00 00 00 02 d6 00 - 39 01 00 00 00 00 02 de 00 - 39 01 00 00 00 00 02 e1 00 - 39 01 00 00 00 00 02 e5 01 - 39 01 00 00 00 00 02 bb 10 - 39 01 00 00 00 00 02 f6 70 - 39 01 00 00 00 00 02 f7 80 - 39 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 02 44 00 - 39 01 00 00 00 00 02 ff 20 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 87 02 - 39 01 00 00 00 00 02 5d 00 - 39 01 00 00 00 00 02 5e 14 - 39 01 00 00 00 00 02 5f eb - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 14 00 - 39 01 00 00 00 00 02 15 10 - 39 01 00 00 00 00 02 16 0a - 39 01 00 00 00 00 02 17 30 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 01 - 39 01 00 00 00 00 02 40 00 - 39 01 00 00 00 00 02 ff 28 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 91 02 - 39 01 00 00 00 00 02 ff e0 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 48 81 - 39 01 00 00 00 00 02 8e 09 - 39 01 00 00 00 00 02 ff f0 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 33 20 - 39 01 00 00 00 00 02 34 35 - 39 01 00 00 00 00 02 ff 10 - 05 01 00 00 78 00 01 11 - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = [ - 15 01 00 00 00 00 02 ff 10 - 15 01 00 00 00 00 02 bc 00 - 05 01 00 00 10 00 01 28 - 05 01 00 00 32 00 01 10 - ]; - qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; - - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <8>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@2 { - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <20>; - qcom,mdss-dsi-h-back-porch = <12>; - qcom,mdss-dsi-h-pulse-width = <8>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <14>; - qcom,mdss-dsi-v-front-porch = <16>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-panel-framerate = <90>; - qcom,mdss-dsi-panel-jitter = <0x3 0x1>; - qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 c0 83 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 - 00 02 68 00 d5 00 0a 0d b7 09 89 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 16 03 - 39 01 00 00 00 00 02 17 70 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 02 - ]; - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 02 ff d0 - 39 01 00 00 00 00 02 75 40 - 39 01 00 00 10 00 02 f1 40 - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 10 00 06 2c 01 02 04 08 10 - 39 01 00 00 00 00 02 ff d0 - 39 01 00 00 00 00 02 75 00 - 39 01 00 00 10 00 02 f1 00 - /* Initial Setting */ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 ba 03 - 39 01 00 00 00 00 02 bc 08 - 39 01 00 00 00 00 02 c0 83 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 - 00 02 68 00 d5 00 0a 0d b7 09 89 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 d5 00 - 39 01 00 00 00 00 02 d6 00 - 39 01 00 00 00 00 02 de 00 - 39 01 00 00 00 00 02 e1 00 - 39 01 00 00 00 00 02 e5 01 - 39 01 00 00 00 00 02 bb 10 - 39 01 00 00 00 00 02 f6 70 - 39 01 00 00 00 00 02 f7 80 - 39 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 02 44 00 - 39 01 00 00 00 00 02 ff 20 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 87 02 - 39 01 00 00 00 00 02 5d 00 - 39 01 00 00 00 00 02 5e 14 - 39 01 00 00 00 00 02 5f eb - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 14 00 - 39 01 00 00 00 00 02 15 10 - 39 01 00 00 00 00 02 16 03 - 39 01 00 00 00 00 02 17 70 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 01 - 39 01 00 00 00 00 02 40 00 - 39 01 00 00 00 00 02 ff 28 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 91 02 - 39 01 00 00 00 00 02 ff e0 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 48 81 - 39 01 00 00 00 00 02 8e 09 - 39 01 00 00 00 00 02 ff f0 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 33 20 - 39 01 00 00 00 00 02 34 35 - 39 01 00 00 00 00 02 ff 10 - 05 01 00 00 78 00 01 11 - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = [ - 15 01 00 00 00 00 02 ff 10 - 15 01 00 00 00 00 02 bc 00 - 05 01 00 00 10 00 01 28 - 05 01 00 00 32 00 01 10 - ]; - qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <8>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@3 { - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <20>; - qcom,mdss-dsi-h-back-porch = <12>; - qcom,mdss-dsi-h-pulse-width = <8>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <14>; - qcom,mdss-dsi-v-front-porch = <16>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-panel-framerate = <120>; - qcom,mdss-dsi-panel-jitter = <0x3 0x1>; - qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 c0 83 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 - 00 02 68 00 d5 00 0a 0d b7 09 89 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 16 00 - 39 01 00 00 00 00 02 17 10 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 03 - ]; - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 02 ff d0 - 39 01 00 00 00 00 02 75 40 - 39 01 00 00 10 00 02 f1 40 - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 10 00 06 2c 01 02 04 08 10 - 39 01 00 00 00 00 02 ff d0 - 39 01 00 00 00 00 02 75 00 - 39 01 00 00 10 00 02 f1 00 - /* Initial Setting */ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 ba 03 - 39 01 00 00 00 00 02 bc 08 - 39 01 00 00 00 00 02 c0 83 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 - 00 02 68 00 d5 00 0a 0d b7 09 89 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 d5 00 - 39 01 00 00 00 00 02 d6 00 - 39 01 00 00 00 00 02 de 00 - 39 01 00 00 00 00 02 e1 00 - 39 01 00 00 00 00 02 e5 01 - 39 01 00 00 00 00 02 bb 10 - 39 01 00 00 00 00 02 f6 70 - 39 01 00 00 00 00 02 f7 80 - 39 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 02 44 00 - 39 01 00 00 00 00 02 ff 20 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 87 02 - 39 01 00 00 00 00 02 5d 00 - 39 01 00 00 00 00 02 5e 14 - 39 01 00 00 00 00 02 5f eb - 39 01 00 00 00 00 02 ff 24 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 14 00 - 39 01 00 00 00 00 02 15 10 - 39 01 00 00 00 00 02 16 00 - 39 01 00 00 00 00 02 17 10 - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 01 - 39 01 00 00 00 00 02 40 00 - 39 01 00 00 00 00 02 ff 28 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 91 02 - 39 01 00 00 00 00 02 ff e0 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 48 81 - 39 01 00 00 00 00 02 8e 09 - 39 01 00 00 00 00 02 ff f0 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 33 20 - 39 01 00 00 00 00 02 34 35 - 39 01 00 00 00 00 02 ff 10 - 05 01 00 00 78 00 01 11 - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = [ - 15 01 00 00 00 00 02 ff 10 - 15 01 00 00 00 00 02 bc 00 - 05 01 00 00 10 00 01 28 - 05 01 00 00 32 00 01 10 - ]; - qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <8>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-sharp-qsync-wqhd-video.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-sharp-qsync-wqhd-video.dtsi deleted file mode 100644 index 7cf760df4c22..000000000000 --- a/arch/arm64/boot/dts/qcom/dsi-panel-sharp-qsync-wqhd-video.dtsi +++ /dev/null @@ -1,131 +0,0 @@ -/* Copyright (c) 2019, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -&mdss_mdp { - dsi_sharp_qsync_wqhd_video: qcom,mdss_dsi_sharp_qsync_wqhd_video { - qcom,mdss-dsi-panel-name = - "Sharp 2k video mode qsync dsi panel"; - qcom,mdss-dsi-panel-type = "dsi_video_mode"; - - qcom,dsi-ctrl-num = <0 1>; - qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; - - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-traffic-mode = "burst_mode"; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-dma-trigger = "trigger_sw"; - qcom,mdss-dsi-mdp-trigger = "none"; - qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; - qcom,mdss-pan-physical-width-dimension = <74>; - qcom,mdss-pan-physical-height-dimension = <134>; - qcom,mdss-dsi-tx-eot-append; - qcom,adjust-timer-wakeup-ms = <1>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750 - 15800 13250 34450 7500 3000>; - qcom,mdss-dsi-panel-peak-brightness = <6450000>; - qcom,mdss-dsi-panel-blackness-level = <4961>; - - qcom,mdss-dsi-display-timings { - timing@0 { - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <20>; - qcom,mdss-dsi-h-back-porch = <12>; - qcom,mdss-dsi-h-pulse-width = <8>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <14>; - qcom,mdss-dsi-v-front-porch = <2008>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 02 ff d0 - 39 01 00 00 00 00 02 75 40 - 39 01 00 00 10 00 02 f1 40 - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 10 00 06 2c 01 02 04 08 10 - 39 01 00 00 00 00 02 ff d0 - 39 01 00 00 00 00 02 75 00 - 39 01 00 00 10 00 02 f1 00 - /* Initial Setting */ - 39 01 00 00 00 00 02 ff 10 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 ba 03 - 39 01 00 00 00 00 02 bc 08 - 39 01 00 00 00 00 02 c0 83 - 39 01 00 00 00 00 11 c1 89 28 00 08 02 - 00 02 68 00 d5 00 0a 0d b7 09 89 - 39 01 00 00 00 00 03 c2 10 f0 - 39 01 00 00 00 00 02 d5 00 - 39 01 00 00 00 00 02 d6 00 - 39 01 00 00 00 00 02 de 00 - 39 01 00 00 00 00 02 e1 00 - 39 01 00 00 00 00 02 e5 01 - 39 01 00 00 00 00 02 bb 03 - 39 01 00 00 00 00 02 f6 70 - 39 01 00 00 00 00 02 f7 80 - 39 01 00 00 00 00 05 be 00 10 00 10 - 39 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 02 44 00 - 39 01 00 00 00 00 02 ff 20 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 87 02 - 39 01 00 00 00 00 02 5d 00 - 39 01 00 00 00 00 02 5e 14 - 39 01 00 00 00 00 02 5f eb - 39 01 00 00 00 00 02 ff 26 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 60 00 - 39 01 00 00 00 00 02 62 01 - 39 01 00 00 00 00 02 40 00 - 39 01 00 00 00 00 02 ff 28 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 91 02 - 39 01 00 00 00 00 02 ff e0 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 48 81 - 39 01 00 00 00 00 02 8e 09 - 39 01 00 00 00 00 02 ff f0 - 39 01 00 00 00 00 02 fb 01 - 39 01 00 00 00 00 02 33 20 - 39 01 00 00 00 00 02 34 35 - 39 01 00 00 00 00 02 ff 10 - 05 01 00 00 78 00 01 11 - 05 01 00 00 78 00 01 29 - ]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = [ - 15 01 00 00 00 00 02 ff 10 - 15 01 00 00 00 00 02 bc 00 - 05 01 00 00 10 00 01 28 - 05 01 00 00 32 00 01 10 - ]; - qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <8>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/guacamole-overlay-dvt.dts b/arch/arm64/boot/dts/qcom/guacamole-overlay-dvt.dts new file mode 100644 index 000000000000..e273cc611f3f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-overlay-dvt.dts @@ -0,0 +1,43 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +#include "guacamole_evt3.dtsi" +#include "guacamole_dvt.dtsi" + +/ { + model = "MTP 18821 18831 15"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0 >; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <15>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole-overlay-evt1.dts b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt1.dts new file mode 100644 index 000000000000..68749dd8d795 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt1.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +/ { + model = "MTP 18821 18831 12"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <12>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole-overlay-evt2-second.dts b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt2-second.dts new file mode 100644 index 000000000000..64fc4a52eb25 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt2-second.dts @@ -0,0 +1,40 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +/ { + model = "MTP 18821 18831 second 55"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <55>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole-overlay-evt2.dts b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt2.dts new file mode 100644 index 000000000000..d75754eb4b0f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt2.dts @@ -0,0 +1,40 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +/ { + model = "MTP 18821 18831 13 54 evt2"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <13 54>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole-overlay-evt3.dts b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt3.dts new file mode 100644 index 000000000000..070ed1c5453c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt3.dts @@ -0,0 +1,41 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +#include "guacamole_evt3.dtsi" +/ { + model = "MTP 18821 18831 14 52 53"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <14 52 53>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole-overlay-pvt.dts b/arch/arm64/boot/dts/qcom/guacamole-overlay-pvt.dts new file mode 100644 index 000000000000..1a3299e5dfed --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-overlay-pvt.dts @@ -0,0 +1,44 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +#include "guacamole_evt3.dtsi" +#include "guacamole_dvt.dtsi" +#include "guacamole_pvt.dtsi" + +/ { + model = "MTP 18821 18831 21 22"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0 >; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <21 22>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole-overlay-t0.dts b/arch/arm64/boot/dts/qcom/guacamole-overlay-t0.dts new file mode 100644 index 000000000000..ef389e47a275 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-overlay-t0.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" + +/ { + model = "MTP 18821 18831 T0 11"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <11>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-dvt.dts b/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-dvt.dts new file mode 100644 index 000000000000..1f8a448555d7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-dvt.dts @@ -0,0 +1,46 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sdx50m.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +#include "guacamole_dvt.dtsi" + + +/ { + model = "SDX50M MTP 18827 15"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18827>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <15>; + +}; diff --git a/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-evt1.dts b/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-evt1.dts new file mode 100644 index 000000000000..5826102194b8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-evt1.dts @@ -0,0 +1,44 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sdx50m.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" + + +/ { + model = "SDX50M MTP 18827 12 13"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18827>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <12 13>; + +}; diff --git a/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-evt2.dts b/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-evt2.dts new file mode 100644 index 000000000000..df0d83680882 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-evt2.dts @@ -0,0 +1,45 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sdx50m.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" + + +/ { + model = "SDX50M MTP 18827 14"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18827>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <14>; + +}; diff --git a/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-pvt.dts b/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-pvt.dts new file mode 100644 index 000000000000..440fa057b30e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-pvt.dts @@ -0,0 +1,47 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sdx50m.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +#include "guacamole_dvt.dtsi" +#include "guacamole_pvt.dtsi" + + +/ { + model = "SDX50M MTP 18827 21 22"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18827>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <21 22>; + +}; diff --git a/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-t0.dts b/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-t0.dts new file mode 100644 index 000000000000..31c592f7d9a4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-sdx50m-overlay-t0.dts @@ -0,0 +1,43 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sdx50m.dtsi" +#include "guacamole_t0.dtsi" + + +/ { + model = "SDX50M MTP 18827 11"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18827>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <11>; + +}; diff --git a/arch/arm64/boot/dts/qcom/guacamole.dtsi b/arch/arm64/boot/dts/qcom/guacamole.dtsi new file mode 100644 index 000000000000..18151a2d7ffb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole.dtsi @@ -0,0 +1,166 @@ +/*this is for different project dtsi*/ +/* OnePlus add thermistor, by rio.zhao*/ + +&thermal_zones { + skin-therm { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + trips { + freq_config1: freq_config1 { + temperature = <52000>; + hysteresis = <2000>; + type = "passive"; + }; + freq_config2: freq_config2 { + temperature = <54000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + cooling-maps { + freq_dev0 { + trip = <&freq_config1>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>;/*345*/ + }; + freq_dev1 { + trip = <&freq_config1>; + cooling-device = + <&CPU0 9 9>;/*1036*/ + }; + freq_dev2 { + trip = <&freq_config1>; + cooling-device = + <&CPU4 13 13>;/*1056*/ + }; + freq_dev3 { + trip = <&freq_config1>; + cooling-device = + <&CPU7 16 16>;/*1171*/ + }; + freq_dev4 { + trip = <&freq_config2>; + cooling-device = + <&CPU0 11 11>;/*844*/ + }; + freq_dev5 { + trip = <&freq_config2>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev6 { + trip = <&freq_config2>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev7 { + trip = <&freq_config2>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev8 { + trip = <&freq_config2>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pa-therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-msm-therm { + trips { + freq_config3: freq_config3 { + temperature = <62000>; + hysteresis = <2000>; + type = "passive"; + }; + freq_config4: freq_config4 { + temperature = <64000>; + hysteresis = <2000>; + type = "passive"; + }; + freq_config5: freq_config5 { + temperature = <66000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + cooling-maps { + freq_dev0 { + trip = <&freq_config3>; + cooling-device = + <&CPU0 2 2>;/*1632 18*/ + }; + freq_dev1 { + trip = <&freq_config3>; + cooling-device = + <&CPU4 8 8>;/*1612 17*/ + }; + freq_dev2 { + trip = <&freq_config3>; + cooling-device = + <&CPU7 9 9>;/*1920 20*/ + }; + freq_dev3 { + trip = <&freq_config4>; + cooling-device = + <&CPU0 4 4>;/*1478*/ + }; + freq_dev4 { + trip = <&freq_config4>; + cooling-device = + <&CPU4 11 11>;/*1286*/ + }; + freq_dev5 { + trip = <&freq_config4>; + cooling-device = + <&CPU7 13 13>;/*1497*/ + }; + freq_dev6 { + trip = <&freq_config4>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-3)>;/*499*/ + }; + freq_dev7 { + trip = <&freq_config5>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-2)>;/*427*/ + }; + }; + }; +}; +&pm8150b_charger { + /* for verify test adjust 530->500 */ + hot-bat-decidegc = <500>; + op,dis_ctrl_current; +}; + +&mtp_batterydata { + #include "OP-fg-batterydata-4000mah.dtsi" +}; + +&wdog{ + qcom,bark-time = <15000>; +}; diff --git a/arch/arm64/boot/dts/qcom/guacamole_dvt.dtsi b/arch/arm64/boot/dts/qcom/guacamole_dvt.dtsi new file mode 100644 index 000000000000..18b79ae52aba --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_dvt.dtsi @@ -0,0 +1 @@ +/*this is for one project different hw version */ \ No newline at end of file diff --git a/arch/arm64/boot/dts/qcom/guacamole_evt1.dtsi b/arch/arm64/boot/dts/qcom/guacamole_evt1.dtsi new file mode 100644 index 000000000000..8f699bb7f922 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_evt1.dtsi @@ -0,0 +1,2 @@ +/*this is for one project different hw version */ + diff --git a/arch/arm64/boot/dts/qcom/guacamole_evt2.dtsi b/arch/arm64/boot/dts/qcom/guacamole_evt2.dtsi new file mode 100644 index 000000000000..8f699bb7f922 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_evt2.dtsi @@ -0,0 +1,2 @@ +/*this is for one project different hw version */ + diff --git a/arch/arm64/boot/dts/qcom/guacamole_evt3.dtsi b/arch/arm64/boot/dts/qcom/guacamole_evt3.dtsi new file mode 100644 index 000000000000..8f699bb7f922 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_evt3.dtsi @@ -0,0 +1,2 @@ +/*this is for one project different hw version */ + diff --git a/arch/arm64/boot/dts/qcom/guacamole_pvt.dtsi b/arch/arm64/boot/dts/qcom/guacamole_pvt.dtsi new file mode 100644 index 000000000000..18b79ae52aba --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_pvt.dtsi @@ -0,0 +1 @@ +/*this is for one project different hw version */ \ No newline at end of file diff --git a/arch/arm64/boot/dts/qcom/guacamole_sdx50m.dtsi b/arch/arm64/boot/dts/qcom/guacamole_sdx50m.dtsi new file mode 100644 index 000000000000..78884d9ed161 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_sdx50m.dtsi @@ -0,0 +1,17 @@ +/*this is for sdx50m project */ +&ois_rear_0 { +ois_gyro,id = <2>;//18827 +}; +&ois_rear_1 { +ois_gyro,id = <2>;//18827 +}; + +&soc { + qcom,msm-imem@146bf000 { + download_mode@0{ + compatible = "qcom,msm-imem-download_mode"; + reg = <0x658 4>; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole_sm8150.dtsi b/arch/arm64/boot/dts/qcom/guacamole_sm8150.dtsi new file mode 100644 index 000000000000..a9e5ae4e8b22 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_sm8150.dtsi @@ -0,0 +1,8 @@ +/*this is for sm8150 version */ + +&ois_rear_0 { + ois_gyro,id = <1>;//18821 +}; +&ois_rear_1 { + ois_gyro,id = <1>;//18821 +}; diff --git a/arch/arm64/boot/dts/qcom/guacamole_t0.dtsi b/arch/arm64/boot/dts/qcom/guacamole_t0.dtsi new file mode 100644 index 000000000000..cba91f689146 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_t0.dtsi @@ -0,0 +1,99 @@ +/*this is for one project different hw version */ + +/*tp 1.8v power change to gpio119 for T0 hw*/ +&qupv3_se17_i2c { + sec-s6sy761@48 { + //enable1v8_gpio = <&tlmm 119 0x00>; + pinctrl-0 = <&tp_irq_active &tp_rst_active &tp_1v8_t0_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_t0_suspend>; + }; +}; + +&qupv3_se17_i2c { + st_fts@49 { + //enable1v8_gpio = <&tlmm 119 0x00>; + pinctrl-0 = <&tp_irq_active &tp_rst_active &tp_1v8_t0_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_t0_suspend>; + }; +}; + +&tlmm { + + + tp_1v8_t0_active: tp_1v8_t0_active { + mux { + pins = "gpio119"; + function = "gpio"; + }; + config { + pins = "gpio119"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + tp_1v8_t0_suspend: tp_1v8_t0_suspend { + mux { + pins = "gpio119"; + function = "gpio"; + }; + config { + pins = "gpio119"; + drive-strength = <8>; + bias-pull-down; + }; + }; +}; + +/* for Battery & Charging STRAT */ +&qupv3_se8_i2c { + oneplus_fastchg@26{ + microchip,mcu-en-gpio = <&tlmm 10 0x00>; + microchip,usb-sw-2-gpio = <&tlmm 59 0x00>; + op,mcl_verion; + }; + +}; + +&pm8150b_charger { + /* for external ship mode suppot */ + op,stm-ctrl-gpio = <&tlmm 21 0x00>; + op,vbus-ctrl-gpio = <&pm8150_gpios 9 GPIO_ACTIVE_LOW>; +}; + +/* for Battery & Charging END */ + +/* @bsp, usb config START*/ +&usb2_phy0 { + qcom,param-override-seq = + <0x67 0x6c/*Disconnection voltage +21.56%*/ + 0x06 0x70/*Pre-emphasis:4x DC voltage level:+6.50%*/ + 0x28 0x74>; +}; + +&extcon_usb1 { + status = "disabled"; +}; + +&usb1 { + status = "disabled"; +}; + +/* @bsp, As QRD-DVT have this config, keep the same config + * for ldo18 power suspend + */ +&usb_qmp_dp_phy { + vdd-supply = <&pm8150_l18>; + qcom,vdd-voltage-level = <0 912000 912000>; +}; + +&sde_dp { + vdda-0p9-supply = <&pm8150_l18>; + qcom,phy-supply-entries { + qcom,phy-supply-entry@0 { + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <912000>; + }; + }; +}; +/* @bsp, usb config END*/ diff --git a/arch/arm64/boot/dts/qcom/guacamoleb-overlay-dvt.dts b/arch/arm64/boot/dts/qcom/guacamoleb-overlay-dvt.dts new file mode 100644 index 000000000000..8db1e3b3e020 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoleb-overlay-dvt.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-guacamoleb.dtsi" +#include "guacamoleb_sm8150.dtsi" +#include "guacamoleb.dtsi" +#include "guacamoleb_dvt.dtsi" + +/ { + model = "MTP 18857 13"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0 >; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18857 >; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <13>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamoleb-overlay-evt.dts b/arch/arm64/boot/dts/qcom/guacamoleb-overlay-evt.dts new file mode 100644 index 000000000000..cbc81cc94b9b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoleb-overlay-evt.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-guacamoleb.dtsi" +#include "guacamoleb_sm8150.dtsi" +#include "guacamoleb.dtsi" +#include "guacamoleb_evt.dtsi" + +/ { + model = "MTP 18857 12 "; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18857>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <12>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamoleb-overlay-pvt.dts b/arch/arm64/boot/dts/qcom/guacamoleb-overlay-pvt.dts new file mode 100644 index 000000000000..0914cf131d2f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoleb-overlay-pvt.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-guacamoleb.dtsi" +#include "guacamoleb_sm8150.dtsi" +#include "guacamoleb.dtsi" +#include "guacamoleb_pvt.dtsi" + +/ { + model = "MTP 18857 14 15"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0 >; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18857>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <14 15>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamoleb-overlay-t0.dts b/arch/arm64/boot/dts/qcom/guacamoleb-overlay-t0.dts new file mode 100644 index 000000000000..694df9a2a39b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoleb-overlay-t0.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-guacamoleb.dtsi" +#include "guacamoleb_sm8150.dtsi" +#include "guacamoleb.dtsi" +#include "guacamoleb_t0.dtsi" + +/ { + model = "MTP 18857 T0 11"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18857>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <11>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamoleb.dtsi b/arch/arm64/boot/dts/qcom/guacamoleb.dtsi new file mode 100644 index 000000000000..2685b9ccd4a4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoleb.dtsi @@ -0,0 +1,490 @@ +/*this is for different project dtsi*/ +/* OnePlus add thermistor, by rio.zhao*/ +&pm8150_adc_tm { + skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + skin-therm { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + trips { + freq_config1: freq_config1 { + temperature = <52000>; + hysteresis = <2000>; + type = "passive"; + }; + freq_config2: freq_config2 { + temperature = <54000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + cooling-maps { + freq_dev0 { + trip = <&freq_config1>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>;/*345*/ + }; + freq_dev1 { + trip = <&freq_config1>; + cooling-device = + <&CPU0 9 9>;/*1036*/ + }; + freq_dev2 { + trip = <&freq_config1>; + cooling-device = + <&CPU4 13 13>;/*1056*/ + }; + freq_dev3 { + trip = <&freq_config1>; + cooling-device = + <&CPU7 16 16>;/*1171*/ + }; + freq_dev4 { + trip = <&freq_config2>; + cooling-device = + <&CPU0 11 11>;/*844*/ + }; + freq_dev5 { + trip = <&freq_config2>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev6 { + trip = <&freq_config2>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev7 { + trip = <&freq_config2>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev8 { + trip = <&freq_config2>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pa-therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-msm-therm { + trips { + freq_config3: freq_config3 { + temperature = <63000>; + hysteresis = <2000>; + type = "passive"; + }; + freq_config4: freq_config4 { + temperature = <65000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + cooling-maps { + freq_dev0 { + trip = <&freq_config3>; + cooling-device = + <&CPU0 2 2>;/*1632 18*/ + }; + freq_dev1 { + trip = <&freq_config3>; + cooling-device = + <&CPU4 8 8>;/*1612 17*/ + }; + freq_dev2 { + trip = <&freq_config3>; + cooling-device = + <&CPU7 9 9>;/*1920 20*/ + }; + freq_dev3 { + trip = <&freq_config4>; + cooling-device = + <&CPU0 4 4>;/*1478*/ + }; + freq_dev4 { + trip = <&freq_config4>; + cooling-device = + <&CPU4 11 11>;/*1286*/ + }; + freq_dev5 { + trip = <&freq_config4>; + cooling-device = + <&CPU7 13 13>;/*1497*/ + }; + freq_dev6 { + trip = <&freq_config3>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-3)>;/*499*/ + }; + freq_dev7 { + trip = <&freq_config4>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-2)>;/*427*/ + }; + }; + }; +}; + +/*tp 1.8v power change to gpio119 for T0 hw*/ +&qupv3_se17_i2c { + sec-s6sy761@48 { + status = "disable"; + // enable1v8_gpio = <&tlmm 119 0x00>; + pinctrl-0 = <&tp_irq_active &tp_rst_active &tp_1v8_t0_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_t0_suspend>; + }; +}; +&qupv3_se17_i2c { + st_fts@49{ + status = "disable"; + }; +}; +&qupv3_se17_i2c { + synaptics-s3706@20 { + //enable1v8_gpio = <&tlmm 119 0x00>; + project-name = "18857"; + reset-gpio = <&tlmm 54 0x00>; + touchpanel,display-coords = <1079 2339>; + touchpanel,panel-coords = <1079 2339>; + touchpanel,tx-rx-num = <16 33>; + pinctrl-0 = <&tp_irq_active &tp_1v8_t0_active &tp_rst_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_t0_suspend>; + }; + /delete-node/ sec-s6sy761@48; + /delete-node/ st_fts@49; +}; + +&tp_rst_active{ + mux { + pins = "gpio54"; + function = "gpio"; + }; + config { + pins = "gpio54"; + drive-strength = <8>; + bias-pull-up; + }; + +}; +&tlmm { + tp_1v8_t0_active: tp_1v8_t0_active { + mux { + pins = "gpio119"; + function = "gpio"; + }; + config { + pins = "gpio119"; + drive-strength = <8>; + bias-pull-up; + }; + }; + tp_1v8_t0_suspend: tp_1v8_t0_suspend { + mux { + pins = "gpio119"; + function = "gpio"; + }; + config { + pins = "gpio119"; + drive-strength = <8>; + bias-pull-down; + }; + }; +}; + +/* add for hall tri_state_key */ + +&tri_state_key { + compatible = "oneplus,hall_tri_state_key"; + status = "ok"; + interrupt-parent = <&tlmm>; +}; + +&qupv3_se9_i2c { + //qcom,clk-freq-out = <300000>; + status = "ok"; + magnachip@0D { + compatible = "tri_key_magnachip,tk_mxm1120,up"; + reg = <0x0D>; + vdd-supply = <&pm8150l_l7>; + magnachip,init-interval = <200>; + interrupt-parent = <&tlmm>; + interrupts = <26 0x02>; + dhall,irq-gpio = <&tlmm 26 0x2008>; + mxm,id = <1>; + pinctrl-names = "uphall_tri_state_key_active"; + pinctrl-0 = <&uphall_tri_state_key_active>; + }; + magnachip@0C { + compatible = "tri_key_magnachip,tk_mxm1120,down"; + reg = <0x0C>; + vdd-supply = <&pm8150l_l7>; + magnachip,init-interval = <200>; + interrupt-parent = <&tlmm>; + interrupts = <27 0x02>; + dhall,irq-gpio = <&tlmm 27 0x2008>; + mxm,id = <2>; + pinctrl-names = "downhall_tri_state_key_active"; + pinctrl-0 = <&downhall_tri_state_key_active>; + }; +}; + +&tlmm { + uphall_tri_state_key_active: uphall_tri_state_key_active { + mux { + pins = "gpio26"; + function = "gpio"; + }; + config { + pins = "gpio26"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + downhall_tri_state_key_active: downhall_tri_state_key_active { + mux { + pins = "gpio27"; + function = "gpio"; + }; + config { + pins = "gpio27"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +/* for Battery & Charging STRAT */ +&qupv3_se8_i2c { + oneplus_fastchg@26{ + microchip,mcu-en-gpio = <&tlmm 10 0x00>; + microchip,usb-sw-2-gpio = <&tlmm 59 0x00>; + }; +}; + +&pm8150b_charger { + /* for external ship mode support */ + op,stm-ctrl-gpio = <&tlmm 21 0x00>; + op,vbus-ctrl-gpio = <&pm8150_gpios 9 GPIO_ACTIVE_LOW>; + /* ibatmax setting for different temp regions */ + op,dis_ctrl_current; + ibatmax-little-cold-ma = <320>; + ibatmax-little-cool-thr-ma = <1750>; + ibatmax-cool-thr-ma = <1000>; + ibatmax-cool-ma = <1450>; + ibatmax-warm-ma = <1050>; + op,little_cold_term_current = <250>; + vph-sel-disable; +}; + +&mtp_batterydata { + #include "OP-fg-batterydata-3700mah.dtsi" +}; +/* for Battery & Charging END */ + +/* @bsp, USB oem config START*/ +&usb2_phy0 { + qcom,param-override-seq = + <0x67 0x6c/*Disconnection voltage +21.56%*/ + 0x09 0x70/*Pre-emphasis:4x DC voltage level:+13.30%*/ + 0x28 0x74>; +}; + +&extcon_usb1 { + status = "disabled"; +}; + +&usb1 { + status = "disabled"; +}; +/* @bsp, USB oem config END*/ + +&qupv3_se1_i2c { + magnachip@0C { + status = "disabled"; + }; + + magnachip@0D { + status = "disabled"; + }; +}; + +&vendor { + step_motor { + status = "disabled"; + }; +}; + +&motor_pl { + status = "disabled"; +}; + +&infrared_pl { + interrupt-parent = <&tlmm>; + interrupts = <163 0x2>; + infrared,irq-gpio = <&tlmm 163 0x2008>; + pinctrl-names = "infrared_input"; + pinctrl-0 = <&free_fall_input>; +}; + +&tlmm { + infrared_input: infrared_input { + mux { + pins = "gpio163"; + function = "gpio"; + }; + config { + pins = "gpio163"; + drive-strength = <2>; + input-enable; + bias-disable; //No Pull + }; + }; + +}; + + + + +&oem_rf_cable { + rf,cable-gpio-1 = <&pm8150_gpios 4 0>; + pinctrl-0 = <&rf_cable_ant0_active &rf_pm8150_cable_ant1>; +}; + +&oem_aboard_check { + /delete-property/ oem,aboard-gpio-1; + pinctrl-0 = <&ab_id1_default>; +}; + +&pm8150_gpios { + rf_pm8150_cable_ant1: rf_pm8150_cable_ant1 { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; +&pm8150b_gpios { + haptics_boost { + haptics_boost_default: haptics_boost_default { + pins = "gpio5"; + function = "normal"; + output-enable; + input-disable; + bias-disable; + qcom,drive-strength = <3>; /* high */ + power-source = <0>; /* VPH_PWR */ + }; + }; +}; +/* OnePlus add haptic, by yangfb*/ +&aw8697_haptic { + status = "disabled"; +}; + +&vendor { + step_motor { + status = "disabled"; + }; +}; + +&pm8150b_gpios { + haptics_boost { + haptics_boost_default: haptics_boost_default { + pins = "gpio5"; + function = "normal"; + output-enable; + input-disable; + bias-disable; + qcom,drive-strength = <3>; /* high */ + power-source = <0>; /* VPH_PWR */ + }; + }; +}; + +&vendor { + haptics_boost_vreg: haptics_boost_vreg { + compatible = "regulator-fixed"; + regulator-name = "haptics_boost"; + gpio = <&pm8150b_gpios 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-enable-ramp-delay = <300>; + pinctrl-names = "default"; + pinctrl-0 = <&haptics_boost_default>; + status = "ok"; + }; +}; +&pm8150b_haptics { + status = "ok"; + vdd-supply = <&haptics_boost_vreg>; + wf_5 { + qcom,wf-brake-pattern = [03 03 03 03]; + }; + wf_6 { + /* WEAK */ + qcom,effect-id = <6>; + qcom,wf-vmax-mv = <2500>; + qcom,wf-pattern = [7e 7e 7e fe fe]; + qcom,wf-play-rate-us = <6667>; + qcom,wf-brake-pattern = [00 00 00 00]; + qcom,lra-auto-resonance-disable; + }; + wf_7 { + /* MIDDLE */ + qcom,effect-id = <7>; + qcom,wf-vmax-mv = <2500>; + qcom,wf-pattern = [7e 7e 7e 7e fe fe fe]; + qcom,wf-play-rate-us = <6667>; + qcom,wf-brake-pattern = [00 00 00 00]; + qcom,lra-auto-resonance-disable; + }; + wf_8 { + /* STRONG */ + qcom,effect-id = <8>; + qcom,wf-vmax-mv = <2500>; + qcom,wf-pattern = [7e 7e 7e 7e 7e fe fe fe]; + qcom,wf-play-rate-us = <6667>; + qcom,wf-brake-pattern = [00 00 00 00]; + qcom,lra-auto-resonance-disable; + }; +}; + +&wdog{ + qcom,bark-time = <15000>; +}; diff --git a/arch/arm64/boot/dts/qcom/guacamoleb_dvt.dtsi b/arch/arm64/boot/dts/qcom/guacamoleb_dvt.dtsi new file mode 100644 index 000000000000..18b79ae52aba --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoleb_dvt.dtsi @@ -0,0 +1 @@ +/*this is for one project different hw version */ \ No newline at end of file diff --git a/arch/arm64/boot/dts/qcom/guacamoleb_evt.dtsi b/arch/arm64/boot/dts/qcom/guacamoleb_evt.dtsi new file mode 100644 index 000000000000..18b79ae52aba --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoleb_evt.dtsi @@ -0,0 +1 @@ +/*this is for one project different hw version */ \ No newline at end of file diff --git a/arch/arm64/boot/dts/qcom/guacamoleb_pvt.dtsi b/arch/arm64/boot/dts/qcom/guacamoleb_pvt.dtsi new file mode 100644 index 000000000000..18b79ae52aba --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoleb_pvt.dtsi @@ -0,0 +1 @@ +/*this is for one project different hw version */ \ No newline at end of file diff --git a/arch/arm64/boot/dts/qcom/guacamoleb_sm8150.dtsi b/arch/arm64/boot/dts/qcom/guacamoleb_sm8150.dtsi new file mode 100644 index 000000000000..8ec64a5dc408 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoleb_sm8150.dtsi @@ -0,0 +1,7 @@ +/*this is for sm8150 version */ +&ois_rear_0 { +ois_gyro,id = <3>;//18821 +}; +&ois_rear_1 { +ois_gyro,id = <3>;//18821 +}; diff --git a/arch/arm64/boot/dts/qcom/guacamoleb_t0.dtsi b/arch/arm64/boot/dts/qcom/guacamoleb_t0.dtsi new file mode 100644 index 000000000000..479382ca9ad9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoleb_t0.dtsi @@ -0,0 +1,4 @@ +/*this is for one project different hw version */ + + + diff --git a/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-dvt.dts b/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-dvt.dts new file mode 100644 index 000000000000..5d9f553032f1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-dvt.dts @@ -0,0 +1,45 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamoles_sdx50m.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_dvt.dtsi" + +#include "guacamoles_sdx50m_dvt.dtsi" + +/ { + model = "SDX50M MTP 18825 15"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18825>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <15>; + +}; diff --git a/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-evt.dts b/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-evt.dts new file mode 100644 index 000000000000..2b3166bb0959 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-evt.dts @@ -0,0 +1,45 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamoles_sdx50m.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" + +#include "guacamoles_sdx50m_evt.dtsi" + +/ { + model = "SDX50M MTP 18825 24"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18825>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <24>; + +}; diff --git a/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-pvt.dts b/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-pvt.dts new file mode 100644 index 000000000000..5e6f508497cc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-pvt.dts @@ -0,0 +1,45 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamoles_sdx50m.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_pvt.dtsi" + +#include "guacamoles_sdx50m_pvt.dtsi" + +/ { + model = "SDX50M MTP 18825 21"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18825>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <21>; + +}; diff --git a/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-t0.dts b/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-t0.dts new file mode 100644 index 000000000000..a2b12f352416 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoles-sdx50m-overlay-t0.dts @@ -0,0 +1,44 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" + +#include "sdx5xm-external-soc.dtsi" +#include "sm8150-sdx50m.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamoles_sdx50m.dtsi" +#include "guacamole_t0.dtsi" + +#include "guacamoles_sdx50m_t0.dtsi" + +/ { + model = "SDX50M MTP 18825 11"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <0x01010008 0x1>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18825>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <11>; + +}; diff --git a/arch/arm64/boot/dts/qcom/guacamoles_sdx50m.dtsi b/arch/arm64/boot/dts/qcom/guacamoles_sdx50m.dtsi new file mode 100644 index 000000000000..74a3457efd7b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoles_sdx50m.dtsi @@ -0,0 +1,11 @@ +/*this is for sdx50m project */ +&ois_rear_0 { +ois_gyro,id = <2>;//18827 +}; +&ois_rear_1 { +ois_gyro,id = <2>;//18827 +}; + +&pm8150b_charger { + op,dis_ctrl_current; +}; diff --git a/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_dvt.dtsi b/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_dvt.dtsi new file mode 100644 index 000000000000..50cb0f3e0436 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_dvt.dtsi @@ -0,0 +1,2 @@ +/*this is for sdx50m project */ + diff --git a/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_evt.dtsi b/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_evt.dtsi new file mode 100644 index 000000000000..25e705a507d3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_evt.dtsi @@ -0,0 +1 @@ +/*this is for sdx50m project */ diff --git a/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_pvt.dtsi b/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_pvt.dtsi new file mode 100644 index 000000000000..25e705a507d3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_pvt.dtsi @@ -0,0 +1 @@ +/*this is for sdx50m project */ diff --git a/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_t0.dtsi b/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_t0.dtsi new file mode 100644 index 000000000000..25e705a507d3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamoles_sdx50m_t0.dtsi @@ -0,0 +1 @@ +/*this is for sdx50m project */ diff --git a/arch/arm64/boot/dts/qcom/msm-arm-smmu-atoll.dtsi b/arch/arm64/boot/dts/qcom/msm-arm-smmu-atoll.dtsi index 9c050f741e01..d96746cce5cd 100644 --- a/arch/arm64/boot/dts/qcom/msm-arm-smmu-atoll.dtsi +++ b/arch/arm64/boot/dts/qcom/msm-arm-smmu-atoll.dtsi @@ -10,7 +10,6 @@ * GNU General Public License for more details. */ #include -#include &soc { kgsl_smmu: arm,smmu-kgsl@5040000 { @@ -37,20 +36,6 @@ ; clock-names = "gcc_gpu_memnoc_gfx_clk"; clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>; - - attach-impl-defs = - <0x6000 0x2378>, - <0x6060 0x1055>, - <0x678c 0x8>, - <0x6794 0x28>, - <0x6800 0x6>, - <0x6900 0x3ff>, - <0x6924 0x204>, - <0x6928 0x11000>, - <0x6930 0x800>, - <0x6960 0xffffffff>, - <0x6b64 0x1a5551>, - <0x6b68 0x9a82a382>; }; apps_smmu: apps-smmu@0x15000000 { @@ -146,17 +131,6 @@ , , ; - qcom,msm-bus,name = "apps_smmu"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - , - <0 0>, - , - , - <0 1000>; anoc_1_tbu: anoc_1_tbu@0x15185000 { compatible = "qcom,qsmmuv500-tbu"; @@ -164,17 +138,6 @@ <0x15182200 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x0 0x400>; - qcom,msm-bus,name = "apps_smmu"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - , - <0 0>, - , - , - <0 1000>; }; anoc_2_tbu: anoc_2_tbu@0x15189000 { @@ -183,17 +146,6 @@ <0x15182208 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x400 0x400>; - qcom,msm-bus,name = "apps_smmu"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - , - <0 0>, - , - , - <0 1000>; }; mnoc_hf_0_tbu: mnoc_hf_0_tbu@0x1518d000 { @@ -204,17 +156,6 @@ qcom,stream-id-range = <0x800 0x400>; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>; - qcom,msm-bus,name = "mnoc_hf_0_tbu"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - , - <0 0>, - , - , - <0 1000>; }; mnoc_sf_0_tbu: mnoc_sf_0_tbu@0x15191000 { @@ -225,17 +166,6 @@ qcom,stream-id-range = <0xc00 0x400>; qcom,regulator-names = "vdd"; vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>; - qcom,msm-bus,name = "mnoc_sf_0_tbu"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - , - <0 0>, - , - , - <0 1000>; }; lpass_noc_tbu: lpass_noc_tbu@0x15195000 { @@ -244,17 +174,6 @@ <0x15182220 0x8>; reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1000 0x400>; - qcom,msm-bus,name = "apps_smmu"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - , - <0 0>, - , - , - <0 1000>; }; compute_dsp_0_tbu: compute_dsp_0_tbu@0x15199000 { @@ -264,17 +183,6 @@ reg-names = "base", "status-reg"; qcom,stream-id-range = <0x1400 0x400>; /* No GDSC */ - qcom,msm-bus,name = "apps_smmu"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,active-only; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - , - , - <0 0>, - , - , - <0 1000>; }; }; @@ -294,13 +202,3 @@ dma-coherent; }; }; - -&apps_smmu { - qcom,actlr = - /* HF_0 and SF_0 TBUs: +3 deep PF */ - <0x800 0x7ff 0x103>, - - /* NPU SIDs: +3 deep PF */ - <0x1460 0x1f 0x303>, - <0x1480 0x1f 0x303>; -}; diff --git a/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi b/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi index bd1f37554f7e..6fab5f53ea61 100644 --- a/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi +++ b/arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi @@ -28,6 +28,7 @@ #global-interrupts = <1>; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cx_gdsc>; + qcom,deferred-regulator-disable-delay = <80>; clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, <&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>, <&clock_gpucc GPU_CC_AHB_CLK>, diff --git a/arch/arm64/boot/dts/qcom/msm-audio-lpass.dtsi b/arch/arm64/boot/dts/qcom/msm-audio-lpass.dtsi index ece4cd67e5e4..34a342a42561 100644 --- a/arch/arm64/boot/dts/qcom/msm-audio-lpass.dtsi +++ b/arch/arm64/boot/dts/qcom/msm-audio-lpass.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -179,11 +179,6 @@ qcom,msm-dai-cdc-dma-dev-id = <45091>; }; - va_cdc_dma_2_tx: qcom,msm-dai-va-cdc-dma-2-tx { - compatible = "qcom,msm-dai-cdc-dma-dev"; - qcom,msm-dai-cdc-dma-dev-id = <45093>; - }; - rx_cdc_dma_0_rx: qcom,msm-dai-rx-cdc-dma-0-rx { compatible = "qcom,msm-dai-cdc-dma-dev"; qcom,msm-dai-cdc-dma-dev-id = <45104>; @@ -336,7 +331,6 @@ sb_7_tx: qcom,msm-dai-q6-sb-7-tx { compatible = "qcom,msm-dai-q6-dev"; qcom,msm-dai-q6-dev-id = <16399>; - qcom,msm-dai-q6-slim-dev-id = <0>; }; sb_8_rx: qcom,msm-dai-q6-sb-8-rx { @@ -347,7 +341,6 @@ sb_8_tx: qcom,msm-dai-q6-sb-8-tx { compatible = "qcom,msm-dai-q6-dev"; qcom,msm-dai-q6-dev-id = <16401>; - qcom,msm-dai-q6-slim-dev-id = <0>; }; sb_9_rx: qcom,msm-dai-q6-sb-9-rx { @@ -517,20 +510,6 @@ qcom,msm-cpudai-afe-clk-ver = <2>; }; - dai_sen_auxpcm: qcom,msm-sen-auxpcm { - compatible = "qcom,msm-auxpcm-dev"; - qcom,msm-cpudai-auxpcm-mode = <0>, <0>; - qcom,msm-cpudai-auxpcm-sync = <1>, <1>; - qcom,msm-cpudai-auxpcm-frame = <5>, <4>; - qcom,msm-cpudai-auxpcm-quant = <2>, <2>; - qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; - qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; - qcom,msm-cpudai-auxpcm-data = <0>, <0>; - qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; - qcom,msm-auxpcm-interface = "senary"; - qcom,msm-cpudai-afe-clk-ver = <2>; - }; - hdmi_dba: qcom,msm-hdmi-dba-codec-rx { compatible = "qcom,msm-hdmi-dba-codec-rx"; qcom,dba-bridge-chip = "adv7533"; @@ -732,44 +711,6 @@ }; }; - tdm_sen_rx: qcom,msm-dai-tdm-sen-rx { - compatible = "qcom,msm-dai-tdm"; - qcom,msm-cpudai-tdm-group-id = <37200>; - qcom,msm-cpudai-tdm-group-num-ports = <1>; - qcom,msm-cpudai-tdm-group-port-id = <36944>; - qcom,msm-cpudai-tdm-clk-rate = <1536000>; - qcom,msm-cpudai-tdm-clk-internal = <1>; - qcom,msm-cpudai-tdm-sync-mode = <1>; - qcom,msm-cpudai-tdm-sync-src = <1>; - qcom,msm-cpudai-tdm-data-out = <0>; - qcom,msm-cpudai-tdm-invert-sync = <1>; - qcom,msm-cpudai-tdm-data-delay = <1>; - dai_sen_tdm_rx_0: qcom,msm-dai-q6-tdm-sen-rx-0 { - compatible = "qcom,msm-dai-q6-tdm"; - qcom,msm-cpudai-tdm-dev-id = <36944>; - qcom,msm-cpudai-tdm-data-align = <0>; - }; - }; - - tdm_sen_tx: qcom,msm-dai-tdm-sen-tx { - compatible = "qcom,msm-dai-tdm"; - qcom,msm-cpudai-tdm-group-id = <37201>; - qcom,msm-cpudai-tdm-group-num-ports = <1>; - qcom,msm-cpudai-tdm-group-port-id = <36945>; - qcom,msm-cpudai-tdm-clk-rate = <1536000>; - qcom,msm-cpudai-tdm-clk-internal = <1>; - qcom,msm-cpudai-tdm-sync-mode = <1>; - qcom,msm-cpudai-tdm-sync-src = <1>; - qcom,msm-cpudai-tdm-data-out = <0>; - qcom,msm-cpudai-tdm-invert-sync = <1>; - qcom,msm-cpudai-tdm-data-delay = <1>; - dai_sen_tdm_tx_0: qcom,msm-dai-q6-tdm-sen-tx-0 { - compatible = "qcom,msm-dai-q6-tdm"; - qcom,msm-cpudai-tdm-dev-id = <36945>; - qcom,msm-cpudai-tdm-data-align = <0>; - }; - }; - dai_pri_spdif_rx: qcom,msm-dai-q6-spdif-pri-rx { compatible = "qcom,msm-dai-q6-spdif"; qcom,msm-dai-q6-dev-id = <20480>; diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index e198ed897b55..087aa21910ce 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -449,11 +449,15 @@ compatible = "qcom,bcl-v5"; reg = <0x1d00 0x100>; interrupts = <0x0 0x1d 0x0 IRQ_TYPE_NONE>, + <0x0 0x1d 0x1 IRQ_TYPE_NONE>, + <0x0 0x1d 0x0 IRQ_TYPE_NONE>, <0x0 0x1d 0x1 IRQ_TYPE_NONE>, <0x0 0x1d 0x2 IRQ_TYPE_NONE>; - interrupt-names = "bcl-lvl0", - "bcl-lvl1", - "bcl-lvl2"; + interrupt-names = "bcl-ibat-lvl0", + "bcl-ibat-lvl1", + "bcl-vbat-lvl0", + "bcl-vbat-lvl1", + "bcl-vbat-lvl2"; #thermal-sensor-cells = <1>; }; @@ -560,7 +564,7 @@ }; pm6150-ibat-lvl0 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm6150_bcl 0>; @@ -592,7 +596,7 @@ }; pm6150-vbat-lvl0 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&pm6150_bcl 2>; @@ -642,54 +646,6 @@ }; }; - pm6150-bcl-lvl0 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm6150_bcl 5>; - wake-capable-sensor; - - trips { - bcl_lvl0: bcl-lvl0 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - - pm6150-bcl-lvl1 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm6150_bcl 6>; - wake-capable-sensor; - - trips { - bcl_lvl1: bcl-lvl1 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - - pm6150-bcl-lvl2 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm6150_bcl 7>; - wake-capable-sensor; - - trips { - bcl_lvl2: bcl-lvl2 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - soc { polling-delay-passive = <100>; polling-delay = <0>; diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index 8398790f72ec..64672673a4f9 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -46,9 +46,9 @@ interrupts = <0x4 0x3d 0x0 IRQ_TYPE_NONE>, <0x4 0x3d 0x1 IRQ_TYPE_NONE>, <0x4 0x3d 0x2 IRQ_TYPE_NONE>; - interrupt-names = "bcl-lvl0", - "bcl-lvl1", - "bcl-lvl2"; + interrupt-names = "bcl-vbat-lvl0", + "bcl-vbat-lvl1", + "bcl-vbat-lvl2"; #thermal-sensor-cells = <1>; }; @@ -120,7 +120,6 @@ <0x4 0xc3 0 IRQ_TYPE_NONE>, <0x4 0xc4 0 IRQ_TYPE_NONE>, <0x4 0xc5 0 IRQ_TYPE_NONE>, - <0x4 0xc6 0 IRQ_TYPE_NONE>, <0x4 0xc7 0 IRQ_TYPE_NONE>, <0x4 0xc8 0 IRQ_TYPE_NONE>, <0x4 0xc9 0 IRQ_TYPE_NONE>, @@ -129,11 +128,12 @@ interrupt-names = "pm6150l_gpio1", "pm6150l_gpio2", "pm6150l_gpio3", "pm6150l_gpio4", "pm6150l_gpio5", "pm6150l_gpio6", - "pm6150l_gpio7", "pm6150l_gpio8", - "pm6150l_gpio9", "pm6150l_gpio10", - "pm6150l_gpio11", "pm6150l_gpio12"; + "pm6150l_gpio8", "pm6150l_gpio9", + "pm6150l_gpio10", "pm6150l_gpio11", + "pm6150l_gpio12"; gpio-controller; #gpio-cells = <2>; + qcom,gpios-disallowed = <7>; }; }; @@ -511,52 +511,4 @@ }; }; }; - - pm6150l-bcl-lvl0 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm6150l_bcl 5>; - wake-capable-sensor; - - trips { - l_bcl_lvl0: l-bcl-lvl0 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - - pm6150l-bcl-lvl1 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm6150l_bcl 6>; - wake-capable-sensor; - - trips { - l_bcl_lvl1: l-bcl-lvl1 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - - pm6150l-bcl-lvl2 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm6150l_bcl 7>; - wake-capable-sensor; - - trips { - l_bcl_lvl2: l-bcl-lvl2 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; }; diff --git a/arch/arm64/boot/dts/qcom/pm6155-vm.dtsi b/arch/arm64/boot/dts/qcom/pm6155-vm.dtsi deleted file mode 100644 index d7a5b9672d14..000000000000 --- a/arch/arm64/boot/dts/qcom/pm6155-vm.dtsi +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -&spmi_bus { - qcom,pm6155@0 { - compatible = "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <2>; - #size-cells = <0>; - - pm6155_1_gpios: pinctrl@c000 { - compatible = "qcom,spmi-gpio"; - reg = <0xc000 0xa00>; - interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>, - <0x0 0xc1 0 IRQ_TYPE_NONE>, - <0x0 0xc2 0 IRQ_TYPE_NONE>, - <0x0 0xc3 0 IRQ_TYPE_NONE>, - <0x0 0xc4 0 IRQ_TYPE_NONE>, - <0x0 0xc5 0 IRQ_TYPE_NONE>, - <0x0 0xc6 0 IRQ_TYPE_NONE>, - <0x0 0xc7 0 IRQ_TYPE_NONE>, - <0x0 0xc8 0 IRQ_TYPE_NONE>, - <0x0 0xc9 0 IRQ_TYPE_NONE>; - interrupt-names = "pm6155_1_gpio1", "pm6155_1_gpio2", - "pm6155_1_gpio3", "pm6155_1_gpio4", - "pm6155_1_gpio5", "pm6155_1_gpio6", - "pm6155_1_gpio7", "pm6155_1_gpio8", - "pm6155_1_gpio9", "pm6155_1_gpio10"; - gpio-controller; - #gpio-cells = <2>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/pm8150-vm.dtsi b/arch/arm64/boot/dts/qcom/pm8150-vm.dtsi deleted file mode 100644 index 6c5a21a6e7f3..000000000000 --- a/arch/arm64/boot/dts/qcom/pm8150-vm.dtsi +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -&spmi_bus { - qcom,pm8150@0 { - compatible = "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <2>; - #size-cells = <0>; - - pm8150_gpios: pinctrl@c000 { - compatible = "qcom,spmi-gpio"; - reg = <0xc000 0xa00>; - interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>, - <0x0 0xc2 0 IRQ_TYPE_NONE>, - <0x0 0xc3 0 IRQ_TYPE_NONE>, - <0x0 0xc5 0 IRQ_TYPE_NONE>, - <0x0 0xc8 0 IRQ_TYPE_NONE>, - <0x0 0xc9 0 IRQ_TYPE_NONE>; - interrupt-names = "pm8150_gpio1", "pm8150_gpio3", - "pm8150_gpio4", "pm8150_gpio6", - "pm8150_gpio9", "pm8150_gpio10"; - gpio-controller; - #gpio-cells = <2>; - qcom,gpios-disallowed = <2 5 7 8>; - }; - }; -}; - -&pm8150_gpios { - key_home { - key_home_default: key_home_default { - pins = "gpio1"; - function = "normal"; - input-enable; - bias-pull-up; - power-source = <0>; - }; - }; - - storage_sd_detect { - storage_cd_default: storage_cd_default { - pins = "gpio4"; - function = "normal"; - input-enable; - bias-pull-up; - power-source = <0>; - }; - }; - - key_vol_up { - key_vol_up_default: key_vol_up_default { - pins = "gpio6"; - function = "normal"; - input-enable; - bias-pull-up; - power-source = <1>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index 4f780f07ecb8..f1e9dc2f8283 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -96,14 +96,15 @@ <0x0 0xc2 0 IRQ_TYPE_NONE>, <0x0 0xc3 0 IRQ_TYPE_NONE>, <0x0 0xc5 0 IRQ_TYPE_NONE>, + <0x0 0xc6 0 IRQ_TYPE_NONE>, <0x0 0xc8 0 IRQ_TYPE_NONE>, <0x0 0xc9 0 IRQ_TYPE_NONE>; interrupt-names = "pm8150_gpio1", "pm8150_gpio3", "pm8150_gpio4", "pm8150_gpio6", - "pm8150_gpio9", "pm8150_gpio10"; + "pm8150_gpio7","pm8150_gpio9", "pm8150_gpio10"; gpio-controller; #gpio-cells = <2>; - qcom,gpios-disallowed = <2 5 7 8>; + qcom,gpios-disallowed = <2 5 8>; }; pm8150_sdam_2: sdam@b100 { diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi index e1ff572b262d..c410e178f2e6 100644 --- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi @@ -55,11 +55,6 @@ clock-names = "xo"; }; - pm8150b_pbs1: qcom,pbs@7200 { - compatible = "qcom,qpnp-pbs"; - reg = <0x7200 0x100>; - }; - pm8150b_qnovo: qcom,sdam-qnovo@b000 { compatible = "qcom,qpnp-qnovo5"; reg = <0xb000 0x100>; @@ -365,11 +360,15 @@ compatible = "qcom,bcl-v5"; reg = <0x1d00 0x100>; interrupts = <0x2 0x1d 0x0 IRQ_TYPE_NONE>, + <0x2 0x1d 0x1 IRQ_TYPE_NONE>, + <0x2 0x1d 0x0 IRQ_TYPE_NONE>, <0x2 0x1d 0x1 IRQ_TYPE_NONE>, <0x2 0x1d 0x2 IRQ_TYPE_NONE>; - interrupt-names = "bcl-lvl0", - "bcl-lvl1", - "bcl-lvl2"; + interrupt-names = "bcl-ibat-lvl0", + "bcl-ibat-lvl1", + "bcl-vbat-lvl0", + "bcl-vbat-lvl1", + "bcl-vbat-lvl2"; #thermal-sensor-cells = <1>; }; @@ -383,7 +382,6 @@ #address-cells = <1>; #size-cells = <1>; qcom,pmic-revid = <&pm8150b_revid>; - qcom,pmic-pbs = <&pm8150b_pbs1>; status = "okay"; qcom,fg-batt-soc@4000 { @@ -599,7 +597,7 @@ }; pm8150b-ibat-lvl0 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm8150b_bcl 0>; @@ -615,7 +613,7 @@ }; pm8150b-ibat-lvl1 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm8150b_bcl 1>; @@ -631,7 +629,7 @@ }; pm8150b-vbat-lvl0 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&pm8150b_bcl 2>; @@ -648,7 +646,7 @@ }; pm8150b-vbat-lvl1 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&pm8150b_bcl 3>; @@ -665,7 +663,7 @@ }; pm8150b-vbat-lvl2 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&pm8150b_bcl 4>; @@ -681,56 +679,8 @@ }; }; - pm8150b-bcl-lvl0 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm8150b_bcl 5>; - wake-capable-sensor; - - trips { - b_bcl_lvl0: b-bcl-lvl0 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - - pm8150b-bcl-lvl1 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm8150b_bcl 6>; - wake-capable-sensor; - - trips { - b_bcl_lvl1: b-bcl-lvl1 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - - pm8150b-bcl-lvl2 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm8150b_bcl 7>; - wake-capable-sensor; - - trips { - b_bcl_lvl2: b-bcl-lvl2 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - soc { - polling-delay-passive = <100>; + polling-delay-passive = <1000>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&bcl_soc>; @@ -739,7 +689,12 @@ trips { soc_trip:soc-trip { - temperature = <10>; + temperature = <5>; + hysteresis = <0>; + type = "passive"; + }; + soc_trip2:soc-trip2 { + temperature = <15>; hysteresis = <0>; type = "passive"; }; diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi index 3586af695f4f..96e20a8df850 100644 --- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi @@ -117,9 +117,9 @@ interrupts = <0x4 0x3d 0x0 IRQ_TYPE_NONE>, <0x4 0x3d 0x1 IRQ_TYPE_NONE>, <0x4 0x3d 0x2 IRQ_TYPE_NONE>; - interrupt-names = "bcl-lvl0", - "bcl-lvl1", - "bcl-lvl2"; + interrupt-names = "bcl-vbat-lvl0", + "bcl-vbat-lvl1", + "bcl-vbat-lvl2"; #thermal-sensor-cells = <1>; }; @@ -464,7 +464,7 @@ }; pm8150l-vph-lvl0 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&pm8150l_bcl 2>; @@ -481,7 +481,7 @@ }; pm8150l-vph-lvl1 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&pm8150l_bcl 3>; @@ -498,7 +498,7 @@ }; pm8150l-vph-lvl2 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&pm8150l_bcl 4>; @@ -513,52 +513,4 @@ }; }; }; - - pm8150l-bcl-lvl0 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm8150l_bcl 5>; - wake-capable-sensor; - - trips { - l_bcl_lvl0: l-bcl-lvl0 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - - pm8150l-bcl-lvl1 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm8150l_bcl 6>; - wake-capable-sensor; - - trips { - l_bcl_lvl1: l-bcl-lvl1 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - - pm8150l-bcl-lvl2 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&pm8150l_bcl 7>; - wake-capable-sensor; - - trips { - l_bcl_lvl2: l-bcl-lvl2 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; }; diff --git a/arch/arm64/boot/dts/qcom/pmi632.dtsi b/arch/arm64/boot/dts/qcom/pmi632.dtsi index 41ddd00c89e1..f97fe75e7fe0 100644 --- a/arch/arm64/boot/dts/qcom/pmi632.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi632.dtsi @@ -394,11 +394,15 @@ compatible = "qcom,bcl-v5"; reg = <0x3d00 0x100>; interrupts = <0x2 0x3d 0x0 IRQ_TYPE_NONE>, + <0x2 0x3d 0x1 IRQ_TYPE_NONE>, + <0x2 0x3d 0x0 IRQ_TYPE_NONE>, <0x2 0x3d 0x1 IRQ_TYPE_NONE>, <0x2 0x3d 0x2 IRQ_TYPE_NONE>; - interrupt-names = "bcl-lvl0", - "bcl-lvl1", - "bcl-lvl2"; + interrupt-names = "bcl-ibat-lvl0", + "bcl-ibat-lvl1", + "bcl-vbat-lvl0", + "bcl-vbat-lvl1", + "bcl-vbat-lvl2"; qcom,ibat-use-qg-adc-5a; #thermal-sensor-cells = <1>; }; @@ -632,7 +636,7 @@ }; pmi632-ibat-lvl0 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&bcl_sensor 0>; @@ -648,7 +652,7 @@ }; pmi632-ibat-lvl1 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&bcl_sensor 1>; @@ -664,7 +668,7 @@ }; pmi632-vbat-lvl0 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&bcl_sensor 2>; @@ -681,7 +685,7 @@ }; pmi632-vbat-lvl1 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&bcl_sensor 3>; @@ -698,7 +702,7 @@ }; pmi632-vbat-lvl2 { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&bcl_sensor 4>; @@ -714,54 +718,6 @@ }; }; - pmi632-bcl-lvl0 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&bcl_sensor 5>; - wake-capable-sensor; - - trips { - bcl_lvl0: bcl-lvl0 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - - pmi632-bcl-lvl1 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&bcl_sensor 6>; - wake-capable-sensor; - - trips { - bcl_lvl1: bcl-lvl1 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - - pmi632-bcl-lvl2 { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-governor = "step_wise"; - thermal-sensors = <&bcl_sensor 7>; - wake-capable-sensor; - - trips { - bcl_lvl2: bcl-lvl2 { - temperature = <1>; - hysteresis = <1>; - type = "passive"; - }; - }; - }; - soc { polling-delay-passive = <100>; polling-delay = <0>; diff --git a/arch/arm64/boot/dts/qcom/qcs401.dtsi b/arch/arm64/boot/dts/qcom/qcs401.dtsi index 06387ed9e2e3..abf0c5893a2b 100644 --- a/arch/arm64/boot/dts/qcom/qcs401.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs401.dtsi @@ -11,7 +11,7 @@ * GNU General Public License for more details. */ -#include "qcs403.dtsi" +#include "qcs405.dtsi" / { model = "Qualcomm Technologies, Inc. QCS401"; @@ -20,5 +20,29 @@ }; &soc { - /delete-node/ qcom,turing@800000; + /delete-node/ qcom,msm-cpufreq; + + msm_cpufreq: qcom,msm-cpufreq { + compatible = "qcom,msm-cpufreq"; + clock-names = "cpu0_clk"; + clocks = <&clock_cpu APCS_MUX_CLK>; + + qcom,cpufreq-table = + < 1094400 >, + < 1248000 >, + < 1401600 >; + }; + + /delete-node/ qcom,cpu0-computemon; + + cpu0_computemon: qcom,cpu0-computemon { + compatible = "qcom,arm-cpu-mon"; + qcom,cpulist = <&CPU0 &CPU1>; + qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; + qcom,core-dev-table = + < 1094400 MHZ_TO_MBPS( 297, 8) >, + < 1248000 MHZ_TO_MBPS( 597, 8) >, + < 1401600 MHZ_TO_MBPS( 710, 8) >; + }; }; + diff --git a/arch/arm64/boot/dts/qcom/qcs403-iot-sku1.dts b/arch/arm64/boot/dts/qcom/qcs403-iot-sku1.dts index 34de78d0baf6..bcf65cf5aa3e 100644 --- a/arch/arm64/boot/dts/qcom/qcs403-iot-sku1.dts +++ b/arch/arm64/boot/dts/qcom/qcs403-iot-sku1.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -22,6 +22,61 @@ compatible = "qcom,qcs403-iot", "qcom,qcs403", "qcom,iot"; qcom,board-id = <0x010020 0x3>; + cpus { + /delete-node/ cpu@102; + /delete-node/ cpu@103; + + cpu-map { + cluster0 { + /delete-node/ core2; + /delete-node/ core3; + }; + }; + }; +}; + +&soc { + cpuss_dump { + /delete-node/ qcom,l1_i_cache102; + /delete-node/ qcom,l1_i_cache103; + /delete-node/ qcom,l1_d_cache102; + /delete-node/ qcom,l1_d_cache103; + }; + + qcom,spm@b012000 { + qcom,cpu-vctl-list = <&CPU0 &CPU1>; + }; + + qcom,lpm-levels { + qcom,pm-cluster@0{ + qcom,pm-cpu { + qcom,cpu = <&CPU0 &CPU1>; + }; + }; + }; + + /delete-node/ cti@61ba000; + /delete-node/ cti@61bb000; + /delete-node/ etm@61be000; + /delete-node/ etm@61bf000; + funnel@61a1000 { + ports { + /delete-node/ port@3; + /delete-node/ port@4; + }; + }; +}; + +&thermal_zones { + cpuss-max-step { + cooling-maps { + /delete-node/ cpu2_cdev; + /delete-node/ cpu3_cdev; + }; + }; + + /delete-node/ cpuss-2-step; + /delete-node/ cpuss-3-step; }; &qnand_1 { diff --git a/arch/arm64/boot/dts/qcom/qcs403-iot-sku2.dts b/arch/arm64/boot/dts/qcom/qcs403-iot-sku2.dts index c782e1d43ca4..4220f8e48ef5 100644 --- a/arch/arm64/boot/dts/qcom/qcs403-iot-sku2.dts +++ b/arch/arm64/boot/dts/qcom/qcs403-iot-sku2.dts @@ -22,6 +22,61 @@ compatible = "qcom,qcs403-iot", "qcom,qcs403", "qcom,iot"; qcom,board-id = <0x010015 0x0>; + cpus { + /delete-node/ cpu@102; + /delete-node/ cpu@103; + + cpu-map { + cluster0 { + /delete-node/ core2; + /delete-node/ core3; + }; + }; + }; +}; + +&soc { + cpuss_dump { + /delete-node/ qcom,l1_i_cache102; + /delete-node/ qcom,l1_i_cache103; + /delete-node/ qcom,l1_d_cache102; + /delete-node/ qcom,l1_d_cache103; + }; + + qcom,spm@b012000 { + qcom,cpu-vctl-list = <&CPU0 &CPU1>; + }; + + qcom,lpm-levels { + qcom,pm-cluster@0{ + qcom,pm-cpu { + qcom,cpu = <&CPU0 &CPU1>; + }; + }; + }; + + /delete-node/ cti@61ba000; + /delete-node/ cti@61bb000; + /delete-node/ etm@61be000; + /delete-node/ etm@61bf000; + funnel@61a1000 { + ports { + /delete-node/ port@3; + /delete-node/ port@4; + }; + }; +}; + +&thermal_zones { + cpuss-max-step { + cooling-maps { + /delete-node/ cpu2_cdev; + /delete-node/ cpu3_cdev; + }; + }; + + /delete-node/ cpuss-2-step; + /delete-node/ cpuss-3-step; }; #include "qcs405-mdss-panels.dtsi" diff --git a/arch/arm64/boot/dts/qcom/qcs403-iot-sku3.dts b/arch/arm64/boot/dts/qcom/qcs403-iot-sku3.dts index 7497da5aad38..637d94ce2e50 100644 --- a/arch/arm64/boot/dts/qcom/qcs403-iot-sku3.dts +++ b/arch/arm64/boot/dts/qcom/qcs403-iot-sku3.dts @@ -22,9 +22,50 @@ compatible = "qcom,qcs403-iot", "qcom,qcs403", "qcom,iot"; qcom,board-id = <0x010020 0x4>; + cpus { + /delete-node/ cpu@102; + /delete-node/ cpu@103; + + cpu-map { + cluster0 { + /delete-node/ core2; + /delete-node/ core3; + }; + }; + }; }; &soc { + cpuss_dump { + /delete-node/ qcom,l1_i_cache102; + /delete-node/ qcom,l1_i_cache103; + /delete-node/ qcom,l1_d_cache102; + /delete-node/ qcom,l1_d_cache103; + }; + + qcom,spm@b012000 { + qcom,cpu-vctl-list = <&CPU0 &CPU1>; + }; + + qcom,lpm-levels { + qcom,pm-cluster@0{ + qcom,pm-cpu { + qcom,cpu = <&CPU0 &CPU1>; + }; + }; + }; + + /delete-node/ cti@61ba000; + /delete-node/ cti@61bb000; + /delete-node/ etm@61be000; + /delete-node/ etm@61bf000; + funnel@61a1000 { + ports { + /delete-node/ port@3; + /delete-node/ port@4; + }; + }; + spi@78b5000 { status = "ok"; spi@0 { @@ -41,6 +82,18 @@ }; }; +&thermal_zones { + cpuss-max-step { + cooling-maps { + /delete-node/ cpu2_cdev; + /delete-node/ cpu3_cdev; + }; + }; + + /delete-node/ cpuss-2-step; + /delete-node/ cpuss-3-step; +}; + &qnand_1 { status = "ok"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs403-iot-sku4.dts b/arch/arm64/boot/dts/qcom/qcs403-iot-sku4.dts index bbc81eb229ed..77ac0f29bb32 100644 --- a/arch/arm64/boot/dts/qcom/qcs403-iot-sku4.dts +++ b/arch/arm64/boot/dts/qcom/qcs403-iot-sku4.dts @@ -22,9 +22,50 @@ compatible = "qcom,qcs403-iot", "qcom,qcs403", "qcom,iot"; qcom,board-id = <0x010020 0x5>; + cpus { + /delete-node/ cpu@102; + /delete-node/ cpu@103; + + cpu-map { + cluster0 { + /delete-node/ core2; + /delete-node/ core3; + }; + }; + }; }; &soc { + cpuss_dump { + /delete-node/ qcom,l1_i_cache102; + /delete-node/ qcom,l1_i_cache103; + /delete-node/ qcom,l1_d_cache102; + /delete-node/ qcom,l1_d_cache103; + }; + + qcom,spm@b012000 { + qcom,cpu-vctl-list = <&CPU0 &CPU1>; + }; + + qcom,lpm-levels { + qcom,pm-cluster@0{ + qcom,pm-cpu { + qcom,cpu = <&CPU0 &CPU1>; + }; + }; + }; + + /delete-node/ cti@61ba000; + /delete-node/ cti@61bb000; + /delete-node/ etm@61be000; + /delete-node/ etm@61bf000; + funnel@61a1000 { + ports { + /delete-node/ port@3; + /delete-node/ port@4; + }; + }; + gpio_keys { vol_mute { gpios = <&tlmm 19 GPIO_ACTIVE_LOW>; @@ -32,6 +73,18 @@ }; }; +&thermal_zones { + cpuss-max-step { + cooling-maps { + /delete-node/ cpu2_cdev; + /delete-node/ cpu3_cdev; + }; + }; + + /delete-node/ cpuss-2-step; + /delete-node/ cpuss-3-step; +}; + &qnand_1 { status = "ok"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs403.dtsi b/arch/arm64/boot/dts/qcom/qcs403.dtsi index 70f1c135f7db..c5058cbaec53 100644 --- a/arch/arm64/boot/dts/qcom/qcs403.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs403.dtsi @@ -17,48 +17,20 @@ model = "Qualcomm Technologies, Inc. QCS403"; qcom,msm-name = "QCS403"; qcom,msm-id = <373 0x0>; - - cpus { - /delete-node/ cpu@102; - /delete-node/ cpu@103; - cpu-map { - cluster0 { - /delete-node/ core2; - /delete-node/ core3; - }; - }; - }; - }; &soc { + /delete-node/ qcom,msm-cpufreq; - cpuss_dump { - /delete-node/ qcom,l1_i_cache102; - /delete-node/ qcom,l1_i_cache103; - /delete-node/ qcom,l1_d_cache102; - /delete-node/ qcom,l1_d_cache103; - }; - qcom,spm@b012000 { - qcom,cpu-vctl-list = <&CPU0 &CPU1>; - }; - qcom,lpm-levels { - qcom,pm-cluster@0{ - qcom,pm-cpu { - qcom,cpu = <&CPU0 &CPU1>; - }; - }; - }; - /delete-node/ cti@61ba000; - /delete-node/ cti@61bb000; - /delete-node/ etm@61be000; - /delete-node/ etm@61bf000; + msm_cpufreq: qcom,msm-cpufreq { + compatible = "qcom,msm-cpufreq"; + clock-names = "cpu0_clk"; + clocks = <&clock_cpu APCS_MUX_CLK>; - funnel@61a1000 { - ports { - /delete-node/ port@3; - /delete-node/ port@4; - }; + qcom,cpufreq-table = + < 1094400 >, + < 1248000 >, + < 1401600 >; }; /delete-node/ qcom,cpu0-computemon; @@ -74,17 +46,6 @@ }; }; -&thermal_zones { - cpuss-max-step { - cooling-maps { - /delete-node/ cpu2_cdev; - /delete-node/ cpu3_cdev; - }; - }; - /delete-node/ cpuss-2-step; - /delete-node/ cpuss-3-step; -}; - &adsp_fw_mem { reg = <0x0 0x87400000 0x0 0x1200000>; }; diff --git a/arch/arm64/boot/dts/qcom/qcs405-linear-pca9956.dtsi b/arch/arm64/boot/dts/qcom/qcs405-linear-pca9956.dtsi index 6980899b38ba..aa18e3b0ddd7 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-linear-pca9956.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-linear-pca9956.dtsi @@ -11,6 +11,10 @@ * GNU General Public License for more details. */ +&va_macro { + qcom,va-dmic-sample-rate = <2400000>; +}; + &i2c_2 { status = "ok"; qcom,clk-freq-out = <100000>; diff --git a/arch/arm64/boot/dts/qcom/qcs405-mhi.dtsi b/arch/arm64/boot/dts/qcom/qcs405-mhi.dtsi new file mode 100644 index 000000000000..12ba814820f3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs405-mhi.dtsi @@ -0,0 +1,716 @@ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&pcie_rc0 { + reg = <0 0 0 0 0>; + + mhi_0: qcom,mhi@0 { + reg = <0 0 0 0 0 >; + + pci-ids = "17cb:0304"; + + /* controller specific configuration */ + qcom,smmu-cfg = <0x0>; + qcom,msm-bus,name = "mhi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 1200000000 650000000>; + + /* mhi bus specific settings */ + mhi,max-channels = <110>; + mhi,timeout = <2000>; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@14 { + reg = <14>; + label = "QMI0"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@15 { + reg = <15>; + label = "QMI0"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@16 { + reg = <16>; + label = "QMI1"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@17 { + reg = <17>; + label = "QMI1"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,auto-queue; + mhi,auto-start; + }; + + mhi_chan@32 { + reg = <32>; + label = "DUN"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@33 { + reg = <33>; + label = "DUN"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@46 { + reg = <46>; + label = "IP_SW_0"; + mhi,num-elements = <512>; + mhi,event-ring = <4>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@47 { + reg = <47>; + label = "IP_SW_0"; + mhi,num-elements = <512>; + mhi,event-ring = <5>; + mhi,chan-dir = <2>; + mhi,data-type = <4>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@100 { + reg = <100>; + label = "IP_HW0"; + mhi,num-elements = <512>; + mhi,event-ring = <6>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <3>; + mhi,ee = <0x4>; + mhi,db-mode-switch; + }; + + mhi_chan@101 { + reg = <101>; + label = "IP_HW0"; + mhi,num-elements = <512>; + mhi,event-ring = <7>; + mhi,chan-dir = <2>; + mhi,data-type = <4>; + mhi,doorbell-mode = <3>; + mhi,ee = <0x4>; + }; + + mhi_chan@105 { + reg = <105>; + label = "IP_HW1"; + mhi,num-elements = <512>; + mhi,event-ring = <8>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@106 { + reg = <106>; + label = "IP_HW1"; + mhi,num-elements = <512>; + mhi,event-ring = <9>; + mhi,chan-dir = <2>; + mhi,data-type = <4>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@2 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <3>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@3 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <4>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@4 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <5>; + mhi,chan = <46>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@5 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <6>; + mhi,chan = <47>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,client-manage; + }; + + mhi_event@6 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <5>; + mhi,chan = <100>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + }; + + mhi_event@7 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <6>; + mhi,chan = <101>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + }; + + mhi_event@8 { + mhi,num-elements = <1024>; + mhi,intmod = <0>; + mhi,msi = <7>; + mhi,chan = <105>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,hw-ev; + }; + + mhi_event@9 { + mhi,num-elements = <1024>; + mhi,intmod = <0>; + mhi,msi = <8>; + mhi,chan = <106>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,hw-ev; + mhi,client-manage; + }; + }; + + mhi_devices { + #address-cells = <1>; + #size-cells = <0>; + mhi_netdev_0: mhi_rmnet@0 { + reg = <0x0>; + mhi,chan = "IP_HW0"; + mhi,interface-name = "rmnet_mhi"; + mhi,mru = <0x8000>; + mhi,disable-chain-skb; + }; + + mhi_netdev_1: mhi_rmnet@1 { + reg = <0x1>; + mhi,chan = "IP_HW1"; + mhi,interface-name = "rmnet_mhi"; + mhi,mru = <0x8000>; + mhi,disable-chain-skb; + }; + + mhi_netdev_2: mhi_rmnet@2 { + reg = <0x2>; + mhi,chan = "IP_SW_0"; + mhi,interface-name = "mhi_swip"; + mhi,mru = <0x4000>; + mhi,ethernet-interface; + mhi,disable-chain-skb; + }; + }; + }; + + mhi_1: qcom,mhi@1 { + reg = <0 0 0 0 0 >; + + pci-ids = "17cb:0306"; + + /* controller specific configuration */ + qcom,smmu-cfg = <0x0>; + qcom,msm-bus,name = "mhi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 1200000000 650000000>; + + /* mhi bus specific settings */ + mhi,max-channels = <110>; + mhi,timeout = <2000>; + + mhi_channels { + #address-cells = <1>; + #size-cells = <0>; + mhi_chan@0 { + reg = <0>; + label = "LOOPBACK"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@1 { + reg = <1>; + label = "LOOPBACK"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@4 { + reg = <4>; + label = "DIAG"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@5 { + reg = <5>; + label = "DIAG"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@14 { + reg = <14>; + label = "QMI0"; + mhi,num-elements = <64>; + mhi,event-ring = <1>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@15 { + reg = <15>; + label = "QMI0"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@16 { + reg = <16>; + label = "QMI1"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@17 { + reg = <17>; + label = "QMI1"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@20 { + reg = <20>; + label = "IPCR"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,auto-start; + }; + + mhi_chan@21 { + reg = <21>; + label = "IPCR"; + mhi,num-elements = <64>; + mhi,event-ring = <2>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + mhi,auto-queue; + mhi,auto-start; + }; + + mhi_chan@32 { + reg = <32>; + label = "DUN"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <1>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@33 { + reg = <33>; + label = "DUN"; + mhi,num-elements = <64>; + mhi,event-ring = <3>; + mhi,chan-dir = <2>; + mhi,data-type = <0>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@46 { + reg = <46>; + label = "IP_SW_0"; + mhi,num-elements = <512>; + mhi,event-ring = <4>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@47 { + reg = <47>; + label = "IP_SW_0"; + mhi,num-elements = <512>; + mhi,event-ring = <5>; + mhi,chan-dir = <2>; + mhi,data-type = <4>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@100 { + reg = <100>; + label = "IP_HW0"; + mhi,num-elements = <512>; + mhi,event-ring = <6>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <3>; + mhi,ee = <0x4>; + mhi,db-mode-switch; + }; + + mhi_chan@101 { + reg = <101>; + label = "IP_HW0"; + mhi,num-elements = <512>; + mhi,event-ring = <7>; + mhi,chan-dir = <2>; + mhi,data-type = <4>; + mhi,doorbell-mode = <3>; + mhi,ee = <0x4>; + }; + + mhi_chan@105 { + reg = <105>; + label = "IP_HW1"; + mhi,num-elements = <512>; + mhi,event-ring = <8>; + mhi,chan-dir = <1>; + mhi,data-type = <1>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + + mhi_chan@106 { + reg = <106>; + label = "IP_HW1"; + mhi,num-elements = <512>; + mhi,event-ring = <9>; + mhi,chan-dir = <2>; + mhi,data-type = <4>; + mhi,doorbell-mode = <2>; + mhi,ee = <0x4>; + }; + }; + + mhi_events { + mhi_event@0 { + mhi,num-elements = <32>; + mhi,intmod = <1>; + mhi,msi = <1>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,data-type = <1>; + }; + + mhi_event@1 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <2>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@2 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <3>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@3 { + mhi,num-elements = <256>; + mhi,intmod = <1>; + mhi,msi = <4>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@4 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <5>; + mhi,chan = <46>; + mhi,priority = <1>; + mhi,brstmode = <2>; + }; + + mhi_event@5 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <6>; + mhi,chan = <47>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,client-manage; + }; + + mhi_event@6 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <5>; + mhi,chan = <100>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + }; + + mhi_event@7 { + mhi,num-elements = <1024>; + mhi,intmod = <5>; + mhi,msi = <6>; + mhi,chan = <101>; + mhi,priority = <1>; + mhi,brstmode = <3>; + mhi,hw-ev; + mhi,client-manage; + }; + + mhi_event@8 { + mhi,num-elements = <1024>; + mhi,intmod = <0>; + mhi,msi = <7>; + mhi,chan = <105>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,hw-ev; + }; + + mhi_event@9 { + mhi,num-elements = <1024>; + mhi,intmod = <0>; + mhi,msi = <8>; + mhi,chan = <106>; + mhi,priority = <1>; + mhi,brstmode = <2>; + mhi,hw-ev; + mhi,client-manage; + }; + }; + + mhi_devices { + #address-cells = <1>; + #size-cells = <0>; + mhi_netdev_3: mhi_rmnet@0 { + reg = <0x0>; + mhi,chan = "IP_HW0"; + mhi,interface-name = "rmnet_mhi"; + mhi,mru = <0x8000>; + mhi,disable-chain-skb; + }; + + mhi_netdev_4: mhi_rmnet@1 { + reg = <0x1>; + mhi,chan = "IP_HW1"; + mhi,interface-name = "rmnet_mhi"; + mhi,mru = <0x8000>; + mhi,disable-chain-skb; + }; + + mhi_netdev_5: mhi_rmnet@2 { + reg = <0x2>; + mhi,chan = "IP_SW_0"; + mhi,interface-name = "mhi_swip"; + mhi,mru = <0x4000>; + mhi,ethernet-interface; + mhi,disable-chain-skb; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs405-pcie.dtsi b/arch/arm64/boot/dts/qcom/qcs405-pcie.dtsi index b8fbb572f023..7ead59ebba67 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-pcie.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-pcie.dtsi @@ -81,9 +81,13 @@ qcom,phy-status-offset = <0x3c>; qcom,phy-status-bit = <0>; qcom,phy-power-down-offset = <0x98>; - qcom,boot-option = <0x1>; + qcom,boot-option = <0x0>; qcom,keep-powerdown-phy; + qcom,no-l0s-supported; + qcom,no-l1-supported; + qcom,no-l1ss-supported; + qcom,no-aux-clk-sync; linux,pci-domain = <0>; diff --git a/arch/arm64/boot/dts/qcom/qcs405-va-bolero.dtsi b/arch/arm64/boot/dts/qcom/qcs405-va-bolero.dtsi index 7b5fa64c4e44..766714c24e6f 100644 --- a/arch/arm64/boot/dts/qcom/qcs405-va-bolero.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405-va-bolero.dtsi @@ -19,7 +19,7 @@ va-vdd-micb-supply = <&pms405_l7>; qcom,va-vdd-micb-voltage = <1800000 1800000>; qcom,va-vdd-micb-current = <9000>; - qcom,va-dmic-sample-rate = <2400000>; + qcom,va-dmic-sample-rate = <600000>; }; }; diff --git a/arch/arm64/boot/dts/qcom/qcs405.dtsi b/arch/arm64/boot/dts/qcom/qcs405.dtsi index c58da349d3b3..a669dcfc8f58 100644 --- a/arch/arm64/boot/dts/qcom/qcs405.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs405.dtsi @@ -139,6 +139,13 @@ sdhc2 = &sdhc_2; /* SDC2 SD Card slot */ qpic_nand1 = &qnand_1; pci-domain0 = &pcie0; /* PCIe0 domain */ + mhi0 = &mhi_0; + mhi_netdev0 = &mhi_netdev_0; + mhi_netdev1 = &mhi_netdev_1; + mhi_netdev2 = &mhi_netdev_2; + mhi_netdev3 = &mhi_netdev_3; + mhi_netdev4 = &mhi_netdev_4; + mhi_netdev5 = &mhi_netdev_5; }; soc: soc { }; @@ -1562,6 +1569,7 @@ #include "qcs405-coresight.dtsi" #include "qcs405-usb.dtsi" #include "qcs405-pcie.dtsi" +#include "qcs405-mhi.dtsi" &i2c_5 { smb1351_otg_supply: smb1351-charger@55 { diff --git a/arch/arm64/boot/dts/qcom/qg-batterydata-atl466271_3300mAh.dtsi b/arch/arm64/boot/dts/qcom/qg-batterydata-atl466271_3300mAh.dtsi deleted file mode 100644 index 470cb0bcb6b5..000000000000 --- a/arch/arm64/boot/dts/qcom/qg-batterydata-atl466271_3300mAh.dtsi +++ /dev/null @@ -1,1054 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -qcom,ATL466271_3300mAh { - /* ATL466271_3300mAh_averaged_MasterSlave_Jun12th2019 */ - qcom,max-voltage-uv = <4400000>; - qcom,fg-cc-cv-threshold-uv = <4390000>; - qcom,fastchg-current-ma = <8000>; - qcom,batt-id-kohm = <24>; - qcom,battery-beta = <4250>; - qcom,battery-therm-kohm = <100>; - qcom,battery-type = - "ATL466271_3300mAh_averaged_MasterSlave_Jun12th2019"; - qcom,qg-batt-profile-ver = <100>; - - qcom,jeita-fcc-ranges = <0 100 1600000 - 101 200 3200000 - 201 450 8000000 - 451 550 1600000>; - - qcom,jeita-fv-ranges = <0 100 4400000 - 101 200 4400000 - 201 450 4400000 - 451 550 4050000>; - - qcom,step-chg-ranges = <3500000 4000000 8000000 - 4001000 4200000 6000000 - 4201000 4400000 4000000>; - qcom,ocv-based-step-chg; - - /* COOL = 10 degc, WARM = 45 degC */ - qcom,jeita-soft-thresholds = <0x4ccc 0x20b8>; - /* COLD = 0 degC, HOT = 55 degC*/ - qcom,jeita-hard-thresholds = <0x58cd 0x181d>; - /* COOL hys = 13 degC, WARM hys = 42 degC */ - qcom,jeita-soft-hys-thresholds = <0x48d4 0x23c0>; - qcom,jeita-soft-fcc-ua = <1600000 1600000>; - qcom,jeita-soft-fv-uv = <4400000 4050000>; - - qcom,fcc1-temp-lut { - qcom,lut-col-legend = <0 10 25 40 50>; - qcom,lut-data = <3191 3260 3320 3354 3366>; - }; - - qcom,fcc2-temp-lut { - qcom,lut-col-legend = <(-10) 0 10 25 40 50>; - qcom,lut-data = <3307 3309 3324 3332 3330 3326>; - }; - - qcom,pc-temp-v1-lut { - qcom,lut-col-legend = <0 10 25 40 50>; - qcom,lut-row-legend = <10000 9800 9600 9400 9200>, - <9000 8800 8600 8400 8200>, - <8000 7800 7600 7400 7200>, - <7000 6800 6600 6400 6200>, - <6000 5800 5600 5400 5200>, - <5000 4800 4600 4400 4200>, - <4000 3800 3600 3400 3200>, - <3000 2800 2600 2400 2200>, - <2000 1800 1600 1400 1200>, - <1000 900 800 700 600>, - <500 400 300 200 100>, - <0>; - qcom,lut-data = <43710 43825 43909 43937 43942>, - <43473 43605 43706 43721 43723>, - <43237 43380 43489 43509 43510>, - <43003 43150 43267 43294 43299>, - <42775 42918 43038 43070 43079>, - <42550 42687 42804 42837 42850>, - <42328 42457 42573 42606 42620>, - <42109 42230 42341 42375 42390>, - <41894 42008 42113 42145 42161>, - <41684 41789 41886 41917 41933>, - <41476 41574 41663 41690 41705>, - <41278 41360 41446 41467 41481>, - <41103 41159 41232 41247 41261>, - <40943 40987 41027 41035 41047>, - <40756 40823 40831 40833 40840>, - <40499 40625 40638 40639 40642>, - <40235 40371 40434 40442 40448>, - <40047 40136 40224 40241 40259>, - <39905 39978 40039 40053 40076>, - <39770 39845 39893 39894 39909>, - <39637 39668 39742 39742 39748>, - <39498 39402 39527 39546 39554>, - <39319 39159 39260 39286 39299>, - <39057 39018 39056 39062 39070>, - <38841 38914 38916 38909 38913>, - <38748 38814 38798 38783 38786>, - <38688 38714 38686 38668 38667>, - <38628 38621 38584 38566 38559>, - <38566 38536 38491 38471 38460>, - <38504 38459 38406 38380 38367>, - <38445 38391 38330 38297 38282>, - <38388 38330 38261 38223 38205>, - <38337 38276 38199 38156 38134>, - <38292 38228 38143 38095 38068>, - <38251 38187 38095 38043 38009>, - <38214 38146 38049 37992 37951>, - <38182 38111 38004 37933 37881>, - <38143 38071 37958 37869 37800>, - <38074 38006 37895 37793 37711>, - <37974 37903 37802 37697 37614>, - <37864 37788 37692 37587 37506>, - <37736 37663 37571 37457 37376>, - <37592 37522 37433 37310 37228>, - <37427 37351 37270 37152 37071>, - <37293 37218 37135 37037 36964>, - <37218 37148 37061 36976 36918>, - <37197 37127 37043 36958 36899>, - <37176 37114 37027 36945 36884>, - <37152 37086 37005 36915 36845>, - <37053 36954 36879 36723 36623>, - <36674 36578 36526 36347 36242>, - <36195 36086 36041 35859 35751>, - <35574 35449 35427 35229 35116>, - <34729 34574 34574 34362 34242>, - <33401 33172 33225 32989 32851>, - <30000 30000 30000 30000 30000>; - }; - - qcom,pc-temp-v2-lut { - qcom,lut-col-legend = <(-10) 0 10 25 40 50>; - qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, - <8800 8600 8400 8200 8000 7800>, - <7600 7400 7200 7000 6800 6600>, - <6400 6200 6000 5800 5600 5400>, - <5200 5000 4800 4600 4400 4200>, - <4000 3800 3600 3400 3200 3000>, - <2800 2600 2400 2200 2000 1800>, - <1600 1400 1200 1000 900 800>, - <700 600 500 400 300 200>, - <100 0>; - qcom,lut-data = <43975 43950 43930 43905 43855 43835>, - <43614 43647 43667 43663 43617 43596>, - <43279 43361 43410 43424 43383 43362>, - <42972 43092 43162 43188 43150 43130>, - <42688 42841 42921 42956 42921 42903>, - <42432 42596 42682 42724 42691 42675>, - <42220 42350 42446 42490 42458 42443>, - <42020 42110 42212 42257 42225 42210>, - <41772 41881 41982 42027 41995 41980>, - <41458 41662 41755 41799 41766 41751>, - <41235 41448 41531 41574 41541 41526>, - <41153 41235 41310 41352 41318 41305>, - <41088 41026 41094 41134 41100 41087>, - <40904 40832 40899 40930 40893 40877>, - <40447 40653 40720 40736 40694 40672>, - <40034 40458 40525 40537 40495 40472>, - <39788 40221 40292 40319 40288 40277>, - <39585 39967 40050 40106 40087 40088>, - <39406 39734 39841 39926 39912 39913>, - <39248 39515 39652 39767 39754 39750>, - <39074 39305 39456 39583 39572 39566>, - <38832 39100 39232 39336 39328 39323>, - <38584 38908 39017 39089 39082 39080>, - <38426 38747 38845 38906 38903 38901>, - <38310 38609 38699 38752 38755 38754>, - <38226 38477 38570 38621 38627 38625>, - <38164 38335 38453 38506 38513 38511>, - <38113 38204 38348 38403 38410 38407>, - <38062 38112 38253 38308 38314 38311>, - <38014 38043 38166 38221 38224 38220>, - <37968 37988 38082 38140 38142 38137>, - <37925 37942 37996 38064 38067 38062>, - <37882 37901 37921 37993 37995 37989>, - <37836 37861 37870 37925 37926 37914>, - <37789 37823 37831 37859 37858 37837>, - <37739 37781 37790 37789 37775 37745>, - <37688 37735 37747 37715 37668 37625>, - <37631 37682 37698 37637 37559 37505>, - <37562 37619 37632 37559 37469 37410>, - <37480 37542 37547 37477 37386 37325>, - <37385 37449 37447 37382 37290 37228>, - <37268 37321 37322 37269 37178 37113>, - <37144 37177 37181 37135 37045 36979>, - <37027 37026 37025 36987 36895 36830>, - <36932 36918 36939 36908 36841 36784>, - <36855 36857 36899 36885 36818 36762>, - <36812 36827 36875 36867 36801 36749>, - <36761 36786 36846 36843 36779 36722>, - <36679 36721 36775 36779 36692 36597>, - <36475 36551 36546 36552 36390 36264>, - <36066 36173 36127 36133 35937 35797>, - <35499 35647 35579 35596 35370 35211>, - <34766 34968 34863 34909 34633 34453>, - <33784 34024 33935 33996 33658 33408>, - <32412 32711 32567 32650 31840 31311>, - <28215 28831 27522 28579 27814 27518>; - }; - - qcom,pc-temp-z1-lut { - qcom,lut-col-legend = <0 10 25 40 50>; - qcom,lut-row-legend = <10000 9800 9600 9400 9200>, - <9000 8800 8600 8400 8200>, - <8000 7800 7600 7400 7200>, - <7000 6800 6600 6400 6200>, - <6000 5800 5600 5400 5200>, - <5000 4800 4600 4400 4200>, - <4000 3800 3600 3400 3200>, - <3000 2800 2600 2400 2200>, - <2000 1800 1600 1400 1200>, - <1000 900 800 700 600>, - <500 400 300 200 100>, - <0>; - qcom,lut-data = <11770 11167 10508 10200 10123>, - <11802 11193 10579 10273 10190>, - <11806 11200 10581 10275 10191>, - <11805 11183 10570 10275 10191>, - <11792 11170 10557 10270 10189>, - <11777 11154 10545 10264 10185>, - <11765 11131 10537 10259 10182>, - <11755 11116 10530 10255 10180>, - <11743 11111 10524 10251 10178>, - <11735 11108 10520 10250 10177>, - <11730 11108 10517 10249 10175>, - <11726 11108 10514 10248 10174>, - <11721 11108 10512 10248 10173>, - <11717 11105 10511 10247 10173>, - <11714 11099 10510 10247 10172>, - <11704 11097 10508 10245 10172>, - <11693 11095 10507 10245 10172>, - <11693 11095 10506 10245 10172>, - <11704 11097 10506 10246 10174>, - <11714 11101 10509 10248 10175>, - <11726 11106 10513 10252 10177>, - <11741 11114 10517 10254 10179>, - <11744 11122 10522 10256 10181>, - <11737 11128 10527 10258 10183>, - <11732 11133 10532 10260 10185>, - <11733 11134 10537 10264 10187>, - <11737 11132 10542 10267 10190>, - <11740 11131 10548 10272 10194>, - <11743 11133 10553 10276 10197>, - <11747 11137 10558 10280 10200>, - <11750 11142 10564 10285 10203>, - <11754 11154 10571 10288 10206>, - <11758 11165 10579 10292 10209>, - <11769 11165 10584 10296 10213>, - <11781 11161 10589 10301 10217>, - <11789 11159 10594 10306 10221>, - <11796 11169 10600 10312 10225>, - <11803 11182 10606 10317 10229>, - <11809 11185 10612 10322 10233>, - <11816 11186 10619 10326 10236>, - <11819 11188 10625 10330 10239>, - <11821 11199 10630 10335 10243>, - <11823 11208 10636 10340 10246>, - <11826 11206 10642 10342 10248>, - <11820 11215 10648 10344 10249>, - <11820 11220 10655 10347 10250>, - <11830 11225 10660 10348 10252>, - <11816 11232 10658 10350 10253>, - <11831 11224 10662 10354 10257>, - <11856 11221 10671 10358 10261>, - <11833 11233 10673 10362 10265>, - <11848 11251 10678 10368 10270>, - <11885 11257 10688 10374 10275>, - <11898 11288 10702 10382 10282>, - <11898 11288 10702 10382 10282>, - <11898 11288 10702 10382 10282>; - }; - - qcom,pc-temp-z2-lut { - qcom,lut-col-legend = <0 10 25 40 50>; - qcom,lut-row-legend = <10000 9800 9600 9400 9200>, - <9000 8800 8600 8400 8200>, - <8000 7800 7600 7400 7200>, - <7000 6800 6600 6400 6200>, - <6000 5800 5600 5400 5200>, - <5000 4800 4600 4400 4200>, - <4000 3800 3600 3400 3200>, - <3000 2800 2600 2400 2200>, - <2000 1800 1600 1400 1200>, - <1000 900 800 700 600>, - <500 400 300 200 100>, - <0>; - qcom,lut-data = <9894 9757 10034 10106 10345>, - <9913 9932 10014 10164 10226>, - <9939 10003 10052 10124 10214>, - <9961 9993 10069 10079 10205>, - <9956 9975 10063 10081 10205>, - <9932 9968 10050 10100 10208>, - <9909 9964 10028 10116 10214>, - <9894 9962 9988 10127 10224>, - <9882 9965 9971 10137 10239>, - <9879 9971 9979 10146 10256>, - <9887 9975 9990 10155 10278>, - <9899 9978 9996 10160 10293>, - <9908 9983 10003 10160 10302>, - <9915 10111 10010 10159 10307>, - <9923 10305 10017 10164 10303>, - <9937 10319 10021 10171 10296>, - <9949 10152 10020 10170 10294>, - <9950 10028 10015 10163 10294>, - <9944 10019 10013 10158 10295>, - <9940 10013 10022 10178 10307>, - <9940 10015 10039 10212 10331>, - <9943 10049 10081 10217 10334>, - <9948 10079 10155 10205 10297>, - <9962 10074 10180 10185 10246>, - <9973 10059 10141 10123 10180>, - <9974 10052 10094 10050 10113>, - <9972 10052 10070 10041 10102>, - <9972 10053 10053 10046 10113>, - <9973 10046 10049 10054 10127>, - <9975 10033 10060 10064 10141>, - <9976 10029 10075 10077 10158>, - <9978 10038 10091 10098 10180>, - <9980 10052 10108 10129 10208>, - <9983 10064 10127 10163 10243>, - <9988 10077 10148 10206 10293>, - <9992 10087 10168 10244 10345>, - <9997 10095 10183 10263 10380>, - <10003 10102 10195 10276 10409>, - <10012 10114 10208 10287 10417>, - <10023 10130 10226 10298 10403>, - <10024 10137 10237 10306 10390>, - <10014 10120 10220 10308 10389>, - <10008 10106 10192 10307 10384>, - <10006 10106 10186 10298 10361>, - <10058 10124 10199 10299 10329>, - <10061 10124 10204 10309 10360>, - <10054 10113 10214 10301 10359>, - <10052 10093 10207 10352 10392>, - <10039 10104 10227 10397 10452>, - <9972 10155 10228 10268 10254>, - <10081 10129 10171 10193 10218>, - <10034 10095 10128 10161 10175>, - <9993 10043 10103 10128 10146>, - <9836 9993 10057 10083 10063>, - <9836 9993 10057 10083 10063>, - <9836 9993 10057 10083 10063>; - }; - - qcom,pc-temp-z3-lut { - qcom,lut-col-legend = <0 10 25 40 50>; - qcom,lut-row-legend = <10000 9800 9600 9400 9200>, - <9000 8800 8600 8400 8200>, - <8000 7800 7600 7400 7200>, - <7000 6800 6600 6400 6200>, - <6000 5800 5600 5400 5200>, - <5000 4800 4600 4400 4200>, - <4000 3800 3600 3400 3200>, - <3000 2800 2600 2400 2200>, - <2000 1800 1600 1400 1200>, - <1000 900 800 700 600>, - <500 400 300 200 100>, - <0>; - qcom,lut-data = <19500 19444 19370 19351 19313>, - <19626 19520 19402 19353 19340>, - <19677 19560 19426 19362 19348>, - <19706 19570 19435 19369 19353>, - <19708 19575 19432 19369 19353>, - <19704 19574 19427 19367 19351>, - <19701 19566 19421 19364 19348>, - <19699 19557 19414 19360 19345>, - <19697 19549 19409 19355 19341>, - <19692 19541 19406 19353 19340>, - <19680 19535 19404 19352 19339>, - <19665 19529 19401 19351 19338>, - <19649 19525 19397 19351 19337>, - <19632 19526 19395 19351 19336>, - <19625 19529 19394 19350 19335>, - <19632 19529 19394 19349 19331>, - <19639 19523 19394 19348 19329>, - <19638 19517 19394 19347 19327>, - <19628 19510 19394 19345 19325>, - <19621 19502 19390 19341 19323>, - <19618 19501 19385 19335 19320>, - <19616 19515 19389 19337 19322>, - <19618 19527 19402 19355 19339>, - <19632 19520 19415 19369 19354>, - <19643 19503 19428 19376 19357>, - <19638 19499 19437 19380 19359>, - <19626 19519 19437 19380 19359>, - <19619 19539 19434 19373 19356>, - <19618 19539 19430 19368 19353>, - <19618 19535 19425 19366 19350>, - <19619 19530 19418 19364 19347>, - <19621 19524 19413 19362 19343>, - <19622 19517 19409 19358 19340>, - <19621 19512 19405 19354 19336>, - <19618 19508 19401 19349 19331>, - <19615 19505 19398 19346 19328>, - <19611 19503 19397 19346 19330>, - <19607 19500 19396 19347 19336>, - <19603 19497 19395 19348 19339>, - <19597 19494 19393 19350 19339>, - <19593 19490 19390 19351 19339>, - <19592 19487 19386 19352 19339>, - <19588 19483 19383 19353 19339>, - <19579 19481 19385 19354 19341>, - <19543 19466 19382 19350 19341>, - <19529 19450 19368 19337 19321>, - <19525 19448 19365 19331 19318>, - <19523 19438 19363 19324 19312>, - <19489 19434 19359 19320 19312>, - <19401 19438 19363 19342 19330>, - <19514 19442 19376 19345 19331>, - <19508 19444 19378 19345 19332>, - <19506 19447 19381 19346 19334>, - <19479 19451 19379 19353 19342>, - <19479 19451 19379 19353 19342>, - <19479 19451 19379 19353 19342>; - }; - - qcom,pc-temp-z4-lut { - qcom,lut-col-legend = <0 10 25 40 50>; - qcom,lut-row-legend = <10000 9800 9600 9400 9200>, - <9000 8800 8600 8400 8200>, - <8000 7800 7600 7400 7200>, - <7000 6800 6600 6400 6200>, - <6000 5800 5600 5400 5200>, - <5000 4800 4600 4400 4200>, - <4000 3800 3600 3400 3200>, - <3000 2800 2600 2400 2200>, - <2000 1800 1600 1400 1200>, - <1000 900 800 700 600>, - <500 400 300 200 100>, - <0>; - qcom,lut-data = <15847 15406 14998 14784 14808>, - <15949 15355 15044 14878 14825>, - <15794 15280 14959 14838 14798>, - <15524 15160 14880 14782 14745>, - <15335 15024 14821 14755 14725>, - <15199 14932 14776 14735 14717>, - <15092 14862 14760 14724 14712>, - <15007 14818 14752 14719 14708>, - <14938 14795 14745 14715 14704>, - <14892 14781 14736 14710 14700>, - <14861 14774 14728 14704 14696>, - <14839 14771 14722 14699 14691>, - <14823 14768 14716 14693 14687>, - <14809 14746 14714 14688 14682>, - <14805 14717 14714 14683 14677>, - <14837 14717 14714 14679 14672>, - <14877 14763 14713 14676 14669>, - <14877 14798 14707 14672 14666>, - <14845 14782 14700 14669 14663>, - <14819 14748 14691 14667 14660>, - <14809 14748 14684 14665 14657>, - <14802 14849 14717 14676 14662>, - <14817 14940 14810 14736 14713>, - <14926 14941 14844 14773 14752>, - <15018 14932 14810 14755 14738>, - <15011 14916 14769 14725 14711>, - <14979 14870 14751 14712 14699>, - <14949 14826 14739 14706 14693>, - <14922 14811 14733 14701 14688>, - <14898 14803 14730 14696 14684>, - <14881 14800 14728 14693 14681>, - <14867 14800 14728 14691 14678>, - <14859 14800 14727 14689 14675>, - <14855 14800 14728 14689 14674>, - <14853 14801 14730 14689 14673>, - <14850 14801 14732 14690 14672>, - <14845 14800 14733 14694 14676>, - <14843 14799 14734 14701 14687>, - <14846 14800 14735 14703 14692>, - <14851 14805 14736 14701 14691>, - <14852 14807 14737 14699 14691>, - <14843 14799 14733 14696 14691>, - <14831 14786 14724 14692 14690>, - <14819 14776 14719 14690 14690>, - <14767 14740 14703 14678 14676>, - <14740 14710 14680 14653 14645>, - <14731 14703 14668 14647 14637>, - <14725 14696 14656 14637 14627>, - <14741 14692 14651 14632 14622>, - <14832 14699 14662 14641 14641>, - <14739 14707 14661 14645 14646>, - <14748 14705 14661 14648 14648>, - <14752 14704 14661 14650 14649>, - <14789 14699 14665 14647 14645>, - <14789 14699 14665 14647 14645>, - <14789 14699 14665 14647 14645>; - }; - - qcom,pc-temp-z5-lut { - qcom,lut-col-legend = <0 10 25 40 50>; - qcom,lut-row-legend = <10000 9800 9600 9400 9200>, - <9000 8800 8600 8400 8200>, - <8000 7800 7600 7400 7200>, - <7000 6800 6600 6400 6200>, - <6000 5800 5600 5400 5200>, - <5000 4800 4600 4400 4200>, - <4000 3800 3600 3400 3200>, - <3000 2800 2600 2400 2200>, - <2000 1800 1600 1400 1200>, - <1000 900 800 700 600>, - <500 400 300 200 100>, - <0>; - qcom,lut-data = <11792 12279 13535 15414 14204>, - <13001 13808 15235 16383 17416>, - <13841 15100 16456 17237 19077>, - <14514 16104 17533 18315 20517>, - <15113 17028 18754 19244 21245>, - <15689 18181 19650 20146 21743>, - <16375 19593 19683 20412 21915>, - <17353 20752 19475 20064 21544>, - <18570 21607 19385 19726 21069>, - <19714 22312 19837 19833 21119>, - <20922 22624 20368 20227 21592>, - <21654 22649 20366 20704 22135>, - <21494 22792 20190 21409 22819>, - <21073 24392 20127 22129 23478>, - <21017 26764 20584 22757 23767>, - <22555 26941 21094 23386 23725>, - <24349 24455 21214 23801 23655>, - <24216 22548 21439 24313 23878>, - <22900 22853 21828 24599 24211>, - <22166 23930 23250 24474 24553>, - <23067 25813 24579 24129 24960>, - <25218 31144 24161 23371 24839>, - <27733 35337 22682 21648 23111>, - <31628 31478 21716 20674 21705>, - <34089 22242 21182 20941 21493>, - <31865 19114 20879 21395 21408>, - <26536 20884 21549 21643 21618>, - <23985 23280 23503 21875 22646>, - <23503 25063 24966 22255 23786>, - <23364 26728 25863 23569 24665>, - <23874 27767 26627 25316 25537>, - <25339 28404 27366 26549 26565>, - <26580 28812 28051 27647 27783>, - <27299 28952 28637 28369 28438>, - <27859 29013 29244 28922 28605>, - <28127 28980 29596 29269 28749>, - <28121 28632 29354 28928 29008>, - <28035 28071 28613 27970 29397>, - <28032 27480 27672 27629 29838>, - <28024 26731 26146 27677 30769>, - <27889 25936 24626 27779 31609>, - <27436 24934 23369 28434 31801>, - <26929 24388 22499 29368 31887>, - <26421 24450 22608 28936 31937>, - <27988 25663 22852 26365 31185>, - <27430 25453 21972 22626 21099>, - <26554 25602 22352 22600 22211>, - <26806 23914 24361 22775 24450>, - <23478 23641 24736 23227 28936>, - <18946 23905 22228 28971 29716>, - <23561 21707 23990 27451 26335>, - <20333 21474 23601 25150 24619>, - <18967 20996 23606 23367 22997>, - <16796 21104 21653 24495 23716>, - <16796 21104 21653 24495 23716>, - <16796 21104 21653 24495 23716>; - }; - - qcom,pc-temp-z6-lut { - qcom,lut-col-legend = <0 10 25 40 50>; - qcom,lut-row-legend = <10000 9800 9600 9400 9200>, - <9000 8800 8600 8400 8200>, - <8000 7800 7600 7400 7200>, - <7000 6800 6600 6400 6200>, - <6000 5800 5600 5400 5200>, - <5000 4800 4600 4400 4200>, - <4000 3800 3600 3400 3200>, - <3000 2800 2600 2400 2200>, - <2000 1800 1600 1400 1200>, - <1000 900 800 700 600>, - <500 400 300 200 100>, - <0>; - qcom,lut-data = <15776 15081 14574 14403 14378>, - <15822 15066 14611 14457 14412>, - <15728 15042 14587 14444 14404>, - <15561 14985 14560 14425 14386>, - <15434 14901 14531 14412 14376>, - <15332 14840 14504 14402 14371>, - <15250 14790 14491 14394 14367>, - <15184 14755 14482 14389 14362>, - <15130 14736 14475 14384 14359>, - <15088 14723 14469 14380 14356>, - <15057 14715 14464 14377 14353>, - <15033 14710 14459 14374 14350>, - <15014 14704 14454 14371 14348>, - <14997 14693 14451 14368 14345>, - <14991 14680 14450 14366 14342>, - <15002 14679 14449 14363 14338>, - <15017 14691 14448 14361 14335>, - <15016 14701 14446 14359 14333>, - <14999 14693 14443 14357 14331>, - <14987 14676 14438 14354 14328>, - <14985 14676 14433 14350 14326>, - <14985 14729 14451 14357 14329>, - <14996 14777 14500 14394 14362>, - <15054 14775 14519 14417 14387>, - <15101 14767 14512 14412 14383>, - <15097 14759 14503 14404 14374>, - <15080 14752 14497 14398 14368>, - <15067 14746 14492 14393 14365>, - <15057 14742 14488 14389 14362>, - <15050 14739 14484 14386 14358>, - <15047 14737 14482 14384 14356>, - <15045 14735 14480 14382 14353>, - <15045 14734 14478 14379 14350>, - <15046 14734 14478 14378 14347>, - <15047 14735 14478 14376 14345>, - <15049 14736 14479 14375 14343>, - <15050 14738 14480 14377 14345>, - <15052 14740 14481 14381 14354>, - <15055 14743 14482 14384 14358>, - <15061 14747 14484 14384 14358>, - <15065 14749 14485 14385 14359>, - <15066 14747 14482 14385 14359>, - <15067 14746 14478 14385 14360>, - <15067 14745 14478 14385 14361>, - <15047 14732 14473 14378 14356>, - <15035 14716 14457 14362 14333>, - <15030 14712 14451 14356 14327>, - <15027 14706 14445 14348 14320>, - <15020 14704 14442 14344 14318>, - <15023 14714 14450 14360 14336>, - <15046 14724 14459 14366 14341>, - <15055 14730 14462 14368 14344>, - <15068 14739 14467 14371 14347>, - <15088 14751 14472 14376 14351>, - <15088 14751 14472 14376 14351>, - <15088 14751 14472 14376 14351>; - }; - - qcom,pc-temp-y1-lut { - qcom,lut-col-legend = <(-10) 0 10 25 40 50>; - qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, - <8800 8600 8400 8200 8000 7800>, - <7600 7400 7200 7000 6800 6600>, - <6400 6200 6000 5800 5600 5400>, - <5200 5000 4800 4600 4400 4200>, - <4000 3800 3600 3400 3200 3000>, - <2800 2600 2400 2200 2000 1800>, - <1600 1400 1200 1000 900 800>, - <700 600 500 400 300 200>, - <100 0>; - qcom,lut-data = <5821 5347 5037 4674 4481 4427>, - <5843 5351 5036 4672 4484 4429>, - <5865 5355 5035 4670 4485 4430>, - <5883 5361 5033 4667 4485 4430>, - <5897 5365 5031 4664 4484 4431>, - <5903 5367 5030 4660 4482 4431>, - <5900 5367 5025 4656 4477 4430>, - <5895 5365 5019 4650 4473 4429>, - <5896 5364 5014 4646 4472 4427>, - <5901 5359 5010 4643 4472 4425>, - <5903 5356 5008 4640 4472 4423>, - <5904 5358 5011 4637 4470 4422>, - <5908 5361 5015 4634 4468 4422>, - <5911 5361 5013 4632 4467 4421>, - <5920 5359 5004 4630 4465 4419>, - <5925 5358 5000 4629 4464 4419>, - <5922 5365 5003 4629 4464 4419>, - <5917 5374 5007 4629 4464 4419>, - <5917 5376 5008 4629 4464 4419>, - <5916 5373 5005 4630 4465 4419>, - <5914 5372 5003 4631 4465 4419>, - <5914 5377 5004 4633 4467 4420>, - <5916 5382 5005 4635 4469 4422>, - <5917 5383 5005 4638 4469 4422>, - <5917 5382 5006 4640 4469 4422>, - <5917 5382 5008 4643 4470 4423>, - <5915 5390 5013 4646 4472 4423>, - <5911 5400 5019 4650 4474 4424>, - <5907 5401 5024 4654 4476 4426>, - <5900 5398 5029 4659 4479 4428>, - <5896 5395 5032 4664 4481 4430>, - <5906 5395 5032 4669 4484 4431>, - <5922 5398 5032 4675 4487 4432>, - <5932 5401 5035 4679 4490 4434>, - <5943 5403 5043 4682 4493 4437>, - <5946 5405 5047 4686 4496 4440>, - <5933 5401 5047 4691 4499 4442>, - <5912 5395 5048 4695 4501 4444>, - <5901 5393 5053 4701 4504 4445>, - <5892 5393 5061 4707 4506 4446>, - <5887 5393 5065 4710 4509 4448>, - <5896 5394 5064 4713 4511 4451>, - <5900 5398 5066 4715 4513 4451>, - <5883 5418 5079 4717 4515 4451>, - <5915 5410 5075 4725 4518 4454>, - <5906 5399 5089 4726 4521 4456>, - <5899 5402 5088 4727 4519 4457>, - <5893 5400 5081 4734 4522 4457>, - <5894 5416 5082 4737 4521 4457>, - <5893 5422 5089 4735 4523 4458>, - <5951 5403 5099 4738 4525 4460>, - <5978 5411 5100 4752 4529 4462>, - <5943 5406 5107 4748 4534 4464>, - <5955 5420 5108 4757 4536 4469>, - <5955 5420 5108 4757 4536 4469>, - <5955 5420 5108 4757 4536 4469>; - }; - - qcom,pc-temp-y2-lut { - qcom,lut-col-legend = <(-10) 0 10 25 40 50>; - qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, - <8800 8600 8400 8200 8000 7800>, - <7600 7400 7200 7000 6800 6600>, - <6400 6200 6000 5800 5600 5400>, - <5200 5000 4800 4600 4400 4200>, - <4000 3800 3600 3400 3200 3000>, - <2800 2600 2400 2200 2000 1800>, - <1600 1400 1200 1000 900 800>, - <700 600 500 400 300 200>, - <100 0>; - qcom,lut-data = <10091 10247 10509 10767 10785 10927>, - <10085 10259 10500 10740 10807 10958>, - <10082 10274 10489 10711 10818 10974>, - <10082 10288 10479 10684 10821 10978>, - <10084 10301 10470 10661 10818 10974>, - <10088 10309 10463 10643 10813 10967>, - <10129 10314 10458 10630 10787 10948>, - <10196 10318 10454 10619 10754 10920>, - <10242 10317 10452 10606 10748 10891>, - <10309 10310 10448 10589 10749 10854>, - <10343 10306 10446 10578 10750 10833>, - <10348 10349 10451 10581 10744 10834>, - <10361 10433 10462 10588 10735 10837>, - <10354 10516 10482 10588 10734 10833>, - <10267 10617 10525 10585 10733 10822>, - <10196 10671 10577 10591 10733 10816>, - <9993 10677 10646 10622 10733 10824>, - <9724 10679 10709 10670 10734 10837>, - <9677 10682 10732 10741 10732 10847>, - <9671 10689 10745 10841 10729 10857>, - <9668 10692 10750 10877 10736 10873>, - <9666 10695 10747 10828 10833 10914>, - <9664 10701 10743 10775 10940 10965>, - <9663 10698 10754 10784 10956 10999>, - <9661 10676 10777 10824 10960 11030>, - <9660 10640 10792 10857 10965 11054>, - <9659 10551 10798 10880 10972 11078>, - <9658 10416 10805 10900 10980 11102>, - <9657 10287 10820 10916 10994 11121>, - <9656 10134 10847 10930 11021 11137>, - <9656 10010 10858 10948 11048 11156>, - <9655 9913 10844 10989 11077 11185>, - <9655 9833 10824 11022 11105 11210>, - <9654 9791 10807 11021 11137 11220>, - <9654 9761 10786 11011 11170 11226>, - <9654 9737 10768 11005 11177 11228>, - <9654 9716 10753 11011 11139 11200>, - <9654 9699 10737 11017 11102 11170>, - <9653 9689 10712 11012 11096 11161>, - <9653 9681 10675 10996 11093 11144>, - <9653 9675 10616 10980 11081 11118>, - <9653 9671 10491 10961 11032 11066>, - <9653 9667 10377 10936 11009 11056>, - <9653 9664 10284 10902 11002 11096>, - <9653 9661 10205 10867 11000 10997>, - <9652 9659 10189 10820 10935 10941>, - <9652 9659 10170 10842 10880 10907>, - <9652 9658 10266 10786 10907 10898>, - <9652 9657 10342 10819 10926 10908>, - <9652 9656 10250 10823 10875 10851>, - <9652 9655 10037 10750 10829 10802>, - <9652 9654 9972 10651 10750 10766>, - <9651 9653 9891 10735 10690 10675>, - <9650 9653 10171 10679 10569 10544>, - <9650 9653 10171 10679 10569 10544>, - <9650 9653 10171 10679 10569 10544>; - }; - - qcom,pc-temp-y3-lut { - qcom,lut-col-legend = <(-10) 0 10 25 40 50>; - qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, - <8800 8600 8400 8200 8000 7800>, - <7600 7400 7200 7000 6800 6600>, - <6400 6200 6000 5800 5600 5400>, - <5200 5000 4800 4600 4400 4200>, - <4000 3800 3600 3400 3200 3000>, - <2800 2600 2400 2200 2000 1800>, - <1600 1400 1200 1000 900 800>, - <700 600 500 400 300 200>, - <100 0>; - qcom,lut-data = <14020 13485 13348 13290 13276 13269>, - <13912 13484 13350 13290 13276 13270>, - <13847 13482 13351 13290 13277 13271>, - <13814 13481 13352 13290 13277 13272>, - <13802 13479 13353 13290 13278 13274>, - <13800 13477 13353 13290 13278 13274>, - <13846 13474 13353 13290 13278 13275>, - <13915 13471 13353 13289 13279 13275>, - <13881 13472 13353 13290 13279 13275>, - <13646 13477 13352 13291 13279 13275>, - <13499 13480 13351 13292 13280 13275>, - <13535 13470 13351 13294 13280 13276>, - <13592 13454 13351 13296 13280 13277>, - <13605 13449 13352 13297 13281 13277>, - <13589 13442 13356 13297 13282 13277>, - <13574 13436 13358 13298 13282 13277>, - <13544 13434 13352 13298 13282 13277>, - <13507 13429 13343 13300 13283 13277>, - <13503 13421 13341 13301 13284 13278>, - <13510 13403 13340 13302 13285 13280>, - <13517 13385 13338 13303 13286 13281>, - <13521 13372 13331 13298 13282 13278>, - <13523 13361 13323 13291 13278 13275>, - <13523 13352 13319 13288 13277 13274>, - <13533 13345 13316 13286 13277 13273>, - <13553 13338 13314 13285 13276 13272>, - <13593 13320 13311 13285 13277 13273>, - <13646 13299 13309 13285 13277 13273>, - <13696 13288 13308 13285 13276 13273>, - <13750 13271 13307 13286 13276 13273>, - <13806 13266 13305 13286 13275 13273>, - <13866 13268 13303 13285 13275 13273>, - <13929 13271 13301 13285 13275 13272>, - <13994 13274 13301 13285 13275 13272>, - <14060 13278 13303 13284 13276 13272>, - <14134 13284 13305 13284 13277 13272>, - <14220 13295 13307 13283 13276 13273>, - <14312 13311 13309 13282 13275 13273>, - <14405 13332 13311 13282 13275 13273>, - <14501 13362 13312 13282 13276 13274>, - <14596 13393 13313 13282 13276 13274>, - <14687 13416 13313 13282 13277 13274>, - <14781 13443 13314 13283 13277 13274>, - <14884 13488 13317 13284 13276 13273>, - <14998 13565 13322 13285 13276 13274>, - <14988 13596 13326 13288 13278 13276>, - <15059 13649 13330 13289 13279 13277>, - <15152 13712 13339 13294 13283 13279>, - <15247 13784 13351 13296 13282 13277>, - <15340 13847 13352 13295 13280 13276>, - <15443 13922 13355 13295 13281 13277>, - <15627 14060 13367 13298 13284 13279>, - <15865 14258 13384 13304 13286 13283>, - <16661 14530 13427 13312 13291 13287>, - <16661 14530 13427 13312 13291 13287>, - <16661 14530 13427 13312 13291 13287>; - }; - - qcom,pc-temp-y4-lut { - qcom,lut-col-legend = <(-10) 0 10 25 40 50>; - qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, - <8800 8600 8400 8200 8000 7800>, - <7600 7400 7200 7000 6800 6600>, - <6400 6200 6000 5800 5600 5400>, - <5200 5000 4800 4600 4400 4200>, - <4000 3800 3600 3400 3200 3000>, - <2800 2600 2400 2200 2000 1800>, - <1600 1400 1200 1000 900 800>, - <700 600 500 400 300 200>, - <100 0>; - qcom,lut-data = <18008 16999 16718 16500 16460 16456>, - <18072 17065 16719 16497 16459 16454>, - <18111 17109 16717 16493 16457 16452>, - <18131 17135 16714 16489 16455 16451>, - <18138 17148 16709 16486 16453 16449>, - <18139 17152 16703 16485 16453 16448>, - <18029 17137 16693 16486 16452 16448>, - <17863 17112 16683 16486 16452 16447>, - <17896 17097 16681 16488 16452 16448>, - <18235 17083 16680 16490 16454 16449>, - <18508 17077 16680 16492 16455 16450>, - <18619 17111 16683 16496 16457 16451>, - <18700 17180 16689 16501 16461 16452>, - <18607 17260 16712 16509 16466 16453>, - <18107 17384 16786 16522 16473 16457>, - <17766 17446 16846 16538 16481 16462>, - <17718 17379 16883 16554 16487 16468>, - <17687 17259 16908 16574 16496 16475>, - <17629 17174 16905 16613 16516 16490>, - <17534 17108 16880 16675 16554 16516>, - <17407 17042 16841 16697 16568 16526>, - <17159 16963 16746 16628 16535 16505>, - <16891 16889 16644 16542 16492 16476>, - <16806 16845 16607 16507 16473 16463>, - <16770 16818 16587 16484 16461 16454>, - <16755 16786 16580 16478 16457 16452>, - <16753 16727 16578 16479 16457 16452>, - <16753 16673 16578 16480 16457 16452>, - <16756 16669 16579 16483 16459 16453>, - <16763 16685 16581 16490 16462 16455>, - <16771 16697 16581 16497 16467 16458>, - <16783 16705 16558 16506 16473 16464>, - <16797 16717 16535 16512 16481 16470>, - <16813 16732 16538 16515 16488 16475>, - <16831 16753 16552 16517 16495 16479>, - <16846 16769 16568 16515 16495 16479>, - <16858 16781 16587 16493 16474 16465>, - <16869 16791 16601 16473 16454 16451>, - <16877 16794 16600 16470 16450 16451>, - <16883 16792 16599 16468 16449 16452>, - <16885 16788 16599 16469 16448 16452>, - <16876 16770 16608 16474 16449 16451>, - <16865 16757 16618 16479 16448 16448>, - <16860 16757 16628 16481 16442 16435>, - <16879 16761 16645 16484 16444 16435>, - <16891 16789 16652 16498 16455 16453>, - <16943 16827 16682 16511 16475 16497>, - <17014 16881 16733 16537 16536 16562>, - <17081 16976 16802 16590 16557 16530>, - <17089 17020 16800 16563 16478 16467>, - <17047 16991 16801 16554 16477 16469>, - <17042 17006 16834 16584 16500 16488>, - <17105 17082 16903 16649 16553 16544>, - <17555 17233 17100 16828 16767 16718>, - <17555 17233 17100 16828 16767 16718>, - <17555 17233 17100 16828 16767 16718>; - }; - - qcom,pc-temp-y5-lut { - qcom,lut-col-legend = <(-10) 0 10 25 40 50>; - qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, - <8800 8600 8400 8200 8000 7800>, - <7600 7400 7200 7000 6800 6600>, - <6400 6200 6000 5800 5600 5400>, - <5200 5000 4800 4600 4400 4200>, - <4000 3800 3600 3400 3200 3000>, - <2800 2600 2400 2200 2000 1800>, - <1600 1400 1200 1000 900 800>, - <700 600 500 400 300 200>, - <100 0>; - qcom,lut-data = <11727 11942 13506 16264 17485 13743>, - <11187 12181 13834 16304 17713 15443>, - <10948 12440 14154 16154 17943 16969>, - <10946 12689 14439 15889 18142 18238>, - <11119 12897 14661 15580 18277 19164>, - <11403 13035 14792 15300 18315 19661>, - <12465 13100 14855 14911 18249 19739>, - <13822 13150 14864 14518 18113 19553>, - <13670 13301 14746 14395 17867 19106>, - <11695 13714 14420 14341 17361 18217>, - <10462 13958 14096 14326 16853 17639>, - <11501 13114 13863 14506 16406 17596>, - <13219 11865 13624 14722 15945 17611>, - <13884 11823 13278 14498 15435 17295>, - <13848 12774 12797 13693 14834 16535>, - <13691 13748 12589 13309 14470 15845>, - <13167 14554 12751 13334 14271 15143>, - <12586 15195 13107 13390 14142 14574>, - <13020 15258 13900 13564 14152 14504>, - <14413 15027 15523 14068 14254 14631>, - <15535 14881 16342 14723 14446 14876>, - <15575 14923 16444 15913 15152 15787>, - <15061 15014 16478 16911 16165 16899>, - <14339 15197 16434 16931 17201 17475>, - <12334 15627 16343 16746 18331 17902>, - <11314 15978 16268 16667 18791 18109>, - <11399 15505 16100 16581 18776 18180>, - <11512 14520 15934 16533 18615 18169>, - <11525 13737 16028 16730 18175 18053>, - <11550 12045 16380 17082 17340 17858>, - <11588 11352 16565 17187 16713 17565>, - <11718 11445 16382 17060 16198 16814>, - <11865 11550 16160 16944 15883 16183>, - <11908 11637 16198 17254 16375 16323>, - <11980 11737 16327 17954 17689 16949>, - <12075 11818 16423 18152 18505 17767>, - <12422 11915 16495 17982 18987 19240>, - <12794 12071 16540 17734 19303 20755>, - <12843 12334 16444 17425 19669 21829>, - <12812 12824 16116 17020 20264 22723>, - <12740 13086 15663 16654 20463 22879>, - <12356 12741 14862 16171 20541 22449>, - <11882 12264 14369 16034 20626 22711>, - <11570 11949 14152 16151 21020 24835>, - <11487 11951 14006 15816 18734 20674>, - <11662 11903 13943 16003 17805 20181>, - <11655 12101 13682 15426 17094 17583>, - <11840 12432 13801 16015 16324 15006>, - <12476 12948 14155 15430 14898 14594>, - <12752 13151 14323 16256 17791 17272>, - <12081 13073 14285 16869 17629 17625>, - <11734 12858 14199 16707 19166 17889>, - <11770 12567 13945 17145 18317 18429>, - <11976 12244 15223 16959 17784 17367>, - <11976 12244 15223 16959 17784 17367>, - <11976 12244 15223 16959 17784 17367>; - }; - - qcom,pc-temp-y6-lut { - qcom,lut-col-legend = <(-10) 0 10 25 40 50>; - qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>, - <8800 8600 8400 8200 8000 7800>, - <7600 7400 7200 7000 6800 6600>, - <6400 6200 6000 5800 5600 5400>, - <5200 5000 4800 4600 4400 4200>, - <4000 3800 3600 3400 3200 3000>, - <2800 2600 2400 2200 2000 1800>, - <1600 1400 1200 1000 900 800>, - <700 600 500 400 300 200>, - <100 0>; - qcom,lut-data = <6551 5600 5220 4990 4943 4930>, - <6534 5605 5216 4988 4942 4931>, - <6511 5605 5211 4986 4942 4931>, - <6488 5601 5205 4984 4942 4931>, - <6470 5594 5199 4983 4942 4932>, - <6461 5584 5193 4982 4942 4932>, - <6460 5570 5186 4981 4942 4932>, - <6461 5554 5179 4980 4942 4932>, - <6450 5545 5174 4981 4942 4932>, - <6403 5538 5169 4981 4942 4933>, - <6375 5535 5166 4982 4943 4933>, - <6433 5536 5165 4984 4943 4933>, - <6517 5539 5164 4987 4945 4934>, - <6504 5548 5169 4989 4946 4935>, - <6362 5577 5191 4993 4949 4936>, - <6258 5593 5206 4998 4951 4938>, - <6231 5576 5210 5003 4954 4939>, - <6212 5543 5212 5009 4956 4942>, - <6209 5514 5211 5021 4962 4946>, - <6205 5486 5203 5040 4974 4955>, - <6199 5459 5190 5046 4978 4958>, - <6156 5431 5159 5023 4966 4950>, - <6101 5407 5125 4994 4951 4939>, - <6096 5397 5113 4982 4945 4934>, - <6119 5393 5107 4974 4941 4931>, - <6146 5387 5105 4972 4940 4930>, - <6186 5373 5105 4973 4940 4930>, - <6237 5359 5106 4974 4940 4931>, - <6285 5359 5108 4975 4940 4931>, - <6335 5374 5112 4978 4941 4932>, - <6386 5394 5113 4981 4942 4933>, - <6438 5418 5109 4984 4944 4934>, - <6491 5448 5106 4986 4946 4936>, - <6546 5478 5109 4988 4949 4938>, - <6603 5512 5120 4989 4952 4939>, - <6665 5547 5133 4989 4952 4939>, - <6732 5583 5145 4983 4946 4936>, - <6803 5621 5158 4978 4940 4932>, - <6876 5662 5167 4978 4940 4932>, - <6950 5708 5176 4978 4940 4933>, - <7022 5754 5186 4979 4940 4933>, - <7089 5799 5201 4982 4942 4934>, - <7157 5850 5219 4985 4942 4933>, - <7235 5915 5240 4987 4939 4929>, - <7330 6003 5272 4991 4941 4930>, - <7326 6045 5279 4998 4946 4937>, - <7395 6104 5304 5003 4952 4950>, - <7483 6173 5341 5014 4973 4970>, - <7577 6261 5385 5032 4978 4960>, - <7656 6331 5397 5024 4954 4941>, - <7727 6392 5417 5023 4955 4943>, - <7873 6517 5468 5035 4965 4950>, - <8078 6702 5539 5060 4982 4970>, - <8853 6954 5681 5120 5047 5023>, - <8853 6954 5681 5120 5047 5023>, - <8853 6954 5681 5120 5047 5023>; - }; - -}; diff --git a/arch/arm64/boot/dts/qcom/quin-vm-common.dtsi b/arch/arm64/boot/dts/qcom/quin-vm-common.dtsi index bbe8e8e6f225..3d353aa5dfca 100644 --- a/arch/arm64/boot/dts/qcom/quin-vm-common.dtsi +++ b/arch/arm64/boot/dts/qcom/quin-vm-common.dtsi @@ -248,26 +248,4 @@ compatible = "qcom,vm-restart"; status = "ok"; }; - - spmi_bus: qcom,spmi { - compatible = "qcom,viospmi-pmic-arb"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - viospmi: virtio-spmi@1c800000 { - compatible = "virtio,mmio"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x1c800000 0x1100>; - interrupts = ; - status = "okay"; - }; }; diff --git a/arch/arm64/boot/dts/qcom/sa515m-ccard-pcie-ep.dts b/arch/arm64/boot/dts/qcom/sa515m-ccard-pcie-ep.dts index 0d95e1540cf4..7bd092eebb5c 100644 --- a/arch/arm64/boot/dts/qcom/sa515m-ccard-pcie-ep.dts +++ b/arch/arm64/boot/dts/qcom/sa515m-ccard-pcie-ep.dts @@ -44,7 +44,3 @@ &mhi_device { status = "ok"; }; - -&mhi_net_device { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/qcom/sa515m-ccard.dtsi b/arch/arm64/boot/dts/qcom/sa515m-ccard.dtsi index ee1e7cc77def..6eb3f9aa57b7 100644 --- a/arch/arm64/boot/dts/qcom/sa515m-ccard.dtsi +++ b/arch/arm64/boot/dts/qcom/sa515m-ccard.dtsi @@ -23,59 +23,6 @@ gpio = <&tlmm 23 GPIO_ACTIVE_HIGH>; enable-active-high; }; - - snd_tlv3x: sound-auto { - compatible = "qcom,sdx-asoc-snd-auto"; - qcom,model = "sdx-auto-i2s-snd-card"; - qcom,prim_mi2s_aux_master = <&prim_master>; - qcom,prim_mi2s_aux_slave = <&prim_slave>; - qcom,sec_mi2s_aux_master = <&sec_master>; - qcom,sec_mi2s_aux_slave = <&sec_slave>; - - pinctrl-names = "default"; - pinctrl-0 = <&a2b_cdc_sel_default>, <&i2s_mclk_active>; - - asoc-platform = <&pcm0>, <&pcm1>, <&voip>, <&voice>, - <&loopback>, <&hostless>, <&afe>, <&routing>, - <&pcm_dtmf>, <&host_pcm>, <&compress>; - asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", - "msm-voip-dsp", "msm-pcm-voice", - "msm-pcm-loopback", "msm-pcm-hostless", - "msm-pcm-afe", "msm-pcm-routing", - "msm-pcm-dtmf", "msm-voice-host-pcm", - "msm-compress-dsp"; - asoc-cpu = <&dai_pri_auxpcm>, <&mi2s_prim>, <&mi2s_sec>, - <&dtmf_tx>, - <&rx_capture_tx>, <&rx_playback_rx>, - <&tx_capture_tx>, <&tx_playback_rx>, - <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, - <&afe_proxy_tx>, <&incall_record_rx>, - <&incall_record_tx>, <&incall_music_rx>, - <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, - <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, - <&dai_sec_auxpcm>; - asoc-cpu-names = "msm-dai-q6-auxpcm.1", - "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", - "msm-dai-stub-dev.4", "msm-dai-stub-dev.5", - "msm-dai-stub-dev.6", "msm-dai-stub-dev.7", - "msm-dai-stub-dev.8", "msm-dai-q6-dev.224", - "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", - "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", - "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", - "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", - "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", - "msm-dai-q6-auxpcm.2"; - asoc-codec = <&tlv320aic3x_codec>, <&stub_codec>; - asoc-codec-names = "tlv320aic3x-codec", "msm-stub-codec.1"; - }; - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; }; /* delete pm8150b nodes */ @@ -87,9 +34,6 @@ /delete-node/ pm8150b-vbat-lvl0; /delete-node/ pm8150b-vbat-lvl1; /delete-node/ pm8150b-vbat-lvl2; - /delete-node/ pm8150b-bcl-lvl0; - /delete-node/ pm8150b-bcl-lvl1; - /delete-node/ pm8150b-bcl-lvl2; /delete-node/ soc; }; @@ -116,6 +60,10 @@ status = "okay"; }; +&blsp1_uart4a_hs { + status = "okay"; +}; + &vbus_detect { status = "okay"; }; @@ -151,7 +99,7 @@ interrupts = <88 0>; spi-max-frequency = <5000000>; qcom,clk-freq-mhz = <40000000>; - qcom,max-can-channels = <2>; + qcom,max-can-channels = <1>; qcom,bits-per-word = <8>; qcom,support-can-fd; }; @@ -165,13 +113,6 @@ reset-inverted; AVDD-supply = <&codec_vreg>; IOVDD-supply = <&codec_vreg>; - ai3x-ocmv = <1>; - }; - - eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - pagesize = <32>; }; }; @@ -183,21 +124,9 @@ /delete-property/ vreg_rgmii-supply; pinctrl-names = "default"; pinctrl-0 = <&vreg_rgmii_off_default>; - qcom,phy-reset-delay-msecs = <10>; }; &vreg_rgmii_io_pads { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - -&cnss_qca6390 { - vdd-wlan-ctrl1-supply = <&vreg_conn_pa>; - vdd-wlan-aon-supply = <&pmxprairie_s3>; - vdd-wlan-rfa1-supply = <&pmxprairie_s2>; - vdd-wlan-rfa3-supply = <&pmxprairie_s4>; - qcom,vdd-wlan-ctrl1-info = <0 0 0 0>; - qcom,vdd-wlan-aon-info = <950000 950000 0 0>; - qcom,vdd-wlan-rfa1-info = <1350000 1350000 0 0>; - qcom,vdd-wlan-rfa3-info = <1904000 1904000 450000 0>; -}; diff --git a/arch/arm64/boot/dts/qcom/sa6155-adp-air.dtsi b/arch/arm64/boot/dts/qcom/sa6155-adp-air.dtsi index e86b8deb8f57..61a1491c3e6e 100644 --- a/arch/arm64/boot/dts/qcom/sa6155-adp-air.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155-adp-air.dtsi @@ -51,7 +51,7 @@ }; hsi2s: qcom,hsi2s { - compatible = "qcom,sa6155-hsi2s", "qcom,hsi2s"; + compatible = "qcom,hsi2s"; number-of-interfaces = <2>; reg = <0x1B40000 0x28000>; reg-names = "lpa_if"; @@ -64,8 +64,6 @@ clock-names = "core_clk", "wr0_mem_clk", "wr1_mem_clk", "wr2_mem_clk", "csr_hclk"; - bit-clock-hz = <20000000>; - interrupt-interval-ms = <10>; sdr0: qcom,hs0_i2s { compatible = "qcom,hsi2s-interface"; diff --git a/arch/arm64/boot/dts/qcom/sa6155-adp-star.dtsi b/arch/arm64/boot/dts/qcom/sa6155-adp-star.dtsi index be1b682abcfc..78c3bce754e6 100644 --- a/arch/arm64/boot/dts/qcom/sa6155-adp-star.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155-adp-star.dtsi @@ -44,7 +44,7 @@ }; hsi2s: qcom,hsi2s { - compatible = "qcom,sa6155-hsi2s", "qcom,hsi2s"; + compatible = "qcom,hsi2s"; number-of-interfaces = <2>; reg = <0x1B40000 0x28000>; reg-names = "lpa_if"; @@ -57,8 +57,6 @@ clock-names = "core_clk", "wr0_mem_clk", "wr1_mem_clk", "wr2_mem_clk", "csr_hclk"; - bit-clock-hz = <20000000>; - interrupt-interval-ms = <10>; sdr0: qcom,hs0_i2s { compatible = "qcom,hsi2s-interface"; diff --git a/arch/arm64/boot/dts/qcom/sa6155-pmic.dtsi b/arch/arm64/boot/dts/qcom/sa6155-pmic.dtsi index 737ab8022869..3e00782bcd68 100644 --- a/arch/arm64/boot/dts/qcom/sa6155-pmic.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155-pmic.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -137,15 +137,9 @@ /delete-node/ pm6150-vbat-lvl0; /delete-node/ pm6150-vbat-lvl1; /delete-node/ pm6150-vbat-lvl2; - /delete-node/ pm6150-bcl-lvl0; - /delete-node/ pm6150-bcl-lvl1; - /delete-node/ pm6150-bcl-lvl2; /delete-node/ pm6150l-vph-lvl0; /delete-node/ pm6150l-vph-lvl1; /delete-node/ pm6150l-vph-lvl2; - /delete-node/ pm6150l-bcl-lvl0; - /delete-node/ pm6150l-bcl-lvl1; - /delete-node/ pm6150l-bcl-lvl2; /delete-node/ xo-therm; /delete-node/ sdm-therm; /delete-node/ conn-therm; diff --git a/arch/arm64/boot/dts/qcom/sa6155.dtsi b/arch/arm64/boot/dts/qcom/sa6155.dtsi index b59622839485..1bf14ec01b4a 100644 --- a/arch/arm64/boot/dts/qcom/sa6155.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155.dtsi @@ -118,62 +118,6 @@ }; }; }; - - cpuss-0-step { - trips { - cpu45-config { - temperature = <115000>; - }; - }; - }; - - cpuss-1-step { - trips { - cpu23-config { - temperature = <115000>; - }; - }; - }; - - cpuss-2-step { - trips { - cpu01-config { - temperature = <115000>; - }; - }; - }; - - cpu-1-0-step { - trips { - cpu6-0-config { - temperature = <115000>; - }; - }; - }; - - cpu-1-1-step { - trips { - cpu6-1-config { - temperature = <115000>; - }; - }; - }; - - cpu-1-2-step { - trips { - cpu7-0-config { - temperature = <115000>; - }; - }; - }; - - cpu-1-3-step { - trips { - cpu7-1-config { - temperature = <115000>; - }; - }; - }; }; /* GPU power level overrides */ diff --git a/arch/arm64/boot/dts/qcom/sa6155p-vm-usb.dtsi b/arch/arm64/boot/dts/qcom/sa6155p-vm-usb.dtsi index ef2dcb739f35..3db66cf1455f 100644 --- a/arch/arm64/boot/dts/qcom/sa6155p-vm-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155p-vm-usb.dtsi @@ -119,9 +119,9 @@ "tune2_efuse_addr", "tcsr_conn_box_spare_0"; - vdd-supply = <&L5A>; - vdda18-supply = <&L12A>; - vdda33-supply = <&L13A>; + vdd-supply = <&pm6150_l4>; + vdda18-supply = <&pm6150_l11>; + vdda33-supply = <&pm6150_l17>; qcom,vdd-voltage-level = <0 925000 975000>; qcom,tune2-efuse-bit-pos = <25>; qcom,tune2-efuse-num-bits = <4>; @@ -159,8 +159,8 @@ reg-names = "qmp_phy_base", "vls_clamp_reg"; - vdd-supply = <&L5A>; - core-supply = <&L12A>; + vdd-supply = <&pm6150_l4>; + core-supply = <&pm6150_l11>; qcom,vdd-voltage-level = <0 925000 975000>; qcom,core-voltage-level = <0 1800000 1800000>; qcom,qmp-phy-init-seq = @@ -370,9 +370,9 @@ reg-names = "qusb_phy_base", "tcsr_conn_box_spare_0"; - vdd-supply = <&L5A>; - vdda18-supply = <&L12A>; - vdda33-supply = <&L13A>; + vdd-supply = <&pm6150_l4>; + vdda18-supply = <&pm6150_l11>; + vdda33-supply = <&pm6150_l17>; qcom,vdd-voltage-level = <0 925000 975000>; qcom,qusb-phy-init-seq = <0xc8 0x80 0xb3 0x84 diff --git a/arch/arm64/boot/dts/qcom/sa6155p-vm.dts b/arch/arm64/boot/dts/qcom/sa6155p-vm.dts index 17f8330c92f4..0caf78c1b2e6 100644 --- a/arch/arm64/boot/dts/qcom/sa6155p-vm.dts +++ b/arch/arm64/boot/dts/qcom/sa6155p-vm.dts @@ -30,10 +30,6 @@ status = "ok"; }; -&qupv3_se7_4uart { - status = "ok"; -}; - &usb0 { status = "ok"; }; diff --git a/arch/arm64/boot/dts/qcom/sa6155p-vm.dtsi b/arch/arm64/boot/dts/qcom/sa6155p-vm.dtsi index 89777b7813fc..7432a67530ed 100644 --- a/arch/arm64/boot/dts/qcom/sa6155p-vm.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155p-vm.dtsi @@ -41,67 +41,16 @@ }; &soc { - clock_virt: qcom,virtio-gcc { - compatible = "virtio,mmio"; - reg = <0x1c200000 0x1000>; - interrupts = <0 48 0>; + clock_virt: qcom,virt-gcc { + compatible = "qcom,virt-clk-sm6150-gcc"; #clock-cells = <1>; #reset-cells = <1>; }; - clock_virt_scc: qcom,virtio-scc { - compatible = "virtio,mmio"; - reg = <0x1c300000 0x1000>; - interrupts = <0 49 0>; + clock_virt_scc: qcom,virt-scc { + compatible = "qcom,virt-clk-sm6150-scc"; #clock-cells = <1>; - }; - - regulator_virt: virtio_regulator@1c700000 { - compatible = "virtio,mmio"; - reg = <0x1c700000 0x1000>; - interrupts = <0 42 0>; - - usb30_prim_gdsc: usb30_prim_gdsc { - regulator-name = "usb30_prim_gdsc"; - }; - - usb20_sec_gdsc: usb20_sec_gdsc { - regulator-name = "usb20_sec_gdsc"; - }; - - pcie_0_gdsc: pcie_0_gdsc { - regulator-name = "pcie_0_gdsc"; - }; - - L2A: pm6155_1_l2: regulator-pm6155-1-l2 { - regulator-name = "ldoa2"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <3100000>; - }; - - L5A: pm6155_1_l5: regulator-pm6155-1-l5 { - regulator-name = "ldoa5"; - regulator-min-microvolt = <875000>; - regulator-max-microvolt = <975000>; - }; - - L10A: pm6155_1_l10: regulator-pm6155-1-l10 { - regulator-name = "ldoa10"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <3312000>; - }; - - L12A: pm6155_1_l12: regulator-pm6155-1-l12 { - regulator-name = "ldoa12"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1890000>; - }; - - L13A: pm6155_1_l13: regulator-pm6155-1-l13 { - regulator-name = "ldoa13"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3230000>; - }; + #reset-cells = <1>; }; apps_smmu: apps-smmu@0x15000000 { @@ -191,6 +140,45 @@ status = "ok"; }; + usb30_prim_gdsc: usb30_prim_gdsc { + compatible = "qcom,stub-regulator"; + regulator-name = "usb30_prim_gdsc"; + status = "ok"; + }; + + usb20_sec_gdsc: usb20_sec_gdsc { + compatible = "qcom,stub-regulator"; + regulator-name = "usb20_sec_gdsc"; + status = "ok"; + }; + + pm6150_l11: regulator-pm6150-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l11"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1890000>; + status = "ok"; + }; + + pm6150_l4: regulator-pm6150-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + status = "ok"; + }; + + pm6150_l17: regulator-pm6150-l17 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6150_l17"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3230000>; + status = "ok"; + }; + qcom_seecom: qseecom@86d00000 { compatible = "qcom,qseecom"; reg = <0x86d00000 0xe00000>; @@ -204,6 +192,38 @@ qcom,qsee-reentrancy-support = <2>; }; + pm6155_1_l10: regulator-pm6155-1-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6155_1_l10"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + status = "ok"; + }; + + pm6155_1_l2: regulator-pm6155-1-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6155_1_l2"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3100000>; + status = "ok"; + }; + + pm6155_1_l12: regulator-pm6155-1-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6155_1_l12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1890000>; + status = "ok"; + }; + + pm6155_1_l5: regulator-pm6155-1-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm6155_1_l5"; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + status = "ok"; + }; + VDD_CX_LEVEL: VDD_MX_LEVEL: S2A_LEVEL: pm6155_1_s2_level: regulator-pm6155-1-s2-level { compatible = "qcom,stub-regulator"; @@ -214,6 +234,12 @@ = ; }; + pcie_0_gdsc: pcie_0_gdsc { + compatible = "qcom,stub-regulator"; + regulator-name = "pcie_0_gdsc"; + status = "okay"; + }; + vreg_wlan: vreg_wlan { compatible = "qcom,stub-regulator"; regulator-name = "vreg_wlan"; @@ -315,14 +341,6 @@ status = "disabled"; }; - - bluetooth_ext: bt_qca6174 { - compatible = "qca,qca6174"; - pinctrl-names = "default"; - pinctrl-0 = <&bt_en_active>; - qca,bt-reset-gpio = <&tlmm 85 0>; /* BT_EN */ - status = "ok"; - }; }; #include "sa6155p-vm-pinctrl.dtsi" @@ -331,9 +349,3 @@ #include "sa6155p-vm-usb.dtsi" #include "sa8155-vm-audio.dtsi" #include "sa6155p-vm-pcie.dtsi" -#include "pm6155-vm.dtsi" - -&tlmm { - dirconn-list = <100 216 1>, - <99 215 1>; -}; diff --git a/arch/arm64/boot/dts/qcom/sa6155p.dtsi b/arch/arm64/boot/dts/qcom/sa6155p.dtsi index 5d233dd7021a..48d82ceec6ba 100644 --- a/arch/arm64/boot/dts/qcom/sa6155p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa6155p.dtsi @@ -146,62 +146,6 @@ }; }; }; - - cpuss-0-step { - trips { - cpu45-config { - temperature = <115000>; - }; - }; - }; - - cpuss-1-step { - trips { - cpu23-config { - temperature = <115000>; - }; - }; - }; - - cpuss-2-step { - trips { - cpu01-config { - temperature = <115000>; - }; - }; - }; - - cpu-1-0-step { - trips { - cpu6-0-config { - temperature = <115000>; - }; - }; - }; - - cpu-1-1-step { - trips { - cpu6-1-config { - temperature = <115000>; - }; - }; - }; - - cpu-1-2-step { - trips { - cpu7-0-config { - temperature = <115000>; - }; - }; - }; - - cpu-1-3-step { - trips { - cpu7-1-config { - temperature = <115000>; - }; - }; - }; }; /* GPU power level overrides */ diff --git a/arch/arm64/boot/dts/qcom/sa8155-vm-audio.dtsi b/arch/arm64/boot/dts/qcom/sa8155-vm-audio.dtsi index a9480a4a430f..e101ced50d9d 100644 --- a/arch/arm64/boot/dts/qcom/sa8155-vm-audio.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8155-vm-audio.dtsi @@ -351,9 +351,8 @@ qcom,msm-dai-tdm-quin-rx { compatible = "qcom,msm-dai-tdm"; qcom,msm-cpudai-tdm-group-id = <37184>; - qcom,msm-cpudai-tdm-group-num-ports = <5>; - qcom,msm-cpudai-tdm-group-port-id = <36928 36930 36932 - 36934 36942>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36928 36930 36932 36934>; qcom,msm-cpudai-tdm-clk-rate = <24576000>; qcom,msm-cpudai-tdm-clk-internal = <1>; qcom,msm-cpudai-tdm-sync-mode = <1>; @@ -384,20 +383,13 @@ qcom,msm-cpudai-tdm-dev-id = <36934>; qcom,msm-cpudai-tdm-data-align = <0>; }; - - dai_quin_tdm_rx_7: qcom,msm-dai-q6-tdm-quin-rx-7 { - compatible = "qcom,msm-dai-q6-tdm"; - qcom,msm-cpudai-tdm-dev-id = <36942>; - qcom,msm-cpudai-tdm-data-align = <0>; - }; }; qcom,msm-dai-tdm-quin-tx { compatible = "qcom,msm-dai-tdm"; qcom,msm-cpudai-tdm-group-id = <37185>; - qcom,msm-cpudai-tdm-group-num-ports = <5>; - qcom,msm-cpudai-tdm-group-port-id = <36929 36931 36933 - 36935 36943>; + qcom,msm-cpudai-tdm-group-num-ports = <4>; + qcom,msm-cpudai-tdm-group-port-id = <36929 36931 36933 36935>; qcom,msm-cpudai-tdm-clk-rate = <24576000>; qcom,msm-cpudai-tdm-clk-internal = <1>; qcom,msm-cpudai-tdm-sync-mode = <1>; @@ -428,12 +420,6 @@ qcom,msm-cpudai-tdm-dev-id = <36935>; qcom,msm-cpudai-tdm-data-align = <0>; }; - - dai_quin_tdm_tx_7: qcom,msm-dai-q6-tdm-quin-tx-7 { - compatible = "qcom,msm-dai-q6-tdm"; - qcom,msm-cpudai-tdm-dev-id = <36943>; - qcom,msm-cpudai-tdm-data-align = <0>; - }; }; qcom,avtimer@170f7000 { @@ -503,10 +489,9 @@ <&dai_quat_tdm_tx_2>, <&dai_quat_tdm_tx_3>, <&dai_quat_tdm_tx_7>, <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_rx_1>, <&dai_quin_tdm_rx_2>, - <&dai_quin_tdm_rx_3>, <&dai_quin_tdm_rx_7>, - <&dai_quin_tdm_tx_0>, <&dai_quin_tdm_tx_1>, - <&dai_quin_tdm_tx_2>, <&dai_quin_tdm_tx_3>, - <&dai_quin_tdm_tx_7>; + <&dai_quin_tdm_rx_3>, <&dai_quin_tdm_tx_0>, + <&dai_quin_tdm_tx_1>, <&dai_quin_tdm_tx_2>, + <&dai_quin_tdm_tx_3>; asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", @@ -538,10 +523,9 @@ "msm-dai-q6-tdm.36917", "msm-dai-q6-tdm.36919", "msm-dai-q6-tdm.36927", "msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36930", "msm-dai-q6-tdm.36932", - "msm-dai-q6-tdm.36934", "msm-dai-q6-tdm.36942", - "msm-dai-q6-tdm.36929", "msm-dai-q6-tdm.36931", - "msm-dai-q6-tdm.36933", "msm-dai-q6-tdm.36935", - "msm-dai-q6-tdm.36943"; + "msm-dai-q6-tdm.36934", "msm-dai-q6-tdm.36929", + "msm-dai-q6-tdm.36931", "msm-dai-q6-tdm.36933", + "msm-dai-q6-tdm.36935"; asoc-codec = <&stub_codec>; asoc-codec-names = "msm-stub-codec.1"; qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>; diff --git a/arch/arm64/boot/dts/qcom/sa8155-vm-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sa8155-vm-pinctrl.dtsi index 2c54f126b126..919fcc057493 100644 --- a/arch/arm64/boot/dts/qcom/sa8155-vm-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8155-vm-pinctrl.dtsi @@ -21,452 +21,5 @@ interrupt-controller; #interrupt-cells = <2>; }; - - hs1_i2s_mclk { - hs1_i2s_mclk_sleep: hs1_i2s_mclk_sleep { - mux { - pins = "gpio155"; - function = "gpio"; - }; - - config { - pins = "gpio155"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs1_i2s_mclk_active: hs1_i2s_mclk_active { - mux { - pins = "gpio155"; - function = "hs1_mi2s"; - }; - - config { - pins = "gpio155"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs1_i2s_sck { - hs1_i2s_sck_sleep: hs1_i2s_sck_sleep { - mux { - pins = "gpio156"; - function = "gpio"; - }; - - config { - pins = "gpio156"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs1_i2s_sck_active: hs1_i2s_sck_active { - mux { - pins = "gpio156"; - function = "hs1_mi2s"; - }; - - config { - pins = "gpio156"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs1_i2s_ws { - hs1_i2s_ws_sleep: hs1_i2s_ws_sleep { - mux { - pins = "gpio157"; - function = "gpio"; - }; - - config { - pins = "gpio157"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs1_i2s_ws_active: hs1_i2s_ws_active { - mux { - pins = "gpio157"; - function = "hs1_mi2s"; - }; - - config { - pins = "gpio157"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs1_i2s_data0 { - hs1_i2s_data0_sleep: hs1_i2s_data0_sleep { - mux { - pins = "gpio158"; - function = "sleep"; - }; - - config { - pins = "gpio158"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs1_i2s_data0_active: hs1_i2s_data0_active { - mux { - pins = "gpio158"; - function = "hs1_mi2s"; - }; - - config { - pins = "gpio158"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs1_i2s_data1 { - hs1_i2s_data1_sleep: hs1_i2s_data1_sleep { - mux { - pins = "gpio159"; - function = "gpio"; - }; - - config { - pins = "gpio159"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs1_i2s_data1_active: hs1_i2s_data1_active { - mux { - pins = "gpio159"; - function = "hs1_mi2s"; - }; - - config { - pins = "gpio159"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - }; - }; - }; - - hs2_i2s_mclk { - hs2_i2s_mclk_sleep: hs2_i2s_mclk_sleep { - mux { - pins = "gpio160"; - function = "gpio"; - }; - - config { - pins = "gpio160"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs2_i2s_mclk_active: hs2_i2s_mclk_active { - mux { - pins = "gpio160"; - function = "hs2_mi2s"; - }; - - config { - pins = "gpio160"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs2_i2s_sck { - hs2_i2s_sck_sleep: hs2_i2s_sck_sleep { - mux { - pins = "gpio161"; - function = "gpio"; - }; - - config { - pins = "gpio161"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs2_i2s_sck_active: hs2_i2s_sck_active { - mux { - pins = "gpio161"; - function = "hs2_mi2s"; - }; - - config { - pins = "gpio161"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs2_i2s_ws { - hs2_i2s_ws_sleep: hs2_i2s_ws_sleep { - mux { - pins = "gpio162"; - function = "gpio"; - }; - - config { - pins = "gpio162"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs2_i2s_ws_active: hs2_i2s_ws_active { - mux { - pins = "gpio162"; - function = "hs2_mi2s"; - }; - - config { - pins = "gpio162"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs2_i2s_data0 { - hs2_i2s_data0_sleep: hs2_i2s_data0_sleep { - mux { - pins = "gpio163"; - function = "gpio"; - }; - - config { - pins = "gpio163"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs2_i2s_data0_active: hs2_i2s_data0_active { - mux { - pins = "gpio163"; - function = "hs2_mi2s"; - }; - - config { - pins = "gpio163"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs2_i2s_data1 { - hs2_i2s_data1_sleep: hs2_i2s_data1_sleep { - mux { - pins = "gpio164"; - function = "gpio"; - }; - - config { - pins = "gpio164"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs2_i2s_data1_active: hs2_i2s_data1_active { - mux { - pins = "gpio164"; - function = "hs2_mi2s"; - }; - - config { - pins = "gpio164"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - }; - }; - }; - - hs3_i2s_mclk { - hs3_i2s_mclk_sleep: hs3_i2s_mclk_sleep { - mux { - pins = "gpio125"; - function = "gpio"; - }; - - config { - pins = "gpio125"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs3_i2s_mclk_active: hs3_i2s_mclk_active { - mux { - pins = "gpio125"; - function = "hs3_mi2s"; - }; - - config { - pins = "gpio125"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs3_i2s_sck { - hs3_i2s_sck_sleep: hs3_i2s_sck_sleep { - mux { - pins = "gpio165"; - function = "gpio"; - }; - - config { - pins = "gpio165"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs3_i2s_sck_active: hs3_i2s_sck_active { - mux { - pins = "gpio165"; - function = "hs3_mi2s"; - }; - - config { - pins = "gpio165"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs3_i2s_ws { - hs3_i2s_ws_sleep: hs3_i2s_ws_sleep { - mux { - pins = "gpio166"; - function = "gpio"; - }; - - config { - pins = "gpio166"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs3_i2s_ws_active: hs3_i2s_ws_active { - mux { - pins = "gpio166"; - function = "hs3_mi2s"; - }; - - config { - pins = "gpio166"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs3_i2s_data0 { - hs3_i2s_data0_sleep: hs3_i2s_data0_sleep { - mux { - pins = "gpio167"; - function = "gpio"; - }; - - config { - pins = "gpio167"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs3_i2s_data0_active: hs3_i2s_data0_active { - mux { - pins = "gpio167"; - function = "hs3_mi2s"; - }; - - config { - pins = "gpio167"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs3_i2s_data1 { - hs3_i2s_data1_sleep: hs3_i2s_data1_sleep { - mux { - pins = "gpio168"; - function = "gpio"; - }; - - config { - pins = "gpio168"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs3_i2s_data1_active: hs3_i2s_data1_active { - mux { - pins = "gpio168"; - function = "hs3_mi2s"; - }; - - config { - pins = "gpio168"; - drive-strength = <8>; /* 4 mA */ - bias-disable; /* NO PULL */ - }; - }; - }; }; diff --git a/arch/arm64/boot/dts/qcom/sa8155-vm-usb.dtsi b/arch/arm64/boot/dts/qcom/sa8155-vm-usb.dtsi index 90366d5cb5db..5e79647ad0f3 100644 --- a/arch/arm64/boot/dts/qcom/sa8155-vm-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8155-vm-usb.dtsi @@ -118,9 +118,9 @@ reg-names = "hsusb_phy_base", "phy_rcal_reg"; - vdd-supply = <&pm8150_1_l5>; - vdda18-supply = <&pm8150_1_l12>; - vdda33-supply = <&pm8150_1_l2>; + vdd-supply = <&pm8150_l5>; + vdda18-supply = <&pm8150_l12>; + vdda33-supply = <&pm8150_l2>; qcom,vdd-voltage-level = <0 880000 880000>; clocks = <&clock_gcc RPMH_CXO_CLK>; @@ -140,10 +140,10 @@ reg = <0x88e8000 0x3000>; reg-names = "qmp_phy_base"; - vdd-supply = <&pm8150_1_l5>; + vdd-supply = <&pm8150_l5>; qcom,vdd-voltage-level = <0 880000 880000>; qcom,vdd-max-load-uA = <47000>; - core-supply = <&pm8150_2_l8>; + core-supply = <&pm8150l_l3>; qcom,vbus-valid-override; qcom,link-training-reset; qcom,qmp-phy-init-seq = @@ -394,9 +394,9 @@ reg-names = "hsusb_phy_base", "phy_rcal_reg"; - vdd-supply = <&pm8150_1_l5>; - vdda18-supply = <&pm8150_1_l12>; - vdda33-supply = <&pm8150_1_l2>; + vdd-supply = <&pm8150_l5>; + vdda18-supply = <&pm8150_l12>; + vdda33-supply = <&pm8150_l2>; qcom,vdd-voltage-level = <0 880000 880000>; clocks = <&clock_gcc RPMH_CXO_CLK>; @@ -417,10 +417,10 @@ reg-names = "qmp_phy_base", "pcs_clamp_enable_reg"; - vdd-supply = <&pm8150_1_l5>; + vdd-supply = <&pm8150_l5>; qcom,vdd-voltage-level = <0 880000 880000>; qcom,vdd-max-load-uA = <47000>; - core-supply = <&pm8150_2_l8>; + core-supply = <&pm8150l_l3>; qcom,vbus-valid-override; qcom,qmp-phy-init-seq = /* */ diff --git a/arch/arm64/boot/dts/qcom/sa8155-vm.dtsi b/arch/arm64/boot/dts/qcom/sa8155-vm.dtsi index c51daecfce59..8ec724d101ac 100644 --- a/arch/arm64/boot/dts/qcom/sa8155-vm.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8155-vm.dtsi @@ -29,53 +29,6 @@ }; &soc { - hsi2s: qcom,hsi2s { - compatible = "qcom,sa8155-hsi2s", "qcom,hsi2s"; - number-of-interfaces = <3>; - reg = <0x172C0000 0x28000>, - <0x17080000 0xE000>; - reg-names = "lpa_if", "lpass_tcsr"; - interrupts = ; - bit-clock-hz = <20000000>; - interrupt-interval-ms = <10>; - - sdr0: qcom,hs0_i2s { - compatible = "qcom,hsi2s-interface"; - minor-number = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hs1_i2s_mclk_active &hs1_i2s_sck_active - &hs1_i2s_ws_active &hs1_i2s_data0_active - &hs1_i2s_data1_active>; - pinctrl-1 = <&hs1_i2s_mclk_sleep &hs1_i2s_sck_sleep - &hs1_i2s_ws_sleep &hs1_i2s_data0_sleep - &hs1_i2s_data1_sleep>; - }; - - sdr1: qcom,hs1_i2s { - compatible = "qcom,hsi2s-interface"; - minor-number = <1>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hs2_i2s_mclk_active &hs2_i2s_sck_active - &hs2_i2s_ws_active &hs2_i2s_data0_active - &hs2_i2s_data1_active>; - pinctrl-1 = <&hs2_i2s_mclk_sleep &hs2_i2s_sck_sleep - &hs2_i2s_ws_sleep &hs2_i2s_data0_sleep - &hs2_i2s_data1_sleep>; - }; - - sdr2: qcom,hs2_i2s { - compatible = "qcom,hsi2s-interface"; - minor-number = <2>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hs3_i2s_mclk_active &hs3_i2s_sck_active - &hs3_i2s_ws_active &hs3_i2s_data0_active - &hs3_i2s_data1_active>; - pinctrl-1 = <&hs3_i2s_mclk_sleep &hs3_i2s_sck_sleep - &hs3_i2s_ws_sleep &hs3_i2s_data0_sleep - &hs3_i2s_data1_sleep>; - }; - }; - clock_virt: qcom,virtio-gcc { compatible = "virtio,mmio"; reg = <0x1c200000 0x1000>; @@ -92,96 +45,6 @@ #reset-cells = <1>; }; - regulator_virt: virtio_regulator@1c700000 { - compatible = "virtio,mmio"; - reg = <0x1c700000 0x1000>; - interrupts = <0 42 0>; - - usb30_prim_gdsc: usb30_prim_gdsc { - regulator-name = "usb30_prim_gdsc"; - }; - - usb30_sec_gdsc: usb30_sec_gdsc { - regulator-name = "usb30_sec_gdsc"; - }; - - pcie_0_gdsc: pcie_0_gdsc { - regulator-name = "pcie_0_gdsc"; - }; - - pcie_1_gdsc: pcie_1_gdsc { - regulator-name = "pcie_1_gdsc"; - }; - - L2A: pm8150_1_l2: regulator-pm8150-1-l2 { - regulator-name = "ldoa2"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - }; - - L5A: pm8150_1_l5: regulator-pm8150-1-l5 { - regulator-name = "ldoa5"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - }; - - L12A: pm8150_1_l12: regulator-pm8150-1-l12 { - regulator-name = "ldoa12"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - L17A: pm8150_1_l17: regulator-pm8150-1-l17 { - regulator-name = "ldoa17"; - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - }; - - L8C: pm8150_2_l8: regulator-pm8150-2-l8 { - regulator-name = "ldoc8"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-allow-set-load; - }; - - L13C: pm8150_2_l13: regulator-pm8150-2-l13 { - regulator-name = "ldoc13"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - }; - - L15C: pm8150_2_l15: regulator-pm8150-2-l15 { - regulator-name = "ldoc15"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1904000>; - }; - - L18C: pm8150_2_l18: regulator-pm8150-2-l18 { - regulator-name = "ldoc18"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-allow-set-load; - }; - - S6A: pm8150_1_s6: regulator-pm8150-1-s6 { - regulator-name = "smpa6"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1352000>; - }; - - S4C: pm8150_2_s4: regulator-pm8150-2-s4 { - regulator-name = "smpc4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; - }; - - S5C: pm8150_2_s5: regulator-pm8150-2-s5 { - regulator-name = "smpc5"; - regulator-min-microvolt = <1824000>; - regulator-max-microvolt = <2040000>; - }; - }; - apps_smmu: apps-smmu@0x15000000 { compatible = "qcom,qsmmu-v500"; reg = <0x15000000 0x100000>, @@ -286,6 +149,38 @@ status = "disabled"; }; + S6A: pm8150_1_s6: regulator-pm8150-1-s6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_1_s6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1352000>; + qcom,init-voltage = <600000>; + }; + + S4C: pm8150_2_s4: regulator-pm8150-2-s4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_2_s4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + qcom,init-voltage = <800000>; + }; + + S5C: pm8150_2_s5: regulator-pm8150-2-s5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_2_s5"; + regulator-min-microvolt = <1824000>; + regulator-max-microvolt = <2040000>; + qcom,init-voltage = <1824000>; + }; + + L15C: pm8150_2_l15: regulator-pm8150-2-l15 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_2_l15"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + qcom,init-voltage = <1800000>; + }; + vreg_wlan: vreg_wlan { compatible = "qcom,stub-regulator"; regulator-name = "vreg_wlan"; @@ -313,6 +208,62 @@ gpio = <&tlmm 174 0>; }; + pm8150_l2: regulator-pm8150-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_l2"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + qcom,init-voltage = <3072000>; + status = "okay"; + }; + + pm8150_l5: regulator-pm8150-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_l5"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <23800>; + qcom,init-voltage = <880000>; + status = "okay"; + }; + + pm8150_l12: regulator-pm8150-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_l12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + status = "okay"; + }; + + pm8150l_l3: regulator-pm8150l-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150l_l3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <51800>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + + pm8150_2_l8: regulator-pm8150-2-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_2_l8"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + status = "okay"; + }; + + pm8150_2_l18: regulator-pm8150-2-l18 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_2_l18"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + status = "okay"; + }; + VDD_CX_LEVEL: VDD_MMCX_LEVEL: S9C_LEVEL: pm8150_2_s9_level: regulator-pm8150-2-s9-level { compatible = "qcom,stub-regulator"; @@ -323,6 +274,24 @@ = ; }; + pcie_0_gdsc: pcie_0_gdsc { + compatible = "qcom,stub-regulator"; + regulator-name = "pcie_0_gdsc"; + status = "okay"; + }; + + usb30_prim_gdsc: usb30_prim_gdsc { + compatible = "qcom,stub-regulator"; + regulator-name = "usb30_prim_gdsc"; + status = "okay"; + }; + + usb30_sec_gdsc: usb30_sec_gdsc { + compatible = "qcom,stub-regulator"; + regulator-name = "usb30_sec_gdsc"; + status = "okay"; + }; + qcom_seecom: qseecom@87900000 { compatible = "qcom,qseecom"; reg = <0x87900000 0x2200000>; @@ -521,7 +490,6 @@ #include "sa8155-vm-audio.dtsi" #include "sa8155-vm-pcie.dtsi" #include "sa8155-vm-mhi.dtsi" -#include "pm8150-vm.dtsi" &tlmm { dirconn-list = <37 216 1>; diff --git a/arch/arm64/boot/dts/qcom/sa8155.dtsi b/arch/arm64/boot/dts/qcom/sa8155.dtsi index 95fa47b280ac..9e1752d2f128 100644 --- a/arch/arm64/boot/dts/qcom/sa8155.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8155.dtsi @@ -499,62 +499,6 @@ #include &soc { - hsi2s: qcom,hsi2s { - compatible = "qcom,sa8155-hsi2s", "qcom,hsi2s"; - number-of-interfaces = <3>; - reg = <0x172C0000 0x28000>, - <0x17080000 0xE000>; - reg-names = "lpa_if", "lpass_tcsr"; - interrupts = ; - bit-clock-hz = <20000000>; - interrupt-interval-ms = <10>; - - sdr0: qcom,hs0_i2s { - compatible = "qcom,hsi2s-interface"; - minor-number = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hs1_i2s_mclk_active &hs1_i2s_sck_active - &hs1_i2s_ws_active &hs1_i2s_data0_active - &hs1_i2s_data1_active>; - pinctrl-1 = <&hs1_i2s_mclk_sleep &hs1_i2s_sck_sleep - &hs1_i2s_ws_sleep &hs1_i2s_data0_sleep - &hs1_i2s_data1_sleep>; - iommus = <&apps_smmu 0x1B5C 0x0>; - qcom,smmu-s1-bypass; - qcom,iova-mapping = <0x0 0xFFFFFFFF>; - }; - - sdr1: qcom,hs1_i2s { - compatible = "qcom,hsi2s-interface"; - minor-number = <1>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hs2_i2s_mclk_active &hs2_i2s_sck_active - &hs2_i2s_ws_active &hs2_i2s_data0_active - &hs2_i2s_data1_active>; - pinctrl-1 = <&hs2_i2s_mclk_sleep &hs2_i2s_sck_sleep - &hs2_i2s_ws_sleep &hs2_i2s_data0_sleep - &hs2_i2s_data1_sleep>; - iommus = <&apps_smmu 0x1B5D 0x0>; - qcom,smmu-s1-bypass; - qcom,iova-mapping = <0x0 0xFFFFFFFF>; - }; - - sdr2: qcom,hs2_i2s { - compatible = "qcom,hsi2s-interface"; - minor-number = <2>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hs3_i2s_mclk_active &hs3_i2s_sck_active - &hs3_i2s_ws_active &hs3_i2s_data0_active - &hs3_i2s_data1_active>; - pinctrl-1 = <&hs3_i2s_mclk_sleep &hs3_i2s_sck_sleep - &hs3_i2s_ws_sleep &hs3_i2s_data0_sleep - &hs3_i2s_data1_sleep>; - iommus = <&apps_smmu 0x1B5E 0x0>; - qcom,smmu-s1-bypass; - qcom,iova-mapping = <0x0 0xFFFFFFFF>; - }; - }; - emac_hw: qcom,emac@00020000 { compatible = "qcom,emac-dwc-eqos"; qcom,arm-smmu; diff --git a/arch/arm64/boot/dts/qcom/sa8195-pmic.dtsi b/arch/arm64/boot/dts/qcom/sa8195-pmic.dtsi index c19adc024a9d..2cdf7df42ed9 100644 --- a/arch/arm64/boot/dts/qcom/sa8195-pmic.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8195-pmic.dtsi @@ -75,16 +75,40 @@ /delete-property/ vdda33-supply; }; -&lmh_dcvs1 { - isens_vref_0p8-supply = <&pm8195_3_l5>; - isens-vref-0p8-settings = <880000 880000 20000>; - isens_vref_1p8-supply = <&pm8195_1_l12>; - isens-vref-1p8-settings = <1800000 1800000 20000>; +&mdss_dsi0 { + vdda-1p2-supply = <&pm8195_1_l9>; }; -&clock_camcc { - vdd_mx-supply = <&VDD_MX_LEVEL>; - vdd_mm-supply = <&VDD_MMCX_LEVEL>; +&mdss_dsi1 { + vdda-1p2-supply = <&pm8195_1_l9>; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&pm8195_3_l5>; +}; + +&mdss_dsi_phy1 { + vdda-0p9-supply = <&pm8195_3_l5>; +}; + +&clock_cpucc { + lmh_dcvs1: qcom,limits-dcvs@18350800 { + isens_vref_0p8-supply = <&pm8195_3_l5>; + isens-vref-0p8-settings = <880000 880000 20000>; + isens_vref_1p8-supply = <&pm8195_1_l12>; + isens-vref-1p8-settings = <1800000 1800000 20000>; + }; +}; + + +&soc { + qcom,lpass@17300000 { + vdd_cx-supply = <&VDD_CX_LEVEL>; + }; + clock_camcc: qcom,camcc@ad00000 { + vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + }; }; &gpu_gx_gdsc { diff --git a/arch/arm64/boot/dts/qcom/sa8195-vm.dts b/arch/arm64/boot/dts/qcom/sa8195-vm.dts index 5c7ef0257b31..12807e33cf4e 100644 --- a/arch/arm64/boot/dts/qcom/sa8195-vm.dts +++ b/arch/arm64/boot/dts/qcom/sa8195-vm.dts @@ -36,11 +36,3 @@ &usb2_phy0 { status = "ok"; }; - -&spmi_bus { - status = "disabled"; -}; - -&viospmi { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/qcom/sa8195-vm.dtsi b/arch/arm64/boot/dts/qcom/sa8195-vm.dtsi index 1f0c3ded4e0f..12c910533271 100644 --- a/arch/arm64/boot/dts/qcom/sa8195-vm.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8195-vm.dtsi @@ -11,7 +11,7 @@ */ #include "skeleton64.dtsi" -#include +#include #include #include #include "quin-vm-common.dtsi" @@ -31,19 +31,16 @@ }; &soc { - clock_virt: qcom,virtio-gcc { - compatible = "virtio,mmio"; - reg = <0x1c200000 0x1000>; - interrupts = <0 48 0>; + clock_virt: qcom,virt-gcc { + compatible = "qcom,virt-clk-sm8150-gcc"; #clock-cells = <1>; #reset-cells = <1>; }; - clock_virt_scc: qcom,virtio-scc { - compatible = "virtio,mmio"; - reg = <0x1c300000 0x1000>; - interrupts = <0 49 0>; + clock_virt_scc: qcom,virt-scc { + compatible = "qcom,virt-clk-sm8150-scc"; #clock-cells = <1>; + #reset-cells = <1>; }; apps_smmu: apps-smmu@0x15000000 { @@ -139,55 +136,7 @@ , , , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + ; status = "disabled"; }; @@ -198,31 +147,44 @@ status = "disabled"; }; - pm8195_3_l5: regulator-pm8195-3-l5 { + pm8150_l2: regulator-pm8150-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8150_l2"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + qcom,init-voltage = <3072000>; + status = "okay"; + }; + + pm8150_l5: regulator-pm8150-l5 { compatible = "qcom,stub-regulator"; - regulator-name = "pm8195_3_l5"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <920000>; - qcom,init-voltage = <800000>; - status = "ok"; + regulator-name = "pm8150_l5"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <23800>; + qcom,init-voltage = <880000>; + status = "okay"; }; - pm8195_1_l12: regulator-pm8195-1-l12 { + pm8150_l12: regulator-pm8150-l12 { compatible = "qcom,stub-regulator"; - regulator-name = "pm8195_1_l12"; + regulator-name = "pm8150_l12"; regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1890000>; + regulator-max-microvolt = <1800000>; qcom,init-voltage = <1800000>; - status = "ok"; + status = "okay"; }; - pm8195_3_l16: regulator-pm8195-3-l16 { + pm8150l_l3: regulator-pm8150l-l3 { compatible = "qcom,stub-regulator"; - regulator-name = "pm8195_3_l16"; - regulator-min-microvolt = <2921000>; - regulator-max-microvolt = <3300000>; - qcom,init-voltage = <2921000>; - status = "ok"; + regulator-name = "pm8150l_l3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <51800>; + qcom,init-voltage = <1200000>; + status = "okay"; }; usb30_prim_gdsc: usb30_prim_gdsc { @@ -241,5 +203,5 @@ #include "sdmshrike-pinctrl.dtsi" #include "sm8150-slpi-pinctrl.dtsi" #include "sa8155-vm-qupv3.dtsi" -#include "sa8195-vm-usb.dtsi" +#include "sa8155-vm-usb.dtsi" #include "sa8155-vm-audio.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sa8195p-adp-star.dtsi b/arch/arm64/boot/dts/qcom/sa8195p-adp-star.dtsi index 260046900f35..02e46d986949 100644 --- a/arch/arm64/boot/dts/qcom/sa8195p-adp-star.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8195p-adp-star.dtsi @@ -11,7 +11,6 @@ */ #include -#include "sa8195p-adp-star-display.dtsi" &qupv3_se0_spi { status = "ok"; @@ -35,55 +34,3 @@ &qupv3_se12_2uart { status = "ok"; }; - -&sdhc_2 { - vdd-supply = <&pm8195_1_l10>; - qcom,vdd-voltage-level = <2950000 2960000>; - qcom,vdd-current-level = <200 800000>; - - vdd-io-supply = <&pm8195_1_l2>; - qcom,vdd-io-voltage-level = <1808000 2960000>; - qcom,vdd-io-current-level = <200 22000>; - - pinctrl-names = "active", "sleep"; - pinctrl-0 = <&sdc2_clk_on - &sdc2_cmd_on &sdc2_data_on &storage_cd_default>; - pinctrl-1 = <&sdc2_clk_off - &sdc2_cmd_off &sdc2_data_off &storage_cd_default>; - - cd-gpios = <&pm8195_1_gpios 4 GPIO_ACTIVE_LOW>; - - status = "ok"; -}; - -&pil_lpass { - status = "ok"; -}; - -&pil_ssc { - status = "disabled"; -}; - -&pil_spss { - status = "ok"; -}; - -&pil_turing { - status = "ok"; -}; - -&pil_venus { - status = "ok"; -}; - -&pil_npu { - status = "ok"; -}; - -&glink_modem { - status = "disabled"; -}; - -&ssc_sensors { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/qcom/sa8195p.dtsi b/arch/arm64/boot/dts/qcom/sa8195p.dtsi index 6fae09a904b5..237ab398e218 100644 --- a/arch/arm64/boot/dts/qcom/sa8195p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8195p.dtsi @@ -10,14 +10,8 @@ * GNU General Public License for more details. */ -#include #include "sdmshrike-v2.dtsi" #include "sa8155-audio.dtsi" -#include "sa8195-pmic.dtsi" -#include "sm8150-camera.dtsi" -#include "sm8150-v2-camera.dtsi" -#include "sa8155-camera-sensor.dtsi" -#include "sa8195p-pcie.dtsi" / { model = "Qualcomm Technologies, Inc. SA8195P"; @@ -25,6 +19,7 @@ qcom,msm-id = <405 0x20000>; }; +#include &soc { emac_hw: qcom,emac@00020000 { compatible = "qcom,emac-dwc-eqos"; @@ -110,220 +105,4 @@ qcom,iova-mapping = <0x80000000 0x40000000>; }; }; - - qcom,cam_smmu { - msm_cam_smmu_ife { - iommus = <&apps_smmu 0xAA0 0x4E0>, - <&apps_smmu 0xA20 0x4E0>, - <&apps_smmu 0xA00 0x4E0>, - <&apps_smmu 0xA80 0x4E0>, - <&apps_smmu 0xEA0 0x4E0>, - <&apps_smmu 0xE20 0x4E0>, - <&apps_smmu 0xE00 0x4E0>, - <&apps_smmu 0xE80 0x4E0>; - }; - - msm_cam_smmu_jpeg { - iommus = <&apps_smmu 0x2100 0x20>, - <&apps_smmu 0x2120 0x20>; - }; - - msm_cam_smmu_icp { - iommus = <&apps_smmu 0x2042 0x0>, - <&apps_smmu 0x2080 0x320>, - <&apps_smmu 0x20A0 0x320>, - <&apps_smmu 0x2380 0x320>, - <&apps_smmu 0x23A0 0x320>, - <&apps_smmu 0x20C0 0x300>, - <&apps_smmu 0x23C0 0x300>; - }; - - msm_cam_smmu_fd { - iommus = <&apps_smmu 0x2140 0x20>, - <&apps_smmu 0x2160 0x20>; - }; - - msm_cam_smmu_lrme { - iommus = <&apps_smmu 0x20e0 0x300>, - <&apps_smmu 0x23E0 0x300>; - }; - }; - - cam_csid0 { - clock-rates = - <400000000 0 0 0 400000000 0 0>, - <400000000 0 0 0 558000000 0 0>, - <480000000 0 0 0 637000000 0 0>, - <600000000 0 0 0 760000000 0 0>; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; - }; - - cam_csid1 { - clock-rates = - <400000000 0 0 0 400000000 0 0>, - <400000000 0 0 0 558000000 0 0>, - <480000000 0 0 0 637000000 0 0>, - <600000000 0 0 0 760000000 0 0>; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; - }; - - cam_vfe0 { - clock-rates = - <400000000 0 0>, - <558000000 0 0>, - <637000000 0 0>, - <760000000 0 0>; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; - }; - - cam_vfe1 { - clock-rates = - <400000000 0 0>, - <558000000 0 0>, - <637000000 0 0>, - <760000000 0 0>; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; - }; -}; - -&usb1 { - qcom,default-mode-host; - status = "ok"; -}; - -&slpi_tlmm { - status = "ok"; -}; - -&pil_ssc { - vdd_cx-supply = <&VDD_CX_LEVEL>; - vdd_mx-supply = <&VDD_MX_LEVEL>; - status = "ok"; -}; - -&ssc_sensors { - status = "disabled"; -}; - -&clock_rpmh { - compatible = "qcom,rpmh-clk-sm8150"; -}; - -&clock_scc { - compatible = "qcom,scc-sa8195"; -}; - -&ufsphy_mem { - compatible = "qcom,ufs-phy-qmp-v4"; - vdda-phy-supply = <&pm8195_3_l5>; - vdda-pll-supply = <&pm8195_1_l9>; - vdda-phy-max-microamp = <138000>; - vdda-pll-max-microamp = <65100>; - - status = "ok"; -}; - -&ufshc_mem { - vdd-hba-supply = <&ufs_phy_gdsc>; - vdd-hba-fixed-regulator; - vcc-supply = <&pm8195_3_l10>; - vcc-voltage-level = <2894000 2904000>; - vcc-low-voltage-sup; - vccq-supply = <&pm8195_1_l11>; - vccq2-supply = <&pm8195_3_l7>; - vcc-max-microamp = <750000>; - vccq-max-microamp = <750000>; - vccq2-max-microamp = <750000>; - - status= "ok"; -}; - -&usb2_phy0 { - vdd-supply = <&pm8195_3_l5>; - vdda18-supply = <&pm8195_1_l12>; - vdda33-supply = <&pm8195_3_l16>; -}; - -&usb2_phy1 { - vdd-supply = <&pm8195_3_l5>; - vdda18-supply = <&pm8195_1_l12>; - vdda33-supply = <&pm8195_3_l16>; - status = "ok"; -}; - -&mdss_dsi_phy0 { - vdda-0p9-supply = <&pm8195_3_l5>; -}; - -&mdss_dsi_phy1 { - vdda-0p9-supply = <&pm8195_3_l5>; -}; - -&mdss_dsi0 { - vdda-1p2-supply = <&pm8195_1_l9>; -}; - -&mdss_dsi1 { - vdda-1p2-supply = <&pm8195_1_l9>; -}; - -&sde_dp { - vdda-1p2-supply = <&pm8195_1_l9>; - vdda-0p9-supply = <&pm8195_3_l5>; -}; - -&pil_lpass { - vdd_cx-supply = <&VDD_CX_LEVEL>; - status = "ok"; -}; - -&clock_scc { - vdd_scc_cx-supply = <&pm8195_3_l8_level>; - status = "ok"; -}; - -&cam_csiphy0 { - mipi-csi-vdd-supply = <&pm8195_1_l9>; -}; - -&cam_csiphy1 { - mipi-csi-vdd-supply = <&pm8195_1_l9>; -}; - -&cam_csiphy2 { - mipi-csi-vdd-supply = <&pm8195_1_l9>; -}; - -&cam_csiphy3 { - mipi-csi-vdd-supply = <&pm8195_1_l9>; -}; - -&cam_cci0 { - qcom,cam-sensor@0 { - cam_vio-supply = <&pm8195_s4>; - cam_bob-supply = <&pm8195_s4>; - cam_vana-supply = <&pm8195_s4>; - cam_vdig-supply = <&pm8195_s4>; - }; - - qcom,cam-sensor@1 { - cam_vio-supply = <&pm8195_s4>; - cam_bob-supply = <&pm8195_s4>; - cam_vana-supply = <&pm8195_s4>; - cam_vdig-supply = <&pm8195_s4>; - }; - - qcom,cam-sensor@2 { - cam_vio-supply = <&pm8195_s4>; - cam_bob-supply = <&pm8195_s4>; - cam_vana-supply = <&pm8195_s4>; - cam_vdig-supply = <&pm8195_s4>; - }; - - qcom,cam-sensor@3 { - cam_vio-supply = <&pm8195_s4>; - cam_bob-supply = <&pm8195_s4>; - cam_vana-supply = <&pm8195_s4>; - cam_vdig-supply = <&pm8195_s4>; - }; }; diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-idp.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie-idp.dtsi index 27c0b7a14822..5b7a01baa270 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-idp.dtsi @@ -258,48 +258,6 @@ qcom,platform-te-gpio = <&tlmm 11 0>; }; -&dsi_sharp_qsync_wqhd_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 10 0>; - qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; - qcom,platform-en-gpio = <&pm6150l_gpios 4 0>; - qcom,platform-bklight-en-gpio = <&pm6150l_gpios 5 0>; -}; - -&dsi_sharp_qsync_wqhd_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; - qcom,platform-en-gpio = <&pm6150l_gpios 4 0>; - qcom,platform-bklight-en-gpio = <&pm6150l_gpios 5 0>; -}; - -&dsi_sharp_qsync_fhd_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; - qcom,platform-en-gpio = <&pm6150l_gpios 4 0>; - qcom,platform-bklight-en-gpio = <&pm6150l_gpios 5 0>; -}; - -&dsi_sharp_qsync_fhd_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,platform-te-gpio = <&tlmm 10 0>; - qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>; - qcom,platform-en-gpio = <&pm6150l_gpios 4 0>; - qcom,platform-bklight-en-gpio = <&pm6150l_gpios 5 0>; -}; - &sde_dp { qcom,dp-aux-switch = <&fsa4480>; }; diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi index f39f94baa14c..4bbb187fa85b 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi @@ -26,10 +26,6 @@ #include "dsi-panel-rm69299-visionox-amoled-fhd-plus-video.dtsi" #include "dsi-panel-nt35695b-truly-fhd-video.dtsi" #include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi" -#include "dsi-panel-sharp-qsync-wqhd-cmd.dtsi" -#include "dsi-panel-sharp-qsync-wqhd-video.dtsi" -#include "dsi-panel-sharp-qsync-fhd-video.dtsi" -#include "dsi-panel-sharp-qsync-fhd-cmd.dtsi" #include &soc { @@ -303,50 +299,6 @@ qcom,dsi-panel = <&dsi_rm69299_visionox_amoled_video>; }; - dsi_sharp_qsync_wqhd_cmd_display: qcom,dsi-display@18 { - label = "dsi_sharp_qsync_wqhd_cmd_display"; - qcom,display-type = "primary"; - - qcom,dsi-ctrl-num = <0 1>; - qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - - qcom,dsi-panel = <&dsi_sharp_qsync_wqhd_cmd>; - }; - - dsi_sharp_qsync_wqhd_video_display: qcom,dsi-display@19 { - label = "dsi_sharp_qsync_wqhd_video_display"; - qcom,display-type = "primary"; - - qcom,dsi-ctrl-num = <0 1>; - qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - - qcom,dsi-panel = <&dsi_sharp_qsync_wqhd_video>; - }; - - dsi_sharp_qsync_fhd_video_display: qcom,dsi-display@20 { - label = "dsi_sharp_qsync_fhd_video_display"; - qcom,display-type = "primary"; - - qcom,dsi-ctrl-num = <0 1>; - qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - - qcom,dsi-panel = <&dsi_sharp_qsync_fhd_video>; - }; - - dsi_sharp_qsync_fhd_cmd_display: qcom,dsi-display@21 { - label = "dsi_sharp_qsync_fhd_cmd_display"; - qcom,display-type = "primary"; - - qcom,dsi-ctrl-num = <0 1>; - qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; - - qcom,dsi-panel = <&dsi_sharp_qsync_fhd_cmd>; - }; - sde_dsi: qcom,dsi-display { compatible = "qcom,dsi-display"; @@ -395,11 +347,7 @@ &dsi_rm69298_truly_amoled_cmd_display &dsi_nt35695b_truly_fhd_video_display &dsi_nt35695b_truly_fhd_cmd_display - &dsi_rm69299_visionox_amoled_vid_display - &dsi_sharp_qsync_wqhd_cmd_display - &dsi_sharp_qsync_wqhd_video_display - &dsi_sharp_qsync_fhd_video_display - &dsi_sharp_qsync_fhd_cmd_display>; + &dsi_rm69299_visionox_amoled_vid_display>; }; @@ -788,91 +736,6 @@ qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08 08 05 02 04 00]; qcom,display-topology = <1 0 1>; - }; - }; -}; - -&dsi_sharp_qsync_wqhd_cmd { - qcom,mdss-dsi-t-clk-post = <0x0B>; - qcom,mdss-dsi-t-clk-pre = <0x24>; - qcom,mdss-dsi-display-timings { - timing@0{ /* 2k */ - qcom,mdss-dsi-panel-phy-timings = [00 0B 03 02 1D 1C 03 - 03 01 02 04 00]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - timing@1{ /* fhd */ - qcom,mdss-dsi-panel-phy-timings = [00 0A 01 02 1B 1B 02 - 02 00 02 04 00]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - timing@2{ - qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 1E 1E 04 - 04 02 02 04 00]; - qcom,mdss-mdp-transfer-time-us = <8500>; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - timing@3{ - qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06 - 06 03 02 04 00]; - qcom,mdss-mdp-transfer-time-us = <5800>; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sharp_qsync_wqhd_video { - qcom,mdss-dsi-t-clk-post = <0x0A>; - qcom,mdss-dsi-t-clk-pre = <0x1E>; - qcom,mdss-dsi-display-timings { - timing@0{ - qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 1E 1E 04 - 04 02 02 04 00]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sharp_qsync_fhd_video { - qcom,mdss-dsi-t-clk-post = <0x0A>; - qcom,mdss-dsi-t-clk-pre = <0x20>; - qcom,mdss-dsi-display-timings { - timing@0{ - qcom,mdss-dsi-panel-phy-timings = [00 13 04 04 1F 1F 04 - 05 03 02 04 00]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - }; -}; - -&dsi_sharp_qsync_fhd_cmd { - qcom,mdss-dsi-t-clk-post = <0x09>; - qcom,mdss-dsi-t-clk-pre = <0x12>; - qcom,mdss-dsi-display-timings { - timing@0{ - qcom,mdss-dsi-panel-phy-timings = [00 0A 01 02 1B 1B 02 - 02 00 02 04 00]; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - timing@1{ - qcom,mdss-dsi-panel-phy-timings = [00 0C 02 02 1D 1C 03 - 03 01 02 04 00]; - qcom,mdss-mdp-transfer-time-us = <8500>; - qcom,display-topology = <2 2 2>; - qcom,default-topology-index = <0>; - }; - timing@2{ - qcom,mdss-dsi-panel-phy-timings = [00 0F 03 03 1E 1D 04 - 04 02 02 04 00]; - qcom,mdss-mdp-transfer-time-us = <5800>; - qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-thermal-overlay.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie-thermal-overlay.dtsi index 37c22bca3baf..f47d16937319 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-thermal-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-thermal-overlay.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -125,16 +125,16 @@ }; }; - pm6150-bcl-lvl0 { + pm6150-vbat-lvl0 { cooling-maps { vbat_cpu6 { - trip = <&bcl_lvl0>; + trip = <&vbat_lvl0>; cooling-device = <&CPU6 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; vbat_cpu7 { - trip = <&bcl_lvl0>; + trip = <&vbat_lvl0>; cooling-device = <&CPU7 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; @@ -142,33 +142,16 @@ }; }; - pm6150-bcl-lvl1 { + pm6150-ibat-lvl0 { cooling-maps { ibat_cpu6 { - trip = <&bcl_lvl1>; + trip = <&ibat_lvl0>; cooling-device = <&CPU6 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; ibat_cpu7 { - trip = <&bcl_lvl1>; - cooling-device = - <&CPU7 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - pm6150-bcl-lvl2 { - cooling-maps { - ibat_cpu6 { - trip = <&bcl_lvl2>; - cooling-device = - <&CPU6 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - ibat_cpu7 { - trip = <&bcl_lvl2>; + trip = <&ibat_lvl0>; cooling-device = <&CPU7 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-usb.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie-usb.dtsi index 28103989d07d..367be23a8c81 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-usb.dtsi @@ -19,8 +19,6 @@ reg = <0x0a600000 0x100000>; reg-names = "core_base"; - iommus = <&apps_smmu 0x540 0x0>; - qcom,smmu-s1-bypass; #address-cells = <1>; #size-cells = <1>; ranges; @@ -54,7 +52,6 @@ 0x130 /* GSI_RING_BASE_ADDR_L */ 0x144 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ - qcom,gsi-disable-io-coherency; qcom,dwc-usb3-msm-tx-fifo-size = <21288>; qcom,pm-qos-latency = <62>; diff --git a/arch/arm64/boot/dts/qcom/sdmshrike-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sdmshrike-pinctrl.dtsi index cbc0a8078a31..36a98fc4fbc0 100644 --- a/arch/arm64/boot/dts/qcom/sdmshrike-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmshrike-pinctrl.dtsi @@ -1819,77 +1819,6 @@ }; }; - ap2mdm { - ap2mdm_active: ap2mdm_active { - mux { - /* ap2mdm-status - * ap2mdm-errfatal - * ap2mdm-vddmin - */ - pins = "gpio135", "gpio139"; - function = "gpio"; - }; - - config { - pins = "gpio135", "gpio139"; - drive-strength = <16>; - bias-disable; - }; - }; - ap2mdm_sleep: ap2mdm_sleep { - mux { - /* ap2mdm-status - * ap2mdm-errfatal - * ap2mdm-vddmin - */ - pins = "gpio135", "gpio139"; - function = "gpio"; - }; - - config { - pins = "gpio135", "gpio139"; - drive-strength = <8>; - bias-disable; - }; - - }; - }; - - mdm2ap { - mdm2ap_active: mdm2ap_active { - mux { - /* mdm2ap-status - * mdm2ap-errfatal - * mdm2ap-vddmin - */ - pins = "gpio81", "gpio53"; - function = "gpio"; - }; - - config { - pins = "gpio81", "gpio53"; - drive-strength = <8>; - bias-disable; - }; - }; - mdm2ap_sleep: mdm2ap_sleep { - mux { - /* mdm2ap-status - * mdm2ap-errfatal - * mdm2ap-vddmin - */ - pins = "gpio81", "gpio53"; - function = "gpio"; - }; - - config { - pins = "gpio81", "gpio53"; - drive-strength = <8>; - bias-disable; - }; - }; - }; - cam_sensor_mclk0_active: cam_sensor_mclk0_active { /* MCLK0 */ mux { diff --git a/arch/arm64/boot/dts/qcom/sdmshrike-v2.dtsi b/arch/arm64/boot/dts/qcom/sdmshrike-v2.dtsi index ee52993f5481..13c41d54eb87 100644 --- a/arch/arm64/boot/dts/qcom/sdmshrike-v2.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmshrike-v2.dtsi @@ -260,134 +260,3 @@ iommus = <&apps_smmu 0x1009 0x0460>; }; }; - -&soc { - /delete-node/ llcc-bw-opp-table; - /delete-node/ ddr-bw-opp-table; - /delete-node/ suspendable-ddr-bw-opp-table; - - llcc_bw_opp_table: llcc-bw-opp-table { - compatible = "operating-points-v2"; - BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ - BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */ - BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */ - BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */ - BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */ - BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */ - BW_OPP_ENTRY(1000, 16); /* 15258 MB/s */ - }; - - ddr_bw_opp_table: ddr-bw-opp-table { - compatible = "operating-points-v2"; - BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ - BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ - BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ - BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ - BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ - BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ - BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ - BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */ - BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ - BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ - BW_OPP_ENTRY(2092, 4); /* 7980 MB/s */ - }; - - suspendable_ddr_bw_opp_table: suspendable-ddr-bw-opp-table { - compatible = "operating-points-v2"; - BW_OPP_ENTRY( 0, 4); /* 0 MB/s */ - BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ - BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ - BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ - BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ - BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ - BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ - BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ - BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */ - BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ - BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ - BW_OPP_ENTRY(2092, 4); /* 7980 MB/s */ - }; -}; - -&gpubw { - /delete-property/ qcom,bw-tbl; - operating-points-v2 = <&suspendable_ddr_bw_opp_table>; -}; - -&cpu4_computemon { - qcom,core-dev-table = - < 1920000 MHZ_TO_MBPS( 200, 4) >, - < 2793600 MHZ_TO_MBPS(1017, 4) >, - < 3000000 MHZ_TO_MBPS(2092, 4) >; -}; - -&cpu0_llcc_ddr_latmon { - qcom,core-dev-table = - < 300000 MHZ_TO_MBPS( 200, 4) >, - < 768000 MHZ_TO_MBPS( 451, 4) >, - < 1113600 MHZ_TO_MBPS( 547, 4) >, - < 1478400 MHZ_TO_MBPS( 768, 4) >, - < 1632000 MHZ_TO_MBPS(1017, 4) >; -}; - -&cpu4_llcc_ddr_latmon { - qcom,core-dev-table = - < 300000 MHZ_TO_MBPS( 200, 4) >, - < 710400 MHZ_TO_MBPS( 451, 4) >, - < 825600 MHZ_TO_MBPS( 547, 4) >, - < 1056000 MHZ_TO_MBPS( 768, 4) >, - < 1286400 MHZ_TO_MBPS(1017, 4) >, - < 1612800 MHZ_TO_MBPS(1353, 4) >, - < 1804800 MHZ_TO_MBPS(1555, 4) >, - < 2649600 MHZ_TO_MBPS(1804, 4) >, - < 3000000 MHZ_TO_MBPS(2092, 4) >; -}; - -&cpu0_cpu_l3_latmon { - qcom,core-dev-table = - < 300000 300000000 >, - < 499200 403200000 >, - < 576000 499200000 >, - < 672000 614400000 >, - < 768000 710400000 >, - < 940800 806400000 >, - < 1036800 902400000 >, - < 1113600 998400000 >, - < 1209600 1075280000 >, - < 1305600 1171200000 >, - < 1382400 1267200000 >, - < 1478400 1344000000 >, - < 1632000 1536000000 >, - < 1785600 1612800000 >; -}; - -&cpu4_cpu_l3_latmon { - qcom,core-dev-table = - < 300000 300000000 >, - < 825600 614400000 >, - < 1171200 806400000 >, - < 1401600 998400000 >, - < 1708800 1267200000 >, - < 2016000 1344000000 >, - < 2419200 1536000000 >, - < 2841600 1612800000 >; -}; - -&cpu0_cpu_llcc_latmon { - qcom,core-dev-table = - < 300000 MHZ_TO_MBPS( 150, 16) >, - < 768000 MHZ_TO_MBPS( 300, 16) >, - < 1478400 MHZ_TO_MBPS( 466, 16) >, - < 1632000 MHZ_TO_MBPS( 600, 16) >; -}; - -&cpu4_cpu_llcc_latmon { - qcom,core-dev-table = - < 300000 MHZ_TO_MBPS( 150, 16) >, - < 710400 MHZ_TO_MBPS( 300, 16) >, - < 1056000 MHZ_TO_MBPS( 466, 16) >, - < 1286400 MHZ_TO_MBPS( 600, 16) >, - < 1804800 MHZ_TO_MBPS( 806, 16) >, - < 2649600 MHZ_TO_MBPS( 933, 16) >, - < 3000000 MHZ_TO_MBPS(1000, 16) >; -}; diff --git a/arch/arm64/boot/dts/qcom/sdmshrike.dtsi b/arch/arm64/boot/dts/qcom/sdmshrike.dtsi index 6444e2578bed..50372a88962a 100644 --- a/arch/arm64/boot/dts/qcom/sdmshrike.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmshrike.dtsi @@ -2298,11 +2298,6 @@ }; }; - aop-msg-client { - compatible = "qcom,debugfs-qmp-client"; - mboxes = <&qmp_aop 0>; - mbox-names = "aop"; - }; }; &emac_gdsc { diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dtsi index 8fbf342620c1..f0dfb1eb9a01 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-pcie-ep-mtp.dtsi @@ -40,7 +40,3 @@ &mhi_device { status = "ok"; }; - -&mhi_net_device { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi index 2ba4e8fefb26..841e1675dc7a 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi @@ -1473,32 +1473,5 @@ }; }; - a2b_cdc_sel { - a2b_cdc_sel_default: a2b_cdc_sel_default { - mux { - pins = "gpio97"; - function = "gpio"; - }; - - config { - pins = "gpio97"; - drive-strength = <8>; - bias-disable; - output-high; - }; - }; - }; - - pinctrl_pps: ppsgrp { - mux { - pins = "gpio32"; - function = "nav_gpio"; - }; - - config { - pins = "gpio32"; - bias-pull-down; - }; - }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-regulator.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-regulator.dtsi index 99a5d9774dbd..817bef3db90a 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-regulator.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-regulator.dtsi @@ -508,13 +508,4 @@ gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; enable-active-high; }; - - /* PWR_CTR1_VDD_PA supply */ - vreg_conn_pa: vreg_conn_pa { - compatible = "regulator-fixed"; - regulator-name = "vreg_conn_pa"; - startup-delay-us = <4000>; - enable-active-high; - gpio = <&pmxprairie_gpios 2 GPIO_ACTIVE_HIGH>; - }; }; diff --git a/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi index a09c1c50e69a..a250c6c4fb74 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie-usb.dtsi @@ -54,7 +54,6 @@ 0x240 /* GSI_RING_BASE_ADDR_L */ 0x25c /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ - qcom,gsi-disable-io-coherency; qcom,dwc-usb3-msm-tx-fifo-size = <27696>; qcom,msm-bus,name = "usb"; diff --git a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi index fdb7bca4eee6..9ca2c95b20c8 100644 --- a/arch/arm64/boot/dts/qcom/sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdxprairie.dtsi @@ -691,11 +691,6 @@ }; }; - qcom,mhi_dev_qrtr { - compatible = "qcom,qrtr-mhi-dev"; - qcom,net-id = <3>; - }; - qcom,glinkpkt { compatible = "qcom,glinkpkt"; @@ -1361,12 +1356,6 @@ status = "disabled"; }; - mhi_net_device: qcom,mhi_net_dev { - compatible = "qcom,msm-mhi-dev-net"; - qcom,mhi-ethernet-interface; - status = "disabled"; - }; - sdhc_1: sdhci@8804000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x8804000 0x1000>; @@ -1417,7 +1406,7 @@ qcom,arm-smmu; reg = <0x20000 0x10000>, <0x36000 0x100>, - <0xf100000 0x300000>; + <0x3900000 0x300000>; reg-names = "emac-base", "rgmii-base", "tlmm-central-base"; interrupts-extended = <&pdc 0 62 4>, <&pdc 0 60 4>, <&tlmm 90 2>, <&pdc 0 49 4>, diff --git a/arch/arm64/boot/dts/qcom/sm6150-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sm6150-pinctrl.dtsi index 037e57511850..df5960c939e9 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-pinctrl.dtsi @@ -1821,7 +1821,7 @@ pins = "gpio38"; drive-strength = <4>; /* 4 mA */ bias-no-pull; - output-high; + input-enable; }; }; }; @@ -1849,7 +1849,7 @@ pins = "gpio39"; drive-strength = <4>; /* 4 mA */ bias-no-pull; - input-enable; + output-high; }; }; }; @@ -1905,7 +1905,7 @@ pins = "gpio26"; drive-strength = <4>; /* 4 mA */ bias-no-pull; - output-high; + input-enable; }; }; }; @@ -1933,7 +1933,7 @@ pins = "gpio27"; drive-strength = <4>; /* 4 mA */ bias-no-pull; - input-enable; + output-high; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6150-thermal-overlay.dtsi b/arch/arm64/boot/dts/qcom/sm6150-thermal-overlay.dtsi index 37c22bca3baf..f47d16937319 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-thermal-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-thermal-overlay.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -125,16 +125,16 @@ }; }; - pm6150-bcl-lvl0 { + pm6150-vbat-lvl0 { cooling-maps { vbat_cpu6 { - trip = <&bcl_lvl0>; + trip = <&vbat_lvl0>; cooling-device = <&CPU6 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; vbat_cpu7 { - trip = <&bcl_lvl0>; + trip = <&vbat_lvl0>; cooling-device = <&CPU7 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; @@ -142,33 +142,16 @@ }; }; - pm6150-bcl-lvl1 { + pm6150-ibat-lvl0 { cooling-maps { ibat_cpu6 { - trip = <&bcl_lvl1>; + trip = <&ibat_lvl0>; cooling-device = <&CPU6 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; ibat_cpu7 { - trip = <&bcl_lvl1>; - cooling-device = - <&CPU7 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - }; - }; - - pm6150-bcl-lvl2 { - cooling-maps { - ibat_cpu6 { - trip = <&bcl_lvl2>; - cooling-device = - <&CPU6 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - ibat_cpu7 { - trip = <&bcl_lvl2>; + trip = <&ibat_lvl0>; cooling-device = <&CPU7 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; diff --git a/arch/arm64/boot/dts/qcom/sm6150-usb.dtsi b/arch/arm64/boot/dts/qcom/sm6150-usb.dtsi index f8a5554f5bee..29f885820156 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-usb.dtsi @@ -55,7 +55,6 @@ 0x130 /* GSI_RING_BASE_ADDR_L */ 0x144 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ - qcom,gsi-disable-io-coherency; qcom,dwc-usb3-msm-tx-fifo-size = <21288>; qcom,pm-qos-latency = <61>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-audio.dtsi b/arch/arm64/boot/dts/qcom/sm8150-audio.dtsi index 32e1ec1a75b7..a94883687fdf 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-audio.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-audio.dtsi @@ -157,9 +157,9 @@ &qupv3_se4_i2c { status = "ok"; - fsa4480: fsa4480@43 { + fsa4480: fsa4480@42 { compatible = "qcom,fsa4480-i2c"; - reg = <0x43>; + reg = <0x42>; pinctrl-names = "default"; pinctrl-0 = <&fsa_usbc_ana_en>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150-camera-sensor-mtp.dtsi b/arch/arm64/boot/dts/qcom/sm8150-camera-sensor-mtp.dtsi index 2bd902951c54..7de91fecbd1c 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-camera-sensor-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-camera-sensor-mtp.dtsi @@ -112,6 +112,7 @@ actuator_triple_rear_aux2_regulator: gpio-regulator@6 { compatible = "regulator-fixed"; + status = "disable"; reg = <0x06 0x00>; regulator-name = "actuator_triple_rear_aux2_regulator"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-camera.dtsi b/arch/arm64/boot/dts/qcom/sm8150-camera.dtsi index c20f5a7b7eeb..51944ac4c0cb 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-camera.dtsi @@ -387,10 +387,10 @@ }; iova-mem-region-shared { - /* Shared region is 100MB long */ + /* Shared region is 200MB long */ iova-region-name = "shared"; iova-region-start = <0x7400000>; - iova-region-len = <0x6400000>; + iova-region-len = <0xc800000>; iova-region-id = <0x1>; status = "ok"; }; @@ -398,7 +398,7 @@ iova-mem-region-secondary-heap { /* Secondary heap region is 1MB long */ iova-region-name = "secheap"; - iova-region-start = <0xd800000>; + iova-region-start = <0x13C00000>; iova-region-len = <0x100000>; iova-region-id = <0x4>; status = "ok"; @@ -407,8 +407,8 @@ iova-mem-region-io { /* IO region is approximately 3 GB */ iova-region-name = "io"; - iova-region-start = <0xda00000>; - iova-region-len = <0xace00000>; + iova-region-start = <0x13E00000>; + iova-region-len = <0xa6a00000>; iova-region-id = <0x3>; status = "ok"; }; @@ -416,7 +416,7 @@ iova-mem-qdss-region { /* QDSS region is appropriate 1MB */ iova-region-name = "qdss"; - iova-region-start = <0xd900000>; + iova-region-start = <0x13D00000>; iova-region-len = <0x100000>; iova-region-id = <0x5>; qdss-phy-addr = <0x16790000>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-mhi.dtsi b/arch/arm64/boot/dts/qcom/sm8150-mhi.dtsi index ee8c5a375547..9f53e564ccdf 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mhi.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-mhi.dtsi @@ -546,11 +546,6 @@ mhi,mru = <0x8000>; mhi,rsc-parent = <&mhi_netdev_0>; }; - - mhi_qrtr { - mhi,chan = "IPCR"; - mhi,early-notify; - }; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi b/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi index fa4cc5656e30..54c520d0981d 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi @@ -53,7 +53,8 @@ extcon_usb1: extcon_usb1 { compatible = "linux,extcon-usb-gpio"; - vbus-gpio = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>; + /*pm8150_gpios 10 is for step motor, use the dummy gpio 165 for driver probe */ + vbus-gpio = <&tlmm 165 GPIO_ACTIVE_HIGH>; id-gpio = <&tlmm 101 GPIO_ACTIVE_HIGH>; vbus-out-gpio = <&pm8150_gpios 9 GPIO_ACTIVE_HIGH>; @@ -95,7 +96,7 @@ }; }; - qcom,qbt1000 { + qcomqbt1000:qcom,qbt1000 { compatible = "qcom,qbt1000"; clock-names = "core", "iface"; clock-frequency = <25000000>; @@ -323,8 +324,9 @@ qcom,fg-esr-timer-dischg-fast = <0 7>; qcom,fg-esr-timer-chg-slow = <0 96>; qcom,fg-esr-timer-dischg-slow = <0 96>; - qcom,fg-esr-cal-soc-thresh = <26 230>; - qcom,fg-esr-cal-temp-thresh = <10 40>; + /*op disable ers calibration*/ + /*qcom,fg-esr-cal-soc-thresh = <26 230>;*/ + /*qcom,fg-esr-cal-temp-thresh = <10 40>;*/ }; &sdhc_2 { @@ -602,18 +604,10 @@ }; skin-msm-therm { - polling-delay-passive = <0>; + polling-delay-passive = <2000>; polling-delay = <0>; - thermal-governor = "user_space"; + thermal-governor = "step_wise"; thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>; - wake-capable-sensor; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; }; pa-therm2 { @@ -649,7 +643,7 @@ "usb_in_voltage"; qcom,battery-data = <&mtp_batterydata>; qcom,step-charging-enable; - qcom,sw-jeita-enable; + //qcom,sw-jeita-enable; qcom,wd-bark-time-secs = <16>; qcom,suspend-input-on-debug-batt; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150-oem-camera-guacamoleb.dtsi b/arch/arm64/boot/dts/qcom/sm8150-oem-camera-guacamoleb.dtsi new file mode 100644 index 000000000000..0647e8ebf677 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-oem-camera-guacamoleb.dtsi @@ -0,0 +1,889 @@ +/*this is for camera dtsi*/ +&pm8150l_gpios{ + cam_sensor_pmi_gpio { + + cam_sensor_rear_1_dvdd_active: cam_sensor_rear_1_dvdd_active { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_1_dvdd_suspend: cam_sensor_rear_1_dvdd_suspend { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + }; + + cam_sensor_front_0_ana { + cam_sensor_front_0_ana_active: cam_sensor_front_0_ana_active { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_ana_suspend: cam_sensor_front_0_ana_suspend { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; + + cam_sensor_front_0_dvdd { + cam_sensor_front_0_dvdd_active: cam_sensor_front_0_dvdd_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_dvdd_suspend: cam_sensor_front_0_dvdd_suspend { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; + +}; + +&soc { + led_flash_rear_0: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + + led_flash_rear_1: qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; +}; + +&cam_cci0 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + shared-gpios = <14 13>; + pinctrl-names = "cam_res_mgr_default", "cam_res_mgr_suspend"; + status = "ok"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_1_mclk_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_1_mclk_suspend>; + }; + + actuator_rear_0: qcom,actuator@7 { + cell-index = <7>; + reg = <0x7>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_0_vaf_suspend>; + gpios = <&tlmm 35 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_0"; + }; + + actuator_rear_1: qcom,actuator@8 { + cell-index = <8>; + reg = <0x8>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_0_vaf_suspend>; + gpios = <&tlmm 35 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + ois_rear_0: qcom,ois@2 { + cell-index = <2>; + reg = <2>; + compatible = "qcom,ois"; + cam_vio-supply = <&pm8150l_l1>; + cam_vdig-supply = <&pm8150l_s8>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vio", "cam_vdig", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1352000 3300000>; + rgltr-max-voltage = <0 1352000 3300000>; + rgltr-load-current = <0 1100000 0>; + gpio-no-mux = <0>; + use-shared-clk; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_ois_active + &cam_sensor_rear_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_rear_0_ois_suspend + &cam_sensor_rear_0_dvdd_suspend>; + gpios = <&tlmm 87 0>, + <&tlmm 24 0>; + gpio-vaf = <0>; + gpio-vdig = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <0 0>; + gpio-req-tbl-label = "OIS_REAR_0", + "CAM_VDIG"; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + }; + + ois_rear_1: qcom,ois@1 { + }; + + eeprom_rear_0: qcom,eeprom@7 { + cell-index = <7>; + reg = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_s8>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1352000 0>; + rgltr-max-voltage = <0 3300000 1352000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_dvdd_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 24 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_VDIG_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_1: qcom,eeprom@8 { + cell-index = <8>; + reg = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150_s4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1800000 0>; + rgltr-max-voltage = <0 3300000 1800000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active + &cam_sensor_rear_1_dvdd_active + &cam_sensor_rear_0_ois_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend + &cam_sensor_rear_1_dvdd_suspend + &cam_sensor_rear_0_ois_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>, + <&tlmm 87 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-custom1 = <4>; + gpio-req-tbl-num = <0 1 2 3 0>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1", + "CAM_VDIG_1", + "OIS_REAR_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front_0: qcom,eeprom@9 { + cell-index = <9>; + reg = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_s8>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1352000 0>; + rgltr-max-voltage = <0 3300000 1352000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active + &cam_sensor_front_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend + &cam_sensor_front_0_dvdd_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>, + <&pm8150l_gpios 1 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2", + "CAM_VDIG_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_0>; + actuator-src = <&actuator_rear_0>; + ois-src = <&ois_rear_0>; + eeprom-src = <&eeprom_rear_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_s8>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1352000 0>; + rgltr-max-voltage = <0 3300000 1352000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_ana2_active + &cam_sensor_rear_0_pvdd_active + &cam_sensor_rear_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_ana2_suspend + &cam_sensor_rear_0_pvdd_suspend + &cam_sensor_rear_0_dvdd_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 29 0>, + <&tlmm 25 0>, + <&tlmm 24 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-custom1 = <3>; + gpio-custom2 = <4>; + gpio-vdig = <5>; + gpio-req-tbl-num = <0 1 2 3 4 5>; + gpio-req-tbl-flags = <1 0 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_VANA2_0", + "CAM_PVDD", + "CAM_VDIG"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_1>; + eeprom-src = <&eeprom_rear_1>;//for imx586&s5k3m5 use same eeprom located on master imx586 + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150_s4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1800000 0>; + rgltr-max-voltage = <0 3300000 1800000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active + &cam_sensor_rear_1_dvdd_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend + &cam_sensor_rear_1_dvdd_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1", + "CAM_VDIG_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_s8>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1352000 0>; + rgltr-max-voltage = <0 3300000 1352000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active + &cam_sensor_front_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend + &cam_sensor_front_0_dvdd_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>, + <&pm8150l_gpios 1 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2", + "CAM_VDIG_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; +&tlmm { + cam_sensor_rear_0_mclk_active: cam_sensor_rear_0_mclk_active { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_mclk_suspend: cam_sensor_rear_0_mclk_suspend { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_active: cam_sensor_rear_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_suspend: cam_sensor_rear_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_active: cam_sensor_rear_0_ana_active { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_suspend: cam_sensor_rear_0_ana_suspend { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_active: cam_sensor_rear_0_ana2_active { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_suspend: cam_sensor_rear_0_ana2_suspend { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_pvdd_active: cam_sensor_rear_0_pvdd_active { + /* PVDD */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_pvdd_suspend: cam_sensor_rear_0_pvdd_suspend { + /* PVDD */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_dvdd_active: cam_sensor_rear_0_dvdd_active { + /* VDIG */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_dvdd_suspend: cam_sensor_rear_0_dvdd_suspend { + /* VDIG */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + + cam_sensor_rear_0_vaf_active: cam_sensor_rear_0_vaf_active { + /* AF */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_suspend: cam_sensor_rear_0_vaf_suspend { + /* AF */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ois_active: cam_sensor_rear_0_ois_active { + /* OIS */ + mux { + pins = "gpio87"; + function = "gpio"; + }; + + config { + pins = "gpio87"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ois_suspend: cam_sensor_rear_0_ois_suspend { + /* OIS */ + mux { + pins = "gpio87"; + function = "gpio"; + }; + + config { + pins = "gpio87"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + + cam_sensor_rear_1_mclk_active: cam_sensor_rear_1_mclk_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_suspend: cam_sensor_rear_1_mclk_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_active: cam_sensor_rear_1_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_suspend: cam_sensor_rear_1_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_active: cam_sensor_rear_1_ana_active { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_suspend: cam_sensor_rear_1_ana_suspend { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_active: cam_sensor_rear_1_vaf_active { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_suspend: cam_sensor_rear_1_vaf_suspend { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_active: cam_sensor_front_0_mclk_active { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_suspend: cam_sensor_front_0_mclk_suspend { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_active: cam_sensor_front_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_suspend: cam_sensor_front_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-oem-camera-ov.dtsi b/arch/arm64/boot/dts/qcom/sm8150-oem-camera-ov.dtsi new file mode 100644 index 000000000000..c8f15fd08a07 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-oem-camera-ov.dtsi @@ -0,0 +1,854 @@ +&pm8150_gpios{ + cam_sensor_front_0_dig { + cam_sensor_front_0_dig_active: cam_sensor_front_0_dig_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_dig_suspend: cam_sensor_front_0_dig_suspend{ + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; + +&pm8150l_gpios{ + cam_sensor_tof_pmi_gpio { + cam_sensor_tof_ana_active: cam_sensor_tof_ana_active { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_ana_suspend: cam_sensor_tof_ana_suspend { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_tof_dig_active: cam_sensor_tof_dig_active { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_dig_suspend: cam_sensor_tof_dig_suspend { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_tof_vcc_active: cam_sensor_tof_vcc_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_vcc_suspend: cam_sensor_tof_vcc_suspend { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_tof_lvcc_active: cam_sensor_tof_lvcc_active { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_lvcc_suspend: cam_sensor_tof_lvcc_suspend { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; + + cam_sensor_front_0_ana { + cam_sensor_front_0_ana_active: cam_sensor_front_0_ana_active { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_ana_suspend: cam_sensor_front_0_ana_suspend { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; + +&soc { + actuator_rear_1: qcom,actuator@8 { + cell-index = <8>; + reg = <0x8>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_1_vaf_suspend>; + gpios = <&tlmm 35 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + actuator_rear_0: qcom,actuator@7 { + cell-index = <7>; + reg = <0x7>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_0_vaf_suspend>; + gpios = <&tlmm 29 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_0"; + }; + + eeprom_rear_0: qcom,eeprom@7 { + cell-index = <7>; + reg = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1000000 0>; + rgltr-max-voltage = <0 3300000 1200000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_dig_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_dig_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_DIG_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_1: qcom,eeprom@8 { + cell-index = <8>; + reg = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1000000 0>; + rgltr-max-voltage = <0 3300000 1200000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_mclk_active + &cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active + &cam_sensor_rear_1_dig_active>; + pinctrl-1 = <&cam_sensor_rear_1_mclk_suspend + &cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend + &cam_sensor_rear_1_dig_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>, + <&tlmm 26 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1", + "CAM_DIG_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_front_0: qcom,eeprom@9 { + cell-index = <9>; + reg = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1000000 0>; + rgltr-max-voltage = <0 3300000 1200000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active + &cam_sensor_front_0_dig_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend + &cam_sensor_front_0_dig_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>, + <&pm8150_gpios 1 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2", + "CAM_DIG_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_tof: qcom,eeprom@10 { + cell-index = <10>; + reg = <0xA>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0>; + rgltr-max-voltage = <0 0>; + rgltr-load-current = <0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_tof_mclk_active + &cam_sensor_tof_rest_active>; + pinctrl-1 = <&cam_sensor_tof_mclk_suspend + &cam_sensor_tof_rest_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear_0>; + //ois-src = <&ois_rear>; + //eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_dig_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_dig_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&pm8150l_gpios 4 GPIO_ACTIVE_HIGH>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_DIG_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + //eeprom-src = <&eeprom_front>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active + &cam_sensor_front_0_dig_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend + &cam_sensor_front_0_dig_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 4 GPIO_ACTIVE_HIGH>, + <&pm8150l_gpios 1 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2", + "CAM_DIG_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + //laser start + stmvl53l1: st,stmvl53l1@0 { + compatible = "st,stmvl53l1"; + //reg = <0x29>; + //avdd-supply = <&pm8150l_bob>; + laser_vdd-supply = <&pm8150l_l1>; + //pinctrl-names = "laser_default", "laser_suspend"; + //pinctrl-0 = <&stm_laser_pwren_active>; + //pinctrl-1 = <&stm_laser_pwren_suspend>; + xsdn-gpio = <24>; + pwren-gpio = <26>; + intr-gpio = <131>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + }; +//laser end +}; + +&tlmm { + cam_sensor_rear_0_mclk_active: cam_sensor_rear_0_mclk_active { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_mclk_suspend: cam_sensor_rear_0_mclk_suspend { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_active: cam_sensor_rear_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_suspend: cam_sensor_rear_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_active: cam_sensor_rear_0_ana_active { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_suspend: cam_sensor_rear_0_ana_suspend { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_dig_active: cam_sensor_rear_0_dig_active { + /* DIG */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_dig_suspend: cam_sensor_rear_0_dig_suspend { + /* DIG */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_active: cam_sensor_rear_0_vaf_active { + /* DIG */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_suspend: cam_sensor_rear_0_vaf_suspend { + /* DIG */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_active: cam_sensor_rear_1_mclk_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_suspend: cam_sensor_rear_1_mclk_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_active: cam_sensor_rear_1_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_suspend: cam_sensor_rear_1_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_active: cam_sensor_rear_1_ana_active { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_suspend: cam_sensor_rear_1_ana_suspend { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_active: cam_sensor_rear_1_vaf_active { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_suspend: cam_sensor_rear_1_vaf_suspend { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_dig_active: cam_sensor_rear_1_dig_active { + /* DIG */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_dig_suspend: cam_sensor_rear_1_dig_suspend { + /* DIG */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_active: cam_sensor_front_0_mclk_active { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_suspend: cam_sensor_front_0_mclk_suspend { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_active: cam_sensor_front_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_suspend: cam_sensor_front_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_mclk_active: cam_sensor_tof_mclk_active { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_mclk_suspend: cam_sensor_tof_mclk_suspend { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_rest_active: cam_sensor_tof_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_rest_suspend: cam_sensor_tof_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-oem-camera-t0.dtsi b/arch/arm64/boot/dts/qcom/sm8150-oem-camera-t0.dtsi new file mode 100644 index 000000000000..137c6903ebca --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-oem-camera-t0.dtsi @@ -0,0 +1,1055 @@ +&pm8150_gpios{ + cam_sensor_laser { + cam_sensor_laser_xsdn_active: cam_sensor_laser_xsdn_active { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_laser_xsdn_suspend: cam_sensor_laser_xsdn_suspend{ + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; + +&pm8150b_gpios{ + cam_sensor_laser { + cam_sensor_laser_intr_active: cam_sensor_laser_intr_active { + pins = "gpio10"; + function = "normal"; + power-source = <0>; + //bias-pull-up; + bias-disable; + output-high; + input-enable; + }; + + cam_sensor_laser_intr_suspend: cam_sensor_laser_intr_suspend{ + pins = "gpio10"; + function = "normal"; + power-source = <0>; + //bias-pull-down; + bias-disable; + output-low; + input-enable; + }; + }; +}; + +&pm8150l_gpios{ + cam_sensor_pmi_gpio { + cam_sensor_rear_0_dvdd_active: cam_sensor_rear_0_dvdd_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_0_dvdd_suspend: cam_sensor_rear_0_dvdd_suspend { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_rear_2_ana_active: cam_sensor_rear_2_ana_active { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_2_ana_suspend: cam_sensor_rear_2_ana_suspend { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_rear_2_af_active: cam_sensor_rear_2_af_active { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_2_af_suspend: cam_sensor_rear_2_af_suspend { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; + + cam_sensor_front_0_ana { + cam_sensor_front_0_ana_active: cam_sensor_front_0_ana_active { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_ana_suspend: cam_sensor_front_0_ana_suspend { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; + +&soc { +//laser start + stmvl53l1: st,stmvl53l1@0 { + compatible = "st,stmvl53l1"; + //reg = <0x29>; + //avdd-supply = <&pm8150l_bob>; + laser_vdd-supply = <&pm8150l_l1>; + pinctrl-names = "laser_default", "laser_suspend"; + pinctrl-0 = <&cam_sensor_laser_xsdn_active + &cam_sensor_laser_pwren_active + &cam_sensor_laser_intr_active>; + pinctrl-1 = <&cam_sensor_laser_xsdn_suspend + &cam_sensor_laser_pwren_suspend + &cam_sensor_laser_intr_suspend>; + xsdn-gpio = <&pm8150_gpios 4 GPIO_ACTIVE_HIGH>; + pwren-gpio = <&tlmm 26 0>; + intr-gpio = <&pm8150b_gpios 10 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&spmi_bus>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + }; +//laser end + + led_flash_rear_0: qcom,camera-flash@7 { + cell-index = <7>; + reg = <0x07 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_1: qcom,camera-flash@8 { + cell-index = <8>; + reg = <0x08 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_2: qcom,camera-flash@9 { + cell-index = <9>; + reg = <0x09 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; +}; + +&cam_cci0 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + shared-gpios = <14 13>; + pinctrl-names = "cam_res_mgr_default", "cam_res_mgr_suspend"; + status = "ok"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_1_mclk_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_1_mclk_suspend>; + }; + + actuator_rear_0: qcom,actuator@7 { + cell-index = <7>; + reg = <0x7>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_0_vaf_suspend>; + gpios = <&tlmm 25 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_0"; + }; + + actuator_rear_1: qcom,actuator@8 { + cell-index = <8>; + reg = <0x8>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_1_vaf_suspend>; + gpios = <&tlmm 35 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + actuator_rear_2: qcom,actuator@9 { + cell-index = <9>; + reg = <0x9>; + compatible = "qcom,actuator"; + cci-device = <1>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_af_active>; + pinctrl-1 = <&cam_sensor_rear_2_af_suspend>; + gpios = <&pm8150l_gpios 4 GPIO_ACTIVE_HIGH>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + ois_rear_0: qcom,ois@02{ + cell-index = <2>; + reg = <2>; + compatible = "qcom,ois"; + cam_vio-supply = <&pm8150l_l1>; + cam_vdig-supply = <&pm8009_l6>;//s5k3m5 ois + cam_vaf-supply = <&pm8009_l5>; + regulator-names = "cam_vio", "cam_vdig", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2856000 2800000>; + rgltr-max-voltage = <0 2856000 2800000>; + rgltr-load-current = <0 80000 0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + }; + + ois_rear_1: qcom,ois@3 { + cell-index = <3>; + reg = <3>; + compatible = "qcom,ois"; + cam_vio-supply = <&pm8150l_l1>; + cam_vdig-supply = <&pm8009_l5>;//imx586 ois + cam_vaf-supply = <&pm8009_l6>; + regulator-names = "cam_vio", "cam_vdig", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2800000 2856000>; + rgltr-max-voltage = <0 2800000 2856000>; + rgltr-load-current = <0 80000 0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + }; + + eeprom_rear_0: qcom,eeprom@7 { + cell-index = <7>; + reg = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1104000 0>; + rgltr-max-voltage = <0 3300000 1104000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_1: qcom,eeprom@8 { + cell-index = <8>; + reg = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front_0: qcom,eeprom@9 { + cell-index = <9>; + reg = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_2: qcom,eeprom@10 { + cell-index = <10>; + reg = <0xA>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_mclk_active + &cam_sensor_rear_2_rest_active + &cam_sensor_rear_2_ana_active>; + pinctrl-1 = <&cam_sensor_rear_2_mclk_suspend + &cam_sensor_rear_2_rest_suspend + &cam_sensor_rear_2_ana_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2 >; + gpio-req-tbl-flags = <1 0 0 >; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA_3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_0>; + actuator-src = <&actuator_rear_0>; + ois-src = <&ois_rear_0>; + eeprom-src = <&eeprom_rear_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1104000 0>; + rgltr-max-voltage = <0 3300000 1104000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_ana2_active + &cam_sensor_rear_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_ana2_suspend + &cam_sensor_rear_0_dvdd_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 29 0>, + <&pm8150l_gpios 1 GPIO_ACTIVE_HIGH>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-custom1 = <3>; + gpio-custom2 = <4>; + gpio-req-tbl-num = <0 1 2 3 4>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_VANA2_0", + "CAM_PVDD"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_1>; + led-flash-src = <&led_flash_rear_1>; + eeprom-src = <&eeprom_rear_0>;//for imx586&s5k3m5 use same eeprom located on master imx586 + ois-src = <&ois_rear_1>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x03>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + led-flash-src = <&led_flash_rear_2>; + eeprom-src = <&eeprom_rear_2>; + actuator-src = <&actuator_rear_2>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_mclk_active + &cam_sensor_rear_2_rest_active + &cam_sensor_rear_2_ana_active>; + pinctrl-1 = <&cam_sensor_rear_2_mclk_suspend + &cam_sensor_rear_2_rest_suspend + &cam_sensor_rear_2_ana_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2 >; + gpio-req-tbl-flags = <1 0 0 >; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA_3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; + +&tlmm { + cam_sensor_rear_0_mclk_active: cam_sensor_rear_0_mclk_active { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_mclk_suspend: cam_sensor_rear_0_mclk_suspend { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_active: cam_sensor_rear_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_suspend: cam_sensor_rear_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_active: cam_sensor_rear_0_ana_active { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_suspend: cam_sensor_rear_0_ana_suspend { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_active: cam_sensor_rear_0_ana2_active { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_suspend: cam_sensor_rear_0_ana2_suspend { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_active: cam_sensor_rear_0_vaf_active { + /* AF */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_suspend: cam_sensor_rear_0_vaf_suspend { + /* AF */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_active: cam_sensor_rear_1_mclk_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_suspend: cam_sensor_rear_1_mclk_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_active: cam_sensor_rear_1_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_suspend: cam_sensor_rear_1_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_active: cam_sensor_rear_1_ana_active { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_suspend: cam_sensor_rear_1_ana_suspend { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_active: cam_sensor_rear_1_vaf_active { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_suspend: cam_sensor_rear_1_vaf_suspend { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_active: cam_sensor_front_0_mclk_active { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_suspend: cam_sensor_front_0_mclk_suspend { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_active: cam_sensor_front_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_suspend: cam_sensor_front_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_mclk_active: cam_sensor_rear_2_mclk_active { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_mclk_suspend: cam_sensor_rear_2_mclk_suspend { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_rest_active: cam_sensor_rear_2_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_rest_suspend: cam_sensor_rear_2_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_pwren_active: cam_sensor_laser_pwren_active { + /* RESET, STANDBY */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_pwren_suspend: cam_sensor_laser_pwren_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-oem-camera-v2.dtsi b/arch/arm64/boot/dts/qcom/sm8150-oem-camera-v2.dtsi new file mode 100644 index 000000000000..e80107dee1c1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-oem-camera-v2.dtsi @@ -0,0 +1,1035 @@ +&pm8150l_gpios{ + cam_sensor_pmi_gpio { + cam_sensor_rear_0_dvdd_active: cam_sensor_rear_0_dvdd_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_0_dvdd_suspend: cam_sensor_rear_0_dvdd_suspend { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_rear_2_ana_active: cam_sensor_rear_2_ana_active { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_2_ana_suspend: cam_sensor_rear_2_ana_suspend { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_rear_2_af_active: cam_sensor_rear_2_af_active { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_2_af_suspend: cam_sensor_rear_2_af_suspend { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; + + cam_sensor_front_0_ana { + cam_sensor_front_0_ana_active: cam_sensor_front_0_ana_active { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_ana_suspend: cam_sensor_front_0_ana_suspend { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; + +&soc { +//laser start + stmvl53l1: st,stmvl53l1@0 { + compatible = "st,stmvl53l1"; + //reg = <0x29>; + //avdd-supply = <&pm8150l_bob>; + laser_vdd-supply = <&pm8150l_l1>; + pinctrl-names = "laser_default", "laser_suspend"; + pinctrl-0 = <&cam_sensor_laser_xsdn_active + &cam_sensor_laser_pwren_active + &cam_sensor_laser_intr_active>; + pinctrl-1 = <&cam_sensor_laser_xsdn_suspend + &cam_sensor_laser_pwren_suspend + &cam_sensor_laser_intr_suspend>; + xsdn-gpio = <&tlmm 24 0>; + pwren-gpio = <&tlmm 26 0>; + intr-gpio = <&tlmm 131 0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + }; +//laser end +}; + +&cam_cci0 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + shared-gpios = <14 13>; + pinctrl-names = "cam_res_mgr_default", "cam_res_mgr_suspend"; + status = "ok"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_1_mclk_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_1_mclk_suspend>; + }; + + actuator_rear_0: qcom,actuator@7 { + cell-index = <7>; + reg = <0x7>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_0_vaf_suspend>; + gpios = <&tlmm 25 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_0"; + }; + + actuator_rear_1: qcom,actuator@8 { + cell-index = <8>; + reg = <0x8>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_1_vaf_suspend>; + gpios = <&tlmm 35 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + actuator_rear_2: qcom,actuator@9 { + cell-index = <9>; + reg = <0x9>; + compatible = "qcom,actuator"; + cci-device = <1>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_af_active>; + pinctrl-1 = <&cam_sensor_rear_2_af_suspend>; + gpios = <&pm8150l_gpios 4 GPIO_ACTIVE_HIGH>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + ois_rear_0: qcom,ois@2 { + cell-index = <2>; + reg = <2>; + compatible = "qcom,ois"; + cam_vio-supply = <&pm8150l_l1>; + cam_vdig-supply = <&pm8009_l6>;//s5k3m5 ois + cam_vaf-supply = <&pm8009_l5>; + regulator-names = "cam_vio", "cam_vdig", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2856000 2800000>; + rgltr-max-voltage = <0 2856000 2800000>; + rgltr-load-current = <0 80000 0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + }; + + ois_rear_1: qcom,ois@3 { + cell-index = <3>; + reg = <3>; + compatible = "qcom,ois"; + cam_vio-supply = <&pm8150l_l1>; + cam_vdig-supply = <&pm8009_l5>;//imx586 ois + cam_vaf-supply = <&pm8009_l6>; + regulator-names = "cam_vio", "cam_vdig", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2800000 2856000>; + rgltr-max-voltage = <0 2800000 2856000>; + rgltr-load-current = <0 80000 0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + }; + + eeprom_rear_0: qcom,eeprom@7 { + cell-index = <7>; + reg = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1104000 0>; + rgltr-max-voltage = <0 3300000 1104000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_1: qcom,eeprom@8 { + cell-index = <8>; + reg = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1050000 0>; + rgltr-max-voltage = <0 3300000 1050000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front_0: qcom,eeprom@9 { + cell-index = <9>; + reg = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_2: qcom,eeprom@10 { + cell-index = <10>; + reg = <0xA>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1050000 0>; + rgltr-max-voltage = <0 3300000 1050000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_mclk_active + &cam_sensor_rear_2_rest_active + &cam_sensor_rear_2_ana_active>; + pinctrl-1 = <&cam_sensor_rear_2_mclk_suspend + &cam_sensor_rear_2_rest_suspend + &cam_sensor_rear_2_ana_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2 >; + gpio-req-tbl-flags = <1 0 0 >; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA_3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear_0>; + ois-src = <&ois_rear_0>; + eeprom-src = <&eeprom_rear_1>;//for imx586&s5k3m5 use same eeprom located on slave s5k3m5 + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1104000 0>; + rgltr-max-voltage = <0 3300000 1104000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_ana2_active + &cam_sensor_rear_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_ana2_suspend + &cam_sensor_rear_0_dvdd_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 29 0>, + <&pm8150l_gpios 1 GPIO_ACTIVE_HIGH>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-custom1 = <3>; + gpio-custom2 = <4>; + gpio-req-tbl-num = <0 1 2 3 4>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_VANA2_0", + "CAM_PVDD"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_1>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_1>; + ois-src = <&ois_rear_1>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1050000 0>; + rgltr-max-voltage = <0 3300000 1050000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x03>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_rear_2>; + actuator-src = <&actuator_rear_2>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1050000 0>; + rgltr-max-voltage = <0 3300000 1050000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_mclk_active + &cam_sensor_rear_2_rest_active + &cam_sensor_rear_2_ana_active>; + pinctrl-1 = <&cam_sensor_rear_2_mclk_suspend + &cam_sensor_rear_2_rest_suspend + &cam_sensor_rear_2_ana_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2 >; + gpio-req-tbl-flags = <1 0 0 >; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA_3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; + +&tlmm { + cam_sensor_rear_0_mclk_active: cam_sensor_rear_0_mclk_active { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_mclk_suspend: cam_sensor_rear_0_mclk_suspend { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_active: cam_sensor_rear_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_suspend: cam_sensor_rear_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_active: cam_sensor_rear_0_ana_active { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_suspend: cam_sensor_rear_0_ana_suspend { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_active: cam_sensor_rear_0_ana2_active { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_suspend: cam_sensor_rear_0_ana2_suspend { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_active: cam_sensor_rear_0_vaf_active { + /* AF */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_suspend: cam_sensor_rear_0_vaf_suspend { + /* AF */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_active: cam_sensor_rear_1_mclk_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_suspend: cam_sensor_rear_1_mclk_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_active: cam_sensor_rear_1_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_suspend: cam_sensor_rear_1_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_active: cam_sensor_rear_1_ana_active { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_suspend: cam_sensor_rear_1_ana_suspend { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_active: cam_sensor_rear_1_vaf_active { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_suspend: cam_sensor_rear_1_vaf_suspend { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_active: cam_sensor_front_0_mclk_active { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_suspend: cam_sensor_front_0_mclk_suspend { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_active: cam_sensor_front_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_suspend: cam_sensor_front_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_mclk_active: cam_sensor_rear_2_mclk_active { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_mclk_suspend: cam_sensor_rear_2_mclk_suspend { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_rest_active: cam_sensor_rear_2_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_rest_suspend: cam_sensor_rear_2_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_xsdn_active: cam_sensor_laser_xsdn_active { + /* RESET, STANDBY */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_xsdn_suspend: cam_sensor_laser_xsdn_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_pwren_active: cam_sensor_laser_pwren_active { + /* RESET, STANDBY */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_pwren_suspend: cam_sensor_laser_pwren_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_intr_active: cam_sensor_laser_intr_active { + /* RESET, STANDBY */ + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_intr_suspend: cam_sensor_laser_intr_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-oem-camera.dtsi b/arch/arm64/boot/dts/qcom/sm8150-oem-camera.dtsi new file mode 100644 index 000000000000..08f12def4458 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-oem-camera.dtsi @@ -0,0 +1,968 @@ +&pm8150_gpios{ + cam_sensor_front_0_dig { + cam_sensor_front_0_dig_active: cam_sensor_front_0_dig_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_dig_suspend: cam_sensor_front_0_dig_suspend{ + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; + +&pm8150l_gpios{ + cam_sensor_tof_pmi_gpio { + cam_sensor_tof_ana_active: cam_sensor_tof_ana_active { + pins = "gpio3"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_ana_suspend: cam_sensor_tof_ana_suspend { + pins = "gpio3"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_tof_dig_active: cam_sensor_tof_dig_active { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_dig_suspend: cam_sensor_tof_dig_suspend { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_tof_vcc_active: cam_sensor_tof_vcc_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_vcc_suspend: cam_sensor_tof_vcc_suspend { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_tof_lvcc_active: cam_sensor_tof_lvcc_active { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_tof_lvcc_suspend: cam_sensor_tof_lvcc_suspend { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; + + cam_sensor_front_0_ana { + cam_sensor_front_0_ana_active: cam_sensor_front_0_ana_active { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_ana_suspend: cam_sensor_front_0_ana_suspend { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; +&soc { + actuator_rear_0: qcom,actuator@7 { + cell-index = <7>; + reg = <0x7>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_0_vaf_suspend>; + gpios = <&tlmm 24 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_0"; + }; + + actuator_rear_1: qcom,actuator@8 { + cell-index = <8>; + reg = <0x8>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_1_vaf_suspend>; + gpios = <&tlmm 35 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + eeprom_rear_0: qcom,eeprom@7 { + cell-index = <7>; + reg = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_dig_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_dig_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 29 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_DIG_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_1: qcom,eeprom@8 { + cell-index = <8>; + reg = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_mclk_active + &cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active + &cam_sensor_rear_1_dig_active>; + pinctrl-1 = <&cam_sensor_rear_1_mclk_suspend + &cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend + &cam_sensor_rear_1_dig_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>, + <&tlmm 26 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1", + "CAM_DIG_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_front_0: qcom,eeprom@9 { + cell-index = <9>; + reg = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active + &cam_sensor_front_0_dig_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend + &cam_sensor_front_0_dig_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>, + <&pm8150_gpios 1 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2", + "CAM_DIG_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_tof: qcom,eeprom@10 { + cell-index = <10>; + reg = <0xA>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0>; + rgltr-max-voltage = <0 0>; + rgltr-load-current = <0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_tof_mclk_active + &cam_sensor_tof_rest_active>; + pinctrl-1 = <&cam_sensor_tof_mclk_suspend + &cam_sensor_tof_rest_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear_0>; + //ois-src = <&ois_rear>; + eeprom-src = <&eeprom_rear_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_dig_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_dig_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 29 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_DIG_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_1>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_1>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_mclk_active + &cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active + &cam_sensor_rear_1_dig_active>; + pinctrl-1 = <&cam_sensor_rear_1_mclk_suspend + &cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend + &cam_sensor_rear_1_dig_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>, + <&tlmm 26 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1", + "CAM_DIG_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active + &cam_sensor_front_0_dig_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend + &cam_sensor_front_0_dig_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>, + <&pm8150_gpios 1 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2", + "CAM_DIG_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x03>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_rear_tof>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8150l_bob>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 3300000 0>; + rgltr-max-voltage = <0 3300000 3300000 0>; + rgltr-load-current = <0 80000 80000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_tof_mclk_active + &cam_sensor_tof_rest_active + &cam_sensor_tof_ana_active + &cam_sensor_tof_dig_active + &cam_sensor_tof_vcc_active + &cam_sensor_tof_lvcc_active>; + pinctrl-1 = <&cam_sensor_tof_mclk_suspend + &cam_sensor_tof_rest_suspend + &cam_sensor_tof_ana_suspend + &cam_sensor_tof_dig_suspend + &cam_sensor_tof_vcc_suspend + &cam_sensor_tof_lvcc_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&pm8150l_gpios 3 GPIO_ACTIVE_HIGH>, + <&pm8150l_gpios 4 GPIO_ACTIVE_HIGH>, + <&pm8150l_gpios 1 GPIO_ACTIVE_HIGH>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vdig = <3>; + gpio-custom1 = <4>; + gpio-custom2 = <5>; + gpio-req-tbl-num = <0 1 2 3 4 5>; + gpio-req-tbl-flags = <1 0 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA_3", + "CAM_DIG_3", + "CAM_VCC_3", + "CAM_LVCC_3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +//laser start + stmvl53l1: st,stmvl53l1@0 { + compatible = "st,stmvl53l1"; + //reg = <0x29>; + //avdd-supply = <&pm8150l_bob>; + laser_vdd-supply = <&pm8150l_l1>; + //pinctrl-names = "laser_default", "laser_suspend"; + //pinctrl-0 = <&stm_laser_pwren_active>; + //pinctrl-1 = <&stm_laser_pwren_suspend>; + xsdn-gpio = <30>; + pwren-gpio = <11>; + intr-gpio = <131>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + }; +//laser end +}; + +&tlmm { + cam_sensor_rear_0_mclk_active: cam_sensor_rear_0_mclk_active { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_mclk_suspend: cam_sensor_rear_0_mclk_suspend { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_active: cam_sensor_rear_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_suspend: cam_sensor_rear_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_active: cam_sensor_rear_0_ana_active { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_suspend: cam_sensor_rear_0_ana_suspend { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_dig_active: cam_sensor_rear_0_dig_active { + /* DIG */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_dig_suspend: cam_sensor_rear_0_dig_suspend { + /* DIG */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_active: cam_sensor_rear_0_vaf_active { + /* DIG */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_suspend: cam_sensor_rear_0_vaf_suspend { + /* DIG */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_active: cam_sensor_rear_1_mclk_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_suspend: cam_sensor_rear_1_mclk_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_active: cam_sensor_rear_1_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_suspend: cam_sensor_rear_1_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_active: cam_sensor_rear_1_ana_active { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_suspend: cam_sensor_rear_1_ana_suspend { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_active: cam_sensor_rear_1_vaf_active { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_suspend: cam_sensor_rear_1_vaf_suspend { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_dig_active: cam_sensor_rear_1_dig_active { + /* DIG */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_dig_suspend: cam_sensor_rear_1_dig_suspend { + /* DIG */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_active: cam_sensor_front_0_mclk_active { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_suspend: cam_sensor_front_0_mclk_suspend { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_active: cam_sensor_front_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_suspend: cam_sensor_front_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_mclk_active: cam_sensor_tof_mclk_active { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_mclk_suspend: cam_sensor_tof_mclk_suspend { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_rest_active: cam_sensor_tof_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_tof_rest_suspend: cam_sensor_tof_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-oem.dtsi b/arch/arm64/boot/dts/qcom/sm8150-oem.dtsi new file mode 100644 index 000000000000..57eba48c3557 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-oem.dtsi @@ -0,0 +1,1340 @@ +/* Display */ +&soc { + dsi_samsung_oneplus_dsc_cmd_display: qcom,dsi-display@23 { + label = "dsi_samsung_oneplus_dsc_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-panel = <&dsi_samsung_oneplus_dsc_cmd>; + }; + + dsi_samsung_s6e3fc2x01_cmd_display: qcom,dsi-display@24 { + label = "dsi_samsung_s6e3fc2x01_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-panel = <&dsi_samsung_s6e3fc2x01_cmd>; + }; + + dsi_samsung_sofef00_m_video_display: qcom,dsi-display@27 { + label = "dsi_samsung_sofef00_m_video_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-panel = <&dsi_samsung_sofef00_m_video>; + }; + + + tri_state_key:tri_state_key { + compatible = "oneplus, tri-state-key"; + status = "okay"; + interrupt-parent = <&tlmm>; + tristate,gpio_key1 = <&tlmm 27 0x00>; + tristate,gpio_key2 = <&tlmm 134 0x00>; + tristate,gpio_key3 = <&tlmm 125 0x00>; + pinctrl-names = + "pmx_tri_state_key_active", + "pmx_tri_state_key_suspend"; + pinctrl-0 = <&tri_state_key_active>; + pinctrl-1 = <&tri_state_key_suspend>; + }; + + fingerprint_detect:fingerprint_detect { + compatible = "oneplus,fpdetect"; + fp-gpio-id0 = <&tlmm 90 0>; + fp-gpio-id1 = <&pm8150_gpios 3 0>; + pinctrl-names = "fp_id_init"; + pinctrl-0 = <&fp_id0_init &fp_id1_init>; + }; + + goodix_fp { + compatible = "goodix,fingerprint"; + interrupt-parent = <&tlmm>; + //vdd-3v2-supply = <&pm8998_l22>; + //vdd-voltage = <3200000 3200000>; + //vdd-current = <50000>; + fp-gpio-irq = <&tlmm 118 0x00>; + fp-gpio-reset = <&tlmm 131 0x00>; + fp-gpio-enable = <&tlmm 101 0x00>; + pinctrl-names = "fp_en_init", "fp_dis_init"; + pinctrl-0 = <&fp_vdd_init &fp_irq_init>; + pinctrl-1 = <&fp_vdd_dis_init>; + status = "okay"; + }; +}; + +&qcomqbt1000{ + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; + qfp-int2 = <&tlmm 131 0x00>; + qcom,finger-detect-gpio = <&tlmm 101 0>; +}; + +&sde_dsi { + pinctrl-names = "panel_active", "panel_suspend","default"; + pinctrl-0 = <&sde_dsi_active &sde_te_active &display_panel_avdd_eldo_default>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend &display_panel_avdd_eldo_off>; + /delete-property/ lab-supply; + /delete-property/ ibb-supply; + /delete-property/ vdd-supply; + qcom,dsi-display-list = + <&dsi_samsung_oneplus_dsc_cmd_display + &dsi_samsung_s6e3fc2x01_cmd_display + &dsi_samsung_sofef00_m_video_display>; +}; + +&tlmm{ + display_panel_avdd_eldo_off: display_panel_avdd_eldo_off { + mux { + pins = "gpio130"; + function = "gpio"; + }; + config { + pins = "gpio130"; + drive-strength = <8>; + bias-disable = <0>; + output-low; + }; + }; + + tri_state_key_active: tri_state_key_active { + mux { + pins = "gpio125", "gpio134", "gpio27"; + function = "gpio"; + }; + config { + pins = "gpio125", "gpio134", "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; + + tri_state_key_suspend: tri_state_key_suspend { + mux { + pins = "gpio125", "gpio134", "gpio27"; + function = "gpio"; + }; + config { + pins = "gpio125", "gpio134", "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; + +}; + +//wangdongdong@AudioDrv, add for 4M memory increase of adsp begain +&pil_adsp_mem { + reg = <0x0 0x8be00000 0x0 0x1e00000>; +}; + +&pil_modem_mem { + reg = <0x0 0x8dc00000 0x0 0x9600000>; +}; + +&pil_video_mem { + reg = <0x0 0x97200000 0x0 0x500000>; +}; + +&pil_slpi_mem { + reg = <0x0 0x97700000 0x0 0x1400000>; +}; + +&pil_ipa_fw_mem { + reg = <0x0 0x98b00000 0x0 0x10000>; +}; + +&pil_ipa_gsi_mem { + reg = <0x0 0x98b10000 0x0 0x5000>; +}; + +&pil_gpu_mem { + reg = <0x0 0x98b15000 0x0 0x2000>; +}; + +&pil_spss_mem { + reg = <0x0 0x98c00000 0x0 0x100000>; +}; + +&pil_cdsp_mem { + reg = <0x0 0x98d00000 0x0 0x1400000>; +}; +//wangdongdong@AudioDrv, add for 4M memory increase of adsp end + +//dujie@MM.Audio add begain +/* #if OP_FEATURE_MM_RECORDING_SCREEN == 1*/ +/* zhanglixia@MM.Audio, 2019/07/13, add for screen record*/ + +&snd_934x { + qcom,afe-rxtx-lb = <1>; + asoc-cpu = <&dai_hdmi>, <&dai_dp>, + <&dai_mi2s0>, <&dai_mi2s1>, + <&dai_mi2s2>, <&dai_mi2s3>, + <&dai_mi2s4>, <&dai_pri_auxpcm>, + <&dai_sec_auxpcm>, <&dai_tert_auxpcm>, + <&dai_quat_auxpcm>, <&dai_quin_auxpcm>, + <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, + <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, + <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, <&sb_5_rx>, <&sb_6_rx>, + <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>, + <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>, + <&dai_quat_tdm_rx_1>, + <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>, + <&afe_loopback_tx>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", + "msm-dai-q6-mi2s.4", "msm-dai-q6-auxpcm.1", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3", + "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5", + "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", + "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", + "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", + "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", + "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", + "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", + "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", + "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897", + "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913", + "msm-dai-q6-tdm.36914", + "msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36929", + "msm-dai-q6-dev.24577"; +}; +/* #endif*/ +&snd_9360 { + status = "disabled"; +}; +&wcd9360_cdc { + status = "disabled"; +}; +&clock_audio { + status = "disabled"; +}; + +&snd_934x { + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "hifi amp", "LINEOUT1", + "hifi amp", "LINEOUT2", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC3", "MIC BIAS4", + "MIC BIAS4", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS1", + "MIC BIAS1", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS1", + "MIC BIAS1", "Handset Mic", + "DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "DMIC4", "MIC BIAS4", + "MIC BIAS4", "Digital Mic4", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT"; + + qcom,wsa-max-devs = <0>; + qcom,msm-mbhc-usbc-audio-supported = <1>; + qcom,msm-mbhc-hs-mic-max-threshold-mv = <2550>; + pinctrl-names = "quat_mi2s_enable","quat_mi2s_disable", + "quat_tdm_enable","quat_tdm_disable"; + pinctrl-0 = <&quat_mi2s_active + &quat_mi2s_sd0_active &quat_mi2s_sd1_active>; + pinctrl-1 = <&quat_mi2s_sleep + &quat_mi2s_sd0_sleep &quat_mi2s_sd1_sleep>; + pinctrl-2 = <&quat_tdm_active + &quat_tdm_din_active &quat_tdm_dout_active>; + pinctrl-3 = <&quat_tdm_sleep + &quat_tdm_din_sleep &quat_tdm_dout_sleep>; + + // yewenliang@MM.Audio, 2019/06/07, fix cap noise issues in handset mode + vreg_ldo-supply = <&pm8150l_l10>; + vreg_bob-supply = <&pm8150l_bob>; +}; + +&wcd934x_cdc { + qcom,cdc-micbias1-mv = <2700>; + qcom,cdc-micbias2-mv = <2700>; + qcom,cdc-micbias4-mv = <2700>; +}; + +&wsa881x_70211{ + status = "disabled"; +}; + +&wsa881x_70212{ + status = "disabled"; +}; + +&wsa881x_70213{ + status = "disabled"; +}; + +&wsa881x_70214{ + status = "disabled"; +}; + +&qupv3_se4_i2c { + tfa98xx_right: tfa98xx_right@34 { + compatible = "nxp,tfa98xx"; + reg = <0x34>; + reset-gpio = <&tlmm 37 0>; + status = "ok"; + }; + + tfa98xx_left: tfa98xx_left@35 { + compatible = "nxp,tfa98xx"; + reg = <0x35>; + reset-gpio = <&tlmm 100 0>; + status = "ok"; + }; +}; + +&dai_mi2s3 { + qcom,msm-mi2s-rx-lines = <2>; + qcom,msm-mi2s-tx-lines = <1>; +}; + +//Because pcie0 wakeup-gpio is same pa-gpio, so disabled it +&pcie0 { + status = "disabled"; +}; +//dujie@MM.Audio add end + +&sde_dsi_active { + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + drive-strength = <8>; + bias-disable = <0>; + }; +}; +&sde_dsi_suspend { + mux { + pins = "gpio78"; + function = "gpio"; + }; + + config { + pins = "gpio78"; + drive-strength = <2>; + bias-pull-down; + }; +}; + +/*for aw haptic start*/ +&qupv3_se7_i2c { + status = "ok"; + aw8697_haptic:aw8697_haptic@5A { + compatible = "awinic,aw8697_haptic"; + reg = <0x5A>; + reset-gpio = <&tlmm 116 0x00>; + irq-gpio = <&tlmm 24 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <&aw_irq &aw_reset>; + status = "okay"; + }; +}; +/*for aw haptic end*/ + +/* Touch */ +&qupv3_se17_i2c { + status = "ok"; + sec-s6sy761@48 { + compatible = "sec-s6sy761"; + reg = <0x48>; + project-name = "18821"; + chip-name = "SY761"; + module_id = <7>; + reset-gpio = <&tlmm 54 0x00>; + irq-gpio = <&tlmm 122 0x2008>; + vdd_2v8-supply = <&pm8150_l17>; //set 3.3 by ldo + vdd_2v8_volt = <3008000>; + //enable1v8_gpio = <&tlmm 119 0x00>; //set 1.8v by gpio + touchpanel,display-coords = <1439 3119>; + touchpanel,panel-coords = <1439 3119>; + touchpanel,tx-rx-num = <17 37>; + //edge_limit_support = <1>; + //spurious_fingerprint_support = <1>; + //charger_pump_support = <1>; + charge_detect_support = <1>; + black_gesture_support = <1>; + //black_gesture_test_support = <1>; + game_switch_support = <1>; + face_detect_support = <1>; + lcd_refresh_rate_switch = <1>; + touch_hold_support = <1>; + //lcd_trigger_fp_check = <1>; + pinctrl-names = "pin_set_high", "pin_set_low"; + pinctrl-0 = <&tp_1v8_active &tp_irq_active &tp_rst_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_suspend>; + }; +}; +&qupv3_se17_i2c { + status = "ok"; + synaptics-s3706@20 { + compatible = "synaptics-s3706"; + reg = <0x20>; + //project-name = "18857"; + chip-name = "S3706"; + //reset-gpio = <&tlmm 54 0x00>; + irq-gpio = <&tlmm 122 0x2008>; + vdd_2v8-supply = <&pm8150_l17>; //set 3.3 by ldo + vdd_2v8_volt = <3008000>; + //enable1v8_gpio = <&tlmm 59 0x00>; //set 1.8v by gpio + //touchpanel,display-coords = <1080 2340>; + //touchpanel,panel-coords = <1080 2340>; + //touchpanel,tx-rx-num = <16 33>; + black_gesture_support = <1>; + face_detect_support = <1>; + touch_hold_support = <1>; + charge_detect_support = <1>; + module_id = <7>; + pinctrl-names = "pin_set_high", "pin_set_low"; + pinctrl-0 = <&tp_irq_active &tp_rst_active &tp_1v8_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_suspend>; + }; +}; + +/* Add for NXP NFCC */ +&qupv3_se9_i2c { + nq@28 { + status = "disabled"; + }; + + pn5xx@28 { + compatible = "nxp,pn544"; + reg = <0x28>; + nxp,pn544-irq = <&tlmm 47 0x00>; + nxp,pn544-ven = <&tlmm 41 0x00>; + nxp,pn544-fw-dwnld = <&tlmm 48 0x00>; + nxp,pn544-clk-gpio = <&tlmm 113 0x00>; + nxp,pn544-ese-pwr = <&tlmm 49 0x00>; + nfc_voltage_s4-supply = <&pm8150_s4>; + interrupt-parent = <&tlmm>; + qcom,clk-src = "BBCLK3"; + interrupts = <47 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + +/* Add for NXP eSE */ +&qupv3_se0_spi { + status = "ok"; + + ese@0 { + compatible = "nxp,p61"; + reg = <0>; + spi-max-frequency = <8000000>; + nxp,nfcc = "4-0028"; + }; +}; + +&tlmm { + +aw_irq: aw_irq { + mux { + pins = "gpio116"; + function = "gpio"; + }; + + config { + pins = "gpio116"; + drive-strength = <2>; + }; + }; + +aw_reset: aw_reset { + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; + bias-disable; + }; + }; + +tp_irq_active: tp_irq_active { + mux { + pins = "gpio122"; + function = "gpio"; + }; + config { + pins = "gpio122"; + drive-strength = <8>; + bias-disable; + input-enable; + }; + }; + tp_rst_active: tp_rst_active { + mux { + pins = "gpio54"; + function = "gpio"; + }; + config { + pins = "gpio54"; + drive-strength = <8>; + bias-disable; + }; + }; + tp_1v8_active: tp_1v8_active { + mux { + pins = "gpio119"; + function = "gpio"; + }; + config { + pins = "gpio119"; + drive-strength = <8>; + bias-pull-up; + }; + }; + tp_rst_suspend: tp_rst_suspend { + mux { + pins = "gpio54"; + function = "gpio"; + }; + config { + pins = "gpio54"; + drive-strength = <8>; + bias-pull-down; + }; + }; + tp_1v8_suspend: tp_1v8_suspend { + mux { + pins = "gpio119"; + function = "gpio"; + }; + config { + pins = "gpio119"; + drive-strength = <8>; + bias-pull-down; + }; + }; + + fp_irq_init: fp_irq_init { + mux { + pins = "gpio118"; + function = "gpio"; + }; + + config { + pins = "gpio118"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + }; + + fp_reset_init: fp_reset_init { + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + fp_vdd_init: fp_vdd_init { + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + drive-strength = <8>; + bias-pull-up; + output-high; + }; + }; + + fp_vdd_dis_init: fp_vdd_dis_init { + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + drive-strength = <8>; + bias-pull-down; + output-low; + }; + }; + + fp_id0_init: fp_id0_init { + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; + bias-disable; /* No Pull */ + input-enable; + }; + }; +}; + +&vendor { + infrared_pl: infrared_pl { + compatible = "oneplus-infrared"; + vdd-supply = <&pm8150l_l9>; + }; +}; + + +//quentin.lin add 2018/11/07 +&vendor { + motor_pl: motor_pl { + compatible = "oneplus-motor"; + interrupt-parent = <&tlmm>; + interrupts = <163 0x2>; + motor,irq-gpio = <&tlmm 163 0x2008>; + pinctrl-names = "free_fall_input"; + pinctrl-0 = <&free_fall_input>; + structure,id = <0>; + }; +}; + + +// quentin.lin@oneplus.com 2018/11/26 edit for free fall +&tlmm { + free_fall_input: free_fall_input { + mux { + pins = "gpio163"; + function = "gpio"; + }; + config { + pins = "gpio163"; + drive-strength = <2>; + input-enable; + bias-disable; //No Pull + }; + }; + +}; + + +&qupv3_se1_i2c { + status = "ok"; + magnachip@0C { + compatible = "magnachip,mxm1120,up"; + reg = <0x0C>; + vdd-supply = <&pm8150l_l7>; + vio-supply = <&pm8150l_l8>; + magnachip,init-interval = <200>; + interrupt-parent = <&tlmm>; + interrupts = <120 0x2>; + dhall,irq-gpio = <&tlmm 120 0x2008>; + mxm,id = <1>; + }; + magnachip@0D { + compatible = "magnachip,mxm1120,down"; + reg = <0x0D>; + vdd-supply = <&pm8150l_l7>; + vio-supply = <&pm8150l_l8>; + magnachip,init-interval = <200>; + interrupt-parent = <&tlmm>; + interrupts = <121 0x2>; + dhall,irq-gpio = <&tlmm 121 0x2008>; + mxm,id = <2>; + }; +}; + + +/* @bsp, 2019/04/17 Battery & Charging porting STRAT */ +&qupv3_se8_i2c { + qcom,clk-freq-out = <100000>; + status = "ok"; + bq27541_battery:bq27541-battery@55 { + status = "ok"; + compatible = "ti,bq27541-battery"; + reg = <0x55>; + qcom,modify-soc-smooth; + }; + + oneplus_fastchg@26{ + status = "ok"; + compatible = "microchip,oneplus_fastchg"; + reg = <0x26>; + microchip,mcu-en-gpio = <&tlmm 10 0x00>; + microchip,usb-sw-1-gpio = <&tlmm 94 0x00>; + microchip,usb-sw-2-gpio = <&tlmm 59 0x00>; + microchip,ap-clk = <&tlmm 92 0x00>; + microchip,ap-data = <&tlmm 93 0x00>; + + pinctrl-names = "mux_fastchg_active", + "mux_fastchg_suspend", + "mcu_data_active", + "mcu_data_suspend"; + pinctrl-0 = <&fastchg_active + &usb_sw_active + &ap_clk_active>; + pinctrl-1 = <&usb_sw_suspend + &fastchg_suspend + &ap_clk_suspend>; + pinctrl-2 =<&ap_data_active>; + pinctrl-3 =<&ap_data_suspend>; + op,fw-erase-count = <384>; + op,fw-addr-low = <0x88>; + op,fw-addr-high = <0>; + }; +}; + +&pm8150b_gpios { + gpio1_adc { + gpio1_adc_default: gpio1_adc_default { + pins = "gpio1"; /* GPIO 1 */ + function = "normal"; /* normal */ + bias-pull-up; + bias-high-impedance; /* DISABLE GPIO1 for ADC*/ + }; + }; + + gpio12_adc { + gpio12_adc_default: gpio12_adc_default { + pins = "gpio12"; /* GPIO 12 */ + function = "normal"; /* normal */ + bias-pull-up; + bias-high-impedance; /* DISABLE GPIO12 for ADC*/ + }; + }; +}; + +&pm8150b_vadc { + gpio12_v { + reg = ; + label = "gpio12_v"; + qcom,pre-scaling = <1 1>; + }; + gpio1_v { + reg = ;/* 0x30*/ + label = "gpio1_v"; + qcom,ratiometric; + qcom,hw-settle-time = <800>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150b_charger { + qcom,dc-icl-ua = <1200000>; + qcom,fcc-max-ua = <500000>; + qcom,usb-icl-ua = <1800000>; + qcom,fv-max-uv = <4365000>; + /* ibatmax setting for different temp regions */ + ibatmax-little-cold-ma = <350>; + ibatmax-cool-ma = <2000>; + ibatmax-little-cool-ma = <2100>; + ibatmax-pre-normal-ma = <2100>; + ibatmax-normal-ma = <3000>; + ibatmax-warm-ma = <1100>; + ibatmax-little-cool-thr-ma = <1900>; + ibatmax-cool-thr-ma = <1100>; + /* vbatmax setting for different temp regions */ + vbatmax-little-cold-mv = <3975>; + vbatmax-cool-mv = <4390>; + vbatmax-little-cool-mv = <4390>; + vbatmax-pre-normal-mv = <4390>; + vbatmax-normal-mv = <4390>; + vbatmax-warm-mv = <4130>; + little-cool-vbat-thr-mv = <4180>; + cool-vbat-thr-mv = <4180>; + /* vbatdet setting for different temp regions */ + vbatdet-little-cold-mv = <3700>; + vbatdet-cool-mv = <4150>; + vbatdet-little-cool-mv = <4270>; + vbatdet-pre-normal-mv = <4270>; + vbatdet-normal-mv = <4270>; + vbatdet-warm-mv = <3980>; + /* temp region settings */ + cold-bat-decidegc = <20>; + little-cold-bat-decidegc = <0>; + cool-bat-decidegc = <50>; + little-cool-bat-decidegc = <120>; + pre-normal-bat-decidegc = <160>; + warm-bat-decidegc = <450>; + hot-bat-decidegc = <500>; + qcom,otg-cl-ua = <1500000>; + op,sw-iterm-ma = <310>; + op,sw-check-full-enable; + + /*otg low battery current limit*/ + op,otg-icl-ctrl-enable; + otg-low-battery-thr = <15>; + otg-low-bat-icl-thr = <1000000>; + otg-normal-bat-icl-thr = <1500000>; + //disable-pd; + qcom,lpd-disable; + /*add to disable HVDCP*/ + qcom,hvdcp-disable; + /*usb connector hw auto detection*/ + op,usb-check = <&tlmm 91 0x00>; + /* other settings */ + qcom,cutoff-voltage-with-charger = <3250>; + qcom,msm-bus,name = "dash_clk_vote"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <1 731 0 300000000>, + <1 731 0 0>; + /*ffc temp region*/ + ffc-pre-normal-decidegc = <160>; + ffc-normal-decidegc = <350>; + ffc-warm-decidegc = <400>; + ffc-normal-fcc-ma = <650>; + ffc-warm-fcc-ma = <750>; + ffc-normal-cutoff-ma = <550>; + ffc-warm-cutoff-ma = <650>; + ffc-full-vbat-mv = <4430>; + + /* for external ship mode suppot */ + pinctrl-names = "op_ship_mode_default","op_usb_temp_adc_default"; + pinctrl-0 = <&ship_mode_default>; + pinctrl-1= <&gpio1_adc_default>; + + op,stm-ctrl-gpio = <&tlmm 21 0x00>; + /* for usb connector temp protect */ + op,low-voltage-charger; + io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>, + <&pm8150b_vadc ADC_USB_IN_V_16>, + <&pm8150b_vadc ADC_USB_IN_I>, + <&pm8150b_vadc ADC_CHG_TEMP>, + <&pm8150b_vadc ADC_AMUX_THM4_PU1>, + <&pm8150b_vadc ADC_VPH_PWR>, + <&pm8150b_vadc ADC_SBUx>; + io-channel-names = "mid_voltage", + "usb_in_voltage", + "usb_in_current", + "chg_temp", + "gpio1_voltage", + "vph_voltage", + "sbux_res"; + op,vbus-ctrl-gpio = <&pm8150l_gpios 9 GPIO_ACTIVE_LOW>; +}; + +&pm8150b_fg { + qcom,fg-force-load-profile; + oem,use_external_fg; + qcom,fg-rsense-sel = <0>; + qcom,fg-sys-term-current = <180>; + qcom,fg-chg-term-current = <165>; +}; + +&tlmm { + pm8150b_charger { + ship_mode_default: ship_mode_default { + mux { + pins = "gpio21"; + function = "gpio"; + }; + + config { + pins = "gpio21"; + drive-strength = <8>; + bias-pull-down; + }; + }; + }; + + oneplus_fastchg { + usb_sw_active: usb_sw_active { + mux { + pins = "gpio94", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio94", "gpio59"; + drive-strength = <16>; + bias-pull-down; + }; + }; + + usb_sw_suspend: usb_sw_suspend { + mux { + pins = "gpio94", "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio94", "gpio59"; + drive-strength = <2>; + bias-disable; + }; + }; + + fastchg_active: fastchg_active { + mux { + pins = "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio10"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + fastchg_suspend: fastchg_suspend { + mux { + pins = "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-disable; + }; + }; + + ap_clk_active: ap_clk_active { + mux { + pins = "gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio92"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + ap_clk_suspend: ap_clk_suspend { + mux { + pins = "gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio92"; + drive-strength = <2>; + bias-disable; + }; + }; + + ap_data_active: ap_data_active { + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + ap_data_suspend: ap_data_suspend { + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + drive-strength = <2>; + bias-disable; + }; + }; + }; +}; +/* @bsp, 2018/07/20 Battery & Charging porting END */ +/* @bsp,step motor START*/ +&pm8150b_gpios { + motor_mode0_gpio: motor_mode0_gpio { + pins = "gpio5"; /* GPIO 5 */ + function = "normal"; /* normal */ + output-high; + bias-disable; /* No Pull */ + }; + motor_mode0_hi_impedance: motor_mode0_hi_impedance { + pins = "gpio5"; /* GPIO 5 */ + function = "normal"; /* normal */ + bias-high-impedance; + }; + motor_boost_en: motor_boost_en { + pins = "gpio12"; /* GPIO 12 */ + function = "normal"; /* normal */ + output-low; + bias-disable; /* No Pull */ + }; + ab_id2 { + ab_id2_default: ab_id2_default { + pins = "gpio2"; + function = "normal"; + input-enable; + bias-disable; + power-source = <0>; + }; + }; +}; + +&pm8150l_gpios { + motor_pwm_config: motor_pwm_config { + pins = "gpio10"; + function = "func1"; + bias-disable; + power-source = <0>; + output-low; + qcom,drive-strength = <3>; + drive-push-pull; + }; + motor_mode1_gpio: motor_mode1_gpio { + pins = "gpio8"; + function = "normal"; + power-source = <0>; /* 3.6V */ + bias-disable; /* No Pull */ + output-low; /* digital output, no invert */ + qcom,drive-strength = <3>; /* LOW strength */ + }; + motor_dir_gpio: motor_dir_gpio { + pins = "gpio11"; + function = "normal"; + bias-disable; /* No Pull */ + power-source = <0>; /* VIN0 3.6V*/ + output-low; /* digital output, no invert */ + qcom,drive-strength = <3>; /* LOW strength */ + }; +}; + +&pm8150_gpios { + motor_sleep_gpio: motor_sleep_gpio { + pins = "gpio10"; + function = "normal"; + power-source = <0>; + bias-disable; + output-low; + }; + fp_id1_init: fp_id1_init { + pins = "gpio3"; + function = "normal"; + power-source = <0>; + bias-disable; + input-enable; + }; +}; + +&vendor { + step_motor { + compatible = "oneplus,step-motor"; + status = "okay"; + + pwms = <&pm8150l_pwm 1 20000000>; + op,boost-en-pin = <&pm8150b_gpios 12 GPIO_ACTIVE_LOW>; + op,mode0-pin = <&pm8150b_gpios 5 GPIO_ACTIVE_LOW>; + op,mode1-pin = <&pm8150l_gpios 8 GPIO_ACTIVE_LOW>; + op,nsleep-pin = <&pm8150_gpios 10 GPIO_ACTIVE_LOW>; + op,dir-pin = <&pm8150l_gpios 11 GPIO_ACTIVE_LOW>; + op,step-pin = <&pm8150l_gpios 10 GPIO_ACTIVE_LOW>; + pinctrl-names = "boost", + "m0_gpio", + "m0_high_impedance", + "m1_gpio", + "sleep_gpio", + "dir_gpio", + "pwm_config"; + pinctrl-0 = <&motor_boost_en>; + pinctrl-1 = <&motor_mode0_gpio>; + pinctrl-2 = <&motor_mode0_hi_impedance>; + pinctrl-3 = <&motor_mode1_gpio>; + pinctrl-4 = <&motor_sleep_gpio>; + pinctrl-5 = <&motor_dir_gpio>; + pinctrl-6 = <&motor_pwm_config>; + }; +}; + +&usb1 { + status = "disabled"; +}; + +/* @bsp,step motor END*/ + +&extcon_usb1 { + status = "disabled"; +}; + +&usb1 { + extcon = <&extcon_usb1>; + status = "disabled"; +}; + +&spmi_bus { + qcom,pm8009@10 { + compatible = "qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm8009_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0x400>; + interrupts = <0xa 0xc0 0 IRQ_TYPE_NONE>, + <0xa 0xc1 0 IRQ_TYPE_NONE>, + <0xa 0xc2 0 IRQ_TYPE_NONE>, + <0xa 0xc3 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8009_gpio1", "pm8009_gpio2", + "pm8009_gpio3", "pm8009_gpio4"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + /*power key + vol down long press hard reset*/ + qcom,pm8150@0 { + qcom,power-on@800 { + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>, + <0x0 0x8 0x5 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr", "resin", "kpdpwr-resin-bark"; + qcom,s3-src = "kpdpwr-and-resin"; + qcom,pon_1 { + qcom,support-reset = <0>; + qcom,s1-timer = <6720>; + qcom,s2-timer = <2000>; + qcom,s2-type = ; + qcom,pull-up; + }; + + qcom,pon_2 { + qcom,support-reset = <0>; + qcom,s1-timer = <6720>; + qcom,s2-timer = <2000>; + qcom,s2-type = ; + qcom,pull-up; + }; + + qcom,pon_3 { + qcom,pon-type = ; + qcom,support-reset = <0>; + qcom,s1-timer = <6720>; + qcom,s2-timer = <2000>; + qcom,s2-type = ; + qcom,pull-up; + }; + }; + }; +}; +&pm8150_gpios { + key_vol_down { + key_vol_down_default: key_vol_down_default { + pins = "gpio7"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <1>; + }; + }; + ab_id1 { + ab_id1_default: ab_id1_default { + pins = "gpio1"; + function = "normal"; + input-enable; + bias-disable; + power-source = <0>; + }; + }; +}; + +&soc { + gpio_keys { + pinctrl-0 = <&key_vol_up_default &key_vol_down_default>; + vol_down { + label = "volume_down"; + gpios = <&pm8150_gpios 7 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; + + bootloader_log { + compatible = "bootloader_log"; + linux,contiguous-region = <&bootloader_log_mem>; + }; +}; + +&reserved_memory { + + bootloader_log_mem: bootloader_log_mem@0x9FFF7000 { + reg = <0 0x9FFF7000 0 0x00009000>; + label = "bootloader_log_mem"; + }; + + param_mem: param_mem@ac200000 { + reg = <0 0xAC200000 0 0x00100000>; + label = "param_mem"; + }; + + //after cdsp_sec_mem + ramoops: ramoops@0xA9800000 { + compatible = "ramoops"; + reg = <0 0xA9800000 0 0x00400000>; + record-size = <0x40000>; //256x1024 + console-size = <0x40000>; + ftrace-size = <0x40000>; + pmsg-size= <0x200000>; + devinfo-size= <0x01000>; + ecc-size= <0x0>; + }; + + mtp_mem: mtp_mem@ac300000 { + reg = <0 0xAC300000 0 0x00B00000>; + label = "mtp_mem"; + }; +}; + +&pm8009_gpios { + pm8009_gpios_pinctl: pm8009_gpios_pinctl { + + rf_cable_ant1: rf_cable_ant1{ + pins = "gpio3"; + function = "normal"; + power-source = <1>; + bias-pull-up; + qcom,pull-up-strength = <0>; /* 30uA pull up */ + input-enable; /* digital input */ + }; + rf_cable_ant3: rf_cable_ant3 { + pins = "gpio4"; + function = "normal"; + power-source = <1>; + bias-pull-up; + qcom,pull-up-strength = <0>; /* 30uA pull up */ + input-enable; /* digital input */ + }; + }; +}; + +&soc { + oem_aboard_check:oem_aboard_check { + compatible = "oem,aboard"; + interrupt-parent = <&tlmm>; + oem,aboard-gpio-0 = <&pm8150_gpios 1 0>; + oem,aboard-gpio-1 = <&pm8150b_gpios 2 0>; + pinctrl-names = "oem_aboard_active"; + pinctrl-0 = <&ab_id1_default &ab_id2_default>; + }; + oem_serial_pinctrl { + compatible = "oem,oem_serial_pinctrl"; + pinctrl-names = "uart_pinctrl_active","uart_pinctrl_deactive"; + pinctrl-0 = <&qupv3_se12_2uart_active>; + pinctrl-1 = <&qupv3_se12_2uart_oem_sleep>; + }; + + oem_rf_cable:oem_rf_cable { + compatible = "oem,rf_cable"; + interrupt-parent = <&tlmm>; + rf,cable-gpio-0 = <&tlmm 36 0>; + rf,cable-gpio-1 = <&pm8009_gpios 4 0>; + rf,cable-support-timer = <0>; + pinctrl-names = "oem_rf_cable_active"; + pinctrl-0 = <&rf_cable_ant0_active &rf_cable_ant1 &rf_cable_ant3 >; + }; +}; + +&tlmm { + rf_cable_ant0_active: rf_cable_ant0_active { + mux { + pins = "gpio36"; + function = "gpio"; + }; + config { + pins = "gpio36"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se12_2uart_oem_sleep: qupv3_se12_2uart_oem_sleep { + mux { + pins = "gpio85", "gpio86"; + function = "gpio"; + }; + config { + pins = "gpio85", "gpio86"; + drive-strength = <2>; + bias-pull-down; + }; + }; +}; + +&qupv3_se12_2uart { + compatible = "qcom,msm-geni-console-oem"; +}; + +/*disable smb3190 config */ +&smb1390 { + status = "disabled"; +}; +&smb1390_charger { + status = "disabled"; +}; +&smb1355 { + status = "disabled"; +}; +&smb1355_charger { + status = "disabled"; +}; + +/* neil.sun@Connectivity, 2019/05/16, disable SMMU S1 for WLAN and ipa */ +&ipa_smmu_wlan { + qcom,smmu-s1-bypass; +}; + +&icnss { + qcom,smmu-s1-bypass; +}; + +/* eleven.xie@Connectivity, 2019/05/20, disable wil6210 dts config */ +&wil6210 { + status = "disabled"; +}; + diff --git a/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi b/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi index a771977a5bf8..d37a1aaab096 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi @@ -163,9 +163,6 @@ qcom,vreg-0.9-voltage-level = <880000 880000 24000>; qcom,vreg-cx-voltage-level = ; - qcom,bw-scale = ; msi-parent = <&pcie0_msi>; @@ -486,9 +483,6 @@ qcom,vreg-0.9-voltage-level = <880000 880000 24000>; qcom,vreg-cx-voltage-level = ; - qcom,bw-scale = ; msi-parent = <&pcie1_msi>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi index 29df85b5fe82..416bba8e3bd8 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi @@ -69,14 +69,14 @@ storage_cd: storage_cd { mux { - pins = "gpio96"; - function = "gpio"; + /*pins = "gpio96"; + function = "gpio";*/ }; config { - pins = "gpio96"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ + /*pins = "gpio96";*/ + /*bias-pull-up;*/ /* pull up */ + /*drive-strength = <2>;*/ /* 2 MA */ }; }; @@ -513,14 +513,14 @@ wil6210_refclk3_en_pin: wil6210_refclk3_en_pin { mux { - pins = "gpio87"; - function = "gpio"; + /*pins = "gpio87"; + function = "gpio";*/ }; config { - pins = "gpio87"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ + /*pins = "gpio87";*/ + /*bias-pull-down;*/ /* PULL DOWN */ + /*drive-strength = <2>;*/ /* 2 MA */ }; }; @@ -1689,7 +1689,8 @@ config { pins = "gpio55", "gpio56"; drive-strength = <2>; - bias-pull-up; + bias-disable; + input-enable; }; }; }; @@ -4285,456 +4286,6 @@ }; }; - hs1_i2s_mclk { - hs1_i2s_mclk_sleep: hs1_i2s_mclk_sleep { - mux { - pins = "gpio155"; - function = "gpio"; - }; - - config { - pins = "gpio155"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs1_i2s_mclk_active: hs1_i2s_mclk_active { - mux { - pins = "gpio155"; - function = "hs1_mi2s"; - }; - - config { - pins = "gpio155"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs1_i2s_sck { - hs1_i2s_sck_sleep: hs1_i2s_sck_sleep { - mux { - pins = "gpio156"; - function = "gpio"; - }; - - config { - pins = "gpio156"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs1_i2s_sck_active: hs1_i2s_sck_active { - mux { - pins = "gpio156"; - function = "hs1_mi2s"; - }; - - config { - pins = "gpio156"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs1_i2s_ws { - hs1_i2s_ws_sleep: hs1_i2s_ws_sleep { - mux { - pins = "gpio157"; - function = "gpio"; - }; - - config { - pins = "gpio157"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs1_i2s_ws_active: hs1_i2s_ws_active { - mux { - pins = "gpio157"; - function = "hs1_mi2s"; - }; - - config { - pins = "gpio157"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs1_i2s_data0 { - hs1_i2s_data0_sleep: hs1_i2s_data0_sleep { - mux { - pins = "gpio158"; - function = "sleep"; - }; - - config { - pins = "gpio158"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs1_i2s_data0_active: hs1_i2s_data0_active { - mux { - pins = "gpio158"; - function = "hs1_mi2s"; - }; - - config { - pins = "gpio158"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs1_i2s_data1 { - hs1_i2s_data1_sleep: hs1_i2s_data1_sleep { - mux { - pins = "gpio159"; - function = "gpio"; - }; - - config { - pins = "gpio159"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs1_i2s_data1_active: hs1_i2s_data1_active { - mux { - pins = "gpio159"; - function = "hs1_mi2s"; - }; - - config { - pins = "gpio159"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - input-enable; - }; - }; - }; - - hs2_i2s_mclk { - hs2_i2s_mclk_sleep: hs2_i2s_mclk_sleep { - mux { - pins = "gpio160"; - function = "gpio"; - }; - - config { - pins = "gpio160"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs2_i2s_mclk_active: hs2_i2s_mclk_active { - mux { - pins = "gpio160"; - function = "hs2_mi2s"; - }; - - config { - pins = "gpio160"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs2_i2s_sck { - hs2_i2s_sck_sleep: hs2_i2s_sck_sleep { - mux { - pins = "gpio161"; - function = "gpio"; - }; - - config { - pins = "gpio161"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs2_i2s_sck_active: hs2_i2s_sck_active { - mux { - pins = "gpio161"; - function = "hs2_mi2s"; - }; - - config { - pins = "gpio161"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs2_i2s_ws { - hs2_i2s_ws_sleep: hs2_i2s_ws_sleep { - mux { - pins = "gpio162"; - function = "gpio"; - }; - - config { - pins = "gpio162"; - drive-strength = <2>; /* 8 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs2_i2s_ws_active: hs2_i2s_ws_active { - mux { - pins = "gpio162"; - function = "hs2_mi2s"; - }; - - config { - pins = "gpio162"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs2_i2s_data0 { - hs2_i2s_data0_sleep: hs2_i2s_data0_sleep { - mux { - pins = "gpio163"; - function = "gpio"; - }; - - config { - pins = "gpio163"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs2_i2s_data0_active: hs2_i2s_data0_active { - mux { - pins = "gpio163"; - function = "hs2_mi2s"; - }; - - config { - pins = "gpio163"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs2_i2s_data1 { - hs2_i2s_data1_sleep: hs2_i2s_data1_sleep { - mux { - pins = "gpio164"; - function = "gpio"; - }; - - config { - pins = "gpio164"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs2_i2s_data1_active: hs2_i2s_data1_active { - mux { - pins = "gpio164"; - function = "hs2_mi2s"; - }; - - config { - pins = "gpio164"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - input-enable; - }; - }; - }; - - hs3_i2s_mclk { - hs3_i2s_mclk_sleep: hs3_i2s_mclk_sleep { - mux { - pins = "gpio125"; - function = "gpio"; - }; - - config { - pins = "gpio125"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs3_i2s_mclk_active: hs3_i2s_mclk_active { - mux { - pins = "gpio125"; - function = "hs3_mi2s"; - }; - - config { - pins = "gpio125"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs3_i2s_sck { - hs3_i2s_sck_sleep: hs3_i2s_sck_sleep { - mux { - pins = "gpio165"; - function = "gpio"; - }; - - config { - pins = "gpio165"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs3_i2s_sck_active: hs3_i2s_sck_active { - mux { - pins = "gpio165"; - function = "hs3_mi2s"; - }; - - config { - pins = "gpio165"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs3_i2s_ws { - hs3_i2s_ws_sleep: hs3_i2s_ws_sleep { - mux { - pins = "gpio166"; - function = "gpio"; - }; - - config { - pins = "gpio166"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs3_i2s_ws_active: hs3_i2s_ws_active { - mux { - pins = "gpio166"; - function = "hs3_mi2s"; - }; - - config { - pins = "gpio166"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs3_i2s_data0 { - hs3_i2s_data0_sleep: hs3_i2s_data0_sleep { - mux { - pins = "gpio167"; - function = "gpio"; - }; - - config { - pins = "gpio167"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs3_i2s_data0_active: hs3_i2s_data0_active { - mux { - pins = "gpio167"; - function = "hs3_mi2s"; - }; - - config { - pins = "gpio167"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - output-high; - }; - }; - }; - - hs3_i2s_data1 { - hs3_i2s_data1_sleep: hs3_i2s_data1_sleep { - mux { - pins = "gpio168"; - function = "gpio"; - }; - - config { - pins = "gpio168"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* PULL DOWN */ - input-enable; - }; - }; - - hs3_i2s_data1_active: hs3_i2s_data1_active { - mux { - pins = "gpio168"; - function = "hs3_mi2s"; - }; - - config { - pins = "gpio168"; - drive-strength = <8>; /* 8 mA */ - bias-disable; /* NO PULL */ - input-enable; - }; - }; - }; - emac { emac_mdc: emac_mdc { mux { diff --git a/arch/arm64/boot/dts/qcom/sm8150-regulator.dtsi b/arch/arm64/boot/dts/qcom/sm8150-regulator.dtsi index 40a4ab37f02a..e12333e4bc09 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-regulator.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-regulator.dtsi @@ -909,13 +909,13 @@ }; rpmh-regulator-ldof2 { - compatible = "qcom,rpmh-xob-regulator"; + compatible = "qcom,rpmh-vrm-regulator"; mboxes = <&apps_rsc 0>; qcom,resource-name = "ldof2"; L2F: pm8009_l2: regulator-pm8009-l2 { regulator-name = "pm8009_l2"; qcom,set = ; - regulator-min-microvolt = <1200000>; + regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1200000>; }; }; @@ -944,6 +944,54 @@ }; }; + rpmh-regulator-ldof1 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof1"; + L1F: pm8009_l1: regulator-pm8009-l1 { + regulator-name = "pm8009_l1"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + }; + + rpmh-regulator-ldof3 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof3"; + L3F: pm8009_l3: regulator-pm8009-l3 { + regulator-name = "pm8009_l3"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + }; + + rpmh-regulator-ldof4 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof4"; + L4F: pm8009_l4: regulator-pm8009-l4 { + regulator-name = "pm8009_l4"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + }; + + rpmh-regulator-ldof7 { + compatible = "qcom,rpmh-xob-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof7"; + L7F: pm8009_l7: regulator-pm8009-l7 { + regulator-name = "pm8009_l7"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + refgen: refgen-regulator@88e7000 { compatible = "qcom,refgen-regulator"; reg = <0x88e7000 0x60>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi index 58bb42baefe7..5e6720c77084 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi @@ -33,6 +33,10 @@ #include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi" #include +#include "dsi-panel-samsung_oneplus_dsc.dtsi" +#include "dsi-panel-samsung_s6e3fc2x01.dtsi" +#include "dsi-panel-samsung_sofef00_m_video.dtsi" + &tlmm { display_panel_avdd_eldo_default: display_panel_avdd_eldo_default { @@ -174,7 +178,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-enable-ramp-delay = <233>; - gpio = <&tlmm 130 0>; +// gpio = <&tlmm 130 0>; enable-active-high; regulator-boot-on; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sdxprairie-mtp-overlay.dts b/arch/arm64/boot/dts/qcom/sm8150-sdxprairie-mtp-overlay.dts index 94a61455100e..8e62d71f7763 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sdxprairie-mtp-overlay.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-sdxprairie-mtp-overlay.dts @@ -24,6 +24,8 @@ #include "sm8150-sdxprairie.dtsi" #include "sm8150-mtp-audio-overlay.dtsi" +#include "sm8150-oem.dtsi" + / { model = "SDXPRAIRIE MTP"; compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi index 19e713aacb6f..2c01b219613a 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sdxprairie.dtsi @@ -42,8 +42,7 @@ }; mhi_chan@25 { - mhi,num-elements = <32>; - mhi,event-ring = <1>; + status = "disabled"; }; mhi_chan@80 { @@ -91,6 +90,7 @@ mhi_devices { mhi_qrtr { + mhi,chan = "IPCR"; qcom,net-id = <3>; }; }; @@ -206,6 +206,16 @@ status = "disabled"; }; + +&icnss { + esoc-names = "mdm"; + esoc-0 = <&mdm3>; +}; + +&icnss { + qcom,clk-monitor-enable; +}; + &soc { qmi-tmd-devices { compatible = "qcom,qmi-cooling-devices"; diff --git a/arch/arm64/boot/dts/qcom/sm8150-thermal-overlay.dtsi b/arch/arm64/boot/dts/qcom/sm8150-thermal-overlay.dtsi index 643bb84e3669..87e75cf559e7 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-thermal-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-thermal-overlay.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -127,134 +127,169 @@ soc { cooling-maps { - soc_cpu4 { - trip = <&soc_trip>; + soctrip_cpu4 { + trip = <&soc_trip2>; cooling-device = - <&CPU4 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + <&CPU4 6 6>; }; - soc_cpu5 { - trip = <&soc_trip>; + soctrip_cpu7 { + trip = <&soc_trip2>; cooling-device = - <&CPU5 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; - soc_cpu6 { + soctrip_cpu6 { trip = <&soc_trip>; cooling-device = <&CPU6 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - soc_cpu7 { - trip = <&soc_trip>; - cooling-device = - <&CPU7 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + THERMAL_MAX_LIMIT>; }; }; }; - pm8150b-bcl-lvl0 { + pm8150b-vbat-lvl0 { cooling-maps { vbat_cpu4 { - trip = <&b_bcl_lvl0>; + trip = <&vbat_lvl0>; cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; vbat_cpu5 { - trip = <&b_bcl_lvl0>; + trip = <&vbat_lvl0>; cooling-device = <&CPU5 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; vbat_gpu0 { - trip = <&b_bcl_lvl0>; + trip = <&vbat_lvl0>; cooling-device = <&msm_gpu 2 2>; }; }; }; - pm8150b-bcl-lvl1 { + pm8150b-vbat-lvl1 { cooling-maps { vbat_cpu6 { - trip = <&b_bcl_lvl1>; + trip = <&vbat_lvl1>; cooling-device = <&CPU6 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; vbat_cpu7 { - trip = <&b_bcl_lvl1>; + trip = <&vbat_lvl1>; cooling-device = <&CPU7 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; vbat_gpu1 { - trip = <&b_bcl_lvl1>; + trip = <&vbat_lvl1>; cooling-device = <&msm_gpu 4 4>; }; }; }; - pm8150b-bcl-lvl2 { + pm8150b-vbat-lvl2 { cooling-maps { vbat_gpu2 { - trip = <&b_bcl_lvl2>; + trip = <&vbat_lvl2>; cooling-device = <&msm_gpu THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; }; }; - pm8150l-bcl-lvl0 { + pm8150b-ibat-lvl0 { + cooling-maps { + ibat_cpu4 { + trip = <&ibat_lvl0>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + ibat_cpu5 { + trip = <&ibat_lvl0>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + ibat_gpu0 { + trip = <&ibat_lvl0>; + cooling-device = <&msm_gpu 2 2>; + }; + }; + }; + + pm8150b-ibat-lvl1 { + cooling-maps { + ibat_cpu6 { + trip = <&ibat_lvl1>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + ibat_cpu7 { + trip = <&ibat_lvl1>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + ibat_gpu1 { + trip = <&ibat_lvl1>; + cooling-device = <&msm_gpu 4 4>; + }; + }; + }; + + pm8150l-vph-lvl0 { disable-thermal-zone; cooling-maps { vph_cpu4 { - trip = <&l_bcl_lvl0>; + trip = <&vph_lvl0>; cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; vph_cpu5 { - trip = <&l_bcl_lvl0>; + trip = <&vph_lvl0>; cooling-device = <&CPU5 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; vph_gpu0 { - trip = <&l_bcl_lvl0>; + trip = <&vph_lvl0>; cooling-device = <&msm_gpu 2 2>; }; }; }; - pm8150l-bcl-lvl1 { + pm8150l-vph-lvl1 { disable-thermal-zone; cooling-maps { vph_cpu6 { - trip = <&l_bcl_lvl1>; + trip = <&vph_lvl1>; cooling-device = <&CPU6 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; vph_cpu7 { - trip = <&l_bcl_lvl1>; + trip = <&vph_lvl1>; cooling-device = <&CPU7 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; vph_gpu1 { - trip = <&l_bcl_lvl1>; + trip = <&vph_lvl1>; cooling-device = <&msm_gpu 4 4>; }; }; }; - pm8150l-bcl-lvl2 { + pm8150l-vph-lvl2 { disable-thermal-zone; cooling-maps { vph_gpu2 { - trip = <&l_bcl_lvl2>; + trip = <&vph_lvl2>; cooling-device = <&msm_gpu THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150-thermal.dtsi b/arch/arm64/boot/dts/qcom/sm8150-thermal.dtsi index 59c7e913659c..79460e4d4401 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-thermal.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-thermal.dtsi @@ -774,8 +774,8 @@ }; gpuss-max-step { - polling-delay-passive = <10>; - polling-delay = <100>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-governor = "step_wise"; wake-capable-sensor; trips { diff --git a/arch/arm64/boot/dts/qcom/sm8150-usb.dtsi b/arch/arm64/boot/dts/qcom/sm8150-usb.dtsi index 210ead532d21..cc1d4930aa87 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-usb.dtsi @@ -61,6 +61,7 @@ 0x144 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + qcom,pm-qos-latency = <44>; qcom,msm-bus,name = "usb0"; qcom,msm-bus,num-cases = <4>; @@ -98,10 +99,11 @@ snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,ssp-u3-u0-quirk; - snps,usb3-u1u2-disable; + //snps,usb3-u1u2-disable; usb-core-id = <0>; tx-fifo-resize; - maximum-speed = "super-speed-plus"; + maximum-speed = "super-speed"; + //maximum-speed = "super-speed-plus"; dr_mode = "otg"; }; @@ -386,6 +388,7 @@ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <27696>; qcom,charging-disabled; + qcom,pm-qos-latency = <44>; qcom,msm-bus,name = "usb1"; qcom,msm-bus,num-cases = <3>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-v2-camera.dtsi b/arch/arm64/boot/dts/qcom/sm8150-v2-camera.dtsi index c0793f3d7c87..9bcdf51cfe09 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-v2-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-v2-camera.dtsi @@ -238,7 +238,7 @@ /* Shared region is 150MB long */ iova-region-name = "shared"; iova-region-start = <0x7400000>; - iova-region-len = <0x9600000>; + iova-region-len = <0xc800000>; iova-region-id = <0x1>; status = "ok"; }; @@ -246,7 +246,7 @@ iova-mem-region-secondary-heap { /* Secondary heap region is 1MB long */ iova-region-name = "secheap"; - iova-region-start = <0x10A00000>; + iova-region-start = <0x13C00000>; iova-region-len = <0x100000>; iova-region-id = <0x4>; status = "ok"; @@ -255,8 +255,8 @@ iova-mem-region-io { /* IO region is approximately 3.3 GB */ iova-region-name = "io"; - iova-region-start = <0x10C00000>; - iova-region-len = <0xCF300000>; + iova-region-start = <0x13E00000>; + iova-region-len = <0xCC100000>; iova-region-id = <0x3>; status = "ok"; }; @@ -264,7 +264,7 @@ iova-mem-qdss-region { /* QDSS region is appropriate 1MB */ iova-region-name = "qdss"; - iova-region-start = <0x10B00000>; + iova-region-start = <0x13D00000>; iova-region-len = <0x100000>; iova-region-id = <0x5>; qdss-phy-addr = <0x16790000>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-v2.dtsi b/arch/arm64/boot/dts/qcom/sm8150-v2.dtsi index 737195c6a3ea..a94098ec58ca 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-v2.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-v2.dtsi @@ -1128,6 +1128,12 @@ USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0 USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00 0 USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00 0 + /*op do optimize A/B side 0x1214/0x1614:0x06 0x1308/0x1708:0x0c + *0x120C/0x160C:0x06 + */ + USB3_DP_QSERDES_TXA_TX_DRV_LVL 0x06 0 + USB3_DP_QSERDES_TXA_PRE_EMPH 0x0c 0 + USB3_DP_QSERDES_TXA_TX_EMP_POST1_LVL 0x06 0 USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16 0 USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x05 0 USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x20 0 @@ -1171,6 +1177,12 @@ USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0 USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00 0 USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00 0 + /*op do optimize A/B side 0x1214/0x1614:0x06 0x1308/0x1708:0x0c + *0x120C/0x160C:0x06 + */ + USB3_DP_QSERDES_TXB_TX_DRV_LVL 0x06 0 + USB3_DP_QSERDES_TXB_PRE_EMPH 0x0c 0 + USB3_DP_QSERDES_TXB_TX_EMP_POST1_LVL 0x06 0 USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16 0 USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x05 0 USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x01 0 diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 2799385f733a..f5e52a2e1f48 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -580,7 +580,7 @@ compatible = "android,fstab"; vendor { compatible = "android,vendor"; - dev = "/dev/block/platform/soc/8804000.sdhci/by-name/vendor"; + dev = "/dev/block/platform/soc/1d84000.sdhci/by-name/vendor"; type = "ext4"; mnt_flags = "ro,barrier=1,discard"; fsmgr_flags = "wait,slotselect,avb"; @@ -3003,7 +3003,8 @@ qcom_seecom: qseecom@87900000 { compatible = "qcom,qseecom"; - reg = <0x87900000 0x2200000>; + /* enlarge TA memory size from 34M to 62M on 2018/11/22 */ + reg = <0x87900000 0x3E00000>; reg-names = "secapp-region"; memory-region = <&qseecom_mem>; qcom,hlos-num-ce-hw-instances = <1>; @@ -3020,7 +3021,8 @@ qcom_smcinvoke: smcinvoke@87900000 { compatible = "qcom,smcinvoke"; - reg = <0x87900000 0x2200000>; + /* enlarge TA memory size from 34M to 62M on 2018/11/22 */ + reg = <0x87900000 0x3E00000>; reg-names = "secapp-region"; }; diff --git a/arch/arm64/boot/dts/qcom/trinket-thermal-overlay.dtsi b/arch/arm64/boot/dts/qcom/trinket-thermal-overlay.dtsi index 1c3a5fe6a950..cc055b4a542d 100644 --- a/arch/arm64/boot/dts/qcom/trinket-thermal-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-thermal-overlay.dtsi @@ -125,52 +125,52 @@ }; }; - pmi632-bcl-lvl0 { + pmi632-vbat-lvl0 { cooling-maps { - cpu0_cdev { - trip = <&bcl_lvl0>; + vbat_cpu0 { + trip = <&pmi632_vbat_lvl0>; cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-6) (THERMAL_MAX_LIMIT-6)>; }; - cpu1_cdev { - trip = <&bcl_lvl0>; + vbat_cpu1 { + trip = <&pmi632_vbat_lvl0>; cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-6) (THERMAL_MAX_LIMIT-6)>; }; - cpu2_cdev { - trip = <&bcl_lvl0>; + vbat_cpu2 { + trip = <&pmi632_vbat_lvl0>; cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-6) (THERMAL_MAX_LIMIT-6)>; }; - cpu3_cdev { - trip = <&bcl_lvl0>; + vbat_cpu3 { + trip = <&pmi632_vbat_lvl0>; cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-6) (THERMAL_MAX_LIMIT-6)>; }; - cpu4_cdev { - trip = <&bcl_lvl0>; + vbat_cpu4 { + trip = <&pmi632_vbat_lvl0>; cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-6) (THERMAL_MAX_LIMIT-6)>; }; - cpu5_cdev { - trip = <&bcl_lvl0>; + vbat_cpu5 { + trip = <&pmi632_vbat_lvl0>; cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-6) (THERMAL_MAX_LIMIT-6)>; }; - cpu6_cdev { - trip = <&bcl_lvl0>; + vbat_cpu6 { + trip = <&pmi632_vbat_lvl0>; cooling-device = <&CPU6 (THERMAL_MAX_LIMIT-6) (THERMAL_MAX_LIMIT-6)>; }; - cpu7_cdev { - trip = <&bcl_lvl0>; + vbat_cpu7 { + trip = <&pmi632_vbat_lvl0>; cooling-device = <&CPU7 (THERMAL_MAX_LIMIT-6) (THERMAL_MAX_LIMIT-6)>; @@ -178,52 +178,52 @@ }; }; - pmi632-bcl-lvl1 { + pmi632-vbat-lvl1 { cooling-maps { - cpu0_cdev { - trip = <&bcl_lvl1>; + vbat_cpu0 { + trip = <&pmi632_vbat_lvl1>; cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) (THERMAL_MAX_LIMIT-5)>; }; - cpu1_cdev { - trip = <&bcl_lvl1>; + vbat_cpu1 { + trip = <&pmi632_vbat_lvl1>; cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) (THERMAL_MAX_LIMIT-5)>; }; - cpu2_cdev { - trip = <&bcl_lvl1>; + vbat_cpu2 { + trip = <&pmi632_vbat_lvl1>; cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) (THERMAL_MAX_LIMIT-5)>; }; - cpu3_cdev { - trip = <&bcl_lvl1>; + vbat_cpu3 { + trip = <&pmi632_vbat_lvl1>; cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) (THERMAL_MAX_LIMIT-5)>; }; - cpu4_cdev { - trip = <&bcl_lvl1>; + vbat_cpu4 { + trip = <&pmi632_vbat_lvl1>; cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-5) (THERMAL_MAX_LIMIT-5)>; }; - cpu5_cdev { - trip = <&bcl_lvl1>; + vbat_cpu5 { + trip = <&pmi632_vbat_lvl1>; cooling-device = <&CPU5 (THERMAL_MAX_LIMIT-5) (THERMAL_MAX_LIMIT-5)>; }; - cpu6_cdev { - trip = <&bcl_lvl1>; + vbat_cpu6 { + trip = <&pmi632_vbat_lvl1>; cooling-device = <&CPU6 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; - cpu7_cdev { - trip = <&bcl_lvl1>; + vbat_cpu7 { + trip = <&pmi632_vbat_lvl1>; cooling-device = <&CPU7 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; @@ -231,52 +231,158 @@ }; }; - pmi632-bcl-lvl2 { + pmi632-vbat-lvl2 { cooling-maps { - cpu0_cdev { - trip = <&bcl_lvl2>; + vbat_cpu0 { + trip = <&pmi632_vbat_lvl2>; cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-5) (THERMAL_MAX_LIMIT-5)>; }; - cpu1_cdev { - trip = <&bcl_lvl2>; + vbat_cpu1 { + trip = <&pmi632_vbat_lvl2>; cooling-device = <&CPU1 (THERMAL_MAX_LIMIT-5) (THERMAL_MAX_LIMIT-5)>; }; - cpu2_cdev { - trip = <&bcl_lvl2>; + vbat_cpu2 { + trip = <&pmi632_vbat_lvl2>; cooling-device = <&CPU2 (THERMAL_MAX_LIMIT-5) (THERMAL_MAX_LIMIT-5)>; }; - cpu3_cdev { - trip = <&bcl_lvl2>; + vbat_cpu3 { + trip = <&pmi632_vbat_lvl2>; cooling-device = <&CPU3 (THERMAL_MAX_LIMIT-5) (THERMAL_MAX_LIMIT-5)>; }; - cpu4_cdev { - trip = <&bcl_lvl2>; + vbat_cpu4 { + trip = <&pmi632_vbat_lvl2>; cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; - cpu5_cdev { - trip = <&bcl_lvl2>; + vbat_cpu5 { + trip = <&pmi632_vbat_lvl2>; cooling-device = <&CPU5 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; - cpu6_cdev { - trip = <&bcl_lvl2>; + vbat_cpu6 { + trip = <&pmi632_vbat_lvl2>; cooling-device = <&CPU6 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; - cpu7_cdev { - trip = <&bcl_lvl2>; + vbat_cpu7 { + trip = <&pmi632_vbat_lvl2>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pmi632-ibat-lvl0 { + cooling-maps { + ibat_cpu0 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU0 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + ibat_cpu1 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU1 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + ibat_cpu2 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU2 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + ibat_cpu3 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU3 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + ibat_cpu4 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU4 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + ibat_cpu5 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU5 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + ibat_cpu6 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU6 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + ibat_cpu7 { + trip = <&pmi632_ibat_lvl0>; + cooling-device = + <&CPU7 (THERMAL_MAX_LIMIT-6) + (THERMAL_MAX_LIMIT-6)>; + }; + }; + }; + + pmi632-ibat-lvl1 { + cooling-maps { + ibat_cpu0 { + trip = <&pmi632_ibat_lvl1>; + cooling-device = + <&CPU0 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + ibat_cpu1 { + trip = <&pmi632_ibat_lvl1>; + cooling-device = + <&CPU1 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + ibat_cpu2 { + trip = <&pmi632_ibat_lvl1>; + cooling-device = + <&CPU2 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + ibat_cpu3 { + trip = <&pmi632_ibat_lvl1>; + cooling-device = + <&CPU3 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + ibat_cpu4 { + trip = <&pmi632_ibat_lvl1>; + cooling-device = + <&CPU4 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + ibat_cpu5 { + trip = <&pmi632_ibat_lvl1>; + cooling-device = + <&CPU5 (THERMAL_MAX_LIMIT-5) + (THERMAL_MAX_LIMIT-5)>; + }; + ibat_cpu6 { + trip = <&pmi632_ibat_lvl1>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + ibat_cpu7 { + trip = <&pmi632_ibat_lvl1>; cooling-device = <&CPU7 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; diff --git a/arch/arm64/boot/dts/qcom/trinket-usb.dtsi b/arch/arm64/boot/dts/qcom/trinket-usb.dtsi index bb5087492c11..5a7c14dd4bb8 100644 --- a/arch/arm64/boot/dts/qcom/trinket-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/trinket-usb.dtsi @@ -54,7 +54,6 @@ 0x144 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <21288>; - qcom,gsi-disable-io-coherency; qcom,msm-bus,name = "usb0"; qcom,msm-bus,num-cases = <4>; diff --git a/arch/arm64/boot/install.sh b/arch/arm64/boot/install.sh old mode 100644 new mode 100755 diff --git a/arch/arm64/configs/vendor/atoll-perf_defconfig b/arch/arm64/configs/vendor/atoll-perf_defconfig index 3a37a69f1c58..0a1d220d5122 100644 --- a/arch/arm64/configs/vendor/atoll-perf_defconfig +++ b/arch/arm64/configs/vendor/atoll-perf_defconfig @@ -67,7 +67,6 @@ CONFIG_ZSMALLOC=y CONFIG_BALANCE_ANON_FILE_RECLAIM=y CONFIG_SECCOMP=y # CONFIG_UNMAP_KERNEL_AT_EL0 is not set -CONFIG_ARM64_SSBD=y CONFIG_ARMV8_DEPRECATED=y CONFIG_SWP_EMULATION=y CONFIG_CP15_BARRIER_EMULATION=y @@ -79,6 +78,7 @@ CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y CONFIG_KRYO_PMU_WORKAROUND=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_COMPAT=y +CONFIG_PM_AUTOSLEEP=y CONFIG_PM_WAKELOCKS=y CONFIG_PM_WAKELOCKS_LIMIT=0 # CONFIG_PM_WAKELOCKS_GC is not set @@ -105,7 +105,6 @@ CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y -CONFIG_NET_IPGRE_DEMUX=y CONFIG_SYN_COOKIES=y CONFIG_NET_IPVTI=y CONFIG_INET_AH=y @@ -224,7 +223,6 @@ CONFIG_NET_CLS_FW=y CONFIG_NET_CLS_U32=y CONFIG_CLS_U32_MARK=y CONFIG_NET_CLS_FLOW=y -CONFIG_NET_CLS_BPF=y CONFIG_NET_EMATCH=y CONFIG_NET_EMATCH_CMP=y CONFIG_NET_EMATCH_NBYTE=y @@ -252,7 +250,6 @@ CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y CONFIG_ZRAM=y CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_LOOP_MIN_COUNT=16 CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_HDCP_QSEECOM=y @@ -294,13 +291,11 @@ CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=y CONFIG_PPP_MULTILINK=y CONFIG_PPPOE=y -CONFIG_PPTP=y CONFIG_PPPOL2TP=y CONFIG_PPPOLAC=y CONFIG_PPPOPNS=y CONFIG_PPP_ASYNC=y CONFIG_PPP_SYNC_TTY=y -CONFIG_USB_RTL8152=y CONFIG_USB_USBNET=y CONFIG_WIL6210=m CONFIG_WCNSS_MEM_PRE_ALLOC=y @@ -322,15 +317,6 @@ CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_EXTRA_SYSFS=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_TEST_REPORTING=y -CONFIG_TOUCHSCREEN_SYNAPTICS_TCM=y -CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_CORE=y -CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_TOUCH=y -CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_DEVICE=y -CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_TESTING=y -CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_REFLASH=y -CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_RECOVERY=y -CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_ZEROFLASH=y -CONFIG_TOUCHSCREEN_SYNAPTICS_TCM_DIAGNOSTICS=y CONFIG_INPUT_MISC=y CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_UINPUT=y @@ -338,7 +324,6 @@ CONFIG_INPUT_UINPUT=y # CONFIG_LEGACY_PTYS is not set # CONFIG_DEVMEM is not set CONFIG_SERIAL_MSM_GENI=y -CONFIG_SERIAL_MSM_WITH_HALF_SAMPLING=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_MSM_LEGACY=y # CONFIG_DEVPORT is not set @@ -361,6 +346,7 @@ CONFIG_SLIMBUS_MSM_NGD=y CONFIG_PTP_1588_CLOCK=y CONFIG_PINCTRL_SX150X=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_PINCTRL_SDMMAGPIE=y CONFIG_PINCTRL_ATOLL=y CONFIG_PINCTRL_SLPI=y CONFIG_GPIO_SYSFS=y @@ -384,16 +370,15 @@ CONFIG_QTI_THERMAL_LIMITS_DCVS=y CONFIG_QTI_VIRTUAL_SENSOR=y CONFIG_QTI_AOP_REG_COOLING_DEVICE=y CONFIG_QTI_QMI_COOLING_DEVICE=y -CONFIG_QTI_QMI_SENSOR=y CONFIG_REGULATOR_COOLING_DEVICE=y CONFIG_QTI_BCL_PMIC5=y CONFIG_QTI_BCL_SOC_DRIVER=y CONFIG_QTI_ADC_TM=y +CONFIG_QTI_CX_IPEAK_COOLING_DEVICE=y CONFIG_MFD_I2C_PMIC=y CONFIG_MFD_SPMI_PMIC=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_PROXY_CONSUMER=y -CONFIG_REGULATOR_PM8008=y CONFIG_REGULATOR_QPNP_AMOLED=y CONFIG_REGULATOR_QPNP_LCDB=y CONFIG_REGULATOR_REFGEN=y @@ -553,12 +538,6 @@ CONFIG_MSM_VIDEOCC_SDMMAGPIE=y CONFIG_MSM_NPUCC_SDMMAGPIE=y CONFIG_MSM_GPUCC_SDMMAGPIE=y CONFIG_MSM_DEBUGCC_SDMMAGPIE=y -CONFIG_SM_GCC_ATOLL=y -CONFIG_SM_CAMCC_ATOLL=y -CONFIG_SM_VIDEOCC_ATOLL=y -CONFIG_SM_DISPCC_ATOLL=y -CONFIG_SM_NPUCC_ATOLL=y -CONFIG_SM_DEBUGCC_ATOLL=y CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y CONFIG_QCOM_APCS_IPC=y @@ -575,6 +554,8 @@ CONFIG_RPMSG_QCOM_GLINK_SPI=y CONFIG_QCOM_CPUSS_DUMP=y CONFIG_QCOM_RUN_QUEUE_STATS=y CONFIG_QCOM_LLCC=y +CONFIG_QCOM_SM6150_LLCC=y +CONFIG_QCOM_SDMMAGPIE_LLCC=y CONFIG_QCOM_ATOLL_LLCC=y CONFIG_QCOM_LLCC_PERFMON=m CONFIG_QCOM_QMI_HELPERS=y @@ -665,7 +646,6 @@ CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y CONFIG_QFMT_V2=y CONFIG_FUSE_FS=y -CONFIG_OVERLAY_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS_POSIX_ACL=y diff --git a/arch/arm64/configs/vendor/atoll_defconfig b/arch/arm64/configs/vendor/atoll_defconfig index a1b038e0b444..f27b39732be8 100644 --- a/arch/arm64/configs/vendor/atoll_defconfig +++ b/arch/arm64/configs/vendor/atoll_defconfig @@ -72,7 +72,6 @@ CONFIG_BALANCE_ANON_FILE_RECLAIM=y CONFIG_SECCOMP=y # CONFIG_UNMAP_KERNEL_AT_EL0 is not set CONFIG_PRINT_VMEMLAYOUT=y -CONFIG_ARM64_SSBD=y CONFIG_ARMV8_DEPRECATED=y CONFIG_SWP_EMULATION=y CONFIG_CP15_BARRIER_EMULATION=y @@ -83,6 +82,7 @@ CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y CONFIG_KRYO_PMU_WORKAROUND=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_COMPAT=y +CONFIG_PM_AUTOSLEEP=y CONFIG_PM_WAKELOCKS=y CONFIG_PM_WAKELOCKS_LIMIT=0 # CONFIG_PM_WAKELOCKS_GC is not set @@ -110,7 +110,6 @@ CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y -CONFIG_NET_IPGRE_DEMUX=y CONFIG_SYN_COOKIES=y CONFIG_NET_IPVTI=y CONFIG_INET_AH=y @@ -230,7 +229,6 @@ CONFIG_NET_CLS_FW=y CONFIG_NET_CLS_U32=y CONFIG_CLS_U32_MARK=y CONFIG_NET_CLS_FLOW=y -CONFIG_NET_CLS_BPF=y CONFIG_NET_EMATCH=y CONFIG_NET_EMATCH_CMP=y CONFIG_NET_EMATCH_NBYTE=y @@ -260,7 +258,6 @@ CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y CONFIG_ZRAM=y CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_LOOP_MIN_COUNT=16 CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_HDCP_QSEECOM=y @@ -302,13 +299,11 @@ CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=y CONFIG_PPP_MULTILINK=y CONFIG_PPPOE=y -CONFIG_PPTP=y CONFIG_PPPOL2TP=y CONFIG_PPPOLAC=y CONFIG_PPPOPNS=y CONFIG_PPP_ASYNC=y CONFIG_PPP_SYNC_TTY=y -CONFIG_USB_RTL8152=y CONFIG_USB_USBNET=y CONFIG_WIL6210=m CONFIG_WCNSS_MEM_PRE_ALLOC=y @@ -348,7 +343,6 @@ CONFIG_INPUT_UINPUT=y # CONFIG_DEVMEM is not set CONFIG_SERIAL_MSM_GENI=y CONFIG_SERIAL_MSM_GENI_CONSOLE=y -CONFIG_SERIAL_MSM_WITH_HALF_SAMPLING=y CONFIG_SERIAL_DEV_BUS=y CONFIG_TTY_PRINTK=y CONFIG_HW_RANDOM=y @@ -373,6 +367,7 @@ CONFIG_SLIMBUS_MSM_NGD=y CONFIG_PTP_1588_CLOCK=y CONFIG_PINCTRL_SX150X=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_PINCTRL_SDMMAGPIE=y CONFIG_PINCTRL_ATOLL=y CONFIG_PINCTRL_SLPI=y CONFIG_GPIO_SYSFS=y @@ -396,16 +391,15 @@ CONFIG_QTI_THERMAL_LIMITS_DCVS=y CONFIG_QTI_VIRTUAL_SENSOR=y CONFIG_QTI_AOP_REG_COOLING_DEVICE=y CONFIG_QTI_QMI_COOLING_DEVICE=y -CONFIG_QTI_QMI_SENSOR=y CONFIG_REGULATOR_COOLING_DEVICE=y CONFIG_QTI_BCL_PMIC5=y CONFIG_QTI_BCL_SOC_DRIVER=y CONFIG_QTI_ADC_TM=y +CONFIG_QTI_CX_IPEAK_COOLING_DEVICE=y CONFIG_MFD_I2C_PMIC=y CONFIG_MFD_SPMI_PMIC=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_PROXY_CONSUMER=y -CONFIG_REGULATOR_PM8008=y CONFIG_REGULATOR_QPNP_AMOLED=y CONFIG_REGULATOR_QPNP_LCDB=y CONFIG_REGULATOR_REFGEN=y @@ -574,12 +568,6 @@ CONFIG_MSM_VIDEOCC_SDMMAGPIE=y CONFIG_MSM_NPUCC_SDMMAGPIE=y CONFIG_MSM_GPUCC_SDMMAGPIE=y CONFIG_MSM_DEBUGCC_SDMMAGPIE=y -CONFIG_SM_GCC_ATOLL=y -CONFIG_SM_CAMCC_ATOLL=y -CONFIG_SM_VIDEOCC_ATOLL=y -CONFIG_SM_DISPCC_ATOLL=y -CONFIG_SM_NPUCC_ATOLL=y -CONFIG_SM_DEBUGCC_ATOLL=y CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y CONFIG_QCOM_APCS_IPC=y @@ -596,6 +584,8 @@ CONFIG_RPMSG_QCOM_GLINK_SPI=y CONFIG_QCOM_CPUSS_DUMP=y CONFIG_QCOM_RUN_QUEUE_STATS=y CONFIG_QCOM_LLCC=y +CONFIG_QCOM_SM6150_LLCC=y +CONFIG_QCOM_SDMMAGPIE_LLCC=y CONFIG_QCOM_ATOLL_LLCC=y CONFIG_QCOM_LLCC_PERFMON=m CONFIG_QCOM_QMI_HELPERS=y @@ -693,7 +683,6 @@ CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y CONFIG_QFMT_V2=y CONFIG_FUSE_FS=y -CONFIG_OVERLAY_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS_POSIX_ACL=y diff --git a/arch/arm64/configs/vendor/qcs403_defconfig b/arch/arm64/configs/vendor/qcs403_defconfig deleted file mode 100644 index c859d4b29da2..000000000000 --- a/arch/arm64/configs/vendor/qcs403_defconfig +++ /dev/null @@ -1,604 +0,0 @@ -CONFIG_POSIX_MQUEUE=y -CONFIG_AUDIT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_SCHED_WALT=y -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_RCU_EXPERT=y -CONFIG_RCU_FAST_NO_HZ=y -CONFIG_RCU_NOCB_CPU=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_CGROUPS=y -CONFIG_CGROUP_SCHED=y -CONFIG_RT_GROUP_SCHED=y -CONFIG_CGROUP_FREEZER=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_DEBUG=y -CONFIG_NAMESPACES=y -# CONFIG_UTS_NS is not set -# CONFIG_PID_NS is not set -CONFIG_DEFAULT_USE_ENERGY_AWARE=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_KALLSYMS_ALL=y -CONFIG_EMBEDDED=y -CONFIG_SLAB_FREELIST_HARDENED=y -CONFIG_PROFILING=y -CONFIG_CC_STACKPROTECTOR_STRONG=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SIG=y -CONFIG_MODULE_SIG_FORCE=y -CONFIG_MODULE_SIG_SHA512=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_ARCH_QCOM=y -CONFIG_ARCH_QCS403=y -CONFIG_PCI=y -CONFIG_PCI_MSM=y -CONFIG_PCI_MSM_MSI=y -CONFIG_NR_CPUS=4 -CONFIG_PREEMPT=y -CONFIG_CLEANCACHE=y -CONFIG_CMA=y -CONFIG_CMA_DEBUGFS=y -CONFIG_ZSMALLOC=y -CONFIG_SECCOMP=y -# CONFIG_HARDEN_BRANCH_PREDICTOR is not set -CONFIG_ARMV8_DEPRECATED=y -CONFIG_SWP_EMULATION=y -CONFIG_CP15_BARRIER_EMULATION=y -CONFIG_SETEND_EMULATION=y -CONFIG_ARM64_SW_TTBR0_PAN=y -CONFIG_RANDOMIZE_BASE=y -CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_COMPAT=y -CONFIG_PM_AUTOSLEEP=y -CONFIG_PM_WAKELOCKS=y -CONFIG_PM_WAKELOCKS_LIMIT=0 -# CONFIG_PM_WAKELOCKS_GC is not set -CONFIG_PM_DEBUG=y -CONFIG_CPU_IDLE=y -CONFIG_ARM_CPUIDLE=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_MSM=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=y -CONFIG_XFRM_STATISTICS=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_INET_AH=y -CONFIG_INET_ESP=y -CONFIG_INET_IPCOMP=y -# CONFIG_INET_XFRM_MODE_BEET is not set -CONFIG_INET_DIAG_DESTROY=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -CONFIG_IPV6_OPTIMISTIC_DAD=y -CONFIG_INET6_AH=y -CONFIG_INET6_ESP=y -CONFIG_INET6_IPCOMP=y -CONFIG_IPV6_MIP6=y -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_NETFILTER=y -CONFIG_NF_CONNTRACK=y -CONFIG_NF_CONNTRACK_SECMARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CONNTRACK_AMANDA=y -CONFIG_NF_CONNTRACK_FTP=y -CONFIG_NF_CONNTRACK_H323=y -CONFIG_NF_CONNTRACK_IRC=y -CONFIG_NF_CONNTRACK_NETBIOS_NS=y -CONFIG_NF_CONNTRACK_PPTP=y -CONFIG_NF_CONNTRACK_SANE=y -CONFIG_NF_CONNTRACK_TFTP=y -CONFIG_NF_CT_NETLINK=y -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y -CONFIG_NETFILTER_XT_TARGET_CONNMARK=y -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y -CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y -CONFIG_NETFILTER_XT_TARGET_LOG=y -CONFIG_NETFILTER_XT_TARGET_MARK=y -CONFIG_NETFILTER_XT_TARGET_NFLOG=y -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y -CONFIG_NETFILTER_XT_TARGET_NOTRACK=y -CONFIG_NETFILTER_XT_TARGET_TEE=y -CONFIG_NETFILTER_XT_TARGET_TPROXY=y -CONFIG_NETFILTER_XT_TARGET_TRACE=y -CONFIG_NETFILTER_XT_TARGET_SECMARK=y -CONFIG_NETFILTER_XT_TARGET_TCPMSS=y -CONFIG_NETFILTER_XT_MATCH_COMMENT=y -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y -CONFIG_NETFILTER_XT_MATCH_CONNMARK=y -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y -CONFIG_NETFILTER_XT_MATCH_DSCP=y -CONFIG_NETFILTER_XT_MATCH_ESP=y -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y -CONFIG_NETFILTER_XT_MATCH_HELPER=y -CONFIG_NETFILTER_XT_MATCH_IPRANGE=y -CONFIG_NETFILTER_XT_MATCH_LENGTH=y -CONFIG_NETFILTER_XT_MATCH_LIMIT=y -CONFIG_NETFILTER_XT_MATCH_MAC=y -CONFIG_NETFILTER_XT_MATCH_MARK=y -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y -CONFIG_NETFILTER_XT_MATCH_POLICY=y -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y -CONFIG_NETFILTER_XT_MATCH_QUOTA=y -CONFIG_NETFILTER_XT_MATCH_QUOTA2=y -CONFIG_NETFILTER_XT_MATCH_STATE=y -CONFIG_NETFILTER_XT_MATCH_STATISTIC=y -CONFIG_NETFILTER_XT_MATCH_STRING=y -CONFIG_NETFILTER_XT_MATCH_TIME=y -CONFIG_NETFILTER_XT_MATCH_U32=y -CONFIG_NF_CONNTRACK_IPV4=y -CONFIG_IP_NF_IPTABLES=y -CONFIG_IP_NF_MATCH_AH=y -CONFIG_IP_NF_MATCH_ECN=y -CONFIG_IP_NF_MATCH_RPFILTER=y -CONFIG_IP_NF_MATCH_TTL=y -CONFIG_IP_NF_FILTER=y -CONFIG_IP_NF_TARGET_REJECT=y -CONFIG_IP_NF_NAT=y -CONFIG_IP_NF_TARGET_MASQUERADE=y -CONFIG_IP_NF_TARGET_NETMAP=y -CONFIG_IP_NF_TARGET_REDIRECT=y -CONFIG_IP_NF_MANGLE=y -CONFIG_IP_NF_RAW=y -CONFIG_IP_NF_SECURITY=y -CONFIG_IP_NF_ARPTABLES=y -CONFIG_IP_NF_ARPFILTER=y -CONFIG_IP_NF_ARP_MANGLE=y -CONFIG_NF_CONNTRACK_IPV6=y -CONFIG_IP6_NF_IPTABLES=y -CONFIG_IP6_NF_MATCH_RPFILTER=y -CONFIG_IP6_NF_FILTER=y -CONFIG_IP6_NF_TARGET_REJECT=y -CONFIG_IP6_NF_MANGLE=y -CONFIG_IP6_NF_RAW=y -CONFIG_BRIDGE_NF_EBTABLES=y -CONFIG_BRIDGE_EBT_BROUTE=y -CONFIG_BRIDGE_EBT_T_FILTER=y -CONFIG_BRIDGE_EBT_T_NAT=y -CONFIG_BRIDGE_EBT_ARP=y -CONFIG_BRIDGE_EBT_IP=y -CONFIG_BRIDGE_EBT_IP6=y -CONFIG_BRIDGE_EBT_ARPREPLY=y -CONFIG_BRIDGE_EBT_DNAT=y -CONFIG_BRIDGE_EBT_SNAT=y -CONFIG_L2TP=y -CONFIG_L2TP_DEBUGFS=y -CONFIG_L2TP_V3=y -CONFIG_L2TP_IP=y -CONFIG_L2TP_ETH=y -CONFIG_BRIDGE=y -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_HTB=y -CONFIG_NET_SCH_PRIO=y -CONFIG_NET_CLS_FW=y -CONFIG_NET_CLS_U32=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_FLOW=y -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=y -CONFIG_NET_EMATCH_NBYTE=y -CONFIG_NET_EMATCH_U32=y -CONFIG_NET_EMATCH_META=y -CONFIG_NET_EMATCH_TEXT=y -CONFIG_NET_CLS_ACT=y -CONFIG_QRTR=y -CONFIG_QRTR_SMD=y -CONFIG_QRTR_USB=y -CONFIG_RMNET_USB=y -CONFIG_BT=y -# CONFIG_BT_BREDR is not set -# CONFIG_BT_LE is not set -# CONFIG_BT_DEBUGFS is not set -CONFIG_MSM_BT_POWER=y -CONFIG_CFG80211=y -CONFIG_CFG80211_INTERNAL_REGDB=y -CONFIG_MAC80211=m -CONFIG_MAC80211_RC_MINSTREL_VHT=y -CONFIG_MAC80211_DEBUGFS=y -CONFIG_RFKILL=y -CONFIG_NTAG_NQ=y -CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y -CONFIG_DMA_CMA=y -CONFIG_MHI_BUS=y -CONFIG_MHI_DEBUG=y -CONFIG_MHI_QCOM=y -CONFIG_MHI_NETDEV=y -CONFIG_MHI_UCI=y -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_MSM_QPIC_NAND=y -CONFIG_MTD_NAND=y -CONFIG_MTD_UBI=y -CONFIG_ZRAM=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_QSEECOM=y -CONFIG_UID_SYS_STATS=y -CONFIG_QPNP_MISC=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -CONFIG_CHR_DEV_SCH=y -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_SCSI_UFSHCD=y -CONFIG_SCSI_UFSHCD_PLATFORM=y -CONFIG_SCSI_UFS_QCOM=y -CONFIG_SCSI_UFSHCD_CMD_LOGGING=y -CONFIG_MD=y -CONFIG_BLK_DEV_DM=y -CONFIG_DM_CRYPT=y -CONFIG_DM_VERITY=y -CONFIG_DM_VERITY_FEC=y -CONFIG_NETDEVICES=y -CONFIG_DUMMY=y -CONFIG_TUN=y -CONFIG_AT803X_PHY=y -CONFIG_PPP=y -CONFIG_PPP_BSDCOMP=y -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=y -CONFIG_PPP_MULTILINK=y -CONFIG_PPPOE=y -CONFIG_PPPOL2TP=y -CONFIG_PPPOLAC=y -CONFIG_PPPOPNS=y -CONFIG_PPP_ASYNC=y -CONFIG_PPP_SYNC_TTY=y -CONFIG_USB_USBNET=y -CONFIG_USB_NET_SMSC75XX=y -CONFIG_ATH10K=m -CONFIG_ATH10K_PCI=m -CONFIG_ATH10K_DEBUG=y -CONFIG_ATH10K_DEBUGFS=y -CONFIG_WCNSS_MEM_PRE_ALLOC=y -CONFIG_CLD_LL_CORE=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_EVBUG=m -CONFIG_INPUT_KEYRESET=y -CONFIG_KEYBOARD_GPIO=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_JOYSTICK=y -CONFIG_JOYSTICK_XPAD=y -CONFIG_INPUT_TABLET=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ATMEL_MXT=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_HBTP_INPUT=y -CONFIG_INPUT_QPNP_POWER_ON=y -CONFIG_INPUT_UINPUT=y -CONFIG_INPUT_GPIO=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_DEVMEM is not set -CONFIG_SERIAL_MSM=y -CONFIG_SERIAL_MSM_CONSOLE=y -CONFIG_SERIAL_MSM_HS=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MSM_LEGACY=y -CONFIG_DIAG_CHAR=y -CONFIG_MSM_ADSPRPC=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MSM_V2=y -CONFIG_SPI=y -CONFIG_SPI_DEBUG=y -CONFIG_SPI_QUP=y -CONFIG_SPI_SPIDEV=y -CONFIG_SPMI=y -CONFIG_SPMI_MSM_PMIC_ARB_DEBUG=y -CONFIG_SLIMBUS_MSM_NGD=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PINCTRL_QCS405=y -CONFIG_FRAGMENTED_GPIO_ADDRESS_SPACE=y -CONFIG_PINCTRL_QCOM_SPMI_PMIC=y -CONFIG_GPIO_SYSFS=y -CONFIG_POWER_RESET_QCOM=y -CONFIG_QCOM_DLOAD_MODE=y -CONFIG_SMB1351_USB_CHARGER=y -CONFIG_THERMAL=y -CONFIG_THERMAL_WRITABLE_TRIPS=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_GOV_LOW_LIMITS=y -CONFIG_CPU_THERMAL=y -CONFIG_DEVFREQ_THERMAL=y -CONFIG_QCOM_SPMI_TEMP_ALARM=y -CONFIG_THERMAL_TSENS=y -CONFIG_QTI_VIRTUAL_SENSOR=y -CONFIG_QTI_QMI_COOLING_DEVICE=y -CONFIG_REGULATOR_COOLING_DEVICE=y -CONFIG_QTI_ADC_TM=y -CONFIG_QTI_RPM_SMD_COOLING_DEVICE=y -CONFIG_MFD_SPMI_PMIC=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_FAN53555=y -CONFIG_REGULATOR_CPR=y -CONFIG_REGULATOR_MEM_ACC=y -CONFIG_REGULATOR_RPM_SMD=y -CONFIG_REGULATOR_SPM=y -CONFIG_REGULATOR_STUB=y -CONFIG_RC_DEVICES=y -CONFIG_IR_MSM_GENI=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_RADIO_SUPPORT=y -CONFIG_MEDIA_CONTROLLER=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_SOC_CAMERA=y -CONFIG_SOC_CAMERA_PLATFORM=y -CONFIG_FB=y -CONFIG_FB_MSM=y -CONFIG_FB_MSM_MDSS=y -CONFIG_FB_MSM_MDSS_WRITEBACK=y -CONFIG_FB_MSM_MDSS_HDMI_PANEL=y -CONFIG_FB_MSM_MDSS_SPI_PANEL=y -CONFIG_FB_MSM_MDSS_RGB_PANEL=y -CONFIG_FB_MSM_MDSS_DSI_CTRL_STATUS=y -CONFIG_FB_MSM_MDSS_XLOG_DEBUG=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_DYNAMIC_MINORS=y -CONFIG_SND_USB_AUDIO=y -CONFIG_SND_SOC=y -CONFIG_HIDRAW=y -CONFIG_UHID=y -CONFIG_HID_APPLE=y -CONFIG_HID_ELECOM=y -CONFIG_HID_MAGICMOUSE=y -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MULTITOUCH=y -CONFIG_USB_HIDDEV=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_MON=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_ACM=y -CONFIG_USB_STORAGE=y -CONFIG_USB_STORAGE_DATAFAB=y -CONFIG_USB_STORAGE_FREECOM=y -CONFIG_USB_STORAGE_ISD200=y -CONFIG_USB_STORAGE_USBAT=y -CONFIG_USB_STORAGE_SDDR09=y -CONFIG_USB_STORAGE_SDDR55=y -CONFIG_USB_STORAGE_JUMPSHOT=y -CONFIG_USB_STORAGE_ALAUDA=y -CONFIG_USB_STORAGE_KARMA=y -CONFIG_USB_STORAGE_CYPRESS_ATACB=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_MSM=y -CONFIG_USB_SERIAL=y -CONFIG_USB_EHSET_TEST_FIXTURE=y -CONFIG_USB_LINK_LAYER_TEST=y -CONFIG_USB_TYPEC_MUX_NXP5150A=y -CONFIG_USB_QCOM_DIAG_BRIDGE=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_MSM_SNPS_FEMTO_PHY=y -CONFIG_USB_MSM_SSPHY=y -CONFIG_USB_QCOM_EMU_PHY=y -CONFIG_DUAL_ROLE_USB_INTF=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DEBUG_FILES=y -CONFIG_USB_GADGET_DEBUG_FS=y -CONFIG_USB_GADGET_VBUS_DRAW=900 -CONFIG_USB_CONFIGFS=y -CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_USB_CONFIGFS_UEVENT=y -CONFIG_USB_CONFIGFS_F_DIAG=y -CONFIG_MMC=y -CONFIG_MMC_PERF_PROFILING=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_BLOCK_DEFERRED_RESUME=y -CONFIG_MMC_TEST=m -CONFIG_MMC_RING_BUFFER=y -CONFIG_MMC_PARANOID_SD_INIT=y -CONFIG_MMC_CLKGATE=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_MSM=y -CONFIG_MMC_SDHCI_MSM_ICE=y -CONFIG_MMC_CQ_HCI=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_PCA9956B=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_QPNP=y -CONFIG_DMADEVICES=y -CONFIG_QCOM_SPS_DMA=y -CONFIG_UIO=y -CONFIG_STAGING=y -CONFIG_ASHMEM=y -CONFIG_ION=y -CONFIG_QPNP_REVID=y -CONFIG_SPS=y -CONFIG_SPS_SUPPORT_NDP_BAM=y -CONFIG_QCOM_MDSS_PLL=y -CONFIG_QCOM_CLK_SMD_RPM=y -CONFIG_SPMI_PMIC_CLKDIV=y -CONFIG_MDM_DEBUGCC_QCS405=y -CONFIG_CLOCK_CPU_QCS405=y -CONFIG_QCS_CMN_BLK_PLL=y -CONFIG_HWSPINLOCK=y -CONFIG_HWSPINLOCK_QCOM=y -CONFIG_ARM_ARCH_TIMER_VCT_ACCESS=y -CONFIG_MAILBOX=y -CONFIG_QCOM_APCS_IPC=y -CONFIG_ARM_SMMU=y -CONFIG_QCOM_LAZY_MAPPING=y -CONFIG_IOMMU_DEBUG=y -CONFIG_IOMMU_DEBUG_TRACKING=y -CONFIG_IOMMU_TESTS=y -CONFIG_RPMSG_CHAR=y -CONFIG_RPMSG_QCOM_GLINK_RPM=y -CONFIG_RPMSG_QCOM_GLINK_SMEM=y -CONFIG_MSM_RPM_SMD=y -CONFIG_QCOM_CPUSS_DUMP=y -CONFIG_QCOM_QMI_HELPERS=y -CONFIG_QCOM_SMEM=y -CONFIG_QCOM_SMD_RPM=y -CONFIG_MSM_SPM=y -CONFIG_MSM_L2_SPM=y -CONFIG_QCOM_SCM=y -CONFIG_QCOM_MEMORY_DUMP_V2=y -CONFIG_MSM_DEBUG_LAR_UNLOCK=y -CONFIG_QCOM_WATCHDOG_V2=y -CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y -CONFIG_QCOM_WDOG_IPI_ENABLE=y -CONFIG_QCOM_SMP2P=y -CONFIG_MSM_SERVICE_LOCATOR=y -CONFIG_MSM_SERVICE_NOTIFIER=y -CONFIG_MSM_SUBSYSTEM_RESTART=y -CONFIG_MSM_PIL=y -CONFIG_MSM_SYSMON_QMI_COMM=y -CONFIG_MSM_PIL_SSR_GENERIC=y -CONFIG_MSM_BOOT_STATS=y -CONFIG_MSM_CORE_HANG_DETECT=y -CONFIG_QCOM_DCC_V2=y -CONFIG_ICNSS=y -CONFIG_ICNSS_DEBUG=y -CONFIG_ICNSS_QMI=y -CONFIG_QCOM_BUS_SCALING=y -CONFIG_MSM_TZ_SMMU=y -CONFIG_QCOM_GLINK=y -CONFIG_QCOM_GLINK_PKT=y -CONFIG_QTI_RPM_STATS_LOG=y -CONFIG_MSM_CDSP_LOADER=y -CONFIG_QCOM_SMCINVOKE=y -CONFIG_MSM_PM=y -CONFIG_QCOM_SMP2P_SLEEPSTATE=y -CONFIG_QCOM_BIMC_BWMON=y -CONFIG_ARM_MEMLAT_MON=y -CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y -CONFIG_DEVFREQ_GOV_MEMLAT=y -CONFIG_QCOM_DEVFREQ_DEVBW=y -CONFIG_EXTCON_USB_GPIO=y -CONFIG_IIO=y -CONFIG_QCOM_SPMI_ADC5=y -CONFIG_PWM=y -CONFIG_PWM_QTI_LPG=y -CONFIG_QCOM_KGSL=y -CONFIG_QTI_MPM=y -CONFIG_ANDROID=y -CONFIG_ANDROID_BINDER_IPC=y -CONFIG_MSM_TZ_LOG=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT3_FS=y -CONFIG_EXT4_FS_SECURITY=y -CONFIG_QUOTA=y -CONFIG_QUOTA_NETLINK_INTERFACE=y -# CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_QFMT_V2=y -CONFIG_FUSE_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_SQUASHFS=y -CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y -CONFIG_SQUASHFS_XATTR=y -# CONFIG_SQUASHFS_ZLIB is not set -CONFIG_SQUASHFS_XZ=y -CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -CONFIG_PRINTK_TIME=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_DEBUG_INFO=y -CONFIG_PAGE_OWNER=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_PAGEALLOC=y -CONFIG_SLUB_DEBUG_PANIC_ON=y -CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y -CONFIG_PAGE_POISONING=y -CONFIG_PAGE_POISONING_ENABLE_DEFAULT=y -CONFIG_DEBUG_OBJECTS=y -CONFIG_DEBUG_OBJECTS_FREE=y -CONFIG_DEBUG_OBJECTS_TIMERS=y -CONFIG_DEBUG_OBJECTS_WORK=y -CONFIG_DEBUG_OBJECTS_RCU_HEAD=y -CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y -CONFIG_SLUB_DEBUG_ON=y -CONFIG_DEBUG_KMEMLEAK=y -CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=4000 -CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y -CONFIG_DEBUG_STACK_USAGE=y -CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_PANIC_ON_RECURSIVE_FAULT=y -CONFIG_PANIC_ON_OOPS=y -CONFIG_PANIC_TIMEOUT=5 -CONFIG_SCHEDSTATS=y -CONFIG_SCHED_STACK_END_CHECK=y -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_ATOMIC_SLEEP=y -CONFIG_FAULT_INJECTION=y -CONFIG_FAIL_PAGE_ALLOC=y -CONFIG_UFS_FAULT_INJECTION=y -CONFIG_FAULT_INJECTION_DEBUG_FS=y -CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y -CONFIG_IPC_LOGGING=y -CONFIG_QCOM_RTB=y -CONFIG_QCOM_RTB_SEPARATE_CPUS=y -CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_LKDTM=y -CONFIG_BUG_ON_DATA_CORRUPTION=y -CONFIG_CORESIGHT=y -CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y -CONFIG_CORESIGHT_SOURCE_ETM4X=y -CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y -CONFIG_CORESIGHT_STM=y -CONFIG_CORESIGHT_CTI=y -CONFIG_CORESIGHT_TPDA=y -CONFIG_CORESIGHT_TPDM=y -CONFIG_CORESIGHT_HWEVENT=y -CONFIG_CORESIGHT_DUMMY=y -CONFIG_CORESIGHT_REMOTE_ETM=y -CONFIG_CORESIGHT_REMOTE_ETM_DEFAULT_ENABLE=0 -CONFIG_CORESIGHT_EVENT=y -CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y -CONFIG_SECURITY=y -CONFIG_SECURITY_NETWORK=y -CONFIG_LSM_MMAP_MIN_ADDR=4096 -CONFIG_HARDENED_USERCOPY=y -CONFIG_HARDENED_USERCOPY_PAGESPAN=y -CONFIG_SECURITY_SELINUX=y -CONFIG_CRYPTO_CTR=y -CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y -CONFIG_CRYPTO_DEV_QCRYPTO=y -CONFIG_CRYPTO_DEV_QCEDEV=y -CONFIG_CRYPTO_DEV_QCOM_ICE=y diff --git a/arch/arm64/configs/vendor/qcs405-perf_defconfig b/arch/arm64/configs/vendor/qcs405-perf_defconfig index d400e57f2f5e..08d8d66b6353 100644 --- a/arch/arm64/configs/vendor/qcs405-perf_defconfig +++ b/arch/arm64/configs/vendor/qcs405-perf_defconfig @@ -200,6 +200,8 @@ CONFIG_NET_EMATCH_TEXT=y CONFIG_NET_CLS_ACT=y CONFIG_QRTR=y CONFIG_QRTR_SMD=y +CONFIG_QRTR_USB=y +CONFIG_RMNET_USB=y CONFIG_BT=y # CONFIG_BT_BREDR is not set # CONFIG_BT_LE is not set @@ -214,6 +216,10 @@ CONFIG_RFKILL=y CONFIG_NTAG_NQ=y CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y +CONFIG_MHI_BUS=y +CONFIG_MHI_QCOM=y +CONFIG_MHI_NETDEV=y +CONFIG_MHI_UCI=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y @@ -267,9 +273,6 @@ CONFIG_ATH10K_DEBUG=y CONFIG_ATH10K_DEBUGFS=y CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_CLD_LL_CORE=y -CONFIG_CNSS=y -CONFIG_CNSS_SDIO=y -CONFIG_CLD_HL_SDIO_CORE=y CONFIG_INPUT_EVDEV=y CONFIG_INPUT_EVBUG=m CONFIG_INPUT_KEYRESET=y @@ -384,6 +387,7 @@ CONFIG_USB_SERIAL=y CONFIG_USB_EHSET_TEST_FIXTURE=y CONFIG_USB_LINK_LAYER_TEST=y CONFIG_USB_TYPEC_MUX_NXP5150A=y +CONFIG_USB_QCOM_DIAG_BRIDGE=y CONFIG_NOP_USB_XCEIV=y CONFIG_MSM_SNPS_FEMTO_PHY=y CONFIG_USB_MSM_SSPHY=y diff --git a/arch/arm64/configs/vendor/qcs405_defconfig b/arch/arm64/configs/vendor/qcs405_defconfig index 7a0a543823c4..61e6f160b519 100644 --- a/arch/arm64/configs/vendor/qcs405_defconfig +++ b/arch/arm64/configs/vendor/qcs405_defconfig @@ -206,6 +206,8 @@ CONFIG_NET_EMATCH_TEXT=y CONFIG_NET_CLS_ACT=y CONFIG_QRTR=y CONFIG_QRTR_SMD=y +CONFIG_QRTR_USB=y +CONFIG_RMNET_USB=y CONFIG_BT=y # CONFIG_BT_BREDR is not set # CONFIG_BT_LE is not set @@ -220,6 +222,11 @@ CONFIG_RFKILL=y CONFIG_NTAG_NQ=y CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y +CONFIG_MHI_BUS=y +CONFIG_MHI_DEBUG=y +CONFIG_MHI_QCOM=y +CONFIG_MHI_NETDEV=y +CONFIG_MHI_UCI=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y @@ -273,9 +280,6 @@ CONFIG_ATH10K_DEBUG=y CONFIG_ATH10K_DEBUGFS=y CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_CLD_LL_CORE=y -CONFIG_CNSS=y -CONFIG_CNSS_SDIO=y -CONFIG_CLD_HL_SDIO_CORE=y CONFIG_INPUT_EVDEV=y CONFIG_INPUT_EVBUG=m CONFIG_INPUT_KEYRESET=y @@ -394,6 +398,7 @@ CONFIG_USB_SERIAL=y CONFIG_USB_EHSET_TEST_FIXTURE=y CONFIG_USB_LINK_LAYER_TEST=y CONFIG_USB_TYPEC_MUX_NXP5150A=y +CONFIG_USB_QCOM_DIAG_BRIDGE=y CONFIG_NOP_USB_XCEIV=y CONFIG_MSM_SNPS_FEMTO_PHY=y CONFIG_USB_MSM_SSPHY=y diff --git a/arch/arm64/configs/vendor/qti-quin-gvm-perf_defconfig b/arch/arm64/configs/vendor/qti-quin-gvm-perf_defconfig index 43f066057da5..1c21491ae274 100644 --- a/arch/arm64/configs/vendor/qti-quin-gvm-perf_defconfig +++ b/arch/arm64/configs/vendor/qti-quin-gvm-perf_defconfig @@ -308,9 +308,7 @@ CONFIG_SPI=y CONFIG_SPI_QCOM_GENI=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y -CONFIG_PTP_1588_CLOCK=y CONFIG_PINCTRL_SX150X=y -CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_SM8150=y CONFIG_PINCTRL_SDMSHRIKE=y CONFIG_PINCTRL_SM6150=y @@ -324,13 +322,11 @@ CONFIG_THERMAL=y CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THERMAL_GOV_USER_SPACE=y CONFIG_THERMAL_GOV_LOW_LIMITS=y -CONFIG_MFD_SPMI_PMIC=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_PROXY_CONSUMER=y CONFIG_REGULATOR_REFGEN=y CONFIG_REGULATOR_STUB=y -CONFIG_VIRTIO_REGULATOR=y CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_CONTROLLER=y diff --git a/arch/arm64/configs/vendor/qti-quin-gvm_defconfig b/arch/arm64/configs/vendor/qti-quin-gvm_defconfig index 42e89099a103..0ab5f39e47ad 100644 --- a/arch/arm64/configs/vendor/qti-quin-gvm_defconfig +++ b/arch/arm64/configs/vendor/qti-quin-gvm_defconfig @@ -320,9 +320,7 @@ CONFIG_SPI=y CONFIG_SPI_QCOM_GENI=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y -CONFIG_PTP_1588_CLOCK=y CONFIG_PINCTRL_SX150X=y -CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_SM8150=y CONFIG_PINCTRL_SDMSHRIKE=y CONFIG_PINCTRL_SM6150=y @@ -336,13 +334,11 @@ CONFIG_THERMAL=y CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THERMAL_GOV_USER_SPACE=y CONFIG_THERMAL_GOV_LOW_LIMITS=y -CONFIG_MFD_SPMI_PMIC=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_PROXY_CONSUMER=y CONFIG_REGULATOR_REFGEN=y CONFIG_REGULATOR_STUB=y -CONFIG_VIRTIO_REGULATOR=y CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_CONTROLLER=y diff --git a/arch/arm64/configs/vendor/sa2150p-perf_defconfig b/arch/arm64/configs/vendor/sa2150p-perf_defconfig deleted file mode 100644 index 763c76f69500..000000000000 --- a/arch/arm64/configs/vendor/sa2150p-perf_defconfig +++ /dev/null @@ -1,558 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_AUDIT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_SCHED_WALT=y -CONFIG_TASKSTATS=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_RCU_EXPERT=y -CONFIG_RCU_FAST_NO_HZ=y -CONFIG_RCU_NOCB_CPU=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_CGROUPS=y -CONFIG_CGROUP_SCHED=y -CONFIG_RT_GROUP_SCHED=y -CONFIG_CGROUP_FREEZER=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_NAMESPACES=y -# CONFIG_UTS_NS is not set -# CONFIG_PID_NS is not set -CONFIG_DEFAULT_USE_ENERGY_AWARE=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_KALLSYMS_ALL=y -CONFIG_EMBEDDED=y -CONFIG_SLAB_FREELIST_HARDENED=y -CONFIG_PROFILING=y -CONFIG_CC_STACKPROTECTOR_STRONG=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SIG=y -CONFIG_MODULE_SIG_FORCE=y -CONFIG_MODULE_SIG_SHA512=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_ARCH_QCOM=y -CONFIG_ARCH_QCS405=y -CONFIG_PCI=y -CONFIG_PCI_MSM=y -CONFIG_PCI_MSM_MSI=y -CONFIG_NR_CPUS=4 -CONFIG_PREEMPT=y -CONFIG_CMA=y -CONFIG_ZSMALLOC=y -CONFIG_SECCOMP=y -# CONFIG_HARDEN_BRANCH_PREDICTOR is not set -CONFIG_ARMV8_DEPRECATED=y -CONFIG_SWP_EMULATION=y -CONFIG_CP15_BARRIER_EMULATION=y -CONFIG_SETEND_EMULATION=y -CONFIG_ARM64_SW_TTBR0_PAN=y -CONFIG_RANDOMIZE_BASE=y -CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_COMPAT=y -CONFIG_PM_AUTOSLEEP=y -CONFIG_PM_WAKELOCKS=y -CONFIG_PM_WAKELOCKS_LIMIT=0 -# CONFIG_PM_WAKELOCKS_GC is not set -CONFIG_CPU_IDLE=y -CONFIG_ARM_CPUIDLE=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_MSM=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=y -CONFIG_XFRM_STATISTICS=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_INET_AH=y -CONFIG_INET_ESP=y -CONFIG_INET_IPCOMP=y -# CONFIG_INET_XFRM_MODE_BEET is not set -CONFIG_INET_DIAG_DESTROY=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -CONFIG_IPV6_OPTIMISTIC_DAD=y -CONFIG_INET6_AH=y -CONFIG_INET6_ESP=y -CONFIG_INET6_IPCOMP=y -CONFIG_IPV6_MIP6=y -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_NETFILTER=y -CONFIG_NF_CONNTRACK=y -CONFIG_NF_CONNTRACK_SECMARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CONNTRACK_AMANDA=y -CONFIG_NF_CONNTRACK_FTP=y -CONFIG_NF_CONNTRACK_H323=y -CONFIG_NF_CONNTRACK_IRC=y -CONFIG_NF_CONNTRACK_NETBIOS_NS=y -CONFIG_NF_CONNTRACK_PPTP=y -CONFIG_NF_CONNTRACK_SANE=y -CONFIG_NF_CONNTRACK_TFTP=y -CONFIG_NF_CT_NETLINK=y -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y -CONFIG_NETFILTER_XT_TARGET_CONNMARK=y -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y -CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y -CONFIG_NETFILTER_XT_TARGET_LOG=y -CONFIG_NETFILTER_XT_TARGET_MARK=y -CONFIG_NETFILTER_XT_TARGET_NFLOG=y -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y -CONFIG_NETFILTER_XT_TARGET_NOTRACK=y -CONFIG_NETFILTER_XT_TARGET_TEE=y -CONFIG_NETFILTER_XT_TARGET_TPROXY=y -CONFIG_NETFILTER_XT_TARGET_TRACE=y -CONFIG_NETFILTER_XT_TARGET_SECMARK=y -CONFIG_NETFILTER_XT_TARGET_TCPMSS=y -CONFIG_NETFILTER_XT_MATCH_COMMENT=y -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y -CONFIG_NETFILTER_XT_MATCH_CONNMARK=y -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y -CONFIG_NETFILTER_XT_MATCH_DSCP=y -CONFIG_NETFILTER_XT_MATCH_ESP=y -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y -CONFIG_NETFILTER_XT_MATCH_HELPER=y -CONFIG_NETFILTER_XT_MATCH_IPRANGE=y -CONFIG_NETFILTER_XT_MATCH_LENGTH=y -CONFIG_NETFILTER_XT_MATCH_LIMIT=y -CONFIG_NETFILTER_XT_MATCH_MAC=y -CONFIG_NETFILTER_XT_MATCH_MARK=y -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y -CONFIG_NETFILTER_XT_MATCH_POLICY=y -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y -CONFIG_NETFILTER_XT_MATCH_QUOTA=y -CONFIG_NETFILTER_XT_MATCH_QUOTA2=y -CONFIG_NETFILTER_XT_MATCH_STATE=y -CONFIG_NETFILTER_XT_MATCH_STATISTIC=y -CONFIG_NETFILTER_XT_MATCH_STRING=y -CONFIG_NETFILTER_XT_MATCH_TIME=y -CONFIG_NETFILTER_XT_MATCH_U32=y -CONFIG_NF_CONNTRACK_IPV4=y -CONFIG_IP_NF_IPTABLES=y -CONFIG_IP_NF_MATCH_AH=y -CONFIG_IP_NF_MATCH_ECN=y -CONFIG_IP_NF_MATCH_RPFILTER=y -CONFIG_IP_NF_MATCH_TTL=y -CONFIG_IP_NF_FILTER=y -CONFIG_IP_NF_TARGET_REJECT=y -CONFIG_IP_NF_NAT=y -CONFIG_IP_NF_TARGET_MASQUERADE=y -CONFIG_IP_NF_TARGET_NETMAP=y -CONFIG_IP_NF_TARGET_REDIRECT=y -CONFIG_IP_NF_MANGLE=y -CONFIG_IP_NF_RAW=y -CONFIG_IP_NF_SECURITY=y -CONFIG_IP_NF_ARPTABLES=y -CONFIG_IP_NF_ARPFILTER=y -CONFIG_IP_NF_ARP_MANGLE=y -CONFIG_NF_CONNTRACK_IPV6=y -CONFIG_IP6_NF_IPTABLES=y -CONFIG_IP6_NF_MATCH_RPFILTER=y -CONFIG_IP6_NF_FILTER=y -CONFIG_IP6_NF_TARGET_REJECT=y -CONFIG_IP6_NF_MANGLE=y -CONFIG_IP6_NF_RAW=y -CONFIG_BRIDGE_NF_EBTABLES=y -CONFIG_BRIDGE_EBT_BROUTE=y -CONFIG_BRIDGE_EBT_T_FILTER=y -CONFIG_BRIDGE_EBT_T_NAT=y -CONFIG_BRIDGE_EBT_ARP=y -CONFIG_BRIDGE_EBT_IP=y -CONFIG_BRIDGE_EBT_IP6=y -CONFIG_BRIDGE_EBT_ARPREPLY=y -CONFIG_BRIDGE_EBT_DNAT=y -CONFIG_BRIDGE_EBT_SNAT=y -CONFIG_L2TP=y -CONFIG_L2TP_V3=y -CONFIG_L2TP_IP=y -CONFIG_L2TP_ETH=y -CONFIG_BRIDGE=y -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_HTB=y -CONFIG_NET_SCH_PRIO=y -CONFIG_NET_CLS_FW=y -CONFIG_NET_CLS_U32=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_FLOW=y -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=y -CONFIG_NET_EMATCH_NBYTE=y -CONFIG_NET_EMATCH_U32=y -CONFIG_NET_EMATCH_META=y -CONFIG_NET_EMATCH_TEXT=y -CONFIG_NET_CLS_ACT=y -CONFIG_QRTR=y -CONFIG_QRTR_SMD=y -CONFIG_QRTR_USB=y -CONFIG_RMNET_USB=y -CONFIG_BT=y -# CONFIG_BT_BREDR is not set -# CONFIG_BT_LE is not set -# CONFIG_BT_DEBUGFS is not set -CONFIG_MSM_BT_POWER=y -CONFIG_CFG80211=y -CONFIG_CFG80211_INTERNAL_REGDB=y -CONFIG_MAC80211=m -CONFIG_MAC80211_RC_MINSTREL_VHT=y -CONFIG_MAC80211_DEBUGFS=y -CONFIG_RFKILL=y -CONFIG_NTAG_NQ=y -CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y -CONFIG_DMA_CMA=y -CONFIG_MHI_BUS=y -CONFIG_MHI_QCOM=y -CONFIG_MHI_NETDEV=y -CONFIG_MHI_UCI=y -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_MSM_QPIC_NAND=y -CONFIG_MTD_NAND=y -CONFIG_MTD_UBI=y -CONFIG_ZRAM=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_QSEECOM=y -CONFIG_UID_SYS_STATS=y -CONFIG_QPNP_MISC=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -CONFIG_CHR_DEV_SCH=y -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_SCSI_UFSHCD=y -CONFIG_SCSI_UFSHCD_PLATFORM=y -CONFIG_SCSI_UFS_QCOM=y -CONFIG_SCSI_UFSHCD_CMD_LOGGING=y -CONFIG_MD=y -CONFIG_BLK_DEV_DM=y -CONFIG_DM_CRYPT=y -CONFIG_DM_VERITY=y -CONFIG_DM_VERITY_FEC=y -CONFIG_NETDEVICES=y -CONFIG_DUMMY=y -CONFIG_TUN=y -CONFIG_AT803X_PHY=y -CONFIG_PPP=y -CONFIG_PPP_BSDCOMP=y -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=y -CONFIG_PPP_MULTILINK=y -CONFIG_PPPOE=y -CONFIG_PPPOL2TP=y -CONFIG_PPPOLAC=y -CONFIG_PPPOPNS=y -CONFIG_PPP_ASYNC=y -CONFIG_PPP_SYNC_TTY=y -CONFIG_USB_USBNET=y -CONFIG_USB_NET_SMSC75XX=y -CONFIG_ATH10K=m -CONFIG_ATH10K_PCI=m -CONFIG_ATH10K_DEBUG=y -CONFIG_ATH10K_DEBUGFS=y -CONFIG_WCNSS_MEM_PRE_ALLOC=y -CONFIG_CLD_LL_CORE=y -CONFIG_CNSS=y -CONFIG_CNSS_SDIO=y -CONFIG_CLD_HL_SDIO_CORE=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_EVBUG=m -CONFIG_INPUT_KEYRESET=y -CONFIG_KEYBOARD_GPIO=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_JOYSTICK=y -CONFIG_JOYSTICK_XPAD=y -CONFIG_INPUT_TABLET=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ATMEL_MXT=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_HBTP_INPUT=y -CONFIG_INPUT_QPNP_POWER_ON=y -CONFIG_INPUT_UINPUT=y -CONFIG_INPUT_GPIO=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_DEVMEM is not set -CONFIG_SERIAL_MSM_HS=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MSM_LEGACY=y -CONFIG_DIAG_CHAR=y -CONFIG_MSM_ADSPRPC=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MSM_V2=y -CONFIG_SPI=y -CONFIG_SPI_QUP=y -CONFIG_SPI_SPIDEV=y -CONFIG_SPMI=y -CONFIG_SLIMBUS_MSM_NGD=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PINCTRL_QCS405=y -CONFIG_FRAGMENTED_GPIO_ADDRESS_SPACE=y -CONFIG_PINCTRL_QCOM_SPMI_PMIC=y -CONFIG_GPIO_SYSFS=y -CONFIG_POWER_RESET_QCOM=y -CONFIG_QCOM_DLOAD_MODE=y -CONFIG_SMB1351_USB_CHARGER=y -CONFIG_THERMAL=y -CONFIG_THERMAL_WRITABLE_TRIPS=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_GOV_LOW_LIMITS=y -CONFIG_CPU_THERMAL=y -CONFIG_DEVFREQ_THERMAL=y -CONFIG_QCOM_SPMI_TEMP_ALARM=y -CONFIG_THERMAL_TSENS=y -CONFIG_QTI_VIRTUAL_SENSOR=y -CONFIG_QTI_QMI_COOLING_DEVICE=y -CONFIG_REGULATOR_COOLING_DEVICE=y -CONFIG_QTI_ADC_TM=y -CONFIG_QTI_RPM_SMD_COOLING_DEVICE=y -CONFIG_MFD_SPMI_PMIC=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_FAN53555=y -CONFIG_REGULATOR_CPR=y -CONFIG_REGULATOR_MEM_ACC=y -CONFIG_REGULATOR_RPM_SMD=y -CONFIG_REGULATOR_SPM=y -CONFIG_REGULATOR_STUB=y -CONFIG_RC_DEVICES=y -CONFIG_IR_MSM_GENI=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_RADIO_SUPPORT=y -CONFIG_MEDIA_CONTROLLER=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_SOC_CAMERA=y -CONFIG_SOC_CAMERA_PLATFORM=y -CONFIG_FB=y -CONFIG_FB_MSM=y -CONFIG_FB_MSM_MDSS=y -CONFIG_FB_MSM_MDSS_WRITEBACK=y -CONFIG_FB_MSM_MDSS_HDMI_PANEL=y -CONFIG_FB_MSM_MDSS_SPI_PANEL=y -CONFIG_FB_MSM_MDSS_RGB_PANEL=y -CONFIG_FB_MSM_MDSS_DSI_CTRL_STATUS=y -CONFIG_FB_MSM_MDSS_XLOG_DEBUG=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_DYNAMIC_MINORS=y -CONFIG_SND_USB_AUDIO=y -CONFIG_SND_SOC=y -CONFIG_HIDRAW=y -CONFIG_UHID=y -CONFIG_HID_APPLE=y -CONFIG_HID_ELECOM=y -CONFIG_HID_MAGICMOUSE=y -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MULTITOUCH=y -CONFIG_USB_HIDDEV=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_MON=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_ACM=y -CONFIG_USB_STORAGE=y -CONFIG_USB_STORAGE_DATAFAB=y -CONFIG_USB_STORAGE_FREECOM=y -CONFIG_USB_STORAGE_ISD200=y -CONFIG_USB_STORAGE_USBAT=y -CONFIG_USB_STORAGE_SDDR09=y -CONFIG_USB_STORAGE_SDDR55=y -CONFIG_USB_STORAGE_JUMPSHOT=y -CONFIG_USB_STORAGE_ALAUDA=y -CONFIG_USB_STORAGE_KARMA=y -CONFIG_USB_STORAGE_CYPRESS_ATACB=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_MSM=y -CONFIG_USB_SERIAL=y -CONFIG_USB_EHSET_TEST_FIXTURE=y -CONFIG_USB_LINK_LAYER_TEST=y -CONFIG_USB_TYPEC_MUX_NXP5150A=y -CONFIG_USB_QCOM_DIAG_BRIDGE=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_MSM_SNPS_FEMTO_PHY=y -CONFIG_USB_MSM_SSPHY=y -CONFIG_USB_QCOM_EMU_PHY=y -CONFIG_DUAL_ROLE_USB_INTF=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_VBUS_DRAW=900 -CONFIG_USB_CONFIGFS=y -CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_USB_CONFIGFS_UEVENT=y -CONFIG_USB_CONFIGFS_F_DIAG=y -CONFIG_MMC=y -CONFIG_MMC_PERF_PROFILING=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_BLOCK_DEFERRED_RESUME=y -CONFIG_MMC_TEST=m -CONFIG_MMC_PARANOID_SD_INIT=y -CONFIG_MMC_CLKGATE=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_MSM=y -CONFIG_MMC_SDHCI_MSM_ICE=y -CONFIG_MMC_CQ_HCI=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_PCA9956B=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_QPNP=y -CONFIG_DMADEVICES=y -CONFIG_QCOM_SPS_DMA=y -CONFIG_UIO=y -CONFIG_STAGING=y -CONFIG_ASHMEM=y -CONFIG_ION=y -CONFIG_QPNP_REVID=y -CONFIG_SPS=y -CONFIG_SPS_SUPPORT_NDP_BAM=y -CONFIG_QCOM_MDSS_PLL=y -CONFIG_QCOM_CLK_SMD_RPM=y -CONFIG_SPMI_PMIC_CLKDIV=y -CONFIG_MDM_DEBUGCC_QCS405=y -CONFIG_CLOCK_CPU_QCS405=y -CONFIG_QCS_CMN_BLK_PLL=y -CONFIG_HWSPINLOCK=y -CONFIG_HWSPINLOCK_QCOM=y -CONFIG_ARM_ARCH_TIMER_VCT_ACCESS=y -CONFIG_MAILBOX=y -CONFIG_QCOM_APCS_IPC=y -CONFIG_ARM_SMMU=y -CONFIG_QCOM_LAZY_MAPPING=y -CONFIG_IOMMU_DEBUG=y -CONFIG_IOMMU_DEBUG_TRACKING=y -CONFIG_RPMSG_CHAR=y -CONFIG_RPMSG_QCOM_GLINK_RPM=y -CONFIG_RPMSG_QCOM_GLINK_SMEM=y -CONFIG_MSM_RPM_SMD=y -CONFIG_QCOM_QMI_HELPERS=y -CONFIG_QCOM_SMEM=y -CONFIG_QCOM_SMD_RPM=y -CONFIG_MSM_SPM=y -CONFIG_MSM_L2_SPM=y -CONFIG_QCOM_SCM=y -CONFIG_QCOM_MEMORY_DUMP_V2=y -CONFIG_QCOM_WATCHDOG_V2=y -CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y -CONFIG_QCOM_WDOG_IPI_ENABLE=y -CONFIG_QCOM_SMP2P=y -CONFIG_MSM_SERVICE_LOCATOR=y -CONFIG_MSM_SERVICE_NOTIFIER=y -CONFIG_MSM_SUBSYSTEM_RESTART=y -CONFIG_MSM_PIL=y -CONFIG_MSM_SYSMON_QMI_COMM=y -CONFIG_MSM_PIL_SSR_GENERIC=y -CONFIG_MSM_BOOT_STATS=y -CONFIG_QCOM_DCC_V2=y -CONFIG_ICNSS=y -CONFIG_ICNSS_QMI=y -CONFIG_QCOM_BUS_SCALING=y -CONFIG_MSM_TZ_SMMU=y -CONFIG_QCOM_GLINK=y -CONFIG_QCOM_GLINK_PKT=y -CONFIG_MSM_JTAGV8=y -CONFIG_QTI_RPM_STATS_LOG=y -CONFIG_MSM_CDSP_LOADER=y -CONFIG_QCOM_SMCINVOKE=y -CONFIG_MSM_PM=y -CONFIG_QCOM_SMP2P_SLEEPSTATE=y -CONFIG_QCOM_BIMC_BWMON=y -CONFIG_ARM_MEMLAT_MON=y -CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y -CONFIG_DEVFREQ_GOV_MEMLAT=y -CONFIG_QCOM_DEVFREQ_DEVBW=y -CONFIG_EXTCON_USB_GPIO=y -CONFIG_IIO=y -CONFIG_QCOM_SPMI_ADC5=y -CONFIG_PWM=y -CONFIG_PWM_QTI_LPG=y -CONFIG_QCOM_KGSL=y -CONFIG_QTI_MPM=y -CONFIG_ANDROID=y -CONFIG_ANDROID_BINDER_IPC=y -CONFIG_MSM_TZ_LOG=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT3_FS=y -CONFIG_EXT4_FS_SECURITY=y -CONFIG_QUOTA=y -CONFIG_QUOTA_NETLINK_INTERFACE=y -# CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_QFMT_V2=y -CONFIG_FUSE_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_SQUASHFS=y -CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y -CONFIG_SQUASHFS_XATTR=y -# CONFIG_SQUASHFS_ZLIB is not set -CONFIG_SQUASHFS_XZ=y -CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_INFO=y -CONFIG_PAGE_OWNER=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_PAGE_POISONING=y -CONFIG_PAGE_POISONING_ENABLE_DEFAULT=y -CONFIG_PANIC_ON_RECURSIVE_FAULT=y -CONFIG_PANIC_ON_OOPS=y -CONFIG_PANIC_TIMEOUT=5 -CONFIG_SCHEDSTATS=y -CONFIG_IPC_LOGGING=y -CONFIG_BUG_ON_DATA_CORRUPTION=y -CONFIG_CORESIGHT=y -CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y -CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y -CONFIG_CORESIGHT_STM=y -CONFIG_CORESIGHT_CTI=y -CONFIG_CORESIGHT_TPDA=y -CONFIG_CORESIGHT_TPDM=y -CONFIG_CORESIGHT_HWEVENT=y -CONFIG_CORESIGHT_DUMMY=y -CONFIG_CORESIGHT_EVENT=y -CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y -CONFIG_SECURITY=y -CONFIG_SECURITY_NETWORK=y -CONFIG_LSM_MMAP_MIN_ADDR=4096 -CONFIG_HARDENED_USERCOPY=y -CONFIG_HARDENED_USERCOPY_PAGESPAN=y -CONFIG_SECURITY_SELINUX=y -CONFIG_CRYPTO_CTR=y -CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y -CONFIG_CRYPTO_DEV_QCRYPTO=y -CONFIG_CRYPTO_DEV_QCEDEV=y -CONFIG_CRYPTO_DEV_QCOM_ICE=y -CONFIG_STACK_HASH_ORDER_SHIFT=12 diff --git a/arch/arm64/configs/vendor/sa2150p_defconfig b/arch/arm64/configs/vendor/sa2150p_defconfig deleted file mode 100644 index f725b5d3683b..000000000000 --- a/arch/arm64/configs/vendor/sa2150p_defconfig +++ /dev/null @@ -1,608 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_AUDIT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_SCHED_WALT=y -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_RCU_EXPERT=y -CONFIG_RCU_FAST_NO_HZ=y -CONFIG_RCU_NOCB_CPU=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_CGROUPS=y -CONFIG_CGROUP_SCHED=y -CONFIG_RT_GROUP_SCHED=y -CONFIG_CGROUP_FREEZER=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_DEBUG=y -CONFIG_NAMESPACES=y -# CONFIG_UTS_NS is not set -# CONFIG_PID_NS is not set -CONFIG_DEFAULT_USE_ENERGY_AWARE=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_KALLSYMS_ALL=y -CONFIG_EMBEDDED=y -CONFIG_SLAB_FREELIST_HARDENED=y -CONFIG_PROFILING=y -CONFIG_CC_STACKPROTECTOR_STRONG=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SIG=y -CONFIG_MODULE_SIG_FORCE=y -CONFIG_MODULE_SIG_SHA512=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_ARCH_QCOM=y -CONFIG_ARCH_QCS405=y -CONFIG_PCI=y -CONFIG_PCI_MSM=y -CONFIG_PCI_MSM_MSI=y -CONFIG_NR_CPUS=4 -CONFIG_PREEMPT=y -CONFIG_CLEANCACHE=y -CONFIG_CMA=y -CONFIG_CMA_DEBUGFS=y -CONFIG_ZSMALLOC=y -CONFIG_SECCOMP=y -# CONFIG_HARDEN_BRANCH_PREDICTOR is not set -CONFIG_ARMV8_DEPRECATED=y -CONFIG_SWP_EMULATION=y -CONFIG_CP15_BARRIER_EMULATION=y -CONFIG_SETEND_EMULATION=y -CONFIG_ARM64_SW_TTBR0_PAN=y -CONFIG_RANDOMIZE_BASE=y -CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_COMPAT=y -CONFIG_PM_AUTOSLEEP=y -CONFIG_PM_WAKELOCKS=y -CONFIG_PM_WAKELOCKS_LIMIT=0 -# CONFIG_PM_WAKELOCKS_GC is not set -CONFIG_PM_DEBUG=y -CONFIG_CPU_IDLE=y -CONFIG_ARM_CPUIDLE=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_MSM=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=y -CONFIG_XFRM_STATISTICS=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_INET_AH=y -CONFIG_INET_ESP=y -CONFIG_INET_IPCOMP=y -# CONFIG_INET_XFRM_MODE_BEET is not set -CONFIG_INET_DIAG_DESTROY=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -CONFIG_IPV6_OPTIMISTIC_DAD=y -CONFIG_INET6_AH=y -CONFIG_INET6_ESP=y -CONFIG_INET6_IPCOMP=y -CONFIG_IPV6_MIP6=y -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_NETFILTER=y -CONFIG_NF_CONNTRACK=y -CONFIG_NF_CONNTRACK_SECMARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CONNTRACK_AMANDA=y -CONFIG_NF_CONNTRACK_FTP=y -CONFIG_NF_CONNTRACK_H323=y -CONFIG_NF_CONNTRACK_IRC=y -CONFIG_NF_CONNTRACK_NETBIOS_NS=y -CONFIG_NF_CONNTRACK_PPTP=y -CONFIG_NF_CONNTRACK_SANE=y -CONFIG_NF_CONNTRACK_TFTP=y -CONFIG_NF_CT_NETLINK=y -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y -CONFIG_NETFILTER_XT_TARGET_CONNMARK=y -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y -CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y -CONFIG_NETFILTER_XT_TARGET_LOG=y -CONFIG_NETFILTER_XT_TARGET_MARK=y -CONFIG_NETFILTER_XT_TARGET_NFLOG=y -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y -CONFIG_NETFILTER_XT_TARGET_NOTRACK=y -CONFIG_NETFILTER_XT_TARGET_TEE=y -CONFIG_NETFILTER_XT_TARGET_TPROXY=y -CONFIG_NETFILTER_XT_TARGET_TRACE=y -CONFIG_NETFILTER_XT_TARGET_SECMARK=y -CONFIG_NETFILTER_XT_TARGET_TCPMSS=y -CONFIG_NETFILTER_XT_MATCH_COMMENT=y -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y -CONFIG_NETFILTER_XT_MATCH_CONNMARK=y -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y -CONFIG_NETFILTER_XT_MATCH_DSCP=y -CONFIG_NETFILTER_XT_MATCH_ESP=y -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y -CONFIG_NETFILTER_XT_MATCH_HELPER=y -CONFIG_NETFILTER_XT_MATCH_IPRANGE=y -CONFIG_NETFILTER_XT_MATCH_LENGTH=y -CONFIG_NETFILTER_XT_MATCH_LIMIT=y -CONFIG_NETFILTER_XT_MATCH_MAC=y -CONFIG_NETFILTER_XT_MATCH_MARK=y -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y -CONFIG_NETFILTER_XT_MATCH_POLICY=y -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y -CONFIG_NETFILTER_XT_MATCH_QUOTA=y -CONFIG_NETFILTER_XT_MATCH_QUOTA2=y -CONFIG_NETFILTER_XT_MATCH_STATE=y -CONFIG_NETFILTER_XT_MATCH_STATISTIC=y -CONFIG_NETFILTER_XT_MATCH_STRING=y -CONFIG_NETFILTER_XT_MATCH_TIME=y -CONFIG_NETFILTER_XT_MATCH_U32=y -CONFIG_NF_CONNTRACK_IPV4=y -CONFIG_IP_NF_IPTABLES=y -CONFIG_IP_NF_MATCH_AH=y -CONFIG_IP_NF_MATCH_ECN=y -CONFIG_IP_NF_MATCH_RPFILTER=y -CONFIG_IP_NF_MATCH_TTL=y -CONFIG_IP_NF_FILTER=y -CONFIG_IP_NF_TARGET_REJECT=y -CONFIG_IP_NF_NAT=y -CONFIG_IP_NF_TARGET_MASQUERADE=y -CONFIG_IP_NF_TARGET_NETMAP=y -CONFIG_IP_NF_TARGET_REDIRECT=y -CONFIG_IP_NF_MANGLE=y -CONFIG_IP_NF_RAW=y -CONFIG_IP_NF_SECURITY=y -CONFIG_IP_NF_ARPTABLES=y -CONFIG_IP_NF_ARPFILTER=y -CONFIG_IP_NF_ARP_MANGLE=y -CONFIG_NF_CONNTRACK_IPV6=y -CONFIG_IP6_NF_IPTABLES=y -CONFIG_IP6_NF_MATCH_RPFILTER=y -CONFIG_IP6_NF_FILTER=y -CONFIG_IP6_NF_TARGET_REJECT=y -CONFIG_IP6_NF_MANGLE=y -CONFIG_IP6_NF_RAW=y -CONFIG_BRIDGE_NF_EBTABLES=y -CONFIG_BRIDGE_EBT_BROUTE=y -CONFIG_BRIDGE_EBT_T_FILTER=y -CONFIG_BRIDGE_EBT_T_NAT=y -CONFIG_BRIDGE_EBT_ARP=y -CONFIG_BRIDGE_EBT_IP=y -CONFIG_BRIDGE_EBT_IP6=y -CONFIG_BRIDGE_EBT_ARPREPLY=y -CONFIG_BRIDGE_EBT_DNAT=y -CONFIG_BRIDGE_EBT_SNAT=y -CONFIG_L2TP=y -CONFIG_L2TP_DEBUGFS=y -CONFIG_L2TP_V3=y -CONFIG_L2TP_IP=y -CONFIG_L2TP_ETH=y -CONFIG_BRIDGE=y -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_HTB=y -CONFIG_NET_SCH_PRIO=y -CONFIG_NET_CLS_FW=y -CONFIG_NET_CLS_U32=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_FLOW=y -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=y -CONFIG_NET_EMATCH_NBYTE=y -CONFIG_NET_EMATCH_U32=y -CONFIG_NET_EMATCH_META=y -CONFIG_NET_EMATCH_TEXT=y -CONFIG_NET_CLS_ACT=y -CONFIG_QRTR=y -CONFIG_QRTR_SMD=y -CONFIG_QRTR_USB=y -CONFIG_RMNET_USB=y -CONFIG_BT=y -# CONFIG_BT_BREDR is not set -# CONFIG_BT_LE is not set -# CONFIG_BT_DEBUGFS is not set -CONFIG_MSM_BT_POWER=y -CONFIG_CFG80211=y -CONFIG_CFG80211_INTERNAL_REGDB=y -CONFIG_MAC80211=m -CONFIG_MAC80211_RC_MINSTREL_VHT=y -CONFIG_MAC80211_DEBUGFS=y -CONFIG_RFKILL=y -CONFIG_NTAG_NQ=y -CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y -CONFIG_DMA_CMA=y -CONFIG_MHI_BUS=y -CONFIG_MHI_DEBUG=y -CONFIG_MHI_QCOM=y -CONFIG_MHI_NETDEV=y -CONFIG_MHI_UCI=y -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_MSM_QPIC_NAND=y -CONFIG_MTD_NAND=y -CONFIG_MTD_UBI=y -CONFIG_ZRAM=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_QSEECOM=y -CONFIG_UID_SYS_STATS=y -CONFIG_QPNP_MISC=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -CONFIG_CHR_DEV_SCH=y -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_SCSI_UFSHCD=y -CONFIG_SCSI_UFSHCD_PLATFORM=y -CONFIG_SCSI_UFS_QCOM=y -CONFIG_SCSI_UFSHCD_CMD_LOGGING=y -CONFIG_MD=y -CONFIG_BLK_DEV_DM=y -CONFIG_DM_CRYPT=y -CONFIG_DM_VERITY=y -CONFIG_DM_VERITY_FEC=y -CONFIG_NETDEVICES=y -CONFIG_DUMMY=y -CONFIG_TUN=y -CONFIG_AT803X_PHY=y -CONFIG_PPP=y -CONFIG_PPP_BSDCOMP=y -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=y -CONFIG_PPP_MULTILINK=y -CONFIG_PPPOE=y -CONFIG_PPPOL2TP=y -CONFIG_PPPOLAC=y -CONFIG_PPPOPNS=y -CONFIG_PPP_ASYNC=y -CONFIG_PPP_SYNC_TTY=y -CONFIG_USB_USBNET=y -CONFIG_USB_NET_SMSC75XX=y -CONFIG_ATH10K=m -CONFIG_ATH10K_PCI=m -CONFIG_ATH10K_DEBUG=y -CONFIG_ATH10K_DEBUGFS=y -CONFIG_WCNSS_MEM_PRE_ALLOC=y -CONFIG_CLD_LL_CORE=y -CONFIG_CNSS=y -CONFIG_CNSS_SDIO=y -CONFIG_CLD_HL_SDIO_CORE=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_EVBUG=m -CONFIG_INPUT_KEYRESET=y -CONFIG_KEYBOARD_GPIO=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_JOYSTICK=y -CONFIG_JOYSTICK_XPAD=y -CONFIG_INPUT_TABLET=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ATMEL_MXT=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_HBTP_INPUT=y -CONFIG_INPUT_QPNP_POWER_ON=y -CONFIG_INPUT_UINPUT=y -CONFIG_INPUT_GPIO=y -# CONFIG_LEGACY_PTYS is not set -# CONFIG_DEVMEM is not set -CONFIG_SERIAL_MSM=y -CONFIG_SERIAL_MSM_CONSOLE=y -CONFIG_SERIAL_MSM_HS=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MSM_LEGACY=y -CONFIG_DIAG_CHAR=y -CONFIG_MSM_ADSPRPC=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MSM_V2=y -CONFIG_SPI=y -CONFIG_SPI_DEBUG=y -CONFIG_SPI_QUP=y -CONFIG_SPI_SPIDEV=y -CONFIG_SPMI=y -CONFIG_SPMI_MSM_PMIC_ARB_DEBUG=y -CONFIG_SLIMBUS_MSM_NGD=y -CONFIG_PTP_1588_CLOCK=y -CONFIG_PINCTRL_QCS405=y -CONFIG_FRAGMENTED_GPIO_ADDRESS_SPACE=y -CONFIG_PINCTRL_QCOM_SPMI_PMIC=y -CONFIG_GPIO_SYSFS=y -CONFIG_POWER_RESET_QCOM=y -CONFIG_QCOM_DLOAD_MODE=y -CONFIG_SMB1351_USB_CHARGER=y -CONFIG_THERMAL=y -CONFIG_THERMAL_WRITABLE_TRIPS=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_GOV_LOW_LIMITS=y -CONFIG_CPU_THERMAL=y -CONFIG_DEVFREQ_THERMAL=y -CONFIG_QCOM_SPMI_TEMP_ALARM=y -CONFIG_THERMAL_TSENS=y -CONFIG_QTI_VIRTUAL_SENSOR=y -CONFIG_QTI_QMI_COOLING_DEVICE=y -CONFIG_REGULATOR_COOLING_DEVICE=y -CONFIG_QTI_ADC_TM=y -CONFIG_QTI_RPM_SMD_COOLING_DEVICE=y -CONFIG_MFD_SPMI_PMIC=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_FAN53555=y -CONFIG_REGULATOR_CPR=y -CONFIG_REGULATOR_MEM_ACC=y -CONFIG_REGULATOR_RPM_SMD=y -CONFIG_REGULATOR_SPM=y -CONFIG_REGULATOR_STUB=y -CONFIG_RC_DEVICES=y -CONFIG_IR_MSM_GENI=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_RADIO_SUPPORT=y -CONFIG_MEDIA_CONTROLLER=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_SOC_CAMERA=y -CONFIG_SOC_CAMERA_PLATFORM=y -CONFIG_FB=y -CONFIG_FB_MSM=y -CONFIG_FB_MSM_MDSS=y -CONFIG_FB_MSM_MDSS_WRITEBACK=y -CONFIG_FB_MSM_MDSS_HDMI_PANEL=y -CONFIG_FB_MSM_MDSS_SPI_PANEL=y -CONFIG_FB_MSM_MDSS_RGB_PANEL=y -CONFIG_FB_MSM_MDSS_DSI_CTRL_STATUS=y -CONFIG_FB_MSM_MDSS_XLOG_DEBUG=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_DYNAMIC_MINORS=y -CONFIG_SND_USB_AUDIO=y -CONFIG_SND_SOC=y -CONFIG_HIDRAW=y -CONFIG_UHID=y -CONFIG_HID_APPLE=y -CONFIG_HID_ELECOM=y -CONFIG_HID_MAGICMOUSE=y -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MULTITOUCH=y -CONFIG_USB_HIDDEV=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_MON=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_ACM=y -CONFIG_USB_STORAGE=y -CONFIG_USB_STORAGE_DATAFAB=y -CONFIG_USB_STORAGE_FREECOM=y -CONFIG_USB_STORAGE_ISD200=y -CONFIG_USB_STORAGE_USBAT=y -CONFIG_USB_STORAGE_SDDR09=y -CONFIG_USB_STORAGE_SDDR55=y -CONFIG_USB_STORAGE_JUMPSHOT=y -CONFIG_USB_STORAGE_ALAUDA=y -CONFIG_USB_STORAGE_KARMA=y -CONFIG_USB_STORAGE_CYPRESS_ATACB=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_MSM=y -CONFIG_USB_SERIAL=y -CONFIG_USB_EHSET_TEST_FIXTURE=y -CONFIG_USB_LINK_LAYER_TEST=y -CONFIG_USB_TYPEC_MUX_NXP5150A=y -CONFIG_USB_QCOM_DIAG_BRIDGE=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_MSM_SNPS_FEMTO_PHY=y -CONFIG_USB_MSM_SSPHY=y -CONFIG_USB_QCOM_EMU_PHY=y -CONFIG_DUAL_ROLE_USB_INTF=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DEBUG_FILES=y -CONFIG_USB_GADGET_DEBUG_FS=y -CONFIG_USB_GADGET_VBUS_DRAW=900 -CONFIG_USB_CONFIGFS=y -CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_USB_CONFIGFS_UEVENT=y -CONFIG_USB_CONFIGFS_F_DIAG=y -CONFIG_MMC=y -CONFIG_MMC_PERF_PROFILING=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_BLOCK_DEFERRED_RESUME=y -CONFIG_MMC_TEST=m -CONFIG_MMC_RING_BUFFER=y -CONFIG_MMC_PARANOID_SD_INIT=y -CONFIG_MMC_CLKGATE=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_MSM=y -CONFIG_MMC_SDHCI_MSM_ICE=y -CONFIG_MMC_CQ_HCI=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_PCA9956B=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_QPNP=y -CONFIG_DMADEVICES=y -CONFIG_QCOM_SPS_DMA=y -CONFIG_UIO=y -CONFIG_STAGING=y -CONFIG_ASHMEM=y -CONFIG_ION=y -CONFIG_QPNP_REVID=y -CONFIG_SPS=y -CONFIG_SPS_SUPPORT_NDP_BAM=y -CONFIG_QCOM_MDSS_PLL=y -CONFIG_QCOM_CLK_SMD_RPM=y -CONFIG_SPMI_PMIC_CLKDIV=y -CONFIG_MDM_DEBUGCC_QCS405=y -CONFIG_CLOCK_CPU_QCS405=y -CONFIG_QCS_CMN_BLK_PLL=y -CONFIG_HWSPINLOCK=y -CONFIG_HWSPINLOCK_QCOM=y -CONFIG_ARM_ARCH_TIMER_VCT_ACCESS=y -CONFIG_MAILBOX=y -CONFIG_QCOM_APCS_IPC=y -CONFIG_ARM_SMMU=y -CONFIG_QCOM_LAZY_MAPPING=y -CONFIG_IOMMU_DEBUG=y -CONFIG_IOMMU_DEBUG_TRACKING=y -CONFIG_IOMMU_TESTS=y -CONFIG_RPMSG_CHAR=y -CONFIG_RPMSG_QCOM_GLINK_RPM=y -CONFIG_RPMSG_QCOM_GLINK_SMEM=y -CONFIG_MSM_RPM_SMD=y -CONFIG_QCOM_CPUSS_DUMP=y -CONFIG_QCOM_QMI_HELPERS=y -CONFIG_QCOM_SMEM=y -CONFIG_QCOM_SMD_RPM=y -CONFIG_MSM_SPM=y -CONFIG_MSM_L2_SPM=y -CONFIG_QCOM_SCM=y -CONFIG_QCOM_MEMORY_DUMP_V2=y -CONFIG_MSM_DEBUG_LAR_UNLOCK=y -CONFIG_QCOM_WATCHDOG_V2=y -CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y -CONFIG_QCOM_WDOG_IPI_ENABLE=y -CONFIG_QCOM_SMP2P=y -CONFIG_MSM_SERVICE_LOCATOR=y -CONFIG_MSM_SERVICE_NOTIFIER=y -CONFIG_MSM_SUBSYSTEM_RESTART=y -CONFIG_MSM_PIL=y -CONFIG_MSM_SYSMON_QMI_COMM=y -CONFIG_MSM_PIL_SSR_GENERIC=y -CONFIG_MSM_BOOT_STATS=y -CONFIG_MSM_CORE_HANG_DETECT=y -CONFIG_QCOM_DCC_V2=y -CONFIG_ICNSS=y -CONFIG_ICNSS_DEBUG=y -CONFIG_ICNSS_QMI=y -CONFIG_QCOM_BUS_SCALING=y -CONFIG_MSM_TZ_SMMU=y -CONFIG_QCOM_GLINK=y -CONFIG_QCOM_GLINK_PKT=y -CONFIG_QTI_RPM_STATS_LOG=y -CONFIG_MSM_CDSP_LOADER=y -CONFIG_QCOM_SMCINVOKE=y -CONFIG_MSM_PM=y -CONFIG_QCOM_SMP2P_SLEEPSTATE=y -CONFIG_QCOM_BIMC_BWMON=y -CONFIG_ARM_MEMLAT_MON=y -CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y -CONFIG_DEVFREQ_GOV_MEMLAT=y -CONFIG_QCOM_DEVFREQ_DEVBW=y -CONFIG_EXTCON_USB_GPIO=y -CONFIG_IIO=y -CONFIG_QCOM_SPMI_ADC5=y -CONFIG_PWM=y -CONFIG_PWM_QTI_LPG=y -CONFIG_QCOM_KGSL=y -CONFIG_QTI_MPM=y -CONFIG_ANDROID=y -CONFIG_ANDROID_BINDER_IPC=y -CONFIG_MSM_TZ_LOG=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT3_FS=y -CONFIG_EXT4_FS_SECURITY=y -CONFIG_QUOTA=y -CONFIG_QUOTA_NETLINK_INTERFACE=y -# CONFIG_PRINT_QUOTA_WARNING is not set -CONFIG_QFMT_V2=y -CONFIG_FUSE_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_UBIFS_FS=y -CONFIG_UBIFS_FS_ADVANCED_COMPR=y -CONFIG_SQUASHFS=y -CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y -CONFIG_SQUASHFS_XATTR=y -# CONFIG_SQUASHFS_ZLIB is not set -CONFIG_SQUASHFS_XZ=y -CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -CONFIG_PRINTK_TIME=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_DEBUG_INFO=y -CONFIG_PAGE_OWNER=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_PAGEALLOC=y -CONFIG_SLUB_DEBUG_PANIC_ON=y -CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y -CONFIG_PAGE_POISONING=y -CONFIG_PAGE_POISONING_ENABLE_DEFAULT=y -CONFIG_DEBUG_OBJECTS=y -CONFIG_DEBUG_OBJECTS_FREE=y -CONFIG_DEBUG_OBJECTS_TIMERS=y -CONFIG_DEBUG_OBJECTS_WORK=y -CONFIG_DEBUG_OBJECTS_RCU_HEAD=y -CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y -CONFIG_SLUB_DEBUG_ON=y -CONFIG_DEBUG_KMEMLEAK=y -CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=4000 -CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y -CONFIG_DEBUG_STACK_USAGE=y -CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_PANIC_ON_RECURSIVE_FAULT=y -CONFIG_PANIC_ON_OOPS=y -CONFIG_PANIC_TIMEOUT=5 -CONFIG_SCHEDSTATS=y -CONFIG_SCHED_STACK_END_CHECK=y -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_ATOMIC_SLEEP=y -CONFIG_FAULT_INJECTION=y -CONFIG_FAIL_PAGE_ALLOC=y -CONFIG_UFS_FAULT_INJECTION=y -CONFIG_FAULT_INJECTION_DEBUG_FS=y -CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y -CONFIG_IPC_LOGGING=y -CONFIG_QCOM_RTB=y -CONFIG_QCOM_RTB_SEPARATE_CPUS=y -CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_LKDTM=y -CONFIG_BUG_ON_DATA_CORRUPTION=y -CONFIG_CORESIGHT=y -CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y -CONFIG_CORESIGHT_SOURCE_ETM4X=y -CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y -CONFIG_CORESIGHT_STM=y -CONFIG_CORESIGHT_CTI=y -CONFIG_CORESIGHT_TPDA=y -CONFIG_CORESIGHT_TPDM=y -CONFIG_CORESIGHT_HWEVENT=y -CONFIG_CORESIGHT_DUMMY=y -CONFIG_CORESIGHT_REMOTE_ETM=y -CONFIG_CORESIGHT_REMOTE_ETM_DEFAULT_ENABLE=0 -CONFIG_CORESIGHT_EVENT=y -CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y -CONFIG_SECURITY=y -CONFIG_SECURITY_NETWORK=y -CONFIG_LSM_MMAP_MIN_ADDR=4096 -CONFIG_HARDENED_USERCOPY=y -CONFIG_HARDENED_USERCOPY_PAGESPAN=y -CONFIG_SECURITY_SELINUX=y -CONFIG_CRYPTO_CTR=y -CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y -CONFIG_CRYPTO_DEV_QCRYPTO=y -CONFIG_CRYPTO_DEV_QCEDEV=y -CONFIG_CRYPTO_DEV_QCOM_ICE=y diff --git a/arch/arm64/configs/vendor/sa8155-perf_defconfig b/arch/arm64/configs/vendor/sa8155-perf_defconfig index ca9ff962ff29..dde0c1b81692 100644 --- a/arch/arm64/configs/vendor/sa8155-perf_defconfig +++ b/arch/arm64/configs/vendor/sa8155-perf_defconfig @@ -309,9 +309,6 @@ CONFIG_CNSS2_DEBUG=y CONFIG_CNSS2_QMI=y CONFIG_CNSS_ASYNC=y CONFIG_CNSS_GENL=y -CONFIG_NVM=y -CONFIG_NVM_RRPC=y -CONFIG_NVM_PBLK=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set diff --git a/arch/arm64/configs/vendor/sa8155_defconfig b/arch/arm64/configs/vendor/sa8155_defconfig index 940dbf4ca592..98af752b29b7 100644 --- a/arch/arm64/configs/vendor/sa8155_defconfig +++ b/arch/arm64/configs/vendor/sa8155_defconfig @@ -322,9 +322,6 @@ CONFIG_CNSS2_DEBUG=y CONFIG_CNSS2_QMI=y CONFIG_CNSS_ASYNC=y CONFIG_CNSS_GENL=y -CONFIG_NVM=y -CONFIG_NVM_RRPC=y -CONFIG_NVM_PBLK=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set diff --git a/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig b/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig index a449ce2f4880..a395cb5dcaf8 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-auto-perf_defconfig @@ -704,3 +704,8 @@ CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y CONFIG_STACK_HASH_ORDER_SHIFT=12 +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_RAM=y +CONFIG_PSTORE_DEVICE_INFO=y +CONFIG_PSTORE_PMSG=y diff --git a/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig b/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig index 1ddb89cc282f..95eb55e243d9 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-auto_defconfig @@ -377,7 +377,6 @@ CONFIG_PINCTRL_SDMMAGPIE=y CONFIG_PINCTRL_SM6150=y CONFIG_PINCTRL_SLPI=y CONFIG_GPIO_SYSFS=y -CONFIG_GNSS_SIRF=y CONFIG_POWER_RESET_QCOM=y CONFIG_QCOM_DLOAD_MODE=y CONFIG_POWER_RESET_XGENE=y @@ -789,3 +788,8 @@ CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y CONFIG_XZ_DEC=y +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_RAM=y +CONFIG_PSTORE_DEVICE_INFO=y +CONFIG_PSTORE_PMSG=y diff --git a/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig b/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig index 0dd156d0612a..c560420f7c1e 100644 --- a/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe-perf_defconfig @@ -252,7 +252,6 @@ CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y CONFIG_ZRAM=y CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_LOOP_MIN_COUNT=16 CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_HDCP_QSEECOM=y diff --git a/arch/arm64/configs/vendor/sdmsteppe_defconfig b/arch/arm64/configs/vendor/sdmsteppe_defconfig index 7887c8f5b888..b83c506497a7 100644 --- a/arch/arm64/configs/vendor/sdmsteppe_defconfig +++ b/arch/arm64/configs/vendor/sdmsteppe_defconfig @@ -261,7 +261,6 @@ CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y CONFIG_ZRAM=y CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_LOOP_MIN_COUNT=16 CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_HDCP_QSEECOM=y diff --git a/arch/arm64/configs/vendor/sm8150-perf_defconfig b/arch/arm64/configs/vendor/sm8150-perf_defconfig index 1105ae35f0dc..ba7a8a2a95db 100644 --- a/arch/arm64/configs/vendor/sm8150-perf_defconfig +++ b/arch/arm64/configs/vendor/sm8150-perf_defconfig @@ -1,4 +1,4 @@ -CONFIG_HOTPLUG_SIZE_BITS=29 +# CONFIG_HOTPLUG_SIZE_BITS is not set CONFIG_LOCALVERSION="-perf" # CONFIG_LOCALVERSION_AUTO is not set # CONFIG_FHANDLE is not set @@ -64,10 +64,10 @@ CONFIG_SCHED_MC=y CONFIG_NR_CPUS=8 CONFIG_PREEMPT=y CONFIG_HZ_100=y -CONFIG_MEMORY_HOTPLUG=y -CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE=y -CONFIG_MEMORY_HOTPLUG_MOVABLE_NODE=y -CONFIG_MEMORY_HOTREMOVE=y +# CONFIG_MEMORY_HOTPLUG is not set +# CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE is not set +# CONFIG_MEMORY_HOTPLUG_MOVABLE_NODE is not set +# CONFIG_MEMORY_HOTREMOVE is not set CONFIG_CMA=y CONFIG_ZSMALLOC=y CONFIG_BALANCE_ANON_FILE_RECLAIM=y @@ -80,6 +80,7 @@ CONFIG_SETEND_EMULATION=y # CONFIG_ARM64_VHE is not set CONFIG_RANDOMIZE_BASE=y # CONFIG_EFI is not set +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y CONFIG_BUILD_ARM64_UNCOMPRESSED_KERNEL=y CONFIG_KRYO_PMU_WORKAROUND=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set @@ -90,6 +91,7 @@ CONFIG_PM_WAKELOCKS_LIMIT=0 CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_TIMES=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y @@ -254,7 +256,12 @@ CONFIG_CFG80211_CERTIFICATION_ONUS=y CONFIG_CFG80211_REG_CELLULAR_HINTS=y CONFIG_CFG80211_INTERNAL_REGDB=y CONFIG_RFKILL=y -CONFIG_NFC_NQ=y +# CONFIG_NFC_NQ=y +# CONFIG_NFC_PN5XX=y +# CONFIG_NFC_PN80T=y +CONFIG_NXP_ESE_PN8XT=y +CONFIG_NXP_NFC_PN8XT=y +CONFIG_NXP_NFC_ESE_DEVICE=y CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y @@ -319,11 +326,30 @@ CONFIG_CLD_LL_CORE=y CONFIG_CNSS_GENL=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y +CONFIG_TRI_STATE_KEY=y # CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_FINGERPRINT=y +CONFIG_FINGERPRINT_DETECT=y +CONFIG_FINGERPRINT_GOODIX=y CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ST=y +CONFIG_TOUCHPANEL_SAMSUNG=y +CONFIG_TOUCHPANEL_SAMSUNG_S6SY761=y +CONFIG_TOUCHPANEL_ONEPLUS=y +CONFIG_TOUCHPANEL_SYNAPTICS=y +CONFIG_TOUCHPANEL_SYNAPTICS_S3706=y +CONFIG_SENSOR_HALL_MXM1120=y +CONFIG_SENSOR_HALL_IST8801=y +CONFIG_HALL_TRI_STATE_KEY=y + +#CONFIG_TOUCHSCREEN_SYNAPTICS_S3320_I2C_RMI=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_EXTRA_SYSFS=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_TEST_REPORTING=y + CONFIG_INPUT_MISC=y -CONFIG_INPUT_HBTP_INPUT=y +# CONFIG_INPUT_HBTP_INPUT is not set CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_QTI_HAPTICS=y CONFIG_INPUT_UINPUT=y @@ -332,6 +358,7 @@ CONFIG_INPUT_UINPUT=y # CONFIG_LEGACY_PTYS is not set # CONFIG_DEVMEM is not set CONFIG_SERIAL_MSM_GENI=y +CONFIG_SERIAL_MSM_GENI_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_MSM_LEGACY=y # CONFIG_DEVPORT is not set @@ -363,6 +390,11 @@ CONFIG_QPNP_FG_GEN4=y CONFIG_SMB1355_SLAVE_CHARGER=y CONFIG_QPNP_SMB5=y CONFIG_QPNP_QNOVO5=y +CONFIG_FG_BQ27541=y +CONFIG_ONEPLUS_FASTCHG=y +CONFIG_JOYSTICK_XPAD=y +CONFIG_HID_SONY=y +CONFIG_SONY_FF=y CONFIG_SMB1390_CHARGE_PUMP_PSY=y CONFIG_THERMAL=y CONFIG_THERMAL_WRITABLE_TRIPS=y @@ -547,8 +579,8 @@ CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_QCOM_GLINK_SMEM=y CONFIG_RPMSG_QCOM_GLINK_SPSS=y CONFIG_RPMSG_QCOM_GLINK_SPI=y -CONFIG_QCOM_MEM_OFFLINE=y -CONFIG_OVERRIDE_MEMORY_LIMIT=y +# CONFIG_QCOM_MEM_OFFLINE is not set +# CONFIG_OVERRIDE_MEMORY_LIMIT is not set CONFIG_QCOM_CPUSS_DUMP=y CONFIG_QCOM_RUN_QUEUE_STATS=y CONFIG_QCOM_LLCC=y @@ -653,6 +685,8 @@ CONFIG_FUSE_FS=y CONFIG_OVERLAY_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y +CONFIG_EXFAT_FS=y +CONFIG_NTFS_FS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_ECRYPT_FS=y CONFIG_ECRYPT_FS_MESSAGING=y @@ -662,11 +696,15 @@ CONFIG_NLS_ISO8859_1=y CONFIG_PRINTK_TIME=y CONFIG_DEBUG_INFO=y CONFIG_PAGE_OWNER=y +CONFIG_PAGE_OWNER_ENABLE_DEFAULT=y CONFIG_MAGIC_SYSRQ=y CONFIG_PANIC_TIMEOUT=-1 CONFIG_SCHEDSTATS=y # CONFIG_DEBUG_PREEMPT is not set CONFIG_IPC_LOGGING=y +CONFIG_QCOM_RTB=y +CONFIG_QCOM_RTB_SEPARATE_CPUS=y +CONFIG_BLK_DEV_IO_TRACE=y CONFIG_DEBUG_ALIGN_RODATA=y CONFIG_CORESIGHT=y CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y @@ -706,3 +744,37 @@ CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y CONFIG_STACK_HASH_ORDER_SHIFT=12 +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_RAM=y +CONFIG_PSTORE_DEVICE_INFO=y +CONFIG_PSTORE_PMSG=y +CONFIG_PROJECT_INFO=y +CONFIG_BOOTLOADER_LOG=y +CONFIG_OEM_BOOT_MODE=y +CONFIG_AW8697_HAPTIC=y +CONFIG_DIGITAL_HALL_M1120=y +CONFIG_STEP_MOTOR=y +CONFIG_NET_CLS_CGROUP=y +CONFIG_OPCHAIN=y +CONFIG_RF_CABLE_DETECT=y +CONFIG_ADJ_CHAIN=y +CONFIG_DEFRAG=y +CONFIG_FSC=y +CONFIG_SMART_BOOST=y +CONFIG_MEMPLUS=y +CONFIG_OVERLAY_FS=y +CONFIG_HOUSTON=y +CONFIG_CONTROL_CENTER=y +CONFIG_AIGOV=y +CONFIG_ONEPLUS_MEM_MONITOR=y +CONFIG_ONEPLUS_FG_OPT=y +CONFIG_ONEPLUS_HEALTHINFO=y +CONFIG_SLAB_STAT_DEBUG=y +CONFIG_SLABINFO=y +# dylanchang, 2019/4/30, enable noop io scheduler +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# dylanchang,2019/4/1, add for kernel log reserve +CONFIG_WB_KERNEL_LOG=y +CONFIG_SLA=y diff --git a/arch/arm64/configs/vendor/sm8150_defconfig b/arch/arm64/configs/vendor/sm8150_defconfig index 0aa80bf5bdff..ed14c3fbdb69 100644 --- a/arch/arm64/configs/vendor/sm8150_defconfig +++ b/arch/arm64/configs/vendor/sm8150_defconfig @@ -1,4 +1,4 @@ -CONFIG_HOTPLUG_SIZE_BITS=29 +# CONFIG_HOTPLUG_SIZE_BITS is not set # CONFIG_LOCALVERSION_AUTO is not set # CONFIG_FHANDLE is not set CONFIG_AUDIT=y @@ -68,10 +68,10 @@ CONFIG_SCHED_MC=y CONFIG_NR_CPUS=8 CONFIG_PREEMPT=y CONFIG_HZ_100=y -CONFIG_MEMORY_HOTPLUG=y -CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE=y -CONFIG_MEMORY_HOTPLUG_MOVABLE_NODE=y -CONFIG_MEMORY_HOTREMOVE=y +# CONFIG_MEMORY_HOTPLUG is not set +# CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE is not set +# CONFIG_MEMORY_HOTPLUG_MOVABLE_NODE is not set +# CONFIG_MEMORY_HOTREMOVE is not set CONFIG_CLEANCACHE=y CONFIG_CMA=y CONFIG_CMA_DEBUGFS=y @@ -86,6 +86,7 @@ CONFIG_CP15_BARRIER_EMULATION=y CONFIG_SETEND_EMULATION=y # CONFIG_ARM64_VHE is not set CONFIG_RANDOMIZE_BASE=y +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y CONFIG_BUILD_ARM64_UNCOMPRESSED_KERNEL=y CONFIG_KRYO_PMU_WORKAROUND=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set @@ -97,6 +98,7 @@ CONFIG_PM_DEBUG=y CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_TIMES=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y @@ -264,7 +266,12 @@ CONFIG_CFG80211_REG_CELLULAR_HINTS=y CONFIG_CFG80211_INTERNAL_REGDB=y # CONFIG_CFG80211_CRDA_SUPPORT is not set CONFIG_RFKILL=y -CONFIG_NFC_NQ=y +# CONFIG_NFC_NQ=y +# CONFIG_NFC_PN5XX=y +# CONFIG_NFC_PN80T=y +CONFIG_NXP_ESE_PN8XT=y +CONFIG_NXP_NFC_PN8XT=y +CONFIG_NXP_NFC_ESE_DEVICE=y CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y @@ -330,12 +337,31 @@ CONFIG_CLD_LL_CORE=y CONFIG_CNSS_GENL=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y +CONFIG_TRI_STATE_KEY=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_JOYSTICK=y +CONFIG_INPUT_FINGERPRINT=y +CONFIG_FINGERPRINT_DETECT=y +CONFIG_FINGERPRINT_GOODIX=y CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ST=y +CONFIG_TOUCHPANEL_SAMSUNG=y +CONFIG_TOUCHPANEL_SAMSUNG_S6SY761=y +CONFIG_TOUCHPANEL_ONEPLUS=y +CONFIG_TOUCHPANEL_SYNAPTICS=y +CONFIG_TOUCHPANEL_SYNAPTICS_S3706=y +CONFIG_SENSOR_HALL_MXM1120=y +CONFIG_SENSOR_HALL_IST8801=y +CONFIG_HALL_TRI_STATE_KEY=y + +#CONFIG_TOUCHSCREEN_SYNAPTICS_S3320_I2C_RMI=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_EXTRA_SYSFS=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_TEST_REPORTING=y + CONFIG_INPUT_MISC=y -CONFIG_INPUT_HBTP_INPUT=y +# CONFIG_INPUT_HBTP_INPUT is not set CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_QTI_HAPTICS=y CONFIG_INPUT_UINPUT=y @@ -378,6 +404,11 @@ CONFIG_QPNP_FG_GEN4=y CONFIG_SMB1355_SLAVE_CHARGER=y CONFIG_QPNP_SMB5=y CONFIG_QPNP_QNOVO5=y +CONFIG_FG_BQ27541=y +CONFIG_ONEPLUS_FASTCHG=y +CONFIG_JOYSTICK_XPAD=y +CONFIG_HID_SONY=y +CONFIG_SONY_FF=y CONFIG_SMB1390_CHARGE_PUMP_PSY=y CONFIG_THERMAL=y CONFIG_THERMAL_WRITABLE_TRIPS=y @@ -571,8 +602,8 @@ CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_QCOM_GLINK_SMEM=y CONFIG_RPMSG_QCOM_GLINK_SPSS=y CONFIG_RPMSG_QCOM_GLINK_SPI=y -CONFIG_QCOM_MEM_OFFLINE=y -CONFIG_OVERRIDE_MEMORY_LIMIT=y +# CONFIG_QCOM_MEM_OFFLINE is not set +# CONFIG_OVERRIDE_MEMORY_LIMIT is not set CONFIG_QCOM_CPUSS_DUMP=y CONFIG_QCOM_RUN_QUEUE_STATS=y CONFIG_QCOM_LLCC=y @@ -683,6 +714,8 @@ CONFIG_FUSE_FS=y CONFIG_OVERLAY_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y +CONFIG_EXFAT_FS=y +CONFIG_NTFS_FS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_EFIVAR_FS=y CONFIG_ECRYPT_FS=y @@ -712,7 +745,7 @@ CONFIG_DEBUG_OBJECTS_WORK=y CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y CONFIG_SLUB_DEBUG_ON=y CONFIG_DEBUG_KMEMLEAK=y -CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=4000 +CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=8192 CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y CONFIG_DEBUG_STACK_USAGE=y CONFIG_DEBUG_MEMORY_INIT=y @@ -792,3 +825,39 @@ CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y CONFIG_XZ_DEC=y +# yangfb,2018/1/26, add for aging test get log and limmit current +CONFIG_OP_DEBUG_CHG=y +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_RAM=y +CONFIG_PSTORE_DEVICE_INFO=y +CONFIG_PSTORE_PMSG=y +CONFIG_PROJECT_INFO=y +CONFIG_BOOTLOADER_LOG=y +CONFIG_OEM_BOOT_MODE=y +CONFIG_AW8697_HAPTIC=y +CONFIG_DIGITAL_HALL_M1120=y +CONFIG_STEP_MOTOR=y +CONFIG_NET_CLS_CGROUP=y +CONFIG_OPCHAIN=y +CONFIG_RF_CABLE_DETECT=y +CONFIG_ADJ_CHAIN=y +CONFIG_DEFRAG=y +CONFIG_FSC=y +CONFIG_SMART_BOOST=y +CONFIG_MEMPLUS=y +CONFIG_OVERLAY_FS=y +CONFIG_HOUSTON=y +CONFIG_CONTROL_CENTER=y +CONFIG_AIGOV=y +CONFIG_ONEPLUS_MEM_MONITOR=y +CONFIG_ONEPLUS_FG_OPT=y +CONFIG_ONEPLUS_HEALTHINFO=y +CONFIG_SLAB_STAT_DEBUG=y +CONFIG_SLABINFO=y +# dylanchang, 2019/4/30, enable noop io scheduler +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# dylanchang,2019/4/1, add for kernel log reserve +CONFIG_WB_KERNEL_LOG=y +CONFIG_SLA=y diff --git a/arch/arm64/configs/vendor/trinket-perf_defconfig b/arch/arm64/configs/vendor/trinket-perf_defconfig index 797f8f1fba9a..ada21ac70ca0 100644 --- a/arch/arm64/configs/vendor/trinket-perf_defconfig +++ b/arch/arm64/configs/vendor/trinket-perf_defconfig @@ -79,6 +79,7 @@ CONFIG_ARM64_SW_TTBR0_PAN=y # CONFIG_ARM64_PAN is not set # CONFIG_ARM64_VHE is not set CONFIG_RANDOMIZE_BASE=y +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_COMPAT=y CONFIG_PM_WAKELOCKS=y @@ -257,7 +258,6 @@ CONFIG_DMA_CMA=y CONFIG_ZRAM=y CONFIG_ZRAM_DEDUP=y CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_LOOP_MIN_COUNT=16 CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_HDCP_QSEECOM=y diff --git a/arch/arm64/configs/vendor/trinket_defconfig b/arch/arm64/configs/vendor/trinket_defconfig index b9019ce1f73d..ed1eac7f348d 100644 --- a/arch/arm64/configs/vendor/trinket_defconfig +++ b/arch/arm64/configs/vendor/trinket_defconfig @@ -85,6 +85,7 @@ CONFIG_ARM64_SW_TTBR0_PAN=y # CONFIG_ARM64_PAN is not set # CONFIG_ARM64_VHE is not set CONFIG_RANDOMIZE_BASE=y +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_COMPAT=y CONFIG_PM_WAKELOCKS=y @@ -266,7 +267,6 @@ CONFIG_DMA_CMA=y CONFIG_ZRAM=y CONFIG_ZRAM_DEDUP=y CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_LOOP_MIN_COUNT=16 CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_HDCP_QSEECOM=y diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index 802968818aa3..ab1149efda43 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -46,9 +46,7 @@ #define ARM64_HW_DBM 26 #define ARM64_SSBD 27 #define ARM64_MISMATCHED_CACHE_TYPE 28 -#define ARM64_SSBS 29 -#define ARM64_WORKAROUND_1188873 30 -#define ARM64_NCAPS 31 +#define ARM64_NCAPS 29 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h index e174fe5e208a..e2675f9d3da6 100644 --- a/arch/arm64/include/asm/io.h +++ b/arch/arm64/include/asm/io.h @@ -107,11 +107,10 @@ static inline u64 __raw_readq_no_log(const volatile void __iomem *addr) #define __raw_write_logged(v, a, _t) ({ \ int _ret; \ - volatile void __iomem *_a = (a); \ - void *_addr = (void __force *)(_a); \ + void *_addr = (void *)(a); \ _ret = uncached_logk(LOGK_WRITEL, _addr); \ ETB_WAYPOINT; \ - __raw_write##_t##_no_log((v), _a); \ + __raw_write##_t##_no_log((v), _addr); \ if (_ret) \ LOG_BARRIER; \ }) @@ -123,12 +122,11 @@ static inline u64 __raw_readq_no_log(const volatile void __iomem *addr) #define __raw_read_logged(a, _l, _t) ({ \ _t __a; \ - const volatile void __iomem *_a = (a); \ - void *_addr = (void __force *)(_a); \ + void *_addr = (void *)(a); \ int _ret; \ _ret = uncached_logk(LOGK_READL, _addr); \ ETB_WAYPOINT; \ - __a = __raw_read##_l##_no_log(_a); \ + __a = __raw_read##_l##_no_log(_addr); \ if (_ret) \ LOG_BARRIER; \ __a; \ diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index 87653c86b2e6..e02c4bd7c68f 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -147,10 +147,6 @@ static inline void start_thread(struct pt_regs *regs, unsigned long pc, { start_thread_common(regs, pc); regs->pstate = PSR_MODE_EL0t; - - if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE) - regs->pstate |= PSR_SSBS_BIT; - regs->sp = sp; } @@ -167,9 +163,6 @@ static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc, regs->pstate |= COMPAT_PSR_E_BIT; #endif - if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE) - regs->pstate |= COMPAT_PSR_SSBS_BIT; - regs->compat_sp = sp; } #endif diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h index 17c7e949e42c..9faaba0064a2 100644 --- a/arch/arm64/include/asm/ptrace.h +++ b/arch/arm64/include/asm/ptrace.h @@ -50,7 +50,6 @@ #define COMPAT_PSR_I_BIT 0x00000080 #define COMPAT_PSR_A_BIT 0x00000100 #define COMPAT_PSR_E_BIT 0x00000200 -#define COMPAT_PSR_SSBS_BIT 0x00800000 #define COMPAT_PSR_J_BIT 0x01000000 #define COMPAT_PSR_Q_BIT 0x08000000 #define COMPAT_PSR_V_BIT 0x10000000 diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 82e4c7eea8cf..642333e9ba63 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -83,26 +83,13 @@ #endif /* CONFIG_BROKEN_GAS_INST */ -/* - * Instructions for modifying PSTATE fields. - * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints, - * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions - * for accessing PSTATE fields have the following encoding: - * Op0 = 0, CRn = 4 - * Op1, Op2 encodes the PSTATE field modified and defines the constraints. - * CRm = Imm4 for the instruction. - * Rt = 0x1f - */ -#define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) -#define PSTATE_Imm_shift CRm_shift - -#define PSTATE_PAN pstate_field(0, 4) -#define PSTATE_UAO pstate_field(0, 3) -#define PSTATE_SSBS pstate_field(3, 1) +#define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4) +#define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3) -#define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift)) -#define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift)) -#define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift)) +#define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 | REG_PSTATE_PAN_IMM | \ + (!!x)<<8 | 0x1f) +#define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 | REG_PSTATE_UAO_IMM | \ + (!!x)<<8 | 0x1f) #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) @@ -314,7 +301,6 @@ #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) /* Common SCTLR_ELx flags. */ -#define SCTLR_ELx_DSSBS (1UL << 44) #define SCTLR_ELx_EE (1 << 25) #define SCTLR_ELx_I (1 << 12) #define SCTLR_ELx_SA (1 << 3) @@ -375,13 +361,6 @@ #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2 -/* id_aa64pfr1 */ -#define ID_AA64PFR1_SSBS_SHIFT 4 - -#define ID_AA64PFR1_SSBS_PSTATE_NI 0 -#define ID_AA64PFR1_SSBS_PSTATE_ONLY 1 -#define ID_AA64PFR1_SSBS_PSTATE_INSNS 2 - /* id_aa64mmfr0 */ #define ID_AA64MMFR0_TGRAN4_SHIFT 28 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index eed4600efdad..f243c57d1670 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -42,6 +42,5 @@ #define HWCAP_SM4 (1 << 19) #define HWCAP_ASIMDDP (1 << 20) #define HWCAP_SHA512 (1 << 21) -#define HWCAP_SSBS (1 << 22) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi/asm/ptrace.h index eea58f8ec355..67d4c33974e8 100644 --- a/arch/arm64/include/uapi/asm/ptrace.h +++ b/arch/arm64/include/uapi/asm/ptrace.h @@ -45,7 +45,6 @@ #define PSR_I_BIT 0x00000080 #define PSR_A_BIT 0x00000100 #define PSR_D_BIT 0x00000200 -#define PSR_SSBS_BIT 0x00001000 #define PSR_PAN_BIT 0x00400000 #define PSR_UAO_BIT 0x00800000 #define PSR_Q_BIT 0x08000000 diff --git a/arch/arm64/include/uapi/asm/setup.h b/arch/arm64/include/uapi/asm/setup.h index 5d703888f351..9f583cb9e76e 100644 --- a/arch/arm64/include/uapi/asm/setup.h +++ b/arch/arm64/include/uapi/asm/setup.h @@ -22,6 +22,6 @@ #include -#define COMMAND_LINE_SIZE 2048 +#define COMMAND_LINE_SIZE 3072 #endif diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 99ac724f2153..2c27bf15cd2e 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -271,14 +271,6 @@ early_param("ssbd", ssbd_cfg); void arm64_set_ssbd_mitigation(bool state) { - if (this_cpu_has_cap(ARM64_SSBS)) { - if (state) - asm volatile(SET_PSTATE_SSBS(0)); - else - asm volatile(SET_PSTATE_SSBS(1)); - return; - } - switch (psci_ops.conduit) { case PSCI_CONDUIT_HVC: arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_2, state, NULL); @@ -303,11 +295,6 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); - if (this_cpu_has_cap(ARM64_SSBS)) { - required = false; - goto out_printmsg; - } - if (psci_ops.smccc_version == SMCCC_VERSION_1_0) { ssbd_state = ARM64_SSBD_UNKNOWN; return false; @@ -356,6 +343,7 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, switch (ssbd_state) { case ARM64_SSBD_FORCE_DISABLE: + pr_info_once("%s disabled from command-line\n", entry->desc); arm64_set_ssbd_mitigation(false); required = false; break; @@ -368,6 +356,7 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, break; case ARM64_SSBD_FORCE_ENABLE: + pr_info_once("%s forced from command-line\n", entry->desc); arm64_set_ssbd_mitigation(true); required = true; break; @@ -377,17 +366,6 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, break; } -out_printmsg: - switch (ssbd_state) { - case ARM64_SSBD_FORCE_DISABLE: - pr_info_once("%s disabled from command-line\n", entry->desc); - break; - - case ARM64_SSBD_FORCE_ENABLE: - pr_info_once("%s forced from command-line\n", entry->desc); - break; - } - return required; } #endif /* CONFIG_ARM64_SSBD */ @@ -554,12 +532,6 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_CPU_VAR_REV(0, 0), MIDR_CPU_VAR_REV(3, 0)), }, - { - .capability = ARM64_WORKAROUND_REPEAT_TLBI, - MIDR_RANGE(MIDR_KRYO4G, - MIDR_CPU_VAR_REV(12, 14), - MIDR_CPU_VAR_REV(13, 14)), - }, #endif #ifdef CONFIG_ARM64_ERRATUM_858921 { @@ -644,25 +616,6 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .capability = ARM64_SSBD, .matches = has_ssbd_mitigation, }, -#endif -#ifdef CONFIG_ARM64_ERRATUM_1188873 - { - .desc = "ARM erratum 1188873", - .capability = ARM64_WORKAROUND_1188873, - /* Cortex-A76 r0p0 to r2p0 */ - MIDR_RANGE(MIDR_CORTEX_A76, - MIDR_CPU_VAR_REV(0, 0), - MIDR_CPU_VAR_REV(2, 0)), - - }, - { - .desc = "ARM erratum 1188873", - .capability = ARM64_WORKAROUND_1188873, - /* Kryo-4G r15p14 */ - MIDR_RANGE(MIDR_KRYO4G, - MIDR_CPU_VAR_REV(15, 14), - MIDR_CPU_VAR_REV(15, 15)), - }, #endif { } diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index fa4924bad290..152fda8b9cbc 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -142,11 +142,6 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { ARM64_FTR_END, }; -static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI), - ARM64_FTR_END, -}; - static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), @@ -346,8 +341,7 @@ static const struct __ftr_reg_entry { /* Op1 = 0, CRn = 0, CRm = 4 */ ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), - ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1), - ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_raz), + ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_raz), /* Op1 = 0, CRn = 0, CRm = 5 */ ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), @@ -615,6 +609,7 @@ void update_cpu_features(int cpu, /* * EL3 is not our concern. + * ID_AA64PFR1 is currently RES0. */ taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); @@ -983,50 +978,6 @@ static int cpu_copy_el2regs(void *__unused) return 0; } -#ifdef CONFIG_ARM64_SSBD -static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr) -{ - if (user_mode(regs)) - return 1; - - if (instr & BIT(PSTATE_Imm_shift)) - regs->pstate |= PSR_SSBS_BIT; - else - regs->pstate &= ~PSR_SSBS_BIT; - - regs->pc += 4; - return 0; -} - -static struct undef_hook ssbs_emulation_hook = { - .instr_mask = ~(1U << PSTATE_Imm_shift), - .instr_val = 0xd500401f | PSTATE_SSBS, - .fn = ssbs_emulation_handler, -}; - -static int cpu_enable_ssbs(void *__unsused) -{ - static bool undef_hook_registered = false; - static DEFINE_SPINLOCK(hook_lock); - - spin_lock(&hook_lock); - if (!undef_hook_registered) { - register_undef_hook(&ssbs_emulation_hook); - undef_hook_registered = true; - } - spin_unlock(&hook_lock); - - if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) { - write_sysreg((read_sysreg(sctlr_el1) | SCTLR_ELx_DSSBS), - sctlr_el1); - arm64_set_ssbd_mitigation(false); - } else { - arm64_set_ssbd_mitigation(true); - } - return 0; -} -#endif /* CONFIG_ARM64_SSBD */ - static const struct arm64_cpu_capabilities arm64_features[] = { { .desc = "GIC system register CPU interface", @@ -1159,18 +1110,6 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_hw_dbm, .enable = cpu_enable_hw_dbm, }, -#endif -#ifdef CONFIG_ARM64_SSBD - { - .desc = "Speculative Store Bypassing Safe (SSBS)", - .capability = ARM64_SSBS, - .matches = has_cpuid_feature, - .sys_reg = SYS_ID_AA64PFR1_EL1, - .field_pos = ID_AA64PFR1_SSBS_SHIFT, - .sign = FTR_UNSIGNED, - .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY, - .enable = cpu_enable_ssbs, - }, #endif {}, }; @@ -1209,7 +1148,6 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT), HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA), HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC), - HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, HWCAP_SSBS), {}, }; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 1e3fbfb2b977..5bca95fcdfe9 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -81,7 +81,6 @@ static const char *const hwcap_str[] = { "sm4", "asimddp", "sha512", - "ssbs", NULL }; diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index de16794fd64c..7e50aec45858 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -602,7 +602,7 @@ el1_undef: enable_dbg mov x0, sp bl do_undefinstr - kernel_exit 1 + ASM_BUG() el1_dbg: /* * Debug exception handling diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index e0a80e230c5e..66eb8e23bc67 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -1001,7 +1001,7 @@ static void armv8pmu_idle_update(struct arm_pmu *cpu_pmu) struct perf_event *event; int idx; - if (!cpu_pmu) + if (!cpu_pmu || !(cpu_pmu->hw_events)) return; if (__this_cpu_read(is_hotplugging)) diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 6f3258a9d0eb..e31f59db9397 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -365,10 +365,6 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start, if (IS_ENABLED(CONFIG_ARM64_UAO) && cpus_have_const_cap(ARM64_HAS_UAO)) childregs->pstate |= PSR_UAO_BIT; - - if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) - childregs->pstate |= PSR_SSBS_BIT; - p->thread.cpu_context.x19 = stack_start; p->thread.cpu_context.x20 = stk_sz; } diff --git a/arch/arm64/kernel/ssbd.c b/arch/arm64/kernel/ssbd.c index 477ede8809c8..0560738c1d5c 100644 --- a/arch/arm64/kernel/ssbd.c +++ b/arch/arm64/kernel/ssbd.c @@ -3,31 +3,13 @@ * Copyright (C) 2018 ARM Ltd, All Rights Reserved. */ -#include #include #include #include -#include #include #include -static void ssbd_ssbs_enable(struct task_struct *task) -{ - u64 val = is_compat_thread(task_thread_info(task)) ? - COMPAT_PSR_SSBS_BIT : PSR_SSBS_BIT; - - task_pt_regs(task)->pstate |= val; -} - -static void ssbd_ssbs_disable(struct task_struct *task) -{ - u64 val = is_compat_thread(task_thread_info(task)) ? - COMPAT_PSR_SSBS_BIT : PSR_SSBS_BIT; - - task_pt_regs(task)->pstate &= ~val; -} - /* * prctl interface for SSBD */ @@ -63,14 +45,12 @@ static int ssbd_prctl_set(struct task_struct *task, unsigned long ctrl) return -EPERM; task_clear_spec_ssb_disable(task); clear_tsk_thread_flag(task, TIF_SSBD); - ssbd_ssbs_enable(task); break; case PR_SPEC_DISABLE: if (state == ARM64_SSBD_FORCE_DISABLE) return -EPERM; task_set_spec_ssb_disable(task); set_tsk_thread_flag(task, TIF_SSBD); - ssbd_ssbs_disable(task); break; case PR_SPEC_FORCE_DISABLE: if (state == ARM64_SSBD_FORCE_DISABLE) @@ -78,7 +58,6 @@ static int ssbd_prctl_set(struct task_struct *task, unsigned long ctrl) task_set_spec_ssb_disable(task); task_set_spec_ssb_force_disable(task); set_tsk_thread_flag(task, TIF_SSBD); - ssbd_ssbs_disable(task); break; default: return -ERANGE; diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index d1a891023b10..fedd5eb1463e 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -51,6 +51,9 @@ #include #include +/* Save pt_regs ptr to get panic info for display in xbl mode */ +void *panic_info = NULL; + static const char *handler[]= { "Synchronous Abort", "IRQ", @@ -194,6 +197,10 @@ static int __die(const char *str, int err, struct pt_regs *regs) static int die_counter; int ret; + /* Save regs to display in xbl mode */ + if (!panic_info) + panic_info = (void *)regs; + pr_emerg("Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n", str, err, ++die_counter); @@ -303,12 +310,10 @@ static int call_undef_hook(struct pt_regs *regs) int (*fn)(struct pt_regs *regs, u32 instr) = NULL; void __user *pc = (void __user *)instruction_pointer(regs); - if (!user_mode(regs)) { - __le32 instr_le; - if (probe_kernel_address((__force __le32 *)pc, instr_le)) - goto exit; - instr = le32_to_cpu(instr_le); - } else if (compat_thumb_mode(regs)) { + if (!user_mode(regs)) + return 1; + + if (compat_thumb_mode(regs)) { /* 16-bit Thumb instruction */ __le16 instr_le; if (get_user(instr_le, (__le16 __user *)pc)) @@ -406,7 +411,6 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs) trace_undef_instr(regs, pc); force_signal_inject(SIGILL, ILL_ILLOPC, regs, 0); - BUG_ON(!user_mode(regs)); } int cpu_enable_cache_maint_trap(void *__unused) diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index b23cb4101756..c87f97a8740d 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -488,6 +488,9 @@ static int __kprobes do_page_fault(unsigned long addr, unsigned int esr, * the mmap_sem because it would already be released * in __lock_page_or_retry in mm/filemap.c. */ +#ifdef CONFIG_MEMPLUS + count_vm_event(RETRYPAGE); +#endif if (fatal_signal_pending(current)) { if (!user_mode(regs)) goto no_context; diff --git a/arch/blackfin/boot/install.sh b/arch/blackfin/boot/install.sh old mode 100644 new mode 100755 diff --git a/arch/ia64/install.sh b/arch/ia64/install.sh old mode 100644 new mode 100755 diff --git a/arch/ia64/scripts/check-gas b/arch/ia64/scripts/check-gas old mode 100755 new mode 100644 diff --git a/arch/ia64/scripts/toolchain-flags b/arch/ia64/scripts/toolchain-flags old mode 100755 new mode 100644 diff --git a/arch/m32r/boot/compressed/install.sh b/arch/m32r/boot/compressed/install.sh old mode 100644 new mode 100755 diff --git a/arch/m68k/install.sh b/arch/m68k/install.sh old mode 100644 new mode 100755 diff --git a/arch/mn10300/boot/install.sh b/arch/mn10300/boot/install.sh old mode 100644 new mode 100755 diff --git a/arch/nios2/boot/install.sh b/arch/nios2/boot/install.sh old mode 100644 new mode 100755 diff --git a/arch/parisc/boot/install.sh b/arch/parisc/boot/install.sh old mode 100644 new mode 100755 diff --git a/arch/parisc/install.sh b/arch/parisc/install.sh old mode 100644 new mode 100755 diff --git a/arch/powerpc/boot/install.sh b/arch/powerpc/boot/install.sh old mode 100644 new mode 100755 diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper old mode 100755 new mode 100644 diff --git a/arch/powerpc/kernel/prom_init_check.sh b/arch/powerpc/kernel/prom_init_check.sh old mode 100644 new mode 100755 diff --git a/arch/powerpc/kernel/systbl_chk.sh b/arch/powerpc/kernel/systbl_chk.sh old mode 100644 new mode 100755 diff --git a/arch/powerpc/tools/head_check.sh b/arch/powerpc/tools/head_check.sh old mode 100644 new mode 100755 diff --git a/arch/s390/boot/install.sh b/arch/s390/boot/install.sh old mode 100644 new mode 100755 diff --git a/arch/sh/boot/compressed/install.sh b/arch/sh/boot/compressed/install.sh old mode 100644 new mode 100755 diff --git a/arch/sparc/boot/install.sh b/arch/sparc/boot/install.sh old mode 100644 new mode 100755 diff --git a/arch/x86/boot/install.sh b/arch/x86/boot/install.sh old mode 100644 new mode 100755 diff --git a/arch/x86/entry/syscalls/syscallhdr.sh b/arch/x86/entry/syscalls/syscallhdr.sh old mode 100644 new mode 100755 diff --git a/arch/x86/entry/syscalls/syscalltbl.sh b/arch/x86/entry/syscalls/syscalltbl.sh old mode 100644 new mode 100755 diff --git a/arch/x86/kernel/cpu/mkcapflags.sh b/arch/x86/kernel/cpu/mkcapflags.sh old mode 100644 new mode 100755 diff --git a/arch/x86/um/vdso/checkundef.sh b/arch/x86/um/vdso/checkundef.sh old mode 100644 new mode 100755 diff --git a/block/blk-core.c b/block/blk-core.c index 0c7e240430c1..1d7fb3f2d915 100644 --- a/block/blk-core.c +++ b/block/blk-core.c @@ -45,6 +45,10 @@ #include +#ifdef CONFIG_MEMPLUS +#include +#endif + #ifdef CONFIG_DEBUG_FS struct dentry *blk_debugfs_root; #endif @@ -117,6 +121,8 @@ void blk_rq_init(struct request_queue *q, struct request *rq) memset(rq, 0, sizeof(*rq)); INIT_LIST_HEAD(&rq->queuelist); + /*dylanchang, 2019/4/30, add foreground task io opt*/ + INIT_LIST_HEAD(&rq->fg_list); INIT_LIST_HEAD(&rq->timeout_list); rq->cpu = -1; rq->q = q; @@ -828,6 +834,9 @@ static void blk_rq_timed_out_timer(unsigned long data) kblockd_schedule_work(&q->timeout_work); } +/*dylanchang, 2019/4/30, add foreground task io opt*/ +#define FG_CNT_DEF 20 +#define BOTH_CNT_DEF 10 struct request_queue *blk_alloc_queue_node(gfp_t gfp_mask, int node_id) { struct request_queue *q; @@ -857,6 +866,11 @@ struct request_queue *blk_alloc_queue_node(gfp_t gfp_mask, int node_id) (VM_MAX_READAHEAD * 1024) / PAGE_SIZE; q->backing_dev_info->capabilities = BDI_CAP_CGROUP_WRITEBACK; q->backing_dev_info->name = "block"; +/*dylanchang, 2019/4/30, add foreground task io opt*/ + q->fg_count_max = FG_CNT_DEF; + q->both_count_max = BOTH_CNT_DEF; + q->fg_count = FG_CNT_DEF; + q->both_count = BOTH_CNT_DEF; q->node = node_id; setup_timer(&q->backing_dev_info->laptop_mode_wb_timer, @@ -864,6 +878,8 @@ struct request_queue *blk_alloc_queue_node(gfp_t gfp_mask, int node_id) setup_timer(&q->timeout, blk_rq_timed_out_timer, (unsigned long) q); INIT_WORK(&q->timeout_work, NULL); INIT_LIST_HEAD(&q->queue_head); +/*dylanchang, 2019/4/30, add foreground task io opt*/ + INIT_LIST_HEAD(&q->fg_head); INIT_LIST_HEAD(&q->timeout_list); INIT_LIST_HEAD(&q->icq_list); #ifdef CONFIG_BLK_CGROUP @@ -1797,7 +1813,9 @@ unsigned int blk_plug_queued_count(struct request_queue *q) void blk_init_request_from_bio(struct request *req, struct bio *bio) { struct io_context *ioc = rq_ioc(bio); - +/*dylanchang, 2019/4/30, add foreground task io opt*/ + if (bio->bi_opf & REQ_FG) + req->cmd_flags |= REQ_FG; if (bio->bi_opf & REQ_RAHEAD) req->cmd_flags |= REQ_FAILFAST_MASK; @@ -2271,6 +2289,83 @@ blk_qc_t generic_make_request(struct bio *bio) } EXPORT_SYMBOL(generic_make_request); +/*dylanchang, 2019/4/30, add foreground task io opt*/ +#define SYSTEM_APP_UID 1000 +static bool is_system_uid(struct task_struct *t) +{ + int cur_uid; + + cur_uid = task_uid(t).val; + if (cur_uid == SYSTEM_APP_UID) + return true; + + return false; +} + +static bool is_zygote_process(struct task_struct *t) +{ + const struct cred *tcred = __task_cred(t); + + struct task_struct *first_child = NULL; + + if (t->children.next && t->children.next != + (struct list_head *)&t->children.next) + first_child = + container_of(t->children.next, + struct task_struct, sibling); + if (!strcmp(t->comm, "main") && (tcred->uid.val == 0) && + (t->parent != 0 && !strcmp(t->parent->comm, "init"))) + return true; + else + return false; + return false; +} + +static bool is_system_process(struct task_struct *t) +{ + if (is_system_uid(t)) { + if (t->group_leader && ( + !strncmp(t->group_leader->comm, "system_server", 13) || + !strncmp(t->group_leader->comm, "surfaceflinger", 14) || + !strncmp(t->group_leader->comm, "servicemanager", 14) || + !strncmp(t->group_leader->comm, "ndroid.systemui", 15))) + return true; + } + return false; +} + +bool is_critial_process(struct task_struct *t) +{ + if (is_zygote_process(t) || is_system_process(t)) + return true; + + return false; +} + +bool is_filter_process(struct task_struct *t) +{ + if (!strncmp(t->comm, "logcat", TASK_COMM_LEN)) + return true; + + return false; +} +static bool high_prio_for_task(struct task_struct *t) +{ + int cur_uid; + + if (!sysctl_fg_io_opt) + return false; + + cur_uid = task_uid(t).val; + if ((is_fg(cur_uid) && !is_system_uid(t) && + !is_filter_process(t)) || + is_critial_process(t)) + return true; + + return false; +} + + /** * submit_bio - submit a bio to the block device layer for I/O * @bio: The &struct bio which describes the I/O @@ -2310,7 +2405,16 @@ blk_qc_t submit_bio(struct bio *bio) bio_devname(bio, b), count); } } - +/*dylanchang, 2019/4/30, add foreground task io opt*/ +#ifdef CONFIG_MEMPLUS + if (current_is_swapind()) + bio->bi_opf |= REQ_FG; + else if (high_prio_for_task(current)) + bio->bi_opf |= REQ_FG; +#else + if (high_prio_for_task(current)) + bio->bi_opf |= REQ_FG; +#endif return generic_make_request(bio); } EXPORT_SYMBOL(submit_bio); @@ -2663,6 +2767,10 @@ static void blk_dequeue_request(struct request *rq) list_del_init(&rq->queuelist); +/*dylanchang, 2019/4/30, add foreground task io opt*/ + if (sysctl_fg_io_opt && (rq->cmd_flags & REQ_FG)) + list_del_init(&rq->fg_list); + /* * the time frame between a request being removed from the lists * and to it is freed is accounted as io that is in progress at diff --git a/block/blk-flush.c b/block/blk-flush.c index 6603352879e7..86ef012d5f58 100644 --- a/block/blk-flush.c +++ b/block/blk-flush.c @@ -138,10 +138,15 @@ static bool blk_flush_queue_rq(struct request *rq, bool add_front) blk_mq_add_to_requeue_list(rq, add_front, true); return false; } else { - if (add_front) + +/*dylanchang, 2019/4/30, add foreground task io opt*/ + if (add_front) { list_add(&rq->queuelist, &rq->q->queue_head); - else + queue_throtl_add_request(rq->q, rq, true); + } else { list_add_tail(&rq->queuelist, &rq->q->queue_head); + queue_throtl_add_request(rq->q, rq, false); + } return true; } } @@ -465,7 +470,11 @@ void blk_insert_flush(struct request *rq) if (q->mq_ops) blk_mq_sched_insert_request(rq, false, true, false, false); else +/*dylanchang, 2019/4/30, add foreground task io opt*/ + { list_add_tail(&rq->queuelist, &q->queue_head); + queue_throtl_add_request(q, rq, false); + } return; } diff --git a/block/blk-sysfs.c b/block/blk-sysfs.c index e54be402899d..92302b196695 100644 --- a/block/blk-sysfs.c +++ b/block/blk-sysfs.c @@ -111,6 +111,49 @@ queue_ra_store(struct request_queue *q, const char *page, size_t count) return ret; } +/*dylanchang, 2019/4/30, add foreground task io opt*/ +static ssize_t queue_fgio_show(struct request_queue *q, char *page) +{ + int cnt = q->fg_count_max; + + return queue_var_show(cnt, (page)); +} + +static ssize_t +queue_fgio_store(struct request_queue *q, const char *page, size_t count) +{ + unsigned long cnt; + ssize_t ret = queue_var_store(&cnt, page, count); + + if (ret < 0) + return ret; + + q->fg_count_max = cnt; + + return ret; +} +static ssize_t queue_bothio_show(struct request_queue *q, char *page) +{ + int cnt = q->both_count_max; + + return queue_var_show(cnt, (page)); +} + +static ssize_t +queue_bothio_store(struct request_queue *q, const char *page, size_t count) +{ + unsigned long cnt; + ssize_t ret = queue_var_store(&cnt, page, count); + + if (ret < 0) + return ret; + + q->both_count_max = cnt; + + return ret; +} + + static ssize_t queue_max_sectors_show(struct request_queue *q, char *page) { int max_sectors_kb = queue_max_sectors(q) >> 1; @@ -517,6 +560,20 @@ static struct queue_sysfs_entry queue_ra_entry = { .store = queue_ra_store, }; +/*dylanchang, 2019/4/30, add foreground task io opt*/ +static struct queue_sysfs_entry queue_fgio_entry = { + .attr = {.name = "fg_io_cnt_max", .mode = 0644 }, + .show = queue_fgio_show, + .store = queue_fgio_store, +}; + +static struct queue_sysfs_entry queue_bothio_entry = { + .attr = {.name = "both_io_cnt_max", .mode = 0644 }, + .show = queue_bothio_show, + .store = queue_bothio_store, +}; + + static struct queue_sysfs_entry queue_max_sectors_entry = { .attr = {.name = "max_sectors_kb", .mode = S_IRUGO | S_IWUSR }, .show = queue_max_sectors_show, @@ -690,6 +747,9 @@ static struct queue_sysfs_entry throtl_sample_time_entry = { static struct attribute *default_attrs[] = { &queue_requests_entry.attr, &queue_ra_entry.attr, +/*dylanchang, 2019/4/30, add foreground task io opt*/ + &queue_fgio_entry.attr, + &queue_bothio_entry.attr, &queue_max_hw_sectors_entry.attr, &queue_max_sectors_entry.attr, &queue_max_segments_entry.attr, diff --git a/block/blk.h b/block/blk.h index b2c287c2c6a3..4a1ec390a358 100644 --- a/block/blk.h +++ b/block/blk.h @@ -149,6 +149,12 @@ static inline void blk_clear_rq_complete(struct request *rq) void blk_insert_flush(struct request *rq); +/*dylanchang, 2019/4/30, add foreground task io opt*/ +extern int fg_count; +extern int both_count; +extern bool fg_debug; +extern unsigned int sysctl_fg_io_opt; + static inline struct request *__elv_next_request(struct request_queue *q) { struct request *rq; @@ -158,7 +164,32 @@ static inline struct request *__elv_next_request(struct request_queue *q) while (1) { if (!list_empty(&q->queue_head)) { - rq = list_entry_rq(q->queue_head.next); +/*dylanchang, 2019/4/30, add foreground task io opt*/ + if (unlikely(!sysctl_fg_io_opt)) + rq = list_entry_rq(q->queue_head.next); + else { +#ifdef CONFIG_PM + if (!list_empty(&q->fg_head) && + q->fg_count > 0 && + (q->rpm_status == RPM_ACTIVE)) { +#else + if (!list_empty(&q->fg_head) && + q->fg_count > 0) { +#endif + rq = list_entry( + q->fg_head.next, + struct request, + fg_list); + q->fg_count--; + } else if (q->both_count > 0) { + rq = list_entry_rq(q->queue_head.next); + q->both_count--; + } else { + q->fg_count = q->fg_count_max; + q->both_count = q->both_count_max; + rq = list_entry_rq(q->queue_head.next); + } + } return rq; } diff --git a/block/elevator.c b/block/elevator.c index 2346c5b53b93..bda37816da9b 100644 --- a/block/elevator.c +++ b/block/elevator.c @@ -204,6 +204,8 @@ int elevator_init(struct request_queue *q, char *name) return 0; INIT_LIST_HEAD(&q->queue_head); +/*dylanchang, 2019/4/30, add foreground task io opt*/ + INIT_LIST_HEAD(&q->fg_head); q->last_merge = NULL; q->end_sector = 0; q->boundary_rq = NULL; @@ -415,6 +417,8 @@ void elv_dispatch_sort(struct request_queue *q, struct request *rq) } list_add(&rq->queuelist, entry); +/*dylanchang, 2019/4/30, add foreground task io opt*/ + queue_throtl_add_request(q, rq, false); } EXPORT_SYMBOL(elv_dispatch_sort); @@ -435,6 +439,8 @@ void elv_dispatch_add_tail(struct request_queue *q, struct request *rq) q->end_sector = rq_end_sector(rq); q->boundary_rq = rq; list_add_tail(&rq->queuelist, &q->queue_head); +/*dylanchang, 2019/4/30, add foreground task io opt*/ + queue_throtl_add_request(q, rq, false); } EXPORT_SYMBOL(elv_dispatch_add_tail); @@ -663,12 +669,16 @@ void __elv_add_request(struct request_queue *q, struct request *rq, int where) case ELEVATOR_INSERT_FRONT: rq->rq_flags |= RQF_SOFTBARRIER; list_add(&rq->queuelist, &q->queue_head); +/*dylanchang, 2019/4/30, add foreground task io opt*/ + queue_throtl_add_request(q, rq, true); break; case ELEVATOR_INSERT_BACK: rq->rq_flags |= RQF_SOFTBARRIER; elv_drain_elevator(q); list_add_tail(&rq->queuelist, &q->queue_head); +/*dylanchang, 2019/4/30, add foreground task io opt*/ + queue_throtl_add_request(q, rq, false); /* * We kick the queue here for the following reasons. * - The elevator might have returned NULL previously diff --git a/coretech/.gitignore b/coretech/.gitignore new file mode 100644 index 000000000000..ab5c102e72c4 --- /dev/null +++ b/coretech/.gitignore @@ -0,0 +1,21 @@ +uxcore/* +!uxcore/Makefile +!uxcore/opchain_helper.c +!uxcore/opchain_helper.h +!uxcore/opchain_define.h +memplus/* +!memplus/memplus_helper.c +!memplus/memplus_helper.h +!memplus/Makefile +smartboost/* +!smartboost/smartboost_helper.c +!smartboost/smartboost_helper.h +!smartboost/Makefile +defrag/* +!defrag/defrag_helper.c +!defrag/defrag_helper.h +!defrag/Makefile +fsc/* +houston/* +control_center/* +aigov/* diff --git a/coretech/Kconfig b/coretech/Kconfig new file mode 100644 index 000000000000..b363e86ed90c --- /dev/null +++ b/coretech/Kconfig @@ -0,0 +1,34 @@ +config OPCHAIN + default n + bool "Oneplus CoreTech helper, used for opchain module" +config MEMPLUS + default n + bool "memory+ feature" + help + Memory+ feature +config SMART_BOOST + bool "support smart boost feature" + default n + help + this feature allow memory used by recent-app stay in kernel. +config DEFRAG + default n + bool "anti-defragment feature" + help + anti-defragment feature. +config FSC + default n + bool "system layer file status cache" + help + To cache absence file and avoid stat call storm +config HOUSTON + default n + bool "to collect system-wide and pmu data" + help + Realtime temperature monitor +config CONTROL_CENTER + default n + bool "control center" +config AIGOV + default n + bool "A governor which using ai predicted info as input" diff --git a/coretech/Makefile b/coretech/Makefile new file mode 100644 index 000000000000..1ef1c68bf567 --- /dev/null +++ b/coretech/Makefile @@ -0,0 +1,28 @@ +obj-$(CONFIG_OPCHAIN) += uxcore/ +CORE_PATH = $(KBUILD_SRC)/coretech/uxcore/core +ifeq ($(CORE_PATH),$(wildcard $(CORE_PATH))) +obj-$(CONFIG_OPCHAIN) += uxcore/core/ +endif + +obj-$(CONFIG_MEMPLUS) += memplus/ +CORE_PATH = $(KBUILD_SRC)/coretech/memplus/core +ifeq ($(CORE_PATH),$(wildcard $(CORE_PATH))) +obj-$(CONFIG_MEMPLUS) += memplus/core/ +endif + +obj-$(CONFIG_SMART_BOOST) += smartboost/ +CORE_PATH = $(KBUILD_SRC)/coretech/smartboost/core +ifeq ($(CORE_PATH),$(wildcard $(CORE_PATH))) +obj-$(CONFIG_SMART_BOOST) += smartboost/core/ +endif + +obj-$(CONFIG_DEFRAG) += defrag/ +CORE_PATH = $(KBUILD_SRC)/coretech/defrag/core +ifeq ($(CORE_PATH),$(wildcard $(CORE_PATH))) +obj-$(CONFIG_DEFRAG) += defrag/core/ +endif + +obj-$(CONFIG_FSC) += fsc/ +obj-$(CONFIG_HOUSTON) += houston/ +obj-$(CONFIG_CONTROL_CENTER) += control_center/ +obj-$(CONFIG_AIGOV) += aigov/ diff --git a/coretech/defrag/Makefile b/coretech/defrag/Makefile new file mode 100644 index 000000000000..a1e70c67e401 --- /dev/null +++ b/coretech/defrag/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_DEFRAG) += defrag_helper.o diff --git a/coretech/defrag/defrag_helper.c b/coretech/defrag/defrag_helper.c new file mode 100644 index 000000000000..6538bfdbea34 --- /dev/null +++ b/coretech/defrag/defrag_helper.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct defrag_cb_set defrag_cbs; +atomic64_t fp_order_usage[MAX_ORDER] = {ATOMIC64_INIT(0)}; +atomic64_t fp_order_fail[MAX_ORDER] = {ATOMIC64_INIT(0)}; + +/* calling functions */ +struct page *defrag_alloc(struct zone *zone, unsigned long flags, + int migratetype, int order) +{ + if (defrag_cbs.defrag_alloc_cb) + return defrag_cbs.defrag_alloc_cb(zone, + flags, migratetype, order); + return NULL; +} + +long defrag_calc(struct zone *zone, int order, int alloc_flag) +{ + if (likely(defrag_cbs.defrag_calc_cb)) + return defrag_cbs.defrag_calc_cb(zone, order, alloc_flag); + else + return defrag_zone_free_size(zone); +} + +bool defrag_check_alloc_flag(unsigned int alloc_flags, int order) +{ + if (defrag_cbs.defrag_check_alloc_flag_cb) + return defrag_cbs.defrag_check_alloc_flag_cb(alloc_flags, + order); + return false; +} + +void defrag_register_cb_set(struct defrag_cb_set *cbs) +{ + defrag_cbs = *cbs; +} + +void defrag_unregister_cb_set(void) +{ + defrag_cbs.defrag_alloc_cb = NULL; + defrag_cbs.defrag_check_alloc_flag_cb = NULL; + defrag_cbs.defrag_calc_cb = NULL; +} diff --git a/coretech/memplus/Makefile b/coretech/memplus/Makefile new file mode 100644 index 000000000000..2bff8d58cde3 --- /dev/null +++ b/coretech/memplus/Makefile @@ -0,0 +1 @@ +obj-y += memplus_helper.o diff --git a/coretech/memplus/memplus_helper.c b/coretech/memplus/memplus_helper.c new file mode 100644 index 000000000000..886126e9951a --- /dev/null +++ b/coretech/memplus/memplus_helper.c @@ -0,0 +1,61 @@ +#include +#include + +static struct memplus_cb_set cb_set; +#define PF_NO_TAIL(page, enforce) ({ \ + VM_BUG_ON_PGFLAGS(enforce && PageTail(page), page); \ + compound_head(page); }) + +bool memplus_enabled(void) +{ + if (cb_set.memplus_enabled_cb) + return cb_set.memplus_enabled_cb(); + return false; +} +bool __memplus_enabled(void) +{ + if (cb_set.__memplus_enabled_cb) + return cb_set.__memplus_enabled_cb(); + return false; +} +bool current_is_swapind(void) +{ + if (cb_set.current_is_swapind_cb) + return cb_set.current_is_swapind_cb(); + return false; +} + +void memplus_move_swapcache_to_anon_lru(struct page *page) +{ + if (cb_set.memplus_move_swapcache_to_anon_lru_cb) + cb_set.memplus_move_swapcache_to_anon_lru_cb(page); + else + clear_bit(PG_swapcache, &(PF_NO_TAIL(page, 1))->flags); +} +void memplus_move_anon_to_swapcache_lru(struct page *page) +{ + if (cb_set.memplus_move_anon_to_swapcache_lru_cb) + cb_set.memplus_move_anon_to_swapcache_lru_cb(page); + else + set_bit(PG_swapcache, &(PF_NO_TAIL(page, 1))->flags); +} +void memplus_state_check(bool legacy, int oom_adj, + struct task_struct *task, int type, int update) +{ + if (cb_set.memplus_state_check_cb) + cb_set.memplus_state_check_cb(legacy, + oom_adj, task, type, update); +} +bool memplus_check_isolate_page(struct page *page) +{ + if (cb_set.memplus_check_isolate_page_cb) + return cb_set.memplus_check_isolate_page_cb(page); + return false; +} + +void register_cb_set(struct memplus_cb_set *set) +{ + cb_set = *set; +} + +#undef PF_NO_TAIL diff --git a/coretech/smartboost/Makefile b/coretech/smartboost/Makefile new file mode 100644 index 000000000000..6091ef65fe33 --- /dev/null +++ b/coretech/smartboost/Makefile @@ -0,0 +1 @@ +obj-y += smartboost_helper.o diff --git a/coretech/smartboost/smartboost_helper.c b/coretech/smartboost/smartboost_helper.c new file mode 100644 index 000000000000..6d5019c223c1 --- /dev/null +++ b/coretech/smartboost/smartboost_helper.c @@ -0,0 +1,38 @@ +#include +#include + +struct smb_cb_set smb_cbs; + +bool smb_uid_lru_add(struct page *page) +{ + if (smb_cbs.smb_uid_lru_add_cb) + return smb_cbs.smb_uid_lru_add_cb(page); + else + return false; +} + +unsigned long smb_isolate_list_or_putbcak(struct list_head *page_list, + struct lruvec *lruvec, struct pglist_data *pgdat, int priority, + bool enough_list_reclaimed) +{ + if (smb_cbs.smb_isolate_list_or_putbcak_cb) + return smb_cbs.smb_isolate_list_or_putbcak_cb(page_list, + lruvec, pgdat, priority, enough_list_reclaimed); + else + return 0; +} + +bool smb_update_uid_lru_size(struct page *page, + struct lruvec *lruvec, enum lru_list lru) +{ + if (smb_cbs.smb_update_uid_lru_size_cb) + return smb_cbs.smb_update_uid_lru_size_cb(page, lruvec, lru); + else + return false; +} + +void smb_register_cb_set(struct smb_cb_set *set) +{ + smb_cbs = *set; +} + diff --git a/coretech/uxcore/Makefile b/coretech/uxcore/Makefile new file mode 100755 index 000000000000..6a11f257f930 --- /dev/null +++ b/coretech/uxcore/Makefile @@ -0,0 +1 @@ +obj-y += opchain_helper.o diff --git a/coretech/uxcore/opchain_define.h b/coretech/uxcore/opchain_define.h new file mode 100644 index 000000000000..27e359c838b6 --- /dev/null +++ b/coretech/uxcore/opchain_define.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _LINUX_OPCHAIN_DEFINE_H +#define _LINUX_OPCHAIN_DEFINE_H + +#define UX_DEBUG 0 +#define UTASK 0 +#define UT_CLK_BASE 0x01 +#define UT_ETASK 0x02 +#define UT_LATEST_ONE 0x04 +#define UT_PERF_TOP 0x08 +#define UT_FORE (UT_CLK_BASE | UT_ETASK) + +#define OP_CLAIM_S -1 +#define OP_PATH_SLAVE -4 +#define OP_PATH_CLAIM -3 +#define OP_PATH_NORMAL -2 +#define OP_PATH_OCCUPIED -1 +#define MIN_POWER_CPU 0 + +#define ONESEC_NANO 1000000000 + +#if 1 +/* for MSM8998, SDM845*/ +#define FIRST_BIG_CORE 4 +#define NUMS_CPU 8 +#define CPU_VIRTUAL_PLUG_IN(i) (opc_cpu_active(i) && !opc_cpu_isolated(i)) +#else +/* for MSM8996*/ +#define FIRST_BIG_CORE 2 +#define NUMS_CPU 4 +#define CPU_VIRTUAL_PLUG_IN(i) (opc_cpu_active(i)) +#endif + +struct opchain_cb { + unsigned int (*is_opc_task_t)(void *rq, void *t, int type); + int (*opc_binder_pass_t)(void *rq, void* cur, unsigned int dsize, unsigned int *data, int send); + void (*opc_task_switch_t)(unsigned int enqueue, int cpu, void *p, void *rq, unsigned long long clock); + int (*opc_get_claim_on_cpu_t)(int cpu, void *rq); + unsigned int (*opc_get_claims_t)(void **rqs); + int (*opc_select_path_t)(void **rqs, void *w_rq, void *t_rq, void *cur, void *t, int prev_cpu); + unsigned long (*opc_cpu_util_t)(unsigned long util, int cpu, void *t, void *rq, int op_path); + void (*opc_add_to_chain_t)(void *rq, void *t); + int (*opc_check_uxtop_cpu_t)(int uxtop, int cpu); +}; +#endif diff --git a/coretech/uxcore/opchain_helper.c b/coretech/uxcore/opchain_helper.c new file mode 100644 index 000000000000..6bc6673be351 --- /dev/null +++ b/coretech/uxcore/opchain_helper.c @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2015-2017, The OnePlus corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "../kernel/sched/sched.h" +#include "opchain_define.h" + +// tedlin@ASTI 2019/06/12 add for CONFIG_HOUSTON +#include + +#define t_rq(t) task_rq(t) +#define c_rq(cpu) cpu_rq(cpu) + +struct opchain_cb uxcore_api = {NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}; +EXPORT_SYMBOL(uxcore_api); + +unsigned int *opc_boost_tl; +EXPORT_SYMBOL(opc_boost_tl); + +unsigned int *opc_boost; +EXPORT_SYMBOL(opc_boost); + +void opc_set_boost(unsigned int val) +{ + if (opc_boost) + *opc_boost = val; +} +EXPORT_SYMBOL(opc_set_boost); + +bool is_opc_task(struct task_struct *t, int type) +{ + if (uxcore_api.is_opc_task_t) + return uxcore_api.is_opc_task_t((void *)t_rq(t), (void *)t, type); + return 0; +} +EXPORT_SYMBOL(is_opc_task); + +void opc_binder_pass(size_t data_size, uint32_t *data, int send) +{ + if (uxcore_api.opc_binder_pass_t) { + if (uxcore_api.opc_binder_pass_t((void *)t_rq(current), (void *)current, data_size, data, send)) +// tedlin@ASTI 2019/06/12 add for CONFIG_HOUSTON + ht_perf_notify(); + } +} +EXPORT_SYMBOL(opc_binder_pass); + +void opc_task_switch(unsigned int enqueue, int cpu, struct task_struct *p, u64 clock) { + if (uxcore_api.opc_task_switch_t) + uxcore_api.opc_task_switch_t(enqueue, cpu, (void *)p, (void *)t_rq(p), clock); +} +EXPORT_SYMBOL(opc_task_switch); + +int opc_get_claim_on_cpu(int cpu) +{ + if (uxcore_api.opc_get_claim_on_cpu_t) + return uxcore_api.opc_get_claim_on_cpu_t(cpu, (void *)c_rq(cpu)); + return 0; +} +EXPORT_SYMBOL(opc_get_claim_on_cpu); + +unsigned int opc_get_claims(void) +{ + void *rqs[NUMS_CPU]; + int idx; + + if (uxcore_api.opc_get_claims_t) { + for (idx = 0; idx < NUMS_CPU; idx++) { + rqs[idx] = (void *)c_rq(idx); + } + return uxcore_api.opc_get_claims_t(rqs); + } + return 0; +} +EXPORT_SYMBOL(opc_get_claims); + +int opc_select_path(struct task_struct *cur, struct task_struct *t, int prev_cpu) +{ + void *rqs[NUMS_CPU]; + int idx; + + if (uxcore_api.opc_select_path_t) { + for (idx = 0; idx < NUMS_CPU; idx++) { + rqs[idx] = (void *)c_rq(idx); + } + return uxcore_api.opc_select_path_t(rqs, (void *)t_rq(cur), (void *)t_rq(t), (void *)cur, (void *)t, prev_cpu); + } + return OP_PATH_NORMAL; +} +EXPORT_SYMBOL(opc_select_path); + +unsigned long opc_cpu_util(unsigned long util, int cpu, struct task_struct *t, int op_path) +{ + if (uxcore_api.opc_cpu_util_t) + return uxcore_api.opc_cpu_util_t(util, cpu, (void *)t, (void *)c_rq(cpu), op_path); + return util; +} +EXPORT_SYMBOL(opc_cpu_util); + +void opc_add_to_chain(struct task_struct *t) +{ + if (uxcore_api.opc_add_to_chain_t) + uxcore_api.opc_add_to_chain_t((void *)t_rq(t), (void *)t); +} +EXPORT_SYMBOL(opc_add_to_chain); + +bool opc_check_uxtop_cpu(int uxtop, int cpu) +{ + if (uxcore_api.opc_check_uxtop_cpu_t) + return uxcore_api.opc_check_uxtop_cpu_t(uxtop, cpu); + return true; +} +EXPORT_SYMBOL(opc_check_uxtop_cpu); + +unsigned long __init opc_get_orig_capacity(int cpu) +{ + return cpu_rq(cpu)->cpu_capacity_orig; +} +EXPORT_SYMBOL(opc_get_orig_capacity); + +bool opc_utask_slave(struct task_struct *t) +{ + return t->utask_slave; +} +EXPORT_SYMBOL(opc_utask_slave); + +void __exit opc_exit_module(void) +{ + uxcore_api.opc_binder_pass_t = NULL; + uxcore_api.is_opc_task_t = NULL; + uxcore_api.opc_task_switch_t = NULL; + uxcore_api.opc_get_claim_on_cpu_t = NULL; + uxcore_api.opc_get_claims_t = NULL; + uxcore_api.opc_select_path_t = NULL; + uxcore_api.opc_cpu_util_t = NULL; + uxcore_api.opc_add_to_chain_t = NULL; + uxcore_api.opc_check_uxtop_cpu_t = NULL; + opc_boost_tl = NULL; + opc_boost = NULL; +} +EXPORT_SYMBOL(opc_exit_module); diff --git a/coretech/uxcore/opchain_helper.h b/coretech/uxcore/opchain_helper.h new file mode 100644 index 000000000000..5f6eeffa6dd1 --- /dev/null +++ b/coretech/uxcore/opchain_helper.h @@ -0,0 +1,41 @@ +#ifndef _LINUX_OPCHAIN_HELPER_H +#define _LINUX_OPCHAIN_HELPER_H +#include "opchain_define.h" + +#ifdef CONFIG_OPCHAIN +extern struct opchain_cb uxcore_api; +extern void opc_binder_pass(size_t data_size, uint32_t *data, int send); +extern bool is_opc_task(struct task_struct *t, int type); +extern void opc_task_switch(bool enqueue, int cpu, struct task_struct *p, u64 clock); +extern int opc_get_claim_on_cpu(int cpu); +extern unsigned int opc_get_claims(void); +extern int opc_select_path(struct task_struct *cur, struct task_struct *t, int prev_cpu); +extern unsigned long opc_cpu_util(unsigned long util, int cpu, struct task_struct *t, int op_path); +extern bool opc_fps_check(int lvl); +extern void *opc_task_rq(void *t); +extern struct rq *opc_cpu_rq(int cpu); +extern unsigned int opc_task_load(struct task_struct *p); +extern int opc_cpu_active(int cpu); +extern int opc_cpu_isolated(int cpu); +bool opc_check_uxtop_cpu(int uxtop, int cpu); +bool opc_utask_slave(struct task_struct *t); +extern unsigned long __init opc_get_orig_capacity(int cpu); +extern void __exit opc_exit_module(void); +extern void opc_set_boost(unsigned int val); +#define UTASK_SLAVE(t) opc_utask_slave(t) + +#else +#define UTASK_SLAVE(t) 0 +static inline void opc_binder_pass(size_t data_size, uint32_t *data, int send) {} +static inline bool is_opc_task(struct task_struct *t, int type) { return 0; } +static inline void opc_task_switch(bool enqueue, int cpu, struct task_struct *p, u64 clock) {} +static inline int opc_get_claim_on_cpu(int cpu) { return 0; } +static inline unsigned int opc_get_claims(void) { return 0; } +static inline int opc_select_path(struct task_struct *cur, struct task_struct *t, int prev_cpu) { return OP_PATH_NORMAL; } +static inline unsigned long opc_cpu_util(unsigned long util, int cpu, struct task_struct *t, int op_path) { return util; } +static inline bool opc_fps_check(int lvl) { return false;} +static inline void opc_add_to_chain(struct task_struct *t) {} +static inline bool opc_check_uxtop_cpu(int uxtop, int cpu) { return true; } +static inline void opc_set_boost(unsigned int val) {}; +#endif +#endif diff --git a/drivers/Kconfig b/drivers/Kconfig index ed96eb7d8ba2..5d43bd1fbf0b 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -221,4 +221,14 @@ source "drivers/sensors/Kconfig" source "drivers/esoc/Kconfig" +source "drivers/oneplus/Kconfig" + +source "drivers/param_read_write/Kconfig" + +source "drivers/step_motor/Kconfig" + +source "drivers/tri_state_key/Kconfig" + +source "drivers/oem_debug/Kconfig" +source "drivers/vibrator/Kconfig" endmenu diff --git a/drivers/Makefile b/drivers/Makefile index cef0160448bc..f8939274059d 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -188,5 +188,12 @@ obj-$(CONFIG_TEE) += tee/ obj-$(CONFIG_MULTIPLEXER) += mux/ obj-$(CONFIG_SENSORS_SSC) += sensors/ obj-$(CONFIG_ESOC) += esoc/ +obj-y += oneplus/ +obj-y += param_read_write/ +obj-y += step_motor/ +obj-$(CONFIG_TRI_STATE_KEY) += tri_state_key/ +obj-$(CONFIG_AW8697_HAPTIC) += vibrator/ +obj-y += oem_debug/ +obj-y += infrared_proximity/infrared_power_control.o # GNSS driver obj-$(CONFIG_GNSS_SIRF) += gnsssirf/ diff --git a/drivers/android/binder.c b/drivers/android/binder.c index 64824dc8fc22..b9b7f6b5279a 100644 --- a/drivers/android/binder.c +++ b/drivers/android/binder.c @@ -3324,8 +3324,13 @@ static void binder_transaction(struct binder_proc *proc, sg_buf_offset = ALIGN(off_end_offset, sizeof(void *)); sg_buf_end_offset = sg_buf_offset + extra_buffers_size; off_min = 0; + + binder_alloc_pass_binder_buffer(&target_proc->alloc, + t->buffer, tr->data_size); + for (buffer_offset = off_start_offset; buffer_offset < off_end_offset; buffer_offset += sizeof(binder_size_t)) { + struct binder_object_header *hdr; size_t object_size; struct binder_object object; diff --git a/drivers/android/binder_alloc.c b/drivers/android/binder_alloc.c index 7b8a4bea8650..3721980caa46 100644 --- a/drivers/android/binder_alloc.c +++ b/drivers/android/binder_alloc.c @@ -32,6 +32,7 @@ #include #include "binder_alloc.h" #include "binder_trace.h" +#include <../coretech/uxcore/opchain_helper.h> struct list_lru binder_alloc_lru; @@ -1117,6 +1118,21 @@ binder_alloc_copy_user_to_buffer(struct binder_alloc *alloc, return 0; } +void binder_alloc_pass_binder_buffer(struct binder_alloc *alloc, + struct binder_buffer *buffer, + binder_size_t buffer_size) +{ + struct page *page; + pgoff_t pgoff; + void *kptr; + + page = binder_alloc_get_page(alloc, buffer, + 0, &pgoff); + kptr = kmap_atomic(page) + pgoff; + opc_binder_pass(buffer_size, kptr, 1); + kunmap_atomic(kptr); +} + static void binder_alloc_do_buffer_copy(struct binder_alloc *alloc, bool to_buffer, struct binder_buffer *buffer, diff --git a/drivers/android/binder_alloc.h b/drivers/android/binder_alloc.h index b60d161b7a7a..c44797de7f44 100644 --- a/drivers/android/binder_alloc.h +++ b/drivers/android/binder_alloc.h @@ -161,6 +161,10 @@ binder_alloc_get_free_async_space(struct binder_alloc *alloc) return free_async_space; } +void binder_alloc_pass_binder_buffer(struct binder_alloc *alloc, + struct binder_buffer *buffer, + binder_size_t buffer_size); + unsigned long binder_alloc_copy_user_to_buffer(struct binder_alloc *alloc, struct binder_buffer *buffer, diff --git a/drivers/base/power/wakeup.c b/drivers/base/power/wakeup.c index 79cf4c0fb2b7..8114e8883cc7 100644 --- a/drivers/base/power/wakeup.c +++ b/drivers/base/power/wakeup.c @@ -22,6 +22,8 @@ #include #include "power.h" +#include +#include /* * If set, the suspend/hibernate code will abort transitions to a sleep state @@ -71,6 +73,10 @@ static struct wakeup_source deleted_ws = { .lock = __SPIN_LOCK_UNLOCKED(deleted_ws.lock), }; +#define WORK_TIMEOUT (60*1000) +static void ws_printk(struct work_struct *work); +static DECLARE_DELAYED_WORK(ws_printk_work, ws_printk); + /** * wakeup_source_prepare - Prepare a new wakeup source for initialization. * @ws: Wakeup source to prepare. @@ -856,7 +862,7 @@ void pm_print_active_wakeup_sources(void) srcuidx = srcu_read_lock(&wakeup_srcu); list_for_each_entry_rcu(ws, &wakeup_sources, entry) { if (ws->active) { - pr_debug("active wakeup source: %s\n", ws->name); + pr_info("active wakeup source: %s\n", ws->name); active = 1; } else if (!active && (!last_activity_ws || @@ -867,12 +873,30 @@ void pm_print_active_wakeup_sources(void) } if (!active && last_activity_ws) - pr_debug("last active wakeup source: %s\n", + pr_info("last active wakeup source: %s\n", last_activity_ws->name); srcu_read_unlock(&wakeup_srcu, srcuidx); } EXPORT_SYMBOL_GPL(pm_print_active_wakeup_sources); +static void ws_printk(struct work_struct *work) +{ + pm_print_active_wakeup_sources(); + queue_delayed_work(system_freezable_wq, + &ws_printk_work, msecs_to_jiffies(WORK_TIMEOUT)); +} + +void pm_print_active_wakeup_sources_queue(bool on) +{ + if (on) { + queue_delayed_work(system_freezable_wq, &ws_printk_work, + msecs_to_jiffies(WORK_TIMEOUT)); + } else { + cancel_delayed_work(&ws_printk_work); + } +} +EXPORT_SYMBOL_GPL(pm_print_active_wakeup_sources_queue); + /** * pm_wakeup_pending - Check if power transition in progress should be aborted. * @@ -936,6 +960,7 @@ void pm_system_irq_wakeup(unsigned int irq_number) else if (desc->action && desc->action->name) name = desc->action->name; + log_wakeup_reason(irq_number); pr_warn("%s: %d triggered %s\n", __func__, irq_number, name); diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c index 8fd08023c0f5..cc60ddfd971f 100644 --- a/drivers/base/regmap/regmap.c +++ b/drivers/base/regmap/regmap.c @@ -1651,6 +1651,9 @@ int _regmap_write(struct regmap *map, unsigned int reg, dev_info(map->dev, "%x <= %x\n", reg, val); #endif + if ( reg == 0x88E || reg == 0x88d) + dev_info(map->dev, "w:%x <= %x[%s],\n", reg, val,dev_name(map->dev)); + trace_regmap_reg_write(map, reg, val); return map->reg_write(context, reg, val); @@ -2379,6 +2382,8 @@ static int _regmap_read(struct regmap *map, unsigned int reg, if (map->dev && strcmp(dev_name(map->dev), LOG_DEVICE) == 0) dev_info(map->dev, "%x => %x\n", reg, *val); #endif + if ( reg == 0x88E || reg == 0x88d) + dev_info(map->dev, "r:%x <= %x[%s],\n", reg, val,dev_name(map->dev)); trace_regmap_reg_read(map, reg, *val); diff --git a/drivers/bus/mhi/controllers/mhi_arch_qcom.c b/drivers/bus/mhi/controllers/mhi_arch_qcom.c index 56708218081e..9be0e421fe0e 100644 --- a/drivers/bus/mhi/controllers/mhi_arch_qcom.c +++ b/drivers/bus/mhi/controllers/mhi_arch_qcom.c @@ -202,6 +202,7 @@ static void mhi_arch_esoc_ops_power_off(void *priv, unsigned int flags) struct arch_info *arch_info = mhi_dev->arch_info; struct pci_dev *pci_dev = mhi_dev->pci_dev; + MHI_LOG("Enter: mdm_crashed:%d\n", mdm_state); /* diff --git a/drivers/bus/mhi/core/mhi_init.c b/drivers/bus/mhi/core/mhi_init.c index da10001d560c..8765f1428a69 100644 --- a/drivers/bus/mhi/core/mhi_init.c +++ b/drivers/bus/mhi/core/mhi_init.c @@ -1366,7 +1366,6 @@ void mhi_unregister_mhi_controller(struct mhi_controller *mhi_cntrl) list_del(&mhi_cntrl->node); mutex_unlock(&mhi_bus.lock); } -EXPORT_SYMBOL(mhi_unregister_mhi_controller); /* set ptr to control private data */ static inline void mhi_controller_set_devdata(struct mhi_controller *mhi_cntrl, @@ -1467,7 +1466,6 @@ void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl) mhi_deinit_dev_ctxt(mhi_cntrl); mhi_cntrl->pre_init = false; } -EXPORT_SYMBOL(mhi_unprepare_after_power_down); /* match dev to drv */ static int mhi_match(struct device *dev, struct device_driver *drv) @@ -1570,7 +1568,6 @@ static int mhi_driver_probe(struct device *dev) exit_probe: mhi_device_put(mhi_dev, MHI_VOTE_DEVICE); - return ret; } diff --git a/drivers/bus/mhi/core/mhi_internal.h b/drivers/bus/mhi/core/mhi_internal.h index 8853ba4a97c4..e3aaca948dd2 100644 --- a/drivers/bus/mhi/core/mhi_internal.h +++ b/drivers/bus/mhi/core/mhi_internal.h @@ -773,6 +773,7 @@ static inline void mhi_timesync_log(struct mhi_controller *mhi_cntrl) readq_no_log(mhi_tsync->time_reg)); } + /* memory allocation methods */ static inline void *mhi_alloc_coherent(struct mhi_controller *mhi_cntrl, size_t size, diff --git a/drivers/bus/mhi/core/mhi_pm.c b/drivers/bus/mhi/core/mhi_pm.c index dd3e9bdc8744..6ecf5862cbcd 100644 --- a/drivers/bus/mhi/core/mhi_pm.c +++ b/drivers/bus/mhi/core/mhi_pm.c @@ -499,6 +499,8 @@ static int mhi_pm_mission_mode_transition(struct mhi_controller *mhi_cntrl) /* add supported devices */ mhi_create_devices(mhi_cntrl); + /* setup sysfs nodes for userspace votes */ + mhi_create_vote_sysfs(mhi_cntrl); /* setup sysfs nodes for userspace votes */ mhi_create_vote_sysfs(mhi_cntrl); @@ -913,9 +915,6 @@ void mhi_control_error(struct mhi_controller *mhi_cntrl) goto exit_control_error; } - /* notify waiters to bail out early since MHI has entered ERROR state */ - wake_up_all(&mhi_cntrl->state_event); - /* start notifying all clients who request early notification */ device_for_each_child(mhi_cntrl->dev, NULL, mhi_early_notify_device); @@ -1329,7 +1328,6 @@ int mhi_pm_fast_resume(struct mhi_controller *mhi_cntrl, bool notify_client) return 0; } -EXPORT_SYMBOL(mhi_pm_resume); int __mhi_device_get_sync(struct mhi_controller *mhi_cntrl) { diff --git a/drivers/bus/mhi/devices/mhi_netdev.c b/drivers/bus/mhi/devices/mhi_netdev.c index 145157b35ba9..d32a5f482f36 100644 --- a/drivers/bus/mhi/devices/mhi_netdev.c +++ b/drivers/bus/mhi/devices/mhi_netdev.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #define MHI_NETDEV_DRIVER_NAME "mhi_netdev" @@ -90,7 +89,6 @@ struct mhi_netdev { int alias; struct mhi_device *mhi_dev; struct mhi_netdev *rsc_dev; /* rsc linked node */ - struct mhi_netdev *rsc_parent; bool is_rsc_dev; int wake; @@ -100,26 +98,16 @@ struct mhi_netdev { struct napi_struct *napi; struct net_device *ndev; - struct list_head *recycle_pool; - int pool_size; + struct mhi_netbuf **netbuf_pool; + int pool_size; /* must be power of 2 */ + int current_index; bool chain_skb; struct mhi_net_chain *chain; - struct task_struct *alloc_task; - wait_queue_head_t alloc_event; - int bg_pool_limit; /* minimum pool size */ - int bg_pool_size; /* current size of the pool */ - struct list_head *bg_pool; - spinlock_t bg_lock; /* lock to access list */ - - struct dentry *dentry; enum MHI_DEBUG_LEVEL msg_lvl; enum MHI_DEBUG_LEVEL ipc_log_lvl; void *ipc_log; - - /* debug stats */ - u32 abuffers, kbuffers, rbuffers; }; struct mhi_netdev_priv { @@ -132,7 +120,6 @@ struct mhi_netdev_priv { */ struct mhi_netbuf { struct mhi_buf mhi_buf; /* this must be first element */ - bool recycle; void (*unmap)(struct device *dev, dma_addr_t addr, size_t size, enum dma_data_direction dir); }; @@ -177,15 +164,11 @@ static struct mhi_netbuf *mhi_netdev_alloc(struct device *dev, /* we going to use the end of page to store cached data */ netbuf = vaddr + (PAGE_SIZE << order) - sizeof(*netbuf); - netbuf->recycle = false; + mhi_buf = (struct mhi_buf *)netbuf; mhi_buf->page = page; mhi_buf->buf = vaddr; mhi_buf->len = (void *)netbuf - vaddr; - - if (!dev) - return netbuf; - mhi_buf->dma_addr = dma_map_page(dev, page, 0, mhi_buf->len, DMA_FROM_DEVICE); if (dma_mapping_error(dev, mhi_buf->dma_addr)) { @@ -204,10 +187,9 @@ static void mhi_netdev_unmap_page(struct device *dev, dma_unmap_page(dev, dma_addr, len, dir); } -static int mhi_netdev_tmp_alloc(struct mhi_netdev *mhi_netdev, - struct mhi_device *mhi_dev, - int nr_tre) +static int mhi_netdev_tmp_alloc(struct mhi_netdev *mhi_netdev, int nr_tre) { + struct mhi_device *mhi_dev = mhi_netdev->mhi_dev; struct device *dev = mhi_dev->dev.parent; const u32 order = mhi_netdev->order; int i, ret; @@ -231,73 +213,21 @@ static int mhi_netdev_tmp_alloc(struct mhi_netdev *mhi_netdev, __free_pages(mhi_buf->page, order); return ret; } - mhi_netdev->abuffers++; } return 0; } -static int mhi_netdev_queue_bg_pool(struct mhi_netdev *mhi_netdev, - struct mhi_device *mhi_dev, - int nr_tre) -{ - struct device *dev = mhi_dev->dev.parent; - int i, ret; - LIST_HEAD(head); - - spin_lock_bh(&mhi_netdev->bg_lock); - list_splice_init(mhi_netdev->bg_pool, &head); - spin_unlock_bh(&mhi_netdev->bg_lock); - - for (i = 0; i < nr_tre; i++) { - struct mhi_buf *mhi_buf = - list_first_entry_or_null(&head, struct mhi_buf, node); - struct mhi_netbuf *netbuf = (struct mhi_netbuf *)mhi_buf; - - if (!mhi_buf) - break; - - mhi_buf->dma_addr = dma_map_page(dev, mhi_buf->page, 0, - mhi_buf->len, DMA_FROM_DEVICE); - if (dma_mapping_error(dev, mhi_buf->dma_addr)) - break; - - netbuf->unmap = mhi_netdev_unmap_page; - ret = mhi_queue_transfer(mhi_dev, DMA_FROM_DEVICE, mhi_buf, - mhi_buf->len, MHI_EOT); - if (unlikely(ret)) { - MSG_ERR("Failed to queue transfer, ret:%d\n", ret); - mhi_netdev_unmap_page(dev, mhi_buf->dma_addr, - mhi_buf->len, DMA_FROM_DEVICE); - break; - } - list_del(&mhi_buf->node); - mhi_netdev->kbuffers++; - } - - /* add remaining buffers back to main pool */ - spin_lock_bh(&mhi_netdev->bg_lock); - list_splice(&head, mhi_netdev->bg_pool); - mhi_netdev->bg_pool_size -= i; - spin_unlock_bh(&mhi_netdev->bg_lock); - - - /* wake up the bg thread to allocate more buffers */ - wake_up_interruptible(&mhi_netdev->alloc_event); - - return i; -} - -static void mhi_netdev_queue(struct mhi_netdev *mhi_netdev, - struct mhi_device *mhi_dev) +static void mhi_netdev_queue(struct mhi_netdev *mhi_netdev) { + struct mhi_device *mhi_dev = mhi_netdev->mhi_dev; struct device *dev = mhi_dev->dev.parent; struct mhi_netbuf *netbuf; struct mhi_buf *mhi_buf; - struct list_head *pool = mhi_netdev->recycle_pool; + struct mhi_netbuf **netbuf_pool = mhi_netdev->netbuf_pool; int nr_tre = mhi_get_no_free_descriptors(mhi_dev, DMA_FROM_DEVICE); - int i, ret; - const int max_peek = 4; + int i, peak, cur_index, ret; + const int pool_size = mhi_netdev->pool_size - 1, max_peak = 4; MSG_VERB("Enter free_desc:%d\n", nr_tre); @@ -306,21 +236,23 @@ static void mhi_netdev_queue(struct mhi_netdev *mhi_netdev, /* try going thru reclaim pool first */ for (i = 0; i < nr_tre; i++) { - /* peek for the next buffer, we going to peak several times, + /* peak for the next buffer, we going to peak several times, * and we going to give up if buffers are not yet free */ - int peek = 0; - + cur_index = mhi_netdev->current_index; netbuf = NULL; - list_for_each_entry(mhi_buf, pool, node) { + for (peak = 0; peak < max_peak; peak++) { + struct mhi_netbuf *tmp = netbuf_pool[cur_index]; + + mhi_buf = &tmp->mhi_buf; + + cur_index = (cur_index + 1) & pool_size; + /* page == 1 idle, buffer is free to reclaim */ if (page_ref_count(mhi_buf->page) == 1) { - netbuf = (struct mhi_netbuf *)mhi_buf; + netbuf = tmp; break; } - - if (peek++ >= max_peek) - break; } /* could not find a free buffer */ @@ -331,7 +263,6 @@ static void mhi_netdev_queue(struct mhi_netdev *mhi_netdev, * with buffer, the buffer won't be freed */ page_ref_inc(mhi_buf->page); - list_del(&mhi_buf->node); dma_sync_single_for_device(dev, mhi_buf->dma_addr, mhi_buf->len, DMA_FROM_DEVICE); ret = mhi_queue_transfer(mhi_dev, DMA_FROM_DEVICE, mhi_buf, @@ -341,36 +272,30 @@ static void mhi_netdev_queue(struct mhi_netdev *mhi_netdev, netbuf->unmap(dev, mhi_buf->dma_addr, mhi_buf->len, DMA_FROM_DEVICE); page_ref_dec(mhi_buf->page); - list_add(&mhi_buf->node, pool); return; } - mhi_netdev->rbuffers++; + mhi_netdev->current_index = cur_index; } - /* recycling did not work, buffers are still busy use bg pool */ - if (i < nr_tre) - i += mhi_netdev_queue_bg_pool(mhi_netdev, mhi_dev, nr_tre - i); - /* recyling did not work, buffers are still busy allocate temp pkts */ if (i < nr_tre) - mhi_netdev_tmp_alloc(mhi_netdev, mhi_dev, nr_tre - i); + mhi_netdev_tmp_alloc(mhi_netdev, nr_tre - i); } /* allocating pool of memory */ static int mhi_netdev_alloc_pool(struct mhi_netdev *mhi_netdev) { int i; - struct mhi_netbuf *netbuf; - struct mhi_buf *mhi_buf, *tmp; + struct mhi_netbuf *netbuf, **netbuf_pool; + struct mhi_buf *mhi_buf; const u32 order = mhi_netdev->order; struct device *dev = mhi_netdev->mhi_dev->dev.parent; - struct list_head *pool = kmalloc(sizeof(*pool), GFP_KERNEL); - if (!pool) + netbuf_pool = kmalloc_array(mhi_netdev->pool_size, sizeof(*netbuf_pool), + GFP_KERNEL); + if (!netbuf_pool) return -ENOMEM; - INIT_LIST_HEAD(pool); - for (i = 0; i < mhi_netdev->pool_size; i++) { /* allocate paged data */ netbuf = mhi_netdev_alloc(dev, GFP_KERNEL, order); @@ -378,100 +303,44 @@ static int mhi_netdev_alloc_pool(struct mhi_netdev *mhi_netdev) goto error_alloc_page; netbuf->unmap = dma_sync_single_for_cpu; - netbuf->recycle = true; - mhi_buf = (struct mhi_buf *)netbuf; - list_add(&mhi_buf->node, pool); + netbuf_pool[i] = netbuf; } - mhi_netdev->recycle_pool = pool; + mhi_netdev->netbuf_pool = netbuf_pool; return 0; error_alloc_page: - list_for_each_entry_safe(mhi_buf, tmp, pool, node) { - list_del(&mhi_buf->node); + for (--i; i >= 0; i--) { + netbuf = netbuf_pool[i]; + mhi_buf = &netbuf->mhi_buf; dma_unmap_page(dev, mhi_buf->dma_addr, mhi_buf->len, DMA_FROM_DEVICE); __free_pages(mhi_buf->page, order); } - kfree(pool); + kfree(netbuf_pool); return -ENOMEM; } static void mhi_netdev_free_pool(struct mhi_netdev *mhi_netdev) { + int i; + struct mhi_netbuf *netbuf, **netbuf_pool = mhi_netdev->netbuf_pool; struct device *dev = mhi_netdev->mhi_dev->dev.parent; - struct mhi_buf *mhi_buf, *tmp; + struct mhi_buf *mhi_buf; - list_for_each_entry_safe(mhi_buf, tmp, mhi_netdev->recycle_pool, node) { - list_del(&mhi_buf->node); + for (i = 0; i < mhi_netdev->pool_size; i++) { + netbuf = netbuf_pool[i]; + mhi_buf = &netbuf->mhi_buf; dma_unmap_page(dev, mhi_buf->dma_addr, mhi_buf->len, DMA_FROM_DEVICE); __free_pages(mhi_buf->page, mhi_netdev->order); } - kfree(mhi_netdev->recycle_pool); - - /* free the bg pool */ - list_for_each_entry_safe(mhi_buf, tmp, mhi_netdev->bg_pool, node) { - list_del(&mhi_buf->node); - __free_pages(mhi_buf->page, mhi_netdev->order); - mhi_netdev->bg_pool_size--; - } -} - -static int mhi_netdev_alloc_thread(void *data) -{ - struct mhi_netdev *mhi_netdev = data; - struct mhi_netbuf *netbuf; - struct mhi_buf *mhi_buf, *tmp_buf; - const u32 order = mhi_netdev->order; - LIST_HEAD(head); - - while (!kthread_should_stop()) { - while (mhi_netdev->bg_pool_size <= mhi_netdev->bg_pool_limit) { - int buffers = 0, i; - - /* do a bulk allocation */ - for (i = 0; i < NAPI_POLL_WEIGHT; i++) { - if (kthread_should_stop()) - goto exit_alloc; - - netbuf = mhi_netdev_alloc(NULL, GFP_KERNEL, - order); - if (!netbuf) - continue; - - mhi_buf = (struct mhi_buf *)netbuf; - list_add(&mhi_buf->node, &head); - buffers++; - } - - /* add the list to main pool */ - spin_lock_bh(&mhi_netdev->bg_lock); - list_splice_init(&head, mhi_netdev->bg_pool); - mhi_netdev->bg_pool_size += buffers; - spin_unlock_bh(&mhi_netdev->bg_lock); - } - - /* replenish the ring */ - napi_schedule(mhi_netdev->napi); - - /* wait for buffers to run low or thread to stop */ - wait_event_interruptible(mhi_netdev->alloc_event, - kthread_should_stop() || - mhi_netdev->bg_pool_size <= mhi_netdev->bg_pool_limit); - } - -exit_alloc: - list_for_each_entry_safe(mhi_buf, tmp_buf, &head, node) { - list_del(&mhi_buf->node); - __free_pages(mhi_buf->page, order); - } - - return 0; + kfree(mhi_netdev->netbuf_pool); + mhi_netdev->netbuf_pool = NULL; } static int mhi_netdev_poll(struct napi_struct *napi, int budget) @@ -501,10 +370,10 @@ static int mhi_netdev_poll(struct napi_struct *napi, int budget) } /* queue new buffers */ - mhi_netdev_queue(mhi_netdev, mhi_dev); + mhi_netdev_queue(mhi_netdev); if (rsc_dev) - mhi_netdev_queue(mhi_netdev, rsc_dev->mhi_dev); + mhi_netdev_queue(rsc_dev); /* complete work if # of packet processed less than allocated budget */ if (rx_work < budget) @@ -798,8 +667,6 @@ static void mhi_netdev_xfer_dl_cb(struct mhi_device *mhi_dev, struct mhi_net_chain *chain = mhi_netdev->chain; netbuf->unmap(dev, mhi_buf->dma_addr, mhi_buf->len, DMA_FROM_DEVICE); - if (likely(netbuf->recycle)) - list_add_tail(&mhi_buf->node, mhi_netdev->recycle_pool); /* modem is down, drop the buffer */ if (mhi_result->transaction_status == -ENOTCONN) { @@ -850,31 +717,6 @@ static void mhi_netdev_status_cb(struct mhi_device *mhi_dev, enum MHI_CB mhi_cb) struct dentry *dentry; -static int mhi_netdev_debugfs_stats_show(struct seq_file *m, void *d) -{ - struct mhi_netdev *mhi_netdev = m->private; - - seq_printf(m, - "mru:%u order:%u pool_size:%d, bg_pool_size:%d bg_pool_limit:%d abuf:%u kbuf:%u rbuf:%u\n", - mhi_netdev->mru, mhi_netdev->order, mhi_netdev->pool_size, - mhi_netdev->bg_pool_size, mhi_netdev->bg_pool_limit, - mhi_netdev->abuffers, mhi_netdev->kbuffers, - mhi_netdev->rbuffers); - - return 0; -} - -static int mhi_netdev_debugfs_stats_open(struct inode *inode, struct file *fp) -{ - return single_open(fp, mhi_netdev_debugfs_stats_show, inode->i_private); -} - -static const struct file_operations debugfs_stats = { - .open = mhi_netdev_debugfs_stats_open, - .release = single_release, - .read = seq_read, -}; - static void mhi_netdev_create_debugfs(struct mhi_netdev *mhi_netdev) { char node_name[32]; @@ -891,9 +733,6 @@ static void mhi_netdev_create_debugfs(struct mhi_netdev *mhi_netdev) mhi_netdev->dentry = debugfs_create_dir(node_name, dentry); if (IS_ERR_OR_NULL(mhi_netdev->dentry)) return; - - debugfs_create_file_unsafe("stats", 0444, mhi_netdev->dentry, - mhi_netdev, &debugfs_stats); } static void mhi_netdev_create_debugfs_dir(void) @@ -925,12 +764,12 @@ static void mhi_netdev_remove(struct mhi_device *mhi_dev) return; } - kthread_stop(mhi_netdev->alloc_task); netif_stop_queue(mhi_netdev->ndev); napi_disable(mhi_netdev->napi); unregister_netdev(mhi_netdev->ndev); netif_napi_del(mhi_netdev->napi); free_netdev(mhi_netdev->ndev); + mhi_netdev_free_pool(mhi_netdev); if (!IS_ERR_OR_NULL(mhi_netdev->dentry)) debugfs_remove_recursive(mhi_netdev->dentry); @@ -952,9 +791,6 @@ static void mhi_netdev_clone_dev(struct mhi_netdev *mhi_netdev, mhi_netdev->ipc_log_lvl = parent->ipc_log_lvl; mhi_netdev->is_rsc_dev = true; mhi_netdev->chain = parent->chain; - mhi_netdev->rsc_parent = parent; - mhi_netdev->recycle_pool = parent->recycle_pool; - mhi_netdev->bg_pool = parent->bg_pool; } static int mhi_netdev_probe(struct mhi_device *mhi_dev, @@ -976,13 +812,6 @@ static int mhi_netdev_probe(struct mhi_device *mhi_dev, if (!mhi_netdev) return -ENOMEM; - /* move mhi channels to start state */ - ret = mhi_prepare_for_transfer(mhi_dev); - if (ret) { - MSG_ERR("Failed to start channels ret %d\n", ret); - return ret; - } - mhi_netdev->mhi_dev = mhi_dev; mhi_device_set_devdata(mhi_dev, mhi_netdev); @@ -1030,38 +859,6 @@ static int mhi_netdev_probe(struct mhi_device *mhi_dev, if (ret) return ret; - /* setup pool size ~2x ring length*/ - nr_tre = mhi_get_no_free_descriptors(mhi_dev, DMA_FROM_DEVICE); - mhi_netdev->pool_size = 1 << __ilog2_u32(nr_tre); - if (nr_tre > mhi_netdev->pool_size) - mhi_netdev->pool_size <<= 1; - mhi_netdev->pool_size <<= 1; - - /* if we expect child device to share then double the pool */ - if (of_parse_phandle(of_node, "mhi,rsc-child", 0)) - mhi_netdev->pool_size <<= 1; - - /* allocate memory pool */ - ret = mhi_netdev_alloc_pool(mhi_netdev); - if (ret) - return -ENOMEM; - - /* create a background task to allocate memory */ - mhi_netdev->bg_pool = kmalloc(sizeof(*mhi_netdev->bg_pool), - GFP_KERNEL); - if (!mhi_netdev->bg_pool) - return -ENOMEM; - - init_waitqueue_head(&mhi_netdev->alloc_event); - INIT_LIST_HEAD(mhi_netdev->bg_pool); - spin_lock_init(&mhi_netdev->bg_lock); - mhi_netdev->bg_pool_limit = mhi_netdev->pool_size / 4; - mhi_netdev->alloc_task = kthread_run(mhi_netdev_alloc_thread, - mhi_netdev, - mhi_netdev->ndev->name); - if (IS_ERR(mhi_netdev->alloc_task)) - return PTR_ERR(mhi_netdev->alloc_task); - /* create ipc log buffer */ snprintf(node_name, sizeof(node_name), "%s_%04x_%02u.%02u.%02u_%u", @@ -1075,6 +872,25 @@ static int mhi_netdev_probe(struct mhi_device *mhi_dev, mhi_netdev_create_debugfs(mhi_netdev); } + /* move mhi channels to start state */ + ret = mhi_prepare_for_transfer(mhi_dev); + if (ret) { + MSG_ERR("Failed to start channels ret %d\n", ret); + goto error_start; + } + + /* setup pool size ~2x ring length*/ + nr_tre = mhi_get_no_free_descriptors(mhi_dev, DMA_FROM_DEVICE); + mhi_netdev->pool_size = 1 << __ilog2_u32(nr_tre); + if (nr_tre > mhi_netdev->pool_size) + mhi_netdev->pool_size <<= 1; + mhi_netdev->pool_size <<= 1; + + /* allocate memory pool */ + ret = mhi_netdev_alloc_pool(mhi_netdev); + if (ret) + goto error_start; + /* link child node with parent node if it's children dev */ if (p_netdev) p_netdev->rsc_dev = mhi_netdev; @@ -1085,6 +901,18 @@ static int mhi_netdev_probe(struct mhi_device *mhi_dev, napi_schedule(mhi_netdev->napi); return 0; + +error_start: + if (phandle) + return ret; + + netif_stop_queue(mhi_netdev->ndev); + napi_disable(mhi_netdev->napi); + unregister_netdev(mhi_netdev->ndev); + netif_napi_del(mhi_netdev->napi); + free_netdev(mhi_netdev->ndev); + + return ret; } static const struct mhi_device_id mhi_netdev_match_table[] = { diff --git a/drivers/char/adsprpc.c b/drivers/char/adsprpc.c index e052a2bf4476..3c7f8ddf353e 100644 --- a/drivers/char/adsprpc.c +++ b/drivers/char/adsprpc.c @@ -4048,15 +4048,16 @@ static int fastrpc_probe(struct platform_device *pdev) if (range.addr && !of_property_read_bool(dev->of_node, "restrict-access")) { int srcVM[1] = {VMID_HLOS}; - int destVM[3] = {VMID_HLOS, VMID_SSC_Q6, + int destVM[4] = {VMID_HLOS, VMID_MSS_MSA, VMID_SSC_Q6, VMID_ADSP_Q6}; - int destVMperm[3] = {PERM_READ | PERM_WRITE | PERM_EXEC, + int destVMperm[4] = {PERM_READ | PERM_WRITE | PERM_EXEC, + PERM_READ | PERM_WRITE | PERM_EXEC, PERM_READ | PERM_WRITE | PERM_EXEC, PERM_READ | PERM_WRITE | PERM_EXEC, }; VERIFY(err, !hyp_assign_phys(range.addr, range.size, - srcVM, 1, destVM, destVMperm, 3)); + srcVM, 1, destVM, destVMperm, 4)); if (err) goto bail; me->range.addr = range.addr; diff --git a/drivers/char/adsprpc_compat.c b/drivers/char/adsprpc_compat.c old mode 100755 new mode 100644 diff --git a/drivers/char/adsprpc_shared.h b/drivers/char/adsprpc_shared.h old mode 100755 new mode 100644 diff --git a/drivers/char/diag/diag_dci.c b/drivers/char/diag/diag_dci.c index 366eaf277578..32566697f599 100644 --- a/drivers/char/diag/diag_dci.c +++ b/drivers/char/diag/diag_dci.c @@ -726,44 +726,29 @@ int diag_dci_query_event_mask(struct diag_dci_client_tbl *entry, return ((*event_mask_ptr & byte_mask) == byte_mask) ? 1 : 0; } -static int diag_dci_filter_commands(struct diag_pkt_header_t *header, - int header_len) +static int diag_dci_filter_commands(struct diag_pkt_header_t *header) { if (!header) return -ENOMEM; - if (header_len <= 0) - return -EIO; - - if (header_len) { - switch (header->cmd_code) { - case 0x7d: /* Msg Mask Configuration */ - case 0x73: /* Log Mask Configuration */ - case 0x81: /* Event Mask Configuration */ - case 0x82: /* Event Mask Change */ - case 0x60: /* Event Mask Toggle */ - DIAG_LOG(DIAG_DEBUG_DCI, - "diag: command not supported: %d\n", - header->cmd_code); - return 1; - } + switch (header->cmd_code) { + case 0x7d: /* Msg Mask Configuration */ + case 0x73: /* Log Mask Configuration */ + case 0x81: /* Event Mask Configuration */ + case 0x82: /* Event Mask Change */ + case 0x60: /* Event Mask Toggle */ + return 1; } - if (header_len >= (3*sizeof(uint8_t))) { - if (header->cmd_code == 0x4b && header->subsys_id == 0x12) { - switch (header->subsys_cmd_code) { - case 0x60: /* Extended Event Mask Config */ - case 0x61: /* Extended Msg Mask Config */ - case 0x62: /* Extended Log Mask Config */ - case 0x20C: /* Set current Preset ID */ - case 0x20D: /* Get current Preset ID */ - case 0x218: /* HDLC Disabled Command */ - DIAG_LOG(DIAG_DEBUG_DCI, - "diag: command not supported %d %d %d\n", - header->cmd_code, header->subsys_id, - header->subsys_cmd_code); - return 1; - } + if (header->cmd_code == 0x4b && header->subsys_id == 0x12) { + switch (header->subsys_cmd_code) { + case 0x60: /* Extended Event Mask Config */ + case 0x61: /* Extended Msg Mask Config */ + case 0x62: /* Extended Log Mask Config */ + case 0x20C: /* Set current Preset ID */ + case 0x20D: /* Get current Preset ID */ + case 0x218: /* HDLC Disabled Command */ + return 1; } } @@ -1815,7 +1800,7 @@ int diag_dci_send_handshake_pkt(int index) static int diag_dci_process_apps_pkt(struct diag_pkt_header_t *pkt_header, unsigned char *req_buf, int req_len, - int tag, int pkt_header_len) + int tag) { uint8_t cmd_code, subsys_id, i, goto_download = 0; uint8_t header_len = sizeof(struct diag_dci_pkt_header_t); @@ -1825,16 +1810,12 @@ static int diag_dci_process_apps_pkt(struct diag_pkt_header_t *pkt_header, unsigned char *payload_ptr = driver->apps_dci_buf + header_len; struct diag_dci_pkt_header_t dci_header; - if (!pkt_header || !req_buf || req_len <= 0 || tag < 0 || - pkt_header_len <= 0) + if (!pkt_header || !req_buf || req_len <= 0 || tag < 0) return -EIO; - if (pkt_header_len >= (sizeof(uint8_t))) - cmd_code = pkt_header->cmd_code; - if (pkt_header_len >= (2 * sizeof(uint8_t))) - subsys_id = pkt_header->subsys_id; - if (pkt_header_len >= (3 * sizeof(uint8_t))) - ss_cmd_code = pkt_header->subsys_cmd_code; + cmd_code = pkt_header->cmd_code; + subsys_id = pkt_header->subsys_id; + ss_cmd_code = pkt_header->subsys_cmd_code; if (cmd_code == DIAG_CMD_DOWNLOAD) { *payload_ptr = DIAG_CMD_DOWNLOAD; @@ -1955,7 +1936,7 @@ static int diag_dci_process_apps_pkt(struct diag_pkt_header_t *pkt_header, static int diag_process_dci_pkt_rsp(unsigned char *buf, int len) { int ret = DIAG_DCI_TABLE_ERR; - int common_cmd = 0, header_len = 0; + int common_cmd = 0; struct diag_pkt_header_t *header = NULL; unsigned char *temp = buf; unsigned char *req_buf = NULL; @@ -1971,7 +1952,8 @@ static int diag_process_dci_pkt_rsp(unsigned char *buf, int len) if (!buf) return -EIO; - if (len < sizeof(struct dci_pkt_req_t) || + if (len < (sizeof(struct dci_pkt_req_t) + + sizeof(struct diag_pkt_header_t)) || len > DCI_REQ_BUF_SIZE) { pr_err("diag: dci: Invalid length %d len in %s", len, __func__); return -EIO; @@ -1982,6 +1964,13 @@ static int diag_process_dci_pkt_rsp(unsigned char *buf, int len) read_len += sizeof(struct dci_pkt_req_t); req_len -= sizeof(struct dci_pkt_req_t); req_buf = temp; /* Start of the Request */ + header = (struct diag_pkt_header_t *)temp; + read_len += sizeof(struct diag_pkt_header_t); + if (read_len >= DCI_REQ_BUF_SIZE) { + pr_err("diag: dci: In %s, invalid read_len: %d\n", __func__, + read_len); + return -EIO; + } mutex_lock(&driver->dci_mutex); dci_entry = diag_dci_get_client_entry(req_hdr.client_id); @@ -1992,40 +1981,11 @@ static int diag_process_dci_pkt_rsp(unsigned char *buf, int len) return DIAG_DCI_NO_REG; } - header = (void *)temp; - header_len = len - sizeof(struct dci_pkt_req_t); - if (header_len <= 0) { - mutex_unlock(&driver->dci_mutex); - return -EIO; - } - if (header_len >= sizeof(uint8_t)) { - header->cmd_code = (uint16_t)(*(uint8_t *)temp); - read_len += sizeof(uint8_t); - } - if (header_len >= (2 * sizeof(uint8_t))) { - temp += sizeof(uint8_t); - header->subsys_id = (uint16_t)(*(uint8_t *)temp); - read_len += sizeof(uint8_t); - } - if (header_len == (3 * sizeof(uint8_t))) { - temp += sizeof(uint8_t); - header->subsys_cmd_code = (uint16_t)(*(uint8_t *)temp); - read_len += sizeof(uint8_t); - } else if (header_len >= - (2 * sizeof(uint8_t)) + sizeof(uint16_t)) { - temp += sizeof(uint8_t); - header->subsys_cmd_code = (uint16_t)(*(uint16_t *)temp); - read_len += sizeof(uint16_t); - } - if (read_len > DCI_REQ_BUF_SIZE) { - pr_err("diag: dci: In %s, invalid read_len: %d\n", __func__, - read_len); - mutex_unlock(&driver->dci_mutex); - return -EIO; - } - /* Check if the command is allowed on DCI */ - if (diag_dci_filter_commands(header, header_len)) { + if (diag_dci_filter_commands(header)) { + pr_debug("diag: command not supported %d %d %d", + header->cmd_code, header->subsys_id, + header->subsys_cmd_code); mutex_unlock(&driver->dci_mutex); return DIAG_DCI_SEND_DATA_FAIL; } @@ -2079,18 +2039,14 @@ static int diag_process_dci_pkt_rsp(unsigned char *buf, int len) /* Check if it is a dedicated Apps command */ ret = diag_dci_process_apps_pkt(header, req_buf, req_len, - req_entry->tag, header_len); + req_entry->tag); if ((ret == DIAG_DCI_NO_ERROR && !common_cmd) || ret < 0) return ret; - if (header_len >= (sizeof(uint8_t))) - reg_entry.cmd_code = header->cmd_code; - if (header_len >= (2 * sizeof(uint8_t))) - reg_entry.subsys_id = header->subsys_id; - if (header_len >= (3 * sizeof(uint8_t))) { - reg_entry.cmd_code_hi = header->subsys_cmd_code; - reg_entry.cmd_code_lo = header->subsys_cmd_code; - } + reg_entry.cmd_code = header->cmd_code; + reg_entry.subsys_id = header->subsys_id; + reg_entry.cmd_code_hi = header->subsys_cmd_code; + reg_entry.cmd_code_lo = header->subsys_cmd_code; mutex_lock(&driver->cmd_reg_mutex); temp_entry = diag_cmd_search(®_entry, ALL_PROC); diff --git a/drivers/char/diag/diag_debugfs.c b/drivers/char/diag/diag_debugfs.c index 73b7f194b984..1cbfb97f9a21 100644 --- a/drivers/char/diag/diag_debugfs.c +++ b/drivers/char/diag/diag_debugfs.c @@ -553,7 +553,7 @@ static ssize_t diag_dbgfs_read_socketinfo(struct file *file, char __user *ubuf, struct diag_socket_info *info = NULL; struct diagfwd_info *fwd_ctxt = NULL; - if (diag_dbgfs_socketinfo_index >= NUM_TYPES) { + if (diag_dbgfs_socketinfo_index >= NUM_PERIPHERALS) { /* Done. Reset to prepare for future requests */ diag_dbgfs_socketinfo_index = 0; return 0; @@ -659,7 +659,7 @@ static ssize_t diag_dbgfs_read_rpmsginfo(struct file *file, char __user *ubuf, struct diag_rpmsg_info *info = NULL; struct diagfwd_info *fwd_ctxt = NULL; - if (diag_dbgfs_rpmsginfo_index >= NUM_TYPES) { + if (diag_dbgfs_rpmsginfo_index >= NUM_PERIPHERALS) { /* Done. Reset to prepare for future requests */ diag_dbgfs_rpmsginfo_index = 0; return 0; @@ -697,7 +697,7 @@ static ssize_t diag_dbgfs_read_rpmsginfo(struct file *file, char __user *ubuf, bytes_written = scnprintf(buf+bytes_in_buffer, bytes_remaining, - "name\t\t:\t%s:\t%s\n" + "name\t\t:\t%s\n" "hdl\t\t:\t%pK\n" "inited\t\t:\t%d\n" "opened\t\t:\t%d\n" @@ -712,7 +712,6 @@ static ssize_t diag_dbgfs_read_rpmsginfo(struct file *file, char __user *ubuf, "fwd inited\t:\t%d\n" "fwd opened\t:\t%d\n" "fwd ch_open\t:\t%d\n\n", - info->edge, info->name, info->hdl, info->inited, @@ -794,7 +793,7 @@ static ssize_t diag_dbgfs_read_hsicinfo(struct file *file, char __user *ubuf, unsigned int bytes_in_buffer = 0; struct diag_hsic_info *hsic_info = NULL; - if (diag_dbgfs_hsicinfo_index >= NUM_HSIC_DEV) { + if (diag_dbgfs_hsicinfo_index >= NUM_DIAG_USB_DEV) { /* Done. Reset to prepare for future requests */ diag_dbgfs_hsicinfo_index = 0; return 0; @@ -939,7 +938,7 @@ static ssize_t diag_dbgfs_read_bridge(struct file *file, char __user *ubuf, unsigned int bytes_in_buffer = 0; struct diagfwd_bridge_info *info = NULL; - if (diag_dbgfs_bridgeinfo_index >= NUM_REMOTE_DEV) { + if (diag_dbgfs_bridgeinfo_index >= NUM_DIAG_USB_DEV) { /* Done. Reset to prepare for future requests */ diag_dbgfs_bridgeinfo_index = 0; return 0; diff --git a/drivers/char/diag/diag_masks.c b/drivers/char/diag/diag_masks.c index 362597bceba8..8d24bbba32dd 100644 --- a/drivers/char/diag/diag_masks.c +++ b/drivers/char/diag/diag_masks.c @@ -1109,7 +1109,7 @@ static int diag_cmd_update_event_mask(unsigned char *src_buf, int src_len, rsp.num_bits = driver->last_event_id + 1; memcpy(dest_buf, &rsp, header_len); write_len += header_len; - memcpy(dest_buf + write_len, src_buf + header_len, mask_len); + memcpy(dest_buf + write_len, mask_info->ptr, mask_len); write_len += mask_len; for (i = 0; i < NUM_MD_SESSIONS; i++) { @@ -1217,9 +1217,10 @@ static int diag_cmd_get_log_mask(unsigned char *src_buf, int src_len, mask_info = (!info) ? &log_mask : info->log_mask; if (!src_buf || !dest_buf || dest_len <= 0 || !mask_info || src_len < sizeof(struct diag_log_config_get_req_t)) { - pr_err("diag: Invalid input in %s, src_buf: %pK, src_len: %d, dest_buf: %pK, dest_len: %d, mask_info: %pK\n", + + pr_err("diag: Invalid input in %s, src_buf: %pK, src_len: %d, dest_buf: %pK, dest_len: %d, mask_info: %pK,structure size %d\n", __func__, src_buf, src_len, dest_buf, dest_len, - mask_info); + mask_info, sizeof(struct diag_log_config_get_req_t)); mutex_unlock(&driver->md_session_lock); return -EINVAL; } diff --git a/drivers/char/diag/diag_memorydevice.c b/drivers/char/diag/diag_memorydevice.c index b44410250420..3d2bcf7dc9dd 100644 --- a/drivers/char/diag/diag_memorydevice.c +++ b/drivers/char/diag/diag_memorydevice.c @@ -175,7 +175,7 @@ int diag_md_write(int id, unsigned char *buf, int len, int ctx) { int i, peripheral, pid = 0; uint8_t found = 0; - unsigned long flags, flags_sec; + unsigned long flags; struct diag_md_info *ch = NULL; struct diag_md_session_t *session_info = NULL; @@ -207,16 +207,6 @@ int diag_md_write(int id, unsigned char *buf, int len, int ctx) } spin_lock_irqsave(&ch->lock, flags); - if (peripheral == APPS_DATA) { - spin_lock_irqsave(&driver->diagmem_lock, flags_sec); - if (!hdlc_data.allocated && !non_hdlc_data.allocated) { - spin_unlock_irqrestore(&driver->diagmem_lock, - flags_sec); - spin_unlock_irqrestore(&ch->lock, flags); - mutex_unlock(&driver->md_session_lock); - return -EINVAL; - } - } for (i = 0; i < ch->num_tbl_entries && !found; i++) { if (ch->tbl[i].buf != buf) continue; @@ -228,16 +218,14 @@ int diag_md_write(int id, unsigned char *buf, int len, int ctx) ch->tbl[i].len = 0; ch->tbl[i].ctx = 0; } + spin_unlock_irqrestore(&ch->lock, flags); if (found) { - if (peripheral == APPS_DATA) - spin_unlock_irqrestore(&driver->diagmem_lock, - flags_sec); - spin_unlock_irqrestore(&ch->lock, flags); mutex_unlock(&driver->md_session_lock); return -ENOMEM; } + spin_lock_irqsave(&ch->lock, flags); for (i = 0; i < ch->num_tbl_entries && !found; i++) { if (ch->tbl[i].len == 0) { ch->tbl[i].buf = buf; @@ -247,8 +235,6 @@ int diag_md_write(int id, unsigned char *buf, int len, int ctx) diag_ws_on_read(DIAG_WS_MUX, len); } } - if (peripheral == APPS_DATA) - spin_unlock_irqrestore(&driver->diagmem_lock, flags_sec); spin_unlock_irqrestore(&ch->lock, flags); mutex_unlock(&driver->md_session_lock); diff --git a/drivers/char/diag/diagchar_core.c b/drivers/char/diag/diagchar_core.c index 6aa12b99874f..52c5027ebeda 100644 --- a/drivers/char/diag/diagchar_core.c +++ b/drivers/char/diag/diagchar_core.c @@ -457,7 +457,7 @@ static void diag_close_logging_process(const int pid) int i, j; int session_mask = 0; int device_mask = 0; - uint32_t p_mask = 0; + uint32_t p_mask; struct diag_md_session_t *session_info = NULL; struct diag_logging_mode_param_t params; @@ -523,11 +523,9 @@ static void diag_close_logging_process(const int pid) } } } - mutex_lock(&driver->hdlc_disable_mutex); mutex_lock(&driver->md_session_lock); diag_md_session_close(pid); mutex_unlock(&driver->md_session_lock); - mutex_unlock(&driver->hdlc_disable_mutex); diag_switch_logging(¶ms); mutex_unlock(&driver->diagchar_mutex); } @@ -1445,8 +1443,6 @@ static void diag_md_session_close(int pid) driver->md_session_map[proc][i] = NULL; driver->md_session_mask[proc] &= ~session_info->peripheral_mask[proc]; - driver->p_hdlc_disabled[i] = - driver->hdlc_disabled; } } diag_log_mask_free(session_info->log_mask); diff --git a/drivers/char/diag/diagfwd.c b/drivers/char/diag/diagfwd.c index fe9027eaf478..3b67d3b1fe5e 100644 --- a/drivers/char/diag/diagfwd.c +++ b/drivers/char/diag/diagfwd.c @@ -1025,33 +1025,27 @@ int diag_process_apps_pkt(unsigned char *buf, int len, int pid) } temp = buf; - if (len >= sizeof(uint8_t)) { - entry.cmd_code = (uint16_t)(*(uint8_t *)temp); - DIAG_LOG(DIAG_DEBUG_CMD_INFO, - "diag: received cmd_code %02x\n", entry.cmd_code); - } - if (len >= (2 * sizeof(uint8_t))) { - temp += sizeof(uint8_t); - entry.subsys_id = (uint16_t)(*(uint8_t *)temp); - DIAG_LOG(DIAG_DEBUG_CMD_INFO, - "diag: received subsys_id %02x\n", entry.subsys_id); - } - if (len == (3 * sizeof(uint8_t))) { - temp += sizeof(uint8_t); - entry.cmd_code_hi = (uint16_t)(*(uint8_t *)temp); - entry.cmd_code_lo = (uint16_t)(*(uint8_t *)temp); - DIAG_LOG(DIAG_DEBUG_CMD_INFO, - "diag: received cmd_code_hi %02x\n", entry.cmd_code_hi); - } else if (len >= (2 * sizeof(uint8_t)) + sizeof(uint16_t)) { - temp += sizeof(uint8_t); - entry.cmd_code_hi = (uint16_t)(*(uint16_t *)temp); - entry.cmd_code_lo = (uint16_t)(*(uint16_t *)temp); - DIAG_LOG(DIAG_DEBUG_CMD_INFO, - "diag: received cmd_code_hi %02x\n", entry.cmd_code_hi); - } - - if ((len >= sizeof(uint8_t)) && *buf == DIAG_CMD_LOG_ON_DMND && - driver->log_on_demand_support && + + entry.cmd_code = (uint16_t)(*(uint8_t *)temp); + temp += sizeof(uint8_t); + entry.subsys_id = (uint16_t)(*(uint8_t *)temp); + temp += sizeof(uint8_t); + entry.cmd_code_hi = (uint16_t)(*(uint16_t *)temp); + entry.cmd_code_lo = (uint16_t)(*(uint16_t *)temp); + temp += sizeof(uint16_t); + + + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: In %s, received cmd %02x %02x %04x\n", __func__, + entry.cmd_code, entry.subsys_id, entry.cmd_code_hi); + if (entry.cmd_code == 0x4b && + entry.subsys_id == 0x25 && + entry.cmd_code_hi == 0x0003) { + pr_err("trigger a modem crash by diag command\n"); + dump_stack(); + } + + if (*buf == DIAG_CMD_LOG_ON_DMND && driver->log_on_demand_support && driver->feature[PERIPHERAL_MODEM].rcvd_feature_mask) { write_len = diag_cmd_log_on_demand(buf, len, driver->apps_rsp_buf, @@ -1862,9 +1856,6 @@ static int diagfwd_mux_write_done(unsigned char *buf, int len, int buf_ctxt, DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "No apps data buffer is allocated to be freed\n"); if (temp) { - DIAG_LOG(DIAG_DEBUG_PERIPHERALS, - "Freeing Apps data buffer after write done hdlc.allocated: %d, non_hdlc.allocated: %d\n", - hdlc_data.allocated, non_hdlc_data.allocated); diagmem_free(driver, temp->buf, POOL_TYPE_HDLC); temp->buf = NULL; temp->len = 0; diff --git a/drivers/char/misc.c b/drivers/char/misc.c index 1bb9e7cc82e3..b4c4312ab6d2 100644 --- a/drivers/char/misc.c +++ b/drivers/char/misc.c @@ -60,7 +60,7 @@ static DEFINE_MUTEX(misc_mtx); /* * Assigned numbers, used for dynamic minors */ -#define DYNAMIC_MINORS 64 /* like dynamic majors */ +#define DYNAMIC_MINORS 128 /* like dynamic majors */ static DECLARE_BITMAP(misc_minors, DYNAMIC_MINORS); #ifdef CONFIG_PROC_FS diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index c85f6e18cd25..61ffeb6136c5 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -568,56 +568,3 @@ config VIRTIO_CLK depends on VIRTIO ---help--- This is the virtual clock driver for virtio. - -config SM_GCC_ATOLL - tristate "ATOLL Global Clock Controller" - depends on COMMON_CLK_QCOM - select QCOM_GDSC - help - Support for the global clock controller on Qualcomm Technologies, Inc - ATOLL devices. - Say Y if you want to use peripheral devices such as UART, SPI, I2C, - USB, UFS, SD/eMMC, PCIe, etc. - -config SM_CAMCC_ATOLL - tristate "ATOLL Camera Clock Controller" - depends on COMMON_CLK_QCOM - help - Support for the camera clock controller on Qualcomm Technologies, Inc - ATOLL devices. - Say Y if you want to support camera devices and functionality such as - capturing pictures. - -config SM_VIDEOCC_ATOLL - tristate "ATOLL Video Clock Controller" - depends on COMMON_CLK_QCOM - help - Support for the video clock controller on Qualcomm Technologies, Inc. - ATOLL devices. - Say Y if you want to support video devices and functionality such as - video encode/decode. - -config SM_DISPCC_ATOLL - tristate "ATOLL Display Clock Controller" - depends on COMMON_CLK_QCOM - help - Support for the display clock controller on Qualcomm Technologies, Inc - ATOLL devices. - Say Y if you want to support display devices and functionality such as - splash screen. - -config SM_NPUCC_ATOLL - tristate "ATOLL NPU Clock Controller" - depends on COMMON_CLK_QCOM - help - Support for the NPU clock controller on Qualcomm Technologies, Inc - ATOLL devices. - Say Y if you want to enable use of the Network Processing Unit. - -config SM_DEBUGCC_ATOLL - tristate "ATOLL Debug Clock Controller" - depends on COMMON_CLK_QCOM - help - Support for the debug clock controller on Qualcomm Technologies, Inc - ATOLL devices. - Say Y if you want to support the clock measurement functionality. diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 84f42e13f73f..157a9f7e2cbb 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -72,16 +72,10 @@ obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o obj-$(CONFIG_QCOM_CLK_VIRT) += clk-virt.o clk-virt-sm8150.o clk-virt-sm6150.o obj-$(CONFIG_QCS_CMN_BLK_PLL) += cmn-blk-pll.o -obj-$(CONFIG_SM_CAMCC_ATOLL) += camcc-atoll.o -obj-$(CONFIG_SM_DEBUGCC_ATOLL) += debugcc-atoll.o obj-$(CONFIG_SM_DEBUGCC_TRINKET) += debugcc-trinket.o -obj-$(CONFIG_SM_DISPCC_ATOLL) += dispcc-atoll.o obj-$(CONFIG_SM_DISPCC_TRINKET) += dispcc-trinket.o -obj-$(CONFIG_SM_GCC_ATOLL) += gcc-atoll.o obj-$(CONFIG_SM_GCC_TRINKET) += gcc-trinket.o obj-$(CONFIG_SM_GPUCC_TRINKET) += gpucc-trinket.o -obj-$(CONFIG_SM_NPUCC_ATOLL) += npucc-atoll.o -obj-$(CONFIG_SM_VIDEOCC_ATOLL) += videocc-atoll.o obj-$(CONFIG_SM_VIDEOCC_TRINKET) += videocc-trinket.o obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o obj-$(CONFIG_VIRTIO_CLK) += virtio_clk.o virtio_clk_sm8150.o virtio_clk_sm6150.o virtio_clk_sa8195p.o diff --git a/drivers/clk/qcom/camcc-atoll.c b/drivers/clk/qcom/camcc-atoll.c deleted file mode 100644 index 2c32dfc64e06..000000000000 --- a/drivers/clk/qcom/camcc-atoll.c +++ /dev/null @@ -1,1922 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define pr_fmt(fmt) "clk: %s: " fmt, __func__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "clk-alpha-pll.h" -#include "clk-branch.h" -#include "clk-rcg.h" -#include "clk-regmap.h" -#include "common.h" -#include "reset.h" -#include "vdd-level-sdmmagpie.h" - -#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } - -static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner); -static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner); - -enum { - P_BI_TCXO, - P_CAM_CC_PLL0_OUT_EVEN, - P_CAM_CC_PLL1_OUT_EVEN, - P_CAM_CC_PLL2_OUT_AUX2, - P_CAM_CC_PLL2_OUT_EARLY, - P_CAM_CC_PLL3_OUT_MAIN, - P_CORE_BI_PLL_TEST_SE, -}; - -static const struct parent_map cam_cc_parent_map_0[] = { - { P_BI_TCXO, 0 }, - { P_CAM_CC_PLL1_OUT_EVEN, 2 }, - { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const cam_cc_parent_names_0[] = { - "bi_tcxo", - "cam_cc_pll1_out_even", - "cam_cc_pll0_out_even", - "core_bi_pll_test_se", -}; - -static const struct parent_map cam_cc_parent_map_1[] = { - { P_BI_TCXO, 0 }, - { P_CAM_CC_PLL2_OUT_AUX2, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const cam_cc_parent_names_1[] = { - "bi_tcxo", - "cam_cc_pll2_out_aux2", - "core_bi_pll_test_se", -}; - -static const struct parent_map cam_cc_parent_map_2[] = { - { P_BI_TCXO, 0 }, - { P_CAM_CC_PLL2_OUT_EARLY, 4 }, - { P_CAM_CC_PLL3_OUT_MAIN, 5 }, - { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const cam_cc_parent_names_2[] = { - "bi_tcxo", - "cam_cc_pll2_out_early", - "cam_cc_pll3", - "cam_cc_pll0_out_even", - "core_bi_pll_test_se", -}; - -static const struct parent_map cam_cc_parent_map_3[] = { - { P_BI_TCXO, 0 }, - { P_CAM_CC_PLL1_OUT_EVEN, 2 }, - { P_CAM_CC_PLL2_OUT_EARLY, 4 }, - { P_CAM_CC_PLL3_OUT_MAIN, 5 }, - { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const cam_cc_parent_names_3[] = { - "bi_tcxo", - "cam_cc_pll1_out_even", - "cam_cc_pll2_out_early", - "cam_cc_pll3", - "cam_cc_pll0_out_even", - "core_bi_pll_test_se", -}; - -static const struct parent_map cam_cc_parent_map_4[] = { - { P_BI_TCXO, 0 }, - { P_CAM_CC_PLL3_OUT_MAIN, 5 }, - { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const cam_cc_parent_names_4[] = { - "bi_tcxo", - "cam_cc_pll3", - "cam_cc_pll0_out_even", - "core_bi_pll_test_se", -}; - -static const struct parent_map cam_cc_parent_map_5[] = { - { P_BI_TCXO, 0 }, - { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const cam_cc_parent_names_5[] = { - "bi_tcxo", - "cam_cc_pll0_out_even", - "core_bi_pll_test_se", -}; - -static const struct parent_map cam_cc_parent_map_6[] = { - { P_BI_TCXO, 0 }, - { P_CAM_CC_PLL1_OUT_EVEN, 2 }, - { P_CAM_CC_PLL3_OUT_MAIN, 5 }, - { P_CAM_CC_PLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const cam_cc_parent_names_6[] = { - "bi_tcxo", - "cam_cc_pll1_out_even", - "cam_cc_pll3", - "cam_cc_pll0_out_even", - "core_bi_pll_test_se", -}; - -static struct pll_vco agera_vco[] = { - { 600000000, 3300000000, 0 }, - { 600000000, 2000000000, 1 }, -}; - -static struct pll_vco fabia_vco[] = { - { 249600000, 2000000000, 0 }, -}; - -/* 600MHz configuration */ -static const struct alpha_pll_config cam_cc_pll0_config = { - .l = 0x1F, - .frac = 0x4000, - .user_ctl_val = 0x00000001, - .user_ctl_hi_val = 0x00004805, -}; - -static struct clk_alpha_pll cam_cc_pll0 = { - .offset = 0x0, - .vco_table = fabia_vco, - .num_vco = ARRAY_SIZE(fabia_vco), - .type = FABIA_PLL, - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_pll0", - .parent_names = (const char *[]){ "bi_tcxo" }, - .num_parents = 1, - .ops = &clk_fabia_pll_ops, - .vdd_class = &vdd_mx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_MIN] = 615000000, - [VDD_LOW] = 1066000000, - [VDD_LOW_L1] = 1600000000, - [VDD_NOMINAL] = 2000000000}, - }, - }, -}; - -static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { - { 0x0, 1 }, - { } -}; - -static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { - .offset = 0x0, - .post_div_shift = 8, - .post_div_table = post_div_table_cam_cc_pll0_out_even, - .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), - .width = 4, - .type = FABIA_PLL, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_pll0_out_even", - .parent_names = (const char *[]){ "cam_cc_pll0" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_generic_pll_postdiv_ops, - }, -}; - -/* 860MHz configuration */ -static const struct alpha_pll_config cam_cc_pll1_config = { - .l = 0x2A, - .frac = 0x1555, - .user_ctl_val = 0x00000001, - .user_ctl_hi_val = 0x00004805, -}; - -static struct clk_alpha_pll cam_cc_pll1 = { - .offset = 0x1000, - .vco_table = fabia_vco, - .num_vco = ARRAY_SIZE(fabia_vco), - .type = FABIA_PLL, - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_pll1", - .parent_names = (const char *[]){ "bi_tcxo" }, - .num_parents = 1, - .ops = &clk_fabia_pll_ops, - .vdd_class = &vdd_mx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_MIN] = 615000000, - [VDD_LOW] = 1066000000, - [VDD_LOW_L1] = 1600000000, - [VDD_NOMINAL] = 2000000000}, - }, - }, -}; - -static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { - { 0x0, 1 }, - { } -}; - -static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { - .offset = 0x1000, - .post_div_shift = 8, - .post_div_table = post_div_table_cam_cc_pll1_out_even, - .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), - .width = 4, - .type = FABIA_PLL, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_pll1_out_even", - .parent_names = (const char *[]){ "cam_cc_pll1" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_generic_pll_postdiv_ops, - }, -}; - -/* 1920MHz configuration */ -static const struct alpha_pll_config cam_cc_pll2_config = { - .l = 0x64, - .post_div_val = 0x3 << 8, - .post_div_mask = 0x3 << 8, - .aux_output_mask = BIT(1), - .main_output_mask = BIT(0), - .early_output_mask = BIT(3), - .config_ctl_hi_val = 0x400003d2, - .config_ctl_val = 0x20000800, -}; - -static struct clk_alpha_pll cam_cc_pll2 = { - .offset = 0x2000, - .vco_table = agera_vco, - .num_vco = ARRAY_SIZE(agera_vco), - .type = AGERA_PLL, - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_pll2", - .parent_names = (const char *[]){ "bi_tcxo" }, - .num_parents = 1, - .ops = &clk_agera_pll_ops, - .vdd_class = &vdd_mx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_MIN] = 1200000000, - [VDD_LOWER] = 1800000000, - [VDD_LOW] = 2400000000, - [VDD_NOMINAL] = 3000000000, - [VDD_HIGH] = 3300000000}, - }, - }, -}; - -static struct clk_fixed_factor cam_cc_pll2_out_early = { - .mult = 1, - .div = 2, - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_pll2_out_early", - .parent_names = (const char *[]){ "cam_cc_pll2" }, - .num_parents = 1, - .ops = &clk_fixed_factor_ops, - }, -}; - -static const struct clk_div_table post_div_table_cam_cc_pll2_out_aux2[] = { - { 0x1, 2 }, - { } -}; - -static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux2 = { - .offset = 0x2000, - .post_div_shift = 8, - .post_div_table = post_div_table_cam_cc_pll2_out_aux2, - .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_aux2), - .width = 2, - .type = AGERA_PLL, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_pll2_out_aux2", - .parent_names = (const char *[]){ "cam_cc_pll2" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_alpha_pll_postdiv_ops, - }, -}; - -/* 1080MHz configuration */ -static const struct alpha_pll_config cam_cc_pll3_config = { - .l = 0x38, - .alpha = 0x4000, - .user_ctl_val = 0x00000001, - .user_ctl_hi_val = 0x00004805, -}; - -static struct clk_alpha_pll cam_cc_pll3 = { - .offset = 0x3000, - .vco_table = fabia_vco, - .num_vco = ARRAY_SIZE(fabia_vco), - .type = FABIA_PLL, - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_pll3", - .parent_names = (const char *[]){ "bi_tcxo" }, - .num_parents = 1, - .ops = &clk_fabia_pll_ops, - .vdd_class = &vdd_mx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_MIN] = 615000000, - [VDD_LOW] = 1066000000, - [VDD_LOW_L1] = 1600000000, - [VDD_NOMINAL] = 2000000000}, - }, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), - F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), - F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), - F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), - F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_bps_clk_src = { - .cmd_rcgr = 0x6010, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_2, - .freq_tbl = ftbl_cam_cc_bps_clk_src, - .enable_safe_config = true, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_bps_clk_src", - .parent_names = cam_cc_parent_names_2, - .num_parents = 5, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 200000000, - [VDD_LOW] = 360000000, - [VDD_LOW_L1] = 432000000, - [VDD_NOMINAL] = 480000000, - [VDD_HIGH] = 600000000}, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), - F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), - F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_cci_0_clk_src = { - .cmd_rcgr = 0xb0d8, - .mnd_width = 8, - .hid_width = 5, - .parent_map = cam_cc_parent_map_5, - .freq_tbl = ftbl_cam_cc_cci_0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_cci_0_clk_src", - .parent_names = cam_cc_parent_names_5, - .num_parents = 3, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 37500000, - [VDD_LOW] = 50000000, - [VDD_NOMINAL] = 100000000}, - }, -}; - -static struct clk_rcg2 cam_cc_cci_1_clk_src = { - .cmd_rcgr = 0xb14c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = cam_cc_parent_map_5, - .freq_tbl = ftbl_cam_cc_cci_0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_cci_1_clk_src", - .parent_names = cam_cc_parent_names_5, - .num_parents = 3, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 37500000, - [VDD_LOW] = 50000000, - [VDD_NOMINAL] = 100000000}, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), - F(270000000, P_CAM_CC_PLL3_OUT_MAIN, 4, 0, 0), - F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { - .cmd_rcgr = 0x9064, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_3, - .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_cphy_rx_clk_src", - .parent_names = cam_cc_parent_names_3, - .num_parents = 6, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 150000000, - [VDD_LOW] = 270000000, - [VDD_LOW_L1] = 360000000}, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { - .cmd_rcgr = 0x5004, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_0, - .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_csi0phytimer_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 300000000}, - }, -}; - -static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { - .cmd_rcgr = 0x5028, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_0, - .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_csi1phytimer_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 300000000}, - }, -}; - -static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { - .cmd_rcgr = 0x504c, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_0, - .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_csi2phytimer_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 300000000}, - }, -}; - -static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { - .cmd_rcgr = 0x5070, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_0, - .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_csi3phytimer_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 300000000}, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), - F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), - F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), - F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { - .cmd_rcgr = 0x603c, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_0, - .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_fast_ahb_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 100000000, - [VDD_LOW] = 200000000, - [VDD_LOW_L1] = 300000000, - [VDD_NOMINAL] = 404000000}, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), - F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), - F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), - F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), - F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_icp_clk_src = { - .cmd_rcgr = 0xb088, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_2, - .freq_tbl = ftbl_cam_cc_icp_clk_src, - .enable_safe_config = true, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_icp_clk_src", - .parent_names = cam_cc_parent_names_2, - .num_parents = 5, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 240000000, - [VDD_LOW] = 360000000, - [VDD_LOW_L1] = 432000000, - [VDD_NOMINAL] = 480000000, - [VDD_HIGH] = 600000000}, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), - F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), - F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), - F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_ife_0_clk_src = { - .cmd_rcgr = 0x9010, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_4, - .freq_tbl = ftbl_cam_cc_ife_0_clk_src, - .enable_safe_config = true, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_ife_0_clk_src", - .parent_names = cam_cc_parent_names_4, - .num_parents = 4, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 240000000, - [VDD_LOW] = 360000000, - [VDD_LOW_L1] = 432000000, - [VDD_NOMINAL] = 600000000}, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), - F(270000000, P_CAM_CC_PLL3_OUT_MAIN, 4, 0, 0), - F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), - F(480000000, P_CAM_CC_PLL2_OUT_EARLY, 2, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { - .cmd_rcgr = 0x903c, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_3, - .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, - .enable_safe_config = true, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_ife_0_csid_clk_src", - .parent_names = cam_cc_parent_names_3, - .num_parents = 6, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 150000000, - [VDD_LOW] = 270000000, - [VDD_LOW_L1] = 360000000, - [VDD_NOMINAL] = 480000000}, - }, -}; - -static struct clk_rcg2 cam_cc_ife_1_clk_src = { - .cmd_rcgr = 0xa010, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_4, - .freq_tbl = ftbl_cam_cc_ife_0_clk_src, - .enable_safe_config = true, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_ife_1_clk_src", - .parent_names = cam_cc_parent_names_4, - .num_parents = 4, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 240000000, - [VDD_LOW] = 360000000, - [VDD_LOW_L1] = 432000000, - [VDD_NOMINAL] = 600000000}, - }, -}; - -static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { - .cmd_rcgr = 0xa034, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_3, - .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, - .enable_safe_config = true, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_ife_1_csid_clk_src", - .parent_names = cam_cc_parent_names_3, - .num_parents = 6, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 150000000, - [VDD_LOW] = 270000000, - [VDD_LOW_L1] = 360000000, - [VDD_NOMINAL] = 480000000}, - }, -}; - -static struct clk_rcg2 cam_cc_ife_lite_clk_src = { - .cmd_rcgr = 0xb004, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_4, - .freq_tbl = ftbl_cam_cc_ife_0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_ife_lite_clk_src", - .parent_names = cam_cc_parent_names_4, - .num_parents = 4, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 240000000, - [VDD_LOW] = 360000000, - [VDD_LOW_L1] = 432000000, - [VDD_NOMINAL] = 600000000}, - }, -}; - -static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { - .cmd_rcgr = 0xb024, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_3, - .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, - .enable_safe_config = true, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_ife_lite_csid_clk_src", - .parent_names = cam_cc_parent_names_3, - .num_parents = 6, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 150000000, - [VDD_LOW] = 270000000, - [VDD_LOW_L1] = 360000000, - [VDD_NOMINAL] = 480000000}, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), - F(360000000, P_CAM_CC_PLL3_OUT_MAIN, 3, 0, 0), - F(432000000, P_CAM_CC_PLL3_OUT_MAIN, 2.5, 0, 0), - F(540000000, P_CAM_CC_PLL3_OUT_MAIN, 2, 0, 0), - F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_ipe_0_clk_src = { - .cmd_rcgr = 0x7010, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_2, - .freq_tbl = ftbl_cam_cc_ipe_0_clk_src, - .enable_safe_config = true, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_ipe_0_clk_src", - .parent_names = cam_cc_parent_names_2, - .num_parents = 5, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 240000000, - [VDD_LOW] = 360000000, - [VDD_LOW_L1] = 432000000, - [VDD_NOMINAL] = 540000000, - [VDD_HIGH] = 600000000}, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(66666667, P_CAM_CC_PLL0_OUT_EVEN, 9, 0, 0), - F(133333333, P_CAM_CC_PLL0_OUT_EVEN, 4.5, 0, 0), - F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0), - F(320000000, P_CAM_CC_PLL2_OUT_EARLY, 3, 0, 0), - F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_jpeg_clk_src = { - .cmd_rcgr = 0xb04c, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_2, - .freq_tbl = ftbl_cam_cc_jpeg_clk_src, - .enable_safe_config = true, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_jpeg_clk_src", - .parent_names = cam_cc_parent_names_2, - .num_parents = 5, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 66666667, - [VDD_LOW] = 133333333, - [VDD_LOW_L1] = 216000000, - [VDD_NOMINAL] = 320000000, - [VDD_HIGH] = 600000000}, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), - F(216000000, P_CAM_CC_PLL3_OUT_MAIN, 5, 0, 0), - F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), - F(404000000, P_CAM_CC_PLL1_OUT_EVEN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_lrme_clk_src = { - .cmd_rcgr = 0xb0f8, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_6, - .freq_tbl = ftbl_cam_cc_lrme_clk_src, - .enable_safe_config = true, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_lrme_clk_src", - .parent_names = cam_cc_parent_names_6, - .num_parents = 5, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 200000000, - [VDD_LOW] = 216000000, - [VDD_LOW_L1] = 300000000, - [VDD_NOMINAL] = 404000000}, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(24000000, P_CAM_CC_PLL2_OUT_AUX2, 10, 1, 2), - F(64000000, P_CAM_CC_PLL2_OUT_AUX2, 7.5, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_mclk0_clk_src = { - .cmd_rcgr = 0x4004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = cam_cc_parent_map_1, - .freq_tbl = ftbl_cam_cc_mclk0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_mclk0_clk_src", - .parent_names = cam_cc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 64000000}, - }, -}; - -static struct clk_rcg2 cam_cc_mclk1_clk_src = { - .cmd_rcgr = 0x4024, - .mnd_width = 8, - .hid_width = 5, - .parent_map = cam_cc_parent_map_1, - .freq_tbl = ftbl_cam_cc_mclk0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_mclk1_clk_src", - .parent_names = cam_cc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 64000000}, - }, -}; - -static struct clk_rcg2 cam_cc_mclk2_clk_src = { - .cmd_rcgr = 0x4044, - .mnd_width = 8, - .hid_width = 5, - .parent_map = cam_cc_parent_map_1, - .freq_tbl = ftbl_cam_cc_mclk0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_mclk2_clk_src", - .parent_names = cam_cc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 64000000}, - }, -}; - -static struct clk_rcg2 cam_cc_mclk3_clk_src = { - .cmd_rcgr = 0x4064, - .mnd_width = 8, - .hid_width = 5, - .parent_map = cam_cc_parent_map_1, - .freq_tbl = ftbl_cam_cc_mclk0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_mclk3_clk_src", - .parent_names = cam_cc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 64000000}, - }, -}; - -static struct clk_rcg2 cam_cc_mclk4_clk_src = { - .cmd_rcgr = 0x4084, - .mnd_width = 8, - .hid_width = 5, - .parent_map = cam_cc_parent_map_1, - .freq_tbl = ftbl_cam_cc_mclk0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_mclk4_clk_src", - .parent_names = cam_cc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 64000000}, - }, -}; - -static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), - { } -}; - -static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { - .cmd_rcgr = 0x6058, - .mnd_width = 0, - .hid_width = 5, - .parent_map = cam_cc_parent_map_0, - .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, - .enable_safe_config = true, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cam_cc_slow_ahb_clk_src", - .parent_names = cam_cc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 80000000}, - }, -}; - -static struct clk_branch cam_cc_bps_ahb_clk = { - .halt_reg = 0x6070, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6070, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_bps_ahb_clk", - .parent_names = (const char *[]){ - "cam_cc_slow_ahb_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_bps_areg_clk = { - .halt_reg = 0x6054, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6054, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_bps_areg_clk", - .parent_names = (const char *[]){ - "cam_cc_fast_ahb_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_bps_axi_clk = { - .halt_reg = 0x6038, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6038, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_bps_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_bps_clk = { - .halt_reg = 0x6028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_bps_clk", - .parent_names = (const char *[]){ - "cam_cc_bps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_camnoc_axi_clk = { - .halt_reg = 0xb124, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb124, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_camnoc_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_cci_0_clk = { - .halt_reg = 0xb0f0, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb0f0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_cci_0_clk", - .parent_names = (const char *[]){ - "cam_cc_cci_0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_cci_1_clk = { - .halt_reg = 0xb164, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb164, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_cci_1_clk", - .parent_names = (const char *[]){ - "cam_cc_cci_1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_core_ahb_clk = { - .halt_reg = 0xb144, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0xb144, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_core_ahb_clk", - .parent_names = (const char *[]){ - "cam_cc_slow_ahb_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_cpas_ahb_clk = { - .halt_reg = 0xb11c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb11c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_cpas_ahb_clk", - .parent_names = (const char *[]){ - "cam_cc_slow_ahb_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_csi0phytimer_clk = { - .halt_reg = 0x501c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x501c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_csi0phytimer_clk", - .parent_names = (const char *[]){ - "cam_cc_csi0phytimer_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_csi1phytimer_clk = { - .halt_reg = 0x5040, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x5040, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_csi1phytimer_clk", - .parent_names = (const char *[]){ - "cam_cc_csi1phytimer_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_csi2phytimer_clk = { - .halt_reg = 0x5064, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x5064, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_csi2phytimer_clk", - .parent_names = (const char *[]){ - "cam_cc_csi2phytimer_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_csi3phytimer_clk = { - .halt_reg = 0x5088, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x5088, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_csi3phytimer_clk", - .parent_names = (const char *[]){ - "cam_cc_csi3phytimer_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_csiphy0_clk = { - .halt_reg = 0x5020, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x5020, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_csiphy0_clk", - .parent_names = (const char *[]){ - "cam_cc_cphy_rx_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_csiphy1_clk = { - .halt_reg = 0x5044, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x5044, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_csiphy1_clk", - .parent_names = (const char *[]){ - "cam_cc_cphy_rx_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_csiphy2_clk = { - .halt_reg = 0x5068, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x5068, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_csiphy2_clk", - .parent_names = (const char *[]){ - "cam_cc_cphy_rx_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_csiphy3_clk = { - .halt_reg = 0x508c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x508c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_csiphy3_clk", - .parent_names = (const char *[]){ - "cam_cc_cphy_rx_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_icp_clk = { - .halt_reg = 0xb0a0, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb0a0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_icp_clk", - .parent_names = (const char *[]){ - "cam_cc_icp_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_icp_ts_clk = { - .halt_reg = 0xb080, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb080, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_icp_ts_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_0_axi_clk = { - .halt_reg = 0x9080, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x9080, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_ife_0_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_0_clk = { - .halt_reg = 0x9028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x9028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_ife_0_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { - .halt_reg = 0x907c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x907c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_ife_0_cphy_rx_clk", - .parent_names = (const char *[]){ - "cam_cc_cphy_rx_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_0_csid_clk = { - .halt_reg = 0x9054, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x9054, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_ife_0_csid_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_0_csid_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_0_dsp_clk = { - .halt_reg = 0x9038, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x9038, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_ife_0_dsp_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_1_axi_clk = { - .halt_reg = 0xa058, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xa058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_ife_1_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_1_clk = { - .halt_reg = 0xa028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xa028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_ife_1_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { - .halt_reg = 0xa054, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xa054, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_ife_1_cphy_rx_clk", - .parent_names = (const char *[]){ - "cam_cc_cphy_rx_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_1_csid_clk = { - .halt_reg = 0xa04c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xa04c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_ife_1_csid_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_1_csid_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_1_dsp_clk = { - .halt_reg = 0xa030, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xa030, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_ife_1_dsp_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_lite_clk = { - .halt_reg = 0xb01c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb01c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_ife_lite_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_lite_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { - .halt_reg = 0xb044, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb044, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_ife_lite_cphy_rx_clk", - .parent_names = (const char *[]){ - "cam_cc_cphy_rx_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ife_lite_csid_clk = { - .halt_reg = 0xb03c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb03c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_ife_lite_csid_clk", - .parent_names = (const char *[]){ - "cam_cc_ife_lite_csid_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ipe_0_ahb_clk = { - .halt_reg = 0x7040, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x7040, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_ipe_0_ahb_clk", - .parent_names = (const char *[]){ - "cam_cc_slow_ahb_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ipe_0_areg_clk = { - .halt_reg = 0x703c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x703c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_ipe_0_areg_clk", - .parent_names = (const char *[]){ - "cam_cc_fast_ahb_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ipe_0_axi_clk = { - .halt_reg = 0x7038, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x7038, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_ipe_0_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_ipe_0_clk = { - .halt_reg = 0x7028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x7028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_ipe_0_clk", - .parent_names = (const char *[]){ - "cam_cc_ipe_0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_jpeg_clk = { - .halt_reg = 0xb064, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb064, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_jpeg_clk", - .parent_names = (const char *[]){ - "cam_cc_jpeg_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_lrme_clk = { - .halt_reg = 0xb110, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb110, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_lrme_clk", - .parent_names = (const char *[]){ - "cam_cc_lrme_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_mclk0_clk = { - .halt_reg = 0x401c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x401c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_mclk0_clk", - .parent_names = (const char *[]){ - "cam_cc_mclk0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_mclk1_clk = { - .halt_reg = 0x403c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x403c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_mclk1_clk", - .parent_names = (const char *[]){ - "cam_cc_mclk1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_mclk2_clk = { - .halt_reg = 0x405c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x405c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_mclk2_clk", - .parent_names = (const char *[]){ - "cam_cc_mclk2_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_mclk3_clk = { - .halt_reg = 0x407c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x407c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_mclk3_clk", - .parent_names = (const char *[]){ - "cam_cc_mclk3_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_mclk4_clk = { - .halt_reg = 0x409c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x409c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_mclk4_clk", - .parent_names = (const char *[]){ - "cam_cc_mclk4_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_soc_ahb_clk = { - .halt_reg = 0xb140, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb140, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_soc_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch cam_cc_sys_tmr_clk = { - .halt_reg = 0xb0a8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb0a8, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "cam_cc_sys_tmr_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -struct clk_hw *cam_cc_atoll_hws[] = { - [CAM_CC_PLL2_OUT_EARLY] = &cam_cc_pll2_out_early.hw, -}; - -static struct clk_regmap *cam_cc_atoll_clocks[] = { - [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, - [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr, - [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr, - [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, - [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, - [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, - [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, - [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, - [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, - [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, - [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, - [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, - [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, - [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, - [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, - [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, - [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, - [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, - [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, - [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, - [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, - [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, - [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, - [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, - [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, - [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, - [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, - [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, - [CAM_CC_ICP_TS_CLK] = &cam_cc_icp_ts_clk.clkr, - [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr, - [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, - [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, - [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr, - [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr, - [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr, - [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, - [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr, - [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, - [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, - [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr, - [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr, - [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr, - [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, - [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, - [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, - [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, - [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, - [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, - [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr, - [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr, - [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr, - [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr, - [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr, - [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, - [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, - [CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr, - [CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr, - [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, - [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, - [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, - [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, - [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, - [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, - [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, - [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, - [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, - [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, - [CAM_CC_PLL0] = &cam_cc_pll0.clkr, - [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, - [CAM_CC_PLL1] = &cam_cc_pll1.clkr, - [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, - [CAM_CC_PLL2] = &cam_cc_pll2.clkr, - [CAM_CC_PLL2_OUT_AUX2] = &cam_cc_pll2_out_aux2.clkr, - [CAM_CC_PLL3] = &cam_cc_pll3.clkr, - [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, - [CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr, - [CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr, -}; - -static const struct regmap_config cam_cc_atoll_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0xd028, - .fast_io = true, -}; - -static const struct qcom_cc_desc cam_cc_atoll_desc = { - .config = &cam_cc_atoll_regmap_config, - .clks = cam_cc_atoll_clocks, - .num_clks = ARRAY_SIZE(cam_cc_atoll_clocks), - .hwclks = cam_cc_atoll_hws, - .num_hwclks = ARRAY_SIZE(cam_cc_atoll_hws), -}; - -static const struct of_device_id cam_cc_atoll_match_table[] = { - { .compatible = "qcom,atoll-camcc" }, - { } -}; -MODULE_DEVICE_TABLE(of, cam_cc_atoll_match_table); - -static int cam_cc_atoll_probe(struct platform_device *pdev) -{ - struct regmap *regmap; - int ret; - - vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx"); - if (IS_ERR(vdd_cx.regulator[0])) { - if (PTR_ERR(vdd_cx.regulator[0]) != -EPROBE_DEFER) - dev_err(&pdev->dev, - "Unable to get vdd_cx regulator\n"); - return PTR_ERR(vdd_cx.regulator[0]); - } - - vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx"); - if (IS_ERR(vdd_mx.regulator[0])) { - if (PTR_ERR(vdd_mx.regulator[0]) != -EPROBE_DEFER) - dev_err(&pdev->dev, - "Unable to get vdd_mx regulator\n"); - return PTR_ERR(vdd_mx.regulator[0]); - } - - regmap = qcom_cc_map(pdev, &cam_cc_atoll_desc); - if (IS_ERR(regmap)) { - pr_err("Failed to map the cam_cc registers\n"); - return PTR_ERR(regmap); - } - - clk_fabia_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); - clk_fabia_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); - clk_agera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); - clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); - - ret = qcom_cc_really_probe(pdev, &cam_cc_atoll_desc, regmap); - if (ret) { - dev_err(&pdev->dev, "Failed to register Camera CC clocks\n"); - return ret; - } - - dev_info(&pdev->dev, "Registered Camera CC clocks\n"); - return ret; -} - -static struct platform_driver cam_cc_atoll_driver = { - .probe = cam_cc_atoll_probe, - .driver = { - .name = "atoll-camcc", - .of_match_table = cam_cc_atoll_match_table, - }, -}; - -static int __init cam_cc_atoll_init(void) -{ - return platform_driver_register(&cam_cc_atoll_driver); -} -subsys_initcall(cam_cc_atoll_init); - -static void __exit cam_cc_atoll_exit(void) -{ - platform_driver_unregister(&cam_cc_atoll_driver); -} -module_exit(cam_cc_atoll_exit); - -MODULE_DESCRIPTION("QTI CAM_CC atoll Driver"); -MODULE_LICENSE("GPL v2"); -MODULE_ALIAS("platform:cam_cc-atoll"); diff --git a/drivers/clk/qcom/clk-cpu-osm.c b/drivers/clk/qcom/clk-cpu-osm.c index a397013479f1..8d49a370ce99 100644 --- a/drivers/clk/qcom/clk-cpu-osm.c +++ b/drivers/clk/qcom/clk-cpu-osm.c @@ -89,7 +89,6 @@ static bool is_sdmshrike; static bool is_sm6150; static bool is_sdmmagpie; static bool is_trinket; -static bool is_atoll; static inline struct clk_osm *to_clk_osm(struct clk_hw *_hw) { @@ -1032,8 +1031,7 @@ static int clk_osm_resources_init(struct platform_device *pdev) return -ENOMEM; } - if (is_sdmshrike || is_sm6150 || is_sdmmagpie || - is_trinket || is_atoll) + if (is_sdmshrike || is_sm6150 || is_sdmmagpie || is_trinket) return 0; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, @@ -1126,13 +1124,9 @@ static int clk_cpu_osm_driver_probe(struct platform_device *pdev) is_sdmshrike = of_device_is_compatible(pdev->dev.of_node, "qcom,clk-cpu-osm-sdmshrike"); - - is_atoll = of_device_is_compatible(pdev->dev.of_node, - "qcom,clk-cpu-osm-atoll"); - if (is_sdmshrike) clk_cpu_osm_driver_sdmshrike_fixup(); - else if (is_sm6150 || is_sdmmagpie || is_atoll) + else if (is_sm6150 || is_sdmmagpie) clk_cpu_osm_driver_sm6150_fixup(); else if (is_trinket) clk_cpu_osm_driver_trinket_fixup(); @@ -1189,8 +1183,7 @@ static int clk_cpu_osm_driver_probe(struct platform_device *pdev) return rc; } - if (!is_sdmshrike && !is_sm6150 && !is_sdmmagpie && - !is_trinket && !is_atoll) { + if (!is_sdmshrike && !is_sm6150 && !is_sdmmagpie && !is_trinket) { rc = clk_osm_read_lut(pdev, &perfpcl_clk); if (rc) { dev_err(&pdev->dev, "Unable to read OSM LUT for perf plus cluster, rc=%d\n", @@ -1272,7 +1265,6 @@ static const struct of_device_id match_table[] = { { .compatible = "qcom,clk-cpu-osm-sdmmagpie" }, { .compatible = "qcom,clk-cpu-osm-trinket" }, { .compatible = "qcom,clk-cpu-osm-sdmshrike" }, - { .compatible = "qcom,clk-cpu-osm-atoll" }, {} }; diff --git a/drivers/clk/qcom/clk-debug.c b/drivers/clk/qcom/clk-debug.c index 4cc851ed438a..1a2155c821f0 100644 --- a/drivers/clk/qcom/clk-debug.c +++ b/drivers/clk/qcom/clk-debug.c @@ -307,6 +307,19 @@ static int clk_debug_measure_get(void *data, u64 *val) DEFINE_SIMPLE_ATTRIBUTE(clk_measure_fops, clk_debug_measure_get, NULL, "%lld\n"); +// tedlin@ASTI, 2019/06/12 add for ddrfreq query +void clk_get_ddr_freq(u64* val) +{ + struct clk_debug_mux *meas = to_clk_measure(measure); + u32 regval; + *val = 0; + if (likely(meas)) { + regmap_read(meas->regmap[7], 80, ®val); + *val = 1000000000000UL; + do_div(*val, regval); + } +} + static int clk_debug_read_period(void *data, u64 *val) { struct clk_hw *hw = data; diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index b7e69b449d80..97d761daf08e 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -522,7 +522,6 @@ static const struct of_device_id clk_rpmh_match_table[] = { { .compatible = "qcom,rpmh-clk-sdmmagpie", .data = &clk_rpmh_sm6150}, { .compatible = "qcom,rpmh-clk-sdxprairie", .data = &clk_rpmh_sdxprairie}, - { .compatible = "qcom,rpmh-clk-atoll", .data = &clk_rpmh_sm6150}, { } }; MODULE_DEVICE_TABLE(of, clk_rpmh_match_table); diff --git a/drivers/clk/qcom/debugcc-atoll.c b/drivers/clk/qcom/debugcc-atoll.c deleted file mode 100644 index 0252b6db728a..000000000000 --- a/drivers/clk/qcom/debugcc-atoll.c +++ /dev/null @@ -1,800 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define pr_fmt(fmt) "clk: %s: " fmt, __func__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "clk-debug.h" - -static struct measure_clk_data debug_mux_priv = { - .ctl_reg = 0x62024, - .status_reg = 0x62028, - .xo_div4_cbcr = 0x43008, -}; - -static const char *const debug_mux_parent_names[] = { - "cam_cc_bps_ahb_clk", - "cam_cc_bps_areg_clk", - "cam_cc_bps_axi_clk", - "cam_cc_bps_clk", - "cam_cc_camnoc_atb_clk", - "cam_cc_camnoc_axi_clk", - "cam_cc_cci_0_clk", - "cam_cc_cci_1_clk", - "cam_cc_core_ahb_clk", - "cam_cc_cpas_ahb_clk", - "cam_cc_csi0phytimer_clk", - "cam_cc_csi1phytimer_clk", - "cam_cc_csi2phytimer_clk", - "cam_cc_csi3phytimer_clk", - "cam_cc_csiphy0_clk", - "cam_cc_csiphy1_clk", - "cam_cc_csiphy2_clk", - "cam_cc_csiphy3_clk", - "cam_cc_icp_apb_clk", - "cam_cc_icp_atb_clk", - "cam_cc_icp_clk", - "cam_cc_icp_cti_clk", - "cam_cc_icp_ts_clk", - "cam_cc_ife_0_axi_clk", - "cam_cc_ife_0_clk", - "cam_cc_ife_0_cphy_rx_clk", - "cam_cc_ife_0_csid_clk", - "cam_cc_ife_0_dsp_clk", - "cam_cc_ife_1_axi_clk", - "cam_cc_ife_1_clk", - "cam_cc_ife_1_cphy_rx_clk", - "cam_cc_ife_1_csid_clk", - "cam_cc_ife_1_dsp_clk", - "cam_cc_ife_lite_clk", - "cam_cc_ife_lite_cphy_rx_clk", - "cam_cc_ife_lite_csid_clk", - "cam_cc_ipe_0_ahb_clk", - "cam_cc_ipe_0_areg_clk", - "cam_cc_ipe_0_axi_clk", - "cam_cc_ipe_0_clk", - "cam_cc_jpeg_clk", - "cam_cc_lrme_clk", - "cam_cc_mclk0_clk", - "cam_cc_mclk1_clk", - "cam_cc_mclk2_clk", - "cam_cc_mclk3_clk", - "cam_cc_mclk4_clk", - "cam_cc_soc_ahb_clk", - "cam_cc_sys_tmr_clk", - "disp_cc_mdss_ahb_clk", - "disp_cc_mdss_byte0_clk", - "disp_cc_mdss_byte0_intf_clk", - "disp_cc_mdss_dp_aux_clk", - "disp_cc_mdss_dp_crypto_clk", - "disp_cc_mdss_dp_link_clk", - "disp_cc_mdss_dp_link_intf_clk", - "disp_cc_mdss_dp_pixel_clk", - "disp_cc_mdss_esc0_clk", - "disp_cc_mdss_mdp_clk", - "disp_cc_mdss_mdp_lut_clk", - "disp_cc_mdss_non_gdsc_ahb_clk", - "disp_cc_mdss_pclk0_clk", - "disp_cc_mdss_rot_clk", - "disp_cc_mdss_rscc_ahb_clk", - "disp_cc_mdss_rscc_vsync_clk", - "disp_cc_mdss_vsync_clk", - "disp_cc_sleep_clk", - "disp_cc_xo_clk", - "gcc_aggre_ufs_phy_axi_clk", - "gcc_aggre_usb3_prim_axi_clk", - "gcc_boot_rom_ahb_clk", - "gcc_camera_ahb_clk", - "gcc_camera_hf_axi_clk", - "gcc_camera_throttle_hf_axi_clk", - "gcc_camera_xo_clk", - "gcc_ce1_ahb_clk", - "gcc_ce1_axi_clk", - "gcc_ce1_clk", - "gcc_cfg_noc_usb3_prim_axi_clk", - "gcc_cpuss_ahb_clk", - "gcc_cpuss_gnoc_clk", - "gcc_cpuss_rbcpr_clk", - "gcc_ddrss_gpu_axi_clk", - "gcc_disp_ahb_clk", - "gcc_disp_gpll0_clk_src", - "gcc_disp_gpll0_div_clk_src", - "gcc_disp_hf_axi_clk", - "gcc_disp_throttle_hf_axi_clk", - "gcc_disp_xo_clk", - "gcc_gp1_clk", - "gcc_gp2_clk", - "gcc_gp3_clk", - "gcc_gpu_cfg_ahb_clk", - "gcc_gpu_gpll0_clk_src", - "gcc_gpu_gpll0_div_clk_src", - "gcc_gpu_memnoc_gfx_clk", - "gcc_gpu_snoc_dvm_gfx_clk", - "gcc_npu_axi_clk", - "gcc_npu_bwmon_axi_clk", - "gcc_npu_bwmon_dma_cfg_ahb_clk", - "gcc_npu_bwmon_dsp_cfg_ahb_clk", - "gcc_npu_cfg_ahb_clk", - "gcc_npu_dma_clk", - "gcc_npu_gpll0_clk_src", - "gcc_npu_gpll0_div_clk_src", - "gcc_pdm2_clk", - "gcc_pdm_ahb_clk", - "gcc_pdm_xo4_clk", - "gcc_prng_ahb_clk", - "gcc_qspi_cnoc_periph_ahb_clk", - "gcc_qspi_core_clk", - "gcc_qupv3_wrap0_core_2x_clk", - "gcc_qupv3_wrap0_core_clk", - "gcc_qupv3_wrap0_s0_clk", - "gcc_qupv3_wrap0_s1_clk", - "gcc_qupv3_wrap0_s2_clk", - "gcc_qupv3_wrap0_s3_clk", - "gcc_qupv3_wrap0_s4_clk", - "gcc_qupv3_wrap0_s5_clk", - "gcc_qupv3_wrap1_core_2x_clk", - "gcc_qupv3_wrap1_core_clk", - "gcc_qupv3_wrap1_s0_clk", - "gcc_qupv3_wrap1_s1_clk", - "gcc_qupv3_wrap1_s2_clk", - "gcc_qupv3_wrap1_s3_clk", - "gcc_qupv3_wrap1_s4_clk", - "gcc_qupv3_wrap1_s5_clk", - "gcc_qupv3_wrap_0_m_ahb_clk", - "gcc_qupv3_wrap_0_s_ahb_clk", - "gcc_qupv3_wrap_1_m_ahb_clk", - "gcc_qupv3_wrap_1_s_ahb_clk", - "gcc_sdcc1_ahb_clk", - "gcc_sdcc1_apps_clk", - "gcc_sdcc1_ice_core_clk", - "gcc_sdcc2_ahb_clk", - "gcc_sdcc2_apps_clk", - "gcc_sys_noc_cpuss_ahb_clk", - "gcc_ufs_phy_ahb_clk", - "gcc_ufs_phy_axi_clk", - "gcc_ufs_phy_ice_core_clk", - "gcc_ufs_phy_phy_aux_clk", - "gcc_ufs_phy_rx_symbol_0_clk", - "gcc_ufs_phy_tx_symbol_0_clk", - "gcc_ufs_phy_unipro_core_clk", - "gcc_usb30_prim_master_clk", - "gcc_usb30_prim_mock_utmi_clk", - "gcc_usb30_prim_sleep_clk", - "gcc_usb3_prim_phy_aux_clk", - "gcc_usb3_prim_phy_com_aux_clk", - "gcc_usb3_prim_phy_pipe_clk", - "gcc_usb_phy_cfg_ahb2phy_clk", - "gcc_video_ahb_clk", - "gcc_video_axi_clk", - "gcc_video_gpll0_div_clk_src", - "gcc_video_throttle_axi_clk", - "gcc_video_xo_clk", - "gpu_cc_acd_ahb_clk", - "gpu_cc_acd_cxo_clk", - "gpu_cc_ahb_clk", - "gpu_cc_crc_ahb_clk", - "gpu_cc_cx_apb_clk", - "gpu_cc_cx_gfx3d_clk", - "gpu_cc_cx_gfx3d_slv_clk", - "gpu_cc_cx_gmu_clk", - "gpu_cc_cx_qdss_at_clk", - "gpu_cc_cx_qdss_trig_clk", - "gpu_cc_cx_qdss_tsctr_clk", - "gpu_cc_cx_snoc_dvm_clk", - "gpu_cc_cxo_aon_clk", - "gpu_cc_cxo_clk", - "gpu_cc_gx_cxo_clk", - "gpu_cc_gx_gfx3d_clk", - "gpu_cc_gx_gmu_clk", - "gpu_cc_gx_qdss_tsctr_clk", - "gpu_cc_gx_vsense_clk", - "gpu_cc_rbcpr_ahb_clk", - "gpu_cc_rbcpr_clk", - "gpu_cc_sleep_clk", - "measure_only_mccc_clk", - "npu_cc_atb_clk", - "npu_cc_bto_core_clk", - "npu_cc_bwmon_clk", - "npu_cc_cal_hm0_cdc_clk", - "npu_cc_cal_hm0_clk", - "npu_cc_cal_hm0_perf_cnt_clk", - "npu_cc_core_clk", - "npu_cc_dsp_ahbm_clk", - "npu_cc_dsp_ahbs_clk", - "npu_cc_dsp_axi_clk", - "npu_cc_noc_ahb_clk", - "npu_cc_noc_axi_clk", - "npu_cc_noc_dma_clk", - "npu_cc_rsc_xo_clk", - "npu_cc_s2p_clk", - "npu_cc_xo_clk", - "video_cc_apb_clk", - "video_cc_at_clk", - "video_cc_qdss_trig_clk", - "video_cc_qdss_tsctr_div8_clk", - "video_cc_sleep_clk", - "video_cc_vcodec0_axi_clk", - "video_cc_vcodec0_core_clk", - "video_cc_venus_ahb_clk", - "video_cc_venus_ctl_axi_clk", - "video_cc_venus_ctl_core_clk", - "video_cc_xo_clk", - "l3_clk", - "pwrcl_clk", - "perfcl_clk", -}; - -static struct clk_debug_mux gcc_debug_mux = { - .priv = &debug_mux_priv, - .debug_offset = 0x62008, - .post_div_offset = 0x62000, - .cbcr_offset = 0x62004, - .period_offset = 0x50, - .src_sel_mask = 0x3FF, - .src_sel_shift = 0, - .post_div_mask = 0xF, - .post_div_shift = 0, - MUX_SRC_LIST( - { "cam_cc_bps_ahb_clk", 0x46, 4, CAM_CC, - 0xE, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_bps_areg_clk", 0x46, 4, CAM_CC, - 0xD, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_bps_axi_clk", 0x46, 4, CAM_CC, - 0xC, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_bps_clk", 0x46, 4, CAM_CC, - 0xB, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_camnoc_atb_clk", 0x46, 4, CAM_CC, - 0x34, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_camnoc_axi_clk", 0x46, 4, CAM_CC, - 0x2D, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_cci_0_clk", 0x46, 4, CAM_CC, - 0x2A, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_cci_1_clk", 0x46, 4, CAM_CC, - 0x3B, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_core_ahb_clk", 0x46, 4, CAM_CC, - 0x3A, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_cpas_ahb_clk", 0x46, 4, CAM_CC, - 0x2C, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_csi0phytimer_clk", 0x46, 4, CAM_CC, - 0x5, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_csi1phytimer_clk", 0x46, 4, CAM_CC, - 0x7, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_csi2phytimer_clk", 0x46, 4, CAM_CC, - 0x9, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_csi3phytimer_clk", 0x46, 4, CAM_CC, - 0x13, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_csiphy0_clk", 0x46, 4, CAM_CC, - 0x6, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_csiphy1_clk", 0x46, 4, CAM_CC, - 0x8, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_csiphy2_clk", 0x46, 4, CAM_CC, - 0xA, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_csiphy3_clk", 0x46, 4, CAM_CC, - 0x14, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_icp_apb_clk", 0x46, 4, CAM_CC, - 0x32, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_icp_atb_clk", 0x46, 4, CAM_CC, - 0x2F, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_icp_clk", 0x46, 4, CAM_CC, - 0x26, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_icp_cti_clk", 0x46, 4, CAM_CC, - 0x30, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_icp_ts_clk", 0x46, 4, CAM_CC, - 0x31, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_ife_0_axi_clk", 0x46, 4, CAM_CC, - 0x1B, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_ife_0_clk", 0x46, 4, CAM_CC, - 0x17, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_ife_0_cphy_rx_clk", 0x46, 4, CAM_CC, - 0x1A, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_ife_0_csid_clk", 0x46, 4, CAM_CC, - 0x19, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_ife_0_dsp_clk", 0x46, 4, CAM_CC, - 0x18, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_ife_1_axi_clk", 0x46, 4, CAM_CC, - 0x21, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_ife_1_clk", 0x46, 4, CAM_CC, - 0x1D, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_ife_1_cphy_rx_clk", 0x46, 4, CAM_CC, - 0x20, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_ife_1_csid_clk", 0x46, 4, CAM_CC, - 0x1F, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_ife_1_dsp_clk", 0x46, 4, CAM_CC, - 0x1E, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_ife_lite_clk", 0x46, 4, CAM_CC, - 0x22, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_ife_lite_cphy_rx_clk", 0x46, 4, CAM_CC, - 0x24, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_ife_lite_csid_clk", 0x46, 4, CAM_CC, - 0x23, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_ipe_0_ahb_clk", 0x46, 4, CAM_CC, - 0x12, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_ipe_0_areg_clk", 0x46, 4, CAM_CC, - 0x11, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_ipe_0_axi_clk", 0x46, 4, CAM_CC, - 0x10, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_ipe_0_clk", 0x46, 4, CAM_CC, - 0xF, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_jpeg_clk", 0x46, 4, CAM_CC, - 0x25, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_lrme_clk", 0x46, 4, CAM_CC, - 0x2B, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_mclk0_clk", 0x46, 4, CAM_CC, - 0x1, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_mclk1_clk", 0x46, 4, CAM_CC, - 0x2, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_mclk2_clk", 0x46, 4, CAM_CC, - 0x3, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_mclk3_clk", 0x46, 4, CAM_CC, - 0x4, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_mclk4_clk", 0x46, 4, CAM_CC, - 0x15, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_soc_ahb_clk", 0x46, 4, CAM_CC, - 0x2E, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "cam_cc_sys_tmr_clk", 0x46, 4, CAM_CC, - 0x33, 0xFF, 0, 0x3, 0, 2, 0xD000, 0xC004, 0xC008 }, - { "disp_cc_mdss_ahb_clk", 0x47, 4, DISP_CC, - 0x14, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, - { "disp_cc_mdss_byte0_clk", 0x47, 4, DISP_CC, - 0xC, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, - { "disp_cc_mdss_byte0_intf_clk", 0x47, 4, DISP_CC, - 0xD, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, - { "disp_cc_mdss_dp_aux_clk", 0x47, 4, DISP_CC, - 0x13, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, - { "disp_cc_mdss_dp_crypto_clk", 0x47, 4, DISP_CC, - 0x11, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, - { "disp_cc_mdss_dp_link_clk", 0x47, 4, DISP_CC, - 0xF, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, - { "disp_cc_mdss_dp_link_intf_clk", 0x47, 4, DISP_CC, - 0x10, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, - { "disp_cc_mdss_dp_pixel_clk", 0x47, 4, DISP_CC, - 0x12, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, - { "disp_cc_mdss_esc0_clk", 0x47, 4, DISP_CC, - 0xE, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, - { "disp_cc_mdss_mdp_clk", 0x47, 4, DISP_CC, - 0x8, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, - { "disp_cc_mdss_mdp_lut_clk", 0x47, 4, DISP_CC, - 0xA, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, - { "disp_cc_mdss_non_gdsc_ahb_clk", 0x47, 4, DISP_CC, - 0x15, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, - { "disp_cc_mdss_pclk0_clk", 0x47, 4, DISP_CC, - 0x7, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, - { "disp_cc_mdss_rot_clk", 0x47, 4, DISP_CC, - 0x9, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, - { "disp_cc_mdss_rscc_ahb_clk", 0x47, 4, DISP_CC, - 0x17, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, - { "disp_cc_mdss_rscc_vsync_clk", 0x47, 4, DISP_CC, - 0x16, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, - { "disp_cc_mdss_vsync_clk", 0x47, 4, DISP_CC, - 0xB, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, - { "disp_cc_sleep_clk", 0x47, 4, DISP_CC, - 0x1E, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, - { "disp_cc_xo_clk", 0x47, 4, DISP_CC, - 0x1D, 0xFF, 0, 0x3, 0, 4, 0x7000, 0x5008, 0x500C }, - { "gcc_aggre_ufs_phy_axi_clk", 0x11D, 4, GCC, - 0x11D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_aggre_usb3_prim_axi_clk", 0x11B, 4, GCC, - 0x11B, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_boot_rom_ahb_clk", 0x94, 4, GCC, - 0x94, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_camera_ahb_clk", 0x3A, 4, GCC, - 0x3A, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_camera_hf_axi_clk", 0x40, 4, GCC, - 0x40, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_camera_throttle_hf_axi_clk", 0x1AA, 4, GCC, - 0x1AA, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_camera_xo_clk", 0x43, 4, GCC, - 0x43, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_ce1_ahb_clk", 0xA9, 4, GCC, - 0xA9, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_ce1_axi_clk", 0xA8, 4, GCC, - 0xA8, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_ce1_clk", 0xA7, 4, GCC, - 0xA7, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_cfg_noc_usb3_prim_axi_clk", 0x1D, 4, GCC, - 0x1D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_cpuss_ahb_clk", 0xCE, 4, GCC, - 0xCE, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_cpuss_gnoc_clk", 0xCF, 4, GCC, - 0xCF, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_cpuss_rbcpr_clk", 0xD0, 4, GCC, - 0xD0, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_ddrss_gpu_axi_clk", 0xBB, 4, GCC, - 0xBB, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_disp_ahb_clk", 0x3B, 4, GCC, - 0x3B, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_disp_gpll0_clk_src", 0x4C, 4, GCC, - 0x4C, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_disp_gpll0_div_clk_src", 0x4D, 4, GCC, - 0x4D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_disp_hf_axi_clk", 0x41, 4, GCC, - 0x41, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_disp_throttle_hf_axi_clk", 0x1AB, 4, GCC, - 0x1AB, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_disp_xo_clk", 0x44, 4, GCC, - 0x44, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_gp1_clk", 0xDE, 4, GCC, - 0xDE, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_gp2_clk", 0xDF, 4, GCC, - 0xDF, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_gp3_clk", 0xE0, 4, GCC, - 0xE0, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_gpu_cfg_ahb_clk", 0x142, 4, GCC, - 0x142, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_gpu_gpll0_clk_src", 0x148, 4, GCC, - 0x148, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_gpu_gpll0_div_clk_src", 0x149, 4, GCC, - 0x149, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_gpu_memnoc_gfx_clk", 0x145, 4, GCC, - 0x145, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_gpu_snoc_dvm_gfx_clk", 0x147, 4, GCC, - 0x147, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_npu_axi_clk", 0x16A, 4, GCC, - 0x16A, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_npu_bwmon_axi_clk", 0x182, 4, GCC, - 0x182, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_npu_bwmon_dma_cfg_ahb_clk", 0x7E, 4, GCC, - 0x7E, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_npu_bwmon_dsp_cfg_ahb_clk", 0x7F, 4, GCC, - 0x7F, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_npu_cfg_ahb_clk", 0x169, 4, GCC, - 0x169, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_npu_dma_clk", 0x185, 4, GCC, - 0x185, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_npu_gpll0_clk_src", 0x16D, 4, GCC, - 0x16D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_npu_gpll0_div_clk_src", 0x16E, 4, GCC, - 0x16E, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_pdm2_clk", 0x8E, 4, GCC, - 0x8E, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_pdm_ahb_clk", 0x8C, 4, GCC, - 0x8C, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_pdm_xo4_clk", 0x8D, 4, GCC, - 0x8D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_prng_ahb_clk", 0x8F, 4, GCC, - 0x8F, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_qspi_cnoc_periph_ahb_clk", 0x1B0, 4, GCC, - 0x1B0, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_qspi_core_clk", 0x1B1, 4, GCC, - 0x1B1, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_qupv3_wrap0_core_2x_clk", 0x77, 4, GCC, - 0x77, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_qupv3_wrap0_core_clk", 0x76, 4, GCC, - 0x76, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_qupv3_wrap0_s0_clk", 0x78, 4, GCC, - 0x78, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_qupv3_wrap0_s1_clk", 0x79, 4, GCC, - 0x79, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_qupv3_wrap0_s2_clk", 0x7A, 4, GCC, - 0x7A, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_qupv3_wrap0_s3_clk", 0x7B, 4, GCC, - 0x7B, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_qupv3_wrap0_s4_clk", 0x7C, 4, GCC, - 0x7C, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_qupv3_wrap0_s5_clk", 0x7D, 4, GCC, - 0x7D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_qupv3_wrap1_core_2x_clk", 0x80, 4, GCC, - 0x80, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_qupv3_wrap1_core_clk", 0x81, 4, GCC, - 0x81, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_qupv3_wrap1_s0_clk", 0x84, 4, GCC, - 0x84, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_qupv3_wrap1_s1_clk", 0x85, 4, GCC, - 0x85, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_qupv3_wrap1_s2_clk", 0x86, 4, GCC, - 0x86, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_qupv3_wrap1_s3_clk", 0x87, 4, GCC, - 0x87, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_qupv3_wrap1_s4_clk", 0x88, 4, GCC, - 0x88, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_qupv3_wrap1_s5_clk", 0x89, 4, GCC, - 0x89, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_qupv3_wrap_0_m_ahb_clk", 0x74, 4, GCC, - 0x74, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_qupv3_wrap_0_s_ahb_clk", 0x75, 4, GCC, - 0x75, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_qupv3_wrap_1_m_ahb_clk", 0x82, 4, GCC, - 0x82, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_qupv3_wrap_1_s_ahb_clk", 0x83, 4, GCC, - 0x83, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_sdcc1_ahb_clk", 0x15C, 4, GCC, - 0x15C, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_sdcc1_apps_clk", 0x15B, 4, GCC, - 0x15B, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_sdcc1_ice_core_clk", 0x15D, 4, GCC, - 0x15D, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_sdcc2_ahb_clk", 0x71, 4, GCC, - 0x71, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_sdcc2_apps_clk", 0x70, 4, GCC, - 0x70, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_sys_noc_cpuss_ahb_clk", 0xC, 4, GCC, - 0xC, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_ufs_phy_ahb_clk", 0xFC, 4, GCC, - 0xFC, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_ufs_phy_axi_clk", 0xFB, 4, GCC, - 0xFB, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_ufs_phy_ice_core_clk", 0x102, 4, GCC, - 0x102, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_ufs_phy_phy_aux_clk", 0x103, 4, GCC, - 0x103, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_ufs_phy_rx_symbol_0_clk", 0xFE, 4, GCC, - 0xFE, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_ufs_phy_tx_symbol_0_clk", 0xFD, 4, GCC, - 0xFD, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_ufs_phy_unipro_core_clk", 0x101, 4, GCC, - 0x101, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_usb30_prim_master_clk", 0x5F, 4, GCC, - 0x5F, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_usb30_prim_mock_utmi_clk", 0x61, 4, GCC, - 0x61, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_usb30_prim_sleep_clk", 0x60, 4, GCC, - 0x60, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_usb3_prim_phy_aux_clk", 0x62, 4, GCC, - 0x62, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_usb3_prim_phy_com_aux_clk", 0x63, 4, GCC, - 0x63, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_usb3_prim_phy_pipe_clk", 0x64, 4, GCC, - 0x64, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_usb_phy_cfg_ahb2phy_clk", 0x6F, 4, GCC, - 0x6F, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_video_ahb_clk", 0x39, 4, GCC, - 0x39, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_video_axi_clk", 0x3F, 4, GCC, - 0x3F, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_video_gpll0_div_clk_src", 0x18A, 4, GCC, - 0x18A, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_video_throttle_axi_clk", 0x1A9, 4, GCC, - 0x1A9, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gcc_video_xo_clk", 0x42, 4, GCC, - 0x42, 0x3FF, 0, 0xF, 0, 4, 0x62008, 0x62000, 0x62004 }, - { "gpu_cc_acd_ahb_clk", 0x144, 4, GPU_CC, - 0x24, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, - { "gpu_cc_acd_cxo_clk", 0x144, 4, GPU_CC, - 0x1F, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, - { "gpu_cc_ahb_clk", 0x144, 4, GPU_CC, - 0x11, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, - { "gpu_cc_crc_ahb_clk", 0x144, 4, GPU_CC, - 0x12, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, - { "gpu_cc_cx_apb_clk", 0x144, 4, GPU_CC, - 0x15, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, - { "gpu_cc_cx_gfx3d_clk", 0x144, 4, GPU_CC, - 0x1A, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, - { "gpu_cc_cx_gfx3d_slv_clk", 0x144, 4, GPU_CC, - 0x1B, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, - { "gpu_cc_cx_gmu_clk", 0x144, 4, GPU_CC, - 0x19, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, - { "gpu_cc_cx_qdss_at_clk", 0x144, 4, GPU_CC, - 0x13, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, - { "gpu_cc_cx_qdss_trig_clk", 0x144, 4, GPU_CC, - 0x18, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, - { "gpu_cc_cx_qdss_tsctr_clk", 0x144, 4, GPU_CC, - 0x14, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, - { "gpu_cc_cx_snoc_dvm_clk", 0x144, 4, GPU_CC, - 0x16, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, - { "gpu_cc_cxo_aon_clk", 0x144, 4, GPU_CC, - 0xB, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, - { "gpu_cc_cxo_clk", 0x144, 4, GPU_CC, - 0xA, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, - { "gpu_cc_gx_cxo_clk", 0x144, 4, GPU_CC, - 0xF, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, - { "gpu_cc_gx_gfx3d_clk", 0x144, 4, GPU_CC, - 0xC, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, - { "gpu_cc_gx_gmu_clk", 0x144, 4, GPU_CC, - 0x10, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, - { "gpu_cc_gx_qdss_tsctr_clk", 0x144, 4, GPU_CC, - 0xE, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, - { "gpu_cc_gx_vsense_clk", 0x144, 4, GPU_CC, - 0xD, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, - { "gpu_cc_rbcpr_ahb_clk", 0x144, 4, GPU_CC, - 0x1D, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, - { "gpu_cc_rbcpr_clk", 0x144, 4, GPU_CC, - 0x1C, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, - { "gpu_cc_sleep_clk", 0x144, 4, GPU_CC, - 0x17, 0xFF, 0, 0x3, 0, 2, 0x1568, 0x10FC, 0x1100 }, - { "measure_only_mccc_clk", 0xC2, 1, MC_CC, - 0xC2, 0x3FF, 0, 0xF, 0, 1, 0x62008, 0x62000, 0x62004 }, - { "npu_cc_atb_clk", 0x16F, 4, NPU_CC, - 0x17, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, - { "npu_cc_bto_core_clk", 0x16F, 4, NPU_CC, - 0x19, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, - { "npu_cc_bwmon_clk", 0x16F, 4, NPU_CC, - 0x18, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, - { "npu_cc_cal_hm0_cdc_clk", 0x16F, 4, NPU_CC, - 0xB, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, - { "npu_cc_cal_hm0_clk", 0x16F, 4, NPU_CC, - 0x2, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, - { "npu_cc_cal_hm0_perf_cnt_clk", 0x16F, 4, NPU_CC, - 0xD, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, - { "npu_cc_core_clk", 0x16F, 4, NPU_CC, - 0x4, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, - { "npu_cc_dsp_ahbm_clk", 0x16F, 4, NPU_CC, - 0x1C, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, - { "npu_cc_dsp_ahbs_clk", 0x16F, 4, NPU_CC, - 0x1B, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, - { "npu_cc_dsp_axi_clk", 0x16F, 4, NPU_CC, - 0x1E, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, - { "npu_cc_noc_ahb_clk", 0x16F, 4, NPU_CC, - 0x13, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, - { "npu_cc_noc_axi_clk", 0x16F, 4, NPU_CC, - 0x12, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, - { "npu_cc_noc_dma_clk", 0x16F, 4, NPU_CC, - 0x11, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, - { "npu_cc_rsc_xo_clk", 0x16F, 4, NPU_CC, - 0x1A, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, - { "npu_cc_s2p_clk", 0x16F, 4, NPU_CC, - 0x16, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, - { "npu_cc_xo_clk", 0x16F, 4, NPU_CC, - 0x1, 0xFF, 0, 0x3, 0, 2, 0x3000, 0x3004, 0x3008 }, - { "video_cc_apb_clk", 0x48, 4, VIDEO_CC, - 0xA, 0x3F, 0, 0x7, 0, 5, 0xACC, 0x938, 0x940 }, - { "video_cc_at_clk", 0x48, 4, VIDEO_CC, - 0xD, 0x3F, 0, 0x7, 0, 5, 0xACC, 0x938, 0x940 }, - { "video_cc_qdss_trig_clk", 0x48, 4, VIDEO_CC, - 0x9, 0x3F, 0, 0x7, 0, 5, 0xACC, 0x938, 0x940 }, - { "video_cc_qdss_tsctr_div8_clk", 0x48, 4, VIDEO_CC, - 0xC, 0x3F, 0, 0x7, 0, 5, 0xACC, 0x938, 0x940 }, - { "video_cc_sleep_clk", 0x48, 4, VIDEO_CC, - 0x6, 0x3F, 0, 0x7, 0, 5, 0xACC, 0x938, 0x940 }, - { "video_cc_vcodec0_axi_clk", 0x48, 4, VIDEO_CC, - 0x8, 0x3F, 0, 0x7, 0, 5, 0xACC, 0x938, 0x940 }, - { "video_cc_vcodec0_core_clk", 0x48, 4, VIDEO_CC, - 0x3, 0x3F, 0, 0x7, 0, 5, 0xACC, 0x938, 0x940 }, - { "video_cc_venus_ahb_clk", 0x48, 4, VIDEO_CC, - 0xB, 0x3F, 0, 0x7, 0, 5, 0xACC, 0x938, 0x940 }, - { "video_cc_venus_ctl_axi_clk", 0x48, 4, VIDEO_CC, - 0x7, 0x3F, 0, 0x7, 0, 5, 0xACC, 0x938, 0x940 }, - { "video_cc_venus_ctl_core_clk", 0x48, 4, VIDEO_CC, - 0x1, 0x3F, 0, 0x7, 0, 5, 0xACC, 0x938, 0x940 }, - { "video_cc_xo_clk", 0x48, 4, VIDEO_CC, - 0x5, 0x3F, 0, 0x7, 0, 5, 0xACC, 0x938, 0x940 }, - { "l3_clk", 0xD6, 4, CPU_CC, - 0x46, 0x7F, 4, 0xF, 11, 1, 0x0, 0x0, U32_MAX, 16 }, - { "pwrcl_clk", 0xD6, 4, CPU_CC, - 0x44, 0x7F, 4, 0xF, 11, 1, 0x0, 0x0, U32_MAX, 16 }, - { "perfcl_clk", 0xD6, 4, CPU_CC, - 0x45, 0x7F, 4, 0xF, 11, 1, 0x0, 0x0, U32_MAX, 16 }, - ), - .hw.init = &(struct clk_init_data){ - .name = "gcc_debug_mux", - .ops = &clk_debug_mux_ops, - .parent_names = debug_mux_parent_names, - .num_parents = ARRAY_SIZE(debug_mux_parent_names), - .flags = CLK_IS_MEASURE, - }, -}; - -static const struct of_device_id clk_debug_match_table[] = { - { .compatible = "qcom,atoll-debugcc" }, - { } -}; - -static int map_debug_bases(struct platform_device *pdev, char *base, int cc) -{ - if (!of_get_property(pdev->dev.of_node, base, NULL)) - return -ENODEV; - - gcc_debug_mux.regmap[cc] = - syscon_regmap_lookup_by_phandle(pdev->dev.of_node, base); - if (IS_ERR(gcc_debug_mux.regmap[cc])) { - pr_err("Failed to map %s (ret=%ld)\n", base, - PTR_ERR(gcc_debug_mux.regmap[cc])); - return PTR_ERR(gcc_debug_mux.regmap[cc]); - } - return 0; -} - -static int clk_debug_atoll_probe(struct platform_device *pdev) -{ - struct clk *clk; - int ret, count; - - clk = devm_clk_get(&pdev->dev, "xo_clk_src"); - if (IS_ERR(clk)) { - if (PTR_ERR(clk) != -EPROBE_DEFER) - dev_err(&pdev->dev, "Unable to get xo clock\n"); - return PTR_ERR(clk); - } - - debug_mux_priv.cxo = clk; - - ret = of_property_read_u32(pdev->dev.of_node, "qcom,cc-count", - &count); - if (ret < 0) { - dev_err(&pdev->dev, "Num of debug clock controller not specified\n"); - return ret; - } - - if (!count) { - dev_err(&pdev->dev, "Count of CC cannot be zero\n"); - return -EINVAL; - } - - gcc_debug_mux.regmap = devm_kzalloc(&pdev->dev, - sizeof(struct regmap *) * count, GFP_KERNEL); - if (!gcc_debug_mux.regmap) - return -ENOMEM; - - ret = map_debug_bases(pdev, "qcom,gcc", GCC); - if (ret) - return ret; - - ret = map_debug_bases(pdev, "qcom,dispcc", DISP_CC); - if (ret) - return ret; - - ret = map_debug_bases(pdev, "qcom,npucc", NPU_CC); - if (ret) - return ret; - - ret = map_debug_bases(pdev, "qcom,videocc", VIDEO_CC); - if (ret) - return ret; - - ret = map_debug_bases(pdev, "qcom,camcc", CAM_CC); - if (ret) - return ret; - - ret = map_debug_bases(pdev, "qcom,gpucc", GPU_CC); - if (ret) - return ret; - - ret = map_debug_bases(pdev, "qcom,cpucc", CPU_CC); - if (ret) - return ret; - - ret = map_debug_bases(pdev, "qcom,mccc", MC_CC); - if (ret) - return ret; - - clk = devm_clk_register(&pdev->dev, &gcc_debug_mux.hw); - if (IS_ERR(clk)) { - dev_err(&pdev->dev, "Unable to register GCC debug mux\n"); - return PTR_ERR(clk); - } - - ret = clk_debug_measure_register(&gcc_debug_mux.hw); - if (ret) - dev_err(&pdev->dev, "Could not register Measure clock\n"); - else - dev_info(&pdev->dev, "Registered debug mux successfully\n"); - - return ret; -} - -static struct platform_driver clk_debug_driver = { - .probe = clk_debug_atoll_probe, - .driver = { - .name = "atoll-debugcc", - .of_match_table = clk_debug_match_table, - }, -}; - -int __init clk_debug_atoll_init(void) -{ - return platform_driver_register(&clk_debug_driver); -} -fs_initcall(clk_debug_atoll_init); - -MODULE_DESCRIPTION("QTI DEBUG CC atoll Driver"); -MODULE_LICENSE("GPL v2"); -MODULE_ALIAS("platform:atoll-debugcc"); diff --git a/drivers/clk/qcom/dispcc-atoll.c b/drivers/clk/qcom/dispcc-atoll.c deleted file mode 100644 index e959c2919d39..000000000000 --- a/drivers/clk/qcom/dispcc-atoll.c +++ /dev/null @@ -1,889 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define pr_fmt(fmt) "clk: %s: " fmt, __func__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "clk-alpha-pll.h" -#include "clk-branch.h" -#include "clk-rcg.h" -#include "clk-regmap.h" -#include "clk-regmap-divider.h" -#include "common.h" -#include "reset.h" -#include "vdd-level-sdmmagpie.h" - -#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } - -static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner); - -enum { - P_BI_TCXO, - P_CHIP_SLEEP_CLK, - P_CORE_BI_PLL_TEST_SE, - P_DISP_CC_PLL0_OUT_EVEN, - P_DISP_CC_PLL0_OUT_MAIN, - P_DP_PHY_PLL_LINK_CLK, - P_DP_PHY_PLL_VCO_DIV_CLK, - P_DSI0_PHY_PLL_OUT_BYTECLK, - P_DSI0_PHY_PLL_OUT_DSICLK, - P_GPLL0_OUT_MAIN, -}; - -static const struct parent_map disp_cc_parent_map_0[] = { - { P_BI_TCXO, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const disp_cc_parent_names_0[] = { - "bi_tcxo", - "core_bi_pll_test_se", -}; - -static const struct parent_map disp_cc_parent_map_1[] = { - { P_BI_TCXO, 0 }, - { P_DP_PHY_PLL_LINK_CLK, 1 }, - { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const disp_cc_parent_names_1[] = { - "bi_tcxo", - "dp_phy_pll_link_clk", - "dp_phy_pll_vco_div_clk", - "core_bi_pll_test_se", -}; - -static const struct parent_map disp_cc_parent_map_2[] = { - { P_BI_TCXO, 0 }, - { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const disp_cc_parent_names_2[] = { - "bi_tcxo", - "dsi0_phy_pll_out_byteclk", - "core_bi_pll_test_se", -}; - -static const struct parent_map disp_cc_parent_map_3[] = { - { P_BI_TCXO, 0 }, - { P_DISP_CC_PLL0_OUT_MAIN, 1 }, - { P_GPLL0_OUT_MAIN, 4 }, - { P_DISP_CC_PLL0_OUT_EVEN, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const disp_cc_parent_names_3[] = { - "bi_tcxo", - "disp_cc_pll0", - "gcc_disp_gpll0_clk_src", - "disp_cc_pll0_out_even", - "core_bi_pll_test_se", -}; - -static const struct parent_map disp_cc_parent_map_4[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 4 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const disp_cc_parent_names_4[] = { - "bi_tcxo", - "gcc_disp_gpll0_clk_src", - "core_bi_pll_test_se", -}; - -static const struct parent_map disp_cc_parent_map_5[] = { - { P_BI_TCXO, 0 }, - { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const disp_cc_parent_names_5[] = { - "bi_tcxo", - "dsi0_phy_pll_out_dsiclk", - "core_bi_pll_test_se", -}; - -static const struct parent_map disp_cc_parent_map_6[] = { - { P_CHIP_SLEEP_CLK, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const disp_cc_parent_names_6[] = { - "chip_sleep_clk", - "core_bi_pll_test_se", -}; - -static struct pll_vco fabia_vco[] = { - { 249600000, 2000000000, 0 }, - { 125000000, 1000000000, 1 }, -}; - -/* 1380MHz configuration */ -static const struct alpha_pll_config disp_cc_pll0_config = { - .l = 0x47, - .frac = 0xE000, -}; - -static struct clk_alpha_pll disp_cc_pll0 = { - .offset = 0x0, - .vco_table = fabia_vco, - .num_vco = ARRAY_SIZE(fabia_vco), - .type = FABIA_PLL, - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "disp_cc_pll0", - .parent_names = (const char *[]){ "bi_tcxo" }, - .num_parents = 1, - .ops = &clk_fabia_pll_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_MIN] = 615000000, - [VDD_LOW] = 1066000000, - [VDD_LOW_L1] = 1600000000, - [VDD_NOMINAL] = 2000000000}, - }, - }, -}; - - -static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { - .reg = 0x2128, - .shift = 0, - .width = 2, - .clkr.hw.init = &(struct clk_init_data) { - .name = "disp_cc_mdss_byte0_div_clk_src", - .parent_names = - (const char *[]){ "disp_cc_mdss_byte0_clk_src" }, - .num_parents = 1, - .flags = CLK_GET_RATE_NOCACHE, - .ops = &clk_regmap_div_ops, - }, -}; - - -static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = { - .reg = 0x2190, - .shift = 0, - .width = 2, - .clkr.hw.init = &(struct clk_init_data) { - .name = "disp_cc_mdss_dp_link_div_clk_src", - .parent_names = - (const char *[]){ "disp_cc_mdss_dp_link_clk_src" }, - .num_parents = 1, - .ops = &clk_regmap_div_ops, - }, -}; - -static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), - F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), - { } -}; - -static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { - .cmd_rcgr = 0x22bc, - .mnd_width = 0, - .hid_width = 5, - .parent_map = disp_cc_parent_map_4, - .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, - .enable_safe_config = true, - .clkr.hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_ahb_clk_src", - .parent_names = disp_cc_parent_names_4, - .num_parents = 3, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 19200000, - [VDD_LOW] = 37500000, - [VDD_NOMINAL] = 75000000}, - }, -}; - -static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { - .cmd_rcgr = 0x2110, - .mnd_width = 0, - .hid_width = 5, - .parent_map = disp_cc_parent_map_2, - .clkr.hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_byte0_clk_src", - .parent_names = disp_cc_parent_names_2, - .num_parents = 3, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - .ops = &clk_byte2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 187500000, - [VDD_LOW] = 300000000, - [VDD_LOW_L1] = 358000000}, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { - .cmd_rcgr = 0x21dc, - .mnd_width = 0, - .hid_width = 5, - .parent_map = disp_cc_parent_map_0, - .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_dp_aux_clk_src", - .parent_names = disp_cc_parent_names_0, - .num_parents = 2, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 19200000}, - }, -}; - -static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = { - F(108000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), - F(180000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), - F(360000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0), - F(540000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0), - { } -}; - -static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { - .cmd_rcgr = 0x2194, - .mnd_width = 0, - .hid_width = 5, - .parent_map = disp_cc_parent_map_1, - .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_dp_crypto_clk_src", - .parent_names = disp_cc_parent_names_1, - .num_parents = 4, - .flags = CLK_GET_RATE_NOCACHE, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 180000, - [VDD_LOW_L1] = 360000, - [VDD_NOMINAL] = 540000}, - }, -}; - -static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { - F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - { } -}; - -static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { - .cmd_rcgr = 0x2178, - .mnd_width = 0, - .hid_width = 5, - .parent_map = disp_cc_parent_map_1, - .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_dp_link_clk_src", - .parent_names = disp_cc_parent_names_1, - .num_parents = 4, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 270000, - [VDD_LOW_L1] = 540000, - [VDD_NOMINAL] = 810000}, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { - .cmd_rcgr = 0x21ac, - .mnd_width = 16, - .hid_width = 5, - .parent_map = disp_cc_parent_map_1, - .clkr.hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_dp_pixel_clk_src", - .parent_names = disp_cc_parent_names_1, - .num_parents = 4, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - .ops = &clk_dp_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 337500, - [VDD_NOMINAL] = 675000}, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { - .cmd_rcgr = 0x2148, - .mnd_width = 0, - .hid_width = 5, - .parent_map = disp_cc_parent_map_2, - .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_esc0_clk_src", - .parent_names = disp_cc_parent_names_2, - .num_parents = 3, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 19200000}, - }, -}; - -static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0), - F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { - .cmd_rcgr = 0x20c8, - .mnd_width = 0, - .hid_width = 5, - .parent_map = disp_cc_parent_map_3, - .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, - .enable_safe_config = true, - .clkr.hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_mdp_clk_src", - .parent_names = disp_cc_parent_names_3, - .num_parents = 5, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 200000000, - [VDD_LOW] = 300000000, - [VDD_LOW_L1] = 345000000, - [VDD_NOMINAL] = 460000000}, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { - .cmd_rcgr = 0x2098, - .mnd_width = 8, - .hid_width = 5, - .parent_map = disp_cc_parent_map_5, - .clkr.hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_pclk0_clk_src", - .parent_names = disp_cc_parent_names_5, - .num_parents = 3, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_pixel_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 300000000, - [VDD_LOW] = 525000000, - [VDD_LOW_L1] = 625000000}, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { - .cmd_rcgr = 0x20e0, - .mnd_width = 0, - .hid_width = 5, - .parent_map = disp_cc_parent_map_3, - .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, - .enable_safe_config = true, - .clkr.hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_rot_clk_src", - .parent_names = disp_cc_parent_names_3, - .num_parents = 5, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 200000000, - [VDD_LOW] = 300000000, - [VDD_LOW_L1] = 345000000, - [VDD_NOMINAL] = 460000000}, - }, -}; - -static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { - .cmd_rcgr = 0x20f8, - .mnd_width = 0, - .hid_width = 5, - .parent_map = disp_cc_parent_map_0, - .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_vsync_clk_src", - .parent_names = disp_cc_parent_names_0, - .num_parents = 2, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 19200000}, - }, -}; - -static struct clk_branch disp_cc_mdss_ahb_clk = { - .halt_reg = 0x2080, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2080, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_ahb_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_ahb_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_byte0_clk = { - .halt_reg = 0x2028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_byte0_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_byte0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_byte0_intf_clk = { - .halt_reg = 0x202c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x202c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_byte0_intf_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_byte0_div_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dp_aux_clk = { - .halt_reg = 0x2054, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2054, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_dp_aux_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_dp_aux_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dp_crypto_clk = { - .halt_reg = 0x2048, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2048, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_dp_crypto_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_dp_crypto_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dp_link_clk = { - .halt_reg = 0x2040, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2040, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_dp_link_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_dp_link_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { - .halt_reg = 0x2044, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2044, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_dp_link_intf_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_dp_link_div_clk_src", - }, - .num_parents = 1, - .flags = CLK_GET_RATE_NOCACHE, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_dp_pixel_clk = { - .halt_reg = 0x204c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x204c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_dp_pixel_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_dp_pixel_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_esc0_clk = { - .halt_reg = 0x2038, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2038, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_esc0_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_esc0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_mdp_clk = { - .halt_reg = 0x200c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x200c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_mdp_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_mdp_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_mdp_lut_clk = { - .halt_reg = 0x201c, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x201c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_mdp_lut_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_mdp_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { - .halt_reg = 0x4004, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x4004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_non_gdsc_ahb_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_ahb_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_pclk0_clk = { - .halt_reg = 0x2004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_pclk0_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_pclk0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_rot_clk = { - .halt_reg = 0x2014, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_rot_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_rot_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { - .halt_reg = 0x400c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x400c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_rscc_ahb_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_ahb_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { - .halt_reg = 0x4008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_rscc_vsync_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_vsync_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_mdss_vsync_clk = { - .halt_reg = 0x2024, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2024, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "disp_cc_mdss_vsync_clk", - .parent_names = (const char *[]){ - "disp_cc_mdss_vsync_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch disp_cc_xo_clk = { - .halt_reg = 0x605c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x605c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "disp_cc_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_regmap *disp_cc_atoll_clocks[] = { - [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, - [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, - [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, - [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, - [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, - [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, - [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr, - [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr, - [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr, - [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = &disp_cc_mdss_dp_crypto_clk_src.clkr, - [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr, - [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr, - [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = - &disp_cc_mdss_dp_link_div_clk_src.clkr, - [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr, - [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr, - [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr, - [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, - [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, - [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, - [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, - [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, - [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, - [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, - [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, - [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr, - [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr, - [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, - [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, - [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, - [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, - [DISP_CC_PLL0] = &disp_cc_pll0.clkr, - [DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr, -}; - -static const struct regmap_config disp_cc_atoll_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0x10000, - .fast_io = true, -}; - -static const struct qcom_cc_desc disp_cc_atoll_desc = { - .config = &disp_cc_atoll_regmap_config, - .clks = disp_cc_atoll_clocks, - .num_clks = ARRAY_SIZE(disp_cc_atoll_clocks), -}; - -static const struct of_device_id disp_cc_atoll_match_table[] = { - { .compatible = "qcom,atoll-dispcc" }, - { } -}; -MODULE_DEVICE_TABLE(of, disp_cc_atoll_match_table); - -static int disp_cc_atoll_probe(struct platform_device *pdev) -{ - struct regmap *regmap; - int ret; - - vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx"); - if (IS_ERR(vdd_cx.regulator[0])) { - if (PTR_ERR(vdd_cx.regulator[0]) != -EPROBE_DEFER) - dev_err(&pdev->dev, - "Unable to get vdd_cx regulator\n"); - return PTR_ERR(vdd_cx.regulator[0]); - } - - regmap = qcom_cc_map(pdev, &disp_cc_atoll_desc); - if (IS_ERR(regmap)) { - pr_err("Failed to map the disp_cc registers\n"); - return PTR_ERR(regmap); - } - - clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); - - ret = qcom_cc_really_probe(pdev, &disp_cc_atoll_desc, regmap); - if (ret) { - dev_err(&pdev->dev, "Failed to register Display CC clocks\n"); - return ret; - } - - dev_info(&pdev->dev, "Registered Display CC clocks\n"); - return ret; -} - -static struct platform_driver disp_cc_atoll_driver = { - .probe = disp_cc_atoll_probe, - .driver = { - .name = "atoll-dispcc", - .of_match_table = disp_cc_atoll_match_table, - }, -}; - -static int __init disp_cc_atoll_init(void) -{ - return platform_driver_register(&disp_cc_atoll_driver); -} -subsys_initcall(disp_cc_atoll_init); - -static void __exit disp_cc_atoll_exit(void) -{ - platform_driver_unregister(&disp_cc_atoll_driver); -} -module_exit(disp_cc_atoll_exit); - -MODULE_DESCRIPTION("QTI DISP_CC ATOLL Driver"); -MODULE_LICENSE("GPL v2"); -MODULE_ALIAS("platform:disp_cc-atoll"); diff --git a/drivers/clk/qcom/gcc-atoll.c b/drivers/clk/qcom/gcc-atoll.c deleted file mode 100644 index a67e9d49a9de..000000000000 --- a/drivers/clk/qcom/gcc-atoll.c +++ /dev/null @@ -1,2621 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define pr_fmt(fmt) "clk: %s: " fmt, __func__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "common.h" -#include "reset.h" -#include "clk-alpha-pll.h" -#include "clk-branch.h" -#include "clk-rcg.h" -#include "clk-regmap.h" -#include "vdd-level-sdmmagpie.h" - -#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } - -#define GCC_MMSS_MISC 0x9ffc -#define GCC_NPU_MISC 0x4d110 -#define GCC_GPU_MISC 0x71028 - -static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner); -static DEFINE_VDD_REGULATORS(vdd_cx_ao, VDD_NUM, 1, vdd_corner); - -enum { - P_BI_TCXO, - P_CORE_BI_PLL_TEST_SE, - P_GPLL0_OUT_EVEN, - P_GPLL0_OUT_MAIN, - P_GPLL1_OUT_MAIN, - P_GPLL4_OUT_MAIN, - P_GPLL6_OUT_MAIN, - P_GPLL7_OUT_MAIN, - P_SLEEP_CLK, -}; - -static const struct parent_map gcc_parent_map_0[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_0[] = { - "bi_tcxo", - "gpll0", - "gpll0_out_even", - "core_bi_pll_test_se", -}; - -static const char * const gcc_parent_names_0_ao[] = { - "bi_tcxo_ao", - "gpll0", - "gpll0_out_even", - "core_bi_pll_test_se", -}; - -static const struct parent_map gcc_parent_map_1[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL6_OUT_MAIN, 2 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_1[] = { - "bi_tcxo", - "gpll0", - "gpll6", - "gpll0_out_even", - "core_bi_pll_test_se", -}; - -static const struct parent_map gcc_parent_map_2[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL1_OUT_MAIN, 4 }, - { P_GPLL4_OUT_MAIN, 5 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_2[] = { - "bi_tcxo", - "gpll0", - "gpll1", - "gpll4", - "gpll0_out_even", - "core_bi_pll_test_se", -}; - -static const struct parent_map gcc_parent_map_3[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_3[] = { - "bi_tcxo", - "gpll0", - "core_bi_pll_test_se", -}; - -static const struct parent_map gcc_parent_map_4[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_SLEEP_CLK, 5 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_4[] = { - "bi_tcxo", - "gpll0", - "sleep_clk", - "gpll0_out_even", - "core_bi_pll_test_se", -}; - -static const struct parent_map gcc_parent_map_5[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL7_OUT_MAIN, 3 }, - { P_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_5[] = { - "bi_tcxo", - "gpll0", - "gpll7", - "gpll0_out_even", - "core_bi_pll_test_se", -}; - -static const struct parent_map gcc_parent_map_6[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_SLEEP_CLK, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_6[] = { - "bi_tcxo", - "gpll0", - "sleep_clk", - "core_bi_pll_test_se", -}; - -static struct pll_vco fabia_vco[] = { - { 249600000, 2000000000, 0 }, - { 125000000, 1000000000, 1 }, -}; - -static struct clk_alpha_pll gpll0 = { - .offset = 0x0, - .vco_table = fabia_vco, - .num_vco = ARRAY_SIZE(fabia_vco), - .type = FABIA_PLL, - .clkr = { - .enable_reg = 0x52010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpll0", - .parent_names = (const char *[]){ "bi_tcxo" }, - .num_parents = 1, - .ops = &clk_fabia_fixed_pll_ops, - }, - }, -}; - -static const struct clk_div_table post_div_table_gpll0_out_even[] = { - { 0x1, 2 }, - { } -}; - -static struct clk_alpha_pll_postdiv gpll0_out_even = { - .offset = 0x0, - .post_div_shift = 8, - .post_div_table = post_div_table_gpll0_out_even, - .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even), - .width = 4, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll0_out_even", - .parent_names = (const char *[]){ "gpll0" }, - .num_parents = 1, - .ops = &clk_generic_pll_postdiv_ops, - }, -}; - -static struct clk_fixed_factor gcc_pll0_main_div_cdiv = { - .mult = 1, - .div = 2, - .hw.init = &(struct clk_init_data){ - .name = "gcc_pll0_main_div_cdiv", - .parent_names = (const char *[]){ "gpll0" }, - .num_parents = 1, - .ops = &clk_fixed_factor_ops, - }, -}; - -static struct clk_alpha_pll gpll6 = { - .offset = 0x13000, - .vco_table = fabia_vco, - .num_vco = ARRAY_SIZE(fabia_vco), - .type = FABIA_PLL, - .clkr = { - .enable_reg = 0x52010, - .enable_mask = BIT(6), - .hw.init = &(struct clk_init_data){ - .name = "gpll6", - .parent_names = (const char *[]){ "bi_tcxo" }, - .num_parents = 1, - .ops = &clk_fabia_fixed_pll_ops, - }, - }, -}; - -static struct clk_alpha_pll gpll7 = { - .offset = 0x27000, - .vco_table = fabia_vco, - .num_vco = ARRAY_SIZE(fabia_vco), - .type = FABIA_PLL, - .clkr = { - .enable_reg = 0x52010, - .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ - .name = "gpll7", - .parent_names = (const char *[]){ "bi_tcxo" }, - .num_parents = 1, - .ops = &clk_fabia_fixed_pll_ops, - }, - }, -}; - -static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { - .cmd_rcgr = 0x48014, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_ahb_clk_src", - .parent_names = gcc_parent_names_0_ao, - .num_parents = 4, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx_ao, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 19200000, - }, - }, -}; - -static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), - F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_gp1_clk_src = { - .cmd_rcgr = 0x64004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_4, - .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_gp1_clk_src", - .parent_names = gcc_parent_names_4, - .num_parents = 5, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 50000000, - [VDD_LOW] = 100000000, - [VDD_NOMINAL] = 200000000}, - }, -}; - -static struct clk_rcg2 gcc_gp2_clk_src = { - .cmd_rcgr = 0x65004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_4, - .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_gp2_clk_src", - .parent_names = gcc_parent_names_4, - .num_parents = 5, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 50000000, - [VDD_LOW] = 100000000, - [VDD_NOMINAL] = 200000000}, - }, -}; - -static struct clk_rcg2 gcc_gp3_clk_src = { - .cmd_rcgr = 0x66004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_4, - .freq_tbl = ftbl_gcc_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_gp3_clk_src", - .parent_names = gcc_parent_names_4, - .num_parents = 5, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 50000000, - [VDD_LOW] = 100000000, - [VDD_NOMINAL] = 200000000}, - }, -}; - -static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_pdm2_clk_src = { - .cmd_rcgr = 0x33010, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_pdm2_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_pdm2_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 19200000, - [VDD_LOW] = 60000000}, - }, -}; - -static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = { - F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), - F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), - F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_qspi_core_clk_src = { - .cmd_rcgr = 0x4b00c, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gcc_qspi_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_core_clk_src", - .parent_names = gcc_parent_names_2, - .num_parents = 6, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 75000000, - [VDD_LOW] = 150000000, - [VDD_NOMINAL] = 300000000}, - }, -}; - -static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { - F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), - F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), - F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), - F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), - F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), - F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), - F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), - F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), - F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), - F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), - F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), - F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), - F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), - F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { - .cmd_rcgr = 0x17034, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s0_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 5, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 75000000, - [VDD_LOW] = 100000000, - [VDD_NOMINAL] = 128000000}, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { - .cmd_rcgr = 0x17164, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s1_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 5, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 75000000, - [VDD_LOW] = 100000000, - [VDD_NOMINAL] = 128000000}, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { - .cmd_rcgr = 0x17294, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s2_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 5, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 75000000, - [VDD_LOW] = 100000000, - [VDD_NOMINAL] = 128000000}, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { - .cmd_rcgr = 0x173c4, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s3_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 5, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 75000000, - [VDD_LOW] = 100000000, - [VDD_NOMINAL] = 128000000}, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { - .cmd_rcgr = 0x174f4, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s4_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 5, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 75000000, - [VDD_LOW] = 100000000, - [VDD_NOMINAL] = 128000000}, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { - .cmd_rcgr = 0x17624, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s5_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 5, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 75000000, - [VDD_LOW] = 100000000, - [VDD_NOMINAL] = 128000000}, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { - .cmd_rcgr = 0x18018, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s0_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 5, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 75000000, - [VDD_LOW] = 100000000, - [VDD_NOMINAL] = 128000000}, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { - .cmd_rcgr = 0x18148, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s1_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 5, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 75000000, - [VDD_LOW] = 100000000, - [VDD_NOMINAL] = 128000000}, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { - .cmd_rcgr = 0x18278, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s2_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 5, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 75000000, - [VDD_LOW] = 100000000, - [VDD_NOMINAL] = 128000000}, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { - .cmd_rcgr = 0x183a8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s3_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 5, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 75000000, - [VDD_LOW] = 100000000, - [VDD_NOMINAL] = 128000000}, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { - .cmd_rcgr = 0x184d8, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s4_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 5, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 75000000, - [VDD_LOW] = 100000000, - [VDD_NOMINAL] = 128000000}, - }, -}; - -static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { - .cmd_rcgr = 0x18608, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s5_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 5, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 75000000, - [VDD_LOW] = 100000000, - [VDD_NOMINAL] = 128000000}, - }, -}; - -static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { - F(144000, P_BI_TCXO, 16, 3, 25), - F(400000, P_BI_TCXO, 12, 1, 4), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3), - F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), - F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), - F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { - .cmd_rcgr = 0x12028, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, - .enable_safe_config = true, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc1_apps_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 5, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 100000000, - [VDD_LOW_L1] = 384000000}, - }, -}; - -static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { - F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), - F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { - .cmd_rcgr = 0x12010, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, - .enable_safe_config = true, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc1_ice_core_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 100000000, - [VDD_LOW] = 150000000, - [VDD_LOW_L1] = 300000000}, - }, -}; - -static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { - F(400000, P_BI_TCXO, 12, 1, 4), - F(9600000, P_BI_TCXO, 2, 0, 0), - F(19200000, P_BI_TCXO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), - F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { - .cmd_rcgr = 0x1400c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_5, - .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, - .enable_safe_config = true, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_apps_clk_src", - .parent_names = gcc_parent_names_5, - .num_parents = 5, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 100000000, - [VDD_LOW_L1] = 202000000}, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { - F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), - F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), - F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { - .cmd_rcgr = 0x77020, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, - .flags = FORCE_ENABLE_RCG, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_axi_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 50000000, - [VDD_LOW] = 100000000, - [VDD_NOMINAL] = 200000000, - [VDD_HIGH] = 240000000}, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { - F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), - F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), - F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), - F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { - .cmd_rcgr = 0x77048, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, - .flags = FORCE_ENABLE_RCG, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ice_core_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 75000000, - [VDD_LOW] = 150000000, - [VDD_NOMINAL] = 300000000}, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { - F(9600000, P_BI_TCXO, 2, 0, 0), - F(19200000, P_BI_TCXO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { - .cmd_rcgr = 0x77098, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_3, - .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, - .flags = FORCE_ENABLE_RCG, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_phy_aux_clk_src", - .parent_names = gcc_parent_names_3, - .num_parents = 3, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 19200000}, - }, -}; - -static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { - F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), - F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), - F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { - .cmd_rcgr = 0x77060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, - .flags = FORCE_ENABLE_RCG, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_unipro_core_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 37500000, - [VDD_LOW] = 75000000, - [VDD_NOMINAL] = 150000000}, - }, -}; - -static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { - F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), - F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { - .cmd_rcgr = 0xf01c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, - .enable_safe_config = true, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_master_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 66666667, - [VDD_LOW] = 133333333, - [VDD_NOMINAL] = 200000000, - [VDD_HIGH] = 240000000}, - }, -}; - -static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { - .cmd_rcgr = 0xf034, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, - .enable_safe_config = true, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_mock_utmi_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 19200000}, - }, -}; - -static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { - .cmd_rcgr = 0xf060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_6, - .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_aux_clk_src", - .parent_names = gcc_parent_names_6, - .num_parents = 4, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 19200000}, - }, -}; - -static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { - .halt_reg = 0x82024, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x82024, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x82024, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_ufs_phy_axi_clk", - .parent_names = (const char *[]){ - "gcc_ufs_phy_axi_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { - .halt_reg = 0x8201c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8201c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre_usb3_prim_axi_clk", - .parent_names = (const char *[]){ - "gcc_usb30_prim_master_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_boot_rom_ahb_clk = { - .halt_reg = 0x38004, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x38004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ - .name = "gcc_boot_rom_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_ahb_clk = { - .halt_reg = 0xb008, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_hf_axi_clk = { - .halt_reg = 0xb020, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb020, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_hf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_throttle_hf_axi_clk = { - .halt_reg = 0xb080, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb080, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb080, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_throttle_hf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_xo_clk = { - .halt_reg = 0xb02c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb02c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ce1_ahb_clk = { - .halt_reg = 0x4100c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x4100c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(3), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ce1_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ce1_axi_clk = { - .halt_reg = 0x41008, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ce1_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ce1_clk = { - .halt_reg = 0x41004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(5), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ce1_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { - .halt_reg = 0x502c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x502c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cfg_noc_usb3_prim_axi_clk", - .parent_names = (const char *[]){ - "gcc_usb30_prim_master_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_ahb_clk = { - .halt_reg = 0x48000, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(21), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_ahb_clk", - .parent_names = (const char *[]){ - "gcc_cpuss_ahb_clk_src", - }, - .num_parents = 1, - .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_gnoc_clk = { - .halt_reg = 0x48004, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x48004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(22), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_gnoc_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cpuss_rbcpr_clk = { - .halt_reg = 0x48008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x48008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_rbcpr_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ddrss_gpu_axi_clk = { - .halt_reg = 0x4452c, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x4452c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ddrss_gpu_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_ahb_clk = { - .halt_reg = 0xb00c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb00c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb00c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_gpll0_clk_src = { - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(18), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_gpll0_clk_src", - .parent_names = (const char *[]){ - "gpll0", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_gpll0_div_clk_src = { - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(19), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_gpll0_div_clk_src", - .parent_names = (const char *[]){ - "gcc_pll0_main_div_cdiv", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_hf_axi_clk = { - .halt_reg = 0xb024, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb024, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_hf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_throttle_hf_axi_clk = { - .halt_reg = 0xb084, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb084, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb084, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_throttle_hf_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_xo_clk = { - .halt_reg = 0xb030, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb030, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp1_clk = { - .halt_reg = 0x64000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x64000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp1_clk", - .parent_names = (const char *[]){ - "gcc_gp1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp2_clk = { - .halt_reg = 0x65000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x65000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp2_clk", - .parent_names = (const char *[]){ - "gcc_gp2_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp3_clk = { - .halt_reg = 0x66000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x66000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp3_clk", - .parent_names = (const char *[]){ - "gcc_gp3_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_cfg_ahb_clk = { - .halt_reg = 0x71004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x71004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x71004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_cfg_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_gpll0_clk_src = { - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_gpll0_clk_src", - .parent_names = (const char *[]){ - "gpll0", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_gpll0_div_clk_src = { - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(16), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_gpll0_div_clk_src", - .parent_names = (const char *[]){ - "gcc_pll0_main_div_cdiv", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_memnoc_gfx_clk = { - .halt_reg = 0x7100c, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x7100c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_memnoc_gfx_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { - .halt_reg = 0x71018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x71018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_snoc_dvm_gfx_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_axi_clk = { - .halt_reg = 0x4d008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4d008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_bwmon_axi_clk = { - .halt_reg = 0x73008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x73008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_bwmon_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_bwmon_dma_cfg_ahb_clk = { - .halt_reg = 0x73018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x73018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_bwmon_dma_cfg_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_bwmon_dsp_cfg_ahb_clk = { - .halt_reg = 0x7301c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x7301c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_bwmon_dsp_cfg_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_cfg_ahb_clk = { - .halt_reg = 0x4d004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x4d004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x4d004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_cfg_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_dma_clk = { - .halt_reg = 0x4d1a0, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x4d1a0, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x4d1a0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_dma_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_gpll0_clk_src = { - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(25), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_gpll0_clk_src", - .parent_names = (const char *[]){ - "gpll0", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_npu_gpll0_div_clk_src = { - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(26), - .hw.init = &(struct clk_init_data){ - .name = "gcc_npu_gpll0_div_clk_src", - .parent_names = (const char *[]){ - "gcc_pll0_main_div_cdiv", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm2_clk = { - .halt_reg = 0x3300c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3300c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pdm2_clk", - .parent_names = (const char *[]){ - "gcc_pdm2_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm_ahb_clk = { - .halt_reg = 0x33004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x33004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x33004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pdm_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm_xo4_clk = { - .halt_reg = 0x33008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x33008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pdm_xo4_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_prng_ahb_clk = { - .halt_reg = 0x34004, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x34004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(13), - .hw.init = &(struct clk_init_data){ - .name = "gcc_prng_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = { - .halt_reg = 0x4b004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x4b004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x4b004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_cnoc_periph_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qspi_core_clk = { - .halt_reg = 0x4b008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4b008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_core_clk", - .parent_names = (const char *[]){ - "gcc_qspi_core_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { - .halt_reg = 0x17014, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(9), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_core_2x_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_core_clk = { - .halt_reg = 0x1700c, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(8), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_core_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s0_clk = { - .halt_reg = 0x17030, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s0_clk", - .parent_names = (const char *[]){ - "gcc_qupv3_wrap0_s0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s1_clk = { - .halt_reg = 0x17160, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(11), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s1_clk", - .parent_names = (const char *[]){ - "gcc_qupv3_wrap0_s1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s2_clk = { - .halt_reg = 0x17290, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(12), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s2_clk", - .parent_names = (const char *[]){ - "gcc_qupv3_wrap0_s2_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s3_clk = { - .halt_reg = 0x173c0, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(13), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s3_clk", - .parent_names = (const char *[]){ - "gcc_qupv3_wrap0_s3_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s4_clk = { - .halt_reg = 0x174f0, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(14), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s4_clk", - .parent_names = (const char *[]){ - "gcc_qupv3_wrap0_s4_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap0_s5_clk = { - .halt_reg = 0x17620, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap0_s5_clk", - .parent_names = (const char *[]){ - "gcc_qupv3_wrap0_s5_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { - .halt_reg = 0x18004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(18), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_core_2x_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_core_clk = { - .halt_reg = 0x18008, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(19), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_core_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s0_clk = { - .halt_reg = 0x18014, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(22), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s0_clk", - .parent_names = (const char *[]){ - "gcc_qupv3_wrap1_s0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s1_clk = { - .halt_reg = 0x18144, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(23), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s1_clk", - .parent_names = (const char *[]){ - "gcc_qupv3_wrap1_s1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s2_clk = { - .halt_reg = 0x18274, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(24), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s2_clk", - .parent_names = (const char *[]){ - "gcc_qupv3_wrap1_s2_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s3_clk = { - .halt_reg = 0x183a4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(25), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s3_clk", - .parent_names = (const char *[]){ - "gcc_qupv3_wrap1_s3_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s4_clk = { - .halt_reg = 0x184d4, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(26), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s4_clk", - .parent_names = (const char *[]){ - "gcc_qupv3_wrap1_s4_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap1_s5_clk = { - .halt_reg = 0x18604, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(27), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap1_s5_clk", - .parent_names = (const char *[]){ - "gcc_qupv3_wrap1_s5_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { - .halt_reg = 0x17004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(6), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_0_m_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { - .halt_reg = 0x17008, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x17008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_0_s_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { - .halt_reg = 0x1800c, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(20), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_1_m_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { - .halt_reg = 0x18010, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x18010, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x52008, - .enable_mask = BIT(21), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qupv3_wrap_1_s_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc1_ahb_clk = { - .halt_reg = 0x12008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x12008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc1_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc1_apps_clk = { - .halt_reg = 0x1200c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1200c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc1_apps_clk", - .parent_names = (const char *[]){ - "gcc_sdcc1_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc1_ice_core_clk = { - .halt_reg = 0x12040, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x12040, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc1_ice_core_clk", - .parent_names = (const char *[]){ - "gcc_sdcc1_ice_core_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc2_ahb_clk = { - .halt_reg = 0x14008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x14008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc2_apps_clk = { - .halt_reg = 0x14004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x14004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_apps_clk", - .parent_names = (const char *[]){ - "gcc_sdcc2_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { - .halt_reg = 0x4144, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sys_noc_cpuss_ahb_clk", - .parent_names = (const char *[]){ - "gcc_cpuss_ahb_clk_src", - }, - .num_parents = 1, - .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_mem_clkref_clk = { - .halt_reg = 0x8c000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_mem_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_ahb_clk = { - .halt_reg = 0x77014, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77014, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_axi_clk = { - .halt_reg = 0x77038, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77038, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77038, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_axi_clk", - .parent_names = (const char *[]){ - "gcc_ufs_phy_axi_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_ice_core_clk = { - .halt_reg = 0x77090, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77090, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77090, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_ice_core_clk", - .parent_names = (const char *[]){ - "gcc_ufs_phy_ice_core_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_phy_aux_clk = { - .halt_reg = 0x77094, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x77094, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x77094, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_phy_aux_clk", - .parent_names = (const char *[]){ - "gcc_ufs_phy_phy_aux_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { - .halt_reg = 0x7701c, - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x7701c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_rx_symbol_0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { - .halt_reg = 0x77018, - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x77018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_tx_symbol_0_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_unipro_core_clk = { - .halt_reg = 0x7708c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x7708c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x7708c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_unipro_core_clk", - .parent_names = (const char *[]){ - "gcc_ufs_phy_unipro_core_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_prim_master_clk = { - .halt_reg = 0xf010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_master_clk", - .parent_names = (const char *[]){ - "gcc_usb30_prim_master_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { - .halt_reg = 0xf018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_mock_utmi_clk", - .parent_names = (const char *[]){ - "gcc_usb30_prim_mock_utmi_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_prim_sleep_clk = { - .halt_reg = 0xf014, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_prim_sleep_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_clkref_clk = { - .halt_reg = 0x8c010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8c010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_phy_aux_clk = { - .halt_reg = 0xf050, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf050, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_aux_clk", - .parent_names = (const char *[]){ - "gcc_usb3_prim_phy_aux_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { - .halt_reg = 0xf054, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf054, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_com_aux_clk", - .parent_names = (const char *[]){ - "gcc_usb3_prim_phy_aux_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { - .halt_reg = 0xf058, - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0xf058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_prim_phy_pipe_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { - .halt_reg = 0x6a004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x6a004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x6a004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb_phy_cfg_ahb2phy_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_ahb_clk = { - .halt_reg = 0xb004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_axi_clk = { - .halt_reg = 0xb01c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb01c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_gpll0_div_clk_src = { - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(20), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_gpll0_div_clk_src", - .parent_names = (const char *[]){ - "gcc_pll0_main_div_cdiv", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_throttle_axi_clk = { - .halt_reg = 0xb07c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0xb07c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0xb07c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_throttle_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_video_xo_clk = { - .halt_reg = 0xb028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xb028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -struct clk_hw *gcc_atoll_hws[] = { - [GCC_GPLL0_MAIN_DIV_CDIV] = &gcc_pll0_main_div_cdiv.hw, -}; - -static struct clk_regmap *gcc_atoll_clocks[] = { - [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, - [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, - [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, - [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, - [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, - [GCC_CAMERA_THROTTLE_HF_AXI_CLK] = &gcc_camera_throttle_hf_axi_clk.clkr, - [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, - [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, - [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, - [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, - [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, - [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, - [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, - [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, - [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, - [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr, - [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, - [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, - [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, - [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, - [GCC_DISP_THROTTLE_HF_AXI_CLK] = &gcc_disp_throttle_hf_axi_clk.clkr, - [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, - [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, - [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, - [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, - [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, - [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, - [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, - [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, - [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, - [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, - [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, - [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, - [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr, - [GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr, - [GCC_NPU_BWMON_DMA_CFG_AHB_CLK] = &gcc_npu_bwmon_dma_cfg_ahb_clk.clkr, - [GCC_NPU_BWMON_DSP_CFG_AHB_CLK] = &gcc_npu_bwmon_dsp_cfg_ahb_clk.clkr, - [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr, - [GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr, - [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr, - [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr, - [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, - [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, - [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, - [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, - [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, - [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr, - [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr, - [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr, - [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, - [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, - [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, - [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, - [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, - [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, - [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, - [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, - [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, - [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, - [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, - [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, - [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, - [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, - [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, - [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, - [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, - [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, - [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, - [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, - [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, - [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, - [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, - [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, - [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, - [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, - [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, - [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, - [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, - [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, - [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, - [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, - [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, - [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, - [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, - [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, - [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, - [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, - [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, - [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, - [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, - [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr, - [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, - [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, - [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, - [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, - [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, - [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, - [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, - [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, - [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, - [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, - [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = - &gcc_ufs_phy_unipro_core_clk_src.clkr, - [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, - [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, - [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, - [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = - &gcc_usb30_prim_mock_utmi_clk_src.clkr, - [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, - [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, - [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, - [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, - [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, - [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, - [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, - [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, - [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr, - [GCC_VIDEO_GPLL0_DIV_CLK_SRC] = &gcc_video_gpll0_div_clk_src.clkr, - [GCC_VIDEO_THROTTLE_AXI_CLK] = &gcc_video_throttle_axi_clk.clkr, - [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, - [GPLL0] = &gpll0.clkr, - [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, - [GPLL6] = &gpll6.clkr, - [GPLL7] = &gpll7.clkr, -}; - -static const struct qcom_reset_map gcc_atoll_resets[] = { - [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 }, - [GCC_QUSB2PHY_SEC_BCR] = { 0x26004 }, - [GCC_UFS_PHY_BCR] = { 0x77000 }, - [GCC_USB30_PRIM_BCR] = { 0xf000 }, - [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, - [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, - [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, - [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, - [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, - [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, - [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, -}; - -static struct clk_dfs gcc_dfs_clocks[] = { - { &gcc_qupv3_wrap0_s0_clk_src, DFS_ENABLE_RCG }, - { &gcc_qupv3_wrap0_s1_clk_src, DFS_ENABLE_RCG }, - { &gcc_qupv3_wrap0_s2_clk_src, DFS_ENABLE_RCG }, - { &gcc_qupv3_wrap0_s3_clk_src, DFS_ENABLE_RCG }, - { &gcc_qupv3_wrap0_s4_clk_src, DFS_ENABLE_RCG }, - { &gcc_qupv3_wrap0_s5_clk_src, DFS_ENABLE_RCG }, - { &gcc_qupv3_wrap1_s0_clk_src, DFS_ENABLE_RCG }, - { &gcc_qupv3_wrap1_s1_clk_src, DFS_ENABLE_RCG }, - { &gcc_qupv3_wrap1_s2_clk_src, DFS_ENABLE_RCG }, - { &gcc_qupv3_wrap1_s3_clk_src, DFS_ENABLE_RCG }, - { &gcc_qupv3_wrap1_s4_clk_src, DFS_ENABLE_RCG }, - { &gcc_qupv3_wrap1_s5_clk_src, DFS_ENABLE_RCG }, -}; - -static const struct qcom_cc_dfs_desc gcc_atoll_dfs_desc = { - .clks = gcc_dfs_clocks, - .num_clks = ARRAY_SIZE(gcc_dfs_clocks), -}; - -static const struct regmap_config gcc_atoll_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0x18208c, - .fast_io = true, -}; - -static const struct qcom_cc_desc gcc_atoll_desc = { - .config = &gcc_atoll_regmap_config, - .hwclks = gcc_atoll_hws, - .num_hwclks = ARRAY_SIZE(gcc_atoll_hws), - .clks = gcc_atoll_clocks, - .num_clks = ARRAY_SIZE(gcc_atoll_clocks), - .resets = gcc_atoll_resets, - .num_resets = ARRAY_SIZE(gcc_atoll_resets), -}; - -static const struct of_device_id gcc_atoll_match_table[] = { - { .compatible = "qcom,atoll-gcc"}, - { } -}; -MODULE_DEVICE_TABLE(of, gcc_atoll_match_table); - -static int gcc_atoll_probe(struct platform_device *pdev) -{ - struct regmap *regmap; - int ret; - - vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx"); - if (IS_ERR(vdd_cx.regulator[0])) { - if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER)) - dev_err(&pdev->dev, - "Unable to get vdd_cx regulator\n"); - return PTR_ERR(vdd_cx.regulator[0]); - } - - vdd_cx_ao.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx_ao"); - if (IS_ERR(vdd_cx_ao.regulator[0])) { - if (!(PTR_ERR(vdd_cx_ao.regulator[0]) == -EPROBE_DEFER)) - dev_err(&pdev->dev, - "Unable to get vdd_cx_ao regulator\n"); - return PTR_ERR(vdd_cx_ao.regulator[0]); - } - - regmap = qcom_cc_map(pdev, &gcc_atoll_desc); - if (IS_ERR(regmap)) { - pr_err("Failed to map the gcc registers\n"); - return PTR_ERR(regmap); - } - - /* - * Disable the GPLL0 active input to MM blocks, NPU - * and GPU via MISC registers. - */ - regmap_update_bits(regmap, GCC_MMSS_MISC, 0x3, 0x3); - regmap_update_bits(regmap, GCC_NPU_MISC, 0x3, 0x3); - regmap_update_bits(regmap, GCC_GPU_MISC, 0x3, 0x3); - - ret = qcom_cc_really_probe(pdev, &gcc_atoll_desc, regmap); - if (ret) { - dev_err(&pdev->dev, "Failed to register GCC clocks\n"); - return ret; - } - - /* DFS clock registration */ - ret = qcom_cc_register_rcg_dfs(pdev, &gcc_atoll_dfs_desc); - if (ret) - dev_err(&pdev->dev, "Failed to register with DFS!\n"); - - dev_info(&pdev->dev, "Registered GCC clocks\n"); - - return 0; -} - -static struct platform_driver gcc_atoll_driver = { - .probe = gcc_atoll_probe, - .driver = { - .name = "atoll-gcc", - .of_match_table = gcc_atoll_match_table, - }, -}; - -static int __init gcc_atoll_init(void) -{ - return platform_driver_register(&gcc_atoll_driver); -} -subsys_initcall(gcc_atoll_init); - -static void __exit gcc_atoll_exit(void) -{ - platform_driver_unregister(&gcc_atoll_driver); -} -module_exit(gcc_atoll_exit); - -MODULE_DESCRIPTION("QTI GCC atoll Driver"); -MODULE_LICENSE("GPL v2"); -MODULE_ALIAS("platform:gcc-atoll"); diff --git a/drivers/clk/qcom/gcc-sdmshrike.c b/drivers/clk/qcom/gcc-sdmshrike.c index ec5cd2cd6266..1d42142095fc 100644 --- a/drivers/clk/qcom/gcc-sdmshrike.c +++ b/drivers/clk/qcom/gcc-sdmshrike.c @@ -5051,8 +5051,6 @@ static const struct qcom_reset_map gcc_sdmshrike_resets[] = { [GCC_USB30_SEC_BCR] = { 0x10000 }, [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, [GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 }, - [GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 }, - [GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 }, }; diff --git a/drivers/clk/qcom/gpucc-sdmmagpie.c b/drivers/clk/qcom/gpucc-sdmmagpie.c index 0c48b27022dc..0d814dc0bd81 100644 --- a/drivers/clk/qcom/gpucc-sdmmagpie.c +++ b/drivers/clk/qcom/gpucc-sdmmagpie.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -578,7 +578,6 @@ static const struct qcom_cc_desc gpu_cc_sdmmagpie_desc = { static const struct of_device_id gpu_cc_sdmmagpie_match_table[] = { { .compatible = "qcom,gpucc-sdmmagpie" }, - { .compatible = "qcom,atoll-gpucc" }, { } }; MODULE_DEVICE_TABLE(of, gpu_cc_sdmmagpie_match_table); diff --git a/drivers/clk/qcom/mdss/mdss-pll-util.c b/drivers/clk/qcom/mdss/mdss-pll-util.c index 3e60d93f08f4..4d797729bb75 100644 --- a/drivers/clk/qcom/mdss/mdss-pll-util.c +++ b/drivers/clk/qcom/mdss/mdss-pll-util.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -337,7 +337,7 @@ static void mdss_pll_free_bootmem(u32 mem_addr, u32 size) free_reserved_page(pfn_to_page(pfn_idx)); } -static int mdss_pll_util_parse_dt_dfps_sub(struct platform_device *pdev, +static int mdss_pll_util_parse_dt_dfps(struct platform_device *pdev, struct mdss_pll_resources *pll_res) { int rc = 0; @@ -424,6 +424,9 @@ int mdss_pll_util_resource_parse(struct platform_device *pdev, goto clk_err; } + if (mdss_pll_util_parse_dt_dfps(pdev, pll_res)) + pr_err("dfps not enabled!\n"); + return rc; clk_err: @@ -432,13 +435,3 @@ int mdss_pll_util_resource_parse(struct platform_device *pdev, end: return rc; } - -void mdss_pll_util_parse_dt_dfps(struct platform_device *pdev, - struct mdss_pll_resources *pll_res) -{ - int rc = 0; - - rc = mdss_pll_util_parse_dt_dfps_sub(pdev, pll_res); - if (rc) - pr_err("dfps not enabled!\n"); -} diff --git a/drivers/clk/qcom/mdss/mdss-pll.c b/drivers/clk/qcom/mdss/mdss-pll.c index 7c4d0446a5d1..d07f5c262b17 100644 --- a/drivers/clk/qcom/mdss/mdss-pll.c +++ b/drivers/clk/qcom/mdss/mdss-pll.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -366,8 +366,6 @@ static int mdss_pll_probe(struct platform_device *pdev) goto clock_register_error; } - mdss_pll_util_parse_dt_dfps(pdev, pll_res); - return rc; clock_register_error: diff --git a/drivers/clk/qcom/mdss/mdss-pll.h b/drivers/clk/qcom/mdss/mdss-pll.h index dc3a66dd0794..397229d3c5c8 100644 --- a/drivers/clk/qcom/mdss/mdss-pll.h +++ b/drivers/clk/qcom/mdss/mdss-pll.h @@ -251,8 +251,6 @@ int mdss_pll_util_resource_enable(struct mdss_pll_resources *pll_res, bool enable); int mdss_pll_util_resource_parse(struct platform_device *pdev, struct mdss_pll_resources *pll_res); -void mdss_pll_util_parse_dt_dfps(struct platform_device *pdev, - struct mdss_pll_resources *pll_res); struct dss_vreg *mdss_pll_get_mp_by_reg_name(struct mdss_pll_resources *pll_res , char *name); #endif diff --git a/drivers/clk/qcom/npucc-atoll.c b/drivers/clk/qcom/npucc-atoll.c deleted file mode 100644 index 63a988d4dab1..000000000000 --- a/drivers/clk/qcom/npucc-atoll.c +++ /dev/null @@ -1,865 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define pr_fmt(fmt) "clk: %s: " fmt, __func__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "common.h" -#include "clk-regmap.h" -#include "clk-pll.h" -#include "clk-rcg.h" -#include "clk-branch.h" -#include "reset.h" -#include "clk-alpha-pll.h" -#include "vdd-level-sdmmagpie.h" - -#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } - -#define CRC_SID_FSM_CTRL 0x100c -#define CRC_SID_FSM_CTRL_SETTING 0x800000 -#define CRC_MND_CFG 0x1010 -#define CRC_MND_CFG_SETTING 0x15011 - -static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner); - -enum { - P_BI_TCXO, - P_CORE_BI_PLL_TEST_SE, - P_GCC_NPU_GPLL0_CLK, - P_GCC_NPU_GPLL0_DIV_CLK, - P_NPU_CC_PLL0_OUT_EVEN, - P_NPU_CC_PLL1_OUT_EVEN, - P_NPU_Q6SS_PLL_OUT_MAIN, - P_NPU_CC_CRC_DIV, -}; - -static const struct parent_map npu_cc_parent_map_0[] = { - { P_BI_TCXO, 0 }, - { P_NPU_CC_PLL1_OUT_EVEN, 1 }, - { P_NPU_CC_PLL0_OUT_EVEN, 2 }, - { P_GCC_NPU_GPLL0_CLK, 4 }, - { P_GCC_NPU_GPLL0_DIV_CLK, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const npu_cc_parent_names_0[] = { - "bi_tcxo", - "npu_cc_pll1_out_even", - "npu_cc_pll0_out_even", - "gcc_npu_gpll0_clk_src", - "gcc_npu_gpll0_div_clk_src", - "core_bi_pll_test_se", -}; - -static const struct parent_map npu_cc_parent_map_0_crc[] = { - { P_BI_TCXO, 0 }, - { P_NPU_CC_PLL1_OUT_EVEN, 1 }, - { P_NPU_CC_CRC_DIV, 2 }, - { P_GCC_NPU_GPLL0_CLK, 4 }, - { P_GCC_NPU_GPLL0_DIV_CLK, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const npu_cc_parent_names_0_crc[] = { - "bi_tcxo", - "npu_cc_pll1_out_even", - "npu_cc_crc_div", - "gcc_npu_gpll0_clk_src", - "gcc_npu_gpll0_div_clk_src", - "core_bi_pll_test_se", -}; - -static const struct parent_map npu_cc_parent_map_1[] = { - { P_BI_TCXO, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const npu_cc_parent_names_1[] = { - "bi_tcxo", - "core_bi_pll_test_se", -}; - -static const struct parent_map npu_cc_parent_map_2[] = { - { P_BI_TCXO, 0 }, - { P_NPU_Q6SS_PLL_OUT_MAIN, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const npu_cc_parent_names_2[] = { - "bi_tcxo", - "npu_q6ss_pll", - "core_bi_pll_test_se", -}; - -static struct pll_vco fabia_vco[] = { - { 249600000, 2000000000, 0 }, - { 125000000, 1000000000, 1 }, -}; - -static const struct alpha_pll_config npu_cc_pll0_config = { - .l = 0x1C, - .config_ctl_val = 0x20485699, - .config_ctl_hi_val = 0x00002067, - .user_ctl_val = 0x00000001, - .user_ctl_hi_val = 0x00004805, -}; - -static struct clk_alpha_pll npu_cc_pll0 = { - .offset = 0x0, - .vco_table = fabia_vco, - .num_vco = ARRAY_SIZE(fabia_vco), - .type = FABIA_PLL, - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "npu_cc_pll0", - .parent_names = (const char *[]){ "bi_tcxo" }, - .num_parents = 1, - .ops = &clk_fabia_pll_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_MIN] = 615000000, - [VDD_LOW] = 1066000000, - [VDD_LOW_L1] = 1600000000, - [VDD_NOMINAL] = 2000000000}, - }, - }, -}; - -static const struct clk_div_table post_div_table_npu_cc_pll0_out_even[] = { - { 0x0, 1 }, - { } -}; - -static struct clk_alpha_pll_postdiv npu_cc_pll0_out_even = { - .offset = 0x0, - .post_div_shift = 8, - .post_div_table = post_div_table_npu_cc_pll0_out_even, - .num_post_div = ARRAY_SIZE(post_div_table_npu_cc_pll0_out_even), - .width = 4, - .clkr.hw.init = &(struct clk_init_data){ - .name = "npu_cc_pll0_out_even", - .parent_names = (const char *[]){ "npu_cc_pll0" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_generic_pll_postdiv_ops, - }, -}; - -static const struct alpha_pll_config npu_cc_pll1_config = { - .l = 0xF, - .frac = 0xA000, - .config_ctl_val = 0x20485699, - .config_ctl_hi_val = 0x00002067, - .user_ctl_val = 0x00000001, - .user_ctl_hi_val = 0x00004805, -}; - -static struct clk_alpha_pll npu_cc_pll1 = { - .offset = 0x400, - .vco_table = fabia_vco, - .num_vco = ARRAY_SIZE(fabia_vco), - .type = FABIA_PLL, - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "npu_cc_pll1", - .parent_names = (const char *[]){ "bi_tcxo" }, - .num_parents = 1, - .ops = &clk_fabia_pll_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_MIN] = 615000000, - [VDD_LOW] = 1066000000, - [VDD_LOW_L1] = 1600000000, - [VDD_NOMINAL] = 2000000000}, - }, - }, -}; - -static const struct clk_div_table post_div_table_npu_cc_pll1_out_even[] = { - { 0x0, 1 }, - { } -}; - -static struct clk_alpha_pll_postdiv npu_cc_pll1_out_even = { - .offset = 0x400, - .post_div_shift = 8, - .post_div_table = post_div_table_npu_cc_pll1_out_even, - .num_post_div = ARRAY_SIZE(post_div_table_npu_cc_pll1_out_even), - .width = 4, - .clkr.hw.init = &(struct clk_init_data){ - .name = "npu_cc_pll1_out_even", - .parent_names = (const char *[]){ "npu_cc_pll1" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_generic_pll_postdiv_ops, - }, -}; - -static const struct alpha_pll_config npu_q6ss_pll_config = { - .l = 0xD, - .frac = 0x555, - .config_ctl_val = 0x20485699, - .config_ctl_hi_val = 0x00002067, - .user_ctl_val = 0x00000001, - .user_ctl_hi_val = 0x00004805, -}; - -static struct clk_alpha_pll npu_q6ss_pll = { - .offset = 0x0, - .vco_table = fabia_vco, - .num_vco = ARRAY_SIZE(fabia_vco), - .type = FABIA_PLL, - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "npu_q6ss_pll", - .parent_names = (const char *[]){ "bi_tcxo" }, - .num_parents = 1, - .ops = &clk_fabia_pll_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_MIN] = 615000000, - [VDD_LOW] = 1066000000, - [VDD_LOW_L1] = 1600000000, - [VDD_NOMINAL] = 2000000000}, - }, - }, -}; - -static struct clk_fixed_factor npu_cc_crc_div = { - .mult = 1, - .div = 2, - .hw.init = &(struct clk_init_data){ - .name = "npu_cc_crc_div", - .parent_names = (const char *[]){ "npu_cc_pll0_out_even" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_fixed_factor_ops, - }, -}; - -static const struct freq_tbl ftbl_npu_cc_cal_hm0_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(100000000, P_NPU_CC_CRC_DIV, 1, 0, 0), - F(200000000, P_NPU_CC_CRC_DIV, 1, 0, 0), - F(400000000, P_NPU_CC_CRC_DIV, 1, 0, 0), - F(515000000, P_NPU_CC_CRC_DIV, 1, 0, 0), - F(650000000, P_NPU_CC_CRC_DIV, 1, 0, 0), - F(800000000, P_NPU_CC_CRC_DIV, 1, 0, 0), - { } -}; - -static struct clk_rcg2 npu_cc_cal_hm0_clk_src = { - .cmd_rcgr = 0x1100, - .mnd_width = 0, - .hid_width = 5, - .parent_map = npu_cc_parent_map_0_crc, - .freq_tbl = ftbl_npu_cc_cal_hm0_clk_src, - .enable_safe_config = true, - .clkr.hw.init = &(struct clk_init_data){ - .name = "npu_cc_cal_hm0_clk_src", - .parent_names = npu_cc_parent_names_0_crc, - .num_parents = 6, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_MIN] = 100000000, - [VDD_LOWER] = 200000000, - [VDD_LOW] = 400000000, - [VDD_LOW_L1] = 515000000, - [VDD_NOMINAL] = 650000000, - [VDD_HIGH] = 800000000}, - }, -}; - -static const struct freq_tbl ftbl_npu_cc_core_clk_src[] = { - F(60000000, P_GCC_NPU_GPLL0_DIV_CLK, 5, 0, 0), - F(100000000, P_GCC_NPU_GPLL0_DIV_CLK, 3, 0, 0), - F(200000000, P_GCC_NPU_GPLL0_CLK, 3, 0, 0), - F(333333333, P_NPU_CC_PLL1_OUT_EVEN, 4.5, 0, 0), - F(428571429, P_NPU_CC_PLL1_OUT_EVEN, 3.5, 0, 0), - F(500000000, P_NPU_CC_PLL1_OUT_EVEN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 npu_cc_core_clk_src = { - .cmd_rcgr = 0x1010, - .mnd_width = 0, - .hid_width = 5, - .parent_map = npu_cc_parent_map_0, - .freq_tbl = ftbl_npu_cc_core_clk_src, - .enable_safe_config = true, - .clkr.hw.init = &(struct clk_init_data){ - .name = "npu_cc_core_clk_src", - .parent_names = npu_cc_parent_names_0, - .num_parents = 6, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_MIN] = 60000000, - [VDD_LOWER] = 100000000, - [VDD_LOW] = 200000000, - [VDD_LOW_L1] = 333333333, - [VDD_NOMINAL] = 428571429, - [VDD_HIGH] = 500000000}, - }, -}; - -static const struct freq_tbl ftbl_npu_dsp_core_clk_src[] = { - F(250000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0), - F(300000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0), - F(400000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0), - F(500000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0), - F(660000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0), - F(800000000, P_NPU_Q6SS_PLL_OUT_MAIN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 npu_dsp_core_clk_src = { - .cmd_rcgr = 0x28, - .mnd_width = 0, - .hid_width = 5, - .parent_map = npu_cc_parent_map_2, - .freq_tbl = ftbl_npu_dsp_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "npu_dsp_core_clk_src", - .parent_names = npu_cc_parent_names_2, - .num_parents = 3, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_MIN] = 250000000, - [VDD_LOWER] = 300000000, - [VDD_LOW] = 400000000, - [VDD_LOW_L1] = 500000000, - [VDD_NOMINAL] = 660000000, - [VDD_HIGH] = 800000000}, - }, -}; - -static struct clk_branch npu_cc_atb_clk = { - .halt_reg = 0x10d0, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10d0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "npu_cc_atb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch npu_cc_bto_core_clk = { - .halt_reg = 0x10dc, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10dc, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "npu_cc_bto_core_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch npu_cc_bwmon_clk = { - .halt_reg = 0x10d8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10d8, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "npu_cc_bwmon_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch npu_cc_cal_hm0_cdc_clk = { - .halt_reg = 0x1098, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1098, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "npu_cc_cal_hm0_cdc_clk", - .parent_names = (const char *[]){ - "npu_cc_cal_hm0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch npu_cc_cal_hm0_clk = { - .halt_reg = 0x1110, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1110, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "npu_cc_cal_hm0_clk", - .parent_names = (const char *[]){ - "npu_cc_cal_hm0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch npu_cc_cal_hm0_perf_cnt_clk = { - .halt_reg = 0x10a0, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10a0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "npu_cc_cal_hm0_perf_cnt_clk", - .parent_names = (const char *[]){ - "npu_cc_cal_hm0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch npu_cc_core_clk = { - .halt_reg = 0x1030, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1030, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "npu_cc_core_clk", - .parent_names = (const char *[]){ - "npu_cc_core_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch npu_cc_dsp_ahbm_clk = { - .halt_reg = 0x1214, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1214, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "npu_cc_dsp_ahbm_clk", - .parent_names = (const char *[]){ - "npu_cc_core_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch npu_cc_dsp_ahbs_clk = { - .halt_reg = 0x1210, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x1210, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "npu_cc_dsp_ahbs_clk", - .parent_names = (const char *[]){ - "npu_cc_core_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch npu_cc_dsp_axi_clk = { - .halt_reg = 0x121c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x121c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "npu_cc_dsp_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch npu_cc_noc_ahb_clk = { - .halt_reg = 0x10c0, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10c0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "npu_cc_noc_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch npu_cc_noc_axi_clk = { - .halt_reg = 0x10b8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10b8, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "npu_cc_noc_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch npu_cc_noc_dma_clk = { - .halt_reg = 0x10b0, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10b0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "npu_cc_noc_dma_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch npu_cc_rsc_xo_clk = { - .halt_reg = 0x10e0, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10e0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "npu_cc_rsc_xo_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch npu_cc_s2p_clk = { - .halt_reg = 0x10cc, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x10cc, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "npu_cc_s2p_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch npu_cc_xo_clk = { - .halt_reg = 0x1410, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1410, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "npu_cc_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_regmap *npu_cc_atoll_clocks[] = { - [NPU_CC_ATB_CLK] = &npu_cc_atb_clk.clkr, - [NPU_CC_BTO_CORE_CLK] = &npu_cc_bto_core_clk.clkr, - [NPU_CC_BWMON_CLK] = &npu_cc_bwmon_clk.clkr, - [NPU_CC_CAL_HM0_CDC_CLK] = &npu_cc_cal_hm0_cdc_clk.clkr, - [NPU_CC_CAL_HM0_CLK] = &npu_cc_cal_hm0_clk.clkr, - [NPU_CC_CAL_HM0_CLK_SRC] = &npu_cc_cal_hm0_clk_src.clkr, - [NPU_CC_CAL_HM0_PERF_CNT_CLK] = &npu_cc_cal_hm0_perf_cnt_clk.clkr, - [NPU_CC_CORE_CLK] = &npu_cc_core_clk.clkr, - [NPU_CC_CORE_CLK_SRC] = &npu_cc_core_clk_src.clkr, - [NPU_CC_DSP_AHBM_CLK] = &npu_cc_dsp_ahbm_clk.clkr, - [NPU_CC_DSP_AHBS_CLK] = &npu_cc_dsp_ahbs_clk.clkr, - [NPU_CC_DSP_AXI_CLK] = &npu_cc_dsp_axi_clk.clkr, - [NPU_CC_NOC_AHB_CLK] = &npu_cc_noc_ahb_clk.clkr, - [NPU_CC_NOC_AXI_CLK] = &npu_cc_noc_axi_clk.clkr, - [NPU_CC_NOC_DMA_CLK] = &npu_cc_noc_dma_clk.clkr, - [NPU_CC_PLL0] = &npu_cc_pll0.clkr, - [NPU_CC_PLL0_OUT_EVEN] = &npu_cc_pll0_out_even.clkr, - [NPU_CC_PLL1] = &npu_cc_pll1.clkr, - [NPU_CC_PLL1_OUT_EVEN] = &npu_cc_pll1_out_even.clkr, - [NPU_CC_RSC_XO_CLK] = &npu_cc_rsc_xo_clk.clkr, - [NPU_CC_S2P_CLK] = &npu_cc_s2p_clk.clkr, - [NPU_CC_XO_CLK] = &npu_cc_xo_clk.clkr, -}; - -static struct clk_regmap *npu_qdsp6ss_atoll_clocks[] = { - [NPU_DSP_CORE_CLK_SRC] = &npu_dsp_core_clk_src.clkr, -}; - -static struct clk_regmap *npu_qdsp6ss_pll_atoll_clocks[] = { - [NPU_Q6SS_PLL] = &npu_q6ss_pll.clkr, -}; - -static const struct qcom_reset_map npu_cc_atoll_resets[] = { - [NPU_CC_CORE_BCR] = { 0x1000 }, - [NPU_CC_CAL_HM0_BCR] = { 0x10f0 }, - [NPU_CC_DSP_BCR] = { 0x1200 }, -}; - -static const struct regmap_config npu_cc_atoll_regmap_config = { - .name = "cc", - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0xa060, - .fast_io = true, -}; - -static const struct regmap_config npu_qdsp6ss_atoll_regmap_config = { - .name = "qdsp6ss", - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0x203c, - .fast_io = true, -}; - -static const struct regmap_config npu_qdsp6ss_pll_atoll_regmap_config = { - .name = "qdsp6ss_pll", - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0x50, - .fast_io = true, -}; - -static const struct qcom_cc_desc npu_cc_atoll_desc = { - .config = &npu_cc_atoll_regmap_config, - .clks = npu_cc_atoll_clocks, - .num_clks = ARRAY_SIZE(npu_cc_atoll_clocks), - .resets = npu_cc_atoll_resets, - .num_resets = ARRAY_SIZE(npu_cc_atoll_resets), -}; - -static const struct qcom_cc_desc npu_qdsp6ss_atoll_desc = { - .config = &npu_qdsp6ss_atoll_regmap_config, - .clks = npu_qdsp6ss_atoll_clocks, - .num_clks = ARRAY_SIZE(npu_qdsp6ss_atoll_clocks), -}; - -static const struct qcom_cc_desc npu_qdsp6ss_pll_atoll_desc = { - .config = &npu_qdsp6ss_pll_atoll_regmap_config, - .clks = npu_qdsp6ss_pll_atoll_clocks, - .num_clks = ARRAY_SIZE(npu_qdsp6ss_pll_atoll_clocks), -}; - -static const struct of_device_id npu_cc_atoll_match_table[] = { - { .compatible = "qcom,atoll-npucc" }, - { } -}; -MODULE_DEVICE_TABLE(of, npu_cc_atoll_match_table); - -static int enable_npu_crc(struct regmap *regmap, struct regulator *npu_gdsc) -{ - int ret; - - /* Set npu_cc_cal_hm0_clk to the lowest supported frequency */ - clk_set_rate(npu_cc_cal_hm0_clk.clkr.hw.clk, - clk_round_rate(npu_cc_cal_hm0_clk_src.clkr.hw.clk, 1)); - - /* Turn on the NPU GDSC */ - ret = regulator_enable(npu_gdsc); - if (ret) { - pr_err("Failed to enable the NPU GDSC during CRC sequence\n"); - return ret; - } - - /* Enable npu_cc_cal_hm0_clk */ - ret = clk_prepare_enable(npu_cc_cal_hm0_clk.clkr.hw.clk); - if (ret) { - pr_err("Failed to enable npu_cc_cal_hm0_clk during CRC sequence\n"); - regulator_disable(npu_gdsc); - return ret; - } - - /* Enable MND RC */ - regmap_write(regmap, CRC_MND_CFG, CRC_MND_CFG_SETTING); - regmap_write(regmap, CRC_SID_FSM_CTRL, CRC_SID_FSM_CTRL_SETTING); - - /* Wait for 16 cycles before continuing */ - udelay(1); - - /* Disable npu_cc_cal_hm0_clk */ - clk_disable_unprepare(npu_cc_cal_hm0_clk.clkr.hw.clk); - - /* Turn off the NPU GDSC */ - regulator_disable(npu_gdsc); - - return 0; -} - -static int npu_clocks_atoll_probe(struct platform_device *pdev, - const struct qcom_cc_desc *desc, - struct regulator *npu_gdsc) -{ - struct regmap *regmap; - struct resource *res; - void __iomem *base; - int ret; - - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, - desc->config->name); - base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(base)) - return PTR_ERR(base); - - regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - - if (!strcmp("cc", desc->config->name)) { - clk_fabia_pll_configure(&npu_cc_pll0, regmap, - &npu_cc_pll0_config); - clk_fabia_pll_configure(&npu_cc_pll1, regmap, - &npu_cc_pll1_config); - /* Register the fixed factor clock for CRC divider */ - ret = devm_clk_hw_register(&pdev->dev, &npu_cc_crc_div.hw); - if (ret) { - dev_err(&pdev->dev, - "Failed to register CRC divider clock, ret=%d\n", ret); - return ret; - } - } else if (!strcmp("qdsp6ss_pll", desc->config->name)) { - clk_fabia_pll_configure(&npu_q6ss_pll, regmap, - &npu_q6ss_pll_config); - } - - ret = qcom_cc_really_probe(pdev, desc, regmap); - if (ret) { - dev_err(&pdev->dev, "Failed to register NPU CC clocks\n"); - return ret; - } - - if (!strcmp("cc", desc->config->name)) { - ret = enable_npu_crc(regmap, npu_gdsc); - if (ret) { - dev_err(&pdev->dev, - "Failed to enable CRC for NPU cal RCG\n"); - return ret; - } - } - - return ret; -} - -static int npu_cc_atoll_probe(struct platform_device *pdev) -{ - int ret; - struct regulator *npu_gdsc; - - vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx"); - if (IS_ERR(vdd_cx.regulator[0])) { - if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER)) - dev_err(&pdev->dev, - "Unable to get vdd_cx regulator\n"); - return PTR_ERR(vdd_cx.regulator[0]); - } - - npu_gdsc = devm_regulator_get(&pdev->dev, "npu_gdsc"); - if (IS_ERR(npu_gdsc)) { - if (!(PTR_ERR(npu_gdsc) == -EPROBE_DEFER)) - dev_err(&pdev->dev, - "Unable to get npu_gdsc regulator\n"); - return PTR_ERR(npu_gdsc); - } - - ret = npu_clocks_atoll_probe(pdev, &npu_cc_atoll_desc, npu_gdsc); - if (ret < 0) { - dev_err(&pdev->dev, - "npu_cc clock registration failed, ret=%d\n", ret); - return ret; - } - - ret = npu_clocks_atoll_probe(pdev, &npu_qdsp6ss_atoll_desc, npu_gdsc); - if (ret < 0) { - dev_err(&pdev->dev, - "npu_qdsp6ss clock registration failed, ret=%d\n", - ret); - return ret; - } - - ret = npu_clocks_atoll_probe(pdev, &npu_qdsp6ss_pll_atoll_desc, - npu_gdsc); - if (ret < 0) { - dev_err(&pdev->dev, - "npu_qdsp6ss_pll clock registration failed, ret=%d\n", - ret); - return ret; - } - - dev_info(&pdev->dev, "Registered NPU CC clocks\n"); - return ret; -} - -static struct platform_driver npu_cc_atoll_driver = { - .probe = npu_cc_atoll_probe, - .driver = { - .name = "atoll-npucc", - .of_match_table = npu_cc_atoll_match_table, - }, -}; - -static int __init npu_cc_atoll_init(void) -{ - return platform_driver_register(&npu_cc_atoll_driver); -} -subsys_initcall(npu_cc_atoll_init); - -static void __exit npu_cc_atoll_exit(void) -{ - platform_driver_unregister(&npu_cc_atoll_driver); -} -module_exit(npu_cc_atoll_exit); - -MODULE_DESCRIPTION("QTI NPU_CC atoll Driver"); -MODULE_LICENSE("GPL v2"); -MODULE_ALIAS("platform:npu_cc-atoll"); diff --git a/drivers/clk/qcom/scc-sm8150.c b/drivers/clk/qcom/scc-sm8150.c index 554d5590eaba..9cf33169f268 100644 --- a/drivers/clk/qcom/scc-sm8150.c +++ b/drivers/clk/qcom/scc-sm8150.c @@ -576,19 +576,10 @@ static const struct qcom_cc_desc scc_sm8150_desc = { static const struct of_device_id scc_sm8150_match_table[] = { { .compatible = "qcom,scc-sm8150" }, { .compatible = "qcom,scc-sm8150-v2" }, - { .compatible = "qcom,scc-sa8195" }, { } }; MODULE_DEVICE_TABLE(of, scc_sm8150_match_table); -static void scc_sa8195_fixup(struct platform_device *pdev) -{ - if (of_device_is_compatible(pdev->dev.of_node, "qcom,scc-sa8195")) { - vdd_scc_cx.num_levels = VDD_MM_NUM; - vdd_scc_cx.cur_level = VDD_MM_NUM; - } -} - static void scc_sm8150_fixup_sm8150v2(struct regmap *regmap) { scc_pll.config = &scc_pll_config_sm8150_v2; @@ -644,8 +635,7 @@ static int scc_sm8150_fixup(struct platform_device *pdev, struct regmap *regmap) if (!compat || (compatlen <= 0)) return -EINVAL; - if (!strcmp(compat, "qcom,scc-sm8150-v2") || - !strcmp(compat, "qcom,scc-sa8195")) + if (!strcmp(compat, "qcom,scc-sm8150-v2")) scc_sm8150_fixup_sm8150v2(regmap); return 0; @@ -662,8 +652,6 @@ static int scc_sm8150_probe(struct platform_device *pdev) return PTR_ERR(regmap); } - scc_sa8195_fixup(pdev); - vdd_scc_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_scc_cx"); if (IS_ERR(vdd_scc_cx.regulator[0])) { ret = PTR_ERR(vdd_scc_cx.regulator[0]); diff --git a/drivers/clk/qcom/videocc-atoll.c b/drivers/clk/qcom/videocc-atoll.c deleted file mode 100644 index 44a5d8245d29..000000000000 --- a/drivers/clk/qcom/videocc-atoll.c +++ /dev/null @@ -1,326 +0,0 @@ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define pr_fmt(fmt) "clk: %s: " fmt, __func__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "common.h" -#include "clk-regmap.h" -#include "clk-rcg.h" -#include "clk-branch.h" -#include "clk-alpha-pll.h" -#include "vdd-level-sdmmagpie.h" - -#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } - -static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner); - -enum { - P_BI_TCXO, - P_CHIP_SLEEP_CLK, - P_CORE_BI_PLL_TEST_SE, - P_VIDEO_PLL0_OUT_EVEN, - P_VIDEO_PLL0_OUT_MAIN, - P_VIDEO_PLL0_OUT_ODD, -}; - -static const struct parent_map video_cc_parent_map_0[] = { - { P_CHIP_SLEEP_CLK, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const video_cc_parent_names_0[] = { - "chip_sleep_clk", - "core_bi_pll_test_se", -}; - -static const struct parent_map video_cc_parent_map_1[] = { - { P_BI_TCXO, 0 }, - { P_VIDEO_PLL0_OUT_MAIN, 1 }, - { P_VIDEO_PLL0_OUT_EVEN, 2 }, - { P_VIDEO_PLL0_OUT_ODD, 3 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const video_cc_parent_names_1[] = { - "bi_tcxo", - "video_pll0", - "video_pll0_out_even", - "video_pll0_out_odd", - "core_bi_pll_test_se", -}; - -static const struct parent_map video_cc_parent_map_2[] = { - { P_BI_TCXO, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const video_cc_parent_names_2[] = { - "bi_tcxo", - "core_bi_pll_test_se", -}; - -static struct pll_vco fabia_vco[] = { - { 249600000, 2000000000, 0 }, - { 125000000, 1000000000, 1 }, -}; - -static struct alpha_pll_config video_pll0_config = { - .l = 0x1F, - .frac = 0x4000, - .user_ctl_val = 0x00000001, - .user_ctl_hi_val = 0x00004805, -}; - -static struct clk_alpha_pll video_pll0 = { - .offset = 0x42c, - .vco_table = fabia_vco, - .num_vco = ARRAY_SIZE(fabia_vco), - .type = FABIA_PLL, - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "video_pll0", - .parent_names = (const char *[]){ "bi_tcxo" }, - .num_parents = 1, - .ops = &clk_fabia_pll_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_MIN] = 615000000, - [VDD_LOW] = 1066000000, - [VDD_LOW_L1] = 1600000000, - [VDD_NOMINAL] = 2000000000}, - }, - }, -}; - -static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(150000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0), - F(270000000, P_VIDEO_PLL0_OUT_MAIN, 2.5, 0, 0), - F(340000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), - F(434000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), - F(500000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 video_cc_venus_clk_src = { - .cmd_rcgr = 0x7f0, - .mnd_width = 0, - .hid_width = 5, - .parent_map = video_cc_parent_map_1, - .freq_tbl = ftbl_video_cc_venus_clk_src, - .enable_safe_config = true, - .clkr.hw.init = &(struct clk_init_data){ - .name = "video_cc_venus_clk_src", - .parent_names = video_cc_parent_names_1, - .num_parents = 5, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, - .vdd_class = &vdd_cx, - .num_rate_max = VDD_NUM, - .rate_max = (unsigned long[VDD_NUM]) { - [VDD_LOWER] = 150000000, - [VDD_LOW] = 270000000, - [VDD_LOW_L1] = 340000000, - [VDD_NOMINAL] = 434000000, - [VDD_HIGH] = 500000000}, - }, -}; - -static struct clk_branch video_cc_vcodec0_axi_clk = { - .halt_reg = 0x9ec, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x9ec, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "video_cc_vcodec0_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch video_cc_vcodec0_core_clk = { - .halt_reg = 0x890, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x890, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "video_cc_vcodec0_core_clk", - .parent_names = (const char *[]){ - "video_cc_venus_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch video_cc_venus_ahb_clk = { - .halt_reg = 0xa4c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xa4c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "video_cc_venus_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch video_cc_venus_ctl_axi_clk = { - .halt_reg = 0x9cc, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x9cc, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "video_cc_venus_ctl_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch video_cc_venus_ctl_core_clk = { - .halt_reg = 0x850, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x850, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "video_cc_venus_ctl_core_clk", - .parent_names = (const char *[]){ - "video_cc_venus_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch video_cc_xo_clk = { - .halt_reg = 0x984, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x984, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "video_cc_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_regmap *video_cc_atoll_clocks[] = { - [VIDEO_CC_VCODEC0_AXI_CLK] = &video_cc_vcodec0_axi_clk.clkr, - [VIDEO_CC_VCODEC0_CORE_CLK] = &video_cc_vcodec0_core_clk.clkr, - [VIDEO_CC_VENUS_AHB_CLK] = &video_cc_venus_ahb_clk.clkr, - [VIDEO_CC_VENUS_CLK_SRC] = &video_cc_venus_clk_src.clkr, - [VIDEO_CC_VENUS_CTL_AXI_CLK] = &video_cc_venus_ctl_axi_clk.clkr, - [VIDEO_CC_VENUS_CTL_CORE_CLK] = &video_cc_venus_ctl_core_clk.clkr, - [VIDEO_CC_XO_CLK] = &video_cc_xo_clk.clkr, - [VIDEO_PLL0] = &video_pll0.clkr, -}; - -static const struct regmap_config video_cc_atoll_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0xb94, - .fast_io = true, -}; - -static const struct qcom_cc_desc video_cc_atoll_desc = { - .config = &video_cc_atoll_regmap_config, - .clks = video_cc_atoll_clocks, - .num_clks = ARRAY_SIZE(video_cc_atoll_clocks), -}; - -static const struct of_device_id video_cc_atoll_match_table[] = { - { .compatible = "qcom,atoll-videocc" }, - { } -}; -MODULE_DEVICE_TABLE(of, video_cc_atoll_match_table); - -static int video_cc_atoll_probe(struct platform_device *pdev) -{ - struct regmap *regmap; - int ret; - - vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx"); - if (IS_ERR(vdd_cx.regulator[0])) { - if (PTR_ERR(vdd_cx.regulator[0]) != -EPROBE_DEFER) - dev_err(&pdev->dev, - "Unable to get vdd_cx regulator\n"); - return PTR_ERR(vdd_cx.regulator[0]); - } - - regmap = qcom_cc_map(pdev, &video_cc_atoll_desc); - if (IS_ERR(regmap)) { - pr_err("Failed to map the video_cc registers\n"); - return PTR_ERR(regmap); - } - - clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config); - - ret = qcom_cc_really_probe(pdev, &video_cc_atoll_desc, regmap); - if (ret) { - dev_err(&pdev->dev, "Failed to register Video CC clocks\n"); - return ret; - } - - dev_info(&pdev->dev, "Registered Video CC clocks\n"); - return ret; -} - -static struct platform_driver video_cc_atoll_driver = { - .probe = video_cc_atoll_probe, - .driver = { - .name = "atoll-videocc", - .of_match_table = video_cc_atoll_match_table, - }, -}; - -static int __init video_cc_atoll_init(void) -{ - return platform_driver_register(&video_cc_atoll_driver); -} -subsys_initcall(video_cc_atoll_init); - -static void __exit video_cc_atoll_exit(void) -{ - platform_driver_unregister(&video_cc_atoll_driver); -} -module_exit(video_cc_atoll_exit); - -MODULE_DESCRIPTION("QTI VIDEO_CC atoll Driver"); -MODULE_LICENSE("GPL v2"); -MODULE_ALIAS("platform:video_cc-atoll"); diff --git a/drivers/clk/qcom/virtio_clk.c b/drivers/clk/qcom/virtio_clk.c index 3630755e5bcb..ea1c6fc1835b 100644 --- a/drivers/clk/qcom/virtio_clk.c +++ b/drivers/clk/qcom/virtio_clk.c @@ -718,7 +718,7 @@ static void __exit virtio_clk_fini(void) { unregister_virtio_driver(&virtio_clk_driver); } -subsys_initcall_sync(virtio_clk_init); +subsys_initcall(virtio_clk_init); module_exit(virtio_clk_fini); MODULE_DEVICE_TABLE(virtio, id_table); diff --git a/drivers/clk/qcom/virtio_clk_sa8195p.c b/drivers/clk/qcom/virtio_clk_sa8195p.c index 90c07bf8f7ca..2be46624a73d 100644 --- a/drivers/clk/qcom/virtio_clk_sa8195p.c +++ b/drivers/clk/qcom/virtio_clk_sa8195p.c @@ -45,26 +45,11 @@ static const char * const sa8195p_gcc_virtio_clocks[] = { [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = "gcc_cfg_noc_usb3_prim_axi_clk", [GCC_AGGRE_USB3_PRIM_AXI_CLK] = "gcc_aggre_usb3_prim_axi_clk", [GCC_USB30_PRIM_MOCK_UTMI_CLK] = "gcc_usb30_prim_mock_utmi_clk", - [GCC_USB30_PRIM_SLEEP_CLK] = "gcc_usb30_prim_sleep_clk", - [GCC_USB3_PRIM_PHY_AUX_CLK] = "gcc_usb3_prim_phy_aux_clk", - [GCC_USB3_PRIM_PHY_PIPE_CLK] = "gcc_usb3_prim_phy_pipe_clk", - [GCC_USB3_PRIM_CLKREF_CLK] = "gcc_usb3_prim_clkref_en", - [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = "gcc_usb3_prim_phy_com_aux_clk", - [GCC_USB30_SEC_MASTER_CLK] = "gcc_usb30_sec_master_clk", - [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = "gcc_cfg_noc_usb3_sec_axi_clk", - [GCC_AGGRE_USB3_SEC_AXI_CLK] = "gcc_aggre_usb3_sec_axi_clk", - [GCC_USB30_SEC_MOCK_UTMI_CLK] = "gcc_usb30_sec_mock_utmi_clk", - [GCC_USB30_SEC_SLEEP_CLK] = "gcc_usb30_sec_sleep_clk", - [GCC_USB3_SEC_PHY_AUX_CLK] = "gcc_usb3_sec_phy_aux_clk", - [GCC_USB3_SEC_PHY_PIPE_CLK] = "gcc_usb3_sec_phy_pipe_clk", - [GCC_USB3_SEC_CLKREF_CLK] = "gcc_usb3_sec_clkref_en", - [GCC_USB3_SEC_PHY_COM_AUX_CLK] = "gcc_usb3_sec_phy_com_aux_clk", [GCC_PCIE_0_PIPE_CLK] = "gcc_pcie_0_pipe_clk", [GCC_PCIE_0_AUX_CLK] = "gcc_pcie_0_aux_clk", [GCC_PCIE_0_CFG_AHB_CLK] = "gcc_pcie_0_cfg_ahb_clk", [GCC_PCIE_0_MSTR_AXI_CLK] = "gcc_pcie_0_mstr_axi_clk", [GCC_PCIE_0_SLV_AXI_CLK] = "gcc_pcie_0_slv_axi_clk", - [GCC_PCIE_0_CLKREF_CLK] = "gcc_pcie_0_clkref_en", [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = "gcc_pcie_0_slv_q2a_axi_clk", [GCC_AGGRE_NOC_PCIE_TBU_CLK] = "gcc_aggre_noc_pcie_tbu_clk", [GCC_PCIE0_PHY_REFGEN_CLK] = "gcc_pcie0_phy_refgen_clk", @@ -75,9 +60,7 @@ static const char * const sa8195p_gcc_virtio_clocks[] = { static const char * const sa8195p_gcc_virtio_resets[] = { [GCC_QUSB2PHY_PRIM_BCR] = "gcc_qusb2phy_prim_bcr", - [GCC_QUSB2PHY_SEC_BCR] = "gcc_qusb2phy_sec_bcr", [GCC_USB30_PRIM_BCR] = "gcc_usb30_prim_master_clk", - [GCC_USB30_SEC_BCR] = "gcc_usb30_sec_master_clk", [GCC_PCIE_0_BCR] = "gcc_pcie_0_mstr_axi_clk", [GCC_PCIE_0_PHY_BCR] = "gcc_pcie_0_phy_bcr", }; diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 9e653f0bfa6c..dd9614496f53 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -301,13 +301,6 @@ static u64 notrace arm64_858921_read_cntvct_el0(void) } #endif -#ifdef CONFIG_ARM64_ERRATUM_1188873 -static u64 notrace arm64_1188873_read_cntvct_el0(void) -{ - return read_sysreg(cntvct_el0); -} -#endif - #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround); @@ -391,14 +384,6 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { .read_cntvct_el0 = arm64_858921_read_cntvct_el0, }, #endif -#ifdef CONFIG_ARM64_ERRATUM_1188873 - { - .match_type = ate_match_local_cap_id, - .id = (void *)ARM64_WORKAROUND_1188873, - .desc = "ARM erratum 1188873", - .read_cntvct_el0 = arm64_1188873_read_cntvct_el0, - }, -#endif }; typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *, diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index 4c57bff0fe95..a8e9fb2c1e20 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -33,7 +33,10 @@ #include #include +#include #include +#define GOLD_CPU_NUMBER 4 +#define GOLD_PLUS_CPU_NUMBER 7 static LIST_HEAD(cpufreq_policy_list); @@ -60,6 +63,29 @@ static LIST_HEAD(cpufreq_governor_list); #define for_each_governor(__governor) \ list_for_each_entry(__governor, &cpufreq_governor_list, governor_list) +struct qos_request_value { + bool flag; + unsigned int max_cpufreq; + unsigned int min_cpufreq; +}; +static struct qos_request_value c0_qos_request_value = { + .flag = false, + .max_cpufreq = INT_MAX, + .min_cpufreq = MIN_CPUFREQ, +}; +static struct qos_request_value c1_qos_request_value = { + .flag = false, + .max_cpufreq = INT_MAX, + .min_cpufreq = MIN_CPUFREQ, +}; +static struct qos_request_value c2_qos_request_value = { + .flag = false, + .max_cpufreq = INT_MAX, + .min_cpufreq = MIN_CPUFREQ, +}; +unsigned int cluster1_first_cpu = GOLD_CPU_NUMBER; +unsigned int cluster2_first_cpu = GOLD_PLUS_CPU_NUMBER; + /** * The "cpufreq driver" - the arch- or hardware-dependent low * level driver of CPUFreq support, and its spinlock. This lock @@ -342,8 +368,11 @@ static void __cpufreq_notify_transition(struct cpufreq_policy *policy, pr_debug("FREQ: %lu - CPU: %lu\n", (unsigned long)freqs->new, (unsigned long)freqs->cpu); trace_cpu_frequency(freqs->new, freqs->cpu); - cpufreq_stats_record_transition(policy, freqs->new); + + if (freqs->new != policy->cur) + cpufreq_stats_record_transition(policy, freqs->new); cpufreq_times_record_transition(policy, freqs->new); + srcu_notifier_call_chain(&cpufreq_transition_notifier_list, CPUFREQ_POSTCHANGE, freqs); if (likely(policy) && likely(policy->cpu == freqs->cpu)) @@ -1145,6 +1174,10 @@ static struct cpufreq_policy *cpufreq_policy_alloc(unsigned int cpu) INIT_LIST_HEAD(&policy->policy_list); init_rwsem(&policy->rwsem); spin_lock_init(&policy->transition_lock); +// tedlin@ASTI 2019/06/12 add for CONFIG_CONTROL_CENTER +#ifdef CONFIG_CONTROL_CENTER + spin_lock_init(&policy->cc_lock); +#endif init_waitqueue_head(&policy->transition_wait); init_completion(&policy->kobj_unregister); INIT_WORK(&policy->update, handle_update); @@ -1271,6 +1304,13 @@ static int cpufreq_online(unsigned int cpu) } else { policy->min = policy->user_policy.min; policy->max = policy->user_policy.max; +// tedlin@ASTI 2019/06/12 add for CONFIG_CONTROL_CENTER +#ifdef CONFIG_CONTROL_CENTER + spin_lock(&policy->cc_lock); + policy->cc_min = policy->min; + policy->cc_max = policy->max; + spin_unlock(&policy->cc_lock); +#endif } if (cpufreq_driver->get && !cpufreq_driver->setpolicy) { @@ -1891,8 +1931,22 @@ EXPORT_SYMBOL(cpufreq_unregister_notifier); unsigned int cpufreq_driver_fast_switch(struct cpufreq_policy *policy, unsigned int target_freq) { + struct qos_request_value *qos; int ret; + +#ifdef CONFIG_CONTROL_CENTER + if (likely(policy->cc_enable)) + target_freq = clamp_val(target_freq, policy->cc_min, policy->cc_max); +#endif target_freq = clamp_val(target_freq, policy->min, policy->max); + if (policy->cpu >= cluster2_first_cpu) + qos = &c2_qos_request_value; + else { + qos = policy->cpu >= cluster1_first_cpu ? + &c1_qos_request_value : &c0_qos_request_value; + } + target_freq = clamp_val(target_freq, qos->min_cpufreq, + qos->max_cpufreq); ret = cpufreq_driver->fast_switch(policy, target_freq); if (ret) @@ -1995,6 +2049,10 @@ int __cpufreq_driver_target(struct cpufreq_policy *policy, if (cpufreq_disabled()) return -ENODEV; +#ifdef CONFIG_CONTROL_CENTER + if (likely(policy->cc_enable)) + target_freq = clamp_val(target_freq, policy->cc_min, policy->cc_max); +#endif /* Make sure that target_freq is within supported range */ target_freq = clamp_val(target_freq, policy->min, policy->max); @@ -2273,6 +2331,14 @@ static int cpufreq_set_policy(struct cpufreq_policy *policy, policy->min = new_policy->min; policy->max = new_policy->max; +// tedlin@ASTI 2019/06/12 add for CONFIG_CONTROL_CENTER +#ifdef CONFIG_CONTROL_CENTER + spin_lock(&policy->cc_lock); + policy->cc_min = policy->min; + policy->cc_max = policy->max; + spin_unlock(&policy->cc_lock); +#endif + arch_set_max_freq_scale(policy->cpus, policy->max); trace_cpu_frequency_limits(policy->max, policy->min, policy->cpu); @@ -2657,3 +2723,285 @@ static int __init cpufreq_core_init(void) } module_param(off, int, 0444); core_initcall(cpufreq_core_init); + +static int get_c0_available_cpufreq(struct cpufreq_policy *policy) +{ + int max_cpufreq_index = -1, min_cpufreq_index = -1; + int max_index = -1; + int index_max = 0, index_min = 0; + struct cpufreq_frequency_table *table, *pos; + + table = policy->freq_table; + if (!table) { + pr_err("cpufreq:Failed to get frequency table for CPU%u\n", 0); + return -EINVAL; + } + + max_cpufreq_index = (unsigned int)pm_qos_request(PM_QOS_C0_CPUFREQ_MAX); + min_cpufreq_index = (unsigned int)pm_qos_request(PM_QOS_C0_CPUFREQ_MIN); + + /* you can limit the min cpufreq*/ + if (min_cpufreq_index > max_cpufreq_index) + max_cpufreq_index = min_cpufreq_index; + + /* get the available cpufreq + * lock for the max available cpufreq + */ + cpufreq_for_each_valid_entry(pos, table) { + max_index = pos - table; + } + if (max_cpufreq_index & MASK_CPUFREQ) { + index_max = MAX_CPUFREQ - max_cpufreq_index; + if (index_max > max_index) + index_max = 0; + index_max = max_index - index_max; + } else { + if (max_cpufreq_index > max_index) + index_max = max_index; + } + if (min_cpufreq_index & MASK_CPUFREQ) { + index_min = MAX_CPUFREQ - min_cpufreq_index; + if (index_min > max_index) + index_min = 0; + index_min = max_index - index_min; + } else { + if (min_cpufreq_index > max_index) + index_min = max_index; + } + c0_qos_request_value.max_cpufreq = table[index_max].frequency; + c0_qos_request_value.min_cpufreq = table[index_min].frequency; + pr_debug("c0::: m:%d, ii:%d-, mm:%d-", max_index, index_min, index_max); + + return 0; +} + +static int get_c1_available_cpufreq(struct cpufreq_policy *policy) +{ + int max_cpufreq_index = -1, min_cpufreq_index = -1; + int max_index = -1; + int index_max = 0, index_min = 0; + struct cpufreq_frequency_table *table, *pos; + + table = policy->freq_table; + if (!table) { + pr_err("cpufreq: Failed to get frequency table for CPU\n"); + return -EINVAL; + } + + max_cpufreq_index = (unsigned int)pm_qos_request(PM_QOS_C1_CPUFREQ_MAX); + min_cpufreq_index = (unsigned int)pm_qos_request(PM_QOS_C1_CPUFREQ_MIN); + + /* you can limit the min cpufreq*/ + if (min_cpufreq_index > max_cpufreq_index) + max_cpufreq_index = min_cpufreq_index; + + /* get the available cpufreq + * lock for the max available cpufreq + */ + cpufreq_for_each_valid_entry(pos, table) { + max_index = pos - table; + } + + /* add limits */ + if (max_cpufreq_index & MASK_CPUFREQ) { + index_max = MAX_CPUFREQ - max_cpufreq_index; + if (index_max > max_index) + index_max = 0; + index_max = max_index - index_max; + } else { + if (max_cpufreq_index > max_index) + index_max = max_index; + } + if (min_cpufreq_index & MASK_CPUFREQ) { + index_min = MAX_CPUFREQ - min_cpufreq_index; + if (index_min > max_index) + index_min = 0; + index_min = max_index - index_min; + } else { + if (min_cpufreq_index > max_index) + index_min = max_index; + } + c1_qos_request_value.max_cpufreq = table[index_max].frequency; + c1_qos_request_value.min_cpufreq = table[index_min].frequency; + pr_debug("c1::: m:%d, ii:%d-, mm:%d-", max_index, index_min, index_max); + + return 0; +} + +static int get_c2_available_cpufreq(struct cpufreq_policy *policy) +{ + int max_cpufreq_index = -1, min_cpufreq_index = -1; + int max_index = -1; + int index_max = 0, index_min = 0; + struct cpufreq_frequency_table *table, *pos; + + table = policy->freq_table; + if (!table) { + pr_err("cpufreq: Failed to get frequency table for CPU\n"); + return -EINVAL; + } + + max_cpufreq_index = (unsigned int)pm_qos_request(PM_QOS_C2_CPUFREQ_MAX); + min_cpufreq_index = (unsigned int)pm_qos_request(PM_QOS_C2_CPUFREQ_MIN); + + /* you can limit the min cpufreq*/ + if (min_cpufreq_index > max_cpufreq_index) + max_cpufreq_index = min_cpufreq_index; + + /* get the available cpufreq + * lock for the max available cpufreq + */ + cpufreq_for_each_valid_entry(pos, table) { + max_index = pos - table; + } + + /* add limits */ + if (max_cpufreq_index & MASK_CPUFREQ) { + index_max = MAX_CPUFREQ - max_cpufreq_index; + if (index_max > max_index) + index_max = 0; + index_max = max_index - index_max; + } else { + if (max_cpufreq_index > max_index) + index_max = max_index; + } + if (min_cpufreq_index & MASK_CPUFREQ) { + index_min = MAX_CPUFREQ - min_cpufreq_index; + if (index_min > max_index) + index_min = 0; + index_min = max_index - index_min; + } else { + if (min_cpufreq_index > max_index) + index_min = max_index; + } + c2_qos_request_value.max_cpufreq = table[index_max].frequency; + c2_qos_request_value.min_cpufreq = table[index_min].frequency; + pr_debug("c2::: m:%d, ii:%d-, mm:%d-", max_index, index_min, index_max); + + return 0; +} + +static int c0_cpufreq_qos_handler(struct notifier_block *b, + unsigned long val, void *v) +{ + struct cpufreq_policy *policy; + int ret = -1; + + policy = cpufreq_cpu_get(0); + + if (!policy) + return NOTIFY_BAD; + + if (!policy->governor) { + cpufreq_cpu_put(policy); + return NOTIFY_BAD; + } + + if (strcmp(policy->governor->name, "schedutil")) { + cpufreq_cpu_put(policy); + return NOTIFY_OK; + } + + ret = get_c0_available_cpufreq(policy); + if (ret) { + cpufreq_cpu_put(policy); + return NOTIFY_BAD; + } + cpufreq_driver_fast_switch(policy, c0_qos_request_value.min_cpufreq); + + cpufreq_cpu_put(policy); + return NOTIFY_OK; +} + +static struct notifier_block c0_cpufreq_qos_notifier = { + .notifier_call = c0_cpufreq_qos_handler, +}; + +static int c1_cpufreq_qos_handler(struct notifier_block *b, + unsigned long val, void *v) +{ + struct cpufreq_policy *policy; + int ret = -1; + + policy = cpufreq_cpu_get(cluster1_first_cpu); + + if (!policy) + return NOTIFY_BAD; + + if (!policy->governor) { + cpufreq_cpu_put(policy); + return NOTIFY_BAD; + } + + if (strcmp(policy->governor->name, "schedutil")) { + cpufreq_cpu_put(policy); + return NOTIFY_OK; + } + + ret = get_c1_available_cpufreq(policy); + if (ret) { + cpufreq_cpu_put(policy); + return NOTIFY_BAD; + } + + cpufreq_driver_fast_switch(policy, c1_qos_request_value.min_cpufreq); + + cpufreq_cpu_put(policy); + + return NOTIFY_OK; +} + +static struct notifier_block c1_cpufreq_qos_notifier = { + .notifier_call = c1_cpufreq_qos_handler, +}; + +static int c2_cpufreq_qos_handler(struct notifier_block *b, + unsigned long val, void *v) +{ + struct cpufreq_policy *policy; + int ret = -1; + + policy = cpufreq_cpu_get(cluster2_first_cpu); + + if (!policy) + return NOTIFY_BAD; + + if (!policy->governor) { + cpufreq_cpu_put(policy); + return NOTIFY_BAD; + } + + if (strcmp(policy->governor->name, "schedutil")) { + cpufreq_cpu_put(policy); + return NOTIFY_OK; + } + + ret = get_c2_available_cpufreq(policy); + if (ret) { + cpufreq_cpu_put(policy); + return NOTIFY_BAD; + } + + cpufreq_driver_fast_switch(policy, c2_qos_request_value.min_cpufreq); + + cpufreq_cpu_put(policy); + + return NOTIFY_OK; +} + +static struct notifier_block c2_cpufreq_qos_notifier = { + .notifier_call = c2_cpufreq_qos_handler, +}; + +static int __init pm_qos_notifier_init(void) +{ + /* add cpufreq qos notify */ + pm_qos_add_notifier(PM_QOS_C0_CPUFREQ_MAX, &c0_cpufreq_qos_notifier); + pm_qos_add_notifier(PM_QOS_C0_CPUFREQ_MIN, &c0_cpufreq_qos_notifier); + pm_qos_add_notifier(PM_QOS_C1_CPUFREQ_MAX, &c1_cpufreq_qos_notifier); + pm_qos_add_notifier(PM_QOS_C1_CPUFREQ_MIN, &c1_cpufreq_qos_notifier); + pm_qos_add_notifier(PM_QOS_C2_CPUFREQ_MAX, &c2_cpufreq_qos_notifier); + pm_qos_add_notifier(PM_QOS_C2_CPUFREQ_MIN, &c2_cpufreq_qos_notifier); + return 0; +} +subsys_initcall(pm_qos_notifier_init); diff --git a/drivers/cpufreq/cpufreq_performance.c b/drivers/cpufreq/cpufreq_performance.c index dafb679adc58..7f0def1a8118 100644 --- a/drivers/cpufreq/cpufreq_performance.c +++ b/drivers/cpufreq/cpufreq_performance.c @@ -15,11 +15,43 @@ #include #include #include +#include +#define CPUFREQ_INDEX 5 static void cpufreq_gov_performance_limits(struct cpufreq_policy *policy) { + unsigned int index = 0; + unsigned int valid_freq; + struct cpufreq_frequency_table *table, *pos; + static unsigned int first_cpu = 1010; pr_debug("setting to %u kHz\n", policy->max); - __cpufreq_driver_target(policy, policy->max, CPUFREQ_RELATION_H); + if (get_boot_mode() == MSM_BOOT_MODE__WLAN + || (get_boot_mode() == MSM_BOOT_MODE__RF) + || (get_boot_mode() == MSM_BOOT_MODE__FACTORY)) { + if (first_cpu != cpumask_first(policy->related_cpus)) + first_cpu = cpumask_first(policy->related_cpus); + table = policy->freq_table; + if (!table) { + pr_err("Failed to get freqtable\n"); + } else { + for (pos = table; pos->frequency + != CPUFREQ_TABLE_END; pos++) + index++; + if (index > CPUFREQ_INDEX) + index = index - CPUFREQ_INDEX; + valid_freq = table[index].frequency; + if (valid_freq) + __cpufreq_driver_target(policy, + valid_freq, + CPUFREQ_RELATION_H); + else + __cpufreq_driver_target(policy, + policy->max, + CPUFREQ_RELATION_H); + } + } else + __cpufreq_driver_target(policy, policy->max, + CPUFREQ_RELATION_H); } static struct cpufreq_governor cpufreq_gov_performance = { diff --git a/drivers/cpufreq/cpufreq_stats.c b/drivers/cpufreq/cpufreq_stats.c index e75880eb037d..994e630ed910 100644 --- a/drivers/cpufreq/cpufreq_stats.c +++ b/drivers/cpufreq/cpufreq_stats.c @@ -29,12 +29,13 @@ struct cpufreq_stats { static int cpufreq_stats_update(struct cpufreq_stats *stats) { + unsigned long flags; unsigned long long cur_time = get_jiffies_64(); - spin_lock(&cpufreq_stats_lock); + spin_lock_irqsave(&cpufreq_stats_lock, flags); stats->time_in_state[stats->last_index] += cur_time - stats->last_time; stats->last_time = cur_time; - spin_unlock(&cpufreq_stats_lock); + spin_unlock_irqrestore(&cpufreq_stats_lock, flags); return 0; } @@ -59,8 +60,6 @@ static ssize_t show_time_in_state(struct cpufreq_policy *policy, char *buf) ssize_t len = 0; int i; - if (policy->fast_switch_enabled) - return 0; cpufreq_stats_update(stats); for (i = 0; i < stats->state_num; i++) { @@ -85,8 +84,6 @@ static ssize_t show_trans_table(struct cpufreq_policy *policy, char *buf) ssize_t len = 0; int i, j; - if (policy->fast_switch_enabled) - return 0; len += snprintf(buf + len, PAGE_SIZE - len, " From : To\n"); len += snprintf(buf + len, PAGE_SIZE - len, " : "); @@ -235,7 +232,7 @@ void cpufreq_stats_record_transition(struct cpufreq_policy *policy, new_index = freq_table_get_index(stats, new_freq); /* We can't do stats->time_in_state[-1]= .. */ - if (old_index == -1 || new_index == -1 || old_index == new_index) + if (new_index == -1) return; cpufreq_stats_update(stats); diff --git a/drivers/cpuidle/lpm-levels.c b/drivers/cpuidle/lpm-levels.c index ac2c6f7ea8d0..a570d34e6af0 100644 --- a/drivers/cpuidle/lpm-levels.c +++ b/drivers/cpuidle/lpm-levels.c @@ -127,6 +127,12 @@ module_param_named(print_parsed_dt, print_parsed_dt, bool, 0664); static bool sleep_disabled; module_param_named(sleep_disabled, sleep_disabled, bool, 0664); +void msm_cpuidle_set_sleep_disable(bool disable) +{ + sleep_disabled = disable; + pr_info("%s:sleep_disabled=%d\n", __func__, disable); +} + /** * msm_cpuidle_get_deep_idle_latency - Get deep idle latency value * diff --git a/drivers/devfreq/arm-memlat-mon.c b/drivers/devfreq/arm-memlat-mon.c index 740dc6f8d04f..a80d6c2bebe3 100644 --- a/drivers/devfreq/arm-memlat-mon.c +++ b/drivers/devfreq/arm-memlat-mon.c @@ -34,6 +34,9 @@ #include #include +// tedlin@ASTI, 2019/06/12 add for CONFIG_HOUSTON +#include + enum ev_index { INST_IDX, CM_IDX, @@ -123,6 +126,10 @@ static void read_perf_counters(int cpu, struct cpu_grp_info *cpu_grp) } else { devstats->stall_pct = 100; } + +// tedlin@ASTI, 2019/06/12 add to update hw events (CONFIG_HOUSTON) + ht_update_hw_events(devstats->inst_count, devstats->mem_count, cyc_cnt); + } static unsigned long get_cnt(struct memlat_hwmon *hw) diff --git a/drivers/devfreq/bimc-bwmon.c b/drivers/devfreq/bimc-bwmon.c index af19be8c6628..698c60000fe8 100644 --- a/drivers/devfreq/bimc-bwmon.c +++ b/drivers/devfreq/bimc-bwmon.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -28,7 +28,6 @@ #include #include #include -#include #include "governor_bw_hwmon.h" #define GLB_INT_STATUS(m) ((m)->global_base + 0x100) @@ -100,8 +99,6 @@ struct bwmon { void __iomem *global_base; unsigned int mport; int irq; - int nr_clks; - struct clk **clks; const struct bwmon_spec *spec; struct device *dev; struct bw_hwmon hw; @@ -591,16 +588,15 @@ unsigned long get_zone_count(struct bwmon *m, unsigned int zone, WARN(1, "Invalid\n"); return 0; case MON2: - count = readl_relaxed(MON2_ZONE_MAX(m, zone)); + count = readl_relaxed(MON2_ZONE_MAX(m, zone)) + 1; break; case MON3: count = readl_relaxed(MON3_ZONE_MAX(m, zone)); + if (count) + count++; break; } - if (count) - count++; - return count; } @@ -786,27 +782,6 @@ void mon_set_byte_count_filter(struct bwmon *m, enum mon_reg_type type) } } -static __always_inline int mon_clk_enable(struct bwmon *m) -{ - int ret; - int i; - - for (i = 0; i < m->nr_clks; i++) { - ret = clk_prepare_enable(m->clks[i]); - if (ret) { - dev_err(m->dev, "BWMON clk not enabled %d\n", ret); - goto err; - } - } - - return 0; -err: - for (i--; i >= 0; i--) - clk_disable_unprepare(m->clks[i]); - - return ret; -} - static __always_inline int __start_bw_hwmon(struct bw_hwmon *hw, unsigned long mbps, enum mon_reg_type type) { @@ -815,12 +790,6 @@ static __always_inline int __start_bw_hwmon(struct bw_hwmon *hw, int ret; irq_handler_t handler; - ret = mon_clk_enable(m); - if (ret) { - dev_err(m->dev, "Unable to turn on bwmon clks! (%d)\n", ret); - return ret; - } - switch (type) { case MON1: handler = bwmon_intr_handler; @@ -887,14 +856,6 @@ static int start_bw_hwmon3(struct bw_hwmon *hw, unsigned long mbps) return __start_bw_hwmon(hw, mbps, MON3); } -static __always_inline void mon_clk_disable(struct bwmon *m) -{ - int i; - - for (i = m->nr_clks - 1; i >= 0; i--) - clk_disable_unprepare(m->clks[i]); -} - static __always_inline void __stop_bw_hwmon(struct bw_hwmon *hw, enum mon_reg_type type) { @@ -905,7 +866,6 @@ void __stop_bw_hwmon(struct bw_hwmon *hw, enum mon_reg_type type) mon_disable(m, type); mon_clear(m, true, type); mon_irq_clear(m, type); - mon_clk_disable(m); } static void stop_bw_hwmon(struct bw_hwmon *hw) @@ -958,12 +918,6 @@ int __resume_bw_hwmon(struct bw_hwmon *hw, enum mon_reg_type type) int ret; irq_handler_t handler; - ret = mon_clk_enable(m); - if (ret) { - dev_err(m->dev, "Unable to turn on bwmon clks! (%d)\n", ret); - return ret; - } - switch (type) { case MON1: handler = bwmon_intr_handler; @@ -1067,7 +1021,6 @@ static int bimc_bwmon_driver_probe(struct platform_device *pdev) struct bwmon *m; int ret; u32 data, count_unit; - unsigned int len, i; m = devm_kzalloc(dev, sizeof(*m), GFP_KERNEL); if (!m) @@ -1113,42 +1066,6 @@ static int bimc_bwmon_driver_probe(struct platform_device *pdev) m->mport = data; } - if (of_find_property(dev->of_node, "qcom,bwmon_clks", &len)) { - m->nr_clks = of_property_count_strings(dev->of_node, - "qcom,bwmon_clks"); - if (!m->nr_clks) { - dev_err(dev, "Failed to get clock names\n"); - return -EINVAL; - } - - m->clks = devm_kzalloc(dev, sizeof(struct clk *) * m->nr_clks, - GFP_KERNEL); - if (!m->clks) - return -ENOMEM; - - for (i = 0; i < m->nr_clks; i++) { - const char *clock_name; - - ret = of_property_read_string_index(dev->of_node, - "qcom,bwmon_clks", i, - &clock_name); - if (ret) { - pr_err("failed to read clk index %d ret %d\n", - i, ret); - return ret; - } - m->clks[i] = devm_clk_get(dev, clock_name); - if (IS_ERR(m->clks[i])) { - ret = PTR_ERR(m->clks[i]); - if (ret != -EPROBE_DEFER) - dev_err(dev, "Error to get %s clk %d\n", - clock_name, ret); - return ret; - } - } - } else - m->nr_clks = 0; - m->irq = platform_get_irq(pdev, 0); if (m->irq < 0) { dev_err(dev, "Unable to get IRQ number\n"); diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c index 586691521ec2..0320a15ba706 100644 --- a/drivers/devfreq/devfreq.c +++ b/drivers/devfreq/devfreq.c @@ -28,6 +28,8 @@ #include #include "governor.h" +#include + static struct class *devfreq_class; /* @@ -253,7 +255,9 @@ int update_devfreq(struct devfreq *devfreq) unsigned long freq, cur_freq; int err = 0; u32 flags = 0; - +#ifdef CONFIG_CONTROL_CENTER + unsigned long freq_tmp; +#endif if (!mutex_is_locked(&devfreq->lock)) { WARN(true, "devfreq->lock must be locked by the caller.\n"); return -EINVAL; @@ -283,7 +287,20 @@ int update_devfreq(struct devfreq *devfreq) freq = devfreq->max_freq; flags |= DEVFREQ_FLAG_LEAST_UPPER_BOUND; /* Use LUB */ } - +#ifdef CONFIG_CONTROL_CENTER + if (cc_ddr_set_enable) { + if (devfreq->dev.cc_marked) { + freq = max((unsigned long)atomic_read(&cc_expect_ddrfreq), freq); + } + } + if (cc_ddr_lock_enable) { + if (devfreq->dev.cc_marked) { + freq_tmp = atomic_read(&cc_expect_ddrfreq); + if (freq_tmp) + freq = freq_tmp; + } + } +#endif if (devfreq->profile->get_cur_freq) devfreq->profile->get_cur_freq(devfreq->dev.parent, &cur_freq); else @@ -464,7 +481,8 @@ void devfreq_interval_update(struct devfreq *devfreq, unsigned int *delay) mutex_unlock(&devfreq->lock); cancel_delayed_work_sync(&devfreq->work); mutex_lock(&devfreq->lock); - if (!devfreq->stop_polling) + if (!devfreq->stop_polling + && !delayed_work_pending(&devfreq->work)) queue_delayed_work(devfreq_wq, &devfreq->work, msecs_to_jiffies(devfreq->profile->polling_ms)); } @@ -586,6 +604,11 @@ struct devfreq *devfreq_add_device(struct device *dev, devfreq_set_freq_limits(devfreq); dev_set_name(&devfreq->dev, "%s", dev_name(dev)); +#ifdef CONFIG_CONTROL_CENTER + if (dev_name(dev)) + devfreq->dev.cc_marked = cc_is_ddrfreq_related(dev_name(dev)); +#endif + err = device_register(&devfreq->dev); if (err) { mutex_unlock(&devfreq->lock); diff --git a/drivers/devfreq/devfreq_devbw.c b/drivers/devfreq/devfreq_devbw.c index a6b8b9fe1cc7..4e479490ce07 100644 --- a/drivers/devfreq/devfreq_devbw.c +++ b/drivers/devfreq/devfreq_devbw.c @@ -37,6 +37,19 @@ #define MAX_PATHS 2 #define DBL_BUF 2 +#include +struct qos_request_v { + int max_state; + int max_devfreq; + int min_devfreq; +}; + +static bool cpubw_flag; +static struct qos_request_v qos_request_value = { + .max_state = 0, + .max_devfreq = INT_MAX, + .min_devfreq = 0, +}; struct dev_data { struct msm_bus_vectors vectors[MAX_PATHS * DBL_BUF]; struct msm_bus_paths bw_levels[DBL_BUF]; @@ -80,6 +93,50 @@ static int set_bw(struct device *dev, int new_ib, int new_ab) return ret; } +static void find_freq_cpubw(struct devfreq_dev_profile *p, unsigned long *freq, + u32 flags) +{ + int i; + unsigned long atmost, atleast, f; + int min_index, max_index; + + min_index = qos_request_value.min_devfreq; + if (p->max_state > qos_request_value.max_devfreq) + max_index = qos_request_value.max_devfreq; + else + max_index = p->max_state; + + atmost = p->freq_table[min_index]; + atleast = p->freq_table[max_index-1]; + + for (i = min_index; i < max_index; i++) { + f = p->freq_table[i]; + if (f <= *freq) + atmost = max(f, atmost); + if (f >= *freq) + atleast = min(f, atleast); + } + + if (flags & DEVFREQ_FLAG_LEAST_UPPER_BOUND) + *freq = atmost; + else + *freq = atleast; +} + +static int devbw_target_cpubw(struct device *dev, unsigned long *freq, + u32 flags) +{ + struct dev_data *d = dev_get_drvdata(dev); + struct dev_pm_opp *opp; + + opp = devfreq_recommended_opp(dev, freq, flags); + if (!IS_ERR(opp)) + dev_pm_opp_put(opp); + find_freq_cpubw(&d->dp, freq, flags); + + return set_bw(dev, *freq, d->gov_ab); +} + static int devbw_target(struct device *dev, unsigned long *freq, u32 flags) { struct dev_data *d = dev_get_drvdata(dev); @@ -101,6 +158,44 @@ static int devbw_get_dev_status(struct device *dev, return 0; } +static int devfreq_qos_handler(struct notifier_block *b, unsigned long val, + void *v) +{ + unsigned int max_devfreq_index, min_devfreq_index; + unsigned int index_max = 0, index_min = 0; + + max_devfreq_index = (unsigned int)pm_qos_request(PM_QOS_DEVFREQ_MAX); + min_devfreq_index = (unsigned int)pm_qos_request(PM_QOS_DEVFREQ_MIN); + + /* add limit */ + if (max_devfreq_index & MASK_CPUFREQ) { + index_max = MAX_CPUFREQ - max_devfreq_index; + if (index_max > qos_request_value.max_state) + index_max = 0; + index_max = qos_request_value.max_state - index_max; + } else { + if (max_devfreq_index > qos_request_value.max_state) + index_max = qos_request_value.max_state; + } + if (min_devfreq_index & MASK_CPUFREQ) { + index_min = MAX_CPUFREQ - min_devfreq_index; + if (index_min > (qos_request_value.max_state-1)) + index_min = 0; + index_min = qos_request_value.max_state - 1 - index_min; + } else { + if (min_devfreq_index > qos_request_value.max_state) + index_min = qos_request_value.max_state - 1; + } + + qos_request_value.min_devfreq = index_min; + qos_request_value.max_devfreq = index_max; + + return NOTIFY_OK; +} +static struct notifier_block devfreq_qos_notifier = { + .notifier_call = devfreq_qos_handler, +}; + #define PROP_OPERATING_POINTS_V2 "operating-points-v2" static int add_opp_prop_from_child(struct device *dev, @@ -212,7 +307,13 @@ int devfreq_add_devbw(struct device *dev) p = &d->dp; p->polling_ms = 50; - p->target = devbw_target; + + if (strnstr(d->bw_data.name, "soc:qcom,cpu-cpu-llcc-bw", + strlen(d->bw_data.name)) != NULL) { + p->target = devbw_target_cpubw; + cpubw_flag = true; + } else + p->target = devbw_target; p->get_dev_status = devbw_get_dev_status; if (of_get_child_count(dev->of_node)) ret = parse_child_nodes_for_opp(dev); @@ -237,6 +338,12 @@ int devfreq_add_devbw(struct device *dev) return PTR_ERR(d->df); } + if (cpubw_flag) { + cpubw_flag = false; + qos_request_value.max_state = p->max_state; + qos_request_value.min_devfreq = 0; + qos_request_value.max_devfreq = p->max_state; + } return 0; } @@ -284,10 +391,20 @@ static struct platform_driver devbw_driver = { .driver = { .name = "devbw", .of_match_table = devbw_match_table, + .owner = THIS_MODULE, .suppress_bind_attrs = true, }, }; -module_platform_driver(devbw_driver); +static int __init devbw_init(void) +{ + /* add cpufreq qos notify */ + cpubw_flag = false; + pm_qos_add_notifier(PM_QOS_DEVFREQ_MAX, &devfreq_qos_notifier); + pm_qos_add_notifier(PM_QOS_DEVFREQ_MIN, &devfreq_qos_notifier); + platform_driver_register(&devbw_driver); + return 0; +} +device_initcall(devbw_init); MODULE_DESCRIPTION("Device DDR bandwidth voting driver MSM SoCs"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/devfreq/governor_bw_hwmon.c b/drivers/devfreq/governor_bw_hwmon.c index 330c45a8c1fe..164d622c3a50 100644 --- a/drivers/devfreq/governor_bw_hwmon.c +++ b/drivers/devfreq/governor_bw_hwmon.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -617,8 +617,7 @@ static int gov_start(struct devfreq *df) node->orig_data = df->data; df->data = node; - ret = start_monitor(df, true); - if (ret) + if (start_monitor(df, true)) goto err_start; ret = sysfs_create_group(&df->dev.kobj, node->attr_grp); diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c index ca1028e7ab45..eab48c682d85 100644 --- a/drivers/dma/qcom/gpi.c +++ b/drivers/dma/qcom/gpi.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -441,7 +441,6 @@ struct gpi_dev { struct device *dev; struct resource *res; void __iomem *regs; - void __iomem *ee_base; /*ee register base address*/ u32 max_gpii; /* maximum # of gpii instances available per gpi block */ u32 gpii_mask; /* gpii instances available for apps */ u32 ev_factor; /* ev ring length factor */ @@ -2650,7 +2649,6 @@ static int gpi_probe(struct platform_device *pdev) { struct gpi_dev *gpi_dev; int ret, i; - u32 gpi_ee_offset; gpi_dev = devm_kzalloc(&pdev->dev, sizeof(*gpi_dev), GFP_KERNEL); if (!gpi_dev) @@ -2671,8 +2669,6 @@ static int gpi_probe(struct platform_device *pdev) return -EFAULT; } - gpi_dev->ee_base = gpi_dev->regs; - ret = of_property_read_u32(gpi_dev->dev->of_node, "qcom,max-num-gpii", &gpi_dev->max_gpii); if (ret) { @@ -2687,14 +2683,6 @@ static int gpi_probe(struct platform_device *pdev) return ret; } - ret = of_property_read_u32(gpi_dev->dev->of_node, - "qcom,gpi-ee-offset", &gpi_ee_offset); - if (ret) - GPI_LOG(gpi_dev, "No variable ee offset present\n"); - else - gpi_dev->ee_base = - gpi_dev->ee_base - gpi_ee_offset; - ret = of_property_read_u32(gpi_dev->dev->of_node, "qcom,ev-factor", &gpi_dev->ev_factor); if (ret) { @@ -2744,6 +2732,7 @@ static int gpi_probe(struct platform_device *pdev) if (!gpi_dev->gpiis) return -ENOMEM; + /* setup all the supported gpii */ INIT_LIST_HEAD(&gpi_dev->dma_device.channels); for (i = 0; i < gpi_dev->max_gpii; i++) { @@ -2754,9 +2743,9 @@ static int gpi_probe(struct platform_device *pdev) continue; /* set up ev cntxt register map */ - gpii->ev_cntxt_base_reg = gpi_dev->ee_base + + gpii->ev_cntxt_base_reg = gpi_dev->regs + GPI_GPII_n_EV_CH_k_CNTXT_0_OFFS(i, 0); - gpii->ev_cntxt_db_reg = gpi_dev->ee_base + + gpii->ev_cntxt_db_reg = gpi_dev->regs + GPI_GPII_n_EV_CH_k_DOORBELL_0_OFFS(i, 0); gpii->ev_ring_base_lsb_reg = gpii->ev_cntxt_base_reg + CNTXT_2_RING_BASE_LSB; @@ -2764,11 +2753,11 @@ static int gpi_probe(struct platform_device *pdev) CNTXT_4_RING_RP_LSB; gpii->ev_ring_wp_lsb_reg = gpii->ev_cntxt_base_reg + CNTXT_6_RING_WP_LSB; - gpii->ev_cmd_reg = gpi_dev->ee_base + + gpii->ev_cmd_reg = gpi_dev->regs + GPI_GPII_n_EV_CH_CMD_OFFS(i); - gpii->ieob_src_reg = gpi_dev->ee_base + + gpii->ieob_src_reg = gpi_dev->regs + GPI_GPII_n_CNTXT_SRC_IEOB_IRQ_OFFS(i); - gpii->ieob_clr_reg = gpi_dev->ee_base + + gpii->ieob_clr_reg = gpi_dev->regs + GPI_GPII_n_CNTXT_SRC_IEOB_IRQ_CLR_OFFS(i); /* set up irq */ @@ -2785,9 +2774,9 @@ static int gpi_probe(struct platform_device *pdev) struct gpii_chan *gpii_chan = &gpii->gpii_chan[chan]; /* set up ch cntxt register map */ - gpii_chan->ch_cntxt_base_reg = gpi_dev->ee_base + + gpii_chan->ch_cntxt_base_reg = gpi_dev->regs + GPI_GPII_n_CH_k_CNTXT_0_OFFS(i, chan); - gpii_chan->ch_cntxt_db_reg = gpi_dev->ee_base + + gpii_chan->ch_cntxt_db_reg = gpi_dev->regs + GPI_GPII_n_CH_k_DOORBELL_0_OFFS(i, chan); gpii_chan->ch_ring_base_lsb_reg = gpii_chan->ch_cntxt_base_reg + @@ -2798,7 +2787,7 @@ static int gpi_probe(struct platform_device *pdev) gpii_chan->ch_ring_wp_lsb_reg = gpii_chan->ch_cntxt_base_reg + CNTXT_6_RING_WP_LSB; - gpii_chan->ch_cmd_reg = gpi_dev->ee_base + + gpii_chan->ch_cmd_reg = gpi_dev->regs + GPI_GPII_n_CH_CMD_OFFS(i); /* vchan setup */ @@ -2814,7 +2803,7 @@ static int gpi_probe(struct platform_device *pdev) (unsigned long)gpii); init_completion(&gpii->cmd_completion); gpii->gpii_id = i; - gpii->regs = gpi_dev->ee_base; + gpii->regs = gpi_dev->regs; gpii->gpi_dev = gpi_dev; atomic_set(&gpii->dbg_index, 0); } diff --git a/drivers/esoc/esoc-mdm-4x.c b/drivers/esoc/esoc-mdm-4x.c index 2ff2972d454b..eb9399724211 100644 --- a/drivers/esoc/esoc-mdm-4x.c +++ b/drivers/esoc/esoc-mdm-4x.c @@ -16,6 +16,8 @@ #include #include #include "esoc-mdm.h" +#include +#include enum gpio_update_config { GPIO_UPDATE_BOOTING_CONFIG = 1, @@ -264,12 +266,20 @@ static int mdm_cmd_exe(enum esoc_cmd cmd, struct esoc_clink *esoc) if (esoc->statusline_not_a_powersource == false) { esoc_mdm_log( "ESOC_FORCE_PWR_OFF: setting AP2MDM_STATUS = 0\n"); - gpio_set_value(MDM_GPIO(mdm, AP2MDM_STATUS), 0); + dev_err(mdm->dev, + "ESOC_FORCE_PWR_OFF: setting AP2MDM_STATUS = 0\n"); + //gpio_set_value(MDM_GPIO(mdm, AP2MDM_STATUS), 0); } esoc_mdm_log( "ESOC_FORCE_PWR_OFF: Queueing request: ESOC_REQ_SHUTDOWN\n"); + dev_err(mdm->dev, + "ESOC_FORCE_PWR_OFF: Queueing request: ESOC_REQ_SHUTDOWN\n"); esoc_clink_queue_request(ESOC_REQ_SHUTDOWN, esoc); + dev_err(mdm->dev, + "ESOC_FORCE_PWR_OFF: mdm_power_down start!\n"); mdm_power_down(mdm); + dev_err(mdm->dev, + "ESOC_FORCE_PWR_OFF: mdm_power_down end!\n"); mdm_update_gpio_configs(mdm, GPIO_UPDATE_BOOTING_CONFIG); break; case ESOC_RESET: @@ -394,6 +404,26 @@ static void mdm_get_restart_reason(struct work_struct *work) __func__, ret); } mdm->get_restart_reason = false; + + if (is_oem_esoc_ssr() == 1) { + oem_set_esoc_ssr(0); + } + + if (oem_get_download_mode()) { + char detial_buf[] = "\nSDX5x esoc0 modem crash"; + + oem_set_esoc_ssr(0); + if ((strlen(sfr_buf)+sizeof(detial_buf)) < RD_BUF_SIZE) + strncat(sfr_buf, detial_buf, strlen(detial_buf)); + + esoc_mdm_log( + "[OEM_MDM] Trigger panic by OEM to get SDX5x dump!\n"); + dev_err(dev, + "[OEM_MDM] Trigger panic by OEM to get SDX5x dump!\n"); + msleep(5000); + mdm_power_down(mdm); + panic(sfr_buf); + } } void mdm_wait_for_status_low(struct mdm_ctrl *mdm, bool atomic) @@ -846,6 +876,23 @@ static void mdm_free_irq(struct mdm_ctrl *mdm) free_irq(mdm->status_irq, mdm); } +static int esoc_ssr_reason_feature_enable =0; +int get_ssr_reason_state(void) +{ + return esoc_ssr_reason_feature_enable; +} + +static int esoc_ssr_occur =0; +int oem_set_esoc_ssr(int enable) +{ + esoc_ssr_occur = enable; + return 0; +} +int is_oem_esoc_ssr(void) +{ + return esoc_ssr_occur; +} + static int mdm9x55_setup_hw(struct mdm_ctrl *mdm, const struct mdm_ops *ops, struct platform_device *pdev) @@ -1014,6 +1061,10 @@ static int sdx50m_setup_hw(struct mdm_ctrl *mdm, mdm->skip_restart_for_mdm_crash = of_property_read_bool(node, "qcom,esoc-skip-restart-for-mdm-crash"); + esoc_ssr_reason_feature_enable = of_property_read_bool(node, + "oem,esoc_ssr_reason_feature_enable"); + + esoc->clink_ops = clink_ops; esoc->parent = mdm->dev; esoc->owner = THIS_MODULE; @@ -1115,6 +1166,12 @@ static int mdm_probe(struct platform_device *pdev) struct mdm_ctrl *mdm; int ret; + if (get_second_board_absent() == 1) { + pr_err("%s second board absent, don't probe esoc-mdm-4x", + __func__); + ret = -1; + return ret; + } match = of_match_node(mdm_dt_match, node); if (IS_ERR_OR_NULL(match)) return PTR_ERR(match); @@ -1145,6 +1202,12 @@ static struct platform_driver mdm_driver = { static int __init mdm_register(void) { + if (get_second_board_absent() == 1) { + pr_err("%s second board absent, don't probe esoc-mdm-4x", + __func__); + return false; + } + return platform_driver_register(&mdm_driver); } module_init(mdm_register); diff --git a/drivers/esoc/esoc-mdm-dbg-eng.c b/drivers/esoc/esoc-mdm-dbg-eng.c index d3b4bd7fa717..8eb4fea0ec0a 100644 --- a/drivers/esoc/esoc-mdm-dbg-eng.c +++ b/drivers/esoc/esoc-mdm-dbg-eng.c @@ -12,6 +12,7 @@ #include #include #include "esoc.h" +#include /* * cmd_mask : Specifies if a command/notifier is masked, and @@ -342,6 +343,12 @@ int mdm_dbg_eng_init(struct esoc_drv *esoc_drv, int ret; struct device_driver *drv = &esoc_drv->driver; + if (get_second_board_absent() == 1) { + pr_err("%s second board absent, don't probe esoc-mdm-dbg-eng", + __func__); + ret = -1; + return ret; + } ret = driver_create_file(drv, &driver_attr_command_mask); if (ret) { pr_err("Unable to create command mask file\n"); diff --git a/drivers/esoc/esoc-mdm-drv.c b/drivers/esoc/esoc-mdm-drv.c old mode 100755 new mode 100644 index 827b84b71cdc..b85872ab873e --- a/drivers/esoc/esoc-mdm-drv.c +++ b/drivers/esoc/esoc-mdm-drv.c @@ -18,6 +18,7 @@ #include "esoc.h" #include "esoc-mdm.h" #include "mdm-dbg.h" +#include /* Default number of powerup trial requests per session */ #define ESOC_DEF_PON_REQ 3 @@ -26,6 +27,8 @@ #define BOOT_FAIL_ACTION_DEF BOOT_FAIL_ACTION_PANIC +bool modem_5G_panic; + enum esoc_pon_state { PON_INIT, PON_SUCCESS, @@ -184,6 +187,7 @@ static void mdm_handle_clink_evt(enum esoc_evt evt, esoc_mdm_log("Modem not up. Ignoring.\n"); if (mdm_drv->mode == CRASH || mdm_drv->mode != RUN) return; + mdm_drv->mode = CRASH; queue_work(mdm_drv->mdm_queue, &mdm_drv->ssr_work); break; case ESOC_REQ_ENG_ON: @@ -205,9 +209,7 @@ static void mdm_ssr_fn(struct work_struct *work) mdm_wait_for_status_low(mdm, false); - esoc_mdm_log("Starting SSR work and setting crash state\n"); - mdm_drv->mode = CRASH; - + esoc_mdm_log("Starting SSR work\n"); /* * If restarting esoc fails, the SSR framework triggers a kernel panic */ @@ -284,7 +286,7 @@ static void mdm_crash_shutdown(const struct subsys_desc *mdm_subsys) static int mdm_subsys_shutdown(const struct subsys_desc *crashed_subsys, bool force_stop) { - int ret = 0; + int ret; struct esoc_clink *esoc_clink = container_of(crashed_subsys, struct esoc_clink, subsys); struct mdm_drv *mdm_drv = esoc_get_drv_data(esoc_clink); @@ -292,16 +294,14 @@ static int mdm_subsys_shutdown(const struct subsys_desc *crashed_subsys, esoc_mdm_log("Shutdown request from SSR\n"); - mutex_lock(&mdm_drv->poff_lock); if (mdm_drv->mode == CRASH || mdm_drv->mode == PEER_CRASH) { esoc_mdm_log("Shutdown in crash mode\n"); - if (mdm_dbg_stall_cmd(ESOC_PREPARE_DEBUG)) { + if (mdm_dbg_stall_cmd(ESOC_PREPARE_DEBUG)) /* We want to mask debug command. * In this case return success * to move to next stage */ - goto unlock; - } + return 0; esoc_clink_queue_request(ESOC_REQ_CRASH_SHUTDOWN, esoc_clink); esoc_client_link_power_off(esoc_clink, ESOC_HOOK_MDM_CRASH); @@ -312,14 +312,16 @@ static int mdm_subsys_shutdown(const struct subsys_desc *crashed_subsys, if (ret) { esoc_mdm_log("ESOC_PREPARE_DEBUG command failed\n"); dev_err(&esoc_clink->dev, "failed to enter debug\n"); - goto unlock; + return ret; } mdm_drv->mode = IN_DEBUG; } else if (!force_stop) { esoc_mdm_log("Graceful shutdown mode\n"); + mutex_lock(&mdm_drv->poff_lock); if (mdm_drv->mode == PWR_OFF) { + mutex_unlock(&mdm_drv->poff_lock); esoc_mdm_log("mdm already powered-off\n"); - goto unlock; + return 0; } if (esoc_clink->subsys.sysmon_shutdown_ret) { esoc_mdm_log( @@ -332,7 +334,8 @@ static int mdm_subsys_shutdown(const struct subsys_desc *crashed_subsys, * we return success, and leave the state * of the command engine as is. */ - goto unlock; + mutex_unlock(&mdm_drv->poff_lock); + return 0; } dev_dbg(&esoc_clink->dev, "Sending sysmon-shutdown\n"); esoc_mdm_log("Executing the ESOC_PWR_OFF command\n"); @@ -342,18 +345,17 @@ static int mdm_subsys_shutdown(const struct subsys_desc *crashed_subsys, esoc_mdm_log( "Executing the ESOC_PWR_OFF command failed\n"); dev_err(&esoc_clink->dev, "failed to exe power off\n"); - goto unlock; + mutex_unlock(&mdm_drv->poff_lock); + return ret; } esoc_client_link_power_off(esoc_clink, ESOC_HOOK_MDM_DOWN); /* Pull the reset line low to turn off the device */ clink_ops->cmd_exe(ESOC_FORCE_PWR_OFF, esoc_clink); mdm_drv->mode = PWR_OFF; + mutex_unlock(&mdm_drv->poff_lock); } esoc_mdm_log("Shutdown completed\n"); - -unlock: - mutex_unlock(&mdm_drv->poff_lock); - return ret; + return 0; } static void mdm_subsys_retry_powerup_cleanup(struct esoc_clink *esoc_clink, @@ -411,7 +413,10 @@ static int mdm_handle_boot_fail(struct esoc_clink *esoc_clink, u8 *pon_trial) break; case BOOT_FAIL_ACTION_PANIC: esoc_mdm_log("Calling panic!!\n"); - panic("Panic requested on external modem boot failure\n"); + if (get_second_board_absent() == 0 && oem_get_download_mode()) + panic("Panic requested on external modem boot failure\n"); + else + pr_err("Panic requested on external modem boot failure\n"); break; case BOOT_FAIL_ACTION_NOP: esoc_mdm_log("Leaving the modem in its curent state\n"); @@ -436,8 +441,11 @@ static int mdm_subsys_powerup(const struct subsys_desc *crashed_subsys) subsys); struct mdm_drv *mdm_drv = esoc_get_drv_data(esoc_clink); const struct esoc_clink_ops * const clink_ops = esoc_clink->clink_ops; + struct mdm_ctrl *mdm = get_esoc_clink_data(mdm_drv->esoc_clink); int timeout = INT_MAX; + u8 pon_trial = 0; + modem_5G_panic = false; esoc_mdm_log("Powerup request from SSR\n"); @@ -508,11 +516,33 @@ static int mdm_subsys_powerup(const struct subsys_desc *crashed_subsys) "Boot failed. Doing cleanup and attempting to retry\n"); pon_trial++; mdm_subsys_retry_powerup_cleanup(esoc_clink, 0); + + /* PON_RETRY : SDX5X jump to normal mode from dump mode */ + if (!oem_get_download_mode()) { + pr_err("[MDM] DumpMode is disabled. Skip trigger 5G dump\n"); + } else if (is_oem_esoc_ssr() == 1 || get_ssr_reason_state() == 1) { + pr_err("[MDM] Skip trigger during the oem esoc SSR\n"); + } else { + pr_err("[MDM] Trigger kernel panic to get SDX5X dump\n"); + modem_5G_panic = true; + } } else if (mdm_drv->pon_state == PON_SUCCESS) { break; } } while (pon_trial <= atomic_read(&mdm_drv->n_pon_tries)); + //because two times powerup flow, make sure SDX50 is ready + pr_err("[MDM] Roland: check 5G dump gpio\n"); + if (gpio_get_value(MDM_GPIO(mdm, MDM2AP_STATUS)) == 1) { + pr_err("[MDM] gpio check pass, 5g flag [%d]\n", modem_5G_panic); + if (modem_5G_panic == true) { + pr_err("[MDM] Power done SDX50 and wait 5s\n"); + msleep(5000); + mdm_power_down(mdm); + panic("get the SDX50 dump"); // warm reset device + } + } + return 0; } @@ -557,6 +587,12 @@ int esoc_ssr_probe(struct esoc_clink *esoc_clink, struct esoc_drv *drv) struct mdm_drv *mdm_drv; struct esoc_eng *esoc_eng; + if (get_second_board_absent() == 1) { + pr_err("%s second board absent, don't probe esoc-mdm-drv", + __func__); + ret = -1; + return ret; + } mdm_drv = devm_kzalloc(&esoc_clink->dev, sizeof(*mdm_drv), GFP_KERNEL); if (IS_ERR_OR_NULL(mdm_drv)) return PTR_ERR(mdm_drv); @@ -633,6 +669,11 @@ static struct esoc_drv esoc_ssr_drv = { int __init esoc_ssr_init(void) { + if (get_second_board_absent() == 1) { + pr_err("%s second board absent, don't probe esoc-mdm-drv", + __func__); + return false; + } return esoc_drv_register(&esoc_ssr_drv); } module_init(esoc_ssr_init); diff --git a/drivers/esoc/esoc-mdm-pon.c b/drivers/esoc/esoc-mdm-pon.c index 6e75fb5a4dbd..31033f425324 100644 --- a/drivers/esoc/esoc-mdm-pon.c +++ b/drivers/esoc/esoc-mdm-pon.c @@ -11,6 +11,7 @@ */ #include "esoc-mdm.h" +#include /* This function can be called from atomic context. */ static int mdm9x55_toggle_soft_reset(struct mdm_ctrl *mdm, bool atomic) @@ -205,7 +206,11 @@ static int mdm9x55_pon_dt_init(struct mdm_ctrl *mdm) struct device_node *node = mdm->dev->of_node; enum of_gpio_flags flags = OF_GPIO_ACTIVE_LOW; - + if (get_second_board_absent() == 1) { + pr_err("%s second board absent, don't probe esoc-mdm-pon", + __func__); + return false; + } val = of_property_read_u32(node, "qcom,reset-time-ms", &mdm->reset_time_ms); if (val) @@ -228,6 +233,11 @@ static int mdm4x_pon_dt_init(struct mdm_ctrl *mdm) struct device_node *node = mdm->dev->of_node; enum of_gpio_flags flags = OF_GPIO_ACTIVE_LOW; + if (get_second_board_absent() == 1) { + pr_err("%s second board absent, don't probe esoc-mdm-pon", + __func__); + return false; + } val = of_get_named_gpio_flags(node, "qcom,ap2mdm-soft-reset-gpio", 0, &flags); if (val >= 0) { diff --git a/drivers/esoc/esoc_bus.c b/drivers/esoc/esoc_bus.c index 39060590b72f..fbb2f500ace6 100644 --- a/drivers/esoc/esoc_bus.c +++ b/drivers/esoc/esoc_bus.c @@ -13,6 +13,7 @@ #include #include #include "esoc.h" +#include static DEFINE_IDA(esoc_ida); @@ -387,6 +388,11 @@ static int __init esoc_init(void) { int ret; + if (get_second_board_absent() == 1) { + pr_err("%s second board absent, don't probe esoc", __func__); + ret = -1; + return ret; + } ret = device_register(&esoc_bus); if (ret) { pr_err("esoc bus device register fail\n"); diff --git a/drivers/esoc/esoc_dev.c b/drivers/esoc/esoc_dev.c index bd3929074eea..b252d8746ffb 100644 --- a/drivers/esoc/esoc_dev.c +++ b/drivers/esoc/esoc_dev.c @@ -16,6 +16,7 @@ #include #include #include "esoc.h" +#include /** * struct esoc_udev: Userspace char interface @@ -469,6 +470,12 @@ int __init esoc_dev_init(void) { int ret = 0; + if (get_second_board_absent() == 1) { + pr_err("%s second board absent,don't probe esoc_dev", + __func__); + ret = -1; + return ret; + } esoc_class = class_create(THIS_MODULE, "esoc-dev"); if (IS_ERR_OR_NULL(esoc_class)) { pr_err("coudn't create class"); diff --git a/drivers/firmware/qcom/tz_log.c b/drivers/firmware/qcom/tz_log.c index 55444788ba50..2339c16c613b 100644 --- a/drivers/firmware/qcom/tz_log.c +++ b/drivers/firmware/qcom/tz_log.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -904,6 +905,103 @@ static void tzdbg_register_qsee_log_buf(struct platform_device *pdev) return; } +//add tz and qsee log to logkit +static ssize_t proc_qsee_log_func(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + int len = 0; + + memcpy_fromio((void *)tzdbg.diag_buf, tzdbg.virt_iobase, + debug_rw_buf_size); + memcpy_fromio((void *)tzdbg.hyp_diag_buf, tzdbg.hyp_virt_iobase, + tzdbg.hyp_debug_rw_buf_size); + len = _disp_qsee_log_stats(count); + *ppos = 0; + + if (len > count) + len = count; + + return simple_read_from_buffer(user_buf, len, ppos, + tzdbg.stat[6].data, len); +} + + +static const struct file_operations proc_qsee_log_fops = { + .read = proc_qsee_log_func, + .open = simple_open, + .owner = THIS_MODULE, +}; + +static ssize_t proc_tz_log_func(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + int len = 0; + + memcpy_fromio((void *)tzdbg.diag_buf, tzdbg.virt_iobase, + debug_rw_buf_size); + memcpy_fromio((void *)tzdbg.hyp_diag_buf, tzdbg.hyp_virt_iobase, + tzdbg.hyp_debug_rw_buf_size); + + if (TZBSP_DIAG_MAJOR_VERSION_LEGACY < + (tzdbg.diag_buf->version >> 16)) { + len = _disp_tz_log_stats(count); + *ppos = 0; + } else { + len = _disp_tz_log_stats_legacy(); + } + + if (len > count) + len = count; + + return simple_read_from_buffer(user_buf, len, ppos, + tzdbg.stat[5].data, len); +} + +static const struct file_operations proc_tz_log_fops = { + .read = proc_tz_log_func, + .open = simple_open, + .owner = THIS_MODULE, +}; + +static int tzprocfs_init(struct platform_device *pdev) +{ + int rc = 0; + struct proc_dir_entry *prEntry_tmp = NULL; + struct proc_dir_entry *prEntry_dir = NULL; + + prEntry_dir = proc_mkdir("tzdbg", NULL); + + if (prEntry_dir == NULL) { + dev_err(&pdev->dev, "tzdbg procfs_create_dir failed\n"); + return -ENOMEM; + } + + prEntry_tmp = proc_create("qsee_log", 0666, + prEntry_dir, &proc_qsee_log_fops); + + if (prEntry_tmp == NULL) { + dev_err(&pdev->dev, "TZ procfs_create_file qsee_log failed\n"); + rc = -ENOMEM; + goto err; + } + + prEntry_tmp = proc_create("tz_log", 0666, + prEntry_dir, &proc_tz_log_fops); + + if (prEntry_tmp == NULL) { + dev_err(&pdev->dev, "TZ procfs_create_file tz_log failed\n"); + rc = -ENOMEM; + goto err; + } + + return 0; +err: + proc_remove(prEntry_dir); + + return rc; +} + + static int tzdbgfs_init(struct platform_device *pdev) { int rc = 0; @@ -1099,6 +1197,11 @@ static int tz_log_probe(struct platform_device *pdev) if (tzdbgfs_init(pdev)) goto err; + //add tz and qsee log to logkit + if (tzprocfs_init(pdev)) + goto err; + + tzdbg_register_qsee_log_buf(pdev); tzdbg_get_tz_version(); diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 9317f66d4845..9a3ba3047b0b 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -245,8 +245,6 @@ source "drivers/gpu/drm/msm/Kconfig" source "drivers/gpu/drm/msm-hyp/Kconfig" -source "drivers/gpu/drm/msm-lease/Kconfig" - source "drivers/gpu/drm/fsl-dcu/Kconfig" source "drivers/gpu/drm/tegra/Kconfig" diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 74efa90f4742..e6ef7a7c1139 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -85,7 +85,6 @@ obj-$(CONFIG_DRM_BOCHS) += bochs/ obj-$(CONFIG_DRM_VIRTIO_GPU) += virtio/ obj-$(CONFIG_DRM_MSM) += msm/ obj-$(CONFIG_DRM_MSM_HYP) += msm-hyp/ -obj-$(CONFIG_DRM_MSM_LEASE) += msm-lease/ obj-$(CONFIG_DRM_TEGRA) += tegra/ obj-$(CONFIG_DRM_STM) += stm/ obj-$(CONFIG_DRM_STI) += sti/ diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h index fbc3f308fa19..1e86b08a7ea3 100644 --- a/drivers/gpu/drm/drm_internal.h +++ b/drivers/gpu/drm/drm_internal.h @@ -106,6 +106,67 @@ int drm_gem_open_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); void drm_gem_open(struct drm_device *dev, struct drm_file *file_private); void drm_gem_release(struct drm_device *dev, struct drm_file *file_private); +int dsi_display_set_hbm_mode(struct drm_connector *connector, int level); +int dsi_display_get_hbm_mode(struct drm_connector *connector); + + +int dsi_display_get_serial_number(struct drm_connector *connector); +int dsi_display_get_serial_number_year(struct drm_connector *connector); +int dsi_display_get_serial_number_mon(struct drm_connector *connector); +int dsi_display_get_serial_number_day(struct drm_connector *connector); +int dsi_display_get_serial_number_hour(struct drm_connector *connector); +int dsi_display_get_serial_number_min(struct drm_connector *connector); +int dsi_display_set_acl_mode(struct drm_connector *connector, int level); +int dsi_display_get_acl_mode(struct drm_connector *connector); +int dsi_display_set_hbm_mode(struct drm_connector *connector, int level); +int dsi_display_get_hbm_mode(struct drm_connector *connector); +int dsi_display_set_hbm_brightness(struct drm_connector *connector, int level); +int dsi_display_get_hbm_brightness(struct drm_connector *connector); +int dsi_display_set_aod_mode(struct drm_connector *connector, int level); +int dsi_display_get_aod_mode(struct drm_connector *connector); +int dsi_display_set_dci_p3_mode(struct drm_connector *connector, int level); +int dsi_display_get_dci_p3_mode(struct drm_connector *connector); +int dsi_display_set_night_mode(struct drm_connector *connector, int level); +int dsi_display_get_night_mode(struct drm_connector *connector); +int dsi_display_get_serial_number(struct drm_connector *connector); +int dsi_display_get_serial_number_year(struct drm_connector *connector); +int dsi_display_get_serial_number_mon(struct drm_connector *connector); +int dsi_display_get_serial_number_day(struct drm_connector *connector); +int dsi_display_get_serial_number_hour(struct drm_connector *connector); +int dsi_display_get_serial_number_min(struct drm_connector *connector); +int dsi_display_get_serial_number_sec(struct drm_connector *connector); +uint64_t dsi_display_get_serial_number_id(uint64_t serial_number); +int dsi_display_get_code_info(struct drm_connector *connector); +int dsi_display_get_stage_info(struct drm_connector *connector); +int dsi_display_get_production_info(struct drm_connector *connector); +int dsi_display_panel_mismatch_check(struct drm_connector *connector); +int dsi_display_panel_mismatch(struct drm_connector *connector); +int dsi_display_set_aod_disable(struct drm_connector *connector, int disable); +int dsi_display_get_aod_disable(struct drm_connector *connector); +int dsi_display_set_fp_hbm_mode(struct drm_connector *connector, int level); +int dsi_display_get_fp_hbm_mode(struct drm_connector *connector); +int dsi_display_update_dsi_on_command(struct drm_connector *connector, const char *buf, size_t count); +int dsi_display_get_dsi_on_command(struct drm_connector *connector, char *buf); +int dsi_display_update_dsi_panel_command(struct drm_connector *connector, const char *buf, size_t count); +int dsi_display_get_dsi_panel_command(struct drm_connector *connector, char *buf); +int dsi_display_update_dsi_seed_command(struct drm_connector *connector, const char *buf, size_t count); +int dsi_display_get_dsi_seed_command(struct drm_connector *connector, char *buf); +int dsi_display_set_native_display_p3_mode(struct drm_connector *connector, int level); +int dsi_display_get_native_display_p3_mode(struct drm_connector *connector); +int dsi_display_set_native_display_wide_color_mode(struct drm_connector *connector, int level); +int dsi_display_get_native_display_wide_color_mode(struct drm_connector *connector); +int dsi_display_set_native_display_srgb_color_mode(struct drm_connector *connector, int level); +int dsi_display_get_native_display_srgb_color_mode(struct drm_connector *connector); +int dsi_display_set_native_loading_effect_mode(struct drm_connector *connector, int level); +int dsi_display_get_native_display_loading_effect_mode(struct drm_connector *connector); +int dsi_display_set_customer_srgb_mode(struct drm_connector *connector, int level); +int dsi_display_set_customer_p3_mode(struct drm_connector *connector, int level); +int dsi_display_get_customer_srgb_mode(struct drm_connector *connector); +int dsi_display_get_customer_p3_mode(struct drm_connector *connector); + + + + /* drm_debugfs.c drm_debugfs_crc.c */ #if defined(CONFIG_DEBUG_FS) diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c index 0746ac89fcc5..e5621b91bac0 100644 --- a/drivers/gpu/drm/drm_mipi_dsi.c +++ b/drivers/gpu/drm/drm_mipi_dsi.c @@ -561,8 +561,8 @@ EXPORT_SYMBOL(mipi_dsi_set_maximum_return_packet_size); * Return: The number of bytes transmitted on success or a negative error code * on failure. */ -ssize_t mipi_dsi_generic_write(struct mipi_dsi_device *dsi, const void *payload, - size_t size) +ssize_t mipi_dsi_generic_write(struct mipi_dsi_device *dsi, void *payload, + size_t size) { struct mipi_dsi_msg msg = { .channel = dsi->channel, @@ -606,8 +606,9 @@ EXPORT_SYMBOL(mipi_dsi_generic_write); * Return: The number of bytes successfully read or a negative error code on * failure. */ -ssize_t mipi_dsi_generic_read(struct mipi_dsi_device *dsi, const void *params, - size_t num_params, void *data, size_t size) +ssize_t mipi_dsi_generic_read(struct mipi_dsi_device *dsi, void *params, + size_t num_params, void *data, size_t size) + { struct mipi_dsi_msg msg = { .channel = dsi->channel, @@ -651,7 +652,8 @@ EXPORT_SYMBOL(mipi_dsi_generic_read); * code on failure. */ ssize_t mipi_dsi_dcs_write_buffer(struct mipi_dsi_device *dsi, - const void *data, size_t len) + void *data, size_t len) + { struct mipi_dsi_msg msg = { .channel = dsi->channel, @@ -1093,6 +1095,43 @@ int mipi_dsi_dcs_get_display_brightness(struct mipi_dsi_device *dsi, } EXPORT_SYMBOL(mipi_dsi_dcs_get_display_brightness); +/** + * mipi_dsi_dcs_set_display_brightness_samsung() - sets the brightness value of the + * display + * @dsi: DSI peripheral device + * @brightness: brightness value + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_dcs_set_display_brightness_samsung(struct mipi_dsi_device *dsi, + u16 brightness) +{ + u8 payload[2] = {brightness >> 8, brightness & 0xff}; + ssize_t err; + + err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, + payload, sizeof(payload)); + if (err < 0) + return err; + + return 0; +} +EXPORT_SYMBOL(mipi_dsi_dcs_set_display_brightness_samsung); + +int mipi_dsi_dcs_write_c1(struct mipi_dsi_device *dsi, + u16 read_number) +{ + u8 payload[3] = {0x0A, read_number >> 8, read_number & 0xff}; + ssize_t err; + + err = mipi_dsi_dcs_write(dsi, 0xC1,payload, sizeof(payload)); + if (err < 0) + return err; + + return 0; +} +EXPORT_SYMBOL(mipi_dsi_dcs_write_c1); + static int mipi_dsi_drv_probe(struct device *dev) { struct mipi_dsi_driver *drv = to_mipi_dsi_driver(dev->driver); diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c index 1c5b5ce1fd7f..479c15ab4cba 100644 --- a/drivers/gpu/drm/drm_sysfs.c +++ b/drivers/gpu/drm/drm_sysfs.c @@ -21,10 +21,23 @@ #include #include #include "drm_internal.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include #define to_drm_minor(d) dev_get_drvdata(d) #define to_drm_connector(d) dev_get_drvdata(d) +#define DSI_PANEL_SAMSUNG_S6E3HC2 0 +#define DSI_PANEL_SAMSUNG_S6E3FC2X01 1 +extern char gamma_para[2][413]; +extern char dsi_panel_name; /** * DOC: overview * @@ -43,6 +56,10 @@ static struct device_type drm_sysfs_device_minor = { .name = "drm_minor" }; +static struct input_dev *dc_mode_input_dev; +static struct proc_dir_entry *prEntry_dc; +static int dc_mode_report_enable; + struct class *drm_class; static char *drm_devnode(struct device *dev, umode_t *mode) @@ -52,6 +69,71 @@ static char *drm_devnode(struct device *dev, umode_t *mode) static CLASS_ATTR_STRING(version, S_IRUGO, "drm 1.1.0 20060810"); +static ssize_t dc_mode_event_num_read(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) +{ + int ret = 0; + const char *devname = NULL; + struct input_handle *handle; + + if (!dc_mode_input_dev) + return count; + + list_for_each_entry(handle, &(dc_mode_input_dev->h_list), d_node) { + if (strncmp(handle->name, "event", 5) == 0) { + devname = handle->name; + break; + } + } + ret = simple_read_from_buffer(user_buf, count, ppos, devname, strlen(devname)); + return ret; +} + +static const struct file_operations dc_mode_event_num_fops = { + .read = dc_mode_event_num_read, + .open = simple_open, + .owner = THIS_MODULE, +}; + +static ssize_t dc_mode_report_enable_read(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) +{ + ssize_t ret = 0; + char page[4]; + + pr_info("the dc_mode_report_enable is: %d\n", dc_mode_report_enable); + ret = snprintf(page, 4, "%d\n", dc_mode_report_enable); + ret = simple_read_from_buffer(user_buf, count, ppos, page, strlen(page)); + return ret; + +} + +static ssize_t dc_mode_report_enable_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos) +{ + char buf[8] = {0}; + + if (count > 2) + count = 2; + + if (copy_from_user(buf, buffer, count)) { + pr_err("%s: read proc input error.\n", __func__); + return count; + } + + if ('0' == buf[0]) + dc_mode_report_enable = 0; + else if ('1' == buf[0]) + dc_mode_report_enable = 1; + + + return count; +} + +static const struct file_operations dc_mode_report_enable_fops = { + .read = dc_mode_report_enable_read, + .write = dc_mode_report_enable_write, + .open = simple_open, + .owner = THIS_MODULE, +}; + /** * drm_sysfs_init - initialize sysfs helpers * @@ -65,6 +147,7 @@ static CLASS_ATTR_STRING(version, S_IRUGO, "drm 1.1.0 20060810"); int drm_sysfs_init(void) { int err; + struct proc_dir_entry *prEntry_tmp = NULL; drm_class = class_create(THIS_MODULE, "drm"); if (IS_ERR(drm_class)) @@ -76,8 +159,48 @@ int drm_sysfs_init(void) drm_class = NULL; return err; } - drm_class->devnode = drm_devnode; + + prEntry_dc = proc_mkdir("dc_for_sensor", NULL); + if (prEntry_dc == NULL) { + pr_err("Couldn't create dc_for_sensor directory\n"); + return 0; + } + + //create dc_mode_event_num + prEntry_tmp = proc_create("dc_mode_event_num", 0664, + prEntry_dc, &dc_mode_event_num_fops); + if (prEntry_tmp == NULL) { + pr_err("Couldn't create dc_mode_event_num_fops\n"); + return 0; + } + + //create dc_mode_report_enable + prEntry_tmp = proc_create("dc_mode_report_enable", 0666, + prEntry_dc, &dc_mode_report_enable_fops); + if (prEntry_tmp == NULL) { + pr_err("Couldn't create dc_mode_report_enable_fops\n"); + return 0; + } + + //create input event + dc_mode_input_dev = input_allocate_device(); + if (dc_mode_input_dev == NULL) { + pr_err("Failed to allocate dc mode input device\n"); + return 0; + } + + dc_mode_input_dev->name = "oneplus,dc_mode"; + + set_bit(EV_MSC, dc_mode_input_dev->evbit); + set_bit(MSC_RAW, dc_mode_input_dev->mscbit); + + if (input_register_device(dc_mode_input_dev)) { + pr_err("%s: Failed to register dc mode input device\n", __func__); + input_free_device(dc_mode_input_dev); + return 0; + } + return 0; } @@ -88,6 +211,9 @@ int drm_sysfs_init(void) */ void drm_sysfs_destroy(void) { + input_unregister_device(dc_mode_input_dev); + input_free_device(dc_mode_input_dev); + if (IS_ERR_OR_NULL(drm_class)) return; class_remove_file(drm_class, &class_attr_version.attr); @@ -228,17 +354,962 @@ static ssize_t modes_show(struct device *device, return written; } +static ssize_t acl_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int acl_mode = 0; + + acl_mode = dsi_display_get_acl_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "acl mode = %d\n" + "0--acl mode(off)\n" + "1--acl mode(5)\n" + "2--acl mode(10)\n" + "3--acl mode(15)\n", + acl_mode); + return ret; +} + +static ssize_t acl_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int acl_mode = 0; + + ret = kstrtoint(buf, 10, &acl_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_acl_mode(connector, acl_mode); + if (ret) + pr_err("set acl mode(%d) fail\n", acl_mode); + + return count; +} +static ssize_t hbm_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int hbm_mode = 0; + + hbm_mode = dsi_display_get_hbm_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "hbm mode = %d\n" + "0--hbm mode(off)\n" + "1--hbm mode(XX)\n" + "2--hbm mode(XX)\n" + "3--hbm mode(XX)\n" + "4--hbm mode(XX)\n" + "5--hbm mode(670)\n", + hbm_mode); + return ret; +} + +static ssize_t hbm_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int hbm_mode = 0; + + ret = kstrtoint(buf, 10, &hbm_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_hbm_mode(connector, hbm_mode); + if (ret) + pr_err("set hbm mode(%d) fail\n", hbm_mode); + + return count; +} + +static ssize_t hbm_brightness_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int hbm_brightness = 0; + + hbm_brightness = dsi_display_get_hbm_brightness(connector); + + ret = scnprintf(buf, PAGE_SIZE, "%d\n", hbm_brightness); + return ret; +} + +static ssize_t hbm_brightness_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int hbm_brightness = 0; + + ret = kstrtoint(buf, 10, &hbm_brightness); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + ret = dsi_display_set_hbm_brightness(connector, hbm_brightness); + if (ret) + pr_err("set hbm brightness (%d) failed\n", hbm_brightness); + return count; +} + +static ssize_t op_friginer_print_hbm_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int op_hbm_mode = 0; + + op_hbm_mode = dsi_display_get_fp_hbm_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "OP_FP mode = %d\n" + "0--finger-hbm mode(off)\n" + "1--finger-hbm mode(600)\n", + op_hbm_mode); + return ret; +} + +static ssize_t op_friginer_print_hbm_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int op_hbm_mode = 0; + + ret = kstrtoint(buf, 10, &op_hbm_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_fp_hbm_mode(connector, op_hbm_mode); + if (ret) + pr_err("set hbm mode(%d) fail\n", op_hbm_mode); + + return count; +} + +static ssize_t aod_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int aod_mode = 0; + + aod_mode = dsi_display_get_aod_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "%d\n", aod_mode); + return ret; +} + +static ssize_t aod_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int aod_mode = 0; + + ret = kstrtoint(buf, 10, &aod_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + ret = dsi_display_set_aod_mode(connector, aod_mode); + if (ret) + pr_err("set AOD mode(%d) fail\n", aod_mode); + return count; +} + +static ssize_t aod_disable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int aod_disable = 0; + + aod_disable = dsi_display_get_aod_disable(connector); + + ret = scnprintf(buf, PAGE_SIZE, "AOD disable = %d\n" + "0--AOD enable\n" + "1--AOD disable\n", + aod_disable); + return ret; +} + +static ssize_t aod_disable_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int aod_disable = 0; + + ret = kstrtoint(buf, 10, &aod_disable); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_aod_disable(connector, aod_disable); + if (ret) + pr_err("set AOD disable(%d) fail\n", aod_disable); + + return count; +} + +static ssize_t DCI_P3_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int dci_p3_mode = 0; + + dci_p3_mode = dsi_display_get_dci_p3_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "dci-p3 mode = %d\n" + "0--dci-p3 mode Off\n" + "1--dci-p3 mode On\n", + dci_p3_mode); + return ret; +} + +static ssize_t DCI_P3_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int dci_p3_mode = 0; + + ret = kstrtoint(buf, 10, &dci_p3_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_dci_p3_mode(connector, dci_p3_mode); + if (ret) { + pr_err("set dci-p3 mode(%d) fail\n", dci_p3_mode); + } + return count; +} + +static ssize_t night_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int night_mode = 0; + + night_mode = dsi_display_get_night_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "night mode = %d\n" + "0--night mode Off\n" + "1--night mode On\n", + night_mode); + return ret; +} + +static ssize_t night_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int night_mode = 0; + + ret = kstrtoint(buf, 10, &night_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_night_mode(connector, night_mode); + if (ret) { + pr_err("set night mode(%d) fail\n", night_mode); + } + return count; +} + +static ssize_t native_display_p3_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_p3_mode = 0; + + native_display_p3_mode = dsi_display_get_native_display_p3_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "native display p3 mode = %d\n" + "0--native display p3 mode Off\n" + "1--native display p3 mode On\n", + native_display_p3_mode); + return ret; +} + +static ssize_t native_display_p3_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_p3_mode = 0; + + ret = kstrtoint(buf, 10, &native_display_p3_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_native_display_p3_mode(connector, native_display_p3_mode); + if (ret) { + pr_err("set native_display_p3 mode(%d) fail\n", native_display_p3_mode); + } + return count; +} +static ssize_t native_display_wide_color_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_wide_color_mode = 0; + + native_display_wide_color_mode = dsi_display_get_native_display_wide_color_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "native display wide color mode = %d\n" + "0--native display wide color mode Off\n" + "1--native display wide color mode On\n", + native_display_wide_color_mode); + return ret; +} + +static ssize_t native_display_loading_effect_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_loading_effect_mode = 0; + + ret = kstrtoint(buf, 10, &native_display_loading_effect_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_native_loading_effect_mode(connector, native_display_loading_effect_mode); + if (ret) { + pr_err("set loading effect mode(%d) fail\n", native_display_loading_effect_mode); + } + return count; +} + +static ssize_t native_display_loading_effect_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_loading_effect_mode = 0; + + native_display_loading_effect_mode = dsi_display_get_native_display_loading_effect_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "native display loading effect mode = %d\n" + "0--native display loading effect mode Off\n" + "1--native display loading effect mode On\n", + native_display_loading_effect_mode); + return ret; +} + +static ssize_t native_display_customer_p3_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_customer_p3_mode = 0; + + ret = kstrtoint(buf, 10, &native_display_customer_p3_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_customer_p3_mode(connector, native_display_customer_p3_mode); + if (ret) { + pr_err("set customer p3 mode(%d) fail\n", native_display_customer_p3_mode); + } + return count; +} + +static ssize_t native_display_customer_p3_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_customer_p3_mode = 0; + + native_display_customer_p3_mode = dsi_display_get_customer_p3_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "native display customer p3 mode = %d\n" + "0--native display customer p3 mode Off\n" + "1--native display customer p3 mode On\n", + native_display_customer_p3_mode); + return ret; +} +static ssize_t native_display_customer_srgb_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_customer_srgb_mode = 0; + + ret = kstrtoint(buf, 10, &native_display_customer_srgb_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_customer_srgb_mode(connector, native_display_customer_srgb_mode); + if (ret) { + pr_err("set customer srgb mode(%d) fail\n", native_display_customer_srgb_mode); + } + return count; +} + +static ssize_t native_display_customer_srgb_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_customer_srgb_mode = 0; + + native_display_customer_srgb_mode = dsi_display_get_customer_srgb_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "native display customer srgb mode = %d\n" + "0--native display customer srgb mode Off\n" + "1--native display customer srgb mode On\n", + native_display_customer_srgb_mode); + return ret; +} + + +static ssize_t native_display_wide_color_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_wide_color_mode = 0; + + ret = kstrtoint(buf, 10, &native_display_wide_color_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_native_display_wide_color_mode(connector, native_display_wide_color_mode); + if (ret) { + pr_err("set native_display_p3 mode(%d) fail\n", native_display_wide_color_mode); + } + return count; +} + +static ssize_t native_display_srgb_color_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_srgb_color_mode = 0; + + native_display_srgb_color_mode = dsi_display_get_native_display_srgb_color_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "native display srgb color mode = %d\n" + "0--native display srgb color mode Off\n" + "1--native display srgb color mode On\n", + native_display_srgb_color_mode); + return ret; +} + +static ssize_t native_display_srgb_color_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_srgb_color_mode = 0; + + ret = kstrtoint(buf, 10, &native_display_srgb_color_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_native_display_srgb_color_mode(connector, native_display_srgb_color_mode); + if (ret) { + pr_err("set native_display_srgb mode(%d) fail\n", native_display_srgb_color_mode); + } + return count; +} + +static ssize_t gamma_test_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int gamma_test_flag = 0; + int panel_stage_info = 0; + int pvt_mp_panel_flag = 0; + + if (dsi_panel_name == DSI_PANEL_SAMSUNG_S6E3HC2) { + if ((gamma_para[0][18] == 0xFF) && (gamma_para[0][19] == 0xFF) && (gamma_para[0][20] == 0xFF)) { + gamma_test_flag = 0; + } + else { + gamma_test_flag = 1; + } + + panel_stage_info = dsi_display_get_stage_info(connector); + if ((0x07 == panel_stage_info) || (0x10 == panel_stage_info) || (0x11 == panel_stage_info)) { + pvt_mp_panel_flag = 1; + } + else { + pvt_mp_panel_flag = 0; + } + + ret = scnprintf(buf, PAGE_SIZE, "%d\n", (gamma_test_flag << 1) + pvt_mp_panel_flag); + return ret; + } + else { + ret = scnprintf(buf, PAGE_SIZE, "%d\n", 3); + pr_err("It is not S6E3HC2 panel!\n"); + return ret; + } +} + +static ssize_t panel_serial_number_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int panel_year = 0; + int panel_mon = 0; + int panel_day = 0; + int panel_hour = 0; + int panel_min = 0; + int panel_sec = 0; + int panel_code_info = 0; + int panel_stage_info = 0; + int panel_production_info = 0; + char * production_string_info = NULL; + char * stage_string_info = NULL; + int ret = 0; + + dsi_display_get_serial_number(connector); + + panel_year = dsi_display_get_serial_number_year(connector); + panel_mon = dsi_display_get_serial_number_mon(connector); + panel_day = dsi_display_get_serial_number_day(connector); + panel_hour = dsi_display_get_serial_number_hour(connector); + panel_min = dsi_display_get_serial_number_min(connector); + panel_sec = dsi_display_get_serial_number_sec(connector); + panel_code_info = dsi_display_get_code_info(connector); + panel_stage_info = dsi_display_get_stage_info(connector); + panel_production_info = dsi_display_get_production_info(connector); + + if (dsi_panel_name == DSI_PANEL_SAMSUNG_S6E3HC2) { + if (panel_code_info == 0xED) { + if (panel_stage_info == 0x02) + stage_string_info = "STAGE: EVT2"; + else if (panel_stage_info == 0x03) + stage_string_info = "STAGE: EVT2(NEW_DIMMING_SET)"; + else if (panel_stage_info == 0x99) + stage_string_info = "STAGE: EVT2(113MHZ_OSC)"; + else if (panel_stage_info == 0x04) + stage_string_info = "STAGE: DVT1"; + else if (panel_stage_info == 0x05) + stage_string_info = "STAGE: DVT2"; + else if (panel_stage_info == 0x06) + stage_string_info = "STAGE: DVT3"; + else if (panel_stage_info == 0x07) + stage_string_info = "STAGE: PVT(112MHZ_OSC)"; + else if (panel_stage_info == 0x10) + stage_string_info = "STAGE: PVT(113MHZ_OSC)"; + else if (panel_stage_info == 0x11) + stage_string_info = "STAGE: PVT(113MHZ_OSC+X_TALK_IMPROVEMENT)"; + else + stage_string_info = "STAGE: UNKNOWN"; + + if (panel_production_info == 0x0C) + production_string_info = "TPIC: LSI\nCOVER: JNTC\nOTP_GAMMA: 90HZ"; + else if (panel_production_info == 0x0E) + production_string_info = "TPIC: LSI\nCOVER: LENS\nOTP_GAMMA: 90HZ"; + else if (panel_production_info == 0x1C) + production_string_info = "TPIC: STM\nCOVER: JNTC\nOTP_GAMMA: 90HZ"; + else if (panel_production_info == 0x6C) + production_string_info = "TPIC: LSI\nCOVER: JNTC\nOTP_GAMMA: 60HZ"; + else if (panel_production_info == 0x6E) + production_string_info = "TPIC: LSI\nCOVER: LENS\nOTP_GAMMA: 60HZ"; + else if (panel_production_info == 0x1E) + production_string_info = "TPIC: STM\nCOVER: LENS\nOTP_GAMMA: 90HZ"; + else if (panel_production_info == 0x0D) + production_string_info = "TPIC: LSI\nID3: 0x0D\nOTP_GAMMA: 90HZ"; + else + production_string_info = "TPIC: UNKNOWN\nCOVER: UNKNOWN\nOTP_GAMMA: UNKNOWN"; + + ret = scnprintf(buf, PAGE_SIZE, "%04d/%02d/%02d %02d:%02d:%02d\n%s\n%s\nID: %02X %02X %02X\n", + panel_year, panel_mon, panel_day, panel_hour, panel_min, panel_sec, + stage_string_info, production_string_info, panel_code_info, + panel_stage_info, panel_production_info); + } + } else { + ret = scnprintf(buf, PAGE_SIZE, "%04d/%02d/%02d %02d:%02d:%02d\n", + panel_year, panel_mon, panel_day, panel_hour, panel_min, panel_sec); + } + + pr_err("panel year = %d, mon = %d, day = %d, hour = %d, min = %d\n", + panel_year, panel_mon, panel_day, panel_hour, panel_min); + + return ret; +} + +static ssize_t panel_serial_number_AT_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + + int ret = 0; + uint64_t serial_number = 0; + + ret = scnprintf(buf, PAGE_SIZE, "%llu\n",dsi_display_get_serial_number_id(serial_number)); + + return ret; +} + +static ssize_t dsi_on_command_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + + ret = dsi_display_get_dsi_on_command(connector, buf); + + return ret; +} + +static ssize_t dsi_on_command_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + + ret = dsi_display_update_dsi_on_command(connector, buf, count); + if (ret) + pr_err("Failed to update dsi on command, ret=%d\n", ret); + + return count; +} + +static ssize_t dsi_panel_command_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + + ret = dsi_display_get_dsi_panel_command(connector, buf); + + return ret; +} + +static ssize_t dsi_panel_command_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + + ret = dsi_display_update_dsi_panel_command(connector, buf, count); + if (ret) + pr_err("Failed to update dsi panel command, ret=%d\n", ret); + + return count; +} + +static ssize_t dsi_seed_command_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + + ret = dsi_display_get_dsi_seed_command(connector, buf); + + return ret; +} + +static ssize_t dsi_seed_command_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + + ret = dsi_display_update_dsi_seed_command(connector, buf, count); + if (ret) + pr_err("Failed to update dsi seed command, ret=%d\n", ret); + + return count; +} + +int current_freq = 0; +static ssize_t dynamic_dsitiming_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret = 0; + + ret = scnprintf(buf, PAGE_SIZE, "current_freq = %d\n", + current_freq); + return ret; +} + +static ssize_t dynamic_dsitiming_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + int ret = 0; + int freq_value = 0; + + ret = kstrtoint(buf, 10, &freq_value); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + current_freq = freq_value; + + pr_err("freq setting=%d\n", current_freq); + + if (ret) { + pr_err("set dsi freq (%d) fail\n", current_freq); + } + return count; +} + +extern u32 mode_fps; +static ssize_t dynamic_fps_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret = 0; + + ret = scnprintf(buf, PAGE_SIZE, "%d\n", mode_fps); + + return ret; +} + +static ssize_t panel_mismatch_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int wrong_panel = 0; + + dsi_display_panel_mismatch_check(connector); + + wrong_panel = dsi_display_panel_mismatch(connector); + ret = scnprintf(buf, PAGE_SIZE, "panel mismatch = %d\n" + "0--(panel match)\n" + "1--(panel mismatch)\n", + wrong_panel); + return ret; +} + +int oneplus_panel_alpha =0; +int oneplus_force_screenfp = 0; +int op_dimlayer_bl_enable = 0; +int op_dp_enable = 0; +int op_dither_enable = 0; +extern int oneplus_get_panel_brightness_to_alpha(void); + +static ssize_t oneplus_display_get_dim_alpha(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", oneplus_get_panel_brightness_to_alpha()); +} + +static ssize_t oneplus_display_set_dim_alpha(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + sscanf(buf, "%d", &oneplus_panel_alpha); + return count; +} + +static ssize_t oneplus_display_get_forcescreenfp(struct device *dev, + struct device_attribute *attr, char *buf) +{ + + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + oneplus_force_screenfp = dsi_display_get_fp_hbm_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "OP_FP mode = %d\n" + "0--finger-hbm mode(off)\n" + "1--finger-hbm mode(600)\n", + oneplus_force_screenfp); + return sprintf(buf, "%d\n", oneplus_force_screenfp); + +} + +static ssize_t oneplus_display_set_forcescreenfp(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + //sscanf(buf, "%x", &oneplus_force_screenfp); + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + ret = kstrtoint(buf, 10, &oneplus_force_screenfp); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_fp_hbm_mode(connector, oneplus_force_screenfp); + if (ret) + pr_err("set hbm mode(%d) fail\n", oneplus_force_screenfp); + return count; +} + + +static ssize_t op_display_get_dimlayer_enable(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", op_dimlayer_bl_enable); +} + +static ssize_t op_display_set_dimlayer_enable(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + sscanf(buf, "%d", &op_dimlayer_bl_enable); + + pr_err("op_dimlayer_bl_enable : %d\n", op_dimlayer_bl_enable); + + if (dc_mode_report_enable) { + input_event(dc_mode_input_dev, EV_MSC, MSC_RAW, op_dimlayer_bl_enable); + input_sync(dc_mode_input_dev); + } + + return count; +} + +static ssize_t op_display_get_dither_enable(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", op_dither_enable); +} + +static ssize_t op_display_set_dither_enable(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + sscanf(buf, "%d", &op_dither_enable); + + return count; +} + +static ssize_t op_display_get_dp_enable(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", op_dp_enable); +} + +static ssize_t op_display_set_dp_enable(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + sscanf(buf, "%d", &op_dp_enable); + + return count; +} + +extern ssize_t oneplus_display_notify_fp_press(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count); + +extern ssize_t oneplus_display_notify_dim(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count); + +extern ssize_t oneplus_display_notify_aod_hid(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count); static DEVICE_ATTR_RW(status); static DEVICE_ATTR_RO(enabled); static DEVICE_ATTR_RO(dpms); static DEVICE_ATTR_RO(modes); +static DEVICE_ATTR_RW(acl); +static DEVICE_ATTR_RW(hbm); +static DEVICE_ATTR_RW(hbm_brightness); +static DEVICE_ATTR_RW(op_friginer_print_hbm); +static DEVICE_ATTR_RW(aod); +static DEVICE_ATTR_RW(aod_disable); +static DEVICE_ATTR_RW(DCI_P3); +static DEVICE_ATTR_RW(night_mode); +static DEVICE_ATTR_RW(native_display_p3_mode); +static DEVICE_ATTR_RW(native_display_wide_color_mode); +static DEVICE_ATTR_RW(native_display_loading_effect_mode); +static DEVICE_ATTR_RW(native_display_srgb_color_mode); +static DEVICE_ATTR_RW(native_display_customer_p3_mode); +static DEVICE_ATTR_RW(native_display_customer_srgb_mode); +static DEVICE_ATTR_RO(gamma_test); +static DEVICE_ATTR_RO(panel_serial_number); +static DEVICE_ATTR_RO(panel_serial_number_AT); +static DEVICE_ATTR_RW(dsi_on_command); +static DEVICE_ATTR_RW(dsi_panel_command); +static DEVICE_ATTR_RW(dsi_seed_command); +static DEVICE_ATTR_RW(dynamic_dsitiming); +static DEVICE_ATTR_RO(panel_mismatch); +static DEVICE_ATTR_RO(dynamic_fps); +static DEVICE_ATTR(dim_alpha, S_IRUGO|S_IWUSR, oneplus_display_get_dim_alpha, oneplus_display_set_dim_alpha); +static DEVICE_ATTR(force_screenfp, S_IRUGO|S_IWUSR, oneplus_display_get_forcescreenfp, oneplus_display_set_forcescreenfp); +static DEVICE_ATTR(notify_fppress, S_IRUGO|S_IWUSR, NULL, oneplus_display_notify_fp_press); +static DEVICE_ATTR(notify_dim, S_IRUGO|S_IWUSR, NULL, oneplus_display_notify_dim); +static DEVICE_ATTR(notify_aod, S_IRUGO|S_IWUSR, NULL, oneplus_display_notify_aod_hid); +static DEVICE_ATTR(dimlayer_bl_en, S_IRUGO|S_IWUSR, op_display_get_dimlayer_enable, op_display_set_dimlayer_enable); +static DEVICE_ATTR(dp_en, S_IRUGO|S_IWUSR, op_display_get_dp_enable, op_display_set_dp_enable); +static DEVICE_ATTR(dither_en, S_IRUGO|S_IWUSR, op_display_get_dither_enable, op_display_set_dither_enable); static struct attribute *connector_dev_attrs[] = { &dev_attr_status.attr, &dev_attr_enabled.attr, &dev_attr_dpms.attr, &dev_attr_modes.attr, + &dev_attr_acl.attr, + &dev_attr_hbm.attr, + &dev_attr_hbm_brightness.attr, + &dev_attr_op_friginer_print_hbm.attr, + &dev_attr_aod.attr, + &dev_attr_aod_disable.attr, + &dev_attr_DCI_P3.attr, + &dev_attr_night_mode.attr, + &dev_attr_native_display_p3_mode.attr, + &dev_attr_native_display_wide_color_mode.attr, + &dev_attr_native_display_loading_effect_mode.attr, + &dev_attr_native_display_srgb_color_mode.attr, + &dev_attr_native_display_customer_p3_mode.attr, + &dev_attr_native_display_customer_srgb_mode.attr, + &dev_attr_gamma_test.attr, + &dev_attr_panel_serial_number.attr, + &dev_attr_panel_serial_number_AT.attr, + &dev_attr_dsi_on_command.attr, + &dev_attr_dsi_panel_command.attr, + &dev_attr_dsi_seed_command.attr, + &dev_attr_dynamic_dsitiming.attr, + &dev_attr_panel_mismatch.attr, + &dev_attr_force_screenfp.attr, + &dev_attr_dim_alpha.attr, + &dev_attr_dynamic_fps.attr, + &dev_attr_notify_fppress.attr, + &dev_attr_notify_dim.attr, + &dev_attr_notify_aod.attr, + &dev_attr_dimlayer_bl_en.attr, + &dev_attr_dp_en.attr, + &dev_attr_dither_en.attr, NULL }; diff --git a/drivers/gpu/drm/msm-lease/Kconfig b/drivers/gpu/drm/msm-lease/Kconfig deleted file mode 100644 index 5d4596d5ebd9..000000000000 --- a/drivers/gpu/drm/msm-lease/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -# -# Drm MSM lease configuration -# -# This driver provides support for the User Space DRM Masters -# -config DRM_MSM_LEASE - tristate "MSM DRM LEASE" - depends on DRM_MSM - help - DRM/KMS driver for MSM/snapdragon in lease mode. This driver - registers with DRM framework and creates virtual DRI cards at - /dev/dri/card, n=1,2,..., from DRM object names listed in - devicetree. When virtual card is opened, an internal DRM - object leasing will take place and return with the lessee FD. diff --git a/drivers/gpu/drm/msm-lease/Makefile b/drivers/gpu/drm/msm-lease/Makefile deleted file mode 100644 index d2aaa09bf51e..000000000000 --- a/drivers/gpu/drm/msm-lease/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -ccflags-$(CONFIG_DRM_MSM_LEASE) := -Iinclude/drm - -obj-$(CONFIG_DRM_MSM_LEASE) := \ - msm_lease_drv.o diff --git a/drivers/gpu/drm/msm-lease/msm_lease_drv.c b/drivers/gpu/drm/msm-lease/msm_lease_drv.c deleted file mode 100644 index 6534ae05c6ab..000000000000 --- a/drivers/gpu/drm/msm-lease/msm_lease_drv.c +++ /dev/null @@ -1,650 +0,0 @@ -/* Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2017 Keith Packard - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../drm_internal.h" - -#define MAX_LEASE_OBJECT_COUNT 64 - -static DEFINE_MUTEX(g_lease_mutex); -static LIST_HEAD(g_lease_list); -static int (*g_master_open)(struct drm_device *, struct drm_file *); -static void (*g_master_postclose)(struct drm_device *, struct drm_file *); -static const struct file_operations *g_master_ddev_fops; -static struct drm_master *g_master_ddev_master; -static struct kref g_master_ddev_master_ref; -static bool g_master_ddev_name_overridden; - -struct msm_lease { - struct device *dev; - struct drm_device *drm_dev; - struct drm_minor *minor; - struct drm_master *master; - struct list_head head; - u32 object_ids[MAX_LEASE_OBJECT_COUNT]; - int obj_cnt; - const char *dev_name; -}; - -static struct drm_driver msm_lease_driver; - -static inline struct msm_lease *_find_lease_from_minor(struct drm_minor *minor) -{ - struct msm_lease *lease; - - list_for_each_entry(lease, &g_lease_list, head) { - if (lease->minor == minor) - return lease; - } - - return NULL; -} - -static inline struct msm_lease *_find_lease_from_node(struct device_node *node) -{ - struct msm_lease *lease; - - list_for_each_entry(lease, &g_lease_list, head) { - if (lease->dev->of_node == node) - return lease; - } - - return NULL; -} - -static inline bool _find_obj_id(int id, u32 *object_ids, int object_count) -{ - int i; - - for (i = 0; i < object_count; i++) { - if (object_ids[i] == id) - return true; - } - - return false; -} - -static inline bool _obj_is_leased(int id, - u32 *object_ids, int object_count) -{ - struct msm_lease *lease; - - list_for_each_entry(lease, &g_lease_list, head) { - if (_find_obj_id(id, lease->object_ids, lease->obj_cnt)) - return true; - } - - return _find_obj_id(id, object_ids, object_count); -} - -static struct drm_master *msm_lease_get_dev_master(struct drm_device *dev) -{ - if (!g_master_ddev_master) { - mutex_lock(&dev->master_mutex); - - if (dev->master) { - DRM_ERROR("card0 master already opened\n"); - goto out; - } - - g_master_ddev_master = drm_master_create(dev); - if (!g_master_ddev_master) { - DRM_ERROR("failed to create dev master\n"); - goto out; - } - - dev->master = g_master_ddev_master; - kref_init(&g_master_ddev_master_ref); - -out: - mutex_unlock(&dev->master_mutex); - } else - kref_get(&g_master_ddev_master_ref); - - return g_master_ddev_master; -} - -static void msm_lease_destroy_dev_master(struct kref *kref) -{ - struct drm_device *dev = g_master_ddev_master->dev; - - mutex_lock(&dev->master_mutex); - drm_master_put(&dev->master); - mutex_unlock(&dev->master_mutex); - - g_master_ddev_master = NULL; -} - -static void msm_lease_put_dev_master(struct drm_device *dev) -{ - if (!g_master_ddev_master) { - DRM_ERROR("global master deosn't exist\n"); - return; - } - - kref_put(&g_master_ddev_master_ref, msm_lease_destroy_dev_master); -} - -static const char *msm_lease_get_dev_name(struct drm_file *file) -{ - struct msm_lease *lease; - const char *dev_name; - - mutex_lock(&g_lease_mutex); - - lease = _find_lease_from_minor(file->minor); - if (!lease || !lease->dev_name) { - if (file->minor->index == 0 && g_master_ddev_name_overridden) - dev_name = "n/a"; - else - dev_name = file->minor->dev->driver->name; - } else - dev_name = lease->dev_name; - - mutex_unlock(&g_lease_mutex); - return dev_name; -} - -static int msm_lease_open(struct drm_device *dev, struct drm_file *file) -{ - struct msm_lease *lease; - struct drm_master *lessee; - struct drm_master *dev_master; - struct idr leases; - int id, i, rc; - - rc = g_master_open(dev, file); - if (rc) - return rc; - - mutex_lock(&g_lease_mutex); - - lease = _find_lease_from_minor(file->minor); - if (!lease) - goto out; - - if (!lease->master) { - /* get device master */ - dev_master = msm_lease_get_dev_master(dev); - if (!dev_master) { - rc = -EBUSY; - goto out; - } - - /* create local idr */ - idr_init(&leases); - for (i = 0; i < lease->obj_cnt; i++) { - id = idr_alloc(&leases, lease, - lease->object_ids[i], - lease->object_ids[i] + 1, GFP_KERNEL); - if (id < 0) { - msm_lease_put_dev_master(dev); - DRM_ERROR("create idr failed\n"); - rc = id; - goto out; - } - } - - /* create lessee master */ - lessee = drm_master_create(dev); - if (!lessee) { - msm_lease_put_dev_master(dev); - DRM_ERROR("drm_master_create failed\n"); - idr_destroy(&leases); - rc = -ENOMEM; - goto out; - } - - /* create lessee id */ - mutex_lock(&dev->mode_config.idr_mutex); - id = idr_alloc(&dev_master->lessee_idr, - lessee, 1, 0, GFP_KERNEL); - if (id < 0) { - mutex_unlock(&dev->mode_config.idr_mutex); - msm_lease_put_dev_master(dev); - idr_destroy(&leases); - drm_master_put(&lessee); - rc = id; - goto out; - } - - /* init lessee */ - lessee->lessee_id = id; - lessee->lessor = drm_master_get(dev_master); - list_add_tail(&lessee->lessee_list, &dev_master->lessees); - lessee->leases = leases; - mutex_unlock(&dev->mode_config.idr_mutex); - - /* set file as master */ - file->master = lessee; - file->is_master = 1; - file->authenticated = 1; - lease->master = drm_master_get(lessee); - } else - file->master = drm_master_get(lease->master); - -out: - mutex_unlock(&g_lease_mutex); - - return rc; -} - -static void msm_lease_postclose(struct drm_device *dev, struct drm_file *file) -{ - struct msm_lease *lease; - - g_master_postclose(dev, file); - - mutex_lock(&g_lease_mutex); - - lease = _find_lease_from_minor(file->minor); - if (!lease) - goto out; - - if (drm_is_current_master(file)) { - drm_master_put(&lease->master); - msm_lease_put_dev_master(dev); - } - - drm_master_release(file); - -out: - mutex_unlock(&g_lease_mutex); -} - -static long msm_lease_ioctl(struct file *filp, - unsigned int cmd, unsigned long arg) -{ - if (cmd == DRM_IOCTL_VERSION) { - const char *dev_name; - struct drm_version v; - u32 name_len; - long err; - - dev_name = msm_lease_get_dev_name(filp->private_data); - if (!dev_name) - return -EFAULT; - - if (copy_from_user(&v, (void __user *)arg, sizeof(v))) - return -EFAULT; - - name_len = v.name_len; - - err = drm_ioctl_kernel(filp, drm_version, &v, - DRM_UNLOCKED|DRM_RENDER_ALLOW|DRM_CONTROL_ALLOW); - if (err) - return err; - - /* replace device name with card name */ - v.name_len = strlen(dev_name); - if (v.name_len < name_len) - name_len = v.name_len; - - if (v.name && name_len) - if (copy_to_user(v.name, dev_name, name_len)) - return -EFAULT; - - if (copy_to_user((void __user *)arg, &v, sizeof(v))) - return -EFAULT; - - return 0; - } - - return g_master_ddev_fops->unlocked_ioctl(filp, cmd, arg); -} - -static int msm_lease_add_connector(struct drm_device *dev, const char *name, - u32 *object_ids, int *object_count, struct drm_plane *primary) -{ - struct drm_connector *connector; - struct drm_encoder *encoder; - struct drm_crtc *crtc; - struct drm_connector_list_iter conn_iter; - int conn_id = -1, crtc_id = -1; - int rc = 0; - - if (*object_count >= MAX_LEASE_OBJECT_COUNT - 1) { - DRM_ERROR("too many objects added %d\n", *object_count); - return -EINVAL; - } - - mutex_lock(&dev->mode_config.mutex); - - drm_connector_list_iter_begin(dev, &conn_iter); - drm_for_each_connector_iter(connector, &conn_iter) { - if (!strcmp(connector->name, name)) { - conn_id = connector->base.id; - break; - } - } - drm_connector_list_iter_end(&conn_iter); - - if (conn_id < 0) { - DRM_ERROR("failed to find connector %s, defer...\n", name); - rc = -EPROBE_DEFER; - goto out; - } - - if (_obj_is_leased(conn_id, object_ids, *object_count)) { - DRM_ERROR("connector %s is already leased\n", name); - rc = -EBUSY; - goto out; - } - - encoder = drm_encoder_find(dev, NULL, connector->encoder_ids[0]); - if (!encoder) { - DRM_ERROR("failed to find encoder for %s, defer...\n", name); - rc = -EPROBE_DEFER; - goto out; - } - - drm_for_each_crtc(crtc, dev) { - if (!(encoder->possible_crtcs & drm_crtc_mask(crtc))) - continue; - - if (_obj_is_leased(crtc->base.id, object_ids, *object_count)) - continue; - - /* re-initialize crtc primary for legacy set_mode */ - crtc->primary = primary; - primary->crtc = crtc; - - crtc_id = crtc->base.id; - break; - } - - if (crtc_id < 0) { - DRM_ERROR("failed to find crtc for %s, defer...\n", name); - rc = -EPROBE_DEFER; - goto out; - } - - object_ids[(*object_count)++] = conn_id; - object_ids[(*object_count)++] = crtc_id; - -out: - mutex_unlock(&dev->mode_config.mutex); - - return rc; -} - -static int msm_lease_add_plane(struct drm_device *dev, const char *name, - u32 *object_ids, int *object_count, - struct drm_plane **planes, int *plane_count) -{ - struct drm_plane *plane, *added_plane; - int plane_id = -1; - - if (*object_count >= MAX_LEASE_OBJECT_COUNT) { - DRM_ERROR("too many objects %d\n", *object_count); - return -EINVAL; - } - - mutex_lock(&dev->mode_config.mutex); - drm_for_each_plane(plane, dev) { - if (!strcmp(plane->name, name)) { - plane_id = plane->base.id; - added_plane = plane; - break; - } - } - mutex_unlock(&dev->mode_config.mutex); - - if (_obj_is_leased(plane_id, object_ids, *object_count)) { - DRM_ERROR("plane %s is already leased\n", name); - return -EBUSY; - } - - if (plane_id < 0) { - DRM_ERROR("failed to find plane for %s, defer...\n", name); - return -EPROBE_DEFER; - } - - object_ids[(*object_count)++] = plane_id; - planes[(*plane_count)++] = added_plane; - - return 0; -} - -static int msm_lease_parse_objs(struct drm_device *dev, - struct device_node *of_node, - u32 *object_ids, int *object_count) -{ - const char *name; - struct drm_plane *planes[MAX_LEASE_OBJECT_COUNT]; - int count, rc, i, plane_count = 0; - - count = of_property_count_strings(of_node, "qcom,lease-planes"); - if (!count) { - DRM_ERROR("no planes found\n"); - return -EINVAL; - } - - for (i = 0; i < count; i++) { - of_property_read_string_index(of_node, "qcom,lease-planes", - i, &name); - rc = msm_lease_add_plane(dev, name, - object_ids, object_count, - planes, &plane_count); - if (rc) - return rc; - } - - count = of_property_count_strings(of_node, "qcom,lease-connectors"); - if (!count) { - DRM_ERROR("no connectors found\n"); - return -EINVAL; - } - - for (i = 0; i < count; i++) { - of_property_read_string_index(of_node, "qcom,lease-connectors", - i, &name); - rc = msm_lease_add_connector(dev, name, - object_ids, object_count, - i < plane_count ? planes[i] : planes[0]); - if (rc) - return rc; - } - - return 0; -} - -static int msm_lease_parse_misc(struct msm_lease *lease_drv) -{ - of_property_read_string(lease_drv->dev->of_node, - "qcom,dev-name", &lease_drv->dev_name); - - return 0; -} - -static int msm_lease_release(struct inode *inode, struct file *filp) -{ - return g_master_ddev_fops->release(inode, filp); -} - -static int msm_lease_mmap(struct file *filp, struct vm_area_struct *vma) -{ - return g_master_ddev_fops->mmap(filp, vma); -} - -static const struct file_operations msm_lease_fops = { - .owner = THIS_MODULE, - .open = drm_open, - .release = msm_lease_release, - .unlocked_ioctl = msm_lease_ioctl, - .compat_ioctl = drm_compat_ioctl, - .poll = drm_poll, - .read = drm_read, - .llseek = no_llseek, - .mmap = msm_lease_mmap, -}; - -static int msm_lease_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct drm_device *ddev, *master_ddev; - struct drm_minor *minor; - struct msm_lease *lease_drv; - u32 object_ids[MAX_LEASE_OBJECT_COUNT]; - int object_count = 0; - int ret; - - /* defer until primary drm is created */ - minor = drm_minor_acquire(0); - if (IS_ERR(minor)) - return -EPROBE_DEFER; - - /* get master device */ - master_ddev = minor->dev; - drm_minor_release(minor); - if (!master_ddev) - return -EPROBE_DEFER; - - mutex_lock(&g_lease_mutex); - - /* parse lease resources */ - ret = msm_lease_parse_objs(master_ddev, dev->of_node, - object_ids, &object_count); - if (ret) - goto fail; - - lease_drv = devm_kzalloc(dev, sizeof(*lease_drv), GFP_KERNEL); - if (!lease_drv) - goto fail; - - platform_set_drvdata(pdev, lease_drv); - lease_drv->dev = dev; - lease_drv->drm_dev = master_ddev; - - /* parse misc options */ - msm_lease_parse_misc(lease_drv); - - /* create temporary device */ - ddev = drm_dev_alloc(&msm_lease_driver, master_ddev->dev); - if (!ddev) { - dev_err(dev, "failed to allocate drm_device\n"); - goto fail; - } - - ret = drm_dev_register(ddev, 0); - if (ret) { - dev_err(dev, "failed to register drm device\n"); - drm_dev_unref(ddev); - goto fail; - } - - /* redirect minor to master dev */ - minor = ddev->primary; - minor->dev = master_ddev; - minor->type = -1; - ddev->primary = NULL; - - /* unregister temporary driver */ - drm_dev_unregister(ddev); - drm_dev_unref(ddev); - - /* update ids list */ - lease_drv->minor = minor; - lease_drv->obj_cnt = object_count; - memcpy(lease_drv->object_ids, object_ids, sizeof(u32) * object_count); - list_add_tail(&lease_drv->head, &g_lease_list); - - /* hook open/close function */ - if (!g_master_open && !g_master_postclose) { - g_master_open = master_ddev->driver->open; - g_master_postclose = master_ddev->driver->postclose; - master_ddev->driver->open = msm_lease_open; - master_ddev->driver->postclose = msm_lease_postclose; - } - - /* hook ioctl function if dev_name is defined */ - if (!g_master_ddev_fops && lease_drv->dev_name) { - g_master_ddev_fops = master_ddev->driver->fops; - master_ddev->driver->fops = &msm_lease_fops; - } - - /* if lease device has the same name, hide the original name */ - if (lease_drv->dev_name && - !strcmp(lease_drv->dev_name, master_ddev->driver->name)) - g_master_ddev_name_overridden = true; - -fail: - mutex_unlock(&g_lease_mutex); - return ret; -} - -static int msm_lease_remove(struct platform_device *pdev) -{ - struct msm_lease *lease_drv; - - lease_drv = platform_get_drvdata(pdev); - if (!lease_drv) - return 0; - - mutex_lock(&g_lease_mutex); - list_del_init(&lease_drv->head); - mutex_unlock(&g_lease_mutex); - - platform_set_drvdata(pdev, NULL); - - return 0; -} - -static const struct of_device_id dt_match[] = { - { .compatible = "qcom,sde-kms-lease" }, - {} -}; -MODULE_DEVICE_TABLE(of, dt_match); - -static struct platform_driver msm_lease_platform_driver = { - .probe = msm_lease_probe, - .remove = msm_lease_remove, - .driver = { - .name = "msm_lease_drm", - .of_match_table = dt_match, - }, -}; - -static int __init msm_lease_drm_register(void) -{ - return platform_driver_register(&msm_lease_platform_driver); -} - -static void __exit msm_lease_drm_unregister(void) -{ - platform_driver_unregister(&msm_lease_platform_driver); -} - -module_init(msm_lease_drm_register); -module_exit(msm_lease_drm_unregister); - -MODULE_DESCRIPTION("MSM LEASE DRM Driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index aa832242ffab..85f348c95458 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -85,7 +85,6 @@ msm_drm-$(CONFIG_DRM_MSM_MDP5) += mdp/mdp_format.o \ msm_drm-$(CONFIG_DRM_SDE_RSC) += sde_rsc.o \ sde_rsc_hw.o \ - sde_rsc_hw_v3.o \ # use drm gpu driver only if qcom_kgsl driver not available ifneq ($(CONFIG_QCOM_KGSL),y) diff --git a/drivers/gpu/drm/msm/dp/dp_audio.c b/drivers/gpu/drm/msm/dp/dp_audio.c index 649b5c761b2f..1813012412ad 100644 --- a/drivers/gpu/drm/msm/dp/dp_audio.c +++ b/drivers/gpu/drm/msm/dp/dp_audio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -31,7 +31,7 @@ struct dp_audio_private { struct dp_panel *panel; bool ack_enabled; - atomic_t session_on; + bool session_on; bool engine_on; u32 channels; @@ -302,11 +302,6 @@ static void dp_audio_isrc_sdp(struct dp_audio_private *audio) static void dp_audio_setup_sdp(struct dp_audio_private *audio) { - if (!atomic_read(&audio->session_on)) { - pr_warn("session inactive\n"); - return; - } - /* always program stream 0 first before actual stream cfg */ audio->catalog->stream_id = DP_STREAM_0; audio->catalog->config_sdp(audio->catalog); @@ -328,11 +323,6 @@ static void dp_audio_setup_acr(struct dp_audio_private *audio) u32 select = 0; struct dp_catalog_audio *catalog = audio->catalog; - if (!atomic_read(&audio->session_on)) { - pr_warn("session inactive\n"); - return; - } - switch (audio->dp_audio.bw_code) { case DP_LINK_BW_1_62: select = 0; @@ -360,14 +350,10 @@ static void dp_audio_enable(struct dp_audio_private *audio, bool enable) { struct dp_catalog_audio *catalog = audio->catalog; - audio->engine_on = enable; - if (!atomic_read(&audio->session_on)) { - pr_warn("session inactive. enable=%d\n", enable); - return; - } - catalog->data = enable; catalog->enable(catalog); + + audio->engine_on = enable; } static struct dp_audio_private *dp_audio_get_data(struct platform_device *pdev) @@ -467,7 +453,7 @@ static int dp_audio_get_cable_status(struct platform_device *pdev, u32 vote) goto end; } - return atomic_read(&audio->session_on); + return audio->session_on; end: return rc; } @@ -729,7 +715,7 @@ static int dp_audio_on(struct dp_audio *dp_audio) ext = &audio->ext_audio_data; - atomic_set(&audio->session_on, 1); + audio->session_on = true; rc = dp_audio_config(audio, EXT_DISPLAY_CABLE_CONNECT); if (rc) @@ -771,7 +757,7 @@ static int dp_audio_off(struct dp_audio *dp_audio) end: dp_audio_config(audio, EXT_DISPLAY_CABLE_DISCONNECT); - atomic_set(&audio->session_on, 0); + audio->session_on = false; audio->engine_on = false; dp_audio_deregister_ext_disp(audio); diff --git a/drivers/gpu/drm/msm/dp/dp_aux.c b/drivers/gpu/drm/msm/dp/dp_aux.c index d60ee5471754..cb9b268f4dc6 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.c +++ b/drivers/gpu/drm/msm/dp/dp_aux.c @@ -514,7 +514,7 @@ static ssize_t dp_aux_transfer_debug(struct drm_dp_aux *drm_aux, if (aux->read) { timeout = wait_for_completion_timeout(&aux->comp, HZ); if (!timeout) { - pr_err("read timeout 0x%x\n", msg->address); + pr_err("aux timeout for 0x%x\n", msg->address); atomic_set(&aux->aborted, 1); ret = -ETIMEDOUT; goto end; @@ -528,7 +528,7 @@ static ssize_t dp_aux_transfer_debug(struct drm_dp_aux *drm_aux, timeout = wait_for_completion_timeout(&aux->comp, HZ); if (!timeout) { - pr_err("write timeout 0x%x\n", msg->address); + pr_err("aux timeout for 0x%x\n", msg->address); atomic_set(&aux->aborted, 1); ret = -ETIMEDOUT; goto end; @@ -565,8 +565,6 @@ static ssize_t dp_aux_transfer_debug(struct drm_dp_aux *drm_aux, memset(msg->buffer, 0, msg->size); ret = msg->size; end: - if (ret == -ETIMEDOUT) - aux->dp_aux.state |= DP_STATE_AUX_TIMEOUT; aux->dp_aux.reg = 0xFFFF; aux->dp_aux.read = true; aux->dp_aux.size = 0; diff --git a/drivers/gpu/drm/msm/dp/dp_aux.h b/drivers/gpu/drm/msm/dp/dp_aux.h index bfce976da8d5..d683241e36cf 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.h +++ b/drivers/gpu/drm/msm/dp/dp_aux.h @@ -30,7 +30,6 @@ #define DP_STATE_LINK_MAINTENANCE_STARTED BIT(9) #define DP_STATE_LINK_MAINTENANCE_COMPLETED BIT(10) #define DP_STATE_LINK_MAINTENANCE_FAILED BIT(11) -#define DP_STATE_AUX_TIMEOUT BIT(12) enum dp_aux_error { DP_AUX_ERR_NONE = 0, diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index 856465d4932c..036bf45e71c2 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -761,7 +761,6 @@ static void dp_catalog_ctrl_config_ctrl(struct dp_catalog_ctrl *ctrl, u8 ln_cnt) cfg = dp_read(catalog->exe_mode, io_data, DP_CONFIGURATION_CTRL); cfg &= ~(BIT(4) | BIT(5)); cfg |= (ln_cnt - 1) << 4; - cfg &= ~BIT(10); dp_write(catalog->exe_mode, io_data, DP_CONFIGURATION_CTRL, cfg); cfg = dp_read(catalog->exe_mode, io_data, DP_MAINLINK_CTRL); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 78fd2b693cb9..62c73ba93ba6 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -974,16 +974,13 @@ static void dp_display_clean(struct dp_display_private *dp) dp_panel = dp->active_panels[idx]; - if (dp_panel->audio_supported) - dp_panel->audio->off(dp_panel->audio); - dp_display_stream_pre_disable(dp, dp_panel); dp_display_stream_disable(dp, dp_panel); dp_panel->deinit(dp_panel, 0); } dp->power_on = false; - dp->is_connected = false; + dp->ctrl->off(dp->ctrl); } diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c index 82ed2481562e..da04cb64ea60 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -432,7 +432,7 @@ int dp_connector_get_info(struct drm_connector *connector, return 0; } - +extern int op_dp_enable; enum drm_connector_status dp_connector_detect(struct drm_connector *conn, bool force, void *display) @@ -461,6 +461,12 @@ enum drm_connector_status dp_connector_detect(struct drm_connector *conn, conn->display_info.width_mm = info.width_mm; conn->display_info.height_mm = info.height_mm; + if (status == 1) + op_dp_enable = 1; + else + op_dp_enable = 0; + + pr_err("%s:op_dp_enable=%d\n", __func__, op_dp_enable); return status; } diff --git a/drivers/gpu/drm/msm/dp/dp_usbpd.c b/drivers/gpu/drm/msm/dp/dp_usbpd.c index a9da3219e247..c5dfb5c722c3 100644 --- a/drivers/gpu/drm/msm/dp/dp_usbpd.c +++ b/drivers/gpu/drm/msm/dp/dp_usbpd.c @@ -321,7 +321,7 @@ static int dp_usbpd_validate_callback(u8 cmd, static int dp_usbpd_get_ss_lanes(struct dp_usbpd_private *pd) { int rc = 0; - int timeout = 250; + int timeout = 10; /* * By default, USB reserves two lanes for Super Speed. @@ -341,7 +341,7 @@ static int dp_usbpd_get_ss_lanes(struct dp_usbpd_private *pd) pr_warn("USB busy, retry\n"); /* wait for hw recommended delay for usb */ - msleep(20); + msleep(200); timeout--; } } diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c index 7f786eb8b731..60371f37cf3c 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c @@ -111,7 +111,6 @@ static void dsi_catalog_cmn_init(struct dsi_ctrl_hw *ctrl, break; case DSI_CTRL_VERSION_2_2: case DSI_CTRL_VERSION_2_3: - case DSI_CTRL_VERSION_2_4: ctrl->ops.phy_reset_config = dsi_ctrl_hw_22_phy_reset_config; ctrl->ops.config_clk_gating = dsi_ctrl_hw_22_config_clk_gating; ctrl->ops.get_cont_splash_status = @@ -176,7 +175,6 @@ int dsi_catalog_ctrl_setup(struct dsi_ctrl_hw *ctrl, case DSI_CTRL_VERSION_2_0: case DSI_CTRL_VERSION_2_2: case DSI_CTRL_VERSION_2_3: - case DSI_CTRL_VERSION_2_4: ctrl->phy_isolation_enabled = phy_isolation_enabled; dsi_catalog_cmn_init(ctrl, version); break; diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c index 47e347693452..4fe76613df7a 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c @@ -55,7 +55,6 @@ static const enum dsi_ctrl_version dsi_ctrl_v1_4 = DSI_CTRL_VERSION_1_4; static const enum dsi_ctrl_version dsi_ctrl_v2_0 = DSI_CTRL_VERSION_2_0; static const enum dsi_ctrl_version dsi_ctrl_v2_2 = DSI_CTRL_VERSION_2_2; static const enum dsi_ctrl_version dsi_ctrl_v2_3 = DSI_CTRL_VERSION_2_3; -static const enum dsi_ctrl_version dsi_ctrl_v2_4 = DSI_CTRL_VERSION_2_4; static const struct of_device_id msm_dsi_of_match[] = { { @@ -74,10 +73,6 @@ static const struct of_device_id msm_dsi_of_match[] = { .compatible = "qcom,dsi-ctrl-hw-v2.3", .data = &dsi_ctrl_v2_3, }, - { - .compatible = "qcom,dsi-ctrl-hw-v2.4", - .data = &dsi_ctrl_v2_4, - }, {} }; @@ -480,7 +475,6 @@ static int dsi_ctrl_init_regmap(struct platform_device *pdev, break; case DSI_CTRL_VERSION_2_2: case DSI_CTRL_VERSION_2_3: - case DSI_CTRL_VERSION_2_4: ptr = msm_ioremap(pdev, "disp_cc_base", ctrl->name); if (IS_ERR(ptr)) { pr_err("disp_cc base address not found for [%s]\n", @@ -583,7 +577,6 @@ static int dsi_ctrl_clocks_init(struct platform_device *pdev, if (IS_ERR(hs_link->byte_clk)) { rc = PTR_ERR(hs_link->byte_clk); pr_err("failed to get byte_clk, rc=%d\n", rc); - hs_link->byte_clk = NULL; goto fail; } @@ -591,7 +584,6 @@ static int dsi_ctrl_clocks_init(struct platform_device *pdev, if (IS_ERR(hs_link->pixel_clk)) { rc = PTR_ERR(hs_link->pixel_clk); pr_err("failed to get pixel_clk, rc=%d\n", rc); - hs_link->pixel_clk = NULL; goto fail; } @@ -599,7 +591,6 @@ static int dsi_ctrl_clocks_init(struct platform_device *pdev, if (IS_ERR(lp_link->esc_clk)) { rc = PTR_ERR(lp_link->esc_clk); pr_err("failed to get esc_clk, rc=%d\n", rc); - lp_link->esc_clk = NULL; goto fail; } @@ -613,7 +604,6 @@ static int dsi_ctrl_clocks_init(struct platform_device *pdev, if (IS_ERR(rcg->byte_clk)) { rc = PTR_ERR(rcg->byte_clk); pr_err("failed to get byte_clk_rcg, rc=%d\n", rc); - rcg->byte_clk = NULL; goto fail; } @@ -621,7 +611,6 @@ static int dsi_ctrl_clocks_init(struct platform_device *pdev, if (IS_ERR(rcg->pixel_clk)) { rc = PTR_ERR(rcg->pixel_clk); pr_err("failed to get pixel_clk_rcg, rc=%d\n", rc); - rcg->pixel_clk = NULL; goto fail; } @@ -854,7 +843,6 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl, if (config->bit_clk_rate_hz_override == 0) { if (config->panel_mode == DSI_OP_CMD_MODE) { h_period = DSI_H_ACTIVE_DSC(timing); - h_period += timing->overlap_pixels; v_period = timing->v_active; do_div(refresh_rate, timing->mdp_transfer_time_us); @@ -1110,6 +1098,38 @@ int dsi_message_validate_tx_mode(struct dsi_ctrl *dsi_ctrl, return rc; } +#if 0 +static void print_cmd_desc(const struct mipi_dsi_msg *msg) +{ + + char buf[1024]; + int len = 0; + size_t i; + + /* Packet Info */ + len += snprintf(buf, sizeof(buf) - len, "%02x ", msg->type); + len += snprintf(buf + len, sizeof(buf) - len, "%02x ", + (msg->flags & MIPI_DSI_MSG_LASTCOMMAND) ? 1 : 0); /* Last bit */ + len += snprintf(buf + len, sizeof(buf) - len, "%02x ", msg->channel); + len += snprintf(buf + len, sizeof(buf) - len, "%02x ", + (unsigned int)msg->flags); + len += snprintf(buf + len, sizeof(buf) - len, "%02x ", 0); /* Delay */ + len += snprintf(buf + len, sizeof(buf) - len, "%02x ", + (unsigned int)msg->tx_len); + + /* Packet Payload */ + for (i = 0 ; i < msg->tx_len ; i++) { + len += snprintf(buf + len, sizeof(buf) - len, + "%02x ", msg->tx_buf[i]); + /* Break to prevent show too long command */ + if (i > 250) + break; + } + + printk(KERN_ERR"(%02d) %s\n", (unsigned int)msg->tx_len, buf); +} +#endif + static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl, const struct mipi_dsi_msg *msg, u32 flags) @@ -1125,6 +1145,7 @@ static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl, u8 *cmdbuf; struct dsi_mode_info *timing; struct dsi_ctrl_hw_ops dsi_hw_ops = dsi_ctrl->hw.ops; + //print_cmd_desc(msg); /* Select the tx mode to transfer the command */ dsi_message_setup_tx_mode(dsi_ctrl, msg->tx_len, &flags); @@ -2941,12 +2962,10 @@ int dsi_ctrl_update_host_config(struct dsi_ctrl *ctrl, pr_debug("[DSI_%d]Host config updated\n", ctrl->cell_index); memcpy(&ctrl->host_config, config, sizeof(ctrl->host_config)); - ctrl->mode_bounds.x = (ctrl->host_config.video_timing.h_active + - ctrl->host_config.video_timing.overlap_pixels) * - ctrl->horiz_index; + ctrl->mode_bounds.x = ctrl->host_config.video_timing.h_active * + ctrl->horiz_index; ctrl->mode_bounds.y = 0; - ctrl->mode_bounds.w = ctrl->host_config.video_timing.h_active + - ctrl->host_config.video_timing.overlap_pixels; + ctrl->mode_bounds.w = ctrl->host_config.video_timing.h_active; ctrl->mode_bounds.h = ctrl->host_config.video_timing.v_active; memcpy(&ctrl->roi, &ctrl->mode_bounds, sizeof(ctrl->mode_bounds)); ctrl->modeupdated = true; diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h index 4446bba8f16c..aa6b52a9ee4e 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h @@ -36,7 +36,6 @@ * @DSI_CTRL_VERSION_2_0: DSI host v2.0 controller * @DSI_CTRL_VERSION_2_2: DSI host v2.2 controller * @DSI_CTRL_VERSION_2_3: DSI host v2.3 controller - * @DSI_CTRL_VERSION_2_4: DSI host v2.4 controller * @DSI_CTRL_VERSION_MAX: max version */ enum dsi_ctrl_version { @@ -45,7 +44,6 @@ enum dsi_ctrl_version { DSI_CTRL_VERSION_2_0, DSI_CTRL_VERSION_2_2, DSI_CTRL_VERSION_2_3, - DSI_CTRL_VERSION_2_4, DSI_CTRL_VERSION_MAX }; diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c index 909a6840dcc7..725dbd101fb9 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c @@ -310,7 +310,7 @@ void dsi_ctrl_hw_cmn_set_video_timing(struct dsi_ctrl_hw *ctrl, reg |= 1; DSI_W32(ctrl, DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); } else { - width = mode->h_active + mode->overlap_pixels; + width = mode->h_active; } hs_end = mode->h_sync_width; @@ -421,8 +421,8 @@ void dsi_ctrl_hw_cmn_setup_cmd_stream(struct dsi_ctrl_hw *ctrl, stride_final = roi->w * 3; height_final = roi->h; } else { - width_final = mode->h_active + mode->overlap_pixels; - stride_final = h_stride + mode->overlap_pixels * 3; + width_final = mode->h_active; + stride_final = h_stride; height_final = mode->v_active; } diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h index 213142263d58..50fc239cce1d 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h @@ -288,6 +288,72 @@ enum dsi_cmd_set_type { DSI_CMD_SET_POST_TIMING_SWITCH, DSI_CMD_SET_QSYNC_ON, DSI_CMD_SET_QSYNC_OFF, + DSI_CMD_SET_HBM_BRIGHTNESS_ON, + DSI_CMD_SET_HBM_BRIGHTNESS_OFF, + DSI_CMD_SET_HBM_ON_1, + DSI_CMD_SET_HBM_ON_2, + DSI_CMD_SET_HBM_ON_3, + DSI_CMD_SET_HBM_ON_4, + DSI_CMD_SET_HBM_ON_5, + DSI_CMD_SET_HBM_OFF, + DSI_CMD_SET_PANEL_SERIAL_NUMBER, + DSI_CMD_SET_AOD_ON_1, + DSI_CMD_SET_AOD_ON_2, + DSI_CMD_SET_AOD_OFF, + DSI_CMD_AOD_OFF_HBM_ON_SETTING, + DSI_CMD_SET_AOD_OFF_NEW, + DSI_CMD_HBM_OFF_AOD_ON_SETTING, + DSI_CMD_SET_AOD_OFF_SAMSUNG, +// DSI_CMD_SET_SRGB_ON, +// DSI_CMD_SET_SRGB_OFF, + DSI_CMD_SET_DCI_P3_ON, + DSI_CMD_SET_DCI_P3_OFF, + DSI_CMD_SET_NIGHT_ON, + DSI_CMD_SET_NIGHT_OFF, + DSI_CMD_SET_PANEL_ID, + DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON, + DSI_CMD_SET_PANEL_ID1, + DSI_CMD_SET_PANEL_ID2, + DSI_CMD_SET_PANEL_ID3, + DSI_CMD_SET_PANEL_ID4, + DSI_CMD_SET_PANEL_ID5, + DSI_CMD_SET_PANEL_ID6, + DSI_CMD_SET_PANEL_ID7, + DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF, + DSI_CMD_SET_ACL_MODE, + DSI_CMD_SET_LCDINFO_PRE, + DSI_CMD_SET_LCDINFO_POST, + DSI_CMD_SET_CODE_INFO, + DSI_CMD_SET_STAGE_INFO, + DSI_CMD_SET_PRODUCTION_INFO, + DSI_CMD_SET_ESD_LOGREAD_PREREAD, + DSI_CMD_SET_GAMMA_FLASH_PRE_READ_1, + DSI_CMD_SET_GAMMA_FLASH_PRE_READ_2, + DSI_CMD_SET_GAMMA_FLASH_READ_FB, + DSI_CMD_SET_LEVEL2_KEY_ENABLE, + DSI_CMD_SET_GAMMA_OTP_READ_C8_SMRPS, + DSI_CMD_SET_GAMMA_OTP_READ_C8, + DSI_CMD_SET_GAMMA_OTP_READ_C9_SMRPS, + DSI_CMD_SET_GAMMA_OTP_READ_C9, + DSI_CMD_SET_GAMMA_OTP_READ_B3_SMRPS, + DSI_CMD_SET_GAMMA_OTP_READ_B3, + DSI_CMD_SET_LEVEL2_KEY_DISABLE, + DSI_CMD_SET_NATIVE_DISPLAY_P3_ON, + DSI_CMD_SET_NATIVE_DISPLAY_P3_OFF, + DSI_CMD_SET_NATIVE_DISPLAY_WIDE_COLOR_ON, + DSI_CMD_SET_NATIVE_DISPLAY_WIDE_COLOR_OFF, + DSI_CMD_SET_NATIVE_DISPLAY_SRGB_COLOR_ON, + DSI_CMD_SET_NATIVE_DISPLAY_SRGB_COLOR_OFF, + DSI_CMD_SET_113MHZ_OSC_ON, + DSI_CMD_POST_ON_BACKLIGHT, + DSI_CMD_LOADING_EFFECT_ON, + DSI_CMD_LOADING_EFFECT_OFF, + DSI_CMD_LOADING_CUSTOMER_RGB_ON, + DSI_CMD_LOADING_CUSTOMER_RGB_OFF, + DSI_CMD_LOADING_CUSTOMER_P3_ON, + DSI_CMD_LOADING_CUSTOMER_P3_OFF, + DSI_CMD_SET_PANEL_COMMAND, + DSI_CMD_SET_SEED_COMMAND, DSI_CMD_SET_MAX }; @@ -392,7 +458,6 @@ struct dsi_panel_cmd_set { * @clk_rate_hz: DSI bit clock rate per lane in Hz. * @mdp_transfer_time_us: Specifies the mdp transfer time for command mode * panels in microseconds. - * @overlap_pixels: overlap pixels for certain panels. * @dsc_enabled: DSC compression enabled. * @dsc: DSC compression configuration. * @roi_caps: Panel ROI capabilities. @@ -414,7 +479,6 @@ struct dsi_mode_info { u32 refresh_rate; u64 clk_rate_hz; u32 mdp_transfer_time_us; - u32 overlap_pixels; bool dsc_enabled; struct msm_display_dsc_info *dsc; struct msm_roi_caps roi_caps; @@ -568,7 +632,6 @@ struct dsi_host_config { * @mdp_transfer_time_us: Specifies the mdp transfer time for command mode * panels in microseconds. * @clk_rate_hz: DSI bit clock per lane in hz. - * @overlap_pixels: overlap pixels for certain panels. * @topology: Topology selected for the panel * @dsc: DSC compression info * @dsc_enabled: DSC compression enabled @@ -585,7 +648,6 @@ struct dsi_display_mode_priv_info { u32 panel_prefill_lines; u32 mdp_transfer_time_us; u64 clk_rate_hz; - u32 overlap_pixels; struct msm_display_topology topology; struct msm_display_dsc_info dsc; diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c index a4c4e957f10b..3cc5496214fc 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c @@ -31,6 +31,16 @@ #include "dsi_pwr.h" #include "sde_dbg.h" #include "dsi_parser.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include "../sde/sde_trace.h" +#include "dsi_parser.h" #define to_dsi_display(x) container_of(x, struct dsi_display, host) #define INT_BASE_10 10 @@ -44,10 +54,14 @@ #define DSI_CLOCK_BITRATE_RADIX 10 #define MAX_TE_SOURCE_ID 2 +#define WU_SEED_REGISTER 0x67 +#define UG_SEED_REGISTER 0xB1 + DEFINE_MUTEX(dsi_display_clk_mutex); static char dsi_display_primary[MAX_CMDLINE_PARAM_LEN]; static char dsi_display_secondary[MAX_CMDLINE_PARAM_LEN]; +static char SERIAL_NUMBER_flag = 0; static struct dsi_display_boot_param boot_displays[MAX_DSI_ACTIVE_DISPLAY] = { {.boot_param = dsi_display_primary}, {.boot_param = dsi_display_secondary}, @@ -58,6 +72,16 @@ static const struct of_device_id dsi_display_dt_match[] = { {} }; +static int esd_black_count; +static int esd_greenish_count; +static struct dsi_display *primary_display; +static struct input_dev* fresh_rate_input_dev = NULL; +static struct proc_dir_entry *proc_entry_display = NULL; +static int fresh_rate_report_enable = 0; +static bool fresh_rate_input_dev_init = false; + +#define to_dsi_bridge(x) container_of((x), struct dsi_bridge, base) + static void dsi_display_mask_ctrl_error_interrupts(struct dsi_display *display, u32 mask, bool enable) { @@ -183,6 +207,7 @@ void dsi_rect_intersect(const struct dsi_rect *r1, } } +extern int aod_layer_hide; int dsi_display_set_backlight(struct drm_connector *connector, void *display, u32 bl_lvl) { @@ -191,7 +216,7 @@ int dsi_display_set_backlight(struct drm_connector *connector, u32 bl_scale, bl_scale_ad; u64 bl_temp; int rc = 0; - + static int gamma_read_flag; if (dsi_display == NULL || dsi_display->panel == NULL) return -EINVAL; @@ -199,10 +224,89 @@ int dsi_display_set_backlight(struct drm_connector *connector, mutex_lock(&panel->panel_lock); if (!dsi_panel_initialized(panel)) { + panel->hbm_backlight = bl_lvl; + panel->bl_config.bl_level = bl_lvl; + pr_err("HBM_backight =%d\n",panel->hbm_backlight); rc = -EINVAL; goto error; } + + if (strcmp(dsi_display->panel->name, "samsung s6e3fc2x01 cmd mode dsi panel") == 0) { + if (bl_lvl != 0 && panel->bl_config.bl_level == 0) { + if (panel->naive_display_p3_mode) { + mdelay(20); + pr_err("Send DSI_CMD_SET_NATIVE_DISPLAY_P3_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_NATIVE_DISPLAY_P3_ON); + } + if (panel->naive_display_wide_color_mode) { + mdelay(20); + pr_err("Send DSI_CMD_SET_NATIVE_DISPLAY_WIDE_COLOR_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_NATIVE_DISPLAY_WIDE_COLOR_ON); + } + if (panel->naive_display_srgb_color_mode) { + mdelay(20); + pr_err("Send DSI_CMD_SET_NATIVE_DISPLAY_SRGB_COLOR_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_NATIVE_DISPLAY_SRGB_COLOR_ON); + } + if (panel->naive_display_customer_srgb_mode) { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_RGB_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_RGB_ON); + } else { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_RGB_OFF cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_RGB_OFF); + } + if (panel->naive_display_customer_p3_mode) { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_P3_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_P3_ON); + } else { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_P3_OFF cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_P3_OFF); + } + } + } + + if (strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0) { + if (bl_lvl != 0 && panel->bl_config.bl_level == 0) { + if (panel->naive_display_p3_mode) { + mdelay(20); + pr_err("Send DSI_CMD_SET_NATIVE_DISPLAY_P3_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_NATIVE_DISPLAY_P3_ON); + } + if (panel->naive_display_wide_color_mode) { + mdelay(20); + pr_err("Send DSI_CMD_SET_NATIVE_DISPLAY_WIDE_COLOR_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_NATIVE_DISPLAY_WIDE_COLOR_ON); + } + if (panel->naive_display_srgb_color_mode) { + mdelay(20); + pr_err("Send DSI_CMD_SET_NATIVE_DISPLAY_SRGB_COLOR_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_NATIVE_DISPLAY_SRGB_COLOR_ON); + } + if (panel->naive_display_loading_effect_mode) { + pr_err("Send DSI_CMD_LOADING_EFFECT_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_EFFECT_ON); + } else { + pr_err("Send DSI_CMD_LOADING_EFFECT_OFF cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_EFFECT_OFF); + } + if (panel->naive_display_customer_srgb_mode) { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_RGB_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_RGB_ON); + } else { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_RGB_OFF cmds\n"); + //rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_RGB_OFF); + } + if (panel->naive_display_customer_p3_mode) { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_P3_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_P3_ON); + } else { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_P3_OFF cmds\n"); + //rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_P3_OFF); + } + } + } + panel->bl_config.bl_level = bl_lvl; /* scale backlight */ @@ -237,6 +341,22 @@ int dsi_display_set_backlight(struct drm_connector *connector, error: mutex_unlock(&panel->panel_lock); + + if((strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0 + || strcmp(panel->name, "samsung s6e3fc2x01 cmd mode dsi panel") == 0) && (0 == SERIAL_NUMBER_flag)) { + dsi_display_get_serial_number_AT(connector); + } + + if ((gamma_read_flag < 2) && (strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0)) { + if (gamma_read_flag < 1) { + gamma_read_flag++; + } + else { + schedule_delayed_work(&dsi_display->panel->gamma_read_work, 0); + gamma_read_flag++; + } + } + return rc; } @@ -383,6 +503,96 @@ static void dsi_display_aspace_cb_locked(void *cb_data, bool is_detach) dsi_panel_release_panel_lock(display->panel); } +static irqreturn_t dsi_display_panel_err_flag_irq_handler(int irq, void *data) +{ + struct dsi_display *display = (struct dsi_display *)data; + /* + * This irq handler is used for sole purpose of identifying + * ESD attacks on panel and we can safely assume IRQ_HANDLED + * in case of display not being initialized yet + */ + if ((!display) || (!display->panel->is_err_flag_irq_enabled) || (!display->panel->panel_initialized)) + return IRQ_HANDLED; + + pr_err("%s\n", __func__); + + if (!display->panel->err_flag_status) { + display->panel->err_flag_status = true; + cancel_delayed_work_sync(sde_esk_check_delayed_work); + schedule_delayed_work(sde_esk_check_delayed_work, 0); + pr_err("schedule sde_esd_check_delayed_work\n"); + } + + return IRQ_HANDLED; +} + +void dsi_display_change_err_flag_irq_status(struct dsi_display *display, + bool enable) +{ + if (!display) { + pr_err("Invalid params\n"); + return; + } + + if (!gpio_is_valid(display->panel->err_flag_gpio)) + return; + + /* Handle unbalanced irq enable/disbale calls */ + if (enable && !display->panel->is_err_flag_irq_enabled) { + enable_irq(gpio_to_irq(display->panel->err_flag_gpio)); + display->panel->is_err_flag_irq_enabled = true; + pr_err("enable err flag irq\n"); + } else if (!enable && display->panel->is_err_flag_irq_enabled) { + disable_irq(gpio_to_irq(display->panel->err_flag_gpio)); + display->panel->is_err_flag_irq_enabled = false; + pr_err("disable err flag irq\n"); + } +} +EXPORT_SYMBOL(dsi_display_change_err_flag_irq_status); + +static void dsi_display_register_err_flag_irq(struct dsi_display *display) +{ + int rc = 0; + struct platform_device *pdev; + struct device *dev; + unsigned int err_flag_irq; + + pdev = display->pdev; + if (!pdev) { + pr_err("invalid platform device\n"); + return; + } + + dev = &pdev->dev; + if (!dev) { + pr_err("invalid device\n"); + return; + } + + if (!gpio_is_valid(display->panel->err_flag_gpio)) { + pr_err("Failed to get err-flag-gpio\n"); + rc = -EINVAL; + return; + } + + err_flag_irq = gpio_to_irq(display->panel->err_flag_gpio); + + /* Avoid deferred spurious irqs with disable_irq() */ + irq_set_status_flags(err_flag_irq, IRQ_DISABLE_UNLAZY); + + rc = devm_request_irq(dev, err_flag_irq, dsi_display_panel_err_flag_irq_handler, + IRQF_TRIGGER_FALLING | IRQF_ONESHOT, + "ERR_FLAG_GPIO", display); + if (rc) { + pr_err("Err flag request_irq failed for ESD rc:%d\n", rc); + irq_clear_status_flags(err_flag_irq, IRQ_DISABLE_UNLAZY); + return; + } + + disable_irq(err_flag_irq); + display->panel->is_err_flag_irq_enabled = false; +} + static irqreturn_t dsi_display_panel_te_irq_handler(int irq, void *data) { struct dsi_display *display = (struct dsi_display *)data; @@ -708,12 +918,79 @@ static int dsi_display_validate_status(struct dsi_display_ctrl *ctrl, return rc; } +static int dsi_panel_tx_cmd_set_op(struct dsi_panel *panel, + enum dsi_cmd_set_type type) +{ + int rc = 0, i = 0; + ssize_t len; + struct dsi_cmd_desc *cmds; + u32 count; + enum dsi_cmd_set_state state; + struct dsi_display_mode *mode; + const struct mipi_dsi_host_ops *ops = panel->host->ops; + if (!panel || !panel->cur_mode) + return -EINVAL; + + + mode = panel->cur_mode; + + cmds = mode->priv_info->cmd_sets[type].cmds; + count = mode->priv_info->cmd_sets[type].count; + state = mode->priv_info->cmd_sets[type].state; + + if (count == 0) { + pr_debug("[%s] No commands to be sent for state(%d)\n", + panel->name, type); + goto error; + } + for (i = 0; i < count; i++) { + if (state == DSI_CMD_SET_STATE_LP) + cmds->msg.flags |= MIPI_DSI_MSG_USE_LPM; + + if (cmds->last_command) + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + + len = ops->transfer(panel->host, &cmds->msg); + if (len < 0) { + rc = len; + pr_err("failed to set cmds(%d), rc=%d\n", type, rc); + goto error; + } + if (cmds->post_wait_ms) + usleep_range(cmds->post_wait_ms*1000, + ((cmds->post_wait_ms*1000)+10)); + cmds++; + } +error: + return rc; +} + static int dsi_display_status_reg_read(struct dsi_display *display) { int rc = 0, i; struct dsi_display_ctrl *m_ctrl, *ctrl; - - pr_debug(" ++\n"); + struct dsi_display_mode *mode; + u32 flags = 0; + u32 count = 0; + struct dsi_panel *panel = NULL; + struct dsi_cmd_desc *cmds1; + struct dsi_cmd_desc *cmds2; + struct dsi_cmd_desc *cmds3; + struct dsi_cmd_desc *cmds4; + struct dsi_cmd_desc *cmds5; + struct dsi_cmd_desc *cmds6; + struct dsi_cmd_desc *cmds7; + u8 temp_buffer_1[1] = {0}; + u8 temp_buffer_2[1] = {0}; + u8 temp_buffer_3[1] = {0}; + u8 temp_buffer_4[1] = {0}; + u8 temp_buffer_5[2] = {0,}; + u8 temp_buffer_6[16] = {0,}; + u8 temp_buffer_7[34] = {0,}; +// u8 register_0a[1] = {0}; +// u8 register_b6[1] = {0}; + u8 buf[48]; + memset(buf, 0, sizeof(buf)); m_ctrl = &display->ctrl[display->cmd_master_idx]; @@ -730,8 +1007,191 @@ static int dsi_display_status_reg_read(struct dsi_display *display) pr_err("cmd engine enable failed\n"); return -EPERM; } + mode = display->panel->cur_mode; + panel = display->panel; + + if (strcmp(panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0) { + count = mode->priv_info->cmd_sets[DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON].count; + if (!count) { + pr_err("This panel does not read register\n"); + } else { + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + } + cmds1 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID1].cmds; + if (cmds1->last_command) { + cmds1->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds1->msg.rx_buf = buf; + cmds1->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds1->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + + memcpy(temp_buffer_1, cmds1->msg.rx_buf, 1); + memset(buf, 0, sizeof(buf)); + + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + cmds2 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID2].cmds; + if (cmds2->last_command) { + cmds2->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds2->msg.rx_buf = buf; + cmds2->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds2->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + + memcpy(temp_buffer_2, cmds2->msg.rx_buf, 1); + memset(buf, 0, sizeof(buf)); + + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + cmds3 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID3].cmds; + if (cmds3->last_command) { + cmds3->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds3->msg.rx_buf = buf; + cmds3->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds3->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + + memcpy(temp_buffer_3, cmds3->msg.rx_buf, 1); + + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + cmds4 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID4].cmds; + if (cmds4->last_command) { + cmds4->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds4->msg.rx_buf = buf; + cmds4->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds4->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + + memcpy(temp_buffer_4, cmds4->msg.rx_buf, 1); + memset(buf, 0, sizeof(buf)); + + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + cmds5 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID5].cmds; + if (cmds5->last_command) { + cmds5->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds5->msg.rx_buf = buf; + cmds5->msg.rx_len = 2; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds5->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + + memcpy(temp_buffer_5, cmds5->msg.rx_buf, 2); + memset(buf, 0, sizeof(buf)); + + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + cmds6 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID6].cmds; + if (cmds6->last_command) { + cmds6->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds6->msg.rx_buf = buf; + cmds6->msg.rx_len = 16; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds6->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + + memcpy(temp_buffer_6, cmds6->msg.rx_buf, 16); + memset(buf, 0, sizeof(buf)); + + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_SET_ESD_LOGREAD_PREREAD); + + cmds7 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID7].cmds; + if (cmds7->last_command) { + cmds7->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds7->msg.rx_buf = buf; + cmds7->msg.rx_len = 34; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds7->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + + memcpy(temp_buffer_7, cmds7->msg.rx_buf, 34); + + if((temp_buffer_6[0] !=0x80) && (temp_buffer_2[0] != 0x80)) { + rc = -1; + } + else { + rc = 1; + } + } else if (strcmp(panel->name, "samsung s6e3fc2x01 cmd mode dsi panel") == 0) { + count = mode->priv_info->cmd_sets[DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON].count; + if (!count) { + pr_err("This panel does not read register\n"); + } else { + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + } + cmds1 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID1].cmds; + if (cmds1->last_command) { + cmds1->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds1->msg.rx_buf = buf; + cmds1->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds1->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + memcpy(temp_buffer_1, cmds1->msg.rx_buf, 1); + count = mode->priv_info->cmd_sets[DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON].count; + if (!count) { + pr_err("This panel does not read register\n"); + } else { + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + } + cmds2 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID6].cmds; + if (cmds2->last_command) { + cmds2->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds2->msg.rx_buf = buf; + cmds2->msg.rx_len = 2; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds2->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + memcpy(temp_buffer_6, cmds2->msg.rx_buf, 2); + count = mode->priv_info->cmd_sets[DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF].count; + if (!count) { + pr_err("This panel does not read register\n"); + } else { + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + } + if(((temp_buffer_6[0] == 132) && (temp_buffer_6[1] == 0))||(temp_buffer_1[0] != 159)) + rc = -1; + else + rc = 1; + } else { + rc = dsi_display_validate_status(m_ctrl, display->panel); + } - rc = dsi_display_validate_status(m_ctrl, display->panel); if (rc <= 0) { pr_err("[%s] read status failed on master,rc=%d\n", display->name, rc); @@ -755,6 +1215,7 @@ static int dsi_display_status_reg_read(struct dsi_display *display) } exit: dsi_display_cmd_engine_disable(display); + done: return rc; } @@ -803,6 +1264,10 @@ int dsi_display_check_status(struct drm_connector *connector, void *display, panel = dsi_display->panel; dsi_panel_acquire_panel_lock(panel); + + if (strcmp(dsi_display->panel->name, "samsung findx dsc cmd mode dsi panel") == 0){ + goto release_panel_lock; + } if (!panel->panel_initialized) { pr_debug("Panel not initialized\n"); @@ -832,6 +1297,15 @@ int dsi_display_check_status(struct drm_connector *connector, void *display, goto exit; } + if (dsi_display->panel->err_flag_status == true) { + esd_black_count++; + pr_err("%s:black_count=%d, greenish_count=%d, total=%d\n", + __func__, esd_black_count, esd_greenish_count, + esd_black_count + esd_greenish_count); + rc = -1; + goto exit; + } + dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_ON); @@ -1069,12 +1543,15 @@ static bool dsi_display_get_cont_splash_status(struct dsi_display *display) } return true; } +extern int dsi_panel_set_aod_mode(struct dsi_panel *panel, int level); int dsi_display_set_power(struct drm_connector *connector, int power_mode, void *disp) { struct dsi_display *display = disp; int rc = 0; + struct msm_drm_notifier notifier_data; + int blank; if (!display || !display->panel) { pr_err("invalid display/panel\n"); @@ -1092,12 +1569,26 @@ int dsi_display_set_power(struct drm_connector *connector, if (display->panel->power_mode == SDE_MODE_DPMS_LP1 || display->panel->power_mode == SDE_MODE_DPMS_LP2) rc = dsi_panel_set_nolp(display->panel); + /*sned screen on cmd for TP start*/ + blank = MSM_DRM_BLANK_UNBLANK_CUST; + notifier_data.data = ␣ + notifier_data.id = connector_state_crtc_index; + msm_drm_notifier_call_chain(MSM_DRM_EARLY_EVENT_BLANK, + ¬ifier_data); + /*sned screen on cmd for TP end*/ break; case SDE_MODE_DPMS_OFF: + /*sned screen off cmd for TP start*/ + blank = MSM_DRM_BLANK_POWERDOWN_CUST; + notifier_data.data = ␣ + notifier_data.id = connector_state_crtc_index; + msm_drm_notifier_call_chain(MSM_DRM_EARLY_EVENT_BLANK, + ¬ifier_data); + /*sned screen off cmd for TP end*/ + break; default: return rc; } - pr_debug("Power mode transition from %d to %d %s", display->panel->power_mode, power_mode, rc ? "failed" : "successful"); @@ -3676,6 +4167,11 @@ static int dsi_display_res_init(struct dsi_display *display) goto error_ctrl_put; } + if (strcmp(display->panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0) { + INIT_DELAYED_WORK(&display->panel->gamma_read_work, dsi_display_gamma_read_work); + pr_err("INIT_DELAYED_WORK: dsi_display_gamma_read_work\n"); + } + return 0; error_ctrl_put: for (i = i - 1; i >= 0; i--) { @@ -4300,7 +4796,6 @@ static int dsi_display_get_dfps_timing(struct dsi_display *display, struct dsi_display_mode per_ctrl_mode; struct dsi_mode_info *timing; struct dsi_ctrl *m_ctrl; - u32 overlap_pixels = 0; int rc = 0; @@ -4310,6 +4805,7 @@ static int dsi_display_get_dfps_timing(struct dsi_display *display, } m_ctrl = display->ctrl[display->clk_master_idx].ctrl; + dsi_panel_get_dfps_caps(display->panel, &dfps_caps); if (!dfps_caps.dfps_support) { pr_err("dfps not supported by panel\n"); @@ -4335,7 +4831,6 @@ static int dsi_display_get_dfps_timing(struct dsi_display *display, } /* TODO: Remove this direct reference to the dsi_ctrl */ timing = &per_ctrl_mode.timing; - overlap_pixels = per_ctrl_mode.priv_info->overlap_pixels; switch (dfps_caps.type) { case DSI_DFPS_IMMEDIATE_VFP: @@ -4353,7 +4848,7 @@ static int dsi_display_get_dfps_timing(struct dsi_display *display, curr_refresh_rate, timing->refresh_rate, DSI_V_TOTAL(timing), - DSI_H_TOTAL_DSC(timing) + overlap_pixels, + DSI_H_TOTAL_DSC(timing), timing->h_front_porch, &adj_mode->timing.h_front_porch); if (!rc) @@ -5095,6 +5590,8 @@ static int dsi_display_bind(struct device *dev, /* register te irq handler */ dsi_display_register_te_irq(display); + /* register err flag irq handler */ + dsi_display_register_err_flag_irq(display); goto error; @@ -5232,6 +5729,90 @@ static void dsi_display_firmware_display(const struct firmware *fw, pr_debug("success\n"); } +static ssize_t fresh_rate_read(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) +{ + int ret = 0; + char fresh_rate[4] = {0}; + + if (mode_fps == 90) + strcpy(fresh_rate, "90"); + else if (mode_fps == 60) + strcpy(fresh_rate, "60"); + else + strcpy(fresh_rate, "-1"); + + pr_info("fresh_rate : %s\n", fresh_rate); + ret = simple_read_from_buffer(user_buf, count, ppos, fresh_rate, strlen(fresh_rate)); + return ret; +} + +static const struct file_operations fresh_rate_fops = { + .read = fresh_rate_read, + .open = simple_open, + .owner = THIS_MODULE, +}; + +static ssize_t fresh_rate_event_num_read(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) +{ + int ret = 0; + const char *devname = NULL; + struct input_handle *handle; + if (!fresh_rate_input_dev) + return count; + list_for_each_entry(handle, &(fresh_rate_input_dev->h_list), d_node) { + if (strncmp(handle->name, "event", 5) == 0) { + devname = handle->name; + break; + } + } + ret = simple_read_from_buffer(user_buf, count, ppos, devname, strlen(devname)); + return ret; +} + +static const struct file_operations fresh_rate_event_num_fops = { + .read = fresh_rate_event_num_read, + .open = simple_open, + .owner = THIS_MODULE, +}; + +static ssize_t fresh_rate_enable_read(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) +{ + ssize_t ret =0; + char page[4]; + + pr_info("the fresh_rate_report_enable is: %d\n", fresh_rate_report_enable); + ret = sprintf(page, "%d\n", fresh_rate_report_enable); + ret = simple_read_from_buffer(user_buf, count, ppos, page, strlen(page)); + return ret; + +} + +static ssize_t fresh_rate_enable_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos) +{ + char buf[8]={0}; + + if( count > 2) + count = 2; + if(copy_from_user(buf, buffer, count)){ + pr_err("%s: read proc input error.\n", __func__); + return count; + } + if('0' == buf[0]) { + fresh_rate_report_enable = 0; + } else if('1' == buf[0]){ + fresh_rate_report_enable = 1; + } + + return count; +} + +static const struct file_operations fresh_rate_enable_fops = { + .read = fresh_rate_enable_read, + .write = fresh_rate_enable_write, + .open = simple_open, + .owner = THIS_MODULE, +}; + int dsi_display_dev_probe(struct platform_device *pdev) { struct dsi_display *display = NULL; @@ -5242,6 +5823,15 @@ int dsi_display_dev_probe(struct platform_device *pdev) int i, count, rc = 0, index; bool firm_req = false; struct dsi_display_boot_param *boot_disp; + struct proc_dir_entry* proc_entry_tmp = NULL; + + if (fresh_rate_input_dev_init == false) { + proc_entry_display = proc_mkdir("fresh_rate_for_sensor", NULL); + if( proc_entry_display == NULL ){ + pr_err("Couldn't create fresh_rate_for_sensor directory\n"); + } + } + if (!pdev || !pdev->dev.of_node) { pr_err("pdev not found\n"); @@ -5331,12 +5921,61 @@ int dsi_display_dev_probe(struct platform_device *pdev) goto end; } + + if (fresh_rate_input_dev_init == false) { + //create fresh_rate + proc_entry_tmp = proc_create("fresh_rate", 0664, + proc_entry_display, &fresh_rate_fops); + if (proc_entry_tmp == NULL) { + pr_err("Couldn't create fresh_rate_fops\n"); + goto fresh_rate_report_failed; + } + + //create fresh_rate_event_num + proc_entry_tmp = proc_create("fresh_rate_event_num", 0664, + proc_entry_display, &fresh_rate_event_num_fops); + if (proc_entry_tmp == NULL) { + pr_err("Couldn't create fresh_rate_event_num_fops\n"); + goto fresh_rate_report_failed; + } + + //create fresh_rate_enable + proc_entry_tmp = proc_create("fresh_rate_enable", 0666, + proc_entry_display, &fresh_rate_enable_fops); + if (proc_entry_tmp == NULL) { + pr_err("Couldn't create fresh_rate_enable_fops\n"); + goto fresh_rate_report_failed; + } + + //create input event + fresh_rate_input_dev = input_allocate_device(); + if (fresh_rate_input_dev == NULL) { + pr_err("Failed to allocate fresh rate input device\n"); + goto fresh_rate_report_failed; + } + fresh_rate_input_dev->name = "oneplus,fresh_rate"; + + set_bit(EV_MSC, fresh_rate_input_dev->evbit); + set_bit(MSC_RAW, fresh_rate_input_dev->mscbit); + + if (input_register_device(fresh_rate_input_dev)) { + pr_err("%s: Failed to register fresh rate input device\n", __func__); + input_free_device(fresh_rate_input_dev); + goto fresh_rate_report_failed; + } + } + + fresh_rate_input_dev_init = true; + return 0; end: if (display) devm_kfree(&pdev->dev, display); - return rc; + +fresh_rate_report_failed: + pr_err("%s: fresh rate_report_failed\n", __func__); + return 0; } int dsi_display_dev_remove(struct platform_device *pdev) @@ -5358,6 +5997,12 @@ int dsi_display_dev_remove(struct platform_device *pdev) platform_set_drvdata(pdev, NULL); devm_kfree(&pdev->dev, display); + + //unregister_device + pr_err("unregister_device fresh_rate_input_dev...\n"); + input_unregister_device(fresh_rate_input_dev); + input_free_device(fresh_rate_input_dev); + return rc; } @@ -5567,6 +6212,7 @@ static int dsi_display_ext_get_mode_info(struct drm_connector *connector, if (!drm_mode || !mode_info) return -EINVAL; + SDE_EVT32(mode_info, ((unsigned long long)mode_info) >> 32, 0x9999); memset(mode_info, 0, sizeof(*mode_info)); mode_info->frame_rate = drm_mode->vrefresh; mode_info->vtotal = drm_mode->vtotal; @@ -6150,10 +6796,6 @@ int dsi_display_get_modes(struct dsi_display *display, panel_mode.pixel_clk_khz *= display->ctrl_count; } - /* pixel overlap is not supported for single dsi panels */ - if (display->ctrl_count == 1) - panel_mode.priv_info->overlap_pixels = 0; - start = array_idx; for (i = 0; i < num_dfps_rates; i++) { @@ -6189,6 +6831,7 @@ int dsi_display_get_modes(struct dsi_display *display, exit: *out_modes = display->modes; + primary_display = display; rc = 0; error: @@ -6302,16 +6945,16 @@ int dsi_display_find_mode(struct dsi_display *display, } /** - * dsi_display_validate_mode_change() - Validate mode change case. + * dsi_display_validate_mode_change() - Validate if varaible refresh case. * @display: DSI display handle. - * @cur_mode: Current mode. - * @adj_mode: Mode to be set. + * @cur_dsi_mode: Current DSI mode. + * @mode: Mode value structure to be validated. * MSM_MODE_FLAG_SEAMLESS_VRR flag is set if there * is change in fps but vactive and hactive are same. - * DSI_MODE_FLAG_DYN_CLK flag is set if there - * is change in clk but vactive and hactive are same. * Return: error code. */ + u32 mode_fps = 90; +EXPORT_SYMBOL(mode_fps); int dsi_display_validate_mode_change(struct dsi_display *display, struct dsi_display_mode *cur_mode, struct dsi_display_mode *adj_mode) @@ -6320,6 +6963,9 @@ int dsi_display_validate_mode_change(struct dsi_display *display, struct dsi_dfps_capabilities dfps_caps; struct dsi_dyn_clk_caps *dyn_clk_caps; + struct msm_drm_notifier notifier_data; + int dynamic_fps; + if (!display || !adj_mode) { pr_err("Invalid params\n"); return -EINVAL; @@ -6333,38 +6979,57 @@ int dsi_display_validate_mode_change(struct dsi_display *display, mutex_lock(&display->display_lock); if ((cur_mode->timing.v_active == adj_mode->timing.v_active) && - (cur_mode->timing.h_active == adj_mode->timing.h_active)) { + (cur_mode->timing.h_active == adj_mode->timing.h_active)) { /* dfps change use case */ if (cur_mode->timing.refresh_rate != adj_mode->timing.refresh_rate) { dsi_panel_get_dfps_caps(display->panel, &dfps_caps); - if (dfps_caps.dfps_support) { - pr_debug("Mode switch is seamless variable refresh\n"); - adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR; - SDE_EVT32(cur_mode->timing.refresh_rate, - adj_mode->timing.refresh_rate, - cur_mode->timing.h_front_porch, - adj_mode->timing.h_front_porch); + + if (mode_fps != adj_mode->timing.refresh_rate) { + mode_fps = adj_mode->timing.refresh_rate; + dynamic_fps = mode_fps; + notifier_data.data = &dynamic_fps; + notifier_data.id = MSM_DRM_PRIMARY_DISPLAY; + pr_err("set fps: %d, fresh_rate_report_enable : %d\n", dynamic_fps, fresh_rate_report_enable); + msm_drm_notifier_call_chain(MSM_DRM_EARLY_EVENT_BLANK, ¬ifier_data); + + if (fresh_rate_report_enable) { + input_event(fresh_rate_input_dev, EV_MSC, MSC_RAW, mode_fps); + input_sync(fresh_rate_input_dev); + } + + } + + if (!dfps_caps.dfps_support) { + pr_err("invalid mode dfps not supported\n"); + rc = -ENOTSUPP; + goto error; } + pr_debug("Mode switch is seamless variable refresh\n"); + adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR; + SDE_EVT32(cur_mode->timing.refresh_rate, + adj_mode->timing.refresh_rate, + cur_mode->timing.h_front_porch, + adj_mode->timing.h_front_porch); } /* dynamic clk change use case */ if (cur_mode->pixel_clk_khz != adj_mode->pixel_clk_khz) { dyn_clk_caps = &(display->panel->dyn_clk_caps); - if (dyn_clk_caps->dyn_clk_support) { - pr_debug("dynamic clk change detected\n"); - if (adj_mode->dsi_mode_flags - & DSI_MODE_FLAG_VRR) { - pr_err("dfps and dyn clk not supported in same commit\n"); - rc = -ENOTSUPP; - goto error; - } - - adj_mode->dsi_mode_flags |= - DSI_MODE_FLAG_DYN_CLK; - SDE_EVT32(cur_mode->pixel_clk_khz, - adj_mode->pixel_clk_khz); + if (!dyn_clk_caps->dyn_clk_support) { + pr_err("dyn clk change not supported\n"); + rc = -ENOTSUPP; + goto error; + } + if (adj_mode->dsi_mode_flags & DSI_MODE_FLAG_VRR) { + pr_err("dfps and dyn clk not supported in same commit\n"); + rc = -ENOTSUPP; + goto error; } + pr_debug("dynamic clk change detected\n"); + adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_DYN_CLK; + SDE_EVT32(cur_mode->pixel_clk_khz, + adj_mode->pixel_clk_khz); } } @@ -6474,6 +7139,8 @@ int dsi_display_set_mode(struct dsi_display *display, } memcpy(display->panel->cur_mode, &adj_mode, sizeof(adj_mode)); + + mode_fps = display->panel->cur_mode->timing.refresh_rate; error: mutex_unlock(&display->display_lock); return rc; @@ -7146,6 +7813,7 @@ int dsi_display_pre_kickoff(struct drm_connector *connector, int i; bool enable; + SDE_ATRACE_BEGIN("dsi_display_pre_kickoff"); /* check and setup MISR */ if (display->misr_enable) _dsi_display_setup_misr(display); @@ -7196,6 +7864,7 @@ int dsi_display_pre_kickoff(struct drm_connector *connector, mutex_unlock(&display->display_lock); } + SDE_ATRACE_END("dsi_display_pre_kickoff"); return rc; } @@ -7258,6 +7927,8 @@ int dsi_display_enable(struct dsi_display *display) /* Engine states and panel states are populated during splash * resource init and hence we return early */ + SDE_ATRACE_BEGIN("dsi_display_enable"); + if (display->is_cont_splash_enabled) { dsi_display_config_ctrl_for_cont_splash(display); @@ -7340,6 +8011,8 @@ int dsi_display_enable(struct dsi_display *display) error: mutex_unlock(&display->display_lock); SDE_EVT32(SDE_EVTLOG_FUNC_EXIT); + + SDE_ATRACE_END("dsi_display_enable"); return rc; } @@ -7451,25 +8124,2295 @@ int dsi_display_update_pps(char *pps_cmd, void *disp) return 0; } - -int dsi_display_unprepare(struct dsi_display *display) +int dsi_display_set_acl_mode(struct drm_connector *connector, int level) { + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; int rc = 0; - if (!display) { - pr_err("Invalid params\n"); - return -EINVAL; - } + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; - SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY); - mutex_lock(&display->display_lock); + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; - rc = dsi_display_wake_up(display); - if (rc) - pr_err("[%s] display wake up failed, rc=%d\n", - display->name, rc); + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; - rc = dsi_panel_unprepare(display->panel); + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->acl_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_acl_mode(panel, level); + if (rc) + pr_err("unable to set acl mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_acl_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->acl_mode; +} + +int dsi_display_get_gamma_para(struct dsi_display *dsi_display, struct dsi_panel *panel) +{ + int i = 0; + int j = 0; + int rc = 0; + int flags = 0; + char fb[13] = {0}; + //char c8[135] = {0}; + //char c9[180] = {0}; + char b3[47] = {0}; + char fb_temp[13] = {0}; + char c8_temp[135] = {0}; + char c9_temp[180] = {0}; + char b3_temp[47] = {0}; + char gamma_para_60hz[452] = {0}; + char gamma_para_backup[413] = {0}; + int check_sum_60hz = 0; + + struct dsi_cmd_desc *cmds; + struct dsi_display_mode *mode; + struct dsi_display_ctrl *m_ctrl; + + pr_err("%s start\n", __func__); + + m_ctrl = &dsi_display->ctrl[dsi_display->cmd_master_idx]; + if (!panel || !m_ctrl) + return -EINVAL; + + rc = dsi_display_cmd_engine_enable(dsi_display); + if (rc) { + pr_err("cmd engine enable failed\n"); + return -EINVAL; + } + + dsi_panel_acquire_panel_lock(panel); + mode = panel->cur_mode; + +/* Read 60hz gamma para */ + memcpy(gamma_para_backup, gamma_para[0], 413); + do { + check_sum_60hz = 0; + if (j > 0) { + pr_err("Failed to read the 60hz gamma parameters %d!", j); + for (i = 0; i < 52; i++) { + if (i != 51) { + pr_err("[60hz][%d]0x%02X,[%d]0x%02X,[%d]0x%02X,[%d]0x%02X,[%d]0x%02X,[%d]0x%02X,[%d]0x%02X,[%d]0x%02X", + i*8, gamma_para[0][i*8], i*8+1, gamma_para[0][i*8+1], i*8+2, gamma_para[0][i*8+2], i*8+3, gamma_para[0][i*8+3], i*8+4, gamma_para[0][i*8+4], + i*8+5, gamma_para[0][i*8+5], i*8+6, gamma_para[0][i*8+6], i*8+7, gamma_para[0][i*8+7]); + } + else { + pr_err("[60hz][%d]0x%02X,[%d]0x%02X,[%d]0x%02X,[%d]0x%02X,[%d]0x%02X", + i*8, gamma_para[0][i*8], i*8+1, gamma_para[0][i*8+1], i*8+2, gamma_para[0][i*8+2], i*8+3, gamma_para[0][i*8+3], i*8+4, gamma_para[0][i*8+4]); + } + } + mdelay(1000); + } + for(i = 0; i < 452; i++) + { + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_GAMMA_FLASH_PRE_READ_1); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_GAMMA_FLASH_PRE_READ_1 command\n"); + goto error; + } + + rc = dsi_panel_gamma_read_address_setting(panel, i); + if (rc) { + pr_err("Failed to set gamma read address\n"); + goto error; + } + + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_GAMMA_FLASH_PRE_READ_2); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_GAMMA_FLASH_PRE_READ_2 command\n"); + goto error; + } + + flags = 0; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_GAMMA_FLASH_READ_FB].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + if (!m_ctrl->ctrl->vaddr) + goto error; + cmds->msg.rx_buf = fb_temp; + cmds->msg.rx_len = 13; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) { + pr_err("Failed to read DSI_CMD_SET_GAMMA_FLASH_READ_FB\n"); + goto error; + } + memcpy(fb, cmds->msg.rx_buf, 13); + + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_LEVEL2_KEY_DISABLE); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_LEVEL2_KEY_DISABLE command\n"); + goto error; + } + + if (i < 135) { + gamma_para[0][i+18] = fb[12]; + } + else if (i < 315) { + gamma_para[0][i+26] = fb[12]; + } + else if (i < 360) { + gamma_para[0][i+43] = fb[12]; + } + + gamma_para_60hz[i] = fb[12]; + if (i < 449) { + check_sum_60hz = gamma_para_60hz[i] + check_sum_60hz; + } + j++; + } + } + while ((check_sum_60hz != (gamma_para_60hz[450] << 8) + gamma_para_60hz[451]) && (j < 10)); + + if (check_sum_60hz == (gamma_para_60hz[450] << 8) + gamma_para_60hz[451]) { + pr_err("Read 60hz gamma done\n"); + } + else { + pr_err("Failed to read 60hz gamma, use default 60hz gamma.\n"); + memcpy(gamma_para[0], gamma_para_backup, 413); + gamma_read_flag = GAMMA_READ_ERROR; + } + +/* Read 90hz gamma para */ + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_LEVEL2_KEY_ENABLE); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_LEVEL2_KEY_ENABLE command\n"); + goto error; + } + + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_GAMMA_OTP_READ_C8_SMRPS); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_GAMMA_OTP_READ_C8_SMRPS command\n"); + goto error; + } + + flags = 0; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_GAMMA_OTP_READ_C8].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds->msg.rx_buf = c8_temp; + cmds->msg.rx_len = 135; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) { + pr_err("Failed to read DSI_CMD_SET_GAMMA_OTP_READ_C8\n"); + goto error; + } + memcpy(&gamma_para[1][18], cmds->msg.rx_buf, 135); + + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_GAMMA_OTP_READ_C9_SMRPS); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_GAMMA_OTP_READ_C9_SMRPS command\n"); + goto error; + } + + flags = 0; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_GAMMA_OTP_READ_C9].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds->msg.rx_buf = c9_temp; + cmds->msg.rx_len = 180; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) { + pr_err("Failed to read DSI_CMD_SET_GAMMA_OTP_READ_C9\n"); + goto error; + } + memcpy(&gamma_para[1][161], cmds->msg.rx_buf, 180); + + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_GAMMA_OTP_READ_B3_SMRPS); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_GAMMA_OTP_READ_C9_SMRPS command\n"); + goto error; + } + + flags = 0; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_GAMMA_OTP_READ_B3].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds->msg.rx_buf = b3_temp; + cmds->msg.rx_len = 47; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) { + pr_err("Failed to read DSI_CMD_SET_GAMMA_OTP_READ_B3\n"); + goto error; + } + memcpy(b3, cmds->msg.rx_buf, 47); + memcpy(&gamma_para[1][358], &b3[2], 45); + + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_LEVEL2_KEY_DISABLE); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_GAMMA_OTP_READ_C9_SMRPS command\n"); + goto error; + } + pr_err("Read 90hz gamma done\n"); + +error: + dsi_panel_release_panel_lock(panel); + dsi_display_cmd_engine_disable(dsi_display); + pr_err("%s end\n", __func__); + return rc; +} + +int dsi_display_gamma_read(struct dsi_display *dsi_display) +{ + int rc = 0; + struct dsi_panel *panel = NULL; + + pr_err("%s start\n", __func__); + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + mutex_lock(&dsi_display->display_lock); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI clocks, rc=%d\n", dsi_display->name, rc); + goto error; + } + + dsi_display_get_gamma_para(dsi_display, panel); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI clocks, rc=%d\n", dsi_display->name, rc); + goto error; + } + +error: + mutex_unlock(&dsi_display->display_lock); + pr_err("%s end\n", __func__); + return rc; +} + +void dsi_display_gamma_read_work(struct work_struct *work) +{ + struct dsi_display *dsi_display; + + dsi_display = get_main_display(); + + if (((dsi_display->panel->panel_production_info & 0x0F) == 0x0C) + || ((dsi_display->panel->panel_production_info & 0x0F) == 0x0E) + || ((dsi_display->panel->panel_production_info & 0x0F) == 0x0D)) + dsi_display_gamma_read(dsi_display); + + dsi_panel_parse_gamma_cmd_sets(); +} + +int dsi_display_read_serial_number(struct dsi_display *dsi_display, + struct dsi_panel *panel, char *buf, int len) +{ + int rc = 0; + int flags = 0; + int code_info = 0; + int stage_info = 0; + int prodution_info = 0; + struct dsi_cmd_desc *cmds; + struct dsi_display_mode *mode; + struct dsi_display_ctrl *m_ctrl; + + pr_err("%s start\n", __func__); + + m_ctrl = &dsi_display->ctrl[dsi_display->cmd_master_idx]; + + if (!panel || !m_ctrl) + return -EINVAL; + + rc = dsi_display_cmd_engine_enable(dsi_display); + if (rc) { + pr_err("cmd engine enable failed\n"); + return -EINVAL; + } + + dsi_panel_acquire_panel_lock(panel); + mode = panel->cur_mode; + + if (strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0) { + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_LCDINFO_PRE); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_LCDINFO_PRE commands\n"); + goto error; + } + } + + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_SERIAL_NUMBER].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + if (!m_ctrl->ctrl->vaddr) + goto error; + cmds->msg.rx_buf = buf; + cmds->msg.rx_len = len; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) + pr_err("Failed to get panel serial number, rc=%d\n", rc); + + if (strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0) { + + flags = 0; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_CODE_INFO].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + if (!m_ctrl->ctrl->vaddr) + goto error; + cmds->msg.rx_buf = &code_info; + cmds->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) + pr_err("Failed to get code info, rc=%d\n", rc); + + panel->panel_code_info = code_info & 0xff; + pr_err("Code info is 0x%X\n", panel->panel_code_info); + + flags = 0; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_STAGE_INFO].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + if (!m_ctrl->ctrl->vaddr) + goto error; + cmds->msg.rx_buf = &stage_info; + cmds->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) + pr_err("Failed to get stage info, rc=%d\n", rc); + + panel->panel_stage_info = stage_info & 0xff; + pr_err("Stage info is 0x%X\n", panel->panel_stage_info); + + flags = 0; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_PRODUCTION_INFO].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + if (!m_ctrl->ctrl->vaddr) + goto error; + cmds->msg.rx_buf = &prodution_info; + cmds->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) + pr_err("Failed to get production info, rc=%d\n", rc); + + panel->panel_production_info = prodution_info & 0xff; + pr_err("Production info is 0x%X\n", panel->panel_production_info); + + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_LCDINFO_POST); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_LCDINFO_POST commands\n"); + goto error; + } + } + + error: + dsi_panel_release_panel_lock(panel); + dsi_display_cmd_engine_disable(dsi_display); + pr_err("%s end\n", __func__); + + return rc; +} + +int dsi_display_get_serial_number(struct drm_connector *connector) +{ + struct dsi_display_mode *mode; + struct dsi_panel *panel = NULL; + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + char buf[32]; + int panel_year = 0; + int panel_mon = 0; + int panel_day = 0; + int panel_hour = 0; + int panel_min = 0; + int panel_sec = 0; + int len = 0; + int count; + int rc = 0; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + mutex_lock(&dsi_display->display_lock); + + if (!dsi_panel_initialized(panel) || !panel->cur_mode) + goto error; + + mode = panel->cur_mode; + count = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_SERIAL_NUMBER].count; + if (count) { + len = panel->panel_min_index; + if (len > sizeof(buf)) { + pr_err("len is large than buf size!!!\n"); + goto error; + } + + if ((panel->panel_year_index > len) || (panel->panel_mon_index > len) + || (panel->panel_day_index > len) || (panel->panel_hour_index > len) + || (panel->panel_min_index > len)) { + pr_err("Panel serial number index not corrected.\n"); + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_ALL_CLKS, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + memset(buf, 0, sizeof(buf)); + dsi_display_read_serial_number(dsi_display, panel, buf, len); + memcpy(panel->buf_id, buf, 32); + panel_year = 2011 + ((buf[panel->panel_year_index - 1] >> 4) & 0x0f); + if (panel_year == 2011) + panel_year = 0; + panel_mon = buf[panel->panel_mon_index - 1] & 0x0f; + if ((panel_mon > 12) || (panel_mon < 1)) { + pr_err("Panel Mon not corrected.\n"); + panel_mon = 0; + } + panel_day = buf[panel->panel_day_index - 1] & 0x3f; + if ((panel_day > 31) || (panel_day < 1)) { + pr_err("Panel Day not corrected.\n"); + panel_day = 0; + } + panel_hour = buf[panel->panel_hour_index - 1] & 0x3f; + if ((panel_hour > 23) || (panel_hour < 0)) { + pr_err("Panel Hour not corrected.\n"); + panel_hour = 0; + } + panel_min = buf[panel->panel_min_index - 1] & 0x3f; + if ((panel_min > 59) || (panel_min < 0)) { + pr_err("Panel Min not corrected.\n"); + panel_min = 0; + } + panel_sec = buf[panel->panel_sec_index - 1] & 0x3f; + if ((panel_sec > 59) || (panel_sec < 0)) { + pr_err("Panel sec not corrected.\n"); + panel_sec = 0; + } + panel->panel_year = panel_year; + panel->panel_mon = panel_mon; + panel->panel_day = panel_day; + panel->panel_hour = panel_hour; + panel->panel_min = panel_min; + panel->panel_sec = panel_sec; + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_ALL_CLKS, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to enable DSI clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + } else { + pr_err("This panel not support serial number.\n"); + } + +error: + mutex_unlock(&dsi_display->display_lock); + pr_err("%s end\n", __func__); + return 0; +} + +int dsi_display_get_serial_number_year(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_year; +} + +int dsi_display_get_serial_number_mon(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_mon; +} + +int dsi_display_get_serial_number_day(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_day; +} + +int dsi_display_get_serial_number_hour(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_hour; +} + +int dsi_display_get_serial_number_min(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_min; +} + +int dsi_display_get_serial_number_sec(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_sec; +} + +int dsi_display_get_code_info(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_code_info; +} + +int dsi_display_get_stage_info(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_stage_info; +} + +int dsi_display_get_production_info(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_production_info; +} + +int dsi_display_get_serial_number_AT(struct drm_connector *connector) +{ + struct dsi_display_mode *mode; + struct dsi_panel *panel = NULL; + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + char buf[32]; + int panel_year = 0; + int panel_mon = 0; + int panel_day = 0; + int panel_hour = 0; + int panel_min = 0; + int panel_sec = 0; + int len = 0; + u32 count; + int rc = 0; + uint64_t serial_number; + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + mutex_lock(&dsi_display->display_lock); + + if (!dsi_panel_initialized(panel) || !panel->cur_mode) { + goto error; + } + mode = panel->cur_mode; + count = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_SERIAL_NUMBER].count; + + if (count) { + + len = panel->panel_min_index; + if (len > sizeof(buf)) { + pr_err("len is large than buf size!!!\n" ); + goto error; + } + + if ((panel->panel_year_index > len) || (panel->panel_mon_index > len) + || (panel->panel_day_index > len) || (panel->panel_hour_index > len) + || (panel->panel_min_index > len)) { + pr_err("Panel serial number index not corrected.\n"); + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_ALL_CLKS, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + memset(buf, 0, sizeof(buf)); + dsi_display_read_serial_number(dsi_display, panel, buf, len); + memcpy(panel->buf_id, buf, 32); + + panel_year = 2011 + ((buf[panel->panel_year_index-1] >> 4) & 0x0f); + if (panel_year == 2011){ + panel_year = 0; + } + panel_mon = buf[panel->panel_mon_index-1] & 0x0f; + if ((panel_mon > 12) || (panel_mon < 1)){ + pr_err("Panel Mon not corrected.\n"); + panel_mon = 0; + } + panel_day = buf[panel->panel_day_index-1] & 0x3f; + if ((panel_day > 31) || (panel_day < 1)){ + pr_err("Panel Day not corrected.\n"); + panel_day = 0; + } + panel_hour = buf[panel->panel_hour_index-1] & 0x3f; + if ((panel_hour > 23) || (panel_hour < 0)){ + pr_err("Panel Hour not corrected.\n"); + panel_hour = 0; + } + panel_min = buf[panel->panel_min_index-1] & 0x3f; + if ((panel_min > 59) || (panel_min < 0)){ + pr_err("Panel Min not corrected.\n"); + panel_min = 0; + } + panel_sec = buf[panel->panel_sec_index-1] & 0x3f; + if ((panel_sec > 59) || (panel_sec < 0)){ + pr_err("Panel sec not corrected.\n"); + panel_sec = 0; + } +/* + serial_number = ((uint64_t)panel_year << 56) + + ((uint64_t)panel_mon << 48) + + ((uint64_t)panel_day << 40) + + ((uint64_t)panel_hour << 32) + + ((uint64_t)panel_min << 24) + + ((uint64_t)panel_sec << 16) + + ((uint64_t)0 << 8) + + ((uint64_t)0); +*/ + serial_number = (uint64_t)panel_year * 10000000000 + (uint64_t)panel_mon * 100000000 + (uint64_t)panel_day * 1000000 + + (uint64_t)panel_hour * 10000 + (uint64_t)panel_min * 100 + (uint64_t)panel_sec; + + dsi_display_get_serial_number_id(serial_number); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_ALL_CLKS, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to enable DSI clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + } else{ + pr_err("This panel not support serial number.\n"); + } +error: + mutex_unlock(&dsi_display->display_lock); + pr_err("%s END\n", __func__); + return 0; +} + +uint64_t dsi_display_get_serial_number_id(uint64_t serial_number) +{ + + static uint64_t serial_number_at; + + pr_err("%s start\n",__func__); + if(0 == SERIAL_NUMBER_flag) + { + serial_number_at = serial_number; + if(0 == serial_number_at) + SERIAL_NUMBER_flag = 0; + else + SERIAL_NUMBER_flag = 1; + } + + return serial_number_at; +} + + +int dsi_display_set_hbm_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->hbm_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_hbm_mode(panel, level); + if (rc) + pr_err("unable to set hbm mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_hbm_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->hbm_mode; +} + +int dsi_display_set_hbm_brightness(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return -EINVAL; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + if ((strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") != 0) && (strcmp(dsi_display->panel->name, "samsung s6e3fc2x01 cmd mode dsi panel") != 0)) { + dsi_display->panel->hbm_brightness = 0; + return 0; + } + + mutex_lock(&dsi_display->display_lock); + + panel->hbm_brightness = level; + + if (!dsi_panel_initialized(panel)) + goto error; + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_hbm_brightness(panel, level); + if (rc) + pr_err("Failed to set hbm brightness mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_hbm_brightness(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->hbm_brightness; +} + +extern int oneplus_force_screenfp; + +int dsi_display_set_fp_hbm_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->op_force_screenfp = level; + oneplus_force_screenfp=panel->op_force_screenfp; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_op_set_hbm_mode(panel, level); + if (rc) + pr_err("unable to set hbm mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + + +int dsi_display_get_fp_hbm_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->op_force_screenfp; +} + +int dsi_display_set_dci_p3_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->dci_p3_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_dci_p3_mode(panel, level); + if (rc) + pr_err("unable to set dci_p3 mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_dci_p3_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->dci_p3_mode; +} + +int dsi_display_set_night_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->night_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_night_mode(panel, level); + if (rc) + pr_err("unable to set night mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_night_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->night_mode; +} +int dsi_display_set_native_display_p3_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->naive_display_p3_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_native_display_p3_mode(panel, level); + if (rc) + pr_err("unable to set native display p3 mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_native_display_p3_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->naive_display_p3_mode; +} + +int dsi_display_set_native_display_wide_color_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->naive_display_wide_color_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_native_display_wide_color_mode(panel, level); + if (rc) + pr_err("unable to set native display p3 mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_set_native_loading_effect_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->naive_display_loading_effect_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_native_loading_effect_mode(panel, level); + if (rc) + pr_err("unable to set loading effect mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_set_customer_srgb_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->naive_display_customer_srgb_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_customer_srgb_mode(panel, level); + if (rc) + pr_err("unable to set customer srgb mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_set_customer_p3_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->naive_display_customer_p3_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_customer_p3_mode(panel, level); + if (rc) + pr_err("unable to set customer srgb mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} +int dsi_display_set_native_display_srgb_color_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->naive_display_srgb_color_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_native_display_srgb_color_mode(panel, level); + if (rc) + pr_err("unable to set native display p3 mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_native_display_srgb_color_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->naive_display_srgb_color_mode; +} + +int dsi_display_get_native_display_wide_color_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->naive_display_wide_color_mode; +} + +int dsi_display_get_native_display_loading_effect_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->naive_display_loading_effect_mode; +} +int dsi_display_get_customer_srgb_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->naive_display_customer_srgb_mode; +} +int dsi_display_get_customer_p3_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->naive_display_customer_p3_mode; +} + +int dsi_display_set_aod_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + panel->aod_mode = level; + if (strcmp(dsi_display->panel->name, "samsung s6e3fc2x01 cmd mode dsi panel") == 0){ + printk(KERN_ERR"dsi_display_set_aod_mode\n"); + }else if(strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0){ + printk(KERN_ERR"oneplus SDC 2K OLED dsi_display_set_aod_mode\n"); + }else{ + dsi_display->panel->aod_mode=0; + return 0; + } + mutex_lock(&dsi_display->display_lock); + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + rc = dsi_panel_set_aod_mode(panel, level); + if (rc) + pr_err("unable to set aod mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + + return rc; +} + +int dsi_display_get_aod_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->aod_mode; +} + +int dsi_display_set_aod_disable(struct drm_connector *connector, int disable) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + mutex_lock(&dsi_display->display_lock); + panel->aod_disable = disable; + mutex_unlock(&dsi_display->display_lock); + + return rc; +} + +int dsi_display_get_aod_disable(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->aod_disable; +} +int dsi_display_read_panel_id(struct dsi_display *dsi_display, + struct dsi_panel *panel, char* buf, int len) +{ + int rc = 0; + u32 flags = 0; + struct dsi_cmd_desc *cmds; + struct dsi_display_mode *mode; + struct dsi_display_ctrl *m_ctrl; + int retry_times; + + m_ctrl = &dsi_display->ctrl[dsi_display->cmd_master_idx]; + + if (!panel || !m_ctrl) + return -EINVAL; + + rc = dsi_display_cmd_engine_enable(dsi_display); + if (rc) { + pr_err("cmd engine enable failed\n"); + return -EINVAL; + } + + dsi_panel_acquire_panel_lock(panel); + + mode = panel->cur_mode; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID].cmds;; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + if (!m_ctrl->ctrl->vaddr) + goto error; + + cmds->msg.rx_buf = buf; + cmds->msg.rx_len = len; + retry_times = 0; + do { + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + retry_times++; + } while ((rc <= 0) && (retry_times < 3)); + + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + + error: + dsi_panel_release_panel_lock(panel); + + dsi_display_cmd_engine_disable(dsi_display); + + return rc; +} + +char dsi_display_ascii_to_int(char ascii, int *ascii_err) +{ + char int_value; + + if ((ascii >= 48) && (ascii <= 57)){ + int_value = ascii - 48; + } + else if ((ascii >= 65) && (ascii <= 70)) { + int_value = ascii - 65 + 10; + } + else if ((ascii >= 97) && (ascii <= 102)) { + int_value = ascii - 97 + 10; + } + else { + int_value = 0; + *ascii_err = 1; + pr_err("Bad para: %d , please enter the right value!", ascii); + } + + return int_value; +} + +int dsi_display_update_dsi_on_command(struct drm_connector *connector, const char *buf, size_t count) +{ + int i = 0; + int j = 0; + int ascii_err = 0; + unsigned int length; + char *data; + struct dsi_panel_cmd_set *set; + + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return -EINVAL; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + length = count / 3; + data = kzalloc(length + 1, GFP_KERNEL); + + for (i = 0; (buf[i+2] != 10) && (j < length); i = i+3) { + data[j] = dsi_display_ascii_to_int(buf[i], &ascii_err) << 4; + data[j] += dsi_display_ascii_to_int(buf[i+1], &ascii_err); + j++; + } + data[j] = dsi_display_ascii_to_int(buf[i], &ascii_err) << 4; + data[j] += dsi_display_ascii_to_int(buf[i+1], &ascii_err); + if (ascii_err == 1) { + pr_err("Bad Para, ignore this command\n"); + goto error; + } + + set = &panel->cur_mode->priv_info->cmd_sets[DSI_CMD_SET_ON]; + + rc = dsi_panel_update_cmd_sets_sub(set, DSI_CMD_SET_ON, data, length); + if (rc) + pr_err("Failed to update_cmd_sets_sub, rc=%d\n", rc); + +error: + kfree(data); + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +static int dsi_display_get_mipi_dsi_msg(const struct mipi_dsi_msg *msg, char* buf) +{ + int len = 0; + size_t i; + char *tx_buf = (char*)msg->tx_buf; + /* Packet Info */ + len += snprintf(buf + len, PAGE_SIZE - len, "%02X ", msg->type); + /* Last bit */ + len += snprintf(buf + len, PAGE_SIZE - len, "%02X ", (msg->flags & MIPI_DSI_MSG_LASTCOMMAND) ? 1 : 0); + len += snprintf(buf + len, PAGE_SIZE - len, "%02X ", msg->channel); + len += snprintf(buf + len, PAGE_SIZE - len, "%02X ", (unsigned int)msg->flags); + /* Delay */ + len += snprintf(buf + len, PAGE_SIZE - len, "%02X ", msg->wait_ms); + len += snprintf(buf + len, PAGE_SIZE - len, "%02X %02X ", msg->tx_len >> 8, msg->tx_len & 0x00FF); + + /* Packet Payload */ + for (i = 0 ; i < msg->tx_len ; i++) { + len += snprintf(buf + len, PAGE_SIZE - len, "%02X ", tx_buf[i]); + } + len += snprintf(buf + len, PAGE_SIZE - len, "\n"); + + return len; +} + +int dsi_display_get_dsi_on_command(struct drm_connector *connector, char *buf) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + struct dsi_panel_cmd_set *cmd; + int i = 0; + int count = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + cmd = &dsi_display->panel->cur_mode->priv_info->cmd_sets[DSI_CMD_SET_ON]; + + for (i = 0; i < cmd->count; i++) { + count += dsi_display_get_mipi_dsi_msg(&cmd->cmds[i].msg, &buf[count]); + } + + return count; +} + +int dsi_display_update_dsi_panel_command(struct drm_connector *connector, const char *buf, size_t count) +{ + int i = 0; + int j = 0; + int ascii_err = 0; + unsigned int length; + char *data; + struct dsi_panel_cmd_set *set; + + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return -EINVAL; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + if (strcmp(panel->name, "samsung dsc cmd mode oneplus dsi panel") != 0) { + return 0; + } + + mutex_lock(&dsi_display->display_lock); + + if (!dsi_panel_initialized(panel)) + goto error; + + length = count / 3; + data = kzalloc(length + 1, GFP_KERNEL); + + for (i = 0; (buf[i+2] != 10) && (j < length); i = i+3) { + data[j] = dsi_display_ascii_to_int(buf[i], &ascii_err) << 4; + data[j] += dsi_display_ascii_to_int(buf[i+1], &ascii_err); + j++; + } + data[j] = dsi_display_ascii_to_int(buf[i], &ascii_err) << 4; + data[j] += dsi_display_ascii_to_int(buf[i+1], &ascii_err); + if (ascii_err == 1) { + pr_err("Bad Para, ignore this command\n"); + kfree(data); + goto error; + } + + set = &panel->cur_mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_COMMAND]; + + rc = dsi_panel_update_cmd_sets_sub(set, DSI_CMD_SET_PANEL_COMMAND, data, length); + if (rc) + pr_err("Failed to update_cmd_sets_sub, rc=%d\n", rc); + kfree(data); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_send_dsi_panel_command(panel); + if (rc) + pr_err("Failed to send dsi panel command\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_dsi_panel_command(struct drm_connector *connector, char *buf) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + struct dsi_panel_cmd_set *cmd; + int i = 0; + int count = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + cmd = &dsi_display->panel->cur_mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_COMMAND]; + + for (i = 0; i < cmd->count; i++) + count += dsi_display_get_mipi_dsi_msg(&cmd->cmds[i].msg, &buf[count]); + + return count; +} + +int dsi_display_update_dsi_seed_command(struct drm_connector *connector, const char *buf, size_t count) +{ + int i = 0; + int j = 0; + int ascii_err = 0; + unsigned int length; + char *data; + struct dsi_panel_cmd_set *set; + + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return -EINVAL; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + if (strcmp(panel->name, "samsung dsc cmd mode oneplus dsi panel") != 0) { + return 0; + } + + mutex_lock(&dsi_display->display_lock); + + if (!dsi_panel_initialized(panel)) + goto error; + + length = count / 3; + if (length != 0x16) { + pr_err("Insufficient parameters!\n"); + goto error; + } + data = kzalloc(length + 1, GFP_KERNEL); + + for (i = 0; (buf[i+2] != 10) && (j < length); i = i+3) { + data[j] = dsi_display_ascii_to_int(buf[i], &ascii_err) << 4; + data[j] += dsi_display_ascii_to_int(buf[i+1], &ascii_err); + j++; + } + data[j] = dsi_display_ascii_to_int(buf[i], &ascii_err) << 4; + data[j] += dsi_display_ascii_to_int(buf[i+1], &ascii_err); + if (ascii_err == 1) { + pr_err("Bad Para, ignore this command\n"); + kfree(data); + goto error; + } + + set = &panel->cur_mode->priv_info->cmd_sets[DSI_CMD_SET_SEED_COMMAND]; + + if (strcmp(panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0) + data[0] = WU_SEED_REGISTER; + + rc = dsi_panel_update_dsi_seed_command(set->cmds, DSI_CMD_SET_SEED_COMMAND, data); + if (rc) + pr_err("Failed to dsi_panel_update_dsi_seed_command, rc=%d\n", rc); + kfree(data); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_send_dsi_seed_command(panel); + if (rc) + pr_err("Failed to send dsi seed command\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_dsi_seed_command(struct drm_connector *connector, char *buf) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + struct dsi_panel_cmd_set *cmd; + int i = 0; + int count = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + if (strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") != 0) { + return 0; + } + + cmd = &dsi_display->panel->cur_mode->priv_info->cmd_sets[DSI_CMD_SET_SEED_COMMAND]; + + for (i = 0; i < cmd->count; i++) { + count += dsi_display_get_mipi_dsi_msg(&cmd->cmds[i].msg, &buf[count]); + } + + return count; +} + +int dsi_display_panel_mismatch_check(struct drm_connector *connector) +{ + struct dsi_display_mode *mode; + struct dsi_panel *panel = NULL; + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + char buf[32]; + int panel_id; + u32 count; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + mutex_lock(&dsi_display->display_lock); + + if (!dsi_panel_initialized(panel) || !panel->cur_mode) { + panel->panel_mismatch = 0; + goto error; + } + + if (!panel->panel_mismatch_check) { + panel->panel_mismatch = 0; + pr_err("This hw not support panel mismatch check(dvt-mp)\n"); + goto error; + } + + mode = panel->cur_mode; + count = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID].count; + if (count) { + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_ALL_CLKS, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + memset(buf, 0, sizeof(buf)); + dsi_display_read_panel_id(dsi_display, panel, buf, 1); + + panel_id = buf[0]; + panel->panel_mismatch = (panel_id == 0x03)? 1 : 0; + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_ALL_CLKS, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to enable DSI clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + } else{ + panel->panel_mismatch = 0; + pr_err("This panel not support panel mismatch check.\n"); + } +error: + mutex_unlock(&dsi_display->display_lock); + return 0; +} + +int dsi_display_panel_mismatch(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->panel_mismatch; +} + +int dsi_display_unprepare(struct dsi_display *display) +{ + int rc = 0; + + if (!display) { + pr_err("Invalid params\n"); + return -EINVAL; + } + + SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY); + mutex_lock(&display->display_lock); + + rc = dsi_display_wake_up(display); + if (rc) + pr_err("[%s] display wake up failed, rc=%d\n", + display->name, rc); + + rc = dsi_panel_unprepare(display->panel); if (rc) pr_err("[%s] panel unprepare failed, rc=%d\n", display->name, rc); @@ -7519,6 +10462,11 @@ int dsi_display_unprepare(struct dsi_display *display) SDE_EVT32(SDE_EVTLOG_FUNC_EXIT); return rc; } +//*mark.yao@PSW.MM.Display.LCD.Stability,2018/4/28,add for support aod,hbm,seed*/ +struct dsi_display *get_main_display(void) { + return primary_display; +} +EXPORT_SYMBOL(get_main_display); static int __init dsi_display_register(void) { diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h index 4cf3cebb7d02..1d761511d173 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h @@ -417,6 +417,7 @@ int dsi_display_validate_mode_change(struct dsi_display *display, struct dsi_display_mode *cur_dsi_mode, struct dsi_display_mode *mode); +extern int msm_drm_notifier_call_chain(unsigned long val, void *v); /** * dsi_display_set_mode() - Set mode on the display. * @display: Handle to display. @@ -580,6 +581,10 @@ int dsi_display_set_tpg_state(struct dsi_display *display, bool enable); int dsi_display_clock_gate(struct dsi_display *display, bool enable); int dsi_dispaly_static_frame(struct dsi_display *display, bool enable); +uint64_t dsi_display_get_serial_number_id(uint64_t serial_number); + +int dsi_display_get_serial_number_AT(struct drm_connector *connector); + /** * dsi_display_enable_event() - enable interrupt based connector event @@ -694,4 +699,12 @@ int dsi_display_cont_splash_config(void *display); int dsi_display_get_panel_vfp(void *display, int h_active, int v_active); +extern int connector_state_crtc_index; +extern int msm_drm_notifier_call_chain(unsigned long val, void *v); + +struct dsi_display *get_main_display(void); +extern char gamma_para[2][413]; +int dsi_display_gamma_read(struct dsi_display *dsi_display); +void dsi_display_gamma_read_work(struct work_struct *work); +extern struct delayed_work *sde_esk_check_delayed_work; #endif /* _DSI_DISPLAY_H_ */ diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c index a8395de6bb7a..4915f68707c6 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c @@ -21,6 +21,8 @@ #include "sde_connector.h" #include "dsi_drm.h" #include "sde_trace.h" +#include "sde_dbg.h" + #define to_dsi_bridge(x) container_of((x), struct dsi_bridge, base) #define to_dsi_state(x) container_of((x), struct dsi_connector_state, base) @@ -384,7 +386,7 @@ static bool dsi_bridge_mode_fixup(struct drm_bridge *bridge, if (rc) { pr_err("[%s] seamless mode mismatch failure rc=%d\n", c_bridge->display->name, rc); - return false; +// return false; } cur_mode = crtc_state->crtc->mode; @@ -446,7 +448,7 @@ int dsi_conn_get_mode_info(struct drm_connector *connector, if (!dsi_mode.priv_info) return -EINVAL; - + SDE_EVT32(mode_info, ((unsigned long long)mode_info) >> 32, connector, ((unsigned long long)connector) >> 32, 0x9999); memset(mode_info, 0, sizeof(*mode_info)); timing = &dsi_mode.timing; @@ -458,7 +460,6 @@ int dsi_conn_get_mode_info(struct drm_connector *connector, mode_info->clk_rate = dsi_drm_find_bit_clk_rate(display, drm_mode); mode_info->mdp_transfer_time_us = dsi_mode.priv_info->mdp_transfer_time_us; - mode_info->overlap_pixels = dsi_mode.priv_info->overlap_pixels; memcpy(&mode_info->topology, &dsi_mode.priv_info->topology, sizeof(struct msm_display_topology)); @@ -476,7 +477,7 @@ int dsi_conn_get_mode_info(struct drm_connector *connector, memcpy(&mode_info->roi_caps, &dsi_mode.priv_info->roi_caps, sizeof(dsi_mode.priv_info->roi_caps)); } - + SDE_EVT32(dsi_mode.priv_info->dsc_enabled, mode_info->clk_rate, mode_info->frame_rate, 0x9999); return 0; } diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c old mode 100644 new mode 100755 index de28a2e8964d..ae029049ca95 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -19,11 +19,24 @@ #include #include #include