From 2559b4b0452a110b41383ca9b9037b091e132a2a Mon Sep 17 00:00:00 2001 From: Rahul Shahare Date: Fri, 9 Apr 2021 16:03:50 +0530 Subject: [PATCH 01/55] defconfig: Enable config for msm8937_64 Enable config to support SHIPPING_API_LEVEL 30 for msm8937_64. Change-Id: I6266ee8e3e918b0bea8be7fbc30c1634eb9d56b2 Signed-off-by: Rahul Shahare --- arch/arm64/configs/vendor/msm8937-perf_defconfig | 10 +++++----- arch/arm64/configs/vendor/msm8937_defconfig | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/configs/vendor/msm8937-perf_defconfig b/arch/arm64/configs/vendor/msm8937-perf_defconfig index 6f3bf944a570..886147472348 100644 --- a/arch/arm64/configs/vendor/msm8937-perf_defconfig +++ b/arch/arm64/configs/vendor/msm8937-perf_defconfig @@ -16,17 +16,16 @@ CONFIG_RCU_FAST_NO_HZ=y CONFIG_RCU_NOCB_CPU=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_IKHEADERS=y CONFIG_LOG_CPU_MAX_BUF_SHIFT=17 CONFIG_BLK_CGROUP=y CONFIG_DEBUG_BLK_CGROUP=y -CONFIG_RT_GROUP_SCHED=y CONFIG_CGROUP_FREEZER=y CONFIG_CPUSETS=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_BPF=y CONFIG_SCHED_CORE_CTL=y CONFIG_NAMESPACES=y -# CONFIG_UTS_NS is not set # CONFIG_PID_NS is not set CONFIG_SCHED_AUTOGROUP=y CONFIG_SCHED_TUNE=y @@ -40,6 +39,7 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_FHANDLE is not set CONFIG_KALLSYMS_ALL=y CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT_ALWAYS_ON=y CONFIG_EMBEDDED=y # CONFIG_COMPAT_BRK is not set CONFIG_PROFILING=y @@ -84,7 +84,6 @@ CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y CONFIG_PANIC_ON_REFCOUNT_ERROR=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_MODULE_SIG=y CONFIG_MODULE_SIG_FORCE=y @@ -239,6 +238,7 @@ CONFIG_NET_EMATCH_TEXT=y CONFIG_NET_CLS_ACT=y CONFIG_QRTR=y CONFIG_QRTR_SMD=y +CONFIG_BPF_JIT=y CONFIG_BT=y # CONFIG_BT_BREDR is not set # CONFIG_BT_LE is not set @@ -286,6 +286,7 @@ CONFIG_DM_BOW=y CONFIG_NETDEVICES=y CONFIG_DUMMY=y CONFIG_TUN=y +CONFIG_VETH=y # CONFIG_NET_VENDOR_AMAZON is not set CONFIG_MSM_RMNET_BAM=y # CONFIG_NET_VENDOR_EZCHIP is not set @@ -328,6 +329,7 @@ CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_XPAD=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y CONFIG_INPUT_QPNP_POWER_ON=y @@ -434,7 +436,6 @@ CONFIG_HID_MICROSOFT=y CONFIG_HID_MULTITOUCH=y CONFIG_HID_SONY=y CONFIG_USB_HIDDEV=y -CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_MON=y CONFIG_USB_EHCI_HCD=y @@ -616,7 +617,6 @@ CONFIG_SECURITY_SELINUX=y CONFIG_SECURITY_SMACK=y CONFIG_CRYPTO_GCM=y CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_TWOFISH=y CONFIG_CRYPTO_ANSI_CPRNG=y CONFIG_CRYPTO_DEV_QCE=y diff --git a/arch/arm64/configs/vendor/msm8937_defconfig b/arch/arm64/configs/vendor/msm8937_defconfig index bce8b5d83041..ddb40ba139fb 100644 --- a/arch/arm64/configs/vendor/msm8937_defconfig +++ b/arch/arm64/configs/vendor/msm8937_defconfig @@ -16,10 +16,10 @@ CONFIG_RCU_FAST_NO_HZ=y CONFIG_RCU_NOCB_CPU=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_IKHEADERS=y CONFIG_LOG_CPU_MAX_BUF_SHIFT=17 CONFIG_BLK_CGROUP=y CONFIG_DEBUG_BLK_CGROUP=y -CONFIG_RT_GROUP_SCHED=y CONFIG_CGROUP_FREEZER=y CONFIG_CPUSETS=y CONFIG_CGROUP_CPUACCT=y @@ -27,7 +27,6 @@ CONFIG_CGROUP_BPF=y CONFIG_CGROUP_DEBUG=y CONFIG_SCHED_CORE_CTL=y CONFIG_NAMESPACES=y -# CONFIG_UTS_NS is not set # CONFIG_PID_NS is not set CONFIG_SCHED_AUTOGROUP=y CONFIG_SCHED_TUNE=y @@ -41,6 +40,7 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y # CONFIG_FHANDLE is not set CONFIG_KALLSYMS_ALL=y CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT_ALWAYS_ON=y CONFIG_EMBEDDED=y # CONFIG_COMPAT_BRK is not set CONFIG_PROFILING=y @@ -87,7 +87,6 @@ CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y CONFIG_PANIC_ON_REFCOUNT_ERROR=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_MODULE_SIG=y CONFIG_MODULE_SIG_FORCE=y @@ -246,6 +245,7 @@ CONFIG_NET_CLS_ACT=y CONFIG_DNS_RESOLVER=y CONFIG_QRTR=y CONFIG_QRTR_SMD=y +CONFIG_BPF_JIT=y CONFIG_BT=y # CONFIG_BT_BREDR is not set # CONFIG_BT_LE is not set @@ -294,6 +294,7 @@ CONFIG_DM_BOW=y CONFIG_NETDEVICES=y CONFIG_DUMMY=y CONFIG_TUN=y +CONFIG_VETH=y # CONFIG_NET_VENDOR_AMAZON is not set CONFIG_MSM_RMNET_BAM=y # CONFIG_NET_VENDOR_EZCHIP is not set @@ -336,6 +337,7 @@ CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_XPAD=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y CONFIG_INPUT_QPNP_POWER_ON=y @@ -447,7 +449,6 @@ CONFIG_HID_MICROSOFT=y CONFIG_HID_MULTITOUCH=y CONFIG_HID_SONY=y CONFIG_USB_HIDDEV=y -CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_MON=y CONFIG_USB_EHCI_HCD=y @@ -635,7 +636,6 @@ CONFIG_SECURITY_SELINUX=y CONFIG_SECURITY_SMACK=y CONFIG_CRYPTO_GCM=y CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_TWOFISH=y CONFIG_CRYPTO_ANSI_CPRNG=y CONFIG_CRYPTO_DEV_QCE=y From 9054a9c24b56e535f999917fa3770de1e8c159d1 Mon Sep 17 00:00:00 2001 From: Vandana Jain Date: Fri, 16 Apr 2021 13:19:58 +0530 Subject: [PATCH 02/55] msm: camera: QM215 delay during power up sequence Add a delay of 60ms for QM215 target during power up sequence. Change-Id: Ia9dc30bc83a307b636eb7c6a42bf9f04c1cc36aa Signed-off-by: Vandana Jain --- drivers/media/platform/msm/camera_v2/sensor/msm_sensor.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/msm/camera_v2/sensor/msm_sensor.c b/drivers/media/platform/msm/camera_v2/sensor/msm_sensor.c index 5f72b555e0d2..e75fcadd3be0 100644 --- a/drivers/media/platform/msm/camera_v2/sensor/msm_sensor.c +++ b/drivers/media/platform/msm/camera_v2/sensor/msm_sensor.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2011-2018, 2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2011-2018, 2021, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -205,6 +205,9 @@ int msm_sensor_power_up(struct msm_sensor_ctrl_t *s_ctrl) &msm_sensor_secure_func_tbl; } } +#if IS_ENABLED(CONFIG_ARCH_QM215) + msleep(60); +#endif rc = msm_camera_power_up(power_info, s_ctrl->sensor_device_type, sensor_i2c_client); if (rc < 0) From dc880ca423502fdc764212a806ab36d438cb3edb Mon Sep 17 00:00:00 2001 From: Kyle Yan Date: Fri, 1 Dec 2017 17:05:59 -0800 Subject: [PATCH 03/55] soc: qcom: pil: Reuse carveout region for mdt header Currently we allocate a new dma region for our image headers to pass into TZ for image verification. Instead reuse the previously allocated region for the main firmware body to store the image header to avoid having to allocate more memory than needed. Change-Id: I1e50df2b417d9823c4e75f28134a3f9e078463aa Signed-off-by: Kyle Yan Signed-off-by: Archana Sriram --- drivers/soc/qcom/peripheral-loader.c | 23 +++++++++++-------- drivers/soc/qcom/peripheral-loader.h | 4 ++-- drivers/soc/qcom/pil-msa.c | 11 ++++++---- drivers/soc/qcom/subsys-pil-tz.c | 33 +++++++++++++++++----------- 4 files changed, 43 insertions(+), 28 deletions(-) diff --git a/drivers/soc/qcom/peripheral-loader.c b/drivers/soc/qcom/peripheral-loader.c index 5c55fb318904..9a3c53721a42 100644 --- a/drivers/soc/qcom/peripheral-loader.c +++ b/drivers/soc/qcom/peripheral-loader.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2010-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2010-2021, The Linux Foundation. All rights reserved. */ #include @@ -776,11 +776,12 @@ static int pil_init_entry_addr(struct pil_priv *priv, const struct pil_mdt *mdt) } static int pil_alloc_region(struct pil_priv *priv, phys_addr_t min_addr, - phys_addr_t max_addr, size_t align) + phys_addr_t max_addr, size_t align, + size_t mdt_size) { void *region; size_t size = max_addr - min_addr; - size_t aligned_size; + size_t aligned_size = max(size, mdt_size); /* Don't reallocate due to fragmentation concerns, just sanity check */ if (priv->region) { @@ -820,7 +821,8 @@ static int pil_alloc_region(struct pil_priv *priv, phys_addr_t min_addr, return 0; } -static int pil_setup_region(struct pil_priv *priv, const struct pil_mdt *mdt) +static int pil_setup_region(struct pil_priv *priv, const struct pil_mdt *mdt, + size_t mdt_size) { const struct elf32_phdr *phdr; phys_addr_t min_addr_r, min_addr_n, max_addr_r, max_addr_n, start, end; @@ -865,7 +867,8 @@ static int pil_setup_region(struct pil_priv *priv, const struct pil_mdt *mdt) max_addr_r = ALIGN(max_addr_r, SZ_4K); if (relocatable) { - ret = pil_alloc_region(priv, min_addr_r, max_addr_r, align); + ret = pil_alloc_region(priv, min_addr_r, max_addr_r, align, + mdt_size); } else { priv->region_start = min_addr_n; priv->region_end = max_addr_n; @@ -896,14 +899,15 @@ static int pil_cmp_seg(void *priv, struct list_head *a, struct list_head *b) return ret; } -static int pil_init_mmap(struct pil_desc *desc, const struct pil_mdt *mdt) +static int pil_init_mmap(struct pil_desc *desc, const struct pil_mdt *mdt, + size_t mdt_size) { struct pil_priv *priv = desc->priv; const struct elf32_phdr *phdr; struct pil_seg *seg; int i, ret; - ret = pil_setup_region(priv, mdt); + ret = pil_setup_region(priv, mdt, mdt_size); if (ret) return ret; @@ -1275,7 +1279,7 @@ int pil_boot(struct pil_desc *desc) goto release_fw; } - ret = pil_init_mmap(desc, mdt); + ret = pil_init_mmap(desc, mdt, fw->size); if (ret) goto release_fw; @@ -1288,7 +1292,8 @@ int pil_boot(struct pil_desc *desc) pil_log("before_init_image", desc); if (desc->ops->init_image) - ret = desc->ops->init_image(desc, fw->data, fw->size); + ret = desc->ops->init_image(desc, fw->data, fw->size, + priv->region_start, priv->region); if (ret) { pil_err(desc, "Initializing image failed(rc:%d)\n", ret); goto err_boot; diff --git a/drivers/soc/qcom/peripheral-loader.h b/drivers/soc/qcom/peripheral-loader.h index 29fa4b612667..d5e6cf2b6e2a 100644 --- a/drivers/soc/qcom/peripheral-loader.h +++ b/drivers/soc/qcom/peripheral-loader.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2010-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2010-2019,2021, The Linux Foundation. All rights reserved. */ #ifndef __MSM_PERIPHERAL_LOADER_H #define __MSM_PERIPHERAL_LOADER_H @@ -103,7 +103,7 @@ struct pil_image_info { */ struct pil_reset_ops { int (*init_image)(struct pil_desc *pil, const u8 *metadata, - size_t size); + size_t size, phys_addr_t mdata_phys, void *region); int (*mem_setup)(struct pil_desc *pil, phys_addr_t addr, size_t size); int (*verify_blob)(struct pil_desc *pil, phys_addr_t phy_addr, size_t size); diff --git a/drivers/soc/qcom/pil-msa.c b/drivers/soc/qcom/pil-msa.c index 9cff905d3e43..91ae185fa129 100644 --- a/drivers/soc/qcom/pil-msa.c +++ b/drivers/soc/qcom/pil-msa.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -850,7 +850,8 @@ int pil_mss_debug_reset(struct pil_desc *pil) } static int pil_msa_auth_modem_mdt(struct pil_desc *pil, const u8 *metadata, - size_t size) + size_t size, phys_addr_t region_start, + void *region) { struct modem_data *drv = dev_get_drvdata(pil->dev); void *mdata_virt; @@ -934,7 +935,8 @@ static int pil_msa_auth_modem_mdt(struct pil_desc *pil, const u8 *metadata, } static int pil_msa_mss_reset_mba_load_auth_mdt(struct pil_desc *pil, - const u8 *metadata, size_t size) + const u8 *metadata, size_t size, + phys_addr_t region_start, void *region) { int ret; @@ -942,7 +944,8 @@ static int pil_msa_mss_reset_mba_load_auth_mdt(struct pil_desc *pil, if (ret) return ret; - return pil_msa_auth_modem_mdt(pil, metadata, size); + return pil_msa_auth_modem_mdt(pil, metadata, size, region_start, + region); } static int pil_msa_mba_verify_blob(struct pil_desc *pil, phys_addr_t phy_addr, diff --git a/drivers/soc/qcom/subsys-pil-tz.c b/drivers/soc/qcom/subsys-pil-tz.c index e979abd14ee3..68ea839c6355 100644 --- a/drivers/soc/qcom/subsys-pil-tz.c +++ b/drivers/soc/qcom/subsys-pil-tz.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved. */ #include @@ -39,6 +39,13 @@ #define desc_to_data(d) container_of(d, struct pil_tz_data, desc) #define subsys_to_data(d) container_of(d, struct pil_tz_data, subsys_desc) +struct pil_map_fw_info { + void *region; + unsigned long attrs; + phys_addr_t base_addr; + struct device *dev; +}; + /** * struct reg_info - regulator info * @reg: regulator handle @@ -599,16 +606,21 @@ static void pil_remove_proxy_vote(struct pil_desc *pil) } static int pil_init_image_trusted(struct pil_desc *pil, - const u8 *metadata, size_t size) + const u8 *metadata, size_t size, phys_addr_t mdata_phys, + void *region) { struct pil_tz_data *d = desc_to_data(pil); u32 scm_ret = 0; void *mdata_buf; - dma_addr_t mdata_phys; int ret; - unsigned long attrs = 0; - struct device dev = {0}; struct scm_desc desc = {0}; + struct pil_map_fw_info map_fw_info = { + .attrs = pil->attrs, + .region = region, + .base_addr = mdata_phys, + .dev = pil->dev, + }; + void *map_data = pil->map_data ? pil->map_data : &map_fw_info; if (d->subsys_desc.no_auth) return 0; @@ -616,15 +628,10 @@ static int pil_init_image_trusted(struct pil_desc *pil, ret = scm_pas_enable_bw(); if (ret) return ret; - arch_setup_dma_ops(&dev, 0, 0, NULL, 0); - dev.coherent_dma_mask = - DMA_BIT_MASK(sizeof(dma_addr_t) * 8); - attrs |= DMA_ATTR_STRONGLY_ORDERED; - mdata_buf = dma_alloc_attrs(&dev, size, &mdata_phys, GFP_KERNEL, - attrs); + mdata_buf = pil->map_fw_mem(mdata_phys, size, map_data); if (!mdata_buf) { - pr_err("scm-pas: Allocation for metadata failed.\n"); + dev_err(pil->dev, "Failed to map memory for metadata.\n"); scm_pas_disable_bw(); return -ENOMEM; } @@ -638,7 +645,7 @@ static int pil_init_image_trusted(struct pil_desc *pil, &desc); scm_ret = desc.ret[0]; - dma_free_attrs(&dev, size, mdata_buf, mdata_phys, attrs); + pil->unmap_fw_mem(mdata_buf, size, map_data); scm_pas_disable_bw(); if (ret) return ret; From e07f30078f72d416b244b03194abc2bda4182c00 Mon Sep 17 00:00:00 2001 From: Rajesh Bharathwaj Date: Tue, 27 Apr 2021 11:54:03 -0700 Subject: [PATCH 04/55] max31760: add support for additional registers Adding support for register writes and values to change the duty cycle of the fan. Change-Id: I91efd154e9490c4dc1ecc8f84890fc1ef1eaf307 Signed-off-by: Rajesh Bharathwaj --- drivers/misc/max31760.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/misc/max31760.c b/drivers/misc/max31760.c index 2479583fd2f5..3d7b1726faf9 100644 --- a/drivers/misc/max31760.c +++ b/drivers/misc/max31760.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */ #include @@ -121,7 +121,7 @@ static ssize_t fan_show(struct device *dev, struct device_attribute *attr, static ssize_t fan_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { - long val; + long val, val1; struct max31760 *pdata; pdata = dev_get_drvdata(dev); @@ -131,8 +131,15 @@ static ssize_t fan_store(struct device *dev, struct device_attribute *attr, } kstrtol(buf, 0, &val); - pr_debug("%s, count:%d val:%lx, buf:%s\n", - __func__, count, val, buf); + val1 = val >> 8; + pr_debug("%s, count:%d val:%lx, val1:%lx, buf:%s\n", + __func__, count, val, val1, buf); + if (val1 == 0x50) { + val1 = val & 0xFF; + pr_debug("%s, reg value val1:%lx\n", __func__, val1); + max31760_i2c_reg_set(pdata, 0x50, val1); + return count; + } if (val == 0xff) { turn_gpio(pdata, false); From 1c2a32d57cb3fad8584ee3888eaa312cd55594ff Mon Sep 17 00:00:00 2001 From: Rahul Shahare Date: Fri, 9 Apr 2021 16:33:53 +0530 Subject: [PATCH 05/55] defconfig: Enable config for msm8937_32 Enable config to support SHIPPING_API_LEVEL 30 for msm8937_32. Change-Id: I796eb45d0d866851e26eab62aa28b7d52907127e Signed-off-by: Rahul Shahare --- arch/arm/configs/vendor/msm8937-perf_defconfig | 8 ++++---- arch/arm/configs/vendor/msm8937_defconfig | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/configs/vendor/msm8937-perf_defconfig b/arch/arm/configs/vendor/msm8937-perf_defconfig index 847f3c2e08f2..eff4380d1575 100644 --- a/arch/arm/configs/vendor/msm8937-perf_defconfig +++ b/arch/arm/configs/vendor/msm8937-perf_defconfig @@ -16,11 +16,11 @@ CONFIG_RCU_FAST_NO_HZ=y CONFIG_RCU_NOCB_CPU=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_IKHEADERS=y CONFIG_LOG_CPU_MAX_BUF_SHIFT=17 CONFIG_MEMCG=y CONFIG_MEMCG_SWAP=y CONFIG_BLK_CGROUP=y -CONFIG_RT_GROUP_SCHED=y CONFIG_CGROUP_FREEZER=y CONFIG_CPUSETS=y CONFIG_CGROUP_CPUACCT=y @@ -85,7 +85,6 @@ CONFIG_ARCH_MMAP_RND_BITS=16 CONFIG_PANIC_ON_REFCOUNT_ERROR=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_MODULE_SIG=y CONFIG_MODULE_SIG_FORCE=y @@ -244,6 +243,7 @@ CONFIG_NET_CLS_ACT=y CONFIG_DNS_RESOLVER=y CONFIG_QRTR=y CONFIG_QRTR_SMD=y +CONFIG_BPF_JIT=y CONFIG_BT=y # CONFIG_BT_BREDR is not set # CONFIG_BT_LE is not set @@ -293,6 +293,7 @@ CONFIG_DM_BOW=y CONFIG_NETDEVICES=y CONFIG_DUMMY=y CONFIG_TUN=y +CONFIG_VETH=y # CONFIG_NET_VENDOR_AMAZON is not set CONFIG_MSM_RMNET_BAM=y # CONFIG_NET_VENDOR_EZCHIP is not set @@ -336,6 +337,7 @@ CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_XPAD=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y CONFIG_INPUT_QPNP_POWER_ON=y @@ -450,7 +452,6 @@ CONFIG_HID_MICROSOFT=y CONFIG_HID_MULTITOUCH=y CONFIG_HID_SONY=y CONFIG_USB_HIDDEV=y -CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_MON=y CONFIG_USB_EHCI_HCD=y @@ -636,7 +637,6 @@ CONFIG_SECURITY_SELINUX=y CONFIG_SECURITY_SMACK=y CONFIG_CRYPTO_GCM=y CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_TWOFISH=y CONFIG_CRYPTO_LZ4=y CONFIG_CRYPTO_ANSI_CPRNG=y diff --git a/arch/arm/configs/vendor/msm8937_defconfig b/arch/arm/configs/vendor/msm8937_defconfig index 6a72ce846909..a3ce38bbd622 100644 --- a/arch/arm/configs/vendor/msm8937_defconfig +++ b/arch/arm/configs/vendor/msm8937_defconfig @@ -16,12 +16,12 @@ CONFIG_RCU_FAST_NO_HZ=y CONFIG_RCU_NOCB_CPU=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_IKHEADERS=y CONFIG_LOG_CPU_MAX_BUF_SHIFT=17 CONFIG_MEMCG=y CONFIG_MEMCG_SWAP=y CONFIG_BLK_CGROUP=y CONFIG_DEBUG_BLK_CGROUP=y -CONFIG_RT_GROUP_SCHED=y CONFIG_CGROUP_FREEZER=y CONFIG_CPUSETS=y CONFIG_CGROUP_CPUACCT=y @@ -89,7 +89,6 @@ CONFIG_ARCH_MMAP_RND_BITS=16 CONFIG_PANIC_ON_REFCOUNT_ERROR=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_MODULE_SIG=y CONFIG_MODULE_SIG_FORCE=y @@ -248,6 +247,7 @@ CONFIG_NET_CLS_ACT=y CONFIG_DNS_RESOLVER=y CONFIG_QRTR=y CONFIG_QRTR_SMD=y +CONFIG_BPF_JIT=y CONFIG_BT=y # CONFIG_BT_BREDR is not set # CONFIG_BT_LE is not set @@ -298,6 +298,7 @@ CONFIG_DM_BOW=y CONFIG_NETDEVICES=y CONFIG_DUMMY=y CONFIG_TUN=y +CONFIG_VETH=y # CONFIG_NET_VENDOR_AMAZON is not set CONFIG_MSM_RMNET_BAM=y # CONFIG_NET_VENDOR_EZCHIP is not set @@ -341,6 +342,7 @@ CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_XPAD=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y CONFIG_INPUT_QPNP_POWER_ON=y @@ -459,7 +461,6 @@ CONFIG_HID_MICROSOFT=y CONFIG_HID_MULTITOUCH=y CONFIG_HID_SONY=y CONFIG_USB_HIDDEV=y -CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_MON=y CONFIG_USB_EHCI_HCD=y @@ -649,7 +650,6 @@ CONFIG_SECURITY_SELINUX=y CONFIG_SECURITY_SMACK=y CONFIG_CRYPTO_GCM=y CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_TWOFISH=y CONFIG_CRYPTO_LZ4=y CONFIG_CRYPTO_ANSI_CPRNG=y From df22d1d28f03c30356386ce9a632d6e9b95b27c8 Mon Sep 17 00:00:00 2001 From: Rahul Shahare Date: Fri, 19 Mar 2021 11:27:57 +0530 Subject: [PATCH 06/55] ARM: defconfig: Enable config for msm8937_32go Enable config to support SHIPPING_API_LEVEL 30 for msm8937_32go Change-Id: Ie132b141e5a2cde2f7f0f498e084da40540f210d Signed-off-by: Rahul Shahare --- arch/arm/configs/vendor/msm8937_32go-perf_defconfig | 9 ++++----- arch/arm/configs/vendor/msm8937_32go_defconfig | 9 ++++----- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/arm/configs/vendor/msm8937_32go-perf_defconfig b/arch/arm/configs/vendor/msm8937_32go-perf_defconfig index bb682172521f..8a0091c54fe1 100644 --- a/arch/arm/configs/vendor/msm8937_32go-perf_defconfig +++ b/arch/arm/configs/vendor/msm8937_32go-perf_defconfig @@ -16,18 +16,17 @@ CONFIG_RCU_FAST_NO_HZ=y CONFIG_RCU_NOCB_CPU=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_IKHEADERS=y CONFIG_LOG_CPU_MAX_BUF_SHIFT=17 CONFIG_MEMCG=y CONFIG_MEMCG_SWAP=y CONFIG_BLK_CGROUP=y -CONFIG_RT_GROUP_SCHED=y CONFIG_CGROUP_FREEZER=y CONFIG_CPUSETS=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_BPF=y CONFIG_SCHED_CORE_CTL=y CONFIG_NAMESPACES=y -# CONFIG_UTS_NS is not set # CONFIG_PID_NS is not set CONFIG_SCHED_AUTOGROUP=y CONFIG_SCHED_TUNE=y @@ -86,7 +85,6 @@ CONFIG_ARCH_MMAP_RND_BITS=16 CONFIG_PANIC_ON_REFCOUNT_ERROR=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_MODULE_SIG=y CONFIG_MODULE_SIG_FORCE=y @@ -243,6 +241,7 @@ CONFIG_NET_CLS_ACT=y CONFIG_DNS_RESOLVER=y CONFIG_QRTR=y CONFIG_QRTR_SMD=y +CONFIG_BPF_JIT=y CONFIG_BT=y # CONFIG_BT_BREDR is not set # CONFIG_BT_LE is not set @@ -292,6 +291,7 @@ CONFIG_DM_BOW=y CONFIG_NETDEVICES=y CONFIG_DUMMY=y CONFIG_TUN=y +CONFIG_VETH=y # CONFIG_NET_VENDOR_AMAZON is not set CONFIG_MSM_RMNET_BAM=y # CONFIG_NET_VENDOR_EZCHIP is not set @@ -335,6 +335,7 @@ CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_XPAD=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y CONFIG_INPUT_QPNP_POWER_ON=y @@ -450,7 +451,6 @@ CONFIG_HID_MICROSOFT=y CONFIG_HID_MULTITOUCH=y CONFIG_HID_SONY=y CONFIG_USB_HIDDEV=y -CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_MON=y CONFIG_USB_EHCI_HCD=y @@ -639,7 +639,6 @@ CONFIG_SECURITY_SELINUX=y CONFIG_SECURITY_SMACK=y CONFIG_CRYPTO_GCM=y CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_TWOFISH=y CONFIG_CRYPTO_LZ4=y CONFIG_CRYPTO_ANSI_CPRNG=y diff --git a/arch/arm/configs/vendor/msm8937_32go_defconfig b/arch/arm/configs/vendor/msm8937_32go_defconfig index 31999d27d29e..f5585c52b43e 100644 --- a/arch/arm/configs/vendor/msm8937_32go_defconfig +++ b/arch/arm/configs/vendor/msm8937_32go_defconfig @@ -16,12 +16,12 @@ CONFIG_RCU_FAST_NO_HZ=y CONFIG_RCU_NOCB_CPU=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_IKHEADERS=y CONFIG_LOG_CPU_MAX_BUF_SHIFT=17 CONFIG_MEMCG=y CONFIG_MEMCG_SWAP=y CONFIG_BLK_CGROUP=y CONFIG_DEBUG_BLK_CGROUP=y -CONFIG_RT_GROUP_SCHED=y CONFIG_CGROUP_FREEZER=y CONFIG_CPUSETS=y CONFIG_CGROUP_CPUACCT=y @@ -29,7 +29,6 @@ CONFIG_CGROUP_BPF=y CONFIG_CGROUP_DEBUG=y CONFIG_SCHED_CORE_CTL=y CONFIG_NAMESPACES=y -# CONFIG_UTS_NS is not set # CONFIG_PID_NS is not set CONFIG_SCHED_AUTOGROUP=y CONFIG_SCHED_TUNE=y @@ -90,7 +89,6 @@ CONFIG_ARCH_MMAP_RND_BITS=16 CONFIG_PANIC_ON_REFCOUNT_ERROR=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_MODULE_SIG=y CONFIG_MODULE_SIG_FORCE=y @@ -247,6 +245,7 @@ CONFIG_NET_CLS_ACT=y CONFIG_DNS_RESOLVER=y CONFIG_QRTR=y CONFIG_QRTR_SMD=y +CONFIG_BPF_JIT=y CONFIG_BT=y # CONFIG_BT_BREDR is not set # CONFIG_BT_LE is not set @@ -297,6 +296,7 @@ CONFIG_DM_BOW=y CONFIG_NETDEVICES=y CONFIG_DUMMY=y CONFIG_TUN=y +CONFIG_VETH=y # CONFIG_NET_VENDOR_AMAZON is not set CONFIG_MSM_RMNET_BAM=y # CONFIG_NET_VENDOR_EZCHIP is not set @@ -340,6 +340,7 @@ CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_XPAD=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y CONFIG_INPUT_QPNP_POWER_ON=y @@ -457,7 +458,6 @@ CONFIG_HID_MICROSOFT=y CONFIG_HID_MULTITOUCH=y CONFIG_HID_SONY=y CONFIG_USB_HIDDEV=y -CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_MON=y CONFIG_USB_EHCI_HCD=y @@ -651,7 +651,6 @@ CONFIG_SECURITY_SELINUX=y CONFIG_SECURITY_SMACK=y CONFIG_CRYPTO_GCM=y CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_TWOFISH=y CONFIG_CRYPTO_LZ4=y CONFIG_CRYPTO_ANSI_CPRNG=y From 88bff86f88cc3a02fd2ee609f9d684d85d78f662 Mon Sep 17 00:00:00 2001 From: Puranam V G Tejaswi Date: Sat, 8 May 2021 17:59:10 +0530 Subject: [PATCH 07/55] msm: kgsl: Flush mem workqueue and retry if failed to find SVM region In case we get -ENOMEM error when trying to find required SVM region, flush mem workqueue and retry. It is possible that the required region was already freed but the workqueue did not run. Change-Id: I66b0c4dac2fbb8d3b66209b67174645ef37b10df Signed-off-by: Puranam V G Tejaswi --- drivers/gpu/msm/kgsl.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c index c365b3e49e98..e2116c28c493 100644 --- a/drivers/gpu/msm/kgsl.c +++ b/drivers/gpu/msm/kgsl.c @@ -2521,6 +2521,12 @@ static int kgsl_setup_anon_useraddr(struct kgsl_pagetable *pagetable, ret = kgsl_mmu_set_svm_region(pagetable, (uint64_t) hostptr, (uint64_t) size); + /* if OOM, retry once after flushing mem_workqueue */ + if (ret == -ENOMEM) { + flush_workqueue(kgsl_driver.mem_workqueue); + ret = kgsl_mmu_set_svm_region(pagetable, + (uint64_t) hostptr, (uint64_t) size); + } if (ret) return ret; @@ -4894,6 +4900,11 @@ kgsl_get_unmapped_area(struct file *file, unsigned long addr, pgoff, len, (int) val); } else { val = _get_svm_area(private, entry, addr, len, flags); + /* if OOM, retry once after flushing mem_workqueue */ + if (val == -ENOMEM) { + flush_workqueue(kgsl_driver.mem_workqueue); + val = _get_svm_area(private, entry, addr, len, flags); + } if (IS_ERR_VALUE(val)) dev_err_ratelimited(device->dev, "_get_svm_area: pid %d mmap_base %lx addr %lx pgoff %lx len %ld failed error %d\n", From 026146ae55ecc0fea59b6ce30a88b3a755ad4653 Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Wed, 12 May 2021 17:46:28 +0530 Subject: [PATCH 08/55] msm: kgsl: Fix snapshot collection for ib1 Sometimes IB1_BASE from register does not match with IB1 of the ring buffer, this may happen while doing save restore of IB during preemption. In such case, to dump IB1 in snapshot, check for overlap between IB1_BASE and IB1 from the ring buffer and dump IB1 in snapshot as per ring buffer's IB1 base and size. Change-Id: Ic3af8678a11f20f447fcbcbd3ec209283619b96a Signed-off-by: Pankaj Gupta --- drivers/gpu/msm/adreno_snapshot.c | 42 +++++++++++++++++++++++-------- 1 file changed, 32 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/msm/adreno_snapshot.c b/drivers/gpu/msm/adreno_snapshot.c index 780e89d58899..8529084eaaf0 100644 --- a/drivers/gpu/msm/adreno_snapshot.c +++ b/drivers/gpu/msm/adreno_snapshot.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #include @@ -195,7 +195,17 @@ static inline void parse_ib(struct kgsl_device *device, * then push it into the static blob otherwise put it in the dynamic * list */ - if (gpuaddr == snapshot->ib1base) { + if (kgsl_addr_range_overlap(gpuaddr, dwords, + snapshot->ib1base, snapshot->ib1size)) { + /* + * During restore after preemption, ib1base in the register + * can be updated by CP. In such scenarios, to dump complete + * IB1 in snapshot, we should consider ib1base from ringbuffer. + */ + if (gpuaddr != snapshot->ib1base) { + snapshot->ib1base = gpuaddr; + snapshot->ib1size = dwords; + } kgsl_snapshot_push_object(device, process, gpuaddr, dwords); return; } @@ -309,16 +319,29 @@ static void snapshot_rb_ibs(struct kgsl_device *device, } if (adreno_cmd_is_ib(adreno_dev, rbptr[index])) { + uint64_t ibaddr; + uint64_t ibsize; + if (ADRENO_LEGACY_PM4(adreno_dev)) { - if (rbptr[index + 1] == snapshot->ib1base) - break; + ibaddr = rbptr[index + 1]; + ibsize = rbptr[index + 2]; } else { - uint64_t ibaddr; - ibaddr = rbptr[index + 2]; ibaddr = ibaddr << 32 | rbptr[index + 1]; - if (ibaddr == snapshot->ib1base) - break; + ibsize = rbptr[index + 3]; + } + + if (kgsl_addr_range_overlap(ibaddr, ibsize, + snapshot->ib1base, snapshot->ib1size)) { + /* + * During restore after preemption, ib1base in + * the register can be updated by CP. In such + * scenario, to dump complete IB1 in snapshot, + * we should consider ib1base from ringbuffer. + */ + snapshot->ib1base = ibaddr; + snapshot->ib1size = ibsize; + break; } } } while (index != rb->wptr); @@ -916,8 +939,7 @@ void adreno_snapshot(struct kgsl_device *device, struct kgsl_snapshot *snapshot, * figure how often this really happens. */ - if (-ENOENT == find_object(snapshot->ib1base, snapshot->process) && - snapshot->ib1size) { + if (-ENOENT == find_object(snapshot->ib1base, snapshot->process)) { struct kgsl_mem_entry *entry; u64 ibsize; From 45c3e7063729d0f25c44008bf28de25e2aca39a9 Mon Sep 17 00:00:00 2001 From: Armaan Siddiqui Date: Wed, 12 May 2021 23:47:35 +0530 Subject: [PATCH 09/55] msm: ipa3: Fix to copy num of rules from user space Changes done to copy num of rules from user space to kernel side as earlier only payload was being copied. And it is needed to check if user space payload is not modified in between. Change-Id: I14e15fe0c6746226cc44d224d33c00e809cd69ca Signed-off-by: Armaan Siddiqui --- drivers/platform/msm/ipa/ipa_v3/ipa.c | 107 ++++++++++++++++++++++---- 1 file changed, 93 insertions(+), 14 deletions(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c index a1006eb577c9..de8270d255fd 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c @@ -708,6 +708,7 @@ static int ipa3_ioctl_add_rt_rule_v2(unsigned long arg) u32 pyld_sz; u64 uptr = 0; u8 *param = NULL; + u8 *param2 = NULL; u8 *kptr = NULL; if (copy_from_user(header, (const void __user *)arg, @@ -746,11 +747,20 @@ static int ipa3_ioctl_add_rt_rule_v2(unsigned long arg) retval = -EFAULT; goto free_param_kptr; } + + param2 = memdup_user((const void __user *)arg, + sizeof(struct ipa_ioc_add_rt_rule_v2)); + if (IS_ERR(param2)) { + retval = -EFAULT; + goto free_param_kptr; + } + + /* add check in case user-space module compromised */ - if (unlikely(((struct ipa_ioc_add_rt_rule_v2 *)param)->num_rules + if (unlikely(((struct ipa_ioc_add_rt_rule_v2 *)param2)->num_rules != pre_entry)) { IPAERR_RL("current %d pre %d\n", - ((struct ipa_ioc_add_rt_rule_v2 *)param)-> + ((struct ipa_ioc_add_rt_rule_v2 *)param2)-> num_rules, pre_entry); retval = -EFAULT; goto free_param_kptr; @@ -794,6 +804,8 @@ static int ipa3_ioctl_add_rt_rule_v2(unsigned long arg) free_param_kptr: if (!IS_ERR(param)) kfree(param); + if (!IS_ERR(param2)) + kfree(param2); kfree(kptr); return retval; @@ -809,6 +821,7 @@ static int ipa3_ioctl_add_rt_rule_ext_v2(unsigned long arg) u32 pyld_sz; u64 uptr = 0; u8 *param = NULL; + u8 *param2 = NULL; u8 *kptr = NULL; if (copy_from_user(header, @@ -850,11 +863,20 @@ static int ipa3_ioctl_add_rt_rule_ext_v2(unsigned long arg) retval = -EFAULT; goto free_param_kptr; } + + param2 = memdup_user((const void __user *)arg, + sizeof(struct ipa_ioc_add_rt_rule_ext_v2)); + if (IS_ERR(param2)) { + retval = -EFAULT; + goto free_param_kptr; + } + + /* add check in case user-space module compromised */ - if (unlikely(((struct ipa_ioc_add_rt_rule_ext_v2 *)param)->num_rules + if (unlikely(((struct ipa_ioc_add_rt_rule_ext_v2 *)param2)->num_rules != pre_entry)) { IPAERR_RL("current %d pre %d\n", - ((struct ipa_ioc_add_rt_rule_ext_v2 *)param)-> + ((struct ipa_ioc_add_rt_rule_ext_v2 *)param2)-> num_rules, pre_entry); retval = -EFAULT; goto free_param_kptr; @@ -900,6 +922,8 @@ static int ipa3_ioctl_add_rt_rule_ext_v2(unsigned long arg) free_param_kptr: if (!IS_ERR(param)) kfree(param); + if (!IS_ERR(param2)) + kfree(param2); kfree(kptr); return retval; @@ -915,6 +939,7 @@ static int ipa3_ioctl_add_rt_rule_after_v2(unsigned long arg) u32 pyld_sz; u64 uptr = 0; u8 *param = NULL; + u8 *param2 = NULL; u8 *kptr = NULL; if (copy_from_user(header, (const void __user *)arg, @@ -955,11 +980,19 @@ static int ipa3_ioctl_add_rt_rule_after_v2(unsigned long arg) retval = -EFAULT; goto free_param_kptr; } + + param2 = memdup_user((const void __user *)arg, + sizeof(struct ipa_ioc_add_rt_rule_after_v2)); + if (IS_ERR(param2)) { + retval = -EFAULT; + goto free_param_kptr; + } + /* add check in case user-space module compromised */ - if (unlikely(((struct ipa_ioc_add_rt_rule_after_v2 *)param)->num_rules + if (unlikely(((struct ipa_ioc_add_rt_rule_after_v2 *)param2)->num_rules != pre_entry)) { IPAERR_RL("current %d pre %d\n", - ((struct ipa_ioc_add_rt_rule_after_v2 *)param)-> + ((struct ipa_ioc_add_rt_rule_after_v2 *)param2)-> num_rules, pre_entry); retval = -EFAULT; goto free_param_kptr; @@ -1003,6 +1036,8 @@ static int ipa3_ioctl_add_rt_rule_after_v2(unsigned long arg) free_param_kptr: if (!IS_ERR(param)) kfree(param); + if (!IS_ERR(param2)) + kfree(param2); kfree(kptr); return retval; @@ -1018,6 +1053,7 @@ static int ipa3_ioctl_mdfy_rt_rule_v2(unsigned long arg) u32 pyld_sz; u64 uptr = 0; u8 *param = NULL; + u8 *param2 = NULL; u8 *kptr = NULL; if (copy_from_user(header, (const void __user *)arg, @@ -1058,11 +1094,19 @@ static int ipa3_ioctl_mdfy_rt_rule_v2(unsigned long arg) retval = -EFAULT; goto free_param_kptr; } + + param2 = memdup_user((const void __user *)arg, + sizeof(struct ipa_ioc_mdfy_rt_rule_v2)); + if (IS_ERR(param2)) { + retval = -EFAULT; + goto free_param_kptr; + } + /* add check in case user-space module compromised */ - if (unlikely(((struct ipa_ioc_mdfy_rt_rule_v2 *)param)->num_rules + if (unlikely(((struct ipa_ioc_mdfy_rt_rule_v2 *)param2)->num_rules != pre_entry)) { IPAERR_RL("current %d pre %d\n", - ((struct ipa_ioc_mdfy_rt_rule_v2 *)param)-> + ((struct ipa_ioc_mdfy_rt_rule_v2 *)param2)-> num_rules, pre_entry); retval = -EFAULT; goto free_param_kptr; @@ -1106,6 +1150,8 @@ static int ipa3_ioctl_mdfy_rt_rule_v2(unsigned long arg) free_param_kptr: if (!IS_ERR(param)) kfree(param); + if (!IS_ERR(param2)) + kfree(param2); kfree(kptr); return retval; @@ -1121,6 +1167,7 @@ static int ipa3_ioctl_add_flt_rule_v2(unsigned long arg) u32 pyld_sz; u64 uptr = 0; u8 *param = NULL; + u8 *param2 = NULL; u8 *kptr = NULL; if (copy_from_user(header, (const void __user *)arg, @@ -1160,11 +1207,19 @@ static int ipa3_ioctl_add_flt_rule_v2(unsigned long arg) retval = -EFAULT; goto free_param_kptr; } + + param2 = memdup_user((const void __user *)arg, + sizeof(struct ipa_ioc_add_flt_rule_v2)); + if (IS_ERR(param2)) { + retval = -EFAULT; + goto free_param_kptr; + } + /* add check in case user-space module compromised */ - if (unlikely(((struct ipa_ioc_add_flt_rule_v2 *)param)->num_rules + if (unlikely(((struct ipa_ioc_add_flt_rule_v2 *)param2)->num_rules != pre_entry)) { IPAERR_RL("current %d pre %d\n", - ((struct ipa_ioc_add_flt_rule_v2 *)param)-> + ((struct ipa_ioc_add_flt_rule_v2 *)param2)-> num_rules, pre_entry); retval = -EFAULT; goto free_param_kptr; @@ -1207,6 +1262,8 @@ static int ipa3_ioctl_add_flt_rule_v2(unsigned long arg) free_param_kptr: if (!IS_ERR(param)) kfree(param); + if (!IS_ERR(param2)) + kfree(param2); kfree(kptr); return retval; @@ -1222,6 +1279,7 @@ static int ipa3_ioctl_add_flt_rule_after_v2(unsigned long arg) u32 pyld_sz; u64 uptr = 0; u8 *param = NULL; + u8 *param2 = NULL; u8 *kptr = NULL; if (copy_from_user(header, (const void __user *)arg, @@ -1262,11 +1320,19 @@ static int ipa3_ioctl_add_flt_rule_after_v2(unsigned long arg) retval = -EFAULT; goto free_param_kptr; } + + param2 = memdup_user((const void __user *)arg, + sizeof(struct ipa_ioc_add_flt_rule_after_v2)); + if (IS_ERR(param2)) { + retval = -EFAULT; + goto free_param_kptr; + } + /* add check in case user-space module compromised */ - if (unlikely(((struct ipa_ioc_add_flt_rule_after_v2 *)param)->num_rules + if (unlikely(((struct ipa_ioc_add_flt_rule_after_v2 *)param2)->num_rules != pre_entry)) { IPAERR_RL("current %d pre %d\n", - ((struct ipa_ioc_add_flt_rule_after_v2 *)param)-> + ((struct ipa_ioc_add_flt_rule_after_v2 *)param2)-> num_rules, pre_entry); retval = -EFAULT; goto free_param_kptr; @@ -1310,6 +1376,8 @@ static int ipa3_ioctl_add_flt_rule_after_v2(unsigned long arg) free_param_kptr: if (!IS_ERR(param)) kfree(param); + if (!IS_ERR(param2)) + kfree(param2); kfree(kptr); return retval; @@ -1325,6 +1393,7 @@ static int ipa3_ioctl_mdfy_flt_rule_v2(unsigned long arg) u32 pyld_sz; u64 uptr = 0; u8 *param = NULL; + u8 *param2 = NULL; u8 *kptr = NULL; if (copy_from_user(header, (const void __user *)arg, @@ -1365,11 +1434,19 @@ static int ipa3_ioctl_mdfy_flt_rule_v2(unsigned long arg) retval = -EFAULT; goto free_param_kptr; } + + param2 = memdup_user((const void __user *)arg, + sizeof(struct ipa_ioc_mdfy_flt_rule_v2)); + if (IS_ERR(param2)) { + retval = -EFAULT; + goto free_param_kptr; + } + /* add check in case user-space module compromised */ - if (unlikely(((struct ipa_ioc_mdfy_flt_rule_v2 *)param)->num_rules + if (unlikely(((struct ipa_ioc_mdfy_flt_rule_v2 *)param2)->num_rules != pre_entry)) { IPAERR_RL("current %d pre %d\n", - ((struct ipa_ioc_mdfy_flt_rule_v2 *)param)-> + ((struct ipa_ioc_mdfy_flt_rule_v2 *)param2)-> num_rules, pre_entry); retval = -EFAULT; goto free_param_kptr; @@ -1413,6 +1490,8 @@ static int ipa3_ioctl_mdfy_flt_rule_v2(unsigned long arg) free_param_kptr: if (!IS_ERR(param)) kfree(param); + if (!IS_ERR(param2)) + kfree(param2); kfree(kptr); return retval; From 431a9b4a572a414824f8d9df45c86676e49c3ded Mon Sep 17 00:00:00 2001 From: Can Guo Date: Thu, 27 Feb 2020 00:13:30 -0800 Subject: [PATCH 10/55] scsi: ufs-qcom: Add one vendor specific sysfs group Add one vendor specific sysfs group to support additional sysfs nodes, such as err_state and power_mode. Change-Id: Ia69909fc3838a054221191259a015067dd962008 Signed-off-by: Can Guo --- drivers/scsi/ufs/ufs-qcom.c | 68 +++++++++++++++++++++++++++++++++++++ drivers/scsi/ufs/ufs-qcom.h | 3 +- 2 files changed, 70 insertions(+), 1 deletion(-) diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c index 21902e027ee8..da80db241d9a 100644 --- a/drivers/scsi/ufs/ufs-qcom.c +++ b/drivers/scsi/ufs/ufs-qcom.c @@ -65,6 +65,7 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, u32 clk_1us_cycles, u32 clk_40ns_cycles); static void ufs_qcom_pm_qos_suspend(struct ufs_qcom_host *host); +static int ufs_qcom_init_sysfs(struct ufs_hba *hba); static void ufs_qcom_dump_regs(struct ufs_hba *hba, int offset, int len, char *prefix) @@ -2253,6 +2254,8 @@ static int ufs_qcom_init(struct ufs_hba *hba) err = 0; } + ufs_qcom_init_sysfs(hba); + ufs_qcom_save_host_ptr(hba); goto out; @@ -2704,6 +2707,8 @@ static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba, bool no_sleep) struct ufs_qcom_host *host = ufshcd_get_variant(hba); struct phy *phy = host->generic_phy; + host->err_occurred = true; + ufs_qcom_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16, "HCI Vendor Specific Registers "); ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper); @@ -2768,6 +2773,69 @@ static struct ufs_hba_variant ufs_hba_qcom_variant = { .pm_qos_vops = &ufs_hba_pm_qos_variant_ops, }; +/** + * QCOM specific sysfs group and nodes + */ +static ssize_t err_state_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + + return scnprintf(buf, PAGE_SIZE, "%d\n", !!host->err_occurred); +} + +static DEVICE_ATTR_RO(err_state); + +static ssize_t power_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + static const char * const names[] = { + "INVALID MODE", + "FAST MODE", + "SLOW MODE", + "INVALID MODE", + "FASTAUTO MODE", + "SLOWAUTO MODE", + "INVALID MODE", + }; + + /* Print current power info */ + return scnprintf(buf, PAGE_SIZE, + "[Rx,Tx]: Gear[%d,%d], Lane[%d,%d], PWR[%s,%s], Rate-%c\n", + hba->pwr_info.gear_rx, hba->pwr_info.gear_tx, + hba->pwr_info.lane_rx, hba->pwr_info.lane_tx, + names[hba->pwr_info.pwr_rx], + names[hba->pwr_info.pwr_tx], + hba->pwr_info.hs_rate == PA_HS_MODE_B ? 'B' : 'A'); +} + +static DEVICE_ATTR_RO(power_mode); + +static struct attribute *ufs_qcom_sysfs_attrs[] = { + &dev_attr_err_state.attr, + &dev_attr_power_mode.attr, + NULL +}; + +static const struct attribute_group ufs_qcom_sysfs_group = { + .name = "qcom", + .attrs = ufs_qcom_sysfs_attrs, +}; + +static int ufs_qcom_init_sysfs(struct ufs_hba *hba) +{ + int ret; + + ret = sysfs_create_group(&hba->dev->kobj, &ufs_qcom_sysfs_group); + if (ret) + dev_err(hba->dev, "%s: Failed to create qcom sysfs group (err = %d)\n", + __func__, ret); + + return ret; +} + /** * ufs_qcom_probe - probe routine of the driver * @pdev: pointer to Platform device handle diff --git a/drivers/scsi/ufs/ufs-qcom.h b/drivers/scsi/ufs/ufs-qcom.h index 6538637b1c43..bcf0d7c0b205 100644 --- a/drivers/scsi/ufs/ufs-qcom.h +++ b/drivers/scsi/ufs/ufs-qcom.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -365,6 +365,7 @@ struct ufs_qcom_host { struct ufs_vreg *vccq_parent; bool work_pending; bool is_phy_pwr_on; + bool err_occurred; }; static inline u32 From f6e21b2c223e907c0ba77d8547979a43e347a24c Mon Sep 17 00:00:00 2001 From: Asutosh Das Date: Mon, 22 Jun 2020 11:24:51 -0700 Subject: [PATCH 11/55] sysfs: ufs-qcom: Add sysfs entries for flashpvl Added entries are bus_speed_mode, clk_status and err_count. Change-Id: I459c75048d737651d977f5a5c6aa5dd84553156c Signed-off-by: Asutosh Das Signed-off-by: Sridhar Arra --- drivers/scsi/ufs/ufs-qcom.c | 77 ++++++++++++++++++++++++++++++++++++- drivers/scsi/ufs/ufs-qcom.h | 3 ++ 2 files changed, 79 insertions(+), 1 deletion(-) diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c index da80db241d9a..89264a702eb0 100644 --- a/drivers/scsi/ufs/ufs-qcom.c +++ b/drivers/scsi/ufs/ufs-qcom.c @@ -1546,8 +1546,11 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, if (on && (status == POST_CHANGE)) { if (!host->is_phy_pwr_on) { - phy_power_on(host->generic_phy); + err = phy_power_on(host->generic_phy); host->is_phy_pwr_on = true; + + if (!err) + atomic_set(&host->clks_on, on); } /* enable the device ref clock for HS mode*/ if (ufshcd_is_hs_mode(&hba->pwr_info)) @@ -2432,6 +2435,8 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, break; } + if (!err) + atomic_set(&host->scale_up, scale_up); return err; } @@ -2813,9 +2818,79 @@ static ssize_t power_mode_show(struct device *dev, static DEVICE_ATTR_RO(power_mode); +static ssize_t bus_speed_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + + return scnprintf(buf, PAGE_SIZE, "%d\n", + !!atomic_read(&host->scale_up)); +} + +static DEVICE_ATTR_RO(bus_speed_mode); + +static ssize_t clk_status_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + struct ufs_qcom_host *host = ufshcd_get_variant(hba); + + return scnprintf(buf, PAGE_SIZE, "%d\n", + !!atomic_read(&host->clks_on)); +} + +static DEVICE_ATTR_RO(clk_status); + +static unsigned int ufs_qcom_gec(struct ufs_hba *hba, + struct ufs_uic_err_reg_hist *err_hist, + char *err_name) +{ + unsigned long flags; + int i, cnt_err = 0; + + spin_lock_irqsave(hba->host->host_lock, flags); + for (i = 0; i < UIC_ERR_REG_HIST_LENGTH; i++) { + int p = (i + err_hist->pos) % UIC_ERR_REG_HIST_LENGTH; + + if (err_hist->tstamp[p] == 0) + continue; + dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p, + err_hist->reg[p], ktime_to_us(err_hist->tstamp[p])); + + ++cnt_err; + } + + spin_unlock_irqrestore(hba->host->host_lock, flags); + return cnt_err; +} + +static ssize_t err_count_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + + return scnprintf(buf, PAGE_SIZE, + "%s: %d\n%s: %d\n%s: %d\n", + "pa_err_cnt_total", + ufs_qcom_gec(hba, &hba->ufs_stats.pa_err, + "pa_err_cnt_total"), + "dl_err_cnt_total", + ufs_qcom_gec(hba, &hba->ufs_stats.dl_err, + "dl_err_cnt_total"), + "dme_err_cnt", + ufs_qcom_gec(hba, &hba->ufs_stats.dme_err, + "dme_err_cnt")); +} + +static DEVICE_ATTR_RO(err_count); + static struct attribute *ufs_qcom_sysfs_attrs[] = { &dev_attr_err_state.attr, &dev_attr_power_mode.attr, + &dev_attr_bus_speed_mode.attr, + &dev_attr_clk_status.attr, + &dev_attr_err_count.attr, NULL }; diff --git a/drivers/scsi/ufs/ufs-qcom.h b/drivers/scsi/ufs/ufs-qcom.h index bcf0d7c0b205..778309f5eb21 100644 --- a/drivers/scsi/ufs/ufs-qcom.h +++ b/drivers/scsi/ufs/ufs-qcom.h @@ -366,6 +366,9 @@ struct ufs_qcom_host { bool work_pending; bool is_phy_pwr_on; bool err_occurred; + /* FlashPVL entries */ + atomic_t scale_up; + atomic_t clks_on; }; static inline u32 From 705b3bd107207b13117f6d81b214f105d2853522 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 26 Mar 2021 17:57:08 +0530 Subject: [PATCH 12/55] clk: qcom: clk-alpha-pll: Add support for FSM legacy mode The Lucid PLL could require the FSM legacy mode bit to be set for the PLL to be operational, thus add support and set the same when the flag is set. While at it also update the Zonda disable function to remove the additional offset usage. Change-Id: I3ed4b6c38a1769c5021f17e0115215eab615ab62 Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-alpha-pll.c | 10 +++++++--- drivers/clk/qcom/clk-alpha-pll.h | 3 ++- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 07b6ccc2ae57..9e7f9733b019 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2015, 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2015, 2018-2021, The Linux Foundation. All rights reserved. */ #include @@ -30,6 +30,7 @@ #define PLL_VOTE_FSM_RESET BIT(21) #define PLL_UPDATE BIT(22) #define PLL_UPDATE_BYPASS BIT(23) +#define PLL_FSM_LEGACY_MODE BIT(24) #define PLL_ALPHA_EN BIT(24) #define PLL_OFFLINE_ACK BIT(28) #define ALPHA_PLL_ACK_LATCH BIT(29) @@ -1265,10 +1266,10 @@ static int clk_zonda_pll_enable(struct clk_hw *hw) static void clk_zonda_pll_disable(struct clk_hw *hw) { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); - u32 val, mask, off = pll->offset; + u32 val, mask; int ret; - ret = regmap_read(pll->clkr.regmap, off + PLL_MODE(pll), &val); + ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); if (ret) return; @@ -2076,6 +2077,9 @@ void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, PLL_UPDATE_BYPASS, PLL_UPDATE_BYPASS); + if (pll->flags & SUPPORTS_FSM_LEGACY_MODE) + regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE, + PLL_FSM_LEGACY_MODE); /* Disable PLL output */ regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 1e8588eb9f44..5fe56ab670f4 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2015, 2018-2020, The Linux Foundation. All rights reserved. */ +/* Copyright (c) 2015, 2018-2021, The Linux Foundation. All rights reserved. */ #ifndef __QCOM_CLK_ALPHA_PLL_H__ #define __QCOM_CLK_ALPHA_PLL_H__ @@ -91,6 +91,7 @@ struct clk_alpha_pll { #define SUPPORTS_SLEW BIT(4) /* Associated with soft_vote for multiple PLL software instances */ #define SUPPORTS_FSM_VOTE BIT(5) +#define SUPPORTS_FSM_LEGACY_MODE BIT(6) u8 flags; struct clk_regmap clkr; From faa40d6e460e7d62a232d6c457ce47e8e385c7b1 Mon Sep 17 00:00:00 2001 From: Vishnu Satheesh Date: Wed, 12 May 2021 13:04:20 +0530 Subject: [PATCH 13/55] defconfig: Enable config CONFIG_DEBUG_FS for msm8937_64 Enable config CONFIG_DEBUG_FS to support /sys/kernel/debug for msm8937_64. Change-Id: I451b9b8f4b92b4009d04004dd2a1c367b0a46835 Signed-off-by: Vishnu Satheesh --- arch/arm64/configs/vendor/msm8937-perf_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/vendor/msm8937-perf_defconfig b/arch/arm64/configs/vendor/msm8937-perf_defconfig index 537bbfe1e771..3ebcfd031660 100644 --- a/arch/arm64/configs/vendor/msm8937-perf_defconfig +++ b/arch/arm64/configs/vendor/msm8937-perf_defconfig @@ -637,6 +637,7 @@ CONFIG_PRINTK_TIME=y CONFIG_DEBUG_CONSOLE_UNHASHED_POINTERS=y CONFIG_DEBUG_MODULE_LOAD_INFO=y CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_FS=y CONFIG_DEBUG_SECTION_MISMATCH=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_PANIC_ON_OOM=y From bd461f6eb6046c960ce169772c6420f07bdad53b Mon Sep 17 00:00:00 2001 From: Shadab Naseem Date: Fri, 26 Mar 2021 16:02:55 +0530 Subject: [PATCH 14/55] msm: Add initial support for Khaje in Kconfig platform Add ARCH_KHAJE support in the Kconfig platform. Change-Id: I78a4efd9a3534fb5dc68d5523a2bb96551b39d44 Signed-off-by: Shadab Naseem --- arch/arm64/Kconfig.platforms | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index a148ceceb363..f2cfda4c0899 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -183,6 +183,14 @@ config ARCH_BENGAL This enables support for the BENGAL chipset. If you do not wish to build a kernel that runs on this chipset, say 'N' here. +config ARCH_KHAJE + bool "Enable Support for Qualcomm Technologies, Inc. KHAJE" + depends on ARCH_QCOM + select COMMON_CLK_QCOM + help + This enables support for the KHAJE chipset. If you do not + wish to build a kernel that runs on this chipset, say 'N' here. + config ARCH_SCUBA bool "Enable Support for Qualcomm Technologies, Inc. SCUBA" depends on ARCH_QCOM From bfa2e599e7992b115d214286d5776f5aff28feb3 Mon Sep 17 00:00:00 2001 From: Shadab Naseem Date: Tue, 30 Mar 2021 11:52:04 +0530 Subject: [PATCH 15/55] defconfig: Enable ARCH_KHAJE Enable ARCH_KHAJE in the corresponding Bengal defconfig. Change-Id: I851d907c535afb22f31582da77e2fe745baba54e Signed-off-by: Shadab Naseem --- arch/arm64/configs/vendor/bengal-perf_defconfig | 1 + arch/arm64/configs/vendor/bengal_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/bengal-perf_defconfig b/arch/arm64/configs/vendor/bengal-perf_defconfig index 1513fae728c1..cdacc84dc000 100644 --- a/arch/arm64/configs/vendor/bengal-perf_defconfig +++ b/arch/arm64/configs/vendor/bengal-perf_defconfig @@ -50,6 +50,7 @@ CONFIG_PROFILING=y CONFIG_HOTPLUG_SIZE_BITS=29 CONFIG_ARCH_QCOM=y CONFIG_ARCH_BENGAL=y +CONFIG_ARCH_KHAJE=y CONFIG_ARCH_SCUBA=y CONFIG_SCHED_MC=y CONFIG_NR_CPUS=8 diff --git a/arch/arm64/configs/vendor/bengal_defconfig b/arch/arm64/configs/vendor/bengal_defconfig index 06313bebdc67..ce7cafd52fe9 100644 --- a/arch/arm64/configs/vendor/bengal_defconfig +++ b/arch/arm64/configs/vendor/bengal_defconfig @@ -51,6 +51,7 @@ CONFIG_PROFILING=y CONFIG_HOTPLUG_SIZE_BITS=29 CONFIG_ARCH_QCOM=y CONFIG_ARCH_BENGAL=y +CONFIG_ARCH_KHAJE=y CONFIG_ARCH_SCUBA=y CONFIG_SCHED_MC=y CONFIG_NR_CPUS=8 From c6a6ed986d6bca17444d90a850a36b1c1adf56b1 Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Wed, 12 May 2021 20:41:10 +0530 Subject: [PATCH 16/55] msm: ipa2: free the skb Free the skb once it is handled. Change-Id: Ib5ef2b1f5729e294bd95c45b6aa1b00f03a5984d Signed-off-by: Swetha Chikkaboraiah --- drivers/platform/msm/ipa/ipa_v2/ipa_dp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_dp.c b/drivers/platform/msm/ipa/ipa_v2/ipa_dp.c index b3f66161f263..417de103f49b 100644 --- a/drivers/platform/msm/ipa/ipa_v2/ipa_dp.c +++ b/drivers/platform/msm/ipa/ipa_v2/ipa_dp.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2012-2018, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2018, 2020-2021, The Linux Foundation. All rights reserved. */ #include @@ -2600,6 +2600,7 @@ static int ipa_lan_rx_pyld_hdlr(struct sk_buff *skb, } } + sys->free_skb(skb); out: return 0; } From a270f4a09930212b7c76b6f59226846adc37f981 Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Fri, 26 Feb 2021 14:08:57 +0530 Subject: [PATCH 17/55] usb: f_qdss: Avoid wait_for_completion if qdss_disable is called Commit 3741fb2cfb88 ("coresight: byte-cntr: Free USB requests when disconnected") introduced a regression which leads qdss_disable & qdss_close paths to race between them. If qdss_disable path is processing, it would queue disconnect_work which will notify the bypass notifier of USB_DISCONNECT and it will call free_req. Within same time frame if qdss_close is called, it will try to go ahead dequeue the request and wait_for_completion. But since free_req got called, it will free the qreq instance which wait_for_completion uses resulting in kernel panic. Fix this by checking for ep_dequeue status if dequeue was success then only wait_for_completion. Also taking the list operation under qdss->lock in order to avoid any races between qdss_write as well. Change-Id: I7bf9eab4296a509f5b459fa7768987c4a1f1287f Signed-off-by: Udipto Goswami --- drivers/usb/gadget/function/f_qdss.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/usb/gadget/function/f_qdss.c b/drivers/usb/gadget/function/f_qdss.c index 2a4f3d411f07..3abce5adf265 100644 --- a/drivers/usb/gadget/function/f_qdss.c +++ b/drivers/usb/gadget/function/f_qdss.c @@ -2,7 +2,7 @@ /* * f_qdss.c -- QDSS function Driver * - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #include @@ -909,15 +909,20 @@ void usb_qdss_close(struct usb_qdss_ch *ch) if (!qdss) goto close; qdss->qdss_close = true; + spin_lock(&qdss->lock); while (!list_empty(&qdss->queued_data_pool)) { qreq = list_first_entry(&qdss->queued_data_pool, struct qdss_req, list); + spin_unlock(&qdss->lock); spin_unlock_irqrestore(&channel_lock, flags); - usb_ep_dequeue(qdss->port.data, qreq->usb_req); - wait_for_completion(&qreq->write_done); + qdss_log("dequeue req:%pK\n", qreq->usb_req); + if (!usb_ep_dequeue(qdss->port.data, qreq->usb_req)) + wait_for_completion(&qreq->write_done); spin_lock_irqsave(&channel_lock, flags); + spin_lock(&qdss->lock); } + spin_unlock(&qdss->lock); spin_unlock_irqrestore(&channel_lock, flags); usb_qdss_free_req(ch); spin_lock_irqsave(&channel_lock, flags); From 5fadccc7e7143119327d2d4e4df9e1839c8900c1 Mon Sep 17 00:00:00 2001 From: Vasantha Balla Date: Thu, 6 May 2021 12:05:31 +0530 Subject: [PATCH 18/55] vidc_3x: Use static table governor for bus voting Current dynamic bus governor is not valid for sdm660/qm215. so switching back to static table model. Change-Id: If79af9913f637e544b3bb0bd10b9c0632d111825 Signed-off-by: Vasantha Balla --- .../vidc_3x/governors/msm_vidc_table_gov.c | 274 +----------------- .../platform/msm/vidc_3x/msm_vidc_res_parse.c | 127 ++++++++ .../platform/msm/vidc_3x/msm_vidc_resources.h | 23 +- .../media/platform/msm/vidc_3x/venus_hfi.c | 26 +- .../media/platform/msm/vidc_3x/venus_hfi.h | 4 + .../media/platform/msm/vidc_3x/vidc_hfi_api.h | 3 +- 6 files changed, 181 insertions(+), 276 deletions(-) diff --git a/drivers/media/platform/msm/vidc_3x/governors/msm_vidc_table_gov.c b/drivers/media/platform/msm/vidc_3x/governors/msm_vidc_table_gov.c index 38816ff2208c..f4b1d10f959b 100644 --- a/drivers/media/platform/msm/vidc_3x/governors/msm_vidc_table_gov.c +++ b/drivers/media/platform/msm/vidc_3x/governors/msm_vidc_table_gov.c @@ -24,27 +24,6 @@ #include "../vidc_hfi_api.h" -enum bus_profile { - VIDC_BUS_PROFILE_NORMAL = BIT(0), - VIDC_BUS_PROFILE_LOW = BIT(1), - VIDC_BUS_PROFILE_UBWC = BIT(2), -}; - -struct bus_profile_entry { - struct { - u32 load, freq; - } *bus_table; - u32 bus_table_size; - u32 codec_mask; - enum bus_profile profile; -}; - -struct msm_vidc_bus_table_gov { - struct bus_profile_entry *bus_prof_entries; - u32 count; - struct devfreq_governor devfreq_gov; -}; - static int __get_bus_freq(struct msm_vidc_bus_table_gov *gov, struct vidc_bus_vote_data *data, enum bus_profile profile) @@ -85,31 +64,19 @@ static int __get_bus_freq(struct msm_vidc_bus_table_gov *gov, } -static int msm_vidc_table_get_target_freq(struct devfreq *dev, - unsigned long *frequency) +int msm_vidc_table_get_target_freq(struct msm_vidc_bus_table_gov *gov, + struct msm_vidc_gov_data *vidc_data, + unsigned long *frequency) { - struct devfreq_dev_status status = {0}; - struct msm_vidc_gov_data *vidc_data = NULL; - struct msm_vidc_bus_table_gov *gov = NULL; enum bus_profile profile = 0; int i = 0; - if (!dev || !frequency) { - dprintk(VIDC_ERR, "%s: Invalid params %pK, %pK\n", - __func__, dev, frequency); - return -EINVAL; - } - - gov = container_of(dev->governor, - struct msm_vidc_bus_table_gov, devfreq_gov); - if (!gov) { - dprintk(VIDC_ERR, "%s: governor not found\n", __func__); + if (!frequency || !gov || !vidc_data) { + dprintk(VIDC_ERR, "%s: Invalid params %pK\n", + __func__, frequency); return -EINVAL; } - dev->profile->get_dev_status(dev->dev.parent, &status); - vidc_data = (struct msm_vidc_gov_data *)status.private_data; - *frequency = 0; for (i = 0; i < vidc_data->data_count; i++) { struct vidc_bus_vote_data *data = &vidc_data->data[i]; @@ -149,232 +116,3 @@ static int msm_vidc_table_get_target_freq(struct devfreq *dev, exit: return 0; } - -int msm_vidc_table_event_handler(struct devfreq *devfreq, - unsigned int event, void *data) -{ - int rc = 0; - - if (!devfreq) { - dprintk(VIDC_ERR, "%s: NULL devfreq\n", __func__); - return -EINVAL; - } - - switch (event) { - case DEVFREQ_GOV_START: - case DEVFREQ_GOV_RESUME: - mutex_lock(&devfreq->lock); - rc = update_devfreq(devfreq); - mutex_unlock(&devfreq->lock); - break; - } - - return rc; -} - -static int msm_vidc_free_bus_table(struct platform_device *pdev, - struct msm_vidc_bus_table_gov *data) -{ - int rc = 0, i = 0; - - if (!pdev || !data) { - dprintk(VIDC_ERR, "%s: invalid args %pK %pK\n", - __func__, pdev, data); - return -EINVAL; - } - - for (i = 0; i < data->count; i++) - data->bus_prof_entries[i].bus_table = NULL; - - data->bus_prof_entries = NULL; - data->count = 0; - - return rc; -} - -static int msm_vidc_load_bus_table(struct platform_device *pdev, - struct msm_vidc_bus_table_gov *data) -{ - int rc = 0, i = 0, j = 0; - const char *name = NULL; - struct bus_profile_entry *entry = NULL; - struct device_node *parent_node = NULL; - struct device_node *child_node = NULL; - - if (!pdev || !data) { - dprintk(VIDC_ERR, "%s: invalid args %pK %pK\n", - __func__, pdev, data); - return -EINVAL; - } - - of_property_read_string(pdev->dev.of_node, "name", &name); - if (strlen(name) > ARRAY_SIZE(data->devfreq_gov.name) - 1) { - dprintk(VIDC_ERR, - "%s: name is too long, max should be %zu chars\n", - __func__, ARRAY_SIZE(data->devfreq_gov.name) - 1); - return -EINVAL; - } - - strlcpy((char *)data->devfreq_gov.name, name, - ARRAY_SIZE(data->devfreq_gov.name)); - data->devfreq_gov.get_target_freq = msm_vidc_table_get_target_freq; - data->devfreq_gov.event_handler = msm_vidc_table_event_handler; - - parent_node = of_find_node_by_name(pdev->dev.of_node, - "qcom,bus-freq-table"); - if (!parent_node) { - dprintk(VIDC_DBG, "Node qcom,bus-freq-table not found.\n"); - return 0; - } - - data->count = of_get_child_count(parent_node); - if (!data->count) { - dprintk(VIDC_DBG, "No child nodes in qcom,bus-freq-table\n"); - return 0; - } - - data->bus_prof_entries = devm_kzalloc(&pdev->dev, - sizeof(*data->bus_prof_entries) * data->count, - GFP_KERNEL); - if (!data->bus_prof_entries) { - dprintk(VIDC_DBG, "no memory to allocate bus_prof_entries\n"); - return -ENOMEM; - } - - for_each_child_of_node(parent_node, child_node) { - - if (i >= data->count) { - dprintk(VIDC_ERR, - "qcom,bus-freq-table: invalid child node %d, max is %d\n", - i, data->count); - break; - } - entry = &data->bus_prof_entries[i]; - - if (of_find_property(child_node, "qcom,codec-mask", NULL)) { - rc = of_property_read_u32(child_node, - "qcom,codec-mask", &entry->codec_mask); - if (rc) { - dprintk(VIDC_ERR, - "qcom,codec-mask not found\n"); - break; - } - } - - if (of_find_property(child_node, "qcom,low-power-mode", NULL)) - entry->profile = VIDC_BUS_PROFILE_LOW; - else if (of_find_property(child_node, "qcom,ubwc-mode", NULL)) - entry->profile = VIDC_BUS_PROFILE_UBWC; - else - entry->profile = VIDC_BUS_PROFILE_NORMAL; - - if (of_find_property(child_node, - "qcom,load-busfreq-tbl", NULL)) { - rc = msm_vidc_load_u32_table(pdev, child_node, - "qcom,load-busfreq-tbl", - sizeof(*entry->bus_table), - (u32 **)&entry->bus_table, - &entry->bus_table_size); - if (rc) { - dprintk(VIDC_ERR, - "qcom,load-busfreq-tbl failed\n"); - break; - } - } else { - entry->bus_table = NULL; - entry->bus_table_size = 0; - } - - dprintk(VIDC_DBG, - "qcom,load-busfreq-tbl: size %d, codec_mask %#x, profile %#x\n", - entry->bus_table_size, entry->codec_mask, - entry->profile); - for (j = 0; j < entry->bus_table_size; j++) - dprintk(VIDC_DBG, " load %8d freq %8d\n", - entry->bus_table[j].load, - entry->bus_table[j].freq); - - i++; - } - - return rc; -} - -static int msm_vidc_bus_table_probe(struct platform_device *pdev) -{ - int rc = 0; - struct msm_vidc_bus_table_gov *gov = NULL; - - dprintk(VIDC_DBG, "%s\n", __func__); - - gov = devm_kzalloc(&pdev->dev, sizeof(*gov), GFP_KERNEL); - if (!gov) { - dprintk(VIDC_ERR, "%s: allocation failed\n", __func__); - return -ENOMEM; - } - - platform_set_drvdata(pdev, gov); - - rc = msm_vidc_load_bus_table(pdev, gov); - if (rc) - return rc; - - rc = devfreq_add_governor(&gov->devfreq_gov); - if (rc) - dprintk(VIDC_ERR, "%s: add governor failed\n", __func__); - - return rc; -} - -static int msm_vidc_bus_table_remove(struct platform_device *pdev) -{ - int rc = 0; - struct msm_vidc_bus_table_gov *gov = NULL; - - dprintk(VIDC_DBG, "%s\n", __func__); - - gov = platform_get_drvdata(pdev); - if (IS_ERR_OR_NULL(gov)) - return PTR_ERR(gov); - - rc = msm_vidc_free_bus_table(pdev, gov); - if (rc) - dprintk(VIDC_WARN, "%s: free bus table failed\n", __func__); - - rc = devfreq_remove_governor(&gov->devfreq_gov); - - return rc; -} - -static const struct of_device_id device_id[] = { - {.compatible = "qcom,msm-vidc,governor,table"}, - {} -}; - -static struct platform_driver msm_vidc_bus_table_driver = { - .probe = msm_vidc_bus_table_probe, - .remove = msm_vidc_bus_table_remove, - .driver = { - .name = "msm_vidc_bus_table_governor", - .of_match_table = device_id, - }, -}; - -static int __init msm_vidc_bus_table_init(void) -{ - - dprintk(VIDC_DBG, "%s\n", __func__); - - return platform_driver_register(&msm_vidc_bus_table_driver); -} - -module_init(msm_vidc_bus_table_init); - -static void __exit msm_vidc_bus_table_exit(void) -{ - dprintk(VIDC_DBG, "%s\n", __func__); - platform_driver_unregister(&msm_vidc_bus_table_driver); -} - -module_exit(msm_vidc_bus_table_exit); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/media/platform/msm/vidc_3x/msm_vidc_res_parse.c b/drivers/media/platform/msm/vidc_3x/msm_vidc_res_parse.c index e6be84736e9e..1518aa442700 100644 --- a/drivers/media/platform/msm/vidc_3x/msm_vidc_res_parse.c +++ b/drivers/media/platform/msm/vidc_3x/msm_vidc_res_parse.c @@ -72,7 +72,23 @@ static inline enum imem_type read_imem_type(struct platform_device *pdev) IMEM_NONE; } +static inline void msm_vidc_free_bus_table( + struct msm_vidc_platform_resources *res) +{ + int i = 0; + struct msm_vidc_bus_table_gov *data = res->gov_data; + + if (!data) { + dprintk(VIDC_ERR, "%s: invalid args %pK\n", + __func__, data); + } + for (i = 0; i < data->count; i++) + data->bus_prof_entries[i].bus_table = NULL; + + data->bus_prof_entries = NULL; + data->count = 0; +} static inline void msm_vidc_free_allowed_clocks_table( struct msm_vidc_platform_resources *res) { @@ -174,6 +190,7 @@ void msm_vidc_free_platform_resources( struct msm_vidc_platform_resources *res) { msm_vidc_free_clock_table(res); + msm_vidc_free_bus_table(res); msm_vidc_free_regulator_table(res); msm_vidc_free_freq_table(res); msm_vidc_free_platform_version_table(res); @@ -1065,7 +1082,108 @@ static int msm_vidc_load_clock_table( err_load_clk_table_fail: return rc; } +static int msm_vidc_load_bus_table(struct msm_vidc_platform_resources *res) +{ + int rc = 0, i = 0, j = 0; + struct bus_profile_entry *entry = NULL; + struct device_node *parent_node = NULL; + struct device_node *child_node = NULL; + struct msm_vidc_bus_table_gov *gov_data; + struct platform_device *pdev = res->pdev; + + dprintk(VIDC_DBG, "%s\n", __func__); + if (!pdev) { + dprintk(VIDC_ERR, "%s: invalid args %pK\n", + __func__, pdev); + return -EINVAL; + } + res->gov_data = devm_kzalloc(&pdev->dev, sizeof(*gov_data), GFP_KERNEL); + if (!res->gov_data) { + dprintk(VIDC_ERR, "%s: allocation failed\n", __func__); + return -ENOMEM; + } + + gov_data = res->gov_data; + parent_node = of_find_node_by_name(pdev->dev.of_node, + "qcom,bus-freq-table"); + if (!parent_node) { + dprintk(VIDC_DBG, "Node qcom,bus-freq-table not found.\n"); + return 0; + } + + gov_data->count = of_get_child_count(parent_node); + if (!gov_data->count) { + dprintk(VIDC_DBG, "No child nodes in qcom,bus-freq-table\n"); + return 0; + } + + gov_data->bus_prof_entries = devm_kzalloc(&pdev->dev, + sizeof(*gov_data->bus_prof_entries) * gov_data->count, + GFP_KERNEL); + if (!gov_data->bus_prof_entries) { + dprintk(VIDC_DBG, "no memory to allocate bus_prof_entries\n"); + return -ENOMEM; + } + + for_each_child_of_node(parent_node, child_node) { + + if (i >= gov_data->count) { + dprintk(VIDC_ERR, + "qcom,bus-freq-table: invalid child node %d, max is %d\n", + i, gov_data->count); + break; + } + entry = &gov_data->bus_prof_entries[i]; + + if (of_find_property(child_node, "qcom,codec-mask", NULL)) { + rc = of_property_read_u32(child_node, + "qcom,codec-mask", &entry->codec_mask); + if (rc) { + dprintk(VIDC_ERR, + "qcom,codec-mask not found\n"); + break; + } + } + + if (of_find_property(child_node, "qcom,low-power-mode", NULL)) + entry->profile = VIDC_BUS_PROFILE_LOW; + else if (of_find_property(child_node, "qcom,ubwc-mode", NULL)) + entry->profile = VIDC_BUS_PROFILE_UBWC; + else + entry->profile = VIDC_BUS_PROFILE_NORMAL; + + if (of_find_property(child_node, + "qcom,load-busfreq-tbl", NULL)) { + rc = msm_vidc_load_u32_table(pdev, child_node, + "qcom,load-busfreq-tbl", + sizeof(*entry->bus_table), + (u32 **)&entry->bus_table, + &entry->bus_table_size); + if (rc) { + dprintk(VIDC_ERR, + "qcom,load-busfreq-tbl failed\n"); + break; + } + } else { + entry->bus_table = NULL; + entry->bus_table_size = 0; + } + + dprintk(VIDC_DBG, + "qcom,load-busfreq-tbl: size %d, codec_mask %#x, profile %#x\n", + entry->bus_table_size, entry->codec_mask, + entry->profile); + for (j = 0; j < entry->bus_table_size; j++) + dprintk(VIDC_DBG, " load %8d freq %8d\n", + entry->bus_table[j].load, + entry->bus_table[j].freq); + + i++; + } + + return rc; +} int read_platform_resources_from_dt( struct msm_vidc_platform_resources *res) { @@ -1185,6 +1303,13 @@ int read_platform_resources_from_dt( goto err_load_allowed_clocks_table; } + rc = msm_vidc_load_bus_table(res); + if (rc) { + dprintk(VIDC_ERR, + "Failed to load bus table: %d\n", rc); + goto err_load_bus_table; + } + rc = of_property_read_u32(pdev->dev.of_node, "qcom,max-hw-load", &res->max_load); if (rc) { @@ -1236,6 +1361,8 @@ int read_platform_resources_from_dt( err_setup_legacy_cb: err_load_max_hw_load: msm_vidc_free_allowed_clocks_table(res); +err_load_bus_table: + msm_vidc_free_bus_table(res); err_load_allowed_clocks_table: msm_vidc_free_cycles_per_mb_table(res); err_load_cycles_per_mb_table: diff --git a/drivers/media/platform/msm/vidc_3x/msm_vidc_resources.h b/drivers/media/platform/msm/vidc_3x/msm_vidc_resources.h index 11ffeee70789..ec1aec3cfca4 100644 --- a/drivers/media/platform/msm/vidc_3x/msm_vidc_resources.h +++ b/drivers/media/platform/msm/vidc_3x/msm_vidc_resources.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2021, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -149,6 +149,26 @@ struct clock_freq_table { u32 count; }; +enum bus_profile { + VIDC_BUS_PROFILE_NORMAL = BIT(0), + VIDC_BUS_PROFILE_LOW = BIT(1), + VIDC_BUS_PROFILE_UBWC = BIT(2), +}; + +struct bus_profile_entry { + struct { + u32 load, freq; + } *bus_table; + u32 bus_table_size; + u32 codec_mask; + enum bus_profile profile; +}; + +struct msm_vidc_bus_table_gov { + struct bus_profile_entry *bus_prof_entries; + u32 count; +}; + struct msm_vidc_platform_resources { phys_addr_t firmware_base; phys_addr_t register_base; @@ -176,6 +196,7 @@ struct msm_vidc_platform_resources { struct platform_device *pdev; struct regulator_set regulator_set; struct clock_set clock_set; + struct msm_vidc_bus_table_gov *gov_data; struct bus_set bus_set; bool use_non_secure_pil; bool sw_power_collapsible; diff --git a/drivers/media/platform/msm/vidc_3x/venus_hfi.c b/drivers/media/platform/msm/vidc_3x/venus_hfi.c index 918d43667819..d25c3c3b2da5 100644 --- a/drivers/media/platform/msm/vidc_3x/venus_hfi.c +++ b/drivers/media/platform/msm/vidc_3x/venus_hfi.c @@ -113,7 +113,10 @@ static inline void __strict_check(struct venus_hfi_device *device) WARN_ON(VIDC_DBG_WARN_ENABLE); } } - +static inline bool is_clock_bus_voted(struct venus_hfi_device *device) +{ + return (device->bus_vote.total_bw_ddr && device->clk_freq); +} static inline void __set_state(struct venus_hfi_device *device, enum venus_hfi_state state) { @@ -812,13 +815,18 @@ static int __vote_buses(struct venus_hfi_device *device, venus_hfi_for_each_bus(device, bus) { if (!bus->is_prfm_gov_used) { - freq = __calc_bw(bus, &device->bus_vote); - rc = __vote_bandwidth(bus, &freq); - } else { + rc = msm_vidc_table_get_target_freq( + device->res->gov_data, + &device->bus_vote, &freq); + if (rc) { + dprintk(VIDC_ERR, "unable to get freq\n"); + return rc; + } + device->bus_vote.total_bw_ddr = freq; + } else freq = bus->range[1]; - rc = __vote_bandwidth(bus, &freq); - } + rc = __vote_bandwidth(bus, &freq); if (rc) return rc; } @@ -1527,6 +1535,12 @@ static int __iface_cmdq_write_relaxed(struct venus_hfi_device *device, goto err_q_write; } + if (cmd_packet->packet_type == HFI_CMD_SESSION_EMPTY_BUFFER && + !is_clock_bus_voted(device)) + dprintk(VIDC_ERR, "%s: bus %llu bps or clock %lu MHz\n", + __func__, device->bus_vote.total_bw_ddr, + device->clk_freq); + if (!__write_queue(q_info, (u8 *)pkt, requires_interrupt)) { if (device->res->sw_power_collapsible) { cancel_delayed_work(&venus_hfi_pm_work); diff --git a/drivers/media/platform/msm/vidc_3x/venus_hfi.h b/drivers/media/platform/msm/vidc_3x/venus_hfi.h index 30e4a1dfdb2d..83a984062d6c 100644 --- a/drivers/media/platform/msm/vidc_3x/venus_hfi.h +++ b/drivers/media/platform/msm/vidc_3x/venus_hfi.h @@ -52,6 +52,10 @@ extern unsigned long __calc_bw(struct bus_info *bus, struct msm_vidc_gov_data *vidc_data); + +extern int msm_vidc_table_get_target_freq(struct msm_vidc_bus_table_gov *gov, + struct msm_vidc_gov_data *vidc_data, + unsigned long *frequency); struct hfi_queue_table_header { u32 qtbl_version; u32 qtbl_size; diff --git a/drivers/media/platform/msm/vidc_3x/vidc_hfi_api.h b/drivers/media/platform/msm/vidc_3x/vidc_hfi_api.h index 6e3bf2eca6eb..c6c0b261694a 100644 --- a/drivers/media/platform/msm/vidc_3x/vidc_hfi_api.h +++ b/drivers/media/platform/msm/vidc_3x/vidc_hfi_api.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1434,6 +1434,7 @@ struct msm_vidc_gov_data { struct vidc_bus_vote_data *data; u32 data_count; int imem_size; + unsigned long total_bw_ddr; }; enum msm_vidc_power_mode { From c585956be3c55e19cef5b83cdf9aac3738f88d58 Mon Sep 17 00:00:00 2001 From: Ahmad Masri Date: Tue, 15 Dec 2020 14:10:04 +0200 Subject: [PATCH 19/55] wil6210: AP should not forward eapol packets In AP mode, the driver checks each received frame, in case it is multicast or unicast packet targeted to one of the AP clients, the driver does the routing in L2 level. EAPOL packet is plaintext frame and it should not follow the above role. When AP receives an EAPOL packet that is multicast or targeted to a client in the AP network, the driver should not forward this packet immediately in L2. EAPOL packet should be indicated to the network stack which will check the packet validity and will decide if to forward the packet to its client or not. Change-Id: I0edf339c3be5a2300e7b8168866286e71045c0d5 Signed-off-by: Ahmad Masri --- drivers/net/wireless/ath/wil6210/txrx.c | 6 ++++-- drivers/net/wireless/ath/wil6210/txrx.h | 9 ++++++++- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/net/wireless/ath/wil6210/txrx.c b/drivers/net/wireless/ath/wil6210/txrx.c index e204a60c2af6..921d9b241d76 100644 --- a/drivers/net/wireless/ath/wil6210/txrx.c +++ b/drivers/net/wireless/ath/wil6210/txrx.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: ISC /* * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. - * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */ #include @@ -935,7 +935,9 @@ void wil_netif_rx(struct sk_buff *skb, struct net_device *ndev, int cid, dev_kfree_skb(skb); goto stats; } - } else if (wdev->iftype == NL80211_IFTYPE_AP && !vif->ap_isolate) { + } else if (wdev->iftype == NL80211_IFTYPE_AP && !vif->ap_isolate && + /* pass EAPOL packets to local net stack only */ + (wil_skb_get_protocol(skb) != htons(ETH_P_PAE))) { if (mcast) { /* send multicast frames both to higher layers in * local net stack and back to the wireless medium diff --git a/drivers/net/wireless/ath/wil6210/txrx.h b/drivers/net/wireless/ath/wil6210/txrx.h index f3b557bad76c..8184d5bef767 100644 --- a/drivers/net/wireless/ath/wil6210/txrx.h +++ b/drivers/net/wireless/ath/wil6210/txrx.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: ISC */ /* * Copyright (c) 2012-2016 Qualcomm Atheros, Inc. - * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */ #ifndef WIL6210_TXRX_H @@ -625,6 +625,13 @@ static inline u8 *wil_skb_get_sa(struct sk_buff *skb) return eth->h_source; } +static inline __be16 wil_skb_get_protocol(struct sk_buff *skb) +{ + struct ethhdr *eth = (void *)skb->data; + + return eth->h_proto; +} + static inline bool wil_need_txstat(struct sk_buff *skb) { const u8 *da = wil_skb_get_da(skb); From c0c39404eead85a63b796f1a2a3c8999138c329e Mon Sep 17 00:00:00 2001 From: Ahmad Masri Date: Sun, 3 Jan 2021 10:27:49 +0200 Subject: [PATCH 20/55] wil6210: Drop plaintext frames on secure network On secure network, only eap frames are valid unencrypted frames and allowed to be indicated to the local network, any other unencrypted frame should be dropped immediately. Change-Id: Id9d97a4c0984f7bf2d7d6941c4c61e87bc2354cd Signed-off-by: Ahmad Masri --- drivers/net/wireless/ath/wil6210/txrx.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/net/wireless/ath/wil6210/txrx.c b/drivers/net/wireless/ath/wil6210/txrx.c index 921d9b241d76..474361b1784e 100644 --- a/drivers/net/wireless/ath/wil6210/txrx.c +++ b/drivers/net/wireless/ath/wil6210/txrx.c @@ -1005,6 +1005,7 @@ void wil_netif_rx_any(struct sk_buff *skb, struct net_device *ndev) { int cid, security; struct wil6210_priv *wil = ndev_to_wil(ndev); + struct wil6210_vif *vif = ndev_to_vif(ndev); struct wil_net_stats *stats; wil->txrx_ops.get_netif_rx_params(skb, &cid, &security); @@ -1013,6 +1014,18 @@ void wil_netif_rx_any(struct sk_buff *skb, struct net_device *ndev) skb_orphan(skb); + /* pass only EAPOL packets as plaintext */ + if (vif->privacy && !security && + wil_skb_get_protocol(skb) != htons(ETH_P_PAE)) { + wil_dbg_txrx(wil, + "Rx drop plaintext frame with %d bytes in secure network\n", + skb->len); + dev_kfree_skb(skb); + ndev->stats.rx_dropped++; + stats->rx_dropped++; + return; + } + if (security && (wil->txrx_ops.rx_crypto_check(wil, skb) != 0)) { dev_kfree_skb(skb); ndev->stats.rx_dropped++; From 669896525ec2f1c0e0f7f644c65f4997cbc2398b Mon Sep 17 00:00:00 2001 From: Ahmad Masri Date: Sun, 15 Nov 2020 17:43:32 +0200 Subject: [PATCH 21/55] wil6210: check integrity of received AMSDU packets Check integrity of received AMSDU packet, 802.11ad QoS spec requires that AMSDU frame contains only MSDUs whose destination address (DA) and sender address (SA) parameter values map to the same receiver address (RA) and transmitter address (TA) values. wil6210 Talyn HW does not check this before it cuts the AMSDU frame into multiple received MSDU packets. Adding checks to wil6210 driver to enforce spec compliance behavior by checking all AMSDU sub frames if it complies with the following: 1- On AP, check packet SA is its client mac address, and on Client check that the DA is the local mac address. If not drop the packet 2- if AMSDU sub frame was dropped on item 1, drop all next sub frame of the AMSDU by checking it has same sn/tid. This patch drops all WDS frames before it checks valid AMSDU, WDS includes supporting MAC header with 4 addresses which is not supported yet, moreover, WDS implies different validity checks on AMSDU frame. Change-Id: I71a39f95c034f05023e0e7ae3ffb5d2b4f8c6b24 Signed-off-by: Ahmad Masri --- drivers/net/wireless/ath/wil6210/cfg80211.c | 2 - drivers/net/wireless/ath/wil6210/main.c | 10 ++- drivers/net/wireless/ath/wil6210/pcie_bus.c | 3 +- drivers/net/wireless/ath/wil6210/txrx_edma.c | 94 +++++++++++++++++++- drivers/net/wireless/ath/wil6210/txrx_edma.h | 20 ++++- drivers/net/wireless/ath/wil6210/wil6210.h | 8 +- drivers/net/wireless/ath/wil6210/wmi.c | 3 +- 7 files changed, 131 insertions(+), 9 deletions(-) diff --git a/drivers/net/wireless/ath/wil6210/cfg80211.c b/drivers/net/wireless/ath/wil6210/cfg80211.c index e1acafed7ad9..7ac7755f60f5 100644 --- a/drivers/net/wireless/ath/wil6210/cfg80211.c +++ b/drivers/net/wireless/ath/wil6210/cfg80211.c @@ -1050,8 +1050,6 @@ static int wil_cfg80211_change_iface(struct wiphy *wiphy, compressed_rx_status = wil->use_compressed_rx_status; if (type == NL80211_IFTYPE_MONITOR) wil->use_compressed_rx_status = false; - else if (wdev->iftype == NL80211_IFTYPE_MONITOR) - wil->use_compressed_rx_status = true; /* do not reset FW when there are active VIFs, * because it can cause significant disruption diff --git a/drivers/net/wireless/ath/wil6210/main.c b/drivers/net/wireless/ath/wil6210/main.c index 875281f710ff..a8eb58ce1559 100644 --- a/drivers/net/wireless/ath/wil6210/main.c +++ b/drivers/net/wireless/ath/wil6210/main.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: ISC /* * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. - * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */ #include @@ -313,6 +313,7 @@ __acquires(&sta->tid_rx_lock) __releases(&sta->tid_rx_lock) /* statistics */ memset(&sta->stats, 0, sizeof(sta->stats)); sta->stats.tx_latency_min_us = U32_MAX; + wil_sta_info_amsdu_init(sta); } static void _wil6210_disconnect_complete(struct wil6210_vif *vif, @@ -723,6 +724,13 @@ void wil_bcast_fini_all(struct wil6210_priv *wil) } } +void wil_sta_info_amsdu_init(struct wil_sta_info *sta) +{ + sta->amsdu_drop_sn = -1; + sta->amsdu_drop_tid = -1; + sta->amsdu_drop = 0; +} + int wil_priv_init(struct wil6210_priv *wil) { uint i; diff --git a/drivers/net/wireless/ath/wil6210/pcie_bus.c b/drivers/net/wireless/ath/wil6210/pcie_bus.c index d326f99a5ad9..e94c90e6b73a 100644 --- a/drivers/net/wireless/ath/wil6210/pcie_bus.c +++ b/drivers/net/wireless/ath/wil6210/pcie_bus.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: ISC /* * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */ #include @@ -98,7 +98,6 @@ int wil_set_capabilities(struct wil6210_priv *wil) set_bit(hw_capa_no_flash, wil->hw_capa); wil->use_enhanced_dma_hw = true; wil->use_rx_hw_reordering = true; - wil->use_compressed_rx_status = true; if (wil_ipa_offload()) /* IPA offload must use single MSI */ n_msi = 1; diff --git a/drivers/net/wireless/ath/wil6210/txrx_edma.c b/drivers/net/wireless/ath/wil6210/txrx_edma.c index c1fe8add5054..029ab790580f 100644 --- a/drivers/net/wireless/ath/wil6210/txrx_edma.c +++ b/drivers/net/wireless/ath/wil6210/txrx_edma.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: ISC /* - * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021 The Linux Foundation. All rights reserved. */ #include @@ -811,6 +811,92 @@ static int wil_tx_ring_modify_edma(struct wil6210_vif *vif, int ring_id, return -EOPNOTSUPP; } +static int wil_check_amsdu(struct wil6210_priv *wil, void *msg, int cid, + struct wil_ring_rx_data *rxdata, + struct sk_buff *skb) +{ + u8 *sa, *da; + int mid, tid; + u16 seq; + struct wil6210_vif *vif; + struct net_device *ndev; + struct wil_sta_info *sta; + + /* drop all WDS packets - not supported */ + if (wil_rx_status_get_ds_type(wil, msg) == WIL_RX_EDMA_DS_TYPE_WDS) { + wil_dbg_txrx(wil, "WDS is not supported"); + return -EAGAIN; + } + + /* check amsdu packets */ + sta = &wil->sta[cid]; + if (!wil_rx_status_is_basic_amsdu(msg)) { + if (sta->amsdu_drop_sn != -1) + wil_sta_info_amsdu_init(sta); + return 0; + } + + mid = wil_rx_status_get_mid(msg); + tid = wil_rx_status_get_tid(msg); + seq = le16_to_cpu(wil_rx_status_get_seq(wil, msg)); + vif = wil->vifs[mid]; + + if (unlikely(!vif)) { + wil_dbg_txrx(wil, "amsdu with invalid mid %d", mid); + return -EAGAIN; + } + + if (unlikely(sta->amsdu_drop)) { + if (sta->amsdu_drop_sn == seq && sta->amsdu_drop_tid == tid) { + wil_dbg_txrx(wil, "Drop AMSDU sub frame, sn=%d\n", + seq); + return -EAGAIN; + } + + /* previous AMSDU finished - clear drop amsdu flag */ + sta->amsdu_drop = 0; + } + + da = wil_skb_get_da(skb); + /* for all sub frame of the AMSDU, check that the SA or DA are valid + * compared with client/AP mac addresses + */ + switch (vif->wdev.iftype) { + case NL80211_IFTYPE_STATION: + case NL80211_IFTYPE_P2P_CLIENT: + if (is_multicast_ether_addr(da)) + return 0; + + /* On client side, DA should be the client mac address */ + ndev = vif_to_ndev(vif); + if (ether_addr_equal(ndev->dev_addr, da)) + return 0; + break; + + case NL80211_IFTYPE_P2P_GO: + case NL80211_IFTYPE_AP: + sa = wil_skb_get_sa(skb); + /* On AP side, the packet SA should be the client mac address. + * check also the DA is not rfc 1042 header + */ + if (ether_addr_equal(sta->addr, sa) && + !ether_addr_equal(rfc1042_header, da)) + return 0; + break; + default: + return 0; + } + + sta->amsdu_drop_sn = seq; + sta->amsdu_drop_tid = tid; + sta->amsdu_drop = 1; + wil_dbg_txrx(wil, + "Drop AMSDU frame, sn=%d. Drop this and all next sub frames\n", + seq); + + return -EAGAIN; +} + /* This function is used only for RX SW reorder */ static int wil_check_bar(struct wil6210_priv *wil, void *msg, int cid, struct sk_buff *skb, struct wil_net_stats *stats) @@ -1159,6 +1245,12 @@ static struct sk_buff *wil_sring_reap_rx_edma(struct wil6210_priv *wil, wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1, skb->data, skb_headlen(skb), false); + if (!wil->use_compressed_rx_status && + wil_check_amsdu(wil, msg, cid, rxdata, skb)) { + kfree_skb(skb); + goto again; + } + /* use radiotap header only if required */ if (ndev->type == ARPHRD_IEEE80211_RADIOTAP) wil_rx_add_radiotap_header_edma(wil, msg, skb); diff --git a/drivers/net/wireless/ath/wil6210/txrx_edma.h b/drivers/net/wireless/ath/wil6210/txrx_edma.h index af6de2927ce7..f84832aeb867 100644 --- a/drivers/net/wireless/ath/wil6210/txrx_edma.h +++ b/drivers/net/wireless/ath/wil6210/txrx_edma.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: ISC */ -/* Copyright (c) 2012-2016,2018-2019, The Linux Foundation. +/* Copyright (c) 2012-2016,2018-2021, The Linux Foundation. * All rights reserved. */ @@ -47,6 +47,9 @@ #define WIL_RX_EDMA_MID_VALID_BIT BIT(22) +#define WIL_RX_EDMA_AMSDU_BASIC_MASK 0x1 +#define WIL_RX_EDMA_DS_TYPE_WDS 0x3 + #define WIL_EDMA_DESC_TX_MAC_CFG_0_QID_POS 16 #define WIL_EDMA_DESC_TX_MAC_CFG_0_QID_LEN 6 @@ -457,6 +460,21 @@ static inline int wil_rx_status_get_fc1(struct wil6210_priv *wil, void *msg) 0, 5) << 2; } +static inline int wil_rx_status_get_ds_type(struct wil6210_priv *wil, void *msg) +{ + if (wil->use_compressed_rx_status) + return 0; + + return WIL_GET_BITS(((struct wil_rx_status_extended *)msg)->ext.d0, + 19, 20); +} + +static inline int wil_rx_status_is_basic_amsdu(void *msg) +{ + return (WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d1, + 28, 29) == WIL_RX_EDMA_AMSDU_BASIC_MASK); +} + static inline __le16 wil_rx_status_get_seq(struct wil6210_priv *wil, void *msg) { if (wil->use_compressed_rx_status) diff --git a/drivers/net/wireless/ath/wil6210/wil6210.h b/drivers/net/wireless/ath/wil6210/wil6210.h index f82bdcad582a..135f781c08b1 100644 --- a/drivers/net/wireless/ath/wil6210/wil6210.h +++ b/drivers/net/wireless/ath/wil6210/wil6210.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: ISC */ /* * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. - * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */ #ifndef __WIL6210_H__ @@ -797,6 +797,11 @@ struct wil_sta_info { struct wil_tid_crypto_rx group_crypto_rx; u8 aid; /* 1-254; 0 if unknown/not reported */ u8 fst_link_loss; + + /* amsdu frame related info to check if the frame is valid */ + int amsdu_drop_sn; + int amsdu_drop_tid; + u8 amsdu_drop; }; enum { @@ -1615,4 +1620,5 @@ int wmi_set_cqm_rssi_config(struct wil6210_priv *wil, int wmi_set_fst_config(struct wil6210_priv *wil, const u8 *bssid, u8 enabled, u8 entry_mcs, u8 exit_mcs, u8 slevel); int wmi_ut_update_txlatency_base(struct wil6210_priv *wil); +void wil_sta_info_amsdu_init(struct wil_sta_info *sta); #endif /* __WIL6210_H__ */ diff --git a/drivers/net/wireless/ath/wil6210/wmi.c b/drivers/net/wireless/ath/wil6210/wmi.c index 862eedf76caa..e33020f4dba4 100644 --- a/drivers/net/wireless/ath/wil6210/wmi.c +++ b/drivers/net/wireless/ath/wil6210/wmi.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: ISC /* * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. - * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */ #include @@ -1102,6 +1102,7 @@ static void wmi_evt_connect(struct wil6210_vif *vif, int id, void *d, int len) ether_addr_copy(wil->sta[evt->cid].addr, evt->bssid); wil->sta[evt->cid].mid = vif->mid; wil->sta[evt->cid].status = wil_sta_conn_pending; + wil_sta_info_amsdu_init(&wil->sta[evt->cid]); rc = wil_ring_init_tx(vif, evt->cid); if (rc) { From 9093207fa93ecdd0198c61b9c38aaac641f4ee54 Mon Sep 17 00:00:00 2001 From: Prateek Raj Singh Date: Mon, 10 May 2021 14:41:23 +0530 Subject: [PATCH 22/55] Add support for new comanche 1.3 soc ID Added support for new comanche 1.3 soc ID CRs-Fixed: 2942015 Change-Id: I2f1be9127db74614b9d5c2f797468da85559c60e Signed-off-by: Prateek Raj Singh --- drivers/bluetooth/btfm_slim_slave.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/bluetooth/btfm_slim_slave.h b/drivers/bluetooth/btfm_slim_slave.h index 0dbdbfbcd4e6..e706fa916fc8 100644 --- a/drivers/bluetooth/btfm_slim_slave.h +++ b/drivers/bluetooth/btfm_slim_slave.h @@ -98,6 +98,7 @@ enum { QCA_COMANCHE_SOC_ID_0110 = 0x40070110, QCA_COMANCHE_SOC_ID_0120 = 0x40070120, QCA_COMANCHE_SOC_ID_0130 = 0x40070130, + QCA_COMANCHE_SOC_ID_4130 = 0x40074130, QCA_COMANCHE_SOC_ID_5120 = 0x40075120, QCA_COMANCHE_SOC_ID_5130 = 0x40075130, }; From 657fc56243cbe328a723ed53ec40979444d5c281 Mon Sep 17 00:00:00 2001 From: Armaan Siddiqui Date: Tue, 27 Apr 2021 10:54:38 +0530 Subject: [PATCH 23/55] ipa: Remove overwrite copy Add change to remove copy from user module twice. As it was casuing overwrite error. Change-Id: I7ce252d22679f5963ad4d8852040c48c90d03b4a Signed-off-by: Armaan Siddiqui --- drivers/platform/msm/ipa/ipa_v2/ipa.c | 95 +++++---------------------- 1 file changed, 18 insertions(+), 77 deletions(-) diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa.c b/drivers/platform/msm/ipa/ipa_v2/ipa.c index 7e8e083d8715..9a528dea30cf 100644 --- a/drivers/platform/msm/ipa/ipa_v2/ipa.c +++ b/drivers/platform/msm/ipa/ipa_v2/ipa.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2012-2018, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2018, 2020-2021, The Linux Foundation. All rights reserved. */ #include @@ -654,15 +654,11 @@ static long ipa_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) sizeof(struct ipa_ioc_nat_dma_cmd) + pre_entry * sizeof(struct ipa_ioc_nat_dma_one); param = memdup_user((const void __user *)arg, pyld_sz); - if (!param) { + if (IS_ERR(param)) { retval = -ENOMEM; break; } - if (copy_from_user(param, (const void __user *)arg, pyld_sz)) { - retval = -EFAULT; - break; - } /* add check in case user-space module compromised */ if (unlikely(((struct ipa_ioc_nat_dma_cmd *)param)->entries != pre_entry)) { @@ -702,14 +698,10 @@ static long ipa_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) sizeof(struct ipa_ioc_add_hdr) + pre_entry * sizeof(struct ipa_hdr_add); param = memdup_user((const void __user *)arg, pyld_sz); - if (!param) { + if (IS_ERR(param)) { retval = -ENOMEM; break; } - if (copy_from_user(param, (const void __user *)arg, pyld_sz)) { - retval = -EFAULT; - break; - } /* add check in case user-space module compromised */ if (unlikely(((struct ipa_ioc_add_hdr *)param)->num_hdrs != pre_entry)) { @@ -742,14 +734,10 @@ static long ipa_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) sizeof(struct ipa_ioc_del_hdr) + pre_entry * sizeof(struct ipa_hdr_del); param = memdup_user((const void __user *)arg, pyld_sz); - if (!param) { + if (IS_ERR(param)) { retval = -ENOMEM; break; } - if (copy_from_user(param, (const void __user *)arg, pyld_sz)) { - retval = -EFAULT; - break; - } /* add check in case user-space module compromised */ if (unlikely(((struct ipa_ioc_del_hdr *)param)->num_hdls != pre_entry)) { @@ -782,14 +770,10 @@ static long ipa_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) sizeof(struct ipa_ioc_add_rt_rule) + pre_entry * sizeof(struct ipa_rt_rule_add); param = memdup_user((const void __user *)arg, pyld_sz); - if (!param) { + if (IS_ERR(param)) { retval = -ENOMEM; break; } - if (copy_from_user(param, (const void __user *)arg, pyld_sz)) { - retval = -EFAULT; - break; - } /* add check in case user-space module compromised */ if (unlikely(((struct ipa_ioc_add_rt_rule *)param)->num_rules != pre_entry)) { @@ -823,14 +807,10 @@ static long ipa_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) sizeof(struct ipa_ioc_mdfy_rt_rule) + pre_entry * sizeof(struct ipa_rt_rule_mdfy); param = memdup_user((const void __user *)arg, pyld_sz); - if (!param) { + if (IS_ERR(param)) { retval = -ENOMEM; break; } - if (copy_from_user(param, (const void __user *)arg, pyld_sz)) { - retval = -EFAULT; - break; - } /* add check in case user-space module compromised */ if (unlikely(((struct ipa_ioc_mdfy_rt_rule *)param)->num_rules != pre_entry)) { @@ -863,14 +843,10 @@ static long ipa_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) sizeof(struct ipa_ioc_del_rt_rule) + pre_entry * sizeof(struct ipa_rt_rule_del); param = memdup_user((const void __user *)arg, pyld_sz); - if (!param) { + if (IS_ERR(param)) { retval = -ENOMEM; break; } - if (copy_from_user(param, (const void __user *)arg, pyld_sz)) { - retval = -EFAULT; - break; - } /* add check in case user-space module compromised */ if (unlikely(((struct ipa_ioc_del_rt_rule *)param)->num_hdls != pre_entry)) { @@ -902,14 +878,10 @@ static long ipa_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) sizeof(struct ipa_ioc_add_flt_rule) + pre_entry * sizeof(struct ipa_flt_rule_add); param = memdup_user((const void __user *)arg, pyld_sz); - if (!param) { + if (IS_ERR(param)) { retval = -ENOMEM; break; } - if (copy_from_user(param, (const void __user *)arg, pyld_sz)) { - retval = -EFAULT; - break; - } /* add check in case user-space module compromised */ if (unlikely(((struct ipa_ioc_add_flt_rule *)param)->num_rules != pre_entry)) { @@ -943,14 +915,10 @@ static long ipa_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) sizeof(struct ipa_ioc_del_flt_rule) + pre_entry * sizeof(struct ipa_flt_rule_del); param = memdup_user((const void __user *)arg, pyld_sz); - if (!param) { + if (IS_ERR(param)) { retval = -ENOMEM; break; } - if (copy_from_user(param, (const void __user *)arg, pyld_sz)) { - retval = -EFAULT; - break; - } /* add check in case user-space module compromised */ if (unlikely(((struct ipa_ioc_del_flt_rule *)param)->num_hdls != pre_entry)) { @@ -983,14 +951,10 @@ static long ipa_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) sizeof(struct ipa_ioc_mdfy_flt_rule) + pre_entry * sizeof(struct ipa_flt_rule_mdfy); param = memdup_user((const void __user *)arg, pyld_sz); - if (!param) { + if (IS_ERR(param)) { retval = -ENOMEM; break; } - if (copy_from_user(param, (const void __user *)arg, pyld_sz)) { - retval = -EFAULT; - break; - } /* add check in case user-space module compromised */ if (unlikely(((struct ipa_ioc_mdfy_flt_rule *)param)->num_rules != pre_entry)) { @@ -1120,14 +1084,10 @@ static long ipa_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) pyld_sz = sz + pre_entry * sizeof(struct ipa_ioc_tx_intf_prop); param = memdup_user((const void __user *)arg, pyld_sz); - if (!param) { + if (IS_ERR(param)) { retval = -ENOMEM; break; } - if (copy_from_user(param, (const void __user *)arg, pyld_sz)) { - retval = -EFAULT; - break; - } /* add check in case user-space module compromised */ if (unlikely(((struct ipa_ioc_query_intf_tx_props *) param)->num_tx_props @@ -1166,14 +1126,10 @@ static long ipa_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) pyld_sz = sz + pre_entry * sizeof(struct ipa_ioc_rx_intf_prop); param = memdup_user((const void __user *)arg, pyld_sz); - if (!param) { + if (IS_ERR(param)) { retval = -ENOMEM; break; } - if (copy_from_user(param, (const void __user *)arg, pyld_sz)) { - retval = -EFAULT; - break; - } /* add check in case user-space module compromised */ if (unlikely(((struct ipa_ioc_query_intf_rx_props *) param)->num_rx_props != pre_entry)) { @@ -1211,14 +1167,10 @@ static long ipa_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) pyld_sz = sz + pre_entry * sizeof(struct ipa_ioc_ext_intf_prop); param = memdup_user((const void __user *)arg, pyld_sz); - if (!param) { + if (IS_ERR(param)) { retval = -ENOMEM; break; } - if (copy_from_user(param, (const void __user *)arg, pyld_sz)) { - retval = -EFAULT; - break; - } /* add check in case user-space module compromised */ if (unlikely(((struct ipa_ioc_query_intf_ext_props *) param)->num_ext_props != pre_entry)) { @@ -1249,14 +1201,10 @@ static long ipa_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) pyld_sz = sizeof(struct ipa_msg_meta) + pre_entry; param = memdup_user((const void __user *)arg, pyld_sz); - if (!param) { + if (IS_ERR(param)) { retval = -ENOMEM; break; } - if (copy_from_user(param, (const void __user *)arg, pyld_sz)) { - retval = -EFAULT; - break; - } /* add check in case user-space module compromised */ if (unlikely(((struct ipa_msg_meta *)param)->msg_len != pre_entry)) { @@ -1389,14 +1337,10 @@ static long ipa_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) sizeof(struct ipa_ioc_add_hdr_proc_ctx) + pre_entry * sizeof(struct ipa_hdr_proc_ctx_add); param = memdup_user((const void __user *)arg, pyld_sz); - if (!param) { + if (IS_ERR(param)) { retval = -ENOMEM; break; } - if (copy_from_user(param, (const void __user *)arg, pyld_sz)) { - retval = -EFAULT; - break; - } /* add check in case user-space module compromised */ if (unlikely(((struct ipa_ioc_add_hdr_proc_ctx *) param)->num_proc_ctxs != pre_entry)) { @@ -1428,14 +1372,10 @@ static long ipa_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) sizeof(struct ipa_ioc_del_hdr_proc_ctx) + pre_entry * sizeof(struct ipa_hdr_proc_ctx_del); param = memdup_user((const void __user *)arg, pyld_sz); - if (!param) { + if (IS_ERR(param)) { retval = -ENOMEM; break; } - if (copy_from_user(param, (const void __user *)arg, pyld_sz)) { - retval = -EFAULT; - break; - } /* add check in case user-space module compromised */ if (unlikely(((struct ipa_ioc_del_hdr_proc_ctx *) param)->num_hdls != pre_entry)) { @@ -1490,7 +1430,8 @@ static long ipa_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); return -ENOTTY; } - kfree(param); + if (!IS_ERR(param)) + kfree(param); IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); From 11af969929b6f1841e2717654f0a0461b8bb0152 Mon Sep 17 00:00:00 2001 From: Vandana Jain Date: Wed, 19 May 2021 18:27:32 +0530 Subject: [PATCH 24/55] msm: camera: Update SDM439 csiphy driver Add DDL tuning settings. Change-Id: Ib03ded16a37bdc6102aaee92096ec5749a2684c9 Signed-off-by: Vandana Jain --- .../csiphy/include/msm_csiphy_10_0_0_hwreg.h | 6 ++++- .../msm/camera_v2/sensor/csiphy/msm_csiphy.c | 26 +++++++++++++++++++ .../msm/camera_v2/sensor/csiphy/msm_csiphy.h | 6 ++++- 3 files changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_10_0_0_hwreg.h b/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_10_0_0_hwreg.h index ccea30e0e181..5c7da45260a6 100644 --- a/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_10_0_0_hwreg.h +++ b/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_10_0_0_hwreg.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018, 2021, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -73,6 +73,10 @@ static struct csiphy_reg_snps_parms_t csiphy_v10_0_0_snps = { {0x12c, 0x0}, /* mipi_csiphy_rx_lane_0_7_00 */ {0x220, 0x0}, /* mipi_csiphy_rx_lane_1_7_00 */ {0xCC, 0x0}, /* mipi_csiphy_rx_clk_lane_7_00 */ + {0x1F8, 0x20}, /* mipi_csiphy_rx_lane0_ddl_2_00 */ + {0x1FC, 0x10}, /* mipi_csiphy_rx_lane0_ddl_3_00 */ + {0x22C, 0x80}, /* mipi_csiphy_rx_lane_1_10_00 */ + {0x230, 0x10}, /* mipi_csiphy_rx_lane_1_11_00 */ }; static struct snps_freq_value snps_v100_freq_values[] = { diff --git a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c index 014087c63c24..033a0e6bb31c 100644 --- a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c +++ b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c @@ -292,6 +292,32 @@ static int msm_csiphy_snps_2_lane_config( csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg .mipi_csiphy_rx_cb_2_00.addr + offset); + if (local_data_rate <= 1500) { + msm_camera_io_w( + csiphy_dev->ctrl_reg->csiphy_snps_reg + .mipi_csiphy_rx_lane0_ddl_2_00.data, + csiphybase + + csiphy_dev->ctrl_reg->csiphy_snps_reg + .mipi_csiphy_rx_lane0_ddl_2_00.addr + offset); + + msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg + .mipi_csiphy_rx_lane0_ddl_3_00.data, + csiphybase + + csiphy_dev->ctrl_reg->csiphy_snps_reg + .mipi_csiphy_rx_lane0_ddl_3_00.addr + offset); + + msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg + .mipi_csiphy_rx_lane_1_10_00.data, + csiphybase + + csiphy_dev->ctrl_reg->csiphy_snps_reg + .mipi_csiphy_rx_lane_1_10_00.addr + offset); + + msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg + .mipi_csiphy_rx_lane_1_11_00.data, + csiphybase + + csiphy_dev->ctrl_reg->csiphy_snps_reg + .mipi_csiphy_rx_lane_1_11_00.addr + offset); + } return 0; } diff --git a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h index 7a068572d008..498a08b8e48b 100644 --- a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h +++ b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2011-2018, 2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2011-2018, 2020-2021, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -100,6 +100,10 @@ struct csiphy_reg_snps_parms_t { struct csiphy_reg_t mipi_csiphy_rx_lane_0_7_00; struct csiphy_reg_t mipi_csiphy_rx_lane_1_7_00; struct csiphy_reg_t mipi_csiphy_rx_clk_lane_7_00; + struct csiphy_reg_t mipi_csiphy_rx_lane0_ddl_2_00; + struct csiphy_reg_t mipi_csiphy_rx_lane0_ddl_3_00; + struct csiphy_reg_t mipi_csiphy_rx_lane_1_10_00; + struct csiphy_reg_t mipi_csiphy_rx_lane_1_11_00; }; struct csiphy_reg_3ph_parms_t { From c1a6f7ee85852044a2093d70abb8e3452dacc790 Mon Sep 17 00:00:00 2001 From: Vasantha Balla Date: Mon, 17 May 2021 11:30:21 +0530 Subject: [PATCH 25/55] vidc_3x: Change to avoid unloading firmware No need to unload video firmware after session closure. So change added to made it as persistent. Change-Id: I7dbb87209bcc0d521fcd498fb980143a886a6493 Signed-off-by: Vasantha Balla --- .../platform/msm/vidc_3x/msm_v4l2_vidc.c | 3 +- .../platform/msm/vidc_3x/msm_vidc_common.c | 61 +------------------ .../platform/msm/vidc_3x/msm_vidc_internal.h | 4 +- .../platform/msm/vidc_3x/msm_vidc_res_parse.c | 3 - .../platform/msm/vidc_3x/msm_vidc_resources.h | 1 - 5 files changed, 4 insertions(+), 68 deletions(-) diff --git a/drivers/media/platform/msm/vidc_3x/msm_v4l2_vidc.c b/drivers/media/platform/msm/vidc_3x/msm_v4l2_vidc.c index 00a35099babd..a94198f5b3ab 100644 --- a/drivers/media/platform/msm/vidc_3x/msm_v4l2_vidc.c +++ b/drivers/media/platform/msm/vidc_3x/msm_v4l2_vidc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -334,7 +334,6 @@ static int msm_vidc_initialize_core(struct platform_device *pdev, init_completion(&core->completions[i]); } - INIT_DELAYED_WORK(&core->fw_unload_work, msm_vidc_fw_unload_handler); return rc; } diff --git a/drivers/media/platform/msm/vidc_3x/msm_vidc_common.c b/drivers/media/platform/msm/vidc_3x/msm_vidc_common.c index 3dcb707a7d2a..bae2b39a088f 100644 --- a/drivers/media/platform/msm/vidc_3x/msm_vidc_common.c +++ b/drivers/media/platform/msm/vidc_3x/msm_vidc_common.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -2831,35 +2831,15 @@ static int msm_vidc_deinit_core(struct msm_vidc_inst *inst) if (core->state == VIDC_CORE_UNINIT) { dprintk(VIDC_INFO, "Video core: %d is already in state: %d\n", core->id, core->state); + mutex_unlock(&core->lock); goto core_already_uninited; } mutex_unlock(&core->lock); msm_comm_scale_clocks_and_bus(inst); - mutex_lock(&core->lock); - - if (!core->resources.never_unload_fw) { - cancel_delayed_work(&core->fw_unload_work); - - /* - * Delay unloading of firmware. This is useful - * in avoiding firmware download delays in cases where we - * will have a burst of back to back video playback sessions - * e.g. thumbnail generation. - */ - schedule_delayed_work(&core->fw_unload_work, - msecs_to_jiffies(core->state == VIDC_CORE_INVALID ? - 0 : msm_vidc_firmware_unload_delay)); - - dprintk(VIDC_DBG, "firmware unload delayed by %u ms\n", - core->state == VIDC_CORE_INVALID ? - 0 : msm_vidc_firmware_unload_delay); - } - core_already_uninited: change_inst_state(inst, MSM_VIDC_CORE_UNINIT); - mutex_unlock(&core->lock); return 0; } @@ -5313,43 +5293,6 @@ int msm_comm_smem_cache_operations(struct msm_vidc_inst *inst, mem->size, cache_ops); } -void msm_vidc_fw_unload_handler(struct work_struct *work) -{ - struct msm_vidc_core *core = NULL; - struct hfi_device *hdev = NULL; - int rc = 0; - - core = container_of(work, struct msm_vidc_core, fw_unload_work.work); - if (!core || !core->device) { - dprintk(VIDC_ERR, "%s - invalid work or core handle\n", - __func__); - return; - } - - hdev = core->device; - - mutex_lock(&core->lock); - if (list_empty(&core->instances) && - core->state != VIDC_CORE_UNINIT) { - if (core->state > VIDC_CORE_INIT) { - dprintk(VIDC_DBG, "Calling vidc_hal_core_release\n"); - rc = call_hfi_op(hdev, core_release, - hdev->hfi_device_data); - if (rc) { - dprintk(VIDC_ERR, - "Failed to release core, id = %d\n", - core->id); - mutex_unlock(&core->lock); - return; - } - } - core->state = VIDC_CORE_UNINIT; - kfree(core->capabilities); - core->capabilities = NULL; - } - mutex_unlock(&core->lock); -} - int msm_comm_set_color_format(struct msm_vidc_inst *inst, enum hal_buffer buffer_type, int fourcc) { diff --git a/drivers/media/platform/msm/vidc_3x/msm_vidc_internal.h b/drivers/media/platform/msm/vidc_3x/msm_vidc_internal.h index c008d8ff3cb9..5b2daa3c4394 100644 --- a/drivers/media/platform/msm/vidc_3x/msm_vidc_internal.h +++ b/drivers/media/platform/msm/vidc_3x/msm_vidc_internal.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -262,7 +262,6 @@ struct msm_vidc_core { u32 dec_codec_supported; u32 codec_count; struct msm_vidc_capability *capabilities; - struct delayed_work fw_unload_work; bool smmu_fault_handled; }; @@ -414,7 +413,6 @@ struct msm_smem *msm_smem_user_to_kernel(struct msm_vidc_inst *inst, int fd, u32 offset, u32 size, enum hal_buffer buffer_type); -void msm_vidc_fw_unload_handler(struct work_struct *work); /* XXX: normally should be in msm_vidc.h, but that's meant for public APIs, * whereas this is private */ diff --git a/drivers/media/platform/msm/vidc_3x/msm_vidc_res_parse.c b/drivers/media/platform/msm/vidc_3x/msm_vidc_res_parse.c index 1518aa442700..6874a5dcb89d 100644 --- a/drivers/media/platform/msm/vidc_3x/msm_vidc_res_parse.c +++ b/drivers/media/platform/msm/vidc_3x/msm_vidc_res_parse.c @@ -1341,9 +1341,6 @@ int read_platform_resources_from_dt( dprintk(VIDC_DBG, "Power collapse supported = %s\n", res->sw_power_collapsible ? "yes" : "no"); - res->never_unload_fw = of_property_read_bool(pdev->dev.of_node, - "qcom,never-unload-fw"); - of_property_read_u32(pdev->dev.of_node, "qcom,pm-qos-latency-us", &res->pm_qos_latency_us); diff --git a/drivers/media/platform/msm/vidc_3x/msm_vidc_resources.h b/drivers/media/platform/msm/vidc_3x/msm_vidc_resources.h index ec1aec3cfca4..fd4709649fac 100644 --- a/drivers/media/platform/msm/vidc_3x/msm_vidc_resources.h +++ b/drivers/media/platform/msm/vidc_3x/msm_vidc_resources.h @@ -206,7 +206,6 @@ struct msm_vidc_platform_resources { bool thermal_mitigable; const char *fw_name; const char *hfi_version; - bool never_unload_fw; uint32_t pm_qos_latency_us; uint32_t max_inst_count; uint32_t max_secure_inst_count; From f7555bd85ba3351be4d33c7ed47661065309b40f Mon Sep 17 00:00:00 2001 From: Anjaneya Prasad Musunuri Date: Thu, 20 May 2021 15:04:17 +0530 Subject: [PATCH 26/55] msm: drm: uapi: add rounded corner uapi Add uapi for rounded corner programming. Change-Id: I920e1c617bc1f388f81e4e283cb5bde8ed0f7a10 Signed-off-by: Anjaneya Prasad Musunuri --- include/uapi/drm/msm_drm_pp.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/include/uapi/drm/msm_drm_pp.h b/include/uapi/drm/msm_drm_pp.h index 34a4833ecf78..74cb59e17e68 100644 --- a/include/uapi/drm/msm_drm_pp.h +++ b/include/uapi/drm/msm_drm_pp.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #ifndef _MSM_DRM_PP_H_ @@ -573,4 +573,21 @@ struct drm_msm_ad4_manual_str_cfg { __u32 in_str; __u32 out_str; }; + +#define RC_DATA_SIZE_MAX 2720 +#define RC_CFG_SIZE_MAX 4 + +struct drm_msm_rc_mask_cfg { + __u64 flags; + __u32 cfg_param_01; + __u32 cfg_param_02; + __u32 cfg_param_03; + __u32 cfg_param_04[RC_CFG_SIZE_MAX]; + __u32 cfg_param_05[RC_CFG_SIZE_MAX]; + __u32 cfg_param_06[RC_CFG_SIZE_MAX]; + __u64 cfg_param_07; + __u32 cfg_param_08; + __u64 cfg_param_09[RC_DATA_SIZE_MAX]; +}; + #endif /* _MSM_DRM_PP_H_ */ From be68fd2d3720cd2fd75edd89447886100853f4f7 Mon Sep 17 00:00:00 2001 From: Madhuri Medasani Date: Wed, 28 Apr 2021 16:49:31 +0530 Subject: [PATCH 27/55] dt-bindings: clock: Add support for KHAJE clock ids Add clock IDs for GCC/GPUCC/DISPCC for clients to be able to request for clocks from these clock controllers. Change-Id: I77e932413711121c5fab63d9b3436390b9f8014c Signed-off-by: Madhuri Medasani --- include/dt-bindings/clock/qcom,dispcc-khaje.h | 34 ++++ include/dt-bindings/clock/qcom,gcc-khaje.h | 188 ++++++++++++++++++ include/dt-bindings/clock/qcom,gpucc-khaje.h | 27 +++ 3 files changed, 249 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,dispcc-khaje.h create mode 100644 include/dt-bindings/clock/qcom,gcc-khaje.h create mode 100644 include/dt-bindings/clock/qcom,gpucc-khaje.h diff --git a/include/dt-bindings/clock/qcom,dispcc-khaje.h b/include/dt-bindings/clock/qcom,dispcc-khaje.h new file mode 100644 index 000000000000..3c0de28206b3 --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-khaje.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_KHAJE_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_KHAJE_H + +/* DISP_CC clocks */ +#define DISP_CC_PLL0 0 +#define DISP_CC_MDSS_AHB_CLK 1 +#define DISP_CC_MDSS_AHB_CLK_SRC 2 +#define DISP_CC_MDSS_BYTE0_CLK 3 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 4 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 6 +#define DISP_CC_MDSS_ESC0_CLK 7 +#define DISP_CC_MDSS_ESC0_CLK_SRC 8 +#define DISP_CC_MDSS_MDP_CLK 9 +#define DISP_CC_MDSS_MDP_CLK_SRC 10 +#define DISP_CC_MDSS_MDP_LUT_CLK 11 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 12 +#define DISP_CC_MDSS_PCLK0_CLK 13 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 14 +#define DISP_CC_MDSS_ROT_CLK 15 +#define DISP_CC_MDSS_ROT_CLK_SRC 16 +#define DISP_CC_MDSS_RSCC_AHB_CLK 17 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 18 +#define DISP_CC_MDSS_VSYNC_CLK 19 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 20 +#define DISP_CC_SLEEP_CLK 21 +#define DISP_CC_XO_CLK 22 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-khaje.h b/include/dt-bindings/clock/qcom,gcc-khaje.h new file mode 100644 index 000000000000..b0e820190ada --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-khaje.h @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_KHAJE_H +#define _DT_BINDINGS_CLK_QCOM_GCC_KHAJE_H + +/* GCC clocks */ +#define GPLL0 0 +#define GPLL0_OUT_EVEN 1 +#define GPLL1 2 +#define GPLL10 3 +#define GPLL11 4 +#define GPLL3 5 +#define GPLL3_OUT_EVEN 6 +#define GPLL4 7 +#define GPLL5 8 +#define GPLL6 9 +#define GPLL6_OUT_EVEN 10 +#define GPLL7 11 +#define GPLL8 12 +#define GPLL8_OUT_EVEN 13 +#define GPLL9 14 +#define GPLL9_OUT_MAIN 15 +#define GCC_AHB2PHY_CSI_CLK 16 +#define GCC_AHB2PHY_USB_CLK 17 +#define GCC_BIMC_GPU_AXI_CLK 18 +#define GCC_BOOT_ROM_AHB_CLK 19 +#define GCC_CAM_THROTTLE_NRT_CLK 20 +#define GCC_CAM_THROTTLE_RT_CLK 21 +#define GCC_CAMERA_AHB_CLK 22 +#define GCC_CAMERA_XO_CLK 23 +#define GCC_CAMSS_AXI_CLK 24 +#define GCC_CAMSS_AXI_CLK_SRC 25 +#define GCC_CAMSS_CAMNOC_ATB_CLK 26 +#define GCC_CAMSS_CAMNOC_NTS_XO_CLK 27 +#define GCC_CAMSS_CCI_0_CLK 28 +#define GCC_CAMSS_CCI_CLK_SRC 29 +#define GCC_CAMSS_CPHY_0_CLK 30 +#define GCC_CAMSS_CPHY_1_CLK 31 +#define GCC_CAMSS_CPHY_2_CLK 32 +#define GCC_CAMSS_CSI0PHYTIMER_CLK 33 +#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 34 +#define GCC_CAMSS_CSI1PHYTIMER_CLK 35 +#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 36 +#define GCC_CAMSS_CSI2PHYTIMER_CLK 37 +#define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC 38 +#define GCC_CAMSS_MCLK0_CLK 39 +#define GCC_CAMSS_MCLK0_CLK_SRC 40 +#define GCC_CAMSS_MCLK1_CLK 41 +#define GCC_CAMSS_MCLK1_CLK_SRC 42 +#define GCC_CAMSS_MCLK2_CLK 43 +#define GCC_CAMSS_MCLK2_CLK_SRC 44 +#define GCC_CAMSS_MCLK3_CLK 45 +#define GCC_CAMSS_MCLK3_CLK_SRC 46 +#define GCC_CAMSS_NRT_AXI_CLK 47 +#define GCC_CAMSS_OPE_AHB_CLK 48 +#define GCC_CAMSS_OPE_AHB_CLK_SRC 49 +#define GCC_CAMSS_OPE_CLK 50 +#define GCC_CAMSS_OPE_CLK_SRC 51 +#define GCC_CAMSS_RT_AXI_CLK 52 +#define GCC_CAMSS_TFE_0_CLK 53 +#define GCC_CAMSS_TFE_0_CLK_SRC 54 +#define GCC_CAMSS_TFE_0_CPHY_RX_CLK 55 +#define GCC_CAMSS_TFE_0_CSID_CLK 56 +#define GCC_CAMSS_TFE_0_CSID_CLK_SRC 57 +#define GCC_CAMSS_TFE_1_CLK 58 +#define GCC_CAMSS_TFE_1_CLK_SRC 59 +#define GCC_CAMSS_TFE_1_CPHY_RX_CLK 60 +#define GCC_CAMSS_TFE_1_CSID_CLK 61 +#define GCC_CAMSS_TFE_1_CSID_CLK_SRC 62 +#define GCC_CAMSS_TFE_2_CLK 63 +#define GCC_CAMSS_TFE_2_CLK_SRC 64 +#define GCC_CAMSS_TFE_2_CPHY_RX_CLK 65 +#define GCC_CAMSS_TFE_2_CSID_CLK 66 +#define GCC_CAMSS_TFE_2_CSID_CLK_SRC 67 +#define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC 68 +#define GCC_CAMSS_TOP_AHB_CLK 69 +#define GCC_CAMSS_TOP_AHB_CLK_SRC 70 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 71 +#define GCC_CPUSS_GNOC_CLK 72 +#define GCC_DISP_AHB_CLK 73 +#define GCC_DISP_GPLL0_CLK_SRC 74 +#define GCC_DISP_GPLL0_DIV_CLK_SRC 75 +#define GCC_DISP_HF_AXI_CLK 76 +#define GCC_DISP_SLEEP_CLK 77 +#define GCC_DISP_THROTTLE_CORE_CLK 78 +#define GCC_DISP_XO_CLK 79 +#define GCC_GP1_CLK 80 +#define GCC_GP1_CLK_SRC 81 +#define GCC_GP2_CLK 82 +#define GCC_GP2_CLK_SRC 83 +#define GCC_GP3_CLK 84 +#define GCC_GP3_CLK_SRC 85 +#define GCC_GPU_CFG_AHB_CLK 86 +#define GCC_GPU_GPLL0_CLK_SRC 87 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 88 +#define GCC_GPU_IREF_CLK 89 +#define GCC_GPU_MEMNOC_GFX_CLK 90 +#define GCC_GPU_SNOC_DVM_GFX_CLK 91 +#define GCC_GPU_THROTTLE_CORE_CLK 92 +#define GCC_PDM2_CLK 93 +#define GCC_PDM2_CLK_SRC 94 +#define GCC_PDM_AHB_CLK 95 +#define GCC_PDM_XO4_CLK 96 +#define GCC_PRNG_AHB_CLK 97 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 98 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 99 +#define GCC_QMIP_DISP_AHB_CLK 100 +#define GCC_QMIP_GPU_CFG_AHB_CLK 101 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 102 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 103 +#define GCC_QUPV3_WRAP0_CORE_CLK 104 +#define GCC_QUPV3_WRAP0_S0_CLK 105 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 106 +#define GCC_QUPV3_WRAP0_S1_CLK 107 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 108 +#define GCC_QUPV3_WRAP0_S2_CLK 109 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 110 +#define GCC_QUPV3_WRAP0_S3_CLK 111 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 112 +#define GCC_QUPV3_WRAP0_S4_CLK 113 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 114 +#define GCC_QUPV3_WRAP0_S5_CLK 115 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 116 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 117 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 118 +#define GCC_SDCC1_AHB_CLK 119 +#define GCC_SDCC1_APPS_CLK 120 +#define GCC_SDCC1_APPS_CLK_SRC 121 +#define GCC_SDCC1_ICE_CORE_CLK 122 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 123 +#define GCC_SDCC2_AHB_CLK 124 +#define GCC_SDCC2_APPS_CLK 125 +#define GCC_SDCC2_APPS_CLK_SRC 126 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 127 +#define GCC_SYS_NOC_UFS_PHY_AXI_CLK 128 +#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 129 +#define GCC_UFS_CLKREF_CLK 130 +#define GCC_UFS_PHY_AHB_CLK 131 +#define GCC_UFS_PHY_AXI_CLK 132 +#define GCC_UFS_PHY_AXI_CLK_SRC 133 +#define GCC_UFS_PHY_ICE_CORE_CLK 134 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 135 +#define GCC_UFS_PHY_PHY_AUX_CLK 136 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 137 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 138 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 139 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 140 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 141 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 142 +#define GCC_USB30_PRIM_MASTER_CLK 143 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 144 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 145 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 146 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 147 +#define GCC_USB30_PRIM_SLEEP_CLK 148 +#define GCC_USB3_PRIM_CLKREF_CLK 149 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 150 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 151 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 152 +#define GCC_VCODEC0_AXI_CLK 153 +#define GCC_VENUS_AHB_CLK 154 +#define GCC_VENUS_CTL_AXI_CLK 155 +#define GCC_VIDEO_AHB_CLK 156 +#define GCC_VIDEO_AXI0_CLK 157 +#define GCC_VIDEO_THROTTLE_CORE_CLK 158 +#define GCC_VIDEO_VCODEC0_SYS_CLK 159 +#define GCC_VIDEO_VENUS_CLK_SRC 160 +#define GCC_VIDEO_VENUS_CTL_CLK 161 +#define GCC_VIDEO_XO_CLK 162 + +/* GCC resets */ +#define GCC_QUSB2PHY_PRIM_BCR 0 +#define GCC_QUSB2PHY_SEC_BCR 1 +#define GCC_SDCC1_BCR 2 +#define GCC_SDCC2_BCR 3 +#define GCC_UFS_PHY_BCR 4 +#define GCC_USB30_PRIM_BCR 5 +#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 6 +#define GCC_USB3_PHY_PRIM_SP0_BCR 7 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8 +#define GCC_VCODEC0_BCR 9 +#define GCC_VENUS_BCR 10 +#define GCC_VIDEO_INTERFACE_BCR 11 + +#endif diff --git a/include/dt-bindings/clock/qcom,gpucc-khaje.h b/include/dt-bindings/clock/qcom,gpucc-khaje.h new file mode 100644 index 000000000000..e6385c43cb84 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-khaje.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_KHAJE_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_KHAJE_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL0_OUT_MAIN 1 +#define GPU_CC_PLL1 2 +#define GPU_CC_AHB_CLK 3 +#define GPU_CC_CRC_AHB_CLK 4 +#define GPU_CC_CX_GFX3D_CLK 5 +#define GPU_CC_CX_GMU_CLK 6 +#define GPU_CC_CX_SNOC_DVM_CLK 7 +#define GPU_CC_CXO_AON_CLK 8 +#define GPU_CC_CXO_CLK 9 +#define GPU_CC_GMU_CLK_SRC 10 +#define GPU_CC_GX_CXO_CLK 11 +#define GPU_CC_GX_GFX3D_CLK 12 +#define GPU_CC_GX_GFX3D_CLK_SRC 13 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14 +#define GPU_CC_SLEEP_CLK 15 + +#endif From e4fb980c0f6a7fec690574db83ad1996bc6004ed Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Fri, 6 Mar 2020 19:49:10 +0530 Subject: [PATCH 28/55] usb_bam: Set default BAM type as DWC3 if not specified 'Commit 8db85a3d77d5 ("platform: msm: Add USB BAM support to ChipIdea/RMNET")' mandates BAM type to be present in the dtsi file. Absence of this field leads to BAM probe failure. Fix this by setting the default BAM type to DWC3 if the field is not available. Change-Id: I3970855e1d3682901b7557512c68bad1f77260a1 Signed-off-by: Udipto Goswami --- drivers/platform/msm/usb_bam.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/platform/msm/usb_bam.c b/drivers/platform/msm/usb_bam.c index 157385855c43..a304574418d4 100644 --- a/drivers/platform/msm/usb_bam.c +++ b/drivers/platform/msm/usb_bam.c @@ -2876,7 +2876,7 @@ static struct msm_usb_bam_data *usb_bam_dt_to_data( struct device_node *node = pdev->dev.of_node; int rc = 0; u8 i = 0; - u32 bam; + u32 bam = DWC3_CTRL; u32 addr = 0; u32 threshold, max_connections = 0; static struct usb_bam_pipe_connect *usb_bam_connections; @@ -2886,12 +2886,9 @@ static struct msm_usb_bam_data *usb_bam_dt_to_data( if (!usb_bam_data) return NULL; - rc = of_property_read_u32(node, "qcom,bam-type", &bam); - if (rc) { - log_event_err("%s: bam type is missing in device tree\n", - __func__); - return NULL; - } + /* override bam-type if specified, default is dwc3 */ + of_property_read_u32(node, "qcom,bam-type", &bam); + if (bam >= MAX_BAMS) { log_event_err("%s: Invalid bam type %d in device tree\n", __func__, bam); From 768bdc42c0ba5be788fbea9b59790b50937b008c Mon Sep 17 00:00:00 2001 From: Chaitanya Pratapa Date: Sun, 22 Mar 2020 23:56:47 -0700 Subject: [PATCH 29/55] msm: ipa: Fix considering prefetch buf size when mapping IPA HW tries to prefetch 128Bytes of additional memory when dealing with filter/routing tables. This can result in overflowing of memory if we map only the required size. Make changes to consider prefetch memory when allocating routing/filter tables. Change-Id: Id72e4df285a4683dddebb18d98bb9c4dd9667eeb Signed-off-by: Ashok Vuyyuru Signed-off-by: Chaitanya Pratapa --- drivers/platform/msm/ipa/ipa_v3/ipa_flt.c | 5 ++++- drivers/platform/msm/ipa/ipa_v3/ipa_rt.c | 5 ++++- .../platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.c | 14 +++++++++++++- .../platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.h | 5 ++++- .../msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h | 3 ++- 5 files changed, 27 insertions(+), 5 deletions(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c b/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c index d425bbb963e7..48ed8d5cd5ba 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #include "ipa_i.h" @@ -222,6 +222,9 @@ static int ipa_translate_flt_tbl_to_hw_fmt(enum ipa_ip_type ip, /* only body (no header) */ tbl_mem.size = tbl->sz[rlt] - ipahal_get_hw_tbl_hdr_width(); + /* Add prefetech buf size. */ + tbl_mem.size += + ipahal_get_hw_prefetch_buf_size(); if (ipahal_fltrt_allocate_hw_sys_tbl(&tbl_mem)) { IPAERR("fail to alloc sys tbl of size %d\n", tbl_mem.size); diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c b/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c index 19d610e4b89c..12633b7c5498 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #include @@ -169,6 +169,9 @@ static int ipa_translate_rt_tbl_to_hw_fmt(enum ipa_ip_type ip, /* only body (no header) */ tbl_mem.size = tbl->sz[rlt] - ipahal_get_hw_tbl_hdr_width(); + /* Add prefetech buf size. */ + tbl_mem.size += + ipahal_get_hw_prefetch_buf_size(); if (ipahal_fltrt_allocate_hw_sys_tbl(&tbl_mem)) { IPAERR_RL("fail to alloc sys tbl of size %d\n", tbl_mem.size); diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.c b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.c index 9e2ec20c6193..f85c80403b85 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #include @@ -44,6 +44,7 @@ * @flt_parse_hw_rule: Parse flt rule read from H/W * @eq_bitfield: Array of the bit fields of the support equations. * 0xFF means the equation is not supported + * @prefetech_buf_size: Prefetch buf size; */ struct ipahal_fltrt_obj { bool support_hash; @@ -73,6 +74,7 @@ struct ipahal_fltrt_obj { int (*rt_parse_hw_rule)(u8 *addr, struct ipahal_rt_rule_entry *rule); int (*flt_parse_hw_rule)(u8 *addr, struct ipahal_flt_rule_entry *rule); u8 eq_bitfield[IPA_EQ_MAX]; + u32 prefetech_buf_size; }; @@ -654,6 +656,7 @@ static struct ipahal_fltrt_obj ipahal_fltrt_objs[IPA_HW_MAX] = { [IPA_IS_FRAG] = 15, [IPA_IS_PURE_ACK] = 0xFF, }, + IPA3_0_HW_RULE_PREFETCH_BUF_SIZE, }, /* IPAv4 */ @@ -699,6 +702,7 @@ static struct ipahal_fltrt_obj ipahal_fltrt_objs[IPA_HW_MAX] = { [IPA_IS_FRAG] = 15, [IPA_IS_PURE_ACK] = 0xFF, }, + IPA3_0_HW_RULE_PREFETCH_BUF_SIZE, }, /* IPAv4.2 */ @@ -744,6 +748,7 @@ static struct ipahal_fltrt_obj ipahal_fltrt_objs[IPA_HW_MAX] = { [IPA_IS_FRAG] = 15, [IPA_IS_PURE_ACK] = 0xFF, }, + IPA3_0_HW_RULE_PREFETCH_BUF_SIZE, }, /* IPAv4.5 */ @@ -789,6 +794,7 @@ static struct ipahal_fltrt_obj ipahal_fltrt_objs[IPA_HW_MAX] = { [IPA_IS_FRAG] = 15, [IPA_IS_PURE_ACK] = 0, }, + IPA3_0_HW_RULE_PREFETCH_BUF_SIZE, }, }; @@ -3593,6 +3599,12 @@ u32 ipahal_get_lcl_tbl_addr_alignment(void) return ipahal_fltrt_objs[ipahal_ctx->hw_type].lcladdr_alignment; } +/* Get the H/W (flt/rt) prefetch buf size */ +u32 ipahal_get_hw_prefetch_buf_size(void) +{ + return ipahal_fltrt_objs[ipahal_ctx->hw_type].prefetech_buf_size; +} + /* * Rule priority is used to distinguish rules order * at the integrated table consisting from hashable and diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.h b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.h index f18700d0c78c..ad2394e52856 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.h +++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */ #ifndef _IPAHAL_FLTRT_H_ @@ -140,6 +140,9 @@ u32 ipahal_get_hw_tbl_hdr_width(void); */ u32 ipahal_get_lcl_tbl_addr_alignment(void); +/* Get the H/W (flt/rt) prefetch buf size */ +u32 ipahal_get_hw_prefetch_buf_size(void); + /* * Rule priority is used to distinguish rules order * at the integrated table consisting from hashable and diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h index c8a6a3023864..283786236a07 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h +++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #ifndef _IPAHAL_FLTRT_I_H_ @@ -44,6 +44,7 @@ enum ipa_fltrt_equations { #define IPA3_0_HW_TBL_ADDR_MASK (127) #define IPA3_0_HW_RULE_BUF_SIZE (256) #define IPA3_0_HW_RULE_START_ALIGNMENT (7) +#define IPA3_0_HW_RULE_PREFETCH_BUF_SIZE (128) /* From c7795651a7f5130c36e4dab1fa3583f73358959c Mon Sep 17 00:00:00 2001 From: Vandana Jain Date: Wed, 19 May 2021 18:38:23 +0530 Subject: [PATCH 30/55] msm: camera: Add reset logic for snps phy Adding polling logic to check the phy irq status before releasing force mode. Change-Id: Ie2886807c0be95150eb9db32bfce914b70a15433 Signed-off-by: Vandana Jain --- .../csiphy/include/msm_csiphy_10_0_0_hwreg.h | 5 +- .../msm/camera_v2/sensor/csiphy/msm_csiphy.c | 146 +++++++++++++----- .../msm/camera_v2/sensor/csiphy/msm_csiphy.h | 2 - 3 files changed, 109 insertions(+), 44 deletions(-) diff --git a/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_10_0_0_hwreg.h b/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_10_0_0_hwreg.h index 5c7da45260a6..f61c9ac52bfb 100644 --- a/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_10_0_0_hwreg.h +++ b/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_10_0_0_hwreg.h @@ -29,6 +29,9 @@ #define mask_enable_clk_B 0x2 #define mask_ctrl_1_A 0x5 #define mask_ctrl_1_B 0xA +#define mask_reset_A 0x1 +#define mask_reset_B 0x7 +#define mask_shutdown_A 0x3 #define mask_hs_freq_range 0x7F #define mask_osc_freq_2 0xFF #define mask_osc_freq_3 0xF00 @@ -57,8 +60,6 @@ static struct csiphy_reg_snps_parms_t csiphy_v10_0_0_snps = { {0x58C, 0xFF}, /* mipi_csiphy_irq_mask_ctrl_lane_0 */ {0x5C8, 0xFF}, /* mipi_csiphy_irq_mask_ctrl_lane_clk_0 */ {0x20, 0x0}, /* mipi_csiphy_rx_sys_7_00 */ - {0x28, 0x43}, /* mipi_csiphy_rx_sys_9_00 */ - {0x380, 0x0}, /* mipi_csiphy_rx_startup_ovr_0_00 */ {0x384, 0x0}, /* mipi_csiphy_rx_startup_ovr_1_00 */ {0x388, 0xCC}, /* mipi_csiphy_rx_startup_ovr_2_00 */ {0x38C, 0x1}, /* mipi_csiphy_rx_startup_ovr_3_00 */ diff --git a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c index 033a0e6bb31c..2f86108d3ce8 100644 --- a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c +++ b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c @@ -259,10 +259,13 @@ static int msm_csiphy_snps_2_lane_config( csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg .mipi_csiphy_rx_sys_7_00.addr + offset); - msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg - .mipi_csiphy_rx_sys_9_00.data, + value = msm_camera_io_r(csiphybase + + csiphy_dev->ctrl_reg->csiphy_snps_reg + .mipi_csiphy_rx_clk_lane_6_00.addr + offset); + value |= SET_THE_BIT(7); + msm_camera_io_w(value, csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg - .mipi_csiphy_rx_sys_9_00.addr + offset); + .mipi_csiphy_rx_clk_lane_6_00.addr + offset); msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg .mipi_csiphy_rx_startup_ovr_4_00.data, @@ -329,7 +332,7 @@ static int msm_csiphy_snps_lane_config( uint16_t lane_mask = 0; void __iomem *csiphybase; enum snps_csiphy_mode mode = INVALID_MODE; - uint32_t value, num_tries, num_lanes, offset; + uint32_t value, num_tries, num_lanes, offset = SNPS_INTERPHY_OFFSET; uint32_t clk_mux_reg = 0; csiphybase = csiphy_dev->base; @@ -507,17 +510,6 @@ static int msm_csiphy_snps_lane_config( .mipi_csiphy_rx_clk_lane_7_00.addr + SNPS_INTERPHY_OFFSET); - value = msm_camera_io_r(csiphybase + - csiphy_dev->ctrl_reg->csiphy_snps_reg - .mipi_csiphy_rx_startup_ovr_0_00.addr + - SNPS_INTERPHY_OFFSET); - value |= SET_THE_BIT(0); - value |= SET_THE_BIT(1); - msm_camera_io_w(value, - csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg - .mipi_csiphy_rx_startup_ovr_0_00.addr + - SNPS_INTERPHY_OFFSET); - value = msm_camera_io_r(csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg .mipi_csiphy_rx_startup_ovr_1_00.addr + @@ -533,6 +525,7 @@ static int msm_csiphy_snps_lane_config( csiphy_dev->ctrl_reg->csiphy_snps_reg .mipi_csiphy_rx_clk_lane_6_00.addr); value |= SET_THE_BIT(2); + value &= ~(SET_THE_BIT(7)); msm_camera_io_w(value, csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg .mipi_csiphy_rx_clk_lane_6_00.addr); @@ -542,7 +535,7 @@ static int msm_csiphy_snps_lane_config( .mipi_csiphy_rx_clk_lane_6_00.addr + SNPS_INTERPHY_OFFSET); value |= SET_THE_BIT(3); - value |= SET_THE_BIT(7); + value &= ~(SET_THE_BIT(7)); value &= ~(SET_THE_BIT(2)); msm_camera_io_w(value, csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg @@ -604,36 +597,109 @@ static int msm_csiphy_snps_lane_config( csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg .mipi_csiphy_enable_clk.addr); - value = 0x0; - if (mode == AGGREGATE_MODE || mode == TWO_LANE_PHY_A) - value |= mask_ctrl_1_A; - if (mode == AGGREGATE_MODE || mode == TWO_LANE_PHY_B) - value |= mask_ctrl_1_B; - msm_camera_io_w(value, + if (mode == TWO_LANE_PHY_A) { + msm_camera_io_w(mask_reset_A, csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg .mipi_csiphy_ctrl_1.addr); - if (mode == AGGREGATE_MODE || mode == TWO_LANE_PHY_A) - offset = 0x0; - else - offset = SNPS_INTERPHY_OFFSET; + msm_camera_io_w(mask_ctrl_1_A, + csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg + .mipi_csiphy_ctrl_1.addr); - value = 0x0; - num_tries = 0; + value = 0x0; + num_tries = 0; + + do { + num_tries++; + value = msm_camera_io_r(csiphybase + + csiphy_dev->ctrl_reg->csiphy_snps_reg + .mipi_csiphy_rx_startup_obs_2_00.addr); + if ((value | SET_THE_BIT(4)) == value) + break; + usleep_range(100, 150); + } while (num_tries < 6); + if ((value | SET_THE_BIT(4)) != value) { + pr_err("%s: SNPS phy config failed\n", __func__); + return -EINVAL; + } + } - do { - num_tries++; - value = msm_camera_io_r(csiphybase + - csiphy_dev->ctrl_reg->csiphy_snps_reg - .mipi_csiphy_rx_startup_obs_2_00.addr + offset); - if ((value | SET_THE_BIT(4)) == value) - break; - usleep_range(100, 150); - } while (num_tries < 6); + if (mode == TWO_LANE_PHY_B) { + msm_camera_io_w(mask_reset_B, + csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg + .mipi_csiphy_ctrl_1.addr); - if ((value | SET_THE_BIT(4)) != value) { - pr_err("%s: SNPS phy config failed\n", __func__); - return -EINVAL; + msm_camera_io_w(mask_ctrl_1_A|mask_ctrl_1_B, + csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg + .mipi_csiphy_ctrl_1.addr); + + value = 0x0; + num_tries = 0; + + do { + num_tries++; + value = msm_camera_io_r(csiphybase + + csiphy_dev->ctrl_reg->csiphy_snps_reg + .mipi_csiphy_rx_startup_obs_2_00.addr + offset); + if ((value | SET_THE_BIT(4)) == value) + break; + usleep_range(100, 150); + } while (num_tries < 6); + + if ((value | SET_THE_BIT(4)) != value) { + pr_err("%s: SNPS phy config failed\n", __func__); + return -EINVAL; + } + } + + if (mode == AGGREGATE_MODE) { + msm_camera_io_w(mask_shutdown_A, + csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg + .mipi_csiphy_ctrl_1.addr); + + msm_camera_io_w(mask_reset_B, + csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg + .mipi_csiphy_ctrl_1.addr); + + value = 0x0; + num_tries = 0; + + do { + num_tries++; + value = msm_camera_io_r(csiphybase + + csiphy_dev->ctrl_reg->csiphy_snps_reg + .mipi_csiphy_rx_startup_obs_2_00.addr); + if ((value | SET_THE_BIT(4)) == value) + break; + usleep_range(100, 150); + } while (num_tries < 6); + + if ((value | SET_THE_BIT(4)) != value) { + pr_err("%s: SNPS phy config failed\n", __func__); + return -EINVAL; + } + + msm_camera_io_w(mask_ctrl_1_A|mask_ctrl_1_B, + csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg + .mipi_csiphy_ctrl_1.addr); + + value = 0x0; + num_tries = 0; + + do { + num_tries++; + value = msm_camera_io_r(csiphybase + + csiphy_dev->ctrl_reg->csiphy_snps_reg + .mipi_csiphy_rx_startup_obs_2_00.addr + offset); + if ((value | SET_THE_BIT(4)) == value) + break; + usleep_range(100, 150); + } while (num_tries < 6); + + if ((value | SET_THE_BIT(4)) != value) { + pr_err("%s: SNPS phy config failed\n", __func__); + return -EINVAL; + } } msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg diff --git a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h index 498a08b8e48b..ff69f04f862b 100644 --- a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h +++ b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h @@ -84,8 +84,6 @@ struct csiphy_reg_snps_parms_t { struct csiphy_reg_t mipi_csiphy_irq_mask_ctrl_lane_0; struct csiphy_reg_t mipi_csiphy_irq_mask_ctrl_lane_clk_0; struct csiphy_reg_t mipi_csiphy_rx_sys_7_00; - struct csiphy_reg_t mipi_csiphy_rx_sys_9_00; - struct csiphy_reg_t mipi_csiphy_rx_startup_ovr_0_00; struct csiphy_reg_t mipi_csiphy_rx_startup_ovr_1_00; struct csiphy_reg_t mipi_csiphy_rx_startup_ovr_2_00; struct csiphy_reg_t mipi_csiphy_rx_startup_ovr_3_00; From 8d12b9c8c7ef06542ffd03f02135a549ebf28cb2 Mon Sep 17 00:00:00 2001 From: Raghavendra Ambadas Date: Tue, 20 Apr 2021 16:52:10 +0530 Subject: [PATCH 31/55] clk: qcom: mdss: fix blank / un-blank issue for DSI 12nm pll During blank, cache the pll mux registers for pixel_clk_src clock. These cached values need to be programmed during unblank where the clock framework does not call the mux func to re-configure the mux values. For splash disabled case, change the clk width value to select correct clock divider for pxl clk. Change-Id: I1f6258a11d17cc85d43ea74bf50c108e2943984a Signed-off-by: Raghavendra Ambadas --- .../clk/qcom/mdss/mdss-dsi-pll-12nm-util.c | 34 ++++++++++++++++--- drivers/clk/qcom/mdss/mdss-dsi-pll-12nm.c | 16 ++++----- 2 files changed, 36 insertions(+), 14 deletions(-) diff --git a/drivers/clk/qcom/mdss/mdss-dsi-pll-12nm-util.c b/drivers/clk/qcom/mdss/mdss-dsi-pll-12nm-util.c index 876e32681fd4..754b70315f0e 100644 --- a/drivers/clk/qcom/mdss/mdss-dsi-pll-12nm-util.c +++ b/drivers/clk/qcom/mdss/mdss-dsi-pll-12nm-util.c @@ -35,9 +35,10 @@ int pixel_div_set_div(void *context, unsigned int reg, } /* Programming during vco_prepare. Keep this value */ - data = ((div - 1) & 0x7f); + data = (div & 0x7f); MDSS_PLL_REG_W(pll_base, DSIPHY_SSC9, data); pdb->param.pixel_divhf = data; + pll->cached_postdiv3 = data; mdss_pll_resource_enable(pll, false); pr_debug("ndx=%d div=%d divhf=%d\n", @@ -63,7 +64,7 @@ int pixel_div_get_div(void *context, unsigned int reg, } val = (MDSS_PLL_REG_R(pll->pll_base, DSIPHY_SSC9) & 0x7F); - *div = val + 1; + *div = val; pr_debug("pixel_div = %d\n", (*div)); mdss_pll_resource_enable(pll, false); @@ -94,11 +95,14 @@ int set_post_div_mux_sel(void *context, unsigned int reg, data = ((vco_cntrl & 0x3f) | BIT(6)); MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_VCO_CTRL, data); pr_debug("%s: vco_cntrl 0x%x\n", __func__, vco_cntrl); + pll->cached_cfg0 = data; + wmb(); /* make sure register committed before preparing the clocks */ data = ((cpbias_cntrl & 0x1) << 6) | BIT(4); MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_CHAR_PUMP_BIAS_CTRL, data); pr_debug("%s: cpbias_cntrl 0x%x\n", __func__, cpbias_cntrl); + pll->cached_cfg1 = data; pr_debug("ndx=%d post_div_mux_sel=%d p_div=%d\n", pll->index, sel, (u32) BIT(sel)); @@ -168,6 +172,7 @@ int set_gp_mux_sel(void *context, unsigned int reg, /* Programming during vco_prepare. Keep this value */ data = ((sel & 0x7) << 5) | 0x5; MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_CTRL, data); + pll->cached_postdiv1 = data; pr_debug("ndx=%d gp_div_mux_sel=%d gp_cntrl=%d\n", pll->index, sel, (u32) BIT(sel)); @@ -910,10 +915,9 @@ unsigned long vco_12nm_recalc_rate(struct clk_hw *hw, } if (pll->vco_current_rate != 0) { - rate = pll_vco_get_rate_12nm(hw); pr_debug("%s:returning vco rate = %lld\n", __func__, pll->vco_current_rate); - return rate; + return pll->vco_current_rate; } rc = mdss_pll_resource_enable(pll, true); @@ -971,6 +975,22 @@ int pll_vco_prepare_12nm(struct clk_hw *hw) } } + if (!pll->handoff_resources) { + pr_debug("%s ndx = %d cache PLL regs\n", __func__, pll->index); + MDSS_PLL_REG_W(pll->pll_base, + DSIPHY_PLL_VCO_CTRL, pll->cached_cfg0); + udelay(1); + MDSS_PLL_REG_W(pll->pll_base, + DSIPHY_PLL_CHAR_PUMP_BIAS_CTRL, pll->cached_cfg1); + udelay(1); + MDSS_PLL_REG_W(pll->pll_base, + DSIPHY_PLL_CTRL, pll->cached_postdiv1); + udelay(1); + MDSS_PLL_REG_W(pll->pll_base, + DSIPHY_SSC9, pll->cached_postdiv3); + udelay(5); /* h/w recommended delay */ + } + /* * For cases where DSI PHY is already enabled like: * 1.) LP-11 during static screen @@ -1009,6 +1029,12 @@ void pll_vco_unprepare_12nm(struct clk_hw *hw) } pll->vco_cached_rate = clk_hw_get_rate(hw); + + pll->cached_cfg0 = MDSS_PLL_REG_R(pll->pll_base, DSIPHY_PLL_VCO_CTRL); + pll->cached_cfg1 = MDSS_PLL_REG_R(pll->pll_base, + DSIPHY_PLL_CHAR_PUMP_BIAS_CTRL); + pll->cached_postdiv1 = MDSS_PLL_REG_R(pll->pll_base, DSIPHY_PLL_CTRL); + pll->cached_postdiv3 = MDSS_PLL_REG_R(pll->pll_base, DSIPHY_SSC9); dsi_pll_disable(hw); } diff --git a/drivers/clk/qcom/mdss/mdss-dsi-pll-12nm.c b/drivers/clk/qcom/mdss/mdss-dsi-pll-12nm.c index a2ff5f6371f3..5b70d74ca3cf 100644 --- a/drivers/clk/qcom/mdss/mdss-dsi-pll-12nm.c +++ b/drivers/clk/qcom/mdss/mdss-dsi-pll-12nm.c @@ -504,15 +504,14 @@ static struct clk_regmap_mux dsi1pll_gp_div_mux = { static struct clk_regmap_div dsi0pll_pclk_src = { .reg = DSIPHY_SSC9, .shift = 0, - .width = 6, + .width = 3, .clkr = { .hw.init = &(struct clk_init_data){ .name = "dsi0_phy_pll_out_dsiclk", .parent_names = (const char *[]){ "dsi0pll_gp_div_mux"}, .num_parents = 1, - .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT | - CLK_SET_RATE_NO_REPARENT), + .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT), .ops = &clk_regmap_div_ops, }, }, @@ -521,15 +520,14 @@ static struct clk_regmap_div dsi0pll_pclk_src = { static struct clk_regmap_div dsi1pll_pclk_src = { .reg = DSIPHY_SSC9, .shift = 0, - .width = 6, + .width = 3, .clkr = { .hw.init = &(struct clk_init_data){ .name = "dsi1_phy_pll_out_dsiclk", .parent_names = (const char *[]){ "dsi1pll_gp_div_mux"}, .num_parents = 1, - .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT | - CLK_SET_RATE_NO_REPARENT), + .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT), .ops = &clk_regmap_div_ops, }, }, @@ -542,8 +540,7 @@ static struct clk_fixed_factor dsi0pll_byte_clk_src = { .name = "dsi0_phy_pll_out_byteclk", .parent_names = (const char *[]){"dsi0pll_post_div_mux"}, .num_parents = 1, - .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT | - CLK_SET_RATE_NO_REPARENT), + .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT), .ops = &clk_fixed_factor_ops, }, }; @@ -555,8 +552,7 @@ static struct clk_fixed_factor dsi1pll_byte_clk_src = { .name = "dsi1_phy_pll_out_byteclk", .parent_names = (const char *[]){"dsi1pll_post_div_mux"}, .num_parents = 1, - .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT | - CLK_SET_RATE_NO_REPARENT), + .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT), .ops = &clk_fixed_factor_ops, }, }; From e8f23e51be333753e131bf59ee0f65c88de9d788 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Tue, 12 Jan 2021 15:37:29 -0800 Subject: [PATCH 32/55] power: smb1398: Add support for SMB1394 Add support for SMB1394, which is a a variant of SMB1398. Change-Id: I0e508079174ae16e0aa8c5f242be3686126319ea Signed-off-by: Guru Das Srinagesh --- drivers/power/supply/qcom/smb1398-charger.c | 119 ++++++++++++++++++-- 1 file changed, 107 insertions(+), 12 deletions(-) diff --git a/drivers/power/supply/qcom/smb1398-charger.c b/drivers/power/supply/qcom/smb1398-charger.c index c600ecad1411..aa78a2978b8b 100644 --- a/drivers/power/supply/qcom/smb1398-charger.c +++ b/drivers/power/supply/qcom/smb1398-charger.c @@ -128,6 +128,7 @@ #define SMB_EN_POS_TRIGGER BIT(0) #define PERPH0_DIV2_SLAVE 0x2652 +#define CFG_EN_SLAVE_OWN_FREQ BIT(1) #define CFG_DIV2_SYNC_CLK_PHASE_90 BIT(0) #define DIV2_LCM_CFG_REG 0x2653 @@ -147,6 +148,10 @@ #define WIN_OV_400_MV 2 #define WIN_OV_500_MV 3 +#define PERPH0_OVLO_REF_REG 0x265B +#define SMB1394_INPUT_OVLO_CONF_MASK GENMASK(2, 0) +#define SMB1394_INPUT_OVLO_13P04V 0x5 + #define DIV2_MODE_CFG_REG 0x265C #define LCM_EXIT_CTRL_REG 0x265D @@ -178,11 +183,14 @@ #define EN_WIN_UV_BIT BIT(7) #define PERPH0_SOVP_CFG0_REG 0x2680 +#define CFG_OVP_VSNS_THRESHOLD BIT(4) #define CFG_OVP_IGNORE_UVLO BIT(5) #define PERPH0_SSUPPLY_CFG0_REG 0x2682 #define EN_HV_OV_OPTION2_BIT BIT(7) #define EN_MV_OV_OPTION2_BIT BIT(5) +#define CFG_CMP_VOUT_VS_4V_REF_MASK GENMASK(2, 1) +#define CMP_VOUT_VS_4V_REF_3P2V 0x3 /* Value for SMB1394 only */ #define SSUPLY_TEMP_CTRL_REG 0x2683 #define SEL_OUT_TEMP_MAX_MASK GENMASK(7, 5) @@ -236,6 +244,11 @@ #define DIV2_CP_MASTER 0 #define DIV2_CP_SLAVE 1 #define COMBO_PRE_REGULATOR 2 +#define SMB1394_DIV2_CP_PRY 3 +#define SMB1394_DIV2_CP_SECY 4 + +#define IS_SMB1394(role) \ + (role == SMB1394_DIV2_CP_PRY || role == SMB1394_DIV2_CP_SECY) enum isns_mode { ISNS_MODE_OFF = 0, @@ -975,6 +988,19 @@ static int smb1398_div2_cp_get_min_icl(struct smb1398_chip *chip) return chip->div2_cp_min_ilim_ua; } +static char *div2_cp_get_model_name(struct smb1398_chip *chip) +{ + if (IS_SMB1394(chip->div2_cp_role)) + return "SMB1394"; + + if (chip->pmic_rev_id->rev4 > 2) + return "SMB1398_V3"; + else if (chip->pmic_rev_id->rev4 == 2) + return "SMB1398_V2"; + else + return "SMB1398_V1"; +} + static int div2_cp_master_get_prop(struct power_supply *psy, enum power_supply_property prop, union power_supply_propval *val) @@ -1065,8 +1091,7 @@ static int div2_cp_master_get_prop(struct power_supply *psy, val->intval = chip->pmic_rev_id->rev4; break; case POWER_SUPPLY_PROP_MODEL_NAME: - val->strval = (chip->pmic_rev_id->rev4 > 1) ? "SMB1398_V2" : - "SMB1398_V1"; + val->strval = div2_cp_get_model_name(chip); break; case POWER_SUPPLY_PROP_PARALLEL_MODE: val->intval = chip->pl_input_mode; @@ -1926,7 +1951,7 @@ static void smb1398_taper_work(struct work_struct *work) chip->taper_work_running = false; } -static int smb1398_update_ovp(struct smb1398_chip *chip) +static int _smb1398_update_ovp(struct smb1398_chip *chip) { int rc = 0; u8 reg = 0; @@ -1960,7 +1985,38 @@ static int smb1398_update_ovp(struct smb1398_chip *chip) return rc; } - return 0; + return rc; +} + +static int _smb1394_update_ovp(struct smb1398_chip *chip) +{ + int rc = 0; + + rc = smb1398_masked_write(chip, PERPH0_SOVP_CFG0_REG, + CFG_OVP_VSNS_THRESHOLD, CFG_OVP_VSNS_THRESHOLD); + if (rc < 0) { + dev_err(chip->dev, "Couldn't set PERPH0_SOVP_CFG0_REG rc=%d\n", + rc); + return rc; + } + + rc = smb1398_masked_write(chip, PERPH0_OVLO_REF_REG, + SMB1394_INPUT_OVLO_CONF_MASK, + SMB1394_INPUT_OVLO_13P04V); + if (rc < 0) { + dev_err(chip->dev, "Couldn't set PERPH0_OVLO_REF rc=%d\n", rc); + return rc; + } + + return rc; +} + +static int smb1398_update_ovp(struct smb1398_chip *chip) +{ + if (IS_SMB1394(chip->div2_cp_role)) + return _smb1394_update_ovp(chip); + + return _smb1398_update_ovp(chip); } static int smb1398_div2_cp_hw_init(struct smb1398_chip *chip) @@ -2046,6 +2102,17 @@ static int smb1398_div2_cp_hw_init(struct smb1398_chip *chip) return rc; } + if (IS_SMB1394(chip->div2_cp_role)) { + rc = smb1398_masked_write(chip, PERPH0_SSUPPLY_CFG0_REG, + CFG_CMP_VOUT_VS_4V_REF_MASK, + CMP_VOUT_VS_4V_REF_3P2V); + if (rc < 0) { + dev_err(chip->dev, "Couldn't set PERPH0_SSUPPLY_CFG0_REG, rc=%d\n", + rc); + return rc; + } + } + return rc; } @@ -2374,13 +2441,32 @@ static int smb1398_div2_cp_slave_probe(struct smb1398_chip *chip) return rc; } - /* Enable slave clock on its own */ - rc = smb1398_masked_write(chip, NOLOCK_SPARE_REG, - EN_SLAVE_OWN_FREQ_BIT, EN_SLAVE_OWN_FREQ_BIT); - if (rc < 0) { - dev_err(chip->dev, "Couldn't enable slave clock, rc=%d\n", - rc); - return rc; + if (IS_SMB1394(chip->div2_cp_role)) { + rc = smb1398_masked_write(chip, PERPH0_SSUPPLY_CFG0_REG, + CFG_CMP_VOUT_VS_4V_REF_MASK, + CMP_VOUT_VS_4V_REF_3P2V); + if (rc < 0) { + dev_err(chip->dev, "Couldn't set PERPH0_SSUPPLY_CFG0_REG, rc=%d\n", + rc); + return rc; + } + + rc = smb1398_masked_write(chip, PERPH0_DIV2_SLAVE, + CFG_EN_SLAVE_OWN_FREQ, CFG_EN_SLAVE_OWN_FREQ); + if (rc < 0) { + dev_err(chip->dev, "Couldn't set PERPH0_DIV2_SLAVE, rc=%d\n", + rc); + return rc; + } + } else { + /* Enable slave clock on its own */ + rc = smb1398_masked_write(chip, NOLOCK_SPARE_REG, + EN_SLAVE_OWN_FREQ_BIT, EN_SLAVE_OWN_FREQ_BIT); + if (rc < 0) { + dev_err(chip->dev, "Couldn't enable slave clock, rc=%d\n", + rc); + return rc; + } } rc = smb1398_init_div2_cp_slave_psy(chip); @@ -2626,8 +2712,10 @@ static int smb1398_probe(struct platform_device *pdev) chip->div2_cp_role = (int)of_device_get_match_data(chip->dev); switch (chip->div2_cp_role) { case DIV2_CP_MASTER: + case SMB1394_DIV2_CP_PRY: rc = smb1398_div2_cp_master_probe(chip); break; + case SMB1394_DIV2_CP_SECY: case DIV2_CP_SLAVE: rc = smb1398_div2_cp_slave_probe(chip); break; @@ -2658,7 +2746,8 @@ static int smb1398_remove(struct platform_device *pdev) { struct smb1398_chip *chip = platform_get_drvdata(pdev); - if (chip->div2_cp_role == DIV2_CP_MASTER) { + if (chip->div2_cp_role == DIV2_CP_MASTER || + chip->div2_cp_role == SMB1394_DIV2_CP_PRY) { vote(chip->awake_votable, SHUTDOWN_VOTER, false, 0); vote(chip->div2_cp_disable_votable, SHUTDOWN_VOTER, true, 0); vote(chip->div2_cp_ilim_votable, SHUTDOWN_VOTER, true, 0); @@ -2725,6 +2814,12 @@ static const struct of_device_id match_table[] = { { .compatible = "qcom,smb1398-pre-regulator", .data = (void *)COMBO_PRE_REGULATOR, }, + { .compatible = "qcom,smb1394-div2-cp-primary", + .data = (void *)SMB1394_DIV2_CP_PRY, + }, + { .compatible = "qcom,smb1394-div2-cp-secondary", + .data = (void *)SMB1394_DIV2_CP_SECY, + }, { }, }; From 442d31ec7ab461c2438777f7774c3b1456130980 Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Tue, 18 Aug 2020 18:45:49 +0530 Subject: [PATCH 33/55] USB: dwc3: gadget: Increase TX fifo size for isochronous endpoint Increase TX Fifo size for isochronous endpoint in case maxburst is greater than 6 for better performance. Change-Id: I0da45f5a9e2f77947a67776b3e41fd2bb920fca2 Signed-off-by: Vijayavardhan Vennapusa --- drivers/usb/dwc3/gadget.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 8955fc90c9e2..6806669351b3 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -230,6 +230,10 @@ int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc, struct dwc3_ep *dep) && dwc3_is_usb31(dwc)) mult = 6; + if ((dep->endpoint.maxburst > 6) && + usb_endpoint_xfer_isoc(dep->endpoint.desc)) + mult = 6; + tmp = ((max_packet + mdwidth) * mult) + mdwidth; fifo_size = DIV_ROUND_UP(tmp, mdwidth); dep->fifo_depth = fifo_size; From 42a7d6b2e6136e342c261a3adff188e940d4aca1 Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Thu, 1 Apr 2021 14:50:38 +0530 Subject: [PATCH 34/55] USB: uvc: Fix video quality issues for streaming video over USB Increase number of UVC requests from 16 to 64 to avoid video quality issues for video streaming over USB. Change-Id: I8ebdf1bdc3d3d30da5ba3e768a11268200f66d28 Signed-off-by: Vijayavardhan Vennapusa --- drivers/usb/gadget/function/uvc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/gadget/function/uvc.h b/drivers/usb/gadget/function/uvc.h index f63180f0effc..7180c92ae14c 100644 --- a/drivers/usb/gadget/function/uvc.h +++ b/drivers/usb/gadget/function/uvc.h @@ -64,7 +64,7 @@ extern unsigned int uvc_gadget_trace_param; * Driver specific constants */ -#define UVC_NUM_REQUESTS 16 +#define UVC_NUM_REQUESTS 64 #define UVC_MAX_REQUEST_SIZE 64 #define UVC_MAX_EVENTS 4 From b00c55eca43685b1a10aea974314a11482fedc24 Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Thu, 20 May 2021 12:31:08 +0530 Subject: [PATCH 35/55] USB: dwc3: gadget: Queue data for 16 micro frames ahead in future While starting transfer for isochrnous endpoints, make sure first request is queued for 16 microframes ahead in future. Also set PENDING_REQUEST flag before giving back usb request if started_list is empty to avoid queuing in same context. Else it leads to request getting queued for micro frame interval which might have expired and resulting USB HW retiring TRB without sending data to host. Change-Id: Ia5e4512fa2a3ae6637f2be7ef2f102c26d56213c Signed-off-by: Vijayavardhan Vennapusa --- drivers/usb/dwc3/core.h | 2 ++ drivers/usb/dwc3/debug_ipc.c | 5 +++-- drivers/usb/dwc3/gadget.c | 23 +++++++++++++++++++---- 3 files changed, 24 insertions(+), 6 deletions(-) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 9e12cc6c54c4..9422ea5896be 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -722,6 +722,7 @@ struct dwc3_ep_events { * @desc: usb_endpoint_descriptor pointer * @dwc: pointer to DWC controller * @saved_state: ep state saved during hibernation + * @missed_isoc_packets: counter for missed packets sent * @flags: endpoint flags (wedged, stalled, ...) * @number: endpoint number (1 - 15) * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK @@ -752,6 +753,7 @@ struct dwc3_ep { struct dwc3 *dwc; u32 saved_state; + u32 missed_isoc_packets; unsigned flags; #define DWC3_EP_ENABLED BIT(0) #define DWC3_EP_STALL BIT(1) diff --git a/drivers/usb/dwc3/debug_ipc.c b/drivers/usb/dwc3/debug_ipc.c index 1873b222dc8c..0b73285f1dc0 100644 --- a/drivers/usb/dwc3/debug_ipc.c +++ b/drivers/usb/dwc3/debug_ipc.c @@ -149,10 +149,11 @@ void dwc3_dbg_dma_unmap(struct dwc3 *dwc, u8 ep_num, struct dwc3_request *req) req->trb->ctrl & DWC3_TRB_CTRL_HWO); } else { ipc_log_string(dwc->dwc_dma_ipc_log_ctxt, - "%02X-%-3.3s %-25.25s 0x%pK 0x%lx %u 0x%lx %d", + "%02X-%-3.3s %-25.25s 0x%pK 0x%lx %u 0x%lx %d %u", ep_num >> 1, ep_num & 1 ? "IN":"OUT", "UNMAP", &req->request, req->request.dma, req->request.length, - req->trb_dma, req->trb->ctrl & DWC3_TRB_CTRL_HWO); + req->trb_dma, req->trb->ctrl & DWC3_TRB_CTRL_HWO, + req->request.actual); } } diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 6806669351b3..12579d7fe365 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -319,6 +319,12 @@ void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, dwc3_gadget_del_and_unmap_request(dep, req, status); + if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && + (list_empty(&dep->started_list))) { + dep->flags |= DWC3_EP_PENDING_REQUEST; + dbg_event(dep->number, "STARTEDLISTEMPTY", 0); + } + spin_unlock(&dwc->lock); usb_gadget_giveback_request(&dep->endpoint, &req->request); spin_lock(&dwc->lock); @@ -1054,6 +1060,8 @@ static int dwc3_gadget_ep_disable(struct usb_ep *ep) spin_lock_irqsave(&dwc->lock, flags); ret = __dwc3_gadget_ep_disable(dep); dbg_event(dep->number, "DISABLE", ret); + dbg_event(dep->number, "MISSEDISOCPKTS", dep->missed_isoc_packets); + dep->missed_isoc_packets = 0; spin_unlock_irqrestore(&dwc->lock, flags); pm_runtime_mark_last_busy(dwc->sysdev); pm_runtime_put_sync_autosuspend(dwc->sysdev); @@ -1628,7 +1636,7 @@ static void __dwc3_gadget_start_isoc(struct dwc3_ep *dep) wraparound_bits += BIT(14); dep->frame_number = __dwc3_gadget_get_frame(dep->dwc) + - 2 * dep->interval; + max_t(u32, 16, 2 * dep->interval); /* align uf to ep interval */ dep->frame_number = (wraparound_bits | dep->frame_number) & @@ -1687,8 +1695,9 @@ static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) if ((dep->flags & DWC3_EP_PENDING_REQUEST)) { if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) { __dwc3_gadget_start_isoc(dep); - return 0; + dep->flags &= ~DWC3_EP_PENDING_REQUEST; } + return 0; } } @@ -3181,12 +3190,18 @@ static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep, if (event->status & DEPEVT_STATUS_MISSED_ISOC) { status = -EXDEV; - if (list_empty(&dep->started_list)) - stop = true; + dep->missed_isoc_packets++; + dbg_event(dep->number, "MISSEDISOC", 0); } dwc3_gadget_ep_cleanup_completed_requests(dep, event, status); + if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && + (list_empty(&dep->started_list))) { + stop = true; + dbg_event(dep->number, "STOPXFER", dep->frame_number); + } + if (stop) dwc3_stop_active_transfer(dwc, dep->number, true); /* From 92cc2ae1c33aa5c3121da7d763fae3c68b1ba817 Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Fri, 21 May 2021 14:56:11 +0530 Subject: [PATCH 36/55] defconfig: Enable SDM429 configs Enable SDM429 config for MSM8937_32. Change-Id: I6fcb9cc61a2c4ab1046a11b0bc3fa5f495a4963e Signed-off-by: Swetha Chikkaboraiah --- arch/arm/configs/vendor/msm8937-perf_defconfig | 1 + arch/arm/configs/vendor/msm8937_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/configs/vendor/msm8937-perf_defconfig b/arch/arm/configs/vendor/msm8937-perf_defconfig index 8dd105c50c10..55b6dff176a1 100644 --- a/arch/arm/configs/vendor/msm8937-perf_defconfig +++ b/arch/arm/configs/vendor/msm8937-perf_defconfig @@ -50,6 +50,7 @@ CONFIG_ARCH_QM215=y CONFIG_ARCH_MSM8917=y CONFIG_ARCH_MSM8937=y CONFIG_ARCH_SDM439=y +CONFIG_ARCH_SDM429=y # CONFIG_VDSO is not set CONFIG_SMP=y CONFIG_SCHED_MC=y diff --git a/arch/arm/configs/vendor/msm8937_defconfig b/arch/arm/configs/vendor/msm8937_defconfig index 956be8a02b71..d22a1bfd328a 100644 --- a/arch/arm/configs/vendor/msm8937_defconfig +++ b/arch/arm/configs/vendor/msm8937_defconfig @@ -51,6 +51,7 @@ CONFIG_ARCH_QM215=y CONFIG_ARCH_MSM8917=y CONFIG_ARCH_MSM8937=y CONFIG_ARCH_SDM439=y +CONFIG_ARCH_SDM429=y # CONFIG_VDSO is not set CONFIG_SMP=y CONFIG_SCHED_MC=y From fa7b2ce6677bb08c32955657424b70fbb80512d8 Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Fri, 21 May 2021 18:12:01 +0530 Subject: [PATCH 37/55] f_uac2: increase number of requests to 32 for UAC2 Increase number of requests for UAC2 driver from 2 to 32 to reduce missed isoc events with isochronous endpoints. Change-Id: I918f4c9564f1697fd69f135f38f3fc116b3c0900 Signed-off-by: Vijayavardhan Vennapusa --- drivers/usb/gadget/function/u_uac2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/gadget/function/u_uac2.h b/drivers/usb/gadget/function/u_uac2.h index 39b73b777249..6a561cf39d98 100644 --- a/drivers/usb/gadget/function/u_uac2.h +++ b/drivers/usb/gadget/function/u_uac2.h @@ -21,7 +21,7 @@ #define UAC2_DEF_CCHMASK 0x3 #define UAC2_DEF_CSRATE 44100 #define UAC2_DEF_CSSIZE 2 -#define UAC2_DEF_REQ_NUM 2 +#define UAC2_DEF_REQ_NUM 32 struct f_uac2_opts { struct usb_function_instance func_inst; From be93eb3bd33b670fddfc7579f009bfefae7d99f2 Mon Sep 17 00:00:00 2001 From: Manjunatha Madana Date: Mon, 24 May 2021 17:30:02 +0530 Subject: [PATCH 38/55] defconfig: Enable config CONFIG_UTS_NS for msm8937_32 Enable config CONFIG_UTS_NS to support SHIPPING_API_LEVEL 30 for msm8937_32. Change-Id: Iff03b8ca7580904f91283f833f1629fc9feb3af2 Signed-off-by: Manjunatha Madana --- arch/arm/configs/vendor/msm8937-perf_defconfig | 1 - arch/arm/configs/vendor/msm8937_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm/configs/vendor/msm8937-perf_defconfig b/arch/arm/configs/vendor/msm8937-perf_defconfig index 9fe85f23bbb4..b2723fbdded3 100644 --- a/arch/arm/configs/vendor/msm8937-perf_defconfig +++ b/arch/arm/configs/vendor/msm8937-perf_defconfig @@ -27,7 +27,6 @@ CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_BPF=y CONFIG_SCHED_CORE_CTL=y CONFIG_NAMESPACES=y -# CONFIG_UTS_NS is not set # CONFIG_PID_NS is not set CONFIG_SCHED_AUTOGROUP=y CONFIG_SCHED_TUNE=y diff --git a/arch/arm/configs/vendor/msm8937_defconfig b/arch/arm/configs/vendor/msm8937_defconfig index f2340d792e8b..10cba26e4327 100644 --- a/arch/arm/configs/vendor/msm8937_defconfig +++ b/arch/arm/configs/vendor/msm8937_defconfig @@ -29,7 +29,6 @@ CONFIG_CGROUP_BPF=y CONFIG_CGROUP_DEBUG=y CONFIG_SCHED_CORE_CTL=y CONFIG_NAMESPACES=y -# CONFIG_UTS_NS is not set # CONFIG_PID_NS is not set CONFIG_SCHED_AUTOGROUP=y CONFIG_SCHED_TUNE=y From a90aeb624df47f85b0feb96a7290b700e4be1016 Mon Sep 17 00:00:00 2001 From: Pramod Gurav Date: Wed, 14 Dec 2016 19:15:44 +0530 Subject: [PATCH 39/55] tty: serial: msm: Add suspend resume support Add suspend/resume callback support to serial msm driver. Change-Id: I661fca45d2d762a08e331f53d8b3cb7b99117448 Signed-off-by: Pramod Gurav Signed-off-by: Runmin Wang Signed-off-by: Avaneesh Kumar Dwivedi --- drivers/tty/serial/msm_serial.c | 40 ++++++++++++++++++++++----------- 1 file changed, 27 insertions(+), 13 deletions(-) diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c index 4caeca67fd14..7906427283e4 100644 --- a/drivers/tty/serial/msm_serial.c +++ b/drivers/tty/serial/msm_serial.c @@ -1160,15 +1160,6 @@ static int msm_set_baud_rate(struct uart_port *port, unsigned int baud, return baud; } -static void msm_init_clock(struct uart_port *port) -{ - struct msm_port *msm_port = UART_TO_MSM(port); - - clk_prepare_enable(msm_port->clk); - clk_prepare_enable(msm_port->pclk); - msm_serial_set_mnd_regs(port); -} - static int msm_startup(struct uart_port *port) { struct msm_port *msm_port = UART_TO_MSM(port); @@ -1178,7 +1169,19 @@ static int msm_startup(struct uart_port *port) snprintf(msm_port->name, sizeof(msm_port->name), "msm_serial%d", port->line); - msm_init_clock(port); + /* + * UART clk must be kept enabled to + * avoid losing received character + */ + ret = clk_prepare_enable(msm_port->clk); + if (ret) + return ret; + + ret = clk_prepare_enable(msm_port->pclk); + if (ret) + goto err_pclk; + + msm_serial_set_mnd_regs(port); if (likely(port->fifosize > 12)) rfr_level = port->fifosize - 12; @@ -1217,6 +1220,8 @@ static int msm_startup(struct uart_port *port) clk_disable_unprepare(msm_port->pclk); clk_disable_unprepare(msm_port->clk); +err_pclk: + clk_disable_unprepare(msm_port->clk); return ret; } @@ -1231,6 +1236,7 @@ static void msm_shutdown(struct uart_port *port) if (msm_port->is_uartdm) msm_release_dma(msm_port); + clk_disable_unprepare(msm_port->pclk); clk_disable_unprepare(msm_port->clk); free_irq(port->irq, port); @@ -1397,8 +1403,16 @@ static void msm_power(struct uart_port *port, unsigned int state, switch (state) { case 0: - clk_prepare_enable(msm_port->clk); - clk_prepare_enable(msm_port->pclk); + /* + * UART clk must be kept enabled to + * avoid losing received character + */ + if (clk_prepare_enable(msm_port->clk)) + return; + if (clk_prepare_enable(msm_port->pclk)) { + clk_disable_unprepare(msm_port->clk); + return; + } break; case 3: clk_disable_unprepare(msm_port->clk); @@ -1670,7 +1684,7 @@ static int __init msm_console_setup(struct console *co, char *options) if (unlikely(!port->membase)) return -ENXIO; - msm_init_clock(port); + msm_serial_set_mnd_regs(port); if (options) uart_parse_options(options, &baud, &parity, &bits, &flow); From 256736e56578352431ad17fc33c022788e08f43b Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Mon, 26 Apr 2021 12:56:51 +0530 Subject: [PATCH 40/55] defconfig: Enable SDM429 configs Enable SDM429 config for MSM8937_32go. Change-Id: I26e71c6fcf91960ba9dbb0ea623eea88aab904be Signed-off-by: Swetha Chikkaboraiah --- arch/arm/configs/vendor/msm8937_32go-perf_defconfig | 1 + arch/arm/configs/vendor/msm8937_32go_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/configs/vendor/msm8937_32go-perf_defconfig b/arch/arm/configs/vendor/msm8937_32go-perf_defconfig index 4bd6bc58167c..dcb048b1436e 100644 --- a/arch/arm/configs/vendor/msm8937_32go-perf_defconfig +++ b/arch/arm/configs/vendor/msm8937_32go-perf_defconfig @@ -50,6 +50,7 @@ CONFIG_ARCH_QM215=y CONFIG_ARCH_MSM8917=y CONFIG_ARCH_MSM8937=y CONFIG_ARCH_SDM439=y +CONFIG_ARCH_SDM429=y # CONFIG_VDSO is not set CONFIG_SMP=y CONFIG_SCHED_MC=y diff --git a/arch/arm/configs/vendor/msm8937_32go_defconfig b/arch/arm/configs/vendor/msm8937_32go_defconfig index b8e0d873ebc9..9d055beebcfa 100644 --- a/arch/arm/configs/vendor/msm8937_32go_defconfig +++ b/arch/arm/configs/vendor/msm8937_32go_defconfig @@ -51,6 +51,7 @@ CONFIG_ARCH_QM215=y CONFIG_ARCH_MSM8917=y CONFIG_ARCH_MSM8937=y CONFIG_ARCH_SDM439=y +CONFIG_ARCH_SDM429=y # CONFIG_VDSO is not set CONFIG_SMP=y CONFIG_SCHED_MC=y From 003eea8ea972f1debe4b4e46b509cf02f39e7c8d Mon Sep 17 00:00:00 2001 From: Nirmal Abraham Date: Thu, 22 Nov 2018 09:22:02 +0530 Subject: [PATCH 41/55] msm: mdss: clear fences in ESD panel dead scenario When a panel_dead scenario occurs during ESD test, MDP driver's release/retire fences are cleared from mdss_fb_atomic_commit. Since mdss_fb_atomic_commit is called from HAL(user space) context, this leads to race condition between HAL and mdss driver resulting in UI freeze / UI corruption due to the difference between release fence timeline and commit_cnt. To avoid this, handle the panel dead scenario gracefully from the mdss driver context. Change-Id: Id42d88b26bba4c811ae547001759317cda3ef365 Signed-off-by: Nirmal Abraham Signed-off-by: Althaf Neelanchirayil --- drivers/video/fbdev/msm/mdss_fb.c | 31 +++++++++++++------------------ 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/drivers/video/fbdev/msm/mdss_fb.c b/drivers/video/fbdev/msm/mdss_fb.c index 9a8ae556540f..3b1fe465208b 100644 --- a/drivers/video/fbdev/msm/mdss_fb.c +++ b/drivers/video/fbdev/msm/mdss_fb.c @@ -3687,6 +3687,19 @@ static int __mdss_fb_perform_commit(struct msm_fb_data_type *mfd) int ret = -ENOTSUPP; u32 new_dsi_mode, dynamic_dsi_switch = 0; + if (mfd->panel_info->panel_dead) { + pr_debug("Panel dead, Signal fence and exit commit\n"); + /* + * In case of ESD attack, return early from commit + * after signalling fences. + */ + mdss_fb_release_kickoff(mfd); + mdss_fb_signal_timeline(sync_pt_data); + if ((mfd->panel.type == MIPI_CMD_PANEL) && + (mfd->mdp.signal_retire_fence)) + mfd->mdp.signal_retire_fence(mfd, 1); + return ret; + } if (!sync_pt_data->async_wait_fences) mdss_fb_wait_for_fence(sync_pt_data); sync_pt_data->flushed = false; @@ -4657,7 +4670,6 @@ static int mdss_fb_atomic_commit_ioctl(struct fb_info *info, struct mdp_destination_scaler_data *ds_data = NULL; struct mdp_destination_scaler_data __user *ds_data_user; struct msm_fb_data_type *mfd; - struct mdss_overlay_private *mdp5_data = NULL; struct mdss_data_type *mdata; ret = copy_from_user(&commit, argp, sizeof(struct mdp_layer_commit)); @@ -4670,23 +4682,6 @@ static int mdss_fb_atomic_commit_ioctl(struct fb_info *info, if (!mfd) return -EINVAL; - mdp5_data = mfd_to_mdp5_data(mfd); - - if (mfd->panel_info->panel_dead) { - pr_debug("early commit return\n"); - MDSS_XLOG(mfd->panel_info->panel_dead); - /* - * In case of an ESD attack, since we early return from the - * commits, we need to signal the outstanding fences. - */ - mdss_fb_release_fences(mfd); - if ((mfd->panel.type == MIPI_CMD_PANEL) && - mfd->mdp.signal_retire_fence && mdp5_data) - mfd->mdp.signal_retire_fence(mfd, - mdp5_data->retire_cnt); - return 0; - } - output_layer_user = commit.commit_v1.output_layer; if (output_layer_user) { buffer_size = sizeof(struct mdp_output_layer); From f467fd7b82f5a1e1ec791ff17deb23313fdeb218 Mon Sep 17 00:00:00 2001 From: Nirmal Abraham Date: Fri, 22 Jan 2021 12:11:48 +0530 Subject: [PATCH 42/55] fbdev: msm: Increment commit count during null commit Calling overlay_kickoff during overlay_off path without incrementing commit_cnt results in release fence timeline getting incremented and causes early fence signalling in subsequent commits leading to flicker. To avoid this, increment commit_cnt before null commit is initiated. Change-Id: I7ec482bfc192a58fa8819633a7830f440b3bd91b Signed-off-by: Nirmal Abraham --- drivers/video/fbdev/msm/mdss_mdp_overlay.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/fbdev/msm/mdss_mdp_overlay.c b/drivers/video/fbdev/msm/mdss_mdp_overlay.c index 8de4749bf10c..b1bcdce75285 100644 --- a/drivers/video/fbdev/msm/mdss_mdp_overlay.c +++ b/drivers/video/fbdev/msm/mdss_mdp_overlay.c @@ -5899,7 +5899,7 @@ static int mdss_mdp_overlay_off(struct msm_fb_data_type *mfd) pr_debug("cleaning up pipes on fb%d\n", mfd->index); if (mdata->handoff_pending) mdp5_data->allow_kickoff = true; - + atomic_inc(&mfd->mdp_sync_pt_data.commit_cnt); mdss_mdp_overlay_kickoff(mfd, NULL); } else if (!mdss_mdp_ctl_is_power_on(mdp5_data->ctl)) { if (mfd->panel_reconfig) { From 2b1f6b11d569424c4a9b26ca56de87e62d316ba9 Mon Sep 17 00:00:00 2001 From: Chetan C R Date: Mon, 22 Jun 2020 10:49:10 +0530 Subject: [PATCH 43/55] clk: qcom: Add enable_safe_config for gfx3d_clk_src Set enable_safe_config to true for configuring the rcg2 to cxo when disabled. Change-Id: I05d4a85f8c684b4df2ac86c7d70955cd2cecd22e Signed-off-by: Chetan C R --- drivers/clk/qcom/gpucc-sdm660.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gpucc-sdm660.c b/drivers/clk/qcom/gpucc-sdm660.c index ef5b819ab21e..138825de911d 100644 --- a/drivers/clk/qcom/gpucc-sdm660.c +++ b/drivers/clk/qcom/gpucc-sdm660.c @@ -203,6 +203,7 @@ static struct clk_rcg2 gfx3d_clk_src = { .freq_tbl = ftbl_gfx3d_clk_src, .parent_map = gpucc_parent_map_1, .flags = FORCE_ENABLE_RCG, + .enable_safe_config = true, .clkr.hw.init = &gpu_clks_init[0], }; From 0949e032300a952c0b0c1b8333b1a893451a8c4b Mon Sep 17 00:00:00 2001 From: Veerabhadrarao Badiganti Date: Tue, 18 Jun 2019 18:49:41 +0530 Subject: [PATCH 44/55] mmc: sdhci-msm: Skip PWRSAVE_DLL setting for sdcc minor verion 0x4D Skip PWRSAVE_DLL setting for sdcc minor version 0x4D. SDCC controller with this minor version on few MSM uses 14lpp DLL. So we should skip setting this. Change-Id: I5e7b95c88e44a65b26acc0fcf353fb3ba7d0b0eb Signed-off-by: Veerabhadrarao Badiganti Signed-off-by: Sarthak Garg --- drivers/mmc/host/sdhci-msm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 09fa4dd7ad7c..8fd65027f1a4 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. * * drivers/mmc/host/sdhci-msm.c - Qualcomm Technologies, Inc. MSM SDHCI Platform * driver source file @@ -5148,7 +5148,7 @@ static void sdhci_set_default_hw_caps(struct sdhci_msm_host *msm_host, * starts coming. */ if ((major == 1) && ((minor == 0x42) || (minor == 0x46) || - (minor == 0x49) || (minor >= 0x6b))) + (minor == 0x49) || (minor == 0x4D) || (minor >= 0x6b))) msm_host->use_14lpp_dll = true; /* Fake 3.0V support for SDIO devices which requires such voltage */ From 329da4eb964117786199ea5328f9745d93830ae0 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Mon, 24 May 2021 00:08:45 +0530 Subject: [PATCH 45/55] mmc: cmdq_hci: Notify sdhci for enhanced strobe Provide cmdq_host ops of enhanced strobe to notify sdhci on enabling/disabling cmdq. This is needed because of following: Before running CMDQ transfers in HS400 Enhanced Strobe mode, SW should write 3 to HC_VENDOR_SPECIFIC_FUNC3.CMDEN_HS400_INPUT_MASK_CNT register. Default reset value of this register is 2. Change-Id: I36ead91ca8c9aeed967f120f8bdc3d2180af7746 Signed-off-by: Ritesh Harjani [xiaonian@codeaurora.org: fixed trivial merge conflicts] Signed-off-by: Xiaonian Wang Signed-off-by: Sarthak Garg --- drivers/mmc/host/cqhci.c | 6 +++ drivers/mmc/host/cqhci.h | 3 +- drivers/mmc/host/sdhci-msm.c | 71 ++++++++++++++++++------------------ drivers/mmc/host/sdhci.h | 1 - 4 files changed, 44 insertions(+), 37 deletions(-) diff --git a/drivers/mmc/host/cqhci.c b/drivers/mmc/host/cqhci.c index b89f2b795fe3..74215418642f 100644 --- a/drivers/mmc/host/cqhci.c +++ b/drivers/mmc/host/cqhci.c @@ -375,6 +375,9 @@ static int cqhci_enable(struct mmc_host *mmc, struct mmc_card *card) __cqhci_enable(cq_host); + if (cq_host->ops->enhanced_strobe_mask) + cq_host->ops->enhanced_strobe_mask(mmc, true); + cq_host->enabled = true; #ifdef DEBUG @@ -430,6 +433,9 @@ static void cqhci_disable(struct mmc_host *mmc) __cqhci_disable(cq_host); + if (cq_host->ops->enhanced_strobe_mask) + cq_host->ops->enhanced_strobe_mask(mmc, false); + dmam_free_coherent(mmc_dev(mmc), cq_host->data_size, cq_host->trans_desc_base, cq_host->trans_desc_dma_base); diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h index 8c54e978c405..6ad4d2a6301c 100644 --- a/drivers/mmc/host/cqhci.h +++ b/drivers/mmc/host/cqhci.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -339,6 +339,7 @@ struct cqhci_host_ops { u32 (*read_l)(struct cqhci_host *host, int reg); void (*enable)(struct mmc_host *mmc); void (*disable)(struct mmc_host *mmc, bool recovery); + void (*enhanced_strobe_mask)(struct mmc_host *mmc, bool set); }; static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 8fd65027f1a4..21293fc2afbd 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -2553,10 +2553,46 @@ void sdhci_msm_cqe_sdhci_dumpregs(struct mmc_host *mmc) sdhci_dumpregs(host); } +/* + * sdhci_msm_enhanced_strobe_mask :- + * Before running CMDQ transfers in HS400 Enhanced Strobe mode, + * SW should write 3 to + * HC_VENDOR_SPECIFIC_FUNC3.CMDEN_HS400_INPUT_MASK_CNT register. + * The default reset value of this register is 2. + */ +static void sdhci_msm_enhanced_strobe_mask(struct mmc_host *mmc, bool set) +{ + struct sdhci_host *host = mmc_priv(mmc); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + const struct sdhci_msm_offset *msm_host_offset = + msm_host->offset; + + if (!msm_host->enhanced_strobe || + !mmc_card_strobe(msm_host->mmc->card)) { + pr_debug("%s: host/card does not support hs400 enhanced strobe\n", + mmc_hostname(host->mmc)); + return; + } + + if (set) { + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC3) + | CORE_CMDEN_HS400_INPUT_MASK_CNT), + host->ioaddr + msm_host_offset->CORE_VENDOR_SPEC3); + } else { + writel_relaxed((readl_relaxed(host->ioaddr + + msm_host_offset->CORE_VENDOR_SPEC3) + & ~CORE_CMDEN_HS400_INPUT_MASK_CNT), + host->ioaddr + msm_host_offset->CORE_VENDOR_SPEC3); + } +} + static const struct cqhci_host_ops sdhci_msm_cqhci_ops = { .enable = sdhci_msm_cqe_enable, .disable = sdhci_msm_cqe_disable, .dumpregs = sdhci_msm_cqe_sdhci_dumpregs, + .enhanced_strobe_mask = sdhci_msm_enhanced_strobe_mask, }; #ifdef CONFIG_MMC_CQHCI @@ -4360,40 +4396,6 @@ static void sdhci_msm_reset(struct sdhci_host *host, u8 mask) cqhci_suspend(host->mmc); } -/* - * sdhci_msm_enhanced_strobe_mask :- - * Before running CMDQ transfers in HS400 Enhanced Strobe mode, - * SW should write 3 to - * HC_VENDOR_SPECIFIC_FUNC3.CMDEN_HS400_INPUT_MASK_CNT register. - * The default reset value of this register is 2. - */ -static void sdhci_msm_enhanced_strobe_mask(struct sdhci_host *host, bool set) -{ - struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); - struct sdhci_msm_host *msm_host = pltfm_host->priv; - const struct sdhci_msm_offset *msm_host_offset = - msm_host->offset; - - if (!msm_host->enhanced_strobe || - !mmc_card_strobe(msm_host->mmc->card)) { - pr_debug("%s: host/card does not support hs400 enhanced strobe\n", - mmc_hostname(host->mmc)); - return; - } - - if (set) { - writel_relaxed((readl_relaxed(host->ioaddr + - msm_host_offset->CORE_VENDOR_SPEC3) - | CORE_CMDEN_HS400_INPUT_MASK_CNT), - host->ioaddr + msm_host_offset->CORE_VENDOR_SPEC3); - } else { - writel_relaxed((readl_relaxed(host->ioaddr + - msm_host_offset->CORE_VENDOR_SPEC3) - & ~CORE_CMDEN_HS400_INPUT_MASK_CNT), - host->ioaddr + msm_host_offset->CORE_VENDOR_SPEC3); - } -} - static void sdhci_msm_clear_set_dumpregs(struct sdhci_host *host, bool set) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); @@ -5059,7 +5061,6 @@ static struct sdhci_ops sdhci_msm_ops = { .set_bus_width = sdhci_set_bus_width, .reset = sdhci_msm_reset, .clear_set_dumpregs = sdhci_msm_clear_set_dumpregs, - .enhanced_strobe_mask = sdhci_msm_enhanced_strobe_mask, .reset_workaround = sdhci_msm_reset_workaround, .init = sdhci_msm_init, .pre_req = sdhci_msm_pre_req, diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 0e179f59a9a7..44f631a4b1a4 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -733,7 +733,6 @@ struct sdhci_ops { bool enable, u32 type); int (*enable_controller_clock)(struct sdhci_host *host); void (*clear_set_dumpregs)(struct sdhci_host *host, bool set); - void (*enhanced_strobe_mask)(struct sdhci_host *host, bool set); void (*dump_vendor_regs)(struct sdhci_host *host); void (*voltage_switch)(struct sdhci_host *host); int (*select_drive_strength)(struct sdhci_host *host, From de15875219d304744f4510745ff574fe824f8989 Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Fri, 21 May 2021 14:58:10 +0530 Subject: [PATCH 46/55] defconfig: Enable SDM429 configs Enable SDM429 config for MSM8937_64. Change-Id: I90d4bd6e25e35bc38dd3036517b62173b88b76b5 Signed-off-by: Swetha Chikkaboraiah --- arch/arm64/configs/vendor/msm8937-perf_defconfig | 1 + arch/arm64/configs/vendor/msm8937_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/msm8937-perf_defconfig b/arch/arm64/configs/vendor/msm8937-perf_defconfig index cff86ff5915d..b51851ea58b4 100644 --- a/arch/arm64/configs/vendor/msm8937-perf_defconfig +++ b/arch/arm64/configs/vendor/msm8937-perf_defconfig @@ -46,6 +46,7 @@ CONFIG_PROFILING=y CONFIG_ARCH_QCOM=y CONFIG_ARCH_QM215=y CONFIG_ARCH_MSM8937=y +CONFIG_ARCH_SDM429=y CONFIG_ARCH_SDM439=y # CONFIG_ARM64_ERRATUM_1024718 is not set CONFIG_SCHED_MC=y diff --git a/arch/arm64/configs/vendor/msm8937_defconfig b/arch/arm64/configs/vendor/msm8937_defconfig index 989eae2b28da..cd3b46bf1ac6 100644 --- a/arch/arm64/configs/vendor/msm8937_defconfig +++ b/arch/arm64/configs/vendor/msm8937_defconfig @@ -47,6 +47,7 @@ CONFIG_PROFILING=y CONFIG_ARCH_QCOM=y CONFIG_ARCH_QM215=y CONFIG_ARCH_MSM8937=y +CONFIG_ARCH_SDM429=y CONFIG_ARCH_SDM439=y # CONFIG_ARM64_ERRATUM_1024718 is not set CONFIG_SCHED_MC=y From 213cc06a3876ea55e20cda943c8f02b6efe2e24e Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Thu, 27 May 2021 09:36:48 +0530 Subject: [PATCH 47/55] serial: msm_geni_serial: Add ioctl for sending uart error codes to BT host Add changes in serial driver to update uart errors. When BT host driver observes a fault in BT transfers this ioctl needs to be called. On this ioctl call uart driver will return uart error to BT host if there are any. Change-Id: I741b017038b63f1a03aca2169c2190b94b95a15a Signed-off-by: Chandana Kishori Chiluveru --- drivers/tty/serial/msm_geni_serial.c | 119 ++++++++++++++++++++++++--- include/uapi/asm-generic/ioctls.h | 2 +- 2 files changed, 108 insertions(+), 13 deletions(-) diff --git a/drivers/tty/serial/msm_geni_serial.c b/drivers/tty/serial/msm_geni_serial.c index 9d9a1dc84558..09189b7c90e5 100644 --- a/drivers/tty/serial/msm_geni_serial.c +++ b/drivers/tty/serial/msm_geni_serial.c @@ -152,6 +152,30 @@ #define DMA_RX_BUF_SIZE (2048) #define UART_CONSOLE_RX_WM (2) +enum uart_error_code { + UART_ERROR_DEFAULT, + UART_ERROR_INVALID_FW_LOADED, + UART_ERROR_CLK_GET_FAIL, + UART_ERROR_SE_CLK_RATE_FIND_FAIL, + UART_ERROR_SE_RESOURCES_INIT_FAIL, + UART_ERROR_SE_RESOURCES_ON_FAIL, + UART_ERROR_SE_RESOURCES_OFF_FAIL, + UART_ERROR_TX_DMA_MAP_FAIL, + UART_ERROR_TX_CANCEL_FAIL, + UART_ERROR_TX_ABORT_FAIL, + UART_ERROR_TX_FSM_RESET_FAIL, + UART_ERROR_RX_CANCEL_FAIL, + UART_ERROR_RX_ABORT_FAIL, + UART_ERROR_RX_FSM_RESET_FAIL, + UART_ERROR_RX_TTY_INSERT_FAIL, + UART_ERROR_ILLEGAL_INTERRUPT, + UART_ERROR_BUFFER_OVERRUN, + UART_ERROR_RX_PARITY_ERROR, + UART_ERROR_RX_BREAK_ERROR, + UART_ERROR_RX_SBE_ERROR, + SOC_ERROR_START_TX_IOS_SOC_RFR_HIGH +}; + struct msm_geni_serial_ver_info { int hw_major_ver; int hw_minor_ver; @@ -212,6 +236,7 @@ struct msm_geni_serial_port { struct completion s_cmd_timeout; spinlock_t rx_lock; bool bypass_flow_control; + enum uart_error_code uart_error; }; static const struct uart_ops msm_geni_serial_pops; @@ -248,6 +273,19 @@ static struct msm_geni_serial_port msm_geni_console_port; static struct msm_geni_serial_port msm_geni_serial_ports[GENI_UART_NR_PORTS]; static void msm_geni_serial_handle_isr(struct uart_port *uport, unsigned long *flags, bool is_irq_masked); +/* + * The below API is required to pass UART error code to BT HOST. + */ +static void msm_geni_update_uart_error_code(struct msm_geni_serial_port *port, + enum uart_error_code uart_error_code) +{ + if (!port->is_console && !port->uart_error) { + port->uart_error = uart_error_code; + IPC_LOG_MSG(port->ipc_log_misc, + "%s: uart_error_code:%d\n", __func__, port->uart_error); + } +} + /* * The below API is required to check if uport->lock (spinlock) @@ -557,6 +595,7 @@ static int msm_geni_serial_ioctl(struct uart_port *uport, unsigned int cmd, { int ret = -ENOIOCTLCMD; struct msm_geni_serial_port *port = GET_DEV_PORT(uport); + enum uart_error_code uart_error; switch (cmd) { case TIOCPMGET: { @@ -572,13 +611,12 @@ static int msm_geni_serial_ioctl(struct uart_port *uport, unsigned int cmd, break; } case TIOCFAULT: { - geni_se_dump_dbg_regs(&port->serial_rsc, - uport->membase, port->ipc_log_misc); - port->ipc_log_rx = port->ipc_log_single; - port->ipc_log_tx = port->ipc_log_single; - port->ipc_log_misc = port->ipc_log_single; - port->ipc_log_pwr = port->ipc_log_single; - ret = 0; + uart_error = port->uart_error; + port->uart_error = UART_ERROR_DEFAULT; + IPC_LOG_MSG(port->ipc_log_misc, + "%s:TIOCFAULT - uart_error_set:%d new_uart_error:%d\n", + __func__, uart_error, port->uart_error); + ret = uart_error; break; } default: @@ -629,6 +667,10 @@ static unsigned int msm_geni_serial_get_mctrl(struct uart_port *uport) geni_ios = geni_read_reg_nolog(uport->membase, SE_GENI_IOS); if (!(geni_ios & IO2_DATA_IN)) mctrl |= TIOCM_CTS; + else + msm_geni_update_uart_error_code(port, + SOC_ERROR_START_TX_IOS_SOC_RFR_HIGH); + IPC_LOG_MSG(port->ipc_log_misc, "%s: geni_ios:0x%x, mctrl:0x%x\n", __func__, geni_ios, mctrl); return mctrl; @@ -1111,6 +1153,8 @@ static int msm_geni_serial_prep_dma_tx(struct uart_port *uport) } else { IPC_LOG_MSG(msm_port->ipc_log_misc, "%s: TX DMA map Fail %d\n", __func__, ret); + msm_geni_update_uart_error_code(msm_port, + UART_ERROR_TX_DMA_MAP_FAIL); geni_write_reg_nolog(0, uport->membase, SE_UART_TX_TRANS_LEN); msm_port->m_cmd_done = false; @@ -1133,6 +1177,8 @@ static int msm_geni_serial_prep_dma_tx(struct uart_port *uport) IPC_LOG_MSG(msm_port->ipc_log_misc, "%s: tx_cancel failed 0x%x\n", __func__, geni_read_reg_nolog(uport->membase, SE_GENI_STATUS)); + msm_geni_update_uart_error_code(msm_port, + UART_ERROR_TX_CANCEL_FAIL); msm_port->m_cmd_done = false; reinit_completion(&msm_port->m_cmd_timeout); @@ -1150,6 +1196,8 @@ static int msm_geni_serial_prep_dma_tx(struct uart_port *uport) "%s: tx abort failed 0x%x\n", __func__, geni_read_reg_nolog(uport->membase, SE_GENI_STATUS)); + msm_geni_update_uart_error_code(msm_port, + UART_ERROR_TX_ABORT_FAIL); } } @@ -1164,9 +1212,12 @@ static int msm_geni_serial_prep_dma_tx(struct uart_port *uport) timeout = geni_wait_for_cmd_done(uport, is_irq_masked); - if (timeout) + if (timeout) { IPC_LOG_MSG(msm_port->ipc_log_misc, "%s: tx fsm reset failed\n", __func__); + msm_geni_update_uart_error_code( + msm_port, UART_ERROR_TX_FSM_RESET_FAIL); + } } if (msm_port->tx_dma) { @@ -1275,6 +1326,8 @@ static void stop_tx_sequencer(struct uart_port *uport) __func__, geni_read_reg_nolog(uport->membase, SE_GENI_STATUS)); IPC_LOG_MSG(port->ipc_log_misc, "%s: tx_cancel failed 0x%x\n", __func__, geni_read_reg_nolog(uport->membase, SE_GENI_STATUS)); + msm_geni_update_uart_error_code(port, + UART_ERROR_TX_CANCEL_FAIL); port->m_cmd_done = false; reinit_completion(&port->m_cmd_timeout); @@ -1288,6 +1341,8 @@ static void stop_tx_sequencer(struct uart_port *uport) IPC_LOG_MSG(port->ipc_log_misc, "%s: tx abort failed 0x%x\n", __func__, geni_read_reg_nolog(uport->membase, SE_GENI_STATUS)); + msm_geni_update_uart_error_code(port, + UART_ERROR_TX_ABORT_FAIL); } } @@ -1301,9 +1356,12 @@ static void stop_tx_sequencer(struct uart_port *uport) timeout = geni_wait_for_cmd_done(uport, is_irq_masked); - if (timeout) + if (timeout) { IPC_LOG_MSG(port->ipc_log_misc, "%s: tx fsm reset failed\n", __func__); + msm_geni_update_uart_error_code(port, + UART_ERROR_TX_FSM_RESET_FAIL); + } } if (port->tx_dma) { @@ -1522,6 +1580,9 @@ static int stop_rx_sequencer(struct uart_port *uport) __func__, timeout, is_rx_active, geni_status); geni_se_dump_dbg_regs(&port->serial_rsc, uport->membase, port->ipc_log_misc); + msm_geni_update_uart_error_code(port, + UART_ERROR_RX_CANCEL_FAIL); + /* * Possible that stop_rx is called from system resume context * for console usecase. In early resume, irq remains disabled @@ -1551,6 +1612,8 @@ static int stop_rx_sequencer(struct uart_port *uport) IPC_LOG_MSG(port->console_log, "%s abort fail timeout:%d is_rx_active:%d 0x%x\n", __func__, timeout, is_rx_active, geni_status); + msm_geni_update_uart_error_code(port, + UART_ERROR_RX_ABORT_FAIL); geni_se_dump_dbg_regs(&port->serial_rsc, uport->membase, port->ipc_log_misc); } @@ -1563,9 +1626,12 @@ static int stop_rx_sequencer(struct uart_port *uport) timeout = geni_wait_for_cmd_done(uport, is_irq_masked); - if (timeout) + if (timeout) { IPC_LOG_MSG(port->ipc_log_misc, "%s: rx fsm reset failed\n", __func__); + msm_geni_update_uart_error_code(port, + UART_ERROR_RX_FSM_RESET_FAIL); + } } } /* Enable the interrupts once the cancel operation is done. */ @@ -1631,6 +1697,8 @@ static int handle_rx_hs(struct uart_port *uport, if (ret != rx_bytes) { dev_err(uport->dev, "%s: ret %d rx_bytes %d\n", __func__, ret, rx_bytes); + msm_geni_update_uart_error_code(msm_port, + UART_ERROR_RX_TTY_INSERT_FAIL); WARN_ON(1); } uport->icount.rx += ret; @@ -1916,6 +1984,8 @@ static bool handle_rx_dma_xfer(u32 s_irq_status, struct uart_port *uport) "%s.Rx Errors. 0x%x parity:%d\n", __func__, dma_rx_status, uport->icount.parity); + msm_geni_update_uart_error_code(msm_port, + UART_ERROR_RX_PARITY_ERROR); drop_rx = true; } else if (dma_rx_status & UART_DMA_RX_BREAK) { uport->icount.brk++; @@ -1923,6 +1993,8 @@ static bool handle_rx_dma_xfer(u32 s_irq_status, struct uart_port *uport) "%s.Rx Errors. 0x%x break:%d\n", __func__, dma_rx_status, uport->icount.brk); + msm_geni_update_uart_error_code(msm_port, + UART_ERROR_RX_BREAK_ERROR); } if (dma_rx_status & RX_EOT || @@ -1942,6 +2014,8 @@ static bool handle_rx_dma_xfer(u32 s_irq_status, struct uart_port *uport) IPC_LOG_MSG(msm_port->ipc_log_misc, "%s.Rx Errors. 0x%x\n", __func__, dma_rx_status); + msm_geni_update_uart_error_code(msm_port, + UART_ERROR_RX_SBE_ERROR); WARN_ON(1); } @@ -2000,8 +2074,11 @@ static void msm_geni_serial_handle_isr(struct uart_port *uport, IPC_LOG_MSG(msm_port->console_log, "%s.Illegal interrupt. sirq 0x%x mirq:0x%x\n", __func__, s_irq_status, m_irq_status); - else + else { + msm_geni_update_uart_error_code(msm_port, + UART_ERROR_ILLEGAL_INTERRUPT); WARN_ON(1); + } goto exit_geni_serial_isr; } @@ -2018,6 +2095,8 @@ static void msm_geni_serial_handle_isr(struct uart_port *uport, IPC_LOG_MSG(msm_port->ipc_log_misc, "%s.sirq 0x%x buf_overrun:%d\n", __func__, s_irq_status, uport->icount.buf_overrun); + msm_geni_update_uart_error_code(msm_port, + UART_ERROR_BUFFER_OVERRUN); } dma = geni_read_reg_nolog(uport->membase, SE_GENI_DMA_MODE_EN); @@ -2531,6 +2610,8 @@ static void msm_geni_serial_set_termios(struct uart_port *uport, if (ret) { dev_err(uport->dev, "%s: Failed(%d) to find src clk for 0x%x\n", __func__, ret, baud); + msm_geni_update_uart_error_code(port, + UART_ERROR_SE_CLK_RATE_FIND_FAIL); goto exit_set_termios; } @@ -3252,8 +3333,11 @@ static int msm_geni_serial_probe(struct platform_device *pdev) UART_CORE2X_VOTE, (DEFAULT_SE_CLK * DEFAULT_BUS_WIDTH)); - if (ret) + if (ret) { + msm_geni_update_uart_error_code(dev_port, + UART_ERROR_SE_RESOURCES_INIT_FAIL); goto exit_geni_serial_probe; + } dev_port->serial_rsc.ctrl_dev = &pdev->dev; @@ -3274,6 +3358,8 @@ static int msm_geni_serial_probe(struct platform_device *pdev) if (IS_ERR(dev_port->serial_rsc.se_clk)) { ret = PTR_ERR(dev_port->serial_rsc.se_clk); dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); + msm_geni_update_uart_error_code(dev_port, + UART_ERROR_CLK_GET_FAIL); goto exit_geni_serial_probe; } @@ -3281,6 +3367,8 @@ static int msm_geni_serial_probe(struct platform_device *pdev) if (IS_ERR(dev_port->serial_rsc.m_ahb_clk)) { ret = PTR_ERR(dev_port->serial_rsc.m_ahb_clk); dev_err(&pdev->dev, "Err getting M AHB clk %d\n", ret); + msm_geni_update_uart_error_code(dev_port, + UART_ERROR_CLK_GET_FAIL); goto exit_geni_serial_probe; } @@ -3288,6 +3376,8 @@ static int msm_geni_serial_probe(struct platform_device *pdev) if (IS_ERR(dev_port->serial_rsc.s_ahb_clk)) { ret = PTR_ERR(dev_port->serial_rsc.s_ahb_clk); dev_err(&pdev->dev, "Err getting S AHB clk %d\n", ret); + msm_geni_update_uart_error_code(dev_port, + UART_ERROR_CLK_GET_FAIL); goto exit_geni_serial_probe; } @@ -3427,6 +3517,7 @@ static int msm_geni_serial_probe(struct platform_device *pdev) device_create_file(uport->dev, &dev_attr_ver_info); msm_geni_serial_debug_init(uport, is_console); dev_port->port_setup = false; + dev_port->uart_error = UART_ERROR_DEFAULT; ret = msm_geni_serial_get_ver_info(uport); if (ret) goto exit_wakeup_unregister; @@ -3524,6 +3615,8 @@ static int msm_geni_serial_runtime_suspend(struct device *dev) ret = se_geni_resources_off(&port->serial_rsc); if (ret) { dev_err(dev, "%s: Error ret %d\n", __func__, ret); + msm_geni_update_uart_error_code(port, + UART_ERROR_SE_RESOURCES_OFF_FAIL); goto exit_runtime_suspend; } @@ -3560,6 +3653,8 @@ static int msm_geni_serial_runtime_resume(struct device *dev) ret = se_geni_resources_on(&port->serial_rsc); if (ret) { dev_err(dev, "%s: Error ret %d\n", __func__, ret); + msm_geni_update_uart_error_code(port, + UART_ERROR_SE_RESOURCES_ON_FAIL); __pm_relax(port->geni_wake); goto exit_runtime_resume; } diff --git a/include/uapi/asm-generic/ioctls.h b/include/uapi/asm-generic/ioctls.h index 44ccfd8818f2..6b14abd5180c 100644 --- a/include/uapi/asm-generic/ioctls.h +++ b/include/uapi/asm-generic/ioctls.h @@ -79,7 +79,7 @@ #define TIOCGPTLCK _IOR('T', 0x39, int) /* Get Pty lock state */ #define TIOCGEXCL _IOR('T', 0x40, int) /* Get exclusive mode state */ #define TIOCGPTPEER _IO('T', 0x41) /* Safely open the slave */ -#define TIOCFAULT 0x544C /* Uart fault */ +#define TIOCFAULT 0x54EC /* Uart fault */ #define TIOCPMGET 0x544D /* PM get */ #define TIOCPMPUT 0x544E /* PM put */ #define TIOCPMACT 0x544F /* PM is active */ From 75edf721cc8a77fb6a006943692660434a7123e8 Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Mon, 1 Mar 2021 14:51:59 +0800 Subject: [PATCH 48/55] power: supply: smb1398-charger: disable WIN_OV deglitch for SMB1394 Disable WIN_OV deglitch for SMB1394 to avoid device damage from high in-rush current in dead short case. Change-Id: I6f057cf965b489ec000ded57698cd5ef7972cfec Signed-off-by: Fenglin Wu --- drivers/power/supply/qcom/smb1398-charger.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/power/supply/qcom/smb1398-charger.c b/drivers/power/supply/qcom/smb1398-charger.c index aa78a2978b8b..c0d98d60edd7 100644 --- a/drivers/power/supply/qcom/smb1398-charger.c +++ b/drivers/power/supply/qcom/smb1398-charger.c @@ -181,6 +181,7 @@ #define PERPH0_CFG_SDCDC_REG 0x267A #define EN_WIN_UV_BIT BIT(7) +#define EN_WIN_OV_RISE_DEB_BIT BIT(6) #define PERPH0_SOVP_CFG0_REG 0x2680 #define CFG_OVP_VSNS_THRESHOLD BIT(4) @@ -2008,6 +2009,11 @@ static int _smb1394_update_ovp(struct smb1398_chip *chip) return rc; } + rc = smb1398_masked_write(chip, PERPH0_CFG_SDCDC_REG, + EN_WIN_OV_RISE_DEB_BIT, 0); + if (rc < 0) + dev_err(chip->dev, "Couldn't set PERPH0_CFG_SDCDC_REG rc=%d\n", + rc); return rc; } From 45116fddbabac1c2ba1b30692fcca1cd61cf2dc5 Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Tue, 25 May 2021 23:45:52 +0530 Subject: [PATCH 49/55] msm: ipa3: Fix to change the tag process timeout value in cleanup Due to less timeout value it was getting timed out and device was asserting. To avoid the assert increaseing the tag process timeout value. Change-Id: I82d55e7aa9618e13480b34f8ec4f4853dafc646f Signed-off-by: Ashok Vuyyuru --- drivers/platform/msm/ipa/ipa_v3/ipa_i.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h index 29a8fbdb0e1b..062946cc2a0a 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #ifndef _IPA3_I_H_ @@ -272,7 +272,7 @@ enum { #define IPA_AGGR_MAX_STR_LENGTH (10) -#define CLEANUP_TAG_PROCESS_TIMEOUT 1000 +#define CLEANUP_TAG_PROCESS_TIMEOUT 5000 #define IPA_AGGR_STR_IN_BYTES(str) \ (strnlen((str), IPA_AGGR_MAX_STR_LENGTH - 1) + 1) From 86a6c336b83ef849899b0496a5b7c6188fe46215 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Fri, 28 May 2021 14:33:40 +0530 Subject: [PATCH 50/55] dt-bindings: clock: gcc-khaje: Add support for USB3 MUX and BCR USB driver requires support for GCC_USB3_PRIM_PHY_PIPE_CLK_SRC and GCC_USB3_DP_PHY_PRIM_BCR, hence add support for the same. Change-Id: I9435fbe0cae3f44aa04ff368d73f42a78b413396 Signed-off-by: Jagadeesh Kona --- include/dt-bindings/clock/qcom,gcc-khaje.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-khaje.h b/include/dt-bindings/clock/qcom,gcc-khaje.h index b0e820190ada..336dc50b2040 100644 --- a/include/dt-bindings/clock/qcom,gcc-khaje.h +++ b/include/dt-bindings/clock/qcom,gcc-khaje.h @@ -170,6 +170,7 @@ #define GCC_VIDEO_VENUS_CLK_SRC 160 #define GCC_VIDEO_VENUS_CTL_CLK 161 #define GCC_VIDEO_XO_CLK 162 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 163 /* GCC resets */ #define GCC_QUSB2PHY_PRIM_BCR 0 @@ -184,5 +185,6 @@ #define GCC_VCODEC0_BCR 9 #define GCC_VENUS_BCR 10 #define GCC_VIDEO_INTERFACE_BCR 11 +#define GCC_USB3_DP_PHY_PRIM_BCR 12 #endif From a11276a48f214476c196db681c2977c3a6937183 Mon Sep 17 00:00:00 2001 From: Madhuri Medasani Date: Wed, 28 Apr 2021 17:14:32 +0530 Subject: [PATCH 51/55] clk: qcom: gcc-khaje: Add GCC support for KHAJE Add support for Global Clock Controller for peripheral clock clients to be able to request for the clocks for KHAJE. Change-Id: I66eccf7d0ef8789eb8fe63c427504f0da654a548 Signed-off-by: Madhuri Medasani --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-khaje.c | 3727 ++++++++++++++++++++++++++++++++++ 3 files changed, 3736 insertions(+) create mode 100644 drivers/clk/qcom/gcc-khaje.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 6c43d83c29ea..ffd7b70bb234 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -608,3 +608,11 @@ config CLOCK_CPU_SDM Support for the cpu clock controller on SDM based devices(e.g. QM215/SDM429). Say Y if you want to support CPU clock scaling using CPUfreq drivers for dynamic power management. + +config SM_GCC_KHAJE + tristate "KHAJE Global Clock Controller" + depends on COMMON_CLK_QCOM + help + Support for the global clock controller on KHAJE devices. + Say Y if you want to use peripheral devices such as UART, SPI, + I2C, USB, UFS, SDCC, PCIe, Camera, Video etc. diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index fa1f143e1d24..c439648b2d8a 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -76,6 +76,7 @@ obj-$(CONFIG_SM_DEBUGCC_LITO) += debugcc-lito.o obj-$(CONFIG_SM_DISPCC_BENGAL) += dispcc-bengal.o obj-$(CONFIG_SM_DISPCC_LITO) += dispcc-lito.o obj-$(CONFIG_SM_GCC_BENGAL) += gcc-bengal.o +obj-$(CONFIG_SM_GCC_KHAJE) += gcc-khaje.o obj-$(CONFIG_SM_GCC_LITO) += gcc-lito.o obj-$(CONFIG_SM_GPUCC_BENGAL) += gpucc-bengal.o obj-$(CONFIG_SM_GPUCC_LITO) += gpucc-lito.o diff --git a/drivers/clk/qcom/gcc-khaje.c b/drivers/clk/qcom/gcc-khaje.c new file mode 100644 index 000000000000..2cc2ca1b4f04 --- /dev/null +++ b/drivers/clk/qcom/gcc-khaje.c @@ -0,0 +1,3727 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "reset.h" +#include "vdd-level-bengal.h" + +static DEFINE_VDD_REGULATORS(vdd_cx, VDD_HIGH + 1, 1, vdd_corner); +static DEFINE_VDD_REGULATORS(vdd_mx, VDD_HIGH + 1, 1, vdd_corner); + +enum { + P_BI_TCXO, + P_GPLL0_OUT_EVEN, + P_GPLL0_OUT_MAIN, + P_GPLL10_OUT_MAIN, + P_GPLL11_OUT_EVEN, + P_GPLL11_OUT_MAIN, + P_GPLL11_OUT_ODD, + P_GPLL3_OUT_EVEN, + P_GPLL3_OUT_MAIN, + P_GPLL4_OUT_MAIN, + P_GPLL5_OUT_MAIN, + P_GPLL6_OUT_EVEN, + P_GPLL6_OUT_MAIN, + P_GPLL7_OUT_MAIN, + P_GPLL8_OUT_EVEN, + P_GPLL8_OUT_MAIN, + P_GPLL9_OUT_EARLY, + P_GPLL9_OUT_MAIN, + P_SLEEP_CLK, + P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, +}; + +static const struct parent_map gcc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_EVEN, 2 }, +}; + +static const char * const gcc_parent_names_0[] = { + "bi_tcxo", + "gpll0", + "gpll0_out_even", +}; + +static const struct parent_map gcc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_EVEN, 2 }, + { P_GPLL6_OUT_EVEN, 4 }, +}; + +static const char * const gcc_parent_names_1[] = { + "bi_tcxo", + "gpll0", + "gpll0_out_even", + "gpll6_out_even", +}; + +static const struct parent_map gcc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_EVEN, 2 }, + { P_SLEEP_CLK, 5 }, +}; + +static const char * const gcc_parent_names_2[] = { + "bi_tcxo", + "gpll0", + "gpll0_out_even", + "sleep_clk", +}; + +static const struct parent_map gcc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL9_OUT_EARLY, 2 }, + { P_GPLL10_OUT_MAIN, 3 }, + { P_GPLL9_OUT_MAIN, 5 }, + { P_GPLL3_OUT_EVEN, 6 }, +}; + +static const char * const gcc_parent_names_3[] = { + "bi_tcxo", + "gpll0", + "gpll9", + "gpll10", + "gpll9_out_main", + "gpll3_out_even", +}; + +static const struct parent_map gcc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_EVEN, 2 }, + { P_GPLL4_OUT_MAIN, 5 }, + { P_GPLL3_OUT_EVEN, 6 }, +}; + +static const char * const gcc_parent_names_4[] = { + "bi_tcxo", + "gpll0", + "gpll0_out_even", + "gpll4", + "gpll3_out_even", +}; + +static const struct parent_map gcc_parent_map_5[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL8_OUT_MAIN, 2 }, + { P_GPLL10_OUT_MAIN, 3 }, + { P_GPLL8_OUT_EVEN, 4 }, + { P_GPLL9_OUT_MAIN, 5 }, + { P_GPLL3_OUT_EVEN, 6 }, +}; + +static const char * const gcc_parent_names_5[] = { + "bi_tcxo", + "gpll0", + "gpll8", + "gpll10", + "gpll8_out_even", + "gpll9_out_main", + "gpll3_out_even", +}; + +static const struct parent_map gcc_parent_map_6[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL8_OUT_MAIN, 2 }, + { P_GPLL5_OUT_MAIN, 3 }, + { P_GPLL6_OUT_EVEN, 4 }, + { P_GPLL9_OUT_MAIN, 5 }, + { P_GPLL3_OUT_MAIN, 6 }, +}; + +static const char * const gcc_parent_names_6[] = { + "bi_tcxo", + "gpll0", + "gpll8", + "gpll5", + "gpll6_out_even", + "gpll9_out_main", + "gpll3", +}; + +static const struct parent_map gcc_parent_map_7[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_EVEN, 2 }, + { P_GPLL10_OUT_MAIN, 3 }, + { P_GPLL4_OUT_MAIN, 5 }, + { P_GPLL3_OUT_MAIN, 6 }, +}; + +static const char * const gcc_parent_names_7[] = { + "bi_tcxo", + "gpll0", + "gpll0_out_even", + "gpll10", + "gpll4", + "gpll3", +}; + +static const struct parent_map gcc_parent_map_8[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL8_OUT_MAIN, 2 }, + { P_GPLL10_OUT_MAIN, 3 }, + { P_GPLL8_OUT_EVEN, 4 }, + { P_GPLL9_OUT_MAIN, 5 }, + { P_GPLL3_OUT_MAIN, 6 }, +}; + +static const char * const gcc_parent_names_8[] = { + "bi_tcxo", + "gpll0", + "gpll8", + "gpll10", + "gpll8_out_even", + "gpll9_out_main", + "gpll3", +}; + +static const struct parent_map gcc_parent_map_9[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_EVEN, 2 }, + { P_GPLL10_OUT_MAIN, 3 }, + { P_GPLL8_OUT_EVEN, 4 }, + { P_GPLL9_OUT_MAIN, 5 }, + { P_GPLL3_OUT_MAIN, 6 }, +}; + +static const char * const gcc_parent_names_9[] = { + "bi_tcxo", + "gpll0", + "gpll0_out_even", + "gpll10", + "gpll8_out_even", + "gpll9_out_main", + "gpll3", +}; + +static const struct parent_map gcc_parent_map_10[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL8_OUT_MAIN, 2 }, + { P_GPLL10_OUT_MAIN, 3 }, + { P_GPLL6_OUT_MAIN, 4 }, + { P_GPLL9_OUT_MAIN, 5 }, + { P_GPLL3_OUT_EVEN, 6 }, +}; + +static const char * const gcc_parent_names_10[] = { + "bi_tcxo", + "gpll0", + "gpll8", + "gpll10", + "gpll6", + "gpll9_out_main", + "gpll3_out_even", +}; + +static const struct parent_map gcc_parent_map_11[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_EVEN, 2 }, + { P_GPLL7_OUT_MAIN, 3 }, + { P_GPLL4_OUT_MAIN, 5 }, +}; + +static const char * const gcc_parent_names_11[] = { + "bi_tcxo", + "gpll0", + "gpll0_out_even", + "gpll7", + "gpll4", +}; + +static const struct parent_map gcc_parent_map_12[] = { + { P_BI_TCXO, 0 }, + { P_SLEEP_CLK, 5 }, +}; + +static const char * const gcc_parent_names_12[] = { + "bi_tcxo", + "sleep_clk", +}; + +static const struct parent_map gcc_parent_map_13[] = { + { P_BI_TCXO, 0 }, + { P_GPLL11_OUT_MAIN, 1 }, + { P_GPLL11_OUT_EVEN, 2 }, + { P_GPLL11_OUT_ODD, 3 }, +}; + +static const char * const gcc_parent_names_13[] = { + "bi_tcxo", + "gpll11", + "gpll11", + "gpll11", +}; + +static const struct parent_map gcc_parent_map_14[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL6_OUT_EVEN, 4 }, +}; + +static const char * const gcc_parent_names_14[] = { + "bi_tcxo", + "gpll0", + "gpll6_out_even", +}; + +static const struct parent_map gcc_parent_map_15[] = { + { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const char * const gcc_parent_names_15[] = { + "usb3_phy_wrapper_gcc_usb30_pipe_clk", + "bi_tcxo", +}; + +static struct pll_vco lucid_vco[] = { + { 249600000, 2000000000, 0 }, +}; + +static struct pll_vco zonda_vco[] = { + { 595200000, 3600000000, 0 }, +}; + +static struct clk_alpha_pll gpll0 = { + .offset = 0x0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpll0", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_MIN] = 615000000, + [VDD_LOW] = 1066000000, + [VDD_LOW_L1] = 1500000000, + [VDD_NOMINAL] = 1750000000, + [VDD_HIGH] = 2000000000}, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll0_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll0_out_even = { + .offset = 0x0, + .post_div_shift = 8, + .post_div_table = post_div_table_gpll0_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll0_out_even", + .parent_names = (const char *[]){ "gpll0" }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_lucid_ops, + }, +}; + +static struct clk_alpha_pll gpll1 = { + .offset = 0x1000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gpll1", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_MIN] = 615000000, + [VDD_LOW] = 1066000000, + [VDD_LOW_L1] = 1500000000, + [VDD_NOMINAL] = 1750000000, + [VDD_HIGH] = 2000000000}, + }, + }, +}; + +/* 1152MHz configuration */ +static const struct alpha_pll_config gpll10_config = { + .l = 0x3C, + .alpha = 0x0, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x329A299C, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll gpll10 = { + .offset = 0xa000, + .vco_table = lucid_vco, + .num_vco = ARRAY_SIZE(lucid_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .flags = SUPPORTS_FSM_LEGACY_MODE, + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(10), + .hw.init = &(struct clk_init_data){ + .name = "gpll10", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_ops, + .vdd_class = &vdd_mx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_MIN] = 615000000, + [VDD_LOW] = 1066000000, + [VDD_LOW_L1] = 1500000000, + [VDD_NOMINAL] = 1750000000, + [VDD_HIGH] = 2000000000}, + }, + }, +}; + +/* 600MHz configuration */ +static const struct alpha_pll_config gpll11_config = { + .l = 0x1F, + .alpha = 0x4000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x329A299C, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll gpll11 = { + .offset = 0xb000, + .vco_table = lucid_vco, + .num_vco = ARRAY_SIZE(lucid_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_LEGACY_MODE, + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gpll11", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_MIN] = 615000000, + [VDD_LOW] = 1066000000, + [VDD_LOW_L1] = 1500000000, + [VDD_NOMINAL] = 1750000000, + [VDD_HIGH] = 2000000000}, + }, + }, +}; + +static struct clk_alpha_pll gpll3 = { + .offset = 0x3000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(3), + .hw.init = &(struct clk_init_data){ + .name = "gpll3", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_MIN] = 615000000, + [VDD_LOW] = 1066000000, + [VDD_LOW_L1] = 1500000000, + [VDD_NOMINAL] = 1750000000, + [VDD_HIGH] = 2000000000}, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll3_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll3_out_even = { + .offset = 0x3000, + .post_div_shift = 8, + .post_div_table = post_div_table_gpll3_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_gpll3_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll3_out_even", + .parent_names = (const char *[]){ "gpll3" }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_lucid_ops, + }, +}; + +static struct clk_alpha_pll gpll4 = { + .offset = 0x4000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gpll4", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_MIN] = 615000000, + [VDD_LOW] = 1066000000, + [VDD_LOW_L1] = 1500000000, + [VDD_NOMINAL] = 1750000000, + [VDD_HIGH] = 2000000000}, + }, + }, +}; + +static struct clk_alpha_pll gpll5 = { + .offset = 0x5000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(5), + .hw.init = &(struct clk_init_data){ + .name = "gpll5", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_MIN] = 615000000, + [VDD_LOW] = 1066000000, + [VDD_LOW_L1] = 1500000000, + [VDD_NOMINAL] = 1750000000, + [VDD_HIGH] = 2000000000}, + }, + }, +}; + +static struct clk_alpha_pll gpll6 = { + .offset = 0x6000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(6), + .hw.init = &(struct clk_init_data){ + .name = "gpll6", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ops, + .vdd_class = &vdd_mx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_MIN] = 615000000, + [VDD_LOW] = 1066000000, + [VDD_LOW_L1] = 1500000000, + [VDD_NOMINAL] = 1750000000, + [VDD_HIGH] = 2000000000}, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll6_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll6_out_even = { + .offset = 0x6000, + .post_div_shift = 8, + .post_div_table = post_div_table_gpll6_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_gpll6_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll6_out_even", + .parent_names = (const char *[]){ "gpll6" }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_lucid_ops, + }, +}; + +static struct clk_alpha_pll gpll7 = { + .offset = 0x7000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(7), + .hw.init = &(struct clk_init_data){ + .name = "gpll7", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_MIN] = 615000000, + [VDD_LOW] = 1066000000, + [VDD_LOW_L1] = 1500000000, + [VDD_NOMINAL] = 1750000000, + [VDD_HIGH] = 2000000000}, + }, + }, +}; + +/* 400MHz configuration */ +static const struct alpha_pll_config gpll8_config = { + .l = 0x14, + .alpha = 0xD555, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x329A299C, + .user_ctl_val = 0x00000101, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll gpll8 = { + .offset = 0x8000, + .vco_table = lucid_vco, + .num_vco = ARRAY_SIZE(lucid_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_LEGACY_MODE, + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(8), + .hw.init = &(struct clk_init_data){ + .name = "gpll8", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_MIN] = 615000000, + [VDD_LOW] = 1066000000, + [VDD_LOW_L1] = 1500000000, + [VDD_NOMINAL] = 1750000000, + [VDD_HIGH] = 2000000000}, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll8_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll8_out_even = { + .offset = 0x8000, + .post_div_shift = 8, + .post_div_table = post_div_table_gpll8_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_gpll8_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll8_out_even", + .parent_names = (const char *[]){ "gpll8" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ops, + }, +}; + +/* 1440MHz configuration */ +static const struct alpha_pll_config gpll9_config = { + .l = 0x4B, + .alpha = 0x0, + .config_ctl_val = 0x08200800, + .config_ctl_hi_val = 0x05022001, + .config_ctl_hi1_val = 0x00000010, + .user_ctl_val = 0x00000301, +}; + +static struct clk_alpha_pll gpll9 = { + .offset = 0x9000, + .vco_table = zonda_vco, + .num_vco = ARRAY_SIZE(zonda_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], + .clkr = { + .enable_reg = 0x79000, + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gpll9", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_zonda_ops, + .vdd_class = &vdd_mx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 1800000000, + [VDD_LOW] = 2400000000, + [VDD_NOMINAL] = 3000000000, + [VDD_HIGH] = 3600000000}, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll9_out_main[] = { + { 0x3, 4 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll9_out_main = { + .offset = 0x9000, + .post_div_shift = 8, + .post_div_table = post_div_table_gpll9_out_main, + .num_post_div = ARRAY_SIZE(post_div_table_gpll9_out_main), + .width = 2, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll9_out_main", + .parent_names = (const char *[]){ "gpll9" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_zonda_ops, + }, +}; + +static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { + .reg = 0x1a04c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", + .parent_names = + (const char *[]){ "gcc_usb30_prim_mock_utmi_clk_src" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_axi_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_axi_clk_src = { + .cmd_rcgr = 0x5802c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_7, + .freq_tbl = ftbl_gcc_camss_axi_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_axi_clk_src", + .parent_names = gcc_parent_names_7, + .num_parents = ARRAY_SIZE(gcc_parent_names_7), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 150000000, + [VDD_LOW_L1] = 240000000, + [VDD_NOMINAL] = 300000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_cci_clk_src = { + .cmd_rcgr = 0x56000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_9, + .freq_tbl = ftbl_gcc_camss_cci_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cci_clk_src", + .parent_names = gcc_parent_names_9, + .num_parents = ARRAY_SIZE(gcc_parent_names_9), + .flags = CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 37500000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { + .cmd_rcgr = 0x59000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi0phytimer_clk_src", + .parent_names = gcc_parent_names_4, + .num_parents = ARRAY_SIZE(gcc_parent_names_4), + .flags = CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 300000000}, + }, +}; + +static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { + .cmd_rcgr = 0x5901c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi1phytimer_clk_src", + .parent_names = gcc_parent_names_4, + .num_parents = ARRAY_SIZE(gcc_parent_names_4), + .flags = CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 300000000}, + }, +}; + +static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = { + .cmd_rcgr = 0x59038, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi2phytimer_clk_src", + .parent_names = gcc_parent_names_4, + .num_parents = ARRAY_SIZE(gcc_parent_names_4), + .flags = CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 300000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 15), + F(65454545, P_GPLL9_OUT_EARLY, 11, 1, 2), + { } +}; + +static struct clk_rcg2 gcc_camss_mclk0_clk_src = { + .cmd_rcgr = 0x51000, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk0_clk_src", + .parent_names = gcc_parent_names_3, + .num_parents = ARRAY_SIZE(gcc_parent_names_3), + .flags = CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 65454545}, + }, +}; + +static struct clk_rcg2 gcc_camss_mclk1_clk_src = { + .cmd_rcgr = 0x5101c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk1_clk_src", + .parent_names = gcc_parent_names_3, + .num_parents = ARRAY_SIZE(gcc_parent_names_3), + .flags = CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 65454545}, + }, +}; + +static struct clk_rcg2 gcc_camss_mclk2_clk_src = { + .cmd_rcgr = 0x51038, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk2_clk_src", + .parent_names = gcc_parent_names_3, + .num_parents = ARRAY_SIZE(gcc_parent_names_3), + .flags = CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 65454545}, + }, +}; + +static struct clk_rcg2 gcc_camss_mclk3_clk_src = { + .cmd_rcgr = 0x51054, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_camss_mclk0_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk3_clk_src", + .parent_names = gcc_parent_names_3, + .num_parents = ARRAY_SIZE(gcc_parent_names_3), + .flags = CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 65454545}, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_ope_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = { + .cmd_rcgr = 0x55024, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_8, + .freq_tbl = ftbl_gcc_camss_ope_ahb_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_ope_ahb_clk_src", + .parent_names = gcc_parent_names_8, + .num_parents = ARRAY_SIZE(gcc_parent_names_8), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 171428571, + [VDD_NOMINAL] = 240000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(200000000, P_GPLL8_OUT_EVEN, 1, 0, 0), + F(266600000, P_GPLL8_OUT_EVEN, 1, 0, 0), + F(480000000, P_GPLL8_OUT_EVEN, 1, 0, 0), + F(580000000, P_GPLL8_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_ope_clk_src = { + .cmd_rcgr = 0x55004, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_8, + .freq_tbl = ftbl_gcc_camss_ope_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_ope_clk_src", + .parent_names = gcc_parent_names_8, + .num_parents = ARRAY_SIZE(gcc_parent_names_8), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 200000000, + [VDD_LOW_L1] = 266600000, + [VDD_NOMINAL] = 480000000, + [VDD_HIGH] = 580000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0), + F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0), + F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0), + F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0), + F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0), + F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0), + F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0), + F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0), + F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0), + F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0), + F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0), + F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0), + F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0), + F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_tfe_0_clk_src = { + .cmd_rcgr = 0x52004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_5, + .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_tfe_0_clk_src", + .parent_names = gcc_parent_names_5, + .num_parents = ARRAY_SIZE(gcc_parent_names_5), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 300000000, + [VDD_LOW_L1] = 460800000, + [VDD_NOMINAL] = 576000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_tfe_0_csid_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), + F(266571429, P_GPLL5_OUT_MAIN, 3.5, 0, 0), + F(426400000, P_GPLL3_OUT_MAIN, 2.5, 0, 0), + F(466500000, P_GPLL5_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = { + .cmd_rcgr = 0x52094, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_6, + .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_tfe_0_csid_clk_src", + .parent_names = gcc_parent_names_6, + .num_parents = ARRAY_SIZE(gcc_parent_names_6), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 266571429, + [VDD_LOW_L1] = 426400000, + [VDD_NOMINAL] = 466500000}, + }, +}; + +static struct clk_rcg2 gcc_camss_tfe_1_clk_src = { + .cmd_rcgr = 0x52024, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_5, + .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_tfe_1_clk_src", + .parent_names = gcc_parent_names_5, + .num_parents = ARRAY_SIZE(gcc_parent_names_5), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 300000000, + [VDD_LOW_L1] = 460800000, + [VDD_NOMINAL] = 576000000}, + }, +}; + +static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = { + .cmd_rcgr = 0x520b4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_6, + .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_tfe_1_csid_clk_src", + .parent_names = gcc_parent_names_6, + .num_parents = ARRAY_SIZE(gcc_parent_names_6), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 266571429, + [VDD_LOW_L1] = 426400000, + [VDD_NOMINAL] = 466500000}, + }, +}; + +static struct clk_rcg2 gcc_camss_tfe_2_clk_src = { + .cmd_rcgr = 0x52044, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_5, + .freq_tbl = ftbl_gcc_camss_tfe_0_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_tfe_2_clk_src", + .parent_names = gcc_parent_names_5, + .num_parents = ARRAY_SIZE(gcc_parent_names_5), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 300000000, + [VDD_LOW_L1] = 460800000, + [VDD_NOMINAL] = 576000000}, + }, +}; + +static struct clk_rcg2 gcc_camss_tfe_2_csid_clk_src = { + .cmd_rcgr = 0x520d4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_6, + .freq_tbl = ftbl_gcc_camss_tfe_0_csid_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_tfe_2_csid_clk_src", + .parent_names = gcc_parent_names_6, + .num_parents = ARRAY_SIZE(gcc_parent_names_6), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 266571429, + [VDD_LOW_L1] = 426400000, + [VDD_NOMINAL] = 466500000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_tfe_cphy_rx_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(256000000, P_GPLL6_OUT_MAIN, 3, 0, 0), + F(384000000, P_GPLL6_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = { + .cmd_rcgr = 0x52064, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_10, + .freq_tbl = ftbl_gcc_camss_tfe_cphy_rx_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_tfe_cphy_rx_clk_src", + .parent_names = gcc_parent_names_10, + .num_parents = ARRAY_SIZE(gcc_parent_names_10), + .flags = CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 256000000, + [VDD_LOW_L1] = 384000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_camss_top_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0), + F(80000000, P_GPLL0_OUT_MAIN, 7.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_camss_top_ahb_clk_src = { + .cmd_rcgr = 0x58010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_7, + .freq_tbl = ftbl_gcc_camss_top_ahb_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_camss_top_ahb_clk_src", + .parent_names = gcc_parent_names_7, + .num_parents = ARRAY_SIZE(gcc_parent_names_7), + .flags = CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 80000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { + F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_gp1_clk_src = { + .cmd_rcgr = 0x4d004, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_gp1_clk_src", + .parent_names = gcc_parent_names_2, + .num_parents = ARRAY_SIZE(gcc_parent_names_2), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 50000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 200000000}, + }, +}; + +static struct clk_rcg2 gcc_gp2_clk_src = { + .cmd_rcgr = 0x4e004, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_gp2_clk_src", + .parent_names = gcc_parent_names_2, + .num_parents = ARRAY_SIZE(gcc_parent_names_2), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 50000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 200000000}, + }, +}; + +static struct clk_rcg2 gcc_gp3_clk_src = { + .cmd_rcgr = 0x4f004, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_gp3_clk_src", + .parent_names = gcc_parent_names_2, + .num_parents = ARRAY_SIZE(gcc_parent_names_2), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 50000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 200000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pdm2_clk_src = { + .cmd_rcgr = 0x20010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_pdm2_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_pdm2_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000, + [VDD_LOW] = 60000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { + F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), + F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), + F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375), + F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75), + F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625), + F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0), + F(128000000, P_GPLL6_OUT_EVEN, 3, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { + .name = "gcc_qupv3_wrap0_s0_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = ARRAY_SIZE(gcc_parent_names_1), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 75000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 128000000}, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { + .cmd_rcgr = 0x1f148, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { + .name = "gcc_qupv3_wrap0_s1_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = ARRAY_SIZE(gcc_parent_names_1), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 75000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 128000000}, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { + .cmd_rcgr = 0x1f278, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { + .name = "gcc_qupv3_wrap0_s2_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = ARRAY_SIZE(gcc_parent_names_1), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 75000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 128000000}, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { + .cmd_rcgr = 0x1f3a8, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { + .name = "gcc_qupv3_wrap0_s3_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = ARRAY_SIZE(gcc_parent_names_1), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 75000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 128000000}, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { + .cmd_rcgr = 0x1f4d8, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { + .name = "gcc_qupv3_wrap0_s4_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = ARRAY_SIZE(gcc_parent_names_1), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 75000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 128000000}, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { + .cmd_rcgr = 0x1f608, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { + .name = "gcc_qupv3_wrap0_s5_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = ARRAY_SIZE(gcc_parent_names_1), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 75000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 128000000}, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { + .cmd_rcgr = 0x1f738, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { + F(144000, P_BI_TCXO, 16, 3, 25), + F(400000, P_BI_TCXO, 12, 1, 4), + F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3), + F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(192000000, P_GPLL6_OUT_EVEN, 2, 0, 0), + F(384000000, P_GPLL6_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { + .cmd_rcgr = 0x38028, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = ARRAY_SIZE(gcc_parent_names_1), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .flags = CLK_OPS_PARENT_ENABLE, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 100000000, + [VDD_LOW_L1] = 384000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = { + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { + .cmd_rcgr = 0x38010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ice_core_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 100000000, + [VDD_LOW] = 150000000, + [VDD_LOW_L1] = 300000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { + F(400000, P_BI_TCXO, 12, 1, 4), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { + .cmd_rcgr = 0x1e00c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_11, + .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_apps_clk_src", + .parent_names = gcc_parent_names_11, + .num_parents = ARRAY_SIZE(gcc_parent_names_11), + .ops = &clk_rcg2_ops, + .flags = CLK_OPS_PARENT_ENABLE, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 100000000, + [VDD_LOW_L1] = 202000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { + F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { + .cmd_rcgr = 0x45020, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_axi_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 50000000, + [VDD_LOW] = 100000000, + [VDD_NOMINAL] = 200000000, + [VDD_HIGH] = 240000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { + F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), + F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), + F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { + .cmd_rcgr = 0x45048, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_ice_core_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 75000000, + [VDD_LOW] = 150000000, + [VDD_NOMINAL] = 300000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { + F(9600000, P_BI_TCXO, 2, 0, 0), + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { + .cmd_rcgr = 0x4507c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_phy_aux_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { + F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0), + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), + F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { + .cmd_rcgr = 0x45060, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_unipro_core_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 37500000, + [VDD_LOW] = 75000000, + [VDD_NOMINAL] = 150000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { + F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0), + F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { + .cmd_rcgr = 0x1a01c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_master_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 66666667, + [VDD_LOW] = 133333333, + [VDD_NOMINAL] = 200000000, + [VDD_HIGH] = 240000000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { + .cmd_rcgr = 0x1a034, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_mock_utmi_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000}, + }, +}; + +static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { + .cmd_rcgr = 0x1a060, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_12, + .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_prim_phy_aux_clk_src", + .parent_names = gcc_parent_names_12, + .num_parents = ARRAY_SIZE(gcc_parent_names_12), + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 19200000}, + }, +}; + +static const struct freq_tbl ftbl_gcc_video_venus_clk_src[] = { + F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0), + F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0), + F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0), + F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_video_venus_clk_src = { + .cmd_rcgr = 0x58060, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_13, + .freq_tbl = ftbl_gcc_video_venus_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_video_venus_clk_src", + .parent_names = gcc_parent_names_13, + .num_parents = ARRAY_SIZE(gcc_parent_names_13), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 133333333, + [VDD_LOW] = 240000000, + [VDD_LOW_L1] = 300000000, + [VDD_NOMINAL] = 384000000}, + }, +}; + +static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { + .reg = 0x1a05c, + .shift = 0, + .width = 2, + .parent_map = gcc_parent_map_15, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_prim_phy_pipe_clk_src", + .parent_names = gcc_parent_names_15, + .num_parents = ARRAY_SIZE(gcc_parent_names_15), + .ops = &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_branch gcc_ahb2phy_csi_clk = { + .halt_reg = 0x1d004, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x1d004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1d004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ahb2phy_csi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ahb2phy_usb_clk = { + .halt_reg = 0x1d008, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x1d008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1d008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ahb2phy_usb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_bimc_gpu_axi_clk = { + .halt_reg = 0x71154, + .halt_check = BRANCH_HALT_DELAY, + .hwcg_reg = 0x71154, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x71154, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bimc_gpu_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk = { + .halt_reg = 0x23004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x23004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_boot_rom_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cam_throttle_nrt_clk = { + .halt_reg = 0x17070, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x17070, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(27), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cam_throttle_nrt_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cam_throttle_rt_clk = { + .halt_reg = 0x1706c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x1706c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(26), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cam_throttle_rt_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_ahb_clk = { + .halt_reg = 0x17008, + .halt_check = BRANCH_HALT_DELAY, + .hwcg_reg = 0x17008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x17008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camera_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_axi_clk = { + .halt_reg = 0x58044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x58044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_axi_clk", + .parent_names = (const char *[]){ + "gcc_camss_axi_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cci_0_clk = { + .halt_reg = 0x56018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x56018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cci_0_clk", + .parent_names = (const char *[]){ + "gcc_camss_cci_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cphy_0_clk = { + .halt_reg = 0x52088, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x52088, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cphy_0_clk", + .parent_names = (const char *[]){ + "gcc_camss_tfe_cphy_rx_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cphy_1_clk = { + .halt_reg = 0x5208c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5208c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cphy_1_clk", + .parent_names = (const char *[]){ + "gcc_camss_tfe_cphy_rx_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_cphy_2_clk = { + .halt_reg = 0x52090, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x52090, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_cphy_2_clk", + .parent_names = (const char *[]){ + "gcc_camss_tfe_cphy_rx_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi0phytimer_clk = { + .halt_reg = 0x59018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x59018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi0phytimer_clk", + .parent_names = (const char *[]){ + "gcc_camss_csi0phytimer_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi1phytimer_clk = { + .halt_reg = 0x59034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x59034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi1phytimer_clk", + .parent_names = (const char *[]){ + "gcc_camss_csi1phytimer_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_csi2phytimer_clk = { + .halt_reg = 0x59050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x59050, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_csi2phytimer_clk", + .parent_names = (const char *[]){ + "gcc_camss_csi2phytimer_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_mclk0_clk = { + .halt_reg = 0x51018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x51018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk0_clk", + .parent_names = (const char *[]){ + "gcc_camss_mclk0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_mclk1_clk = { + .halt_reg = 0x51034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x51034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk1_clk", + .parent_names = (const char *[]){ + "gcc_camss_mclk1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_mclk2_clk = { + .halt_reg = 0x51050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x51050, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk2_clk", + .parent_names = (const char *[]){ + "gcc_camss_mclk2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_mclk3_clk = { + .halt_reg = 0x5106c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5106c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_mclk3_clk", + .parent_names = (const char *[]){ + "gcc_camss_mclk3_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_nrt_axi_clk = { + .halt_reg = 0x58054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x58054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_nrt_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_ope_ahb_clk = { + .halt_reg = 0x5503c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5503c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_ope_ahb_clk", + .parent_names = (const char *[]){ + "gcc_camss_ope_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_ope_clk = { + .halt_reg = 0x5501c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5501c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_ope_clk", + .parent_names = (const char *[]){ + "gcc_camss_ope_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_rt_axi_clk = { + .halt_reg = 0x5805c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5805c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_rt_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_tfe_0_clk = { + .halt_reg = 0x5201c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5201c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_tfe_0_clk", + .parent_names = (const char *[]){ + "gcc_camss_tfe_0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = { + .halt_reg = 0x5207c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5207c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_tfe_0_cphy_rx_clk", + .parent_names = (const char *[]){ + "gcc_camss_tfe_cphy_rx_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_tfe_0_csid_clk = { + .halt_reg = 0x520ac, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x520ac, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_tfe_0_csid_clk", + .parent_names = (const char *[]){ + "gcc_camss_tfe_0_csid_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_tfe_1_clk = { + .halt_reg = 0x5203c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5203c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_tfe_1_clk", + .parent_names = (const char *[]){ + "gcc_camss_tfe_1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = { + .halt_reg = 0x52080, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x52080, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_tfe_1_cphy_rx_clk", + .parent_names = (const char *[]){ + "gcc_camss_tfe_cphy_rx_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_tfe_1_csid_clk = { + .halt_reg = 0x520cc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x520cc, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_tfe_1_csid_clk", + .parent_names = (const char *[]){ + "gcc_camss_tfe_1_csid_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_tfe_2_clk = { + .halt_reg = 0x5205c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5205c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_tfe_2_clk", + .parent_names = (const char *[]){ + "gcc_camss_tfe_2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_tfe_2_cphy_rx_clk = { + .halt_reg = 0x52084, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x52084, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_tfe_2_cphy_rx_clk", + .parent_names = (const char *[]){ + "gcc_camss_tfe_cphy_rx_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_tfe_2_csid_clk = { + .halt_reg = 0x520ec, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x520ec, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_tfe_2_csid_clk", + .parent_names = (const char *[]){ + "gcc_camss_tfe_2_csid_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camss_top_ahb_clk = { + .halt_reg = 0x58028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x58028, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camss_top_ahb_clk", + .parent_names = (const char *[]){ + "gcc_camss_top_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { + .halt_reg = 0x1a084, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x1a084, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1a084, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cfg_noc_usb3_prim_axi_clk", + .parent_names = (const char *[]){ + "gcc_usb30_prim_master_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_ahb_clk = { + .halt_reg = 0x1700c, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x1700c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1700c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_disp_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_div gcc_disp_gpll0_clk_src = { + .reg = 0x17058, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gcc_disp_gpll0_clk_src", + .parent_names = + (const char *[]){ "gpll0" }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + }, +}; + +static struct clk_branch gcc_disp_gpll0_div_clk_src = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(20), + .hw.init = &(struct clk_init_data){ + .name = "gcc_disp_gpll0_div_clk_src", + .parent_names = (const char *[]){ + "gcc_disp_gpll0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_hf_axi_clk = { + .halt_reg = 0x17020, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x17020, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x17020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_disp_hf_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_sleep_clk = { + .halt_reg = 0x17074, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x17074, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x17074, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_disp_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_throttle_core_clk = { + .halt_reg = 0x17064, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x17064, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(5), + .hw.init = &(struct clk_init_data){ + .name = "gcc_disp_throttle_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk = { + .halt_reg = 0x4d000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4d000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp1_clk", + .parent_names = (const char *[]){ + "gcc_gp1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk = { + .halt_reg = 0x4e000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4e000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp2_clk", + .parent_names = (const char *[]){ + "gcc_gp2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk = { + .halt_reg = 0x4f000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4f000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp3_clk", + .parent_names = (const char *[]){ + "gcc_gp3_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_clk_src = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(15), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_clk_src", + .parent_names = (const char *[]){ + "gpll0", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_div_clk_src = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(16), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_div_clk_src", + .parent_names = (const char *[]){ + "gpll0_out_even", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_iref_clk = { + .halt_reg = 0x36100, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x36100, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_iref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_memnoc_gfx_clk = { + .halt_reg = 0x3600c, + .halt_check = BRANCH_VOTED, + .hwcg_reg = 0x3600c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x3600c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_memnoc_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { + .halt_reg = 0x36018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_snoc_dvm_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_throttle_core_clk = { + .halt_reg = 0x36048, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x36048, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(31), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_throttle_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk = { + .halt_reg = 0x2000c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2000c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm2_clk", + .parent_names = (const char *[]){ + "gcc_pdm2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk = { + .halt_reg = 0x20004, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x20004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x20004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_xo4_clk = { + .halt_reg = 0x20008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x20008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm_xo4_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_prng_ahb_clk = { + .halt_reg = 0x21004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x21004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(13), + .hw.init = &(struct clk_init_data){ + .name = "gcc_prng_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { + .halt_reg = 0x17014, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x17014, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qmip_camera_nrt_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { + .halt_reg = 0x17060, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x17060, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qmip_camera_rt_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_disp_ahb_clk = { + .halt_reg = 0x17018, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x17018, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qmip_disp_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = { + .halt_reg = 0x36040, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x36040, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qmip_gpu_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { + .halt_reg = 0x17010, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x17010, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(25), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qmip_video_vcodec_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { + .halt_reg = 0x1f014, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(9), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_core_2x_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_clk = { + .halt_reg = 0x1f00c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(8), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s0_clk = { + .halt_reg = 0x1f144, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s0_clk", + .parent_names = (const char *[]){ + "gcc_qupv3_wrap0_s0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s1_clk = { + .halt_reg = 0x1f274, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(11), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s1_clk", + .parent_names = (const char *[]){ + "gcc_qupv3_wrap0_s1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s2_clk = { + .halt_reg = 0x1f3a4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(12), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s2_clk", + .parent_names = (const char *[]){ + "gcc_qupv3_wrap0_s2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s3_clk = { + .halt_reg = 0x1f4d4, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(13), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s3_clk", + .parent_names = (const char *[]){ + "gcc_qupv3_wrap0_s3_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s4_clk = { + .halt_reg = 0x1f604, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(14), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s4_clk", + .parent_names = (const char *[]){ + "gcc_qupv3_wrap0_s4_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s5_clk = { + .halt_reg = 0x1f734, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(15), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s5_clk", + .parent_names = (const char *[]){ + "gcc_qupv3_wrap0_s5_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { + .halt_reg = 0x1f004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x1f004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(6), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap_0_m_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { + .halt_reg = 0x1f008, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x1f008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7900c, + .enable_mask = BIT(7), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap_0_s_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk = { + .halt_reg = 0x38008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x38008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk = { + .halt_reg = 0x38004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x38004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_apps_clk", + .parent_names = (const char *[]){ + "gcc_sdcc1_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_ENABLE_HAND_OFF, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ice_core_clk = { + .halt_reg = 0x3800c, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x3800c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x3800c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ice_core_clk", + .parent_names = (const char *[]){ + "gcc_sdcc1_ice_core_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_ahb_clk = { + .halt_reg = 0x1e008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1e008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_apps_clk = { + .halt_reg = 0x1e004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1e004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_apps_clk", + .parent_names = (const char *[]){ + "gcc_sdcc2_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { + .halt_reg = 0x2b06c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x2b06c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sys_noc_cpuss_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { + .halt_reg = 0x45098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x45098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sys_noc_ufs_phy_axi_clk", + .parent_names = (const char *[]){ + "gcc_ufs_phy_axi_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { + .halt_reg = 0x1a080, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x1a080, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1a080, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sys_noc_usb3_prim_axi_clk", + .parent_names = (const char *[]){ + "gcc_usb30_prim_master_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_clkref_clk = { + .halt_reg = 0x8c000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8c000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ahb_clk = { + .halt_reg = 0x45014, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x45014, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x45014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_axi_clk = { + .halt_reg = 0x45010, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x45010, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x45010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_axi_clk", + .parent_names = (const char *[]){ + "gcc_ufs_phy_axi_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ice_core_clk = { + .halt_reg = 0x45044, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x45044, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x45044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_ice_core_clk", + .parent_names = (const char *[]){ + "gcc_ufs_phy_ice_core_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_phy_aux_clk = { + .halt_reg = 0x45078, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x45078, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x45078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_phy_aux_clk", + .parent_names = (const char *[]){ + "gcc_ufs_phy_phy_aux_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { + .halt_reg = 0x4501c, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x4501c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_rx_symbol_0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { + .halt_reg = 0x4509c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4509c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_rx_symbol_1_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { + .halt_reg = 0x45018, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x45018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_tx_symbol_0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_unipro_core_clk = { + .halt_reg = 0x45040, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x45040, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x45040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_unipro_core_clk", + .parent_names = (const char *[]){ + "gcc_ufs_phy_unipro_core_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_master_clk = { + .halt_reg = 0x1a010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_master_clk", + .parent_names = (const char *[]){ + "gcc_usb30_prim_master_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { + .halt_reg = 0x1a018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_mock_utmi_clk", + .parent_names = (const char *[]){ + "gcc_usb30_prim_mock_utmi_postdiv_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_sleep_clk = { + .halt_reg = 0x1a014, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_clkref_clk = { + .halt_reg = 0x9f000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9f000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_prim_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { + .halt_reg = 0x1a054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_prim_phy_com_aux_clk", + .parent_names = (const char *[]){ + "gcc_usb3_prim_phy_aux_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { + .halt_reg = 0x1a058, + .halt_check = BRANCH_HALT_SKIP, + .hwcg_reg = 0x1a058, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1a058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_prim_phy_pipe_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_vcodec0_axi_clk = { + .halt_reg = 0x6e008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6e008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_vcodec0_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_venus_ahb_clk = { + .halt_reg = 0x6e010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6e010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_venus_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_venus_ctl_axi_clk = { + .halt_reg = 0x6e004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6e004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_venus_ctl_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_ahb_clk = { + .halt_reg = 0x17004, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x17004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x17004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_video_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_axi0_clk = { + .halt_reg = 0x1701c, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x1701c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1701c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_video_axi0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_throttle_core_clk = { + .halt_reg = 0x17068, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x17068, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(28), + .hw.init = &(struct clk_init_data){ + .name = "gcc_video_throttle_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_vcodec0_sys_clk = { + .halt_reg = 0x580a4, + .halt_check = BRANCH_HALT_DELAY, + .hwcg_reg = 0x580a4, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x580a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_video_vcodec0_sys_clk", + .parent_names = (const char *[]){ + "gcc_video_venus_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_venus_ctl_clk = { + .halt_reg = 0x5808c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5808c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_video_venus_ctl_clk", + .parent_names = (const char *[]){ + "gcc_video_venus_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_xo_clk = { + .halt_reg = 0x17024, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x17024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_video_xo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *gcc_khaje_clocks[] = { + [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr, + [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr, + [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, + [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, + [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, + [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, + [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, + [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, + [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr, + [GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr, + [GCC_CAMSS_CPHY_0_CLK] = &gcc_camss_cphy_0_clk.clkr, + [GCC_CAMSS_CPHY_1_CLK] = &gcc_camss_cphy_1_clk.clkr, + [GCC_CAMSS_CPHY_2_CLK] = &gcc_camss_cphy_2_clk.clkr, + [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, + [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr, + [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr, + [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr, + [GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr, + [GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr, + [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, + [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr, + [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, + [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr, + [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr, + [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr, + [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr, + [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr, + [GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr, + [GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr, + [GCC_CAMSS_OPE_AHB_CLK_SRC] = &gcc_camss_ope_ahb_clk_src.clkr, + [GCC_CAMSS_OPE_CLK] = &gcc_camss_ope_clk.clkr, + [GCC_CAMSS_OPE_CLK_SRC] = &gcc_camss_ope_clk_src.clkr, + [GCC_CAMSS_RT_AXI_CLK] = &gcc_camss_rt_axi_clk.clkr, + [GCC_CAMSS_TFE_0_CLK] = &gcc_camss_tfe_0_clk.clkr, + [GCC_CAMSS_TFE_0_CLK_SRC] = &gcc_camss_tfe_0_clk_src.clkr, + [GCC_CAMSS_TFE_0_CPHY_RX_CLK] = &gcc_camss_tfe_0_cphy_rx_clk.clkr, + [GCC_CAMSS_TFE_0_CSID_CLK] = &gcc_camss_tfe_0_csid_clk.clkr, + [GCC_CAMSS_TFE_0_CSID_CLK_SRC] = &gcc_camss_tfe_0_csid_clk_src.clkr, + [GCC_CAMSS_TFE_1_CLK] = &gcc_camss_tfe_1_clk.clkr, + [GCC_CAMSS_TFE_1_CLK_SRC] = &gcc_camss_tfe_1_clk_src.clkr, + [GCC_CAMSS_TFE_1_CPHY_RX_CLK] = &gcc_camss_tfe_1_cphy_rx_clk.clkr, + [GCC_CAMSS_TFE_1_CSID_CLK] = &gcc_camss_tfe_1_csid_clk.clkr, + [GCC_CAMSS_TFE_1_CSID_CLK_SRC] = &gcc_camss_tfe_1_csid_clk_src.clkr, + [GCC_CAMSS_TFE_2_CLK] = &gcc_camss_tfe_2_clk.clkr, + [GCC_CAMSS_TFE_2_CLK_SRC] = &gcc_camss_tfe_2_clk_src.clkr, + [GCC_CAMSS_TFE_2_CPHY_RX_CLK] = &gcc_camss_tfe_2_cphy_rx_clk.clkr, + [GCC_CAMSS_TFE_2_CSID_CLK] = &gcc_camss_tfe_2_csid_clk.clkr, + [GCC_CAMSS_TFE_2_CSID_CLK_SRC] = &gcc_camss_tfe_2_csid_clk_src.clkr, + [GCC_CAMSS_TFE_CPHY_RX_CLK_SRC] = &gcc_camss_tfe_cphy_rx_clk_src.clkr, + [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, + [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, + [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, + [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, + [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, + [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, + [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, + [GCC_DISP_SLEEP_CLK] = &gcc_disp_sleep_clk.clkr, + [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, + [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, + [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, + [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, + [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, + [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, + [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, + [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, + [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, + [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr, + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, + [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, + [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, + [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, + [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, + [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, + [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr, + [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr, + [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr, + [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr, + [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr, + [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr, + [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr, + [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr, + [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr, + [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr, + [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr, + [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr, + [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr, + [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, + [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, + [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr, + [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, + [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, + [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, + [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr, + [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, + [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, + [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, + [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, + [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, + [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, + [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, + [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, + [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, + [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, + [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, + [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, + [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, + [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = + &gcc_ufs_phy_unipro_core_clk_src.clkr, + [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, + [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = + &gcc_usb30_prim_mock_utmi_clk_src.clkr, + [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = + &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, + [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, + [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, + [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, + [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, + [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, + [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, + [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr, + [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr, + [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr, + [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, + [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, + [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, + [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr, + [GCC_VIDEO_VENUS_CLK_SRC] = &gcc_video_venus_clk_src.clkr, + [GCC_VIDEO_VENUS_CTL_CLK] = &gcc_video_venus_ctl_clk.clkr, + [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr, + [GPLL0] = &gpll0.clkr, + [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, + [GPLL1] = &gpll1.clkr, + [GPLL10] = &gpll10.clkr, + [GPLL11] = &gpll11.clkr, + [GPLL3] = &gpll3.clkr, + [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr, + [GPLL4] = &gpll4.clkr, + [GPLL5] = &gpll5.clkr, + [GPLL6] = &gpll6.clkr, + [GPLL6_OUT_EVEN] = &gpll6_out_even.clkr, + [GPLL7] = &gpll7.clkr, + [GPLL8] = &gpll8.clkr, + [GPLL8_OUT_EVEN] = &gpll8_out_even.clkr, + [GPLL9] = &gpll9.clkr, + [GPLL9_OUT_MAIN] = &gpll9_out_main.clkr, +}; + +static const struct qcom_reset_map gcc_khaje_resets[] = { + [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 }, + [GCC_SDCC1_BCR] = { 0x38000 }, + [GCC_SDCC2_BCR] = { 0x1e000 }, + [GCC_UFS_PHY_BCR] = { 0x45000 }, + [GCC_USB30_PRIM_BCR] = { 0x1a000 }, + [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, + [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x1b020 }, + [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, + [GCC_VCODEC0_BCR] = { 0x58094 }, + [GCC_VENUS_BCR] = { 0x58078 }, + [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 }, +}; + + +static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), +}; + +static const struct regmap_config gcc_khaje_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xc7000, + .fast_io = true, +}; + +static const struct qcom_cc_desc gcc_khaje_desc = { + .config = &gcc_khaje_regmap_config, + .clks = gcc_khaje_clocks, + .num_clks = ARRAY_SIZE(gcc_khaje_clocks), + .resets = gcc_khaje_resets, + .num_resets = ARRAY_SIZE(gcc_khaje_resets), +}; + +static const struct of_device_id gcc_khaje_match_table[] = { + { .compatible = "qcom,khaje-gcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_khaje_match_table); + +static int gcc_khaje_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + regmap = qcom_cc_map(pdev, &gcc_khaje_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx"); + if (IS_ERR(vdd_cx.regulator[0])) { + if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_cx regulator\n"); + return PTR_ERR(vdd_cx.regulator[0]); + } + + vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx"); + if (IS_ERR(vdd_mx.regulator[0])) { + if (!(PTR_ERR(vdd_mx.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_mx regulator\n"); + return PTR_ERR(vdd_mx.regulator[0]); + } + + /* + * Keep the clocks always-ON + * GCC_CAMERA_XO_CLK, GCC_CPUSS_GNOC_CLK, + * GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK + */ + regmap_update_bits(regmap, 0x17028, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x2b004, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x1702c, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0)); + + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, + ARRAY_SIZE(gcc_dfs_clocks)); + if (ret) + return ret; + + clk_lucid_pll_configure(&gpll10, regmap, &gpll10_config); + clk_lucid_pll_configure(&gpll11, regmap, &gpll11_config); + clk_lucid_pll_configure(&gpll8, regmap, &gpll8_config); + clk_zonda_pll_configure(&gpll9, regmap, &gpll9_config); + + + ret = qcom_cc_really_probe(pdev, &gcc_khaje_desc, regmap); + if (ret) { + dev_err(&pdev->dev, "Failed to register GCC clocks\n"); + return ret; + } + + dev_info(&pdev->dev, "Registered GCC clocks\n"); + + return ret; +} + +static struct platform_driver gcc_khaje_driver = { + .probe = gcc_khaje_probe, + .driver = { + .name = "gcc-khaje", + .of_match_table = gcc_khaje_match_table, + }, +}; + +static int __init gcc_khaje_init(void) +{ + return platform_driver_register(&gcc_khaje_driver); +} +subsys_initcall(gcc_khaje_init); + +static void __exit gcc_khaje_exit(void) +{ + platform_driver_unregister(&gcc_khaje_driver); +} +module_exit(gcc_khaje_exit); + +MODULE_DESCRIPTION("QTI GCC KHAJE Driver"); +MODULE_LICENSE("GPL v2"); From 386845a827cdb0c9d79811a381f066be7a262416 Mon Sep 17 00:00:00 2001 From: Madhuri Medasani Date: Tue, 18 May 2021 16:18:11 +0530 Subject: [PATCH 52/55] clk: qcom: gpucc: Add Graphics Clock controller for KHAJE Add support for Graphics clock controller clocks. Change-Id: Ie1324455e958bcd194e5e73bb8b62faf018b8d1a Signed-off-by: Madhuri Medasani --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-khaje.c | 491 +++++++++++++++++++++++++++++++++ 3 files changed, 500 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-khaje.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index ffd7b70bb234..76dab0c35515 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -616,3 +616,11 @@ config SM_GCC_KHAJE Support for the global clock controller on KHAJE devices. Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, UFS, SDCC, PCIe, Camera, Video etc. + +config SM_GPUCC_KHAJE + tristate "KHAJE Graphics Clock Controller" + select SM_GCC_KHAJE + help + Support for the graphics clock controller on Qualcomm Technologies, Inc + KHAJE devices. + Say Y if you want to support graphics controller devices. diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index c439648b2d8a..5307a0b51ee3 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -79,6 +79,7 @@ obj-$(CONFIG_SM_GCC_BENGAL) += gcc-bengal.o obj-$(CONFIG_SM_GCC_KHAJE) += gcc-khaje.o obj-$(CONFIG_SM_GCC_LITO) += gcc-lito.o obj-$(CONFIG_SM_GPUCC_BENGAL) += gpucc-bengal.o +obj-$(CONFIG_SM_GPUCC_KHAJE) += gpucc-khaje.o obj-$(CONFIG_SM_GPUCC_LITO) += gpucc-lito.o obj-$(CONFIG_SM_NPUCC_LITO) += npucc-lito.o obj-$(CONFIG_SM_VIDEOCC_LITO) += videocc-lito.o diff --git a/drivers/clk/qcom/gpucc-khaje.c b/drivers/clk/qcom/gpucc-khaje.c new file mode 100644 index 000000000000..d0d23b6f2147 --- /dev/null +++ b/drivers/clk/qcom/gpucc-khaje.c @@ -0,0 +1,491 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "vdd-level-bengal.h" + +#define CX_GMU_CBCR_SLEEP_MASK 0xf +#define CX_GMU_CBCR_SLEEP_SHIFT 4 +#define CX_GMU_CBCR_WAKE_MASK 0xf +#define CX_GMU_CBCR_WAKE_SHIFT 8 + +static DEFINE_VDD_REGULATORS(vdd_cx, VDD_HIGH_L1 + 1, 1, vdd_corner); +static DEFINE_VDD_REGULATORS(vdd_mx, VDD_HIGH_L1 + 1, 1, vdd_corner); + + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_2X_DIV_CLK_SRC, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL1_OUT_EVEN, + P_GPU_CC_PLL1_OUT_MAIN, + P_GPU_CC_PLL1_OUT_ODD, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const char * const gpu_cc_parent_names_0[] = { + "bi_tcxo", + "gpu_cc_pll0_out_main", + "gpu_cc_pll1", + "gpll0_out_main", + "gpll0_out_main_div", +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL0_2X_DIV_CLK_SRC, 2 }, + { P_GPU_CC_PLL1_OUT_EVEN, 3 }, + { P_GPU_CC_PLL1_OUT_ODD, 4 }, + { P_GPLL0_OUT_MAIN, 5 }, +}; + +static const char * const gpu_cc_parent_names_1[] = { + "bi_tcxo", + "gpu_cc_pll0_out_main", + "gpu_cc_pll0", + "gpu_cc_pll1", + "gpu_cc_pll1", + "gpll0_out_main", +}; + +static struct pll_vco lucid_vco[] = { + { 249600000, 2000000000, 0 }, +}; + +static struct pll_vco zonda_vco[] = { + { 595200000, 3600000000, 0 }, +}; + +/* 640MHz configuration */ +static const struct alpha_pll_config gpu_cc_pll0_config = { + .l = 0x21, + .alpha = 0x5555, + .config_ctl_val = 0x08200800, + .config_ctl_hi_val = 0x05022001, + .config_ctl_hi1_val = 0x00000010, + .user_ctl_val = 0x00000101, +}; + +static struct clk_alpha_pll gpu_cc_pll0 = { + .offset = 0x0, + .vco_table = zonda_vco, + .num_vco = ARRAY_SIZE(zonda_vco), + .flags = SUPPORTS_DYNAMIC_UPDATE, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll0", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_zonda_ops, + .vdd_class = &vdd_mx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 1800000000, + [VDD_LOW] = 2400000000, + [VDD_NOMINAL] = 3000000000, + [VDD_HIGH] = 3600000000}, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpu_cc_pll0_out_main[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_main = { + .offset = 0x0, + .post_div_shift = 8, + .post_div_table = post_div_table_gpu_cc_pll0_out_main, + .num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_main), + .width = 2, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA], + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll0_out_main", + .parent_names = (const char *[]){ "gpu_cc_pll0" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_zonda_ops, + }, +}; + +/* 690MHz configuration */ +static const struct alpha_pll_config gpu_cc_pll1_config = { + .l = 0x23, + .alpha = 0xF000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x329A299C, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll gpu_cc_pll1 = { + .offset = 0x100, + .vco_table = lucid_vco, + .num_vco = ARRAY_SIZE(lucid_vco), + .flags = SUPPORTS_DYNAMIC_UPDATE, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll1", + .parent_names = (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + .vdd_class = &vdd_mx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_MIN] = 615000000, + [VDD_LOW] = 1066000000, + [VDD_LOW_L1] = 1500000000, + [VDD_NOMINAL] = 1750000000, + [VDD_HIGH] = 2000000000}, + }, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x1120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .enable_safe_config = true, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gmu_clk_src", + .parent_names = gpu_cc_parent_names_0, + .num_parents = ARRAY_SIZE(gpu_cc_parent_names_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 200000000}, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { + F(320000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(465000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(600000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(785000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(820000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1025000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1114800000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { + .cmd_rcgr = 0x101c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk_src", + .parent_names = gpu_cc_parent_names_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_names_1), + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_ops, + .vdd_class = &vdd_cx, + .num_rate_max = VDD_NUM, + .rate_max = (unsigned long[VDD_NUM]) { + [VDD_LOWER] = 320000000, + [VDD_LOW] = 465000000, + [VDD_LOW_L1] = 600000000, + [VDD_NOMINAL] = 785000000, + [VDD_NOMINAL_L1] = 820000000, + [VDD_HIGH] = 1025000000, + [VDD_HIGH_L1] = 1114800000}, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x1078, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk = { + .halt_reg = 0x107c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x107c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_crc_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gfx3d_clk = { + .halt_reg = 0x10a4, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x10a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gfx3d_clk", + .parent_names = (const char *[]){ + "gpu_cc_gx_gfx3d_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x1098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gmu_clk", + .parent_names = (const char *[]){ + "gpu_cc_gmu_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { + .halt_reg = 0x108c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x108c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_snoc_dvm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk = { + .halt_reg = 0x1004, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x109c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x109c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gfx3d_clk = { + .halt_reg = 0x1054, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x1054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk", + .parent_names = (const char *[]){ + "gpu_cc_gx_gfx3d_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk = { + .halt_reg = 0x1090, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1090, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { + .halt_reg = 0x5000, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x5000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *gpu_cc_khaje_clocks[] = { + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, + [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr, + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, + [GPU_CC_PLL0_OUT_MAIN] = &gpu_cc_pll0_out_main.clkr, + [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, +}; + +static const struct regmap_config gpu_cc_khaje_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x7008, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpu_cc_khaje_desc = { + .config = &gpu_cc_khaje_regmap_config, + .clks = gpu_cc_khaje_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_khaje_clocks), +}; + +static const struct of_device_id gpu_cc_khaje_match_table[] = { + { .compatible = "qcom,khaje-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_khaje_match_table); + +static int gpu_cc_khaje_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + unsigned int value, mask; + int ret; + + vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx"); + if (IS_ERR(vdd_cx.regulator[0])) { + if (PTR_ERR(vdd_cx.regulator[0]) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get vdd_cx regulator\n"); + return PTR_ERR(vdd_cx.regulator[0]); + } + + vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx"); + if (IS_ERR(vdd_mx.regulator[0])) { + if (PTR_ERR(vdd_mx.regulator[0]) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get vdd_mx regulator\n"); + return PTR_ERR(vdd_mx.regulator[0]); + } + + regmap = qcom_cc_map(pdev, &gpu_cc_khaje_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* + * Keep the clock always-ON + * GPU_CC_GX_CXO_CLK + */ + regmap_update_bits(regmap, 0x1060, BIT(0), BIT(0)); + + clk_zonda_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); + clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); + + /* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */ + mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT; + mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT; + value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT; + regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg, + mask, value); + + ret = qcom_cc_really_probe(pdev, &gpu_cc_khaje_desc, regmap); + if (ret) { + dev_err(&pdev->dev, "Failed to register GPUCC clocks\n"); + return ret; + } + + dev_info(&pdev->dev, "Registered GPU CC clocks\n"); + + return ret; +} + +static struct platform_driver gpu_cc_khaje_driver = { + .probe = gpu_cc_khaje_probe, + .driver = { + .name = "gpu_cc-khaje", + .of_match_table = gpu_cc_khaje_match_table, + }, +}; + +static int __init gpu_cc_khaje_init(void) +{ + return platform_driver_register(&gpu_cc_khaje_driver); +} +subsys_initcall(gpu_cc_khaje_init); + +static void __exit gpu_cc_khaje_exit(void) +{ + platform_driver_unregister(&gpu_cc_khaje_driver); +} +module_exit(gpu_cc_khaje_exit); + +MODULE_DESCRIPTION("QTI GPU_CC KHAJE Driver"); +MODULE_LICENSE("GPL v2"); From 91b4e04be9b183fe1481ccada67f09aec08e0729 Mon Sep 17 00:00:00 2001 From: Ahmad Masri Date: Sun, 7 Mar 2021 13:06:08 +0200 Subject: [PATCH 53/55] wil6210: Drop unicast sub frame if part of a multicast amsdu Check that for a given multicast amsdu frame, all its sub frames are multicast also, if not, means if found a unicast sub frame, drop it and all the next sub frames for the same multicast amsdu. Change-Id: Ib9bcc45d9fcafec11c9c2a786fcabf278a666cb4 Signed-off-by: Ahmad Masri --- drivers/net/wireless/ath/wil6210/txrx_edma.c | 16 ++++++++++++++-- drivers/net/wireless/ath/wil6210/txrx_edma.h | 2 +- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/net/wireless/ath/wil6210/txrx_edma.c b/drivers/net/wireless/ath/wil6210/txrx_edma.c index 029ab790580f..9960a14e95f8 100644 --- a/drivers/net/wireless/ath/wil6210/txrx_edma.c +++ b/drivers/net/wireless/ath/wil6210/txrx_edma.c @@ -864,9 +864,20 @@ static int wil_check_amsdu(struct wil6210_priv *wil, void *msg, int cid, switch (vif->wdev.iftype) { case NL80211_IFTYPE_STATION: case NL80211_IFTYPE_P2P_CLIENT: + /* check if the MSDU (a sub-frame of AMSDU) is multicast */ if (is_multicast_ether_addr(da)) return 0; + /* check if the current AMSDU (MPDU) frame is a multicast. + * If so we have unicast sub frame as part of a multicast + * AMSDU. Current frame and all sub frames should be dropped. + */ + if (wil_rx_status_get_mcast(msg)) { + wil_dbg_txrx(wil, + "Found unicast sub frame in a multicast mpdu. Drop it\n"); + goto out; + } + /* On client side, DA should be the client mac address */ ndev = vif_to_ndev(vif); if (ether_addr_equal(ndev->dev_addr, da)) @@ -887,12 +898,13 @@ static int wil_check_amsdu(struct wil6210_priv *wil, void *msg, int cid, return 0; } +out: sta->amsdu_drop_sn = seq; sta->amsdu_drop_tid = tid; sta->amsdu_drop = 1; wil_dbg_txrx(wil, - "Drop AMSDU frame, sn=%d. Drop this and all next sub frames\n", - seq); + "Drop AMSDU frame, sn=%d tid=%d. Drop this and all next sub frames\n", + seq, tid); return -EAGAIN; } diff --git a/drivers/net/wireless/ath/wil6210/txrx_edma.h b/drivers/net/wireless/ath/wil6210/txrx_edma.h index f84832aeb867..75d658dc01bc 100644 --- a/drivers/net/wireless/ath/wil6210/txrx_edma.h +++ b/drivers/net/wireless/ath/wil6210/txrx_edma.h @@ -372,7 +372,7 @@ static inline u16 wil_rx_status_get_flow_id(void *msg) static inline u8 wil_rx_status_get_mcast(void *msg) { return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d0, - 26, 26); + 25, 26); } /** From debdfa5c6965373957b3bf353d47c51c59cb07a3 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Tue, 19 Jan 2021 09:53:27 +0530 Subject: [PATCH 54/55] msm: kgsl: Fix nr_removed calculation while reducing pools Current code is reducing total_pages by pcount for each loop iteration which results in decrementing total_pages incorrectly as pcount is total number of pages reduced in all previous iterations. Incorrect total_pages results in incorrect nr_removed. Fix this by not decrementing total_pages and directly accounting for already reduced pages in nr_removed calculation. Change-Id: I69485c26f1f98974eecc30caa1a888ddeafe7c73 Signed-off-by: Deepak Kumar --- drivers/gpu/msm/kgsl_pool.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/msm/kgsl_pool.c b/drivers/gpu/msm/kgsl_pool.c index 9c768458a7c7..ecb05b9b9a06 100644 --- a/drivers/gpu/msm/kgsl_pool.c +++ b/drivers/gpu/msm/kgsl_pool.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */ #include @@ -176,9 +176,7 @@ kgsl_pool_reduce(unsigned int target_pages, bool exit) if (!pool->allocation_allowed && !exit) continue; - total_pages -= pcount; - - nr_removed = total_pages - target_pages; + nr_removed = total_pages - target_pages - pcount; if (nr_removed <= 0) return pcount; From 14912426f6b99f08982ff6bfd5cb75315ec0fc45 Mon Sep 17 00:00:00 2001 From: Jilai Wang Date: Mon, 24 May 2021 09:57:25 -0400 Subject: [PATCH 55/55] msm: npu: Use spinlock for ipc write to avoid context switch Use a spinlock to prevent context switch while sending ipc command to firmware. Change-Id: Ie0066bc410c9c1bc153cf9959721493aebff0424 Signed-off-by: Jilai Wang --- drivers/media/platform/msm/npu/npu_common.h | 5 +++-- drivers/media/platform/msm/npu/npu_host_ipc.c | 8 ++++++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/msm/npu/npu_common.h b/drivers/media/platform/msm/npu/npu_common.h index 3538f762be28..d5be84b99b0c 100644 --- a/drivers/media/platform/msm/npu/npu_common.h +++ b/drivers/media/platform/msm/npu/npu_common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #ifndef _NPU_COMMON_H @@ -134,7 +134,7 @@ struct npu_mbox { }; /** - * struct npul_pwrlevel - Struct holding different pwrlevel info obtained from + * struct npu_pwrlevel - Struct holding different pwrlevel info obtained * from dtsi file * @pwr_level: NPU power level * @freq[]: NPU frequency vote in Hz @@ -246,6 +246,7 @@ struct mbox_bridge_data { struct npu_device { struct mutex dev_lock; + spinlock_t ipc_lock; struct platform_device *pdev; diff --git a/drivers/media/platform/msm/npu/npu_host_ipc.c b/drivers/media/platform/msm/npu/npu_host_ipc.c index 64d91d9d87e4..0787406a830a 100644 --- a/drivers/media/platform/msm/npu/npu_host_ipc.c +++ b/drivers/media/platform/msm/npu/npu_host_ipc.c @@ -74,6 +74,8 @@ static int npu_host_ipc_init_hfi(struct npu_device *npu_dev) uint32_t q_size = 0; uint32_t cur_start_offset = 0; + spin_lock_init(&npu_dev->ipc_lock); + reg_val = REGR(npu_dev, REG_NPU_FW_CTRL_STATUS); /* @@ -140,6 +142,7 @@ static int npu_host_ipc_init_hfi(struct npu_device *npu_dev) reg_val = REGR(npu_dev, (uint32_t)REG_NPU_HOST_CTRL_STATUS); REGW(npu_dev, (uint32_t)REG_NPU_HOST_CTRL_STATUS, reg_val | HOST_CTRL_STATUS_IPC_ADDRESS_READY_VAL); + return status; } @@ -149,13 +152,17 @@ static int npu_host_ipc_send_cmd_hfi(struct npu_device *npu_dev, int status = 0; uint8_t is_rx_req_set = 0; uint32_t retry_cnt = 5; + unsigned long flags; + spin_lock_irqsave(&npu_dev->ipc_lock, flags); status = ipc_queue_write(npu_dev, q_idx, (uint8_t *)cmd_ptr, &is_rx_req_set); if (status == -ENOSPC) { do { + spin_unlock_irqrestore(&npu_dev->ipc_lock, flags); msleep(20); + spin_lock_irqsave(&npu_dev->ipc_lock, flags); status = ipc_queue_write(npu_dev, q_idx, (uint8_t *)cmd_ptr, &is_rx_req_set); } while ((status == -ENOSPC) && (--retry_cnt > 0)); @@ -165,6 +172,7 @@ static int npu_host_ipc_send_cmd_hfi(struct npu_device *npu_dev, if (is_rx_req_set == 1) status = INTERRUPT_RAISE_NPU(npu_dev); } + spin_unlock_irqrestore(&npu_dev->ipc_lock, flags); if (status) NPU_ERR("Cmd Msg put on Command Queue - FAILURE\n");