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arm64: dts: sc7280: Add basic dts/dtsi files for SC7280 soc 
Add initial device tree support for the SC7280 SoC and the IDP
boards based on this SoC

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
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@intel-lab-lkp
Rajendra Nayak authored and intel-lab-lkp committed Feb 12, 2021
1 parent 8623e9e commit add6aba241bd502fd7c4b201016bd0b7a0d6d314
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1 arch/arm64/boot/dts/qcom/Makefile
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@@ -32,6 +32,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-kb.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb
47 arch/arm64/boot/dts/qcom/sc7280-idp.dts
View file
@@ -0,0 +1,47 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* sc7280 IDP board device tree source
*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/

/dts-v1/;

#include "sc7280.dtsi"

/ {
model = "Qualcomm Technologies, Inc. SC7280 IDP platform";
compatible = "qcom,sc7280-idp";

aliases {
serial0 = &uart5;
};

chosen {
stdout-path = "serial0:115200n8";
};
};

&qupv3_id_0 {
status = "okay";
};

&uart5 {
status = "okay";
};

/* PINCTRL - additions to nodes defined in sc7280.dtsi */

&qup_uart5_default {
tx {
pins = "gpio46";
drive-strength = <2>;
bias-disable;
};

rx {
pins = "gpio47";
drive-strength = <2>;
bias-pull-up;
};
};
294 arch/arm64/boot/dts/qcom/sc7280.dtsi
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@@ -0,0 +1,294 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* sc7280 SoC device tree source
*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/

#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
interrupt-parent = <&intc>;

#address-cells = <2>;
#size-cells = <2>;

chosen { };

clocks {
xo_board: xo-board {
compatible = "fixed-clock";
clock-frequency = <76800000>;
#clock-cells = <0>;
};

sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
#clock-cells = <0>;
};
};

cpus {
#address-cells = <2>;
#size-cells = <0>;

CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
};
};
};

CPU1: cpu@100 {
device_type = "cpu";
compatible = "arm,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_100>;
L2_100: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};

CPU2: cpu@200 {
device_type = "cpu";
compatible = "arm,kryo";
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&L2_200>;
L2_200: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};

CPU3: cpu@300 {
device_type = "cpu";
compatible = "arm,kryo";
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&L2_300>;
L2_300: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};

CPU4: cpu@400 {
device_type = "cpu";
compatible = "arm,kryo";
reg = <0x0 0x400>;
enable-method = "psci";
next-level-cache = <&L2_400>;
L2_400: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};

CPU5: cpu@500 {
device_type = "cpu";
compatible = "arm,kryo";
reg = <0x0 0x500>;
enable-method = "psci";
next-level-cache = <&L2_500>;
L2_500: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};

CPU6: cpu@600 {
device_type = "cpu";
compatible = "arm,kryo";
reg = <0x0 0x600>;
enable-method = "psci";
next-level-cache = <&L2_600>;
L2_600: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};

CPU7: cpu@700 {
device_type = "cpu";
compatible = "arm,kryo";
reg = <0x0 0x700>;
enable-method = "psci";
next-level-cache = <&L2_700>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
};

memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0 0x80000000 0 0>;
};

firmware {
scm {
compatible = "qcom,scm-sc7280", "qcom,scm";
};
};

psci {
compatible = "arm,psci-1.0";
method = "smc";
};

soc: soc {
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0 0 0 0x10 0>;
dma-ranges = <0 0 0 0 0x10 0>;
compatible = "simple-bus";

gcc: clock-controller@100000 {
compatible = "qcom,gcc-sc7280";
reg = <0 0x00100000 0 0x1f0000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};

qupv3_id_0: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x009c0000 0 0x2000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";

uart5: serial@994000 {
compatible = "qcom,geni-debug-uart";
reg = <0 0x00994000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};

tlmm: pinctrl@f100000 {
compatible = "qcom,sc7280-pinctrl";
reg = <0 0xf100000 0 0x1000000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 175>;

qup_uart5_default: qup-uart5-default {
pins = "gpio46", "gpio47";
function = "qup13";
};
};

intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
#size-cells = <2>;
ranges;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0 0x17a00000 0 0x10000>, /* GICD */
<0 0x17a60000 0 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;

gic-its@17a40000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0 0x17a40000 0 0x20000>;
status = "disabled";
};
};

timer@17c20000 {
#address-cells = <2>;
#size-cells = <2>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0 0x17c20000 0 0x1000>;

frame@17c21000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c21000 0 0x1000>,
<0 0x17c22000 0 0x1000>;
};

frame@17c23000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c23000 0 0x1000>;
status = "disabled";
};

frame@17c25000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c25000 0 0x1000>;
status = "disabled";
};

frame@17c27000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c27000 0 0x1000>;
status = "disabled";
};

frame@17c29000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c29000 0 0x1000>;
status = "disabled";
};

frame@17c2b000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c2b000 0 0x1000>;
status = "disabled";
};

frame@17c2d000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c2d000 0 0x1000>;
status = "disabled";
};
};
};

timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};

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