drm/i915: Move GT registers to their own header file

This is a huge, chaotic mass of registers copied over as-is without any
real cleanup.  We'll come back and organize these better, align on
consistent coding style, remove dead code, etc. in separate patches
later that will be easier to review.

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

@@ -7,8 +7,9 @@
 
 #include "gt/intel_context.h"
 #include "gt/intel_engine_user.h"
-#include "gt/intel_gt.h"
 #include "gt/intel_gpu_commands.h"
+#include "gt/intel_gt.h"
+#include "gt/intel_gt_regs.h"
 #include "gem/i915_gem_lmem.h"
 
 #include "selftests/igt_flush_test.h"

drivers/gpu/drm/i915/gt/gen6_ppgtt.c

@@ -9,6 +9,7 @@
 #include "i915_scatterlist.h"
 #include "i915_trace.h"
 #include "i915_vgpu.h"
+#include "intel_gt_regs.h"
 #include "intel_engine_regs.h"
 #include "intel_gt.h"
 

drivers/gpu/drm/i915/gt/gen7_renderclear.c

@@ -6,6 +6,7 @@
 #include "gen7_renderclear.h"
 #include "i915_drv.h"
 #include "intel_gpu_commands.h"
+#include "intel_gt_regs.h"
 
 #define GT3_INLINE_DATA_DELAYS 0x1E00
 #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS))

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

@@ -5,8 +5,9 @@
 
 #include "gen8_engine_cs.h"
 #include "i915_drv.h"
-#include "intel_lrc.h"
 #include "intel_gpu_commands.h"
+#include "intel_gt_regs.h"
+#include "intel_lrc.h"
 #include "intel_ring.h"
 
 int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)

drivers/gpu/drm/i915/gt/intel_engine_cs.c

@@ -6,6 +6,7 @@
 #include <drm/drm_print.h>
 
 #include "gem/i915_gem_context.h"
+#include "gt/intel_gt_regs.h"
 
 #include "i915_cmd_parser.h"
 #include "i915_drv.h"

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

@@ -122,6 +122,7 @@
 #include "intel_gt.h"
 #include "intel_gt_irq.h"
 #include "intel_gt_pm.h"
+#include "intel_gt_regs.h"
 #include "intel_gt_requests.h"
 #include "intel_lrc.h"
 #include "intel_lrc_reg.h"

drivers/gpu/drm/i915/gt/intel_ggtt.c

@@ -15,6 +15,7 @@
 #include "gem/i915_gem_lmem.h"
 
 #include "intel_gt.h"
+#include "intel_gt_regs.h"
 #include "i915_drv.h"
 #include "i915_scatterlist.h"
 #include "i915_vgpu.h"

drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c

@@ -7,6 +7,7 @@
 #include "i915_scatterlist.h"
 #include "i915_pvinfo.h"
 #include "i915_vgpu.h"
+#include "intel_gt_regs.h"
 
 /**
  * DOC: fence register handling

drivers/gpu/drm/i915/gt/intel_gt.c

@@ -16,6 +16,7 @@
 #include "intel_gt_buffer_pool.h"
 #include "intel_gt_clock_utils.h"
 #include "intel_gt_pm.h"
+#include "intel_gt_regs.h"
 #include "intel_gt_requests.h"
 #include "intel_migrate.h"
 #include "intel_mocs.h"

drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c

@@ -6,6 +6,7 @@
 #include "i915_drv.h"
 #include "intel_gt.h"
 #include "intel_gt_clock_utils.h"
+#include "intel_gt_regs.h"
 
 static u32 read_reference_ts_freq(struct intel_uncore *uncore)
 {

drivers/gpu/drm/i915/gt/intel_gt_irq.c

@@ -10,7 +10,7 @@
 #include "intel_breadcrumbs.h"
 #include "intel_gt.h"
 #include "intel_gt_irq.h"
-#include "intel_lrc_reg.h"
+#include "intel_gt_regs.h"
 #include "intel_uncore.h"
 #include "intel_rps.h"
 #include "pxp/intel_pxp_irq.h"

drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c

@@ -12,6 +12,7 @@
 #include "intel_gt_debugfs.h"
 #include "intel_gt_pm.h"
 #include "intel_gt_pm_debugfs.h"
+#include "intel_gt_regs.h"
 #include "intel_llc.h"
 #include "intel_pcode.h"
 #include "intel_rc6.h"

drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c

@@ -8,6 +8,7 @@
 #include "intel_gt.h"
 #include "intel_gt_irq.h"
 #include "intel_gt_pm_irq.h"
+#include "intel_gt_regs.h"
 
 static void write_pm_imr(struct intel_gt *gt)
 {