Biju-Das/Add-R…
Commits on Jan 12, 2022
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arm64: dts: renesas: rzg2l-smarc: Enable Display on carrier board
Enable display interface on RZ/G2L SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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arm64: dts: renesas: r9a07g044: Link DSI with DU node
Link DSI with DU node to SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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arm64: dts: renesas: r9a07g044: Add dsi node
Add dsi node to SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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arm64: dts: renesas: r9a07g044: Add DU node
Add DU node to SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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arm64: dts: renesas: r9a07g044: Add vspd node
Add vspd node to SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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arm64: dts: renesas: r9a07g044: Add fcpvd node
Add fcpvd node to SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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drm: rcar-du: Add RZ/G2L DSI driver
This driver supports the MIPI DSI encoder found in the RZ/G2L SoC. It currently supports DSI mode only. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings
The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It can operate in DSI mode, with up to four data lanes. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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media: vsp1: Add support for the RZ/G2L VSPD
The RZ/G2L VSPD provides a single VSPD instance. it has the following sub modules MAU, CTU, RPF, DPR, LUT, BRS, WPF and LIF. It does not have version register, so added a new compatible string to match to get the version value. Also the reset is shared with DU module. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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media: dt-bindings: media: renesas,vsp1: Document RZ/{G2L,V2L} VSPD b…
…indings Document VSPD found in RZ/G2L and RZ/V2L family SoC's. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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drm: rcar-du: Add RZ/G2L LCDC Support
The LCD controller is composed of Frame Compression Processor (FCPVD), Video Signal Processor (VSPD), and Display Unit (DU). It has DPI/DSI interfaces and supports a maximum resolution of 1080p along with 2 rpf's to support blending of two picture layers and raster operations (ROPs). A feature bit for RZ/G2L SoC is introduced to support RZ/G2L with the rest of the SoC supported by this driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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dt-bindings: display: renesas, du: Document r9a07g044l bindings
Extend the Renesas DU display bindings to support the r9a07g044l RZ/G2L. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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drm: rcar-du: Allow DU group feature based on feature bit
RZ/G2L LCDC does not have DU group registers. This patch allows accessing DU group registers for SoC's with group feature bit is set. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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drm: rcar_du: Add RCAR_DU_FEATURE_GROUP feature bit
R-Car has supports DU groups in DU HW, where as it is not supported in RZ/G2L. Add RCAR_DU_FEATURE_GROUP feature bit to support RZ/G2L. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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drm: rcar-du: Allow DU plane feature based on DU feature bit
RZ/G2L LCDC does not have DU plane registers. This patch supports DU planes only for the SoC's with plane feature bit is set. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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drm: rcar-du: Add RCAR_DU_FEATURE_PLANE feature bit
DU plane registers are available on R-Car, but it is not present on RZ/G2L. Add RCAR_DU_FEATURE_PLANE feature bit to support later SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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drm: rcar-du: Add max_width and max_height to struct rcar_du_device_info
There are some differences related to max frame size supported by different R-Car/RZ-G family of SoC's Max frame size supported by R-Car Gen1 & R-Car Gen2 is 4095x2047 Max frame size supported by R-Car Gen3 is 8190x8190 Max frame size supported by RZ/G2L is 1920x1080 Add max_width and max_height to struct rcar_du_device_info to support later SoC without any code changes. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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drm: rcar-du: Add num_rpf to struct rcar_du_device_info
Number of RPF's VSP is different on R-Car and RZ/G2L R-Car Gen3 -> 5 RPF's R-Car Gen2 -> 4 RPF's RZ/G2L -> 2 RPF's Add num_rpf to struct rcar_du_device_info to support later SoC without any code changes. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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drm: rcar-du: of: Increase buff size for compatible variable
Increase buff size for compatible variable to avoid stack corruption with RZ/G2L SoC's(renesas,du-r9a07g044l) which requires a buff size more than the current allocated size. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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clk: renesas: r9a07g044: Add DSI clock and reset entries
Add DSI clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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clk: renesas: r9a07g044: Add LCDC clock and reset entries
Add LCDC clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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clk: renesas: r9a07g044: Add M4 Clock support
Add support for M4 clock which is sourced from pll2_533_div2. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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clk: renesas: r9a07g044: Add M3 Clock support
Add support for M3 clock which is sourced from DSI divider connected to PLL5_4 mux. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support
Add support for {M2, M2_DIV2} clocks which is sourced from pll3_533. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> -
clk: renesas: r9a07g044: Add M1 clock support
Add support for M1 clock which is sourced from FOUTPOSTDIV. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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clk: renesas: rzg2l: Add DSI divider clk support
M3 clock is sourced from DSI Dividers(DSIDIVA and DSIDIVB) This patch uses the LUT to set the divider values for DSI/DPI mode on various frequencies defined in LUT. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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clk: renesas: rzg2l: Add PLL5_4 clk mux support
Add PLL5_4 clk mux support to select clock from different clock sources FOUTPOSTDIV and FOUT1PH0. This patch uses the LUT to select the source based on DSI/DPI mode and frequencies. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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clk: renesas: rzg2l: Add FOUTPOSTDIV clk support
PLL5 generates FOUTPOSTDIV clk and is sourced by LCDC/DSI modules. The FOUTPOSTDIV is connected to PLL5_4 MUX. Video clock is sourced from DSI divider which is connected to PLL5_4 MUX. Added 2 LUT's for generating FOUTPOSTDIV, 1 for DSI mode and other for DPI mode as it requires different parameters for generating the video clock. The LUT supports minimal set of frequency used by commonly used resolutions. This patch uses the above LUT to generate the required video clock by matching the frequency value in LUT with FOUTPOSTDIV/DSI_DIV. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
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Add linux-next specific files for 20220112
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
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mm: hide the FRONTSWAP Kconfig symbol
Select FRONTSWAP from ZSWAP instead of prompting for it. Link: https://lkml.kernel.org/r/20211224062246.1258487-14-hch@lst.de Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Juergen Gross <jgross@suse.com> Cc: Dan Streetman <ddstreet@ieee.org> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Hugh Dickins <hughd@google.com> Cc: Konrad Rzeszutek Wilk <Konrad.wilk@oracle.com> Cc: Matthew Wilcox (Oracle) <willy@infradead.org> Cc: Seth Jennings <sjenning@redhat.com> Cc: Vitaly Wool <vitaly.wool@konsulko.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
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frontswap: remove support for multiple ops
There is only a single instance of frontswap ops in the kernel, so simplify the frontswap code by removing support for multiple operations. Link: https://lkml.kernel.org/r/20211224062246.1258487-13-hch@lst.de Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Juergen Gross <jgross@suse.com> Cc: Dan Streetman <ddstreet@ieee.org> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Hugh Dickins <hughd@google.com> Cc: Konrad Rzeszutek Wilk <Konrad.wilk@oracle.com> Cc: Matthew Wilcox (Oracle) <willy@infradead.org> Cc: Seth Jennings <sjenning@redhat.com> Cc: Vitaly Wool <vitaly.wool@konsulko.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
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mm: mark swap_lock and swap_active_head static
swap_lock and swap_active_head are only used in swapfile.c, so mark them static. Link: https://lkml.kernel.org/r/20211224062246.1258487-12-hch@lst.de Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Juergen Gross <jgross@suse.com> Cc: Dan Streetman <ddstreet@ieee.org> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Hugh Dickins <hughd@google.com> Cc: Konrad Rzeszutek Wilk <Konrad.wilk@oracle.com> Cc: Matthew Wilcox (Oracle) <willy@infradead.org> Cc: Seth Jennings <sjenning@redhat.com> Cc: Vitaly Wool <vitaly.wool@konsulko.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
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frontswap: simplify frontswap_register_ops
Given that frontswap_register_ops must be called from built-in code, there is no need to handle the case of swapfiles coming online before or during it, so delete the code that deals with that case. Link: https://lkml.kernel.org/r/20211224062246.1258487-11-hch@lst.de Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Juergen Gross <jgross@suse.com> Cc: Dan Streetman <ddstreet@ieee.org> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Hugh Dickins <hughd@google.com> Cc: Konrad Rzeszutek Wilk <Konrad.wilk@oracle.com> Cc: Matthew Wilcox (Oracle) <willy@infradead.org> Cc: Seth Jennings <sjenning@redhat.com> Cc: Vitaly Wool <vitaly.wool@konsulko.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
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frontswap: remove frontswap_test
frontswap_test is unused now, remove it. Link: https://lkml.kernel.org/r/20211224062246.1258487-10-hch@lst.de Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Juergen Gross <jgross@suse.com> Cc: Dan Streetman <ddstreet@ieee.org> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Hugh Dickins <hughd@google.com> Cc: Konrad Rzeszutek Wilk <Konrad.wilk@oracle.com> Cc: Matthew Wilcox (Oracle) <willy@infradead.org> Cc: Seth Jennings <sjenning@redhat.com> Cc: Vitaly Wool <vitaly.wool@konsulko.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>