Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Move clock parent tables down, after the GPLL declrataions, so that we
can use gpll hw clock fields in the next commit.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>

In preparation of updating the msm8996 gcc driver, drop all unsupported
GPLL sources (gpll1/gpll1_early_div, gpll2/gpll2_early and gpll3).
Downstream kernel also does not provide support for these GPLL sources,
so it is safe to drop them.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

If all parents are specified as clk_hw, we can use parent_hws instead of
parent_data.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>

Convert the clock driver to specify parent hws/data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

…ents

Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Move clock parent tables down, after the PLL declrataions, so that we
can use pll hw clock fields in the next commit.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

The test clock isn't in the bindings and apparently it's not used by
anyone upstream.  Remove it.

Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>

If all parents are specified as clk_hw, we can use parent_hws instead of
parent_data.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>

The test clock isn't in the bindings and apparently it's not used by
anyone upstream.  Remove it.

Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

…ents

Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

If all parents are specified as clk_hw, we can use parent_hws instead of
parent_data.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>

The test clock isn't in the bindings and apparently it's not used by
anyone upstream.  Remove it.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>

Two clocks are still using parent_names, use parent_hws instead.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

* clk-debugfs:
  clk: Emit a stern warning with writable debugfs enabled
  clk: Add write operation for clk_parent debugfs node

We don't want vendors to be enabling this part of the clk code and
shipping it to customers. Exposing the ability to change clk frequencies
and parents via debugfs is potentially damaging to the system if folks
don't know what they're doing. Emit a strong warning so that the message
is clear: don't enable this outside of development systems.

Fixes: 37215da ("clk: Add support for setting clk_rate via debugfs")
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20211210014237.2130300-1-sboyd@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Useful for testing mux clocks. One can write the index of the parent to
be set into clk_parent node, starting from 0. Example

    # cd /sys/kernel/debug/clk/mout_peri_bus
    # cat clk_possible_parents
      dout_shared0_div4 dout_shared1_div4
    # cat clk_parent
      dout_shared0_div4
    # echo 1 > clk_parent
    # cat clk_parent
      dout_shared1_div4

CLOCK_ALLOW_WRITE_DEBUGFS has to be defined in drivers/clk/clk.c in
order to use this feature.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Link: https://lore.kernel.org/r/20211013172042.10884-1-semen.protsenko@linaro.org
[sboyd@kernel.org: Collapse ifdefs]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

* clk-cleanup:
  clk: __clk_core_init() never takes NULL
  clk: clk_core_get() can also return NULL
  clk/ti/adpll: Make const pointer error a static const array

The only caller of __clk_core_init() allocates the pointer and checks
the allocation for NULL so this check is impossible. Remove it.

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20211208041534.3928718-2-sboyd@kernel.org

Nothing stops a clk controller from registering an OF clk provider
before registering those clks with the clk framework. This is not great
but we deal with it in the clk framework by refusing to hand out struct
clk pointers when 'hw->core' is NULL, the indication that clk_register()
has been called.

Within clk_core_fill_parent_index() we considered this case when a
clk_hw pointer is referenced directly by filling in the parent cache
with an -EPROBE_DEFER pointer when the core pointer is NULL. When we
lookup a parent with clk_core_get() we don't care about the return value
being NULL though, because that was considered largely impossible, but
it's been proven now that it can be NULL if two clk providers are
probing in parallel and the parent provider has been registered before
the clk has. Let's check for NULL here as well and treat it the same as
direct clk_hw references.

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20211208041534.3928718-1-sboyd@kernel.org

Make const pointer error a static const array, removes a dereference
and shrinks object code a little.

Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Link: https://lore.kernel.org/r/20211127173036.150535-1-colin.i.king@gmail.com
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

* clk-at91:
  clk: lan966x: Extend lan966x clock driver for clock gating support
  dt-bindings: clock: lan966x: Extend includes with clock gates
  dt-bindings: clock: lan966x: Extend for clock gate support
  clk: gate: Add devm_clk_hw_register_gate()
  clk: lan966x: Add lan966x SoC clock driver
  dt-bindings: clock: lan966x: Add LAN966X Clock Controller
  dt-bindings: clock: lan966x: Add binding includes for lan966x SoC clock IDs

…l/git/at91/linux into clk-at91

Pull AT91 clk driver updates from Nicolas Ferre:

 - Lan966x Generic Clock Controller driver and associated DT bindings
 - Lan966x clock driver extended to support clock gating

* tag 'clk-at91-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  clk: lan966x: Extend lan966x clock driver for clock gating support
  dt-bindings: clock: lan966x: Extend includes with clock gates
  dt-bindings: clock: lan966x: Extend for clock gate support
  clk: gate: Add devm_clk_hw_register_gate()
  clk: lan966x: Add lan966x SoC clock driver
  dt-bindings: clock: lan966x: Add LAN966X Clock Controller
  dt-bindings: clock: lan966x: Add binding includes for lan966x SoC clock IDs

Extend the clock driver to add support also for clock gating. The
following peripherals can be gated: UHPHS, UDPHS, MCRAMC, HMATRIX.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20211103085102.1656081-5-horatiu.vultur@microchip.com

On lan966x it is allow to control the clock to some peripherals like
USB. So extend the include file with these clocks.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20211103085102.1656081-4-horatiu.vultur@microchip.com

Allow to add an optional resource to be able to access the clock gate
registers.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20211103085102.1656081-3-horatiu.vultur@microchip.com

Add devm_clk_hw_register_gate() - devres-managed version of
clk_hw_register_gate()

Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20211103085102.1656081-2-horatiu.vultur@microchip.com

This adds Generic Clock Controller driver for lan966x SoC.

Lan966x clock controller contains 3 PLLs - cpu_clk, ddr_clk
and sys_clk. It generates and supplies clock to various
peripherals within SoC.
Register settings required to provide GCK clocking to a
peripheral is as below:
GCK_SRC_SEL     = Select clock source.
GCK_PRESCALER   = Set divider value.
GCK_ENA         = 1 - Enable GCK clock.

Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
Co-developed-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20211103061935.25677-4-kavyasree.kotagiri@microchip.com

This adds the DT bindings documentation for lan966x SoC
generic clock controller.

Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20211103061935.25677-3-kavyasree.kotagiri@microchip.com

…ck IDs

LAN966X supports 14 clock outputs for its peripherals.
This include file is introduced to use identifiers for clocks.

Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20211103061935.25677-2-kavyasree.kotagiri@microchip.com

* clk-renesas: (24 commits)
  clk: renesas: r9a07g044: Add TSU clock and reset entry
  mmc: renesas_sdhi: Simplify an expression
  mmc: renesas_sdhi: Use devm_clk_get_optional() to obtain CD clock
  dt-bindings: clock: renesas,cpg-mssr: Document r8a779f0
  clk: renesas: cpg-mssr: propagate return value of_genpd_add_provider_simple()
  clk: renesas: cpg-mssr: Check return value of pm_genpd_init()
  clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple()
  clk: renesas: rzg2l: Check return value of pm_genpd_init()
  clk: renesas: r9a07g044: Add RSPI clock and reset entries
  clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV
  clk: renesas: rzg2l: Add CPG_PL1_DDIV macro
  mmc: renesas_sdhi: Parse DT for SDnH
  mmc: renesas_sdhi: Use dev_err_probe when getting clock fails
  clk: renesas: rcar-gen3: Remove outdated SD_SKIP_FIRST
  clk: renesas: rcar-gen3: Switch to new SD clock handling
  mmc: renesas_sdhi: Flag non-standard SDnH handling for V3M
  clk: renesas: r8a779a0: Add SDnH clock to V3U
  clk: renesas: rcar-gen3: Add SDnH clock
  clk: renesas: rcar-gen3: Add dummy SDnH clock
  clk: renesas: r9a07g044: Add OSTM clock and reset entries
  ...

…m/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add serial (SCI1), watchdog (WDT), timer (OSTM), SPI (RSPI), and
   thermal (TSU) clocks and resets on RZ/G2L
 - Rework SDHI clock handling in the R-Car Gen3 and RZ/G2 clock
   drivers, and in the Renesas SDHI driver
 - Make the Cortex-A55 (I) clock on RZ/G2L programmable,
 - Document support for the new R-Car S4-8 (R8A779F0) SoC
 - Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v5.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (24 commits)
  clk: renesas: r9a07g044: Add TSU clock and reset entry
  mmc: renesas_sdhi: Simplify an expression
  mmc: renesas_sdhi: Use devm_clk_get_optional() to obtain CD clock
  dt-bindings: clock: renesas,cpg-mssr: Document r8a779f0
  clk: renesas: cpg-mssr: propagate return value of_genpd_add_provider_simple()
  clk: renesas: cpg-mssr: Check return value of pm_genpd_init()
  clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple()
  clk: renesas: rzg2l: Check return value of pm_genpd_init()
  clk: renesas: r9a07g044: Add RSPI clock and reset entries
  clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV
  clk: renesas: rzg2l: Add CPG_PL1_DDIV macro
  mmc: renesas_sdhi: Parse DT for SDnH
  mmc: renesas_sdhi: Use dev_err_probe when getting clock fails
  clk: renesas: rcar-gen3: Remove outdated SD_SKIP_FIRST
  clk: renesas: rcar-gen3: Switch to new SD clock handling
  mmc: renesas_sdhi: Flag non-standard SDnH handling for V3M
  clk: renesas: r8a779a0: Add SDnH clock to V3U
  clk: renesas: rcar-gen3: Add SDnH clock
  clk: renesas: rcar-gen3: Add dummy SDnH clock
  clk: renesas: r9a07g044: Add OSTM clock and reset entries
  ...

* clk-fixes:
  clk: Don't parent clks until the parent is fully registered
  clk: versatile: clk-icst: use after free on error path
  clk: qcom: sm6125-gcc: Swap ops of ice and apps on sdcc1

Before commit fc0c209 ("clk: Allow parents to be specified without
string names") child clks couldn't find their parent until the parent
clk was added to a list in __clk_core_init(). After that commit, child
clks can reference their parent clks directly via a clk_hw pointer, or
they can lookup that clk_hw pointer via DT if the parent clk is
registered with an OF clk provider.

The common clk framework treats hw->core being non-NULL as "the clk is
registered" per the logic within clk_core_fill_parent_index():

	parent = entry->hw->core;
	/*
	 * We have a direct reference but it isn't registered yet?
	 * Orphan it and let clk_reparent() update the orphan status
	 * when the parent is registered.
	 */
	if (!parent)

Therefore we need to be extra careful to not set hw->core until the clk
is fully registered with the clk framework. Otherwise we can get into a
situation where a child finds a parent clk and we move the child clk off
the orphan list when the parent isn't actually registered, wrecking our
enable accounting and breaking critical clks.

Consider the following scenario:

  CPU0                                     CPU1
  ----                                     ----
  struct clk_hw clkBad;
  struct clk_hw clkA;

  clkA.init.parent_hws = { &clkBad };

  clk_hw_register(&clkA)                   clk_hw_register(&clkBad)
   ...                                      __clk_register()
					     hw->core = core
					     ...
   __clk_register()
    __clk_core_init()
     clk_prepare_lock()
     __clk_init_parent()
      clk_core_get_parent_by_index()
       clk_core_fill_parent_index()
        if (entry->hw) {
	 parent = entry->hw->core;

At this point, 'parent' points to clkBad even though clkBad hasn't been
fully registered yet. Ouch! A similar problem can happen if a clk
controller registers orphan clks that are referenced in the DT node of
another clk controller.

Let's fix all this by only setting the hw->core pointer underneath the
clk prepare lock in __clk_core_init(). This way we know that
clk_core_fill_parent_index() can't see hw->core be non-NULL until the
clk is fully registered.

Fixes: fc0c209 ("clk: Allow parents to be specified without string names")
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
Link: https://lore.kernel.org/r/20211109043438.4639-1-quic_mdtipton@quicinc.com
[sboyd@kernel.org: Reword commit text, update comment]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>