Do a fix to rockchip io-domain, follow this orders:

* system running state
  -> io-domain vsel to 3.3V (actually is done by pre-disable)
    -> regulator_enable
      -> vsel change according to regulator voltage

* system running state
  -> io-domain vsel to 3.3V
    -> regulator_disable

Found on some Rockchip SoCs, the regulator enable or disable without
care about the io-domain maybe caused soc damaged.

Tested on RV1126 EVB.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

…b1-v10

Since the EMMC pins can be used for other functions as well, we need to
configure the pinctrl.

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20210805120107.27007-8-michael.riesch@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Add the SD card reader to the device tree of the RK3568 EVB1.

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20210805120107.27007-7-michael.riesch@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Add the regulators of the RK809 PMIC to the device tree of the
RK3568 EVB1.

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20210805120107.27007-6-michael.riesch@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Enable the PMU IO domains in the device tree for the RK3568 EVB1.

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20210805120107.27007-5-michael.riesch@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Enable the PMU IO domains for the RK3566 and the RK3568.

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20210805120107.27007-4-michael.riesch@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

The io-domain registers on RK3568 SoCs have three separated bits to
enable/disable the 1.8v/2.5v/3.3v power.

This patch make the write to be a operation, allow rk3568 uses a private
register set function.

Since the 2.5v mode hasn't been fully validated yet, the driver only sets
1.8v [enable] + 3.3v [disable] for 1.8v mode
1.8v [disable] + 3.3v [enable] for 3.3v mode

There is not register order requirement which has been cleared by our IC
team.

For future reference the full usage matrix including the 2.5V setting is:
case  V33  V25  V18  result
0     0    0    0    IO safe, but cannot work
1     0    0    1    IO require 1.8V, should < 1.98V, otherwise IO may damage
2     0    1    0    IO require 2.5V, should < 2.75V, otherwise IO may damage
3     0    1    1    Invalid state, should avoid
4     1    0    0    IO require 3.3V, should < 3.63V, otherwise IO may damage
5     1    0    1    IO require 1.8V, should < 1.98V, otherwise IO may damage
6     1    1    0    IO require 2.5V, should < 2.75V, otherwise IO may damage
7     1    1    1    Invalid state, should avoid

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
[added mode clarification from Jay]
Link: https://lore.kernel.org/r/20210805120107.27007-3-michael.riesch@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Add binding for the RK3568 along a SoC-specific description of
voltage supplies.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
[add soc-specific section]
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210805120107.27007-2-michael.riesch@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

The rockpro64 had a fan node since
commit 5882d65 ("arm64: dts: rockchip: Add PWM fan for RockPro64")
however it was never tied into the thermal driver for automatic control.

Add the links to the thermal node to permit the kernel to handle this
automatically.
Borrowed from the (rk3399-khadas-edge.dtsi).

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20210730151727.729822-1-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

…k Pro

Some chargers try to put the charged device into device data
role. Before this commit this condition caused the tcpm state machine to
issue a hard reset due to a capability missmatch.

Signed-off-by: Dan Johansen <strit@manjaro.org>
Link: https://lore.kernel.org/r/20210805220426.2693062-1-strit@manjaro.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Dumo is another variant of Scarlet, also known as the ASUS Chromebook
Tablet CT100. This is almost the same as Scarlet-Innolux, but uses a
board-specific calibration variant for the WiFi module.

Add a new device tree for it.

Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210812094753.2359087-3-wenst@chromium.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Dumo is another variant of Scarlet, also known as the ASUS Chromebook
Tablet CT100. This is almost the same as Scarlet-Innolux, but uses a
specific calibration variant for the WiFi module.

Add an entry for the board compatibles.

Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210812094753.2359087-2-wenst@chromium.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Currently, no driver support for DDR memory controller (DMC) is present,
as a result, no driver is explicitly consuming the ddrphy clock. This means
that VPLL1 (parent of ddr clock) will be shutdown if we enable
and then disable any child clock of VPLL1 (e.g. SCLK_I2S0_8CH_TX).
If VPLL1 is disabled, the whole system will freeze, because the DDR
controller will lose its clock. So, it's necessary to prevent VPLL1 from
shutting down, by marking the ddrphy4x CLK_IS_CRITICAL.

This bug was discovered when I was porting rockchip_i2s_tdm driver to
mainline kernel from Rockchip 4.4 kernel. I guess that other Rockchip
SoCs without DMC driver may need the same patch. If this applies to
other devices, please let us know.

Signed-off-by: Yunhao Tian <t123yh@outlook.com>
Link: https://lore.kernel.org/r/BYAPR20MB24886765F888A9705CBEB70789E39@BYAPR20MB2488.namprd20.prod.outlook.com
[adapted subject, changed to add the clock to the critical list]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20210729093913.8917-3-michael.riesch@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

While both RK3566 and RK3568 feature the gmac1 node, the gmac0
node is exclusive to the RK3568.

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Link: https://lore.kernel.org/r/20210729093913.8917-2-michael.riesch@wolfvision.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Enable the gmac controller on the Pine64 Quartz64 Model A.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20210728180034.717953-8-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

The rk3568 gpll should run at 1200mhz and the ppll should run at 200mhz.
These are set incorrectly by the bootloader, so fix them here.

gpll boots at 1188mhz, but to get most accurate dividers for all
gpll_dividers it needs to run at 1200mhz, otherwise everyone downstream
isn't quite right.

ppll feeds the combophys, which has a divide by 2 clock, so 200mhz is
required to reach a 100mhz clock input for them.

The vendor-kernel also makes this fix.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
[pulled deeper explanation from discussion into commit message]
Link: https://lore.kernel.org/r/20210728180034.717953-7-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Add the gmac1 controller to the rk356x device tree.
This is the controller common to both the rk3568 and rk3566.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20210728180034.717953-5-pgwipeout@gmail.com
[adjusted sorting a bit]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

The mbi-alias incorrectly points to 0xfd100000 when it should point to
0xfd410000.
This fixes MSIs on rk3568.

Fixes: a3adc0b ("arm64: dts: rockchip: add core dtsi for RK3568 SoC")
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20210728180034.717953-2-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

The rk3036/rk3328 pll types were converted to checking the lock status
via the internal register in january 2020, so don't need the grf
reference since then.

But it was forgotten to remove grf check when deciding between the
pll rate ops (read-only vs. read-write), so a clock driver without
the needed grf reference might've been put into the read-only mode
just because the grf reference was missing.

This affected the rk356x that needs to reclock certain plls at boot.

Fix this by removing the check for the grf for selecting the utilized
operations.

Suggested-by: Heiko Stuebner <heiko@sntech.de>
Fixes: 7f6ffbb ("clk: rockchip: convert rk3036 pll type to use internal lock status")
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
[adjusted the commit message, adjusted the fixes tag]
Link: https://lore.kernel.org/r/20210728180034.717953-3-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

The PX30 has a VPU (both decoder and encoder) with a dedicated IOMMU.
Describe these two entities in device-tree.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Link: https://lore.kernel.org/r/20210728230040.17368-1-ezequiel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Add the watchdog node to rk3568.

Signed-off-by: Liang Chen <cl@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20210622102907.99242-2-heiko@sntech.de

ISP1 is supplied by the tx1rx1 dphy, that is controlled from
inside the dsi1 controller, so include the necessary phy-link
for it.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Tested-by: Sebastian Fricke <sebastian.fricke@posteo.net>
Acked-by: Helen Koike <helen.koike@collabora.com>
Link: https://lore.kernel.org/r/20210210111020.2476369-7-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

This enables variant a of the clkout signal for camera applications
and also the cifclkin pinctrl setting.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Tested-by: Sebastian Fricke <sebastian.fricke@posteo.net>
Acked-by: Helen Koike <helen.koike@collabora.com>
Link: https://lore.kernel.org/r/20210210111020.2476369-6-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

The dsi controller includes access to the dphy which might be used
not only for dsi output but also for csi input on dsi1, so add the
necessary #phy-cells to allow it to be used as phy.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Tested-by: Sebastian Fricke <sebastian.fricke@posteo.net>
Acked-by: Helen Koike <helen.koike@collabora.com>
Link: https://lore.kernel.org/r/20210210111020.2476369-5-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>