When a specific x8 CEM card is bifurcated into x4x4 mode, and the
upstream ports both support hotplugging on each respective x4 device, a
slot management system for the CEM card requires both x4 devices to be
sysfs removed from the OS before it can safely turn-off physical power.
The implications are that Slot Control will display Powered Off status
for the device where the device is actually powered until both ports
have powered off.

When power is removed from the first half, real power and link remains
active while waiting for the second half to have power removed. When
power is then removed from the second half, the first half starts
shutdown sequence and will trigger a DLLSC event. This is misinterpreted
as an enabling event and causes the first half to be re-enabled.

The spurious enable can be resolved by ignoring link status change
events when no link is active when in the off state. This patch adds a
quirk for the card.

Acked-by: Jon Derrick <jonathan.derrick@intel.com>
Signed-off-by: James Puthukattukaran <james.puthukattukaran@oracle.com>

- Zero-initialize pcitest param to avoid random "-d" setting (Shunyong
  Yang)

* remotes/lorenzo/pci/tools:
  tools: PCI: Zero-initialize param

- Make ixp4xx driver depend on ARCH_IXP4XX (Geert Uytterhoeven)

* remotes/lorenzo/pci/misc:
  PCI: controller: PCI_IXP4XX should depend on ARCH_IXP4XX

- Add max-virtual-functions to endpoint binding (Kishon Vijay Abraham I)

- Add pci_epf_add_vepf() API to add virtual function to endpoint (Kishon
  Vijay Abraham I)

- Add pci_epf_vepf_link() to link virtual function to endpoint physical
  function (Kishon Vijay Abraham I)

- Add virtual function number to pci_epc_ops endpoint ops interfaces
  (Kishon Vijay Abraham I)

- Simplify register base address computation for endpoint BAR configuration
  (Kishon Vijay Abraham I)

- Add support to configure virtual functions in cadence endpoint driver
  (Kishon Vijay Abraham I)

- Add SR-IOV configuration to endpoint test driver (Kishon Vijay Abraham I)

- Document configfs usage to create virtual functions for endpoints (Kishon
  Vijay Abraham I)

* remotes/lorenzo/pci/endpoint:
  Documentation: PCI: endpoint/pci-endpoint-cfs: Guide to use SR-IOV
  misc: pci_endpoint_test: Populate sriov_configure ops to configure SR-IOV device
  PCI: cadence: Add support to configure virtual functions
  PCI: cadence: Simplify code to get register base address for configuring BAR
  PCI: endpoint: Add virtual function number in pci_epc ops
  PCI: endpoint: Add support to link a physical function to a virtual function
  PCI: endpoint: Add support to add virtual function in endpoint core
  dt-bindings: PCI: pci-ep: Add binding to specify virtual function

- Document optional clock DT property (Michal Simek)

- Enable PCIe ref clock (Hyun Kwon)

* remotes/lorenzo/pci/xilinx-nwl:
  PCI: xilinx-nwl: Enable the clock through CCF
  dt-bindings: pci: xilinx-nwl: Document optional clock property

- Remove redundant dev_err() after devm_ioremap_resource() (ErKun Yang)

* remotes/lorenzo/pci/xgene:
  PCI: xgene-msi: Remove redundant dev_err() call in xgene_msi_probe()

- Fix handling BME_CHGED event (Om Prakash Singh)

- Fix MSI-X programming (Om Prakash Singh)

- Disable interrupts before entering L2 (Om Prakash Singh)

- Don't allow suspend when Tegra PCIe is in EP mode (Om Prakash Singh)

* remotes/lorenzo/pci/tegra194:
  PCI: tegra194: Cleanup unused code
  PCI: tegra194: Don't allow suspend when Tegra PCIe is in EP mode
  PCI: tegra194: Disable interrupts before entering L2
  PCI: tegra194: Fix MSI-X programming
  PCI: tegra194: Fix handling BME_CHGED event

- Remove unused struct tegra_pcie_bus (Krzysztof Wilczyński)

* remotes/lorenzo/pci/tegra:
  PCI: tegra: make const array err_msg static
  PCI: tegra: Use 'seq_puts' instead of 'seq_printf'
  PCI: tegra: Fix OF node reference leak
  PCI: tegra: Remove unused struct tegra_pcie_bus

- Fix runtime PM imbalance in rcar_pcie_ep_probe() (Dinghao Liu)

* remotes/lorenzo/pci/rcar:
  PCI: rcar: Add L1 link state fix into data abort hook
  PCI: rcar: Fix runtime PM imbalance in rcar_pcie_ep_probe()

- Split DT bindings for PCIe controllers with independent MSI domains into
  separate nodes for MT2712/MT7622 (Chuanjia Liu)

- Locate shared registers from "mediatek,generic-pciecfg" property, pay
  attention to ""linux,pci-domain" property,  use "interrupt-names" and
  "pcie_irq" to fix MSI issue (Chuanjia Liu)

* remotes/lorenzo/pci/mediatek:
  dt-bindings: PCI: mediatek: Update the Device tree bindings

- Don't fail devm_pci_alloc_host_bridge() on missing 'ranges' (Rob Herring)

- Fix BCMA probe resource handling (Rob Herring)

* remotes/lorenzo/pci/iproc:
  PCI: iproc: Fix BCMA probe resource handling
  PCI: of: Don't fail devm_pci_alloc_host_bridge() on missing 'ranges'

- Support Hyper-V Create Interrupt v3 message (Sunil Muthuswamy)

* remotes/lorenzo/pci/hv:
  PCI: hv: Support for create interrupt v3

- Remove surplus break statements (Krzysztof Wilczyński)

- Add Rockchip RK356X host controller driver (Simon Xue)

* remotes/lorenzo/pci/dwc:
  PCI: rockchip-dwc: Add Rockchip RK356X host controller driver
  PCI: dwc: Remove surplus break statement after return
  PCI: artpec6: Remove local code block from within switch statement
  PCI: artpec6: Remove surplus break statement after return

- Convert bool in structs to bitfield (Kishon Vijay Abraham I)

- Work around J7200 non-PCIe SERDES lane electrical issue that prevents
  PCIe link training (Nadeem Athani)

- Add J7200 PCIe support to j721e (Kishon Vijay Abraham I)

- Add AM64 PCIe support to j721e (Kishon Vijay Abraham I)

- Add J7200 and AM64 device IDs to endpoint test (Kishon Vijay Abraham I)

* remotes/lorenzo/pci/cadence:
  misc: pci_endpoint_test: Add deviceID for AM64 and J7200
  PCI: j721e: Add PCIe support for AM64
  PCI: j721e: Add PCIe support for J7200
  PCI: cadence: Add quirk flag to set minimum delay in LTSSM Detect.Quiet state
  PCI: cadence: Use bitfield for *quirk_retrain_flag* instead of bool

- Fix PIO config access status checking (Evan Wang)

- Increase config access polling delay to 1.5s (Pali Rohár)

- Add PCIe Root Capabilities to bridge emulation (Pali Rohár)

- Report Config Request Retry Status when Software Visibility enabled (Pali
  Rohár)

* remotes/lorenzo/pci/aardvark:
  PCI: aardvark: Configure PCIe resources from 'ranges' DT property
  PCI: aardvark: Fix reporting CRS value
  PCI: pci-bridge-emul: Add PCIe Root Capabilities Register
  PCI: aardvark: Increase polling delay to 1.5s while waiting for PIO response
  PCI: aardvark: Fix checking for PIO status

- Add pci_numachip_init() declaration (Krzysztof Wilczyński)

- Allocate pci_dev_str_match_path() string atomically (Dan Carpenter)

* pci/misc:
  PCI: Fix pci_dev_str_match_path() alloc while atomic bug
  x86/PCI: Add pci_numachip_init() declaration

- Check Resource Item Names against those defined for type (Bjorn Helgaas)

- Treat initial 0xff as missing EEPROM (Heiner Kallweit)

- Reject resource tags with invalid size (Bjorn Helgaas)

- Don't check Large Resource Item Names for validity (Bjorn Helgaas)

- Allow access to valid parts of VPD if some is invalid (Bjorn Helgaas)

- Remove pci_vpd_size() old_size argument (Heiner Kallweit)

- Make pci_vpd_wait() uninterruptible (Heiner Kallweit)

- Remove struct pci_vpd.flag (Heiner Kallweit)

- Remove struct pci_vpd_ops (Heiner Kallweit)

- Remove struct pci_vpd.valid member (Heiner Kallweit)

- Embed struct pci_vpd in struct pci_dev (Heiner Kallweit)

- Determine VPD size in pci_vpd_init() (Heiner Kallweit)

- Treat invalid VPD like missing VPD capability (Heiner Kallweit)

* pci/vpd:
  PCI/VPD: Treat invalid VPD like missing VPD capability
  PCI/VPD: Determine VPD size in pci_vpd_init()
  PCI/VPD: Embed struct pci_vpd in struct pci_dev
  PCI/VPD: Remove struct pci_vpd.valid member
  PCI/VPD: Remove struct pci_vpd_ops
  PCI/VPD: Reorder pci_read_vpd(), pci_write_vpd()
  PCI/VPD: Remove struct pci_vpd.flag
  PCI/VPD: Make pci_vpd_wait() uninterruptible
  PCI/VPD: Remove pci_vpd_size() old_size argument
  PCI/VPD: Allow access to valid parts of VPD if some is invalid
  PCI/VPD: Don't check Large Resource Item Names for validity
  PCI/VPD: Reject resource tags with invalid size
  PCI/VPD: Treat initial 0xff as missing EEPROM
  PCI/VPD: Check Resource Item Names against those valid for type
  PCI/VPD: Correct diagnostic for VPD read failure

- Add ACS quirks for NXP LX2xx0 and LX2xx2 platforms (Wasim Khan)

- Enforce pci=noats with Transaction Blocking (Alex Williamson)

* pci/virtualization:
  PCI/ACS: Enforce pci=noats with Transaction Blocking
  PCI: Add ACS quirks for NXP LX2xx0 and LX2xx2 platforms

- Refactor pci_ioremap_bar() and pci_ioremap_wc_bar() (Krzysztof
  Wilczyński)

* pci/resource:
  PCI: Refactor pci_ioremap_bar() and pci_ioremap_wc_bar()

- Convert irq_find_mapping() + generic_handle_irq() to
  generic_handle_domain_irq() (Marc Zyngier)

* pci/irq:
  PCI: Bulk conversion to generic_handle_domain_irq()

- Call Max Payload Size-related fixup quirks early, so they're considered
  by pci_configure_mps() (Marek Behún)

- Restrict Max Payload Size Supported to work around ASMedia ASM1062 SATA
  erratum (Marek Behún)

- Return ~0 data on pciconfig_read() CAP_SYS_ADMIN failure (Krzysztof
  Wilczyński)

* pci/enumeration:
  PCI: Return int from pciconfig_read() syscall
  PCI: Return ~0 data on pciconfig_read() CAP_SYS_ADMIN failure
  PCI: Restrict ASMedia ASM1062 SATA Max Payload Size Supported
  PCI: Call Max Payload Size-related fixup quirks early

In commit 6df6ba9 ("PCI: aardvark: Remove PCIe outbound window
configuration") was removed aardvark PCIe outbound window configuration and
commit description said that was recommended solution by HW designers.

But that commit completely removed support for configuring PCIe IO
resources without removing PCIe IO 'ranges' from DTS files. After that
commit PCIe IO space started to be treated as PCIe MEM space and accessing
it just caused kernel crash.

Moreover implementation of PCIe outbound windows prior that commit was
incorrect. It completely ignored offset between CPU address and PCIe bus
address and expected that in DTS is CPU address always same as PCIe bus
address without doing any checks. Also it completely ignored size of every
PCIe resource specified in 'ranges' DTS property and expected that every
PCIe resource has size 128 MB (also for PCIe IO range). Again without any
check. Apparently none of PCIe resource has in DTS specified size of 128
MB. So it was completely broken and thanks to how aardvark mask works,
configuration was completely ignored.

This patch reverts back support for PCIe outbound window configuration but
implementation is a new without issues mentioned above. PCIe outbound
window is required when DTS specify in 'ranges' property non-zero offset
between CPU and PCIe address space. To address recommendation by HW
designers as specified in commit description of 6df6ba9, set default
outbound parameters as PCIe MEM access without translation and therefore
for this PCIe 'ranges' it is not needed to configure PCIe outbound window.
For PCIe IO space is needed to configure aardvark PCIe outbound window.

This patch fixes kernel crash when trying to access PCIe IO space.

Link: https://lore.kernel.org/r/20210624215546.4015-2-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: stable@vger.kernel.org # 6df6ba9 ("PCI: aardvark: Remove PCIe outbound window configuration")

Add device ID specific to AM64 and J7200 in pci_endpoint_test so that
endpoints configured with those deviceIDs can use pci_endpoint_test
driver.

Link: https://lore.kernel.org/r/20210811123336.31357-6-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

AM64 has the same PCIe IP as in J7200 with certain erratas not
applicable (quirk_detect_quiet_flag). Add support for "ti,am64-pcie-host"
compatible and "ti,am64-pcie-ep" compatible that is specific to AM64.

Link: https://lore.kernel.org/r/20210811123336.31357-5-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

J7200 has the same PCIe IP as in J721E with minor changes in the
wrapper. J7200 allows byte access of bridge configuration space
registers and the register field for LINK_DOWN interrupt is different.
J7200 also requires "quirk_detect_quiet_flag" to be set. Configure these
changes as part of driver data applicable only to J7200.

Link: https://lore.kernel.org/r/20210811123336.31357-4-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

…et state

PCIe fails to link up if SERDES lanes not used by PCIe are assigned to
another protocol. For example, link training fails if lanes 2 and 3 are
assigned to another protocol while lanes 0 and 1 are used for PCIe to
form a two lane link. This failure is due to an incorrect tie-off on an
internal status signal indicating electrical idle.

Status signals going from SERDES to PCIe Controller are tied-off when a
lane is not assigned to PCIe. Signal indicating electrical idle is
incorrectly tied-off to a state that indicates non-idle. As a result,
PCIe sees unused lanes to be out of electrical idle and this causes
LTSSM to exit Detect.Quiet state without waiting for 12ms timeout to
occur. If a receiver is not detected on the first receiver detection
attempt in Detect.Active state, LTSSM goes back to Detect.Quiet and
again moves forward to Detect.Active state without waiting for 12ms as
required by PCIe base specification. Since wait time in Detect.Quiet is
skipped, multiple receiver detect operations are performed back-to-back
without allowing time for capacitance on the transmit lines to
discharge. This causes subsequent receiver detection to always fail even
if a receiver gets connected eventually.

Add a quirk flag "quirk_detect_quiet_flag" to program the minimum
time the LTSSM should wait on entering Detect.Quiet state here.
This has to be set for J7200 as it has an incorrect tie-off on unused
lanes.

Link: https://lore.kernel.org/r/20210811123336.31357-3-kishon@ti.com
Signed-off-by: Nadeem Athani <nadeem@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

No functional change. As we are intending to add additional 1-bit
members in struct j721e_pcie_data/struct cdns_pcie_rc, use bitfields
instead of bool since it takes less space. As discussed in [1],
the preference is to use bitfileds instead of bool inside structures.

[1] -> https://lore.kernel.org/linux-fsdevel/CA+55aFzKQ6Pj18TB8p4Yr0M4t+S+BsiHH=BJNmn=76-NcjTj-g@mail.gmail.com/

Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20210811123336.31357-2-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Add Documentation to help users use PCI endpoint to create virtual
functions using configfs. An endpoint function is designated as a
virtual endpoint function device when it is linked to a physical
endpoint function device (instead of a endpoint controller).

Link: https://lore.kernel.org/r/20210819123343.1951-9-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

…-IOV device

Populate sriov_configure ops with pci_sriov_configure_simple to
configure SR-IOV device.

Link: https://lore.kernel.org/r/20210819123343.1951-8-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Now that support for SR-IOV is added in PCIe endpoint core, add support
to configure virtual functions in the Cadence PCIe EP driver.

Link: https://lore.kernel.org/r/20210819123343.1951-7-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

…ing BAR

No functional change. Simplify code to get register base address for
configuring PCI BAR.

Link: https://lore.kernel.org/r/20210819123343.1951-6-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Add virtual function number in pci_epc ops. EPC controller driver
can perform virtual function specific initialization based on the
virtual function number.

Link: https://lore.kernel.org/r/20210819123343.1951-5-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

…unction

While the physical function has to be linked to endpoint controller, the
virtual function has to be linked to a physical function. Add support to
link a physical function to a virtual function in pci-ep-cfs.

Link: https://lore.kernel.org/r/20210819123343.1951-4-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Add support to add virtual function in endpoint core. The virtual
function can only be associated with a physical function instead of a
endpoint controller. Provide APIs to associate a virtual function with
a physical function here.

[weiyongjun1@huawei.com: PCI: endpoint: Fix missing unlock on error in
 pci_epf_add_vepf() - Reported-by: Hulk Robot <hulkci@huawei.com>]

Link: https://lore.kernel.org/r/20210819123343.1951-3-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

Add binding to specify virtual function (associated with each physical
function) in endpoint mode.

Link: https://lore.kernel.org/r/20210819123343.1951-2-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>