Add myself as the maintainer of DRM bridge drivers for i.MX SoCs.

Signed-off-by: Liu Ying <victor.liu@nxp.com>

This patch adds a drm bridge driver for i.MX8qm LVDS display bridge(LDB)
which is officially named as pixel mapper.  The LDB has two channels.
Each of them supports up to 30bpp parallel input color format and can
map the input to VESA or JEIDA standards.  The two channels can be used
simultaneously, either in dual mode or split mode.  In dual mode, the
two channels output identical data.  In split mode, channel0 outputs
odd pixels and channel1 outputs even pixels.  This patch supports the
LDB single mode and split mode.

Signed-off-by: Liu Ying <victor.liu@nxp.com>

This patch adds a drm bridge driver for i.MX8qxp LVDS display bridge(LDB)
which is officially named as pixel mapper.  The LDB has two channels.
Each of them supports up to 24bpp parallel input color format and can map
the input to VESA or JEIDA standards.  The two channels cannot be used
simultaneously, that is to say, the user should pick one of them to use.
Two LDB channels from two LDB instances can work together in LDB split
mode to support a dual link LVDS display.  The channel indexes have to be
different.  Channel0 outputs odd pixels and channel1 outputs even pixels.
This patch supports the LDB single mode and split mode.

Signed-off-by: Liu Ying <victor.liu@nxp.com>

…ding

This patch adds bindings for i.MX8qm/qxp LVDS display bridge(LDB).

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Liu Ying <victor.liu@nxp.com>

This patch adds a helper to support LDB drm bridge drivers for
i.MX SoCs.  Helper functions supported by this helper should
implement common logics for all LDB modules embedded in i.MX SoCs.

Signed-off-by: Liu Ying <victor.liu@nxp.com>

This patch adds a drm bridge driver for i.MX8qxp pixel link to display
pixel interface(PXL2DPI).  The PXL2DPI interfaces the pixel link 36-bit
data output and the DSI controller’s MIPI-DPI 24-bit data input, and
inputs of LVDS Display Bridge(LDB) module used in LVDS mode, to remap
the pixel color codings between those modules. The PXL2DPI is purely
combinatorial.

Signed-off-by: Liu Ying <victor.liu@nxp.com>

This patch adds bindings for i.MX8qxp pixel link to DPI(PXL2DPI).

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Liu Ying <victor.liu@nxp.com>

… binding

This patch adds bindings for i.MX8qm/qxp Control and Status Registers module.

Signed-off-by: Liu Ying <victor.liu@nxp.com>

This patch adds a drm bridge driver for i.MX8qm/qxp display pixel link.
The pixel link forms a standard asynchronous linkage between
pixel sources(display controller or camera module) and pixel
consumers(imaging or displays).  It consists of two distinct
functions, a pixel transfer function and a control interface.

Reviewed-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Liu Ying <victor.liu@nxp.com>

This patch adds bindings for i.MX8qm/qxp display pixel link.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Liu Ying <victor.liu@nxp.com>

This patch adds a drm bridge driver for i.MX8qm/qxp pixel combiner.
The pixel combiner takes two output streams from a single display
controller and manipulates the two streams to support a number
of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured
as either one screen, two screens, or virtual screens.  The pixel
combiner is also responsible for generating some of the control signals
for the pixel link output channel.  For now, the driver only supports
the bypass mode.

Reviewed-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Liu Ying <victor.liu@nxp.com>

This patch adds bindings for i.MX8qm/qxp pixel combiner.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Liu Ying <victor.liu@nxp.com>

This patch adds documentations for RGB666_1X30_CPADLO, RGB888_1X30_CPADLO,
RGB666_1X36_CPADLO and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp
pixel combiner.  The RGB pixels with padding low per component are
transmitted on a 30-bit input bus(10-bit per component) from a display
controller or a 36-bit output bus(12-bit per component) to a pixel link.

Reviewed-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>

This patch adds RGB666_1X30_CPADLO, RGB888_1X30_CPADLO, RGB666_1X36_CPADLO
and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp pixel combiner.
The RGB pixels with padding low per component are transmitted on a 30-bit
input bus(10-bit per component) from a display controller or a 36-bit
output bus(12-bit per component) to a pixel link.

Reviewed-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>

The imx6ul-evk board designer took the bad decision to tie the
two Ethernet PHY reset lines together. This prevents one Ethernet
interface to work while the other one is brought down. For example:

 # ifconfig eth0 down
 # [  279.386551] fec 2188000.ethernet eth1: Link is Down

Bringing eth0 interface down also causes eth1 to be down.

The Ethernet reset lines comes from the IO expander and both come in
logic level 0 by default.

To fix this issue, remove the Ethernet PHY reset descriptions from
its respective PHY nodes and force both Ethernet PHY lines to be at
logic level 1 via gpio-hog.

Fixes: 2db7e78 ("ARM: dts: imx6ul-14x14-evk: Describe the KSZ8081 reset")
Reported-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

With the first redesign the debug UART had changed from
UART2 to UART1.
As the first hardware revision is considered as alpha and
will not be supported in future. The old setup will not
be preserved.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add missing pinctrl-names for i2c gpio recovery mode.

Fixes: 88f7f6b ("arm64: dts: freescale: Add support for phyBOARD-Pollux-i.MX8MP")
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Reorder flexspi clock-names entry to make it compliant with bindings.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Reorder flexspi clock-names entry to make it compliant with bindings.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

disable-gpio' and 'power-on-gpio' are not valid properties
according to Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt.

Remove the unsupported properties.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Bruno Thomsen <bruno.thomsen@gmail.com>
Reviewed-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Remove the unnecessary #address-cells/#size-cells to avoid warnings
from W=1 build like this:

arch/arm/boot/dts/imx6qdl-gw52xx.dtsi:33.12-78.4: Warning (avoid_unnecessary_addr_size): /gpio-keys: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
[fabio: Make the warning messages more succint]
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Remove the unnecessary #address-cells/#size-cells and rename the node
names to fix the following W=1 dtc warnings:

arch/arm/boot/dts/imx6dl-plybas.dts:26.13-30.5: Warning (unit_address_vs_reg): /gpio_keys/button@20: node has a unit name, but no reg or ranges property
arch/arm/boot/dts/imx6dl-plybas.dts:32.13-36.5: Warning (unit_address_vs_reg): /gpio_keys/button@21: node has a unit name, but no reg or ranges property
arch/arm/boot/dts/imx6dl-plybas.dts:20.12-37.4: Warning (avoid_unnecessary_addr_size): /gpio_keys: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Define GPIO line names for b450v3, b650v3, and b850v3.

Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Explicitly mark I2C GPIOs as open drain to fix the following
kernel message being printed:

enforced open drain please flag it properly in DT/ACPI DSDT/board file

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add PHY voltage supply information fixing the following kernel message:

2188000.ethernet supply phy not found, using dummy regulator

Also add PHY clock information to avoid depending on the bootloader
programming correct values.

The bootloader also sets some reserved registers in the PHY as
advised by Qualcomm, which is not supported by the bindings/kernel
driver, so the reset GPIO has not been added intentionally.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add VBUS regulator GPIO information, so that USB OTG port can
also be used in host mode.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Crypto engine (CAAM) on LS1021A platform is configured HW-coherent,
mark accordingly the DT node.

Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The current setting reflects about 86 Ohms of source-impedance
on the SDIO signals where the WiFi board is hooked up. PCB traces are
routed with 50 Ohms impedance and there are no serial resistors on
those traces.

This commit changes the source-impedance to 52 Ohms to better match our
hardware design.

The impedances given in this commit message refer to 3.3V operation.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Move the "hog" pins to the corresponding pin groups for SPI, ENET, PMIC,
LEDs, so that these pins can be used for different purposes when the
respective drivers are disabled.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>