{"payload":{"header_redesign_enabled":false,"results":[{"id":"213581391","archived":false,"color":"#b2b7f8","followers":3,"has_funding_file":false,"hl_name":"16oh4/FPGA-VLSI","hl_trunc_description":"A collection of designs for FPGA's at RTL level as well as integrated circuits with Cadence Encounter and Virtuoso.","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":213581391,"name":"FPGA-VLSI","owner_id":37783822,"owner_login":"16oh4","updated_at":"2019-12-11T23:44:06.847Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":82,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253A16oh4%252FFPGA-VLSI%2B%2Blanguage%253AVerilog","metadata":null,"warn_limited_results":false,"csrf_tokens":{"/16oh4/FPGA-VLSI/star":{"post":"deXMR-EdHFxXrtyq0bpPi7J2DnXGKzuQpZKGjUR3OZWzBQ_6h0XQbTGsW9wofE1tnkFphQZsCJkKWewId6_07Q"},"/16oh4/FPGA-VLSI/unstar":{"post":"JnV2uMcXIOIfe3_UNBy_L6Rfi99vnefyLNoLb7qQUvd2XhoZ1OxQSzx6j98LTt6qMCRA8_5zfWcQL8fu_xtuuQ"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"m0NP31C0_7JUtPvUDk2EkWtxw7FjyyYqT76MAgrePclD7RaSX7hrL3IvGlimz0nkRYcfh-o3I073gFnCnjnqGw"}}},"title":"Repository search results"}