From 9e95d86ba663ccabdba2e3ee513407cd06cdf961 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 12 Sep 2025 13:31:55 +0800 Subject: [PATCH 01/22] Revert "FROMLIST: riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0" This reverts commit 38b23f5fd0bd3caaff92e2913586dcfb8c2ccf3f. --- arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts index 5df5a37045e6a7..7001d8ffdc3e04 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts @@ -152,18 +152,6 @@ }; }; -&pcie_rc0 { - status = "okay"; -}; - -&pcie_rc1 { - status = "okay"; -}; - -&pcie_rc2 { - status = "okay"; -}; - &pinctrl { emmc_cfg: sdhci-emmc-cfg { sdhci-emmc-wp-pins { From ae4fc9bcac53b3c36f52dc4d9ce51c02befbcd5c Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 12 Sep 2025 13:31:58 +0800 Subject: [PATCH 02/22] Revert "FROMLIST: riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X" This reverts commit a9cf8fdb61edac47bdf0b44c6efd4b2b8b06a84e. --- arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts index bc82afab63da23..d447d66177ee5c 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts @@ -164,18 +164,6 @@ }; }; -&pcie_rc0 { - status = "okay"; -}; - -&pcie_rc1 { - status = "okay"; -}; - -&pcie_rc2 { - status = "okay"; -}; - &pinctrl { emmc_cfg: sdhci-emmc-cfg { sdhci-emmc-wp-pins { From 207bb21df7d4936cbb25db1bcaee0d6f3fedd83f Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 12 Sep 2025 13:31:59 +0800 Subject: [PATCH 03/22] Revert "FROMLIST: riscv: sophgo: dts: enable PCIe for PioneerBox" This reverts commit ae976e5ac75386991d030f1f199d836e226d2dce. --- arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index 452d5f23b5784a..554ec14d58453a 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -128,18 +128,6 @@ }; }; -&pcie_rc0 { - status = "okay"; -}; - -&pcie_rc2 { - status = "okay"; -}; - -&pcie_rc3 { - status = "okay"; -}; - &sd { pinctrl-0 = <&sd_cfg>; pinctrl-names = "default"; From 7ad6d81fa4f69aa6a1690fec5a5492c92ca34367 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 12 Sep 2025 13:32:01 +0800 Subject: [PATCH 04/22] Revert "FROMLIST: riscv: sophgo: dts: add PCIe controllers for SG2042" This reverts commit 09fb5b7f06020674afafe4bac1adc9a025e53098. --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 88 -------------------------- 1 file changed, 88 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index caad6117845c13..0a31957d69ba16 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -264,94 +264,6 @@ #clock-cells = <1>; }; - pcie_rc0: pcie@7060000000 { - compatible = "sophgo,sg2042-pcie-host"; - device_type = "pci"; - reg = <0x70 0x60000000 0x0 0x00800000>, - <0x40 0x00000000 0x0 0x00001000>; - reg-names = "reg", "cfg"; - linux,pci-domain = <0>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000>, - <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, - <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, - <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, - <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; - bus-range = <0x0 0xff>; - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; - msi-parent = <&msi>; - status = "disabled"; - }; - - pcie_rc1: pcie@7060800000 { - compatible = "sophgo,sg2042-pcie-host"; - device_type = "pci"; - reg = <0x70 0x60800000 0x0 0x00800000>, - <0x44 0x00000000 0x0 0x00001000>; - reg-names = "reg", "cfg"; - linux,pci-domain = <1>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0xc0400000 0x44 0xc0400000 0x0 0x00400000>, - <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, - <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, - <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, - <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; - bus-range = <0x0 0xff>; - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; - msi-parent = <&msi>; - status = "disabled"; - }; - - pcie_rc2: pcie@7062000000 { - compatible = "sophgo,sg2042-pcie-host"; - device_type = "pci"; - reg = <0x70 0x62000000 0x0 0x00800000>, - <0x48 0x00000000 0x0 0x00001000>; - reg-names = "reg", "cfg"; - linux,pci-domain = <2>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0xc0800000 0x48 0xc0800000 0x0 0x00400000>, - <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, - <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, - <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, - <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; - bus-range = <0x0 0xff>; - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; - msi-parent = <&msi>; - status = "disabled"; - }; - - pcie_rc3: pcie@7062800000 { - compatible = "sophgo,sg2042-pcie-host"; - device_type = "pci"; - reg = <0x70 0x62800000 0x0 0x00800000>, - <0x4c 0x00000000 0x0 0x00001000>; - reg-names = "reg", "cfg"; - linux,pci-domain = <3>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0xc0c00000 0x4c 0xc0c00000 0x0 0x00400000>, - <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, - <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, - <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, - <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; - bus-range = <0x0 0xff>; - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; - msi-parent = <&msi>; - status = "disabled"; - }; - clint_mswi: interrupt-controller@7094000000 { compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; reg = <0x00000070 0x94000000 0x00000000 0x00004000>; From 219a53b0d2744d5d54fe67d5f4ca0684e65d47c0 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 12 Sep 2025 13:32:03 +0800 Subject: [PATCH 05/22] Revert "FROMLIST: PCI: sg2042: Add Sophgo SG2042 PCIe driver" This reverts commit 4b3a42f1166624bae0a7861c632afc2403793ceb. --- drivers/pci/controller/cadence/Kconfig | 10 -- drivers/pci/controller/cadence/Makefile | 1 - drivers/pci/controller/cadence/pcie-sg2042.c | 104 ------------------- 3 files changed, 115 deletions(-) delete mode 100644 drivers/pci/controller/cadence/pcie-sg2042.c diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig index 02a639e55fd8cf..666e16b6367f14 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -42,15 +42,6 @@ config PCIE_CADENCE_PLAT_EP endpoint mode. This PCIe controller may be embedded into many different vendors SoCs. -config PCIE_SG2042_HOST - tristate "Sophgo SG2042 PCIe controller (host mode)" - depends on OF && (ARCH_SOPHGO || COMPILE_TEST) - select PCIE_CADENCE_HOST - help - Say Y here if you want to support the Sophgo SG2042 PCIe platform - controller in host mode. Sophgo SG2042 PCIe controller uses Cadence - PCIe core. - config PCI_J721E tristate select PCIE_CADENCE_HOST if PCI_J721E_HOST != n @@ -76,5 +67,4 @@ config PCI_J721E_EP Say Y here if you want to support the TI J721E PCIe platform controller in endpoint mode. TI J721E PCIe controller uses Cadence PCIe core. - endmenu diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile index 5e23f8539ecc12..9bac5fb2f13dad 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -4,4 +4,3 @@ obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) += pci-j721e.o -obj-$(CONFIG_PCIE_SG2042_HOST) += pcie-sg2042.o diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c deleted file mode 100644 index c026e1ca5d6e3f..00000000000000 --- a/drivers/pci/controller/cadence/pcie-sg2042.c +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * pcie-sg2042 - PCIe controller driver for Sophgo SG2042 SoC - * - * Copyright (C) 2025 Sophgo Technology Inc. - * Copyright (C) 2025 Chen Wang - */ - -#include -#include -#include -#include - -#include "pcie-cadence.h" - -/* - * SG2042 only supports 4-byte aligned access, so for the rootbus (i.e. to - * read/write the Root Port itself, read32/write32 is required. For - * non-rootbus (i.e. to read/write the PCIe peripheral registers, supports - * 1/2/4 byte aligned access, so directly using read/write should be fine. - */ - -static struct pci_ops sg2042_pcie_root_ops = { - .map_bus = cdns_pci_map_bus, - .read = pci_generic_config_read32, - .write = pci_generic_config_write32, -}; - -static struct pci_ops sg2042_pcie_child_ops = { - .map_bus = cdns_pci_map_bus, - .read = pci_generic_config_read, - .write = pci_generic_config_write, -}; - -static int sg2042_pcie_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct pci_host_bridge *bridge; - struct cdns_pcie *pcie; - struct cdns_pcie_rc *rc; - int ret; - - bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); - if (!bridge) { - dev_err_probe(dev, -ENOMEM, "Failed to alloc host bridge!\n"); - return -ENOMEM; - } - - bridge->ops = &sg2042_pcie_root_ops; - bridge->child_ops = &sg2042_pcie_child_ops; - - rc = pci_host_bridge_priv(bridge); - pcie = &rc->pcie; - pcie->dev = dev; - - platform_set_drvdata(pdev, pcie); - - pm_runtime_set_active(dev); - pm_runtime_no_callbacks(dev); - devm_pm_runtime_enable(dev); - - ret = cdns_pcie_init_phy(dev, pcie); - if (ret) { - dev_err_probe(dev, ret, "Failed to init phy!\n"); - return ret; - } - - ret = cdns_pcie_host_setup(rc); - if (ret) { - dev_err_probe(dev, ret, "Failed to setup host!\n"); - cdns_pcie_disable_phy(pcie); - return ret; - } - - return 0; -} - -static void sg2042_pcie_remove(struct platform_device *pdev) -{ - struct cdns_pcie *pcie = platform_get_drvdata(pdev); - - cdns_pcie_disable_phy(pcie); -} - -static const struct of_device_id sg2042_pcie_of_match[] = { - { .compatible = "sophgo,sg2042-pcie-host" }, - {}, -}; -MODULE_DEVICE_TABLE(of, sg2042_pcie_of_match); - -static struct platform_driver sg2042_pcie_driver = { - .driver = { - .name = "sg2042-pcie", - .of_match_table = sg2042_pcie_of_match, - .pm = &cdns_pcie_pm_ops, - }, - .probe = sg2042_pcie_probe, - .remove = sg2042_pcie_remove, -}; -module_platform_driver(sg2042_pcie_driver); - -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("PCIe controller driver for SG2042 SoCs"); -MODULE_AUTHOR("Chen Wang "); From 7fb6b408ee71ce7c8b65171345df0c9007ff0566 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 12 Sep 2025 13:32:05 +0800 Subject: [PATCH 06/22] Revert "FROMLIST: PCI: cadence: Check pcie-ops before using it." This reverts commit 6b3e82f6db79c9afb9ebef17f59987cf1a66e06d. --- drivers/pci/controller/cadence/pcie-cadence-host.c | 2 +- drivers/pci/controller/cadence/pcie-cadence.c | 4 ++-- drivers/pci/controller/cadence/pcie-cadence.h | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index fffd63d6665e81..59a4631de79fe8 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -531,7 +531,7 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc) cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1); cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1); - if (pcie->ops && pcie->ops->cpu_addr_fixup) + if (pcie->ops->cpu_addr_fixup) cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) | diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c index 61806bbd8aa326..70a19573440ee9 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -92,7 +92,7 @@ void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1); /* Set the CPU address */ - if (pcie->ops && pcie->ops->cpu_addr_fixup) + if (pcie->ops->cpu_addr_fixup) cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) | @@ -123,7 +123,7 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, } /* Set the CPU address */ - if (pcie->ops && pcie->ops->cpu_addr_fixup) + if (pcie->ops->cpu_addr_fixup) cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(17) | diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 3b23ab8cf89f7e..a149845d341ae4 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -488,7 +488,7 @@ static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) static inline int cdns_pcie_start_link(struct cdns_pcie *pcie) { - if (pcie->ops && pcie->ops->start_link) + if (pcie->ops->start_link) return pcie->ops->start_link(pcie); return 0; @@ -496,13 +496,13 @@ static inline int cdns_pcie_start_link(struct cdns_pcie *pcie) static inline void cdns_pcie_stop_link(struct cdns_pcie *pcie) { - if (pcie->ops && pcie->ops->stop_link) + if (pcie->ops->stop_link) pcie->ops->stop_link(pcie); } static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie) { - if (pcie->ops && pcie->ops->link_up) + if (pcie->ops->link_up) return pcie->ops->link_up(pcie); return true; From 47c3440d2569fa86002c1eaabfc97b657ca1319b Mon Sep 17 00:00:00 2001 From: Han Gao Date: Fri, 12 Sep 2025 13:32:07 +0800 Subject: [PATCH 07/22] Revert "FROMLIST: dt-bindings: pci: Add Sophgo SG2042 PCIe host" This reverts commit 6e357865586a32b7cf73c04a3122816030332740. --- .../bindings/pci/sophgo,sg2042-pcie-host.yaml | 64 ------------------- 1 file changed, 64 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml deleted file mode 100644 index f8b7ca57fff14c..00000000000000 --- a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml +++ /dev/null @@ -1,64 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/pci/sophgo,sg2042-pcie-host.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Sophgo SG2042 PCIe Host (Cadence PCIe Wrapper) - -description: - Sophgo SG2042 PCIe host controller is based on the Cadence PCIe core. - -maintainers: - - Chen Wang - -properties: - compatible: - const: sophgo,sg2042-pcie-host - - reg: - maxItems: 2 - - reg-names: - items: - - const: reg - - const: cfg - - vendor-id: - const: 0x1f1c - - device-id: - const: 0x2042 - - msi-parent: true - -allOf: - - $ref: cdns-pcie-host.yaml# - -required: - - compatible - - reg - - reg-names - -unevaluatedProperties: false - -examples: - - | - #include - - pcie@62000000 { - compatible = "sophgo,sg2042-pcie-host"; - device_type = "pci"; - reg = <0x62000000 0x00800000>, - <0x48000000 0x00001000>; - reg-names = "reg", "cfg"; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>, - <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; - bus-range = <0x00 0xff>; - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; - msi-parent = <&msi>; - }; From 2a7ec952aa079445cc14c13fdc349a78415f49a4 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Fri, 12 Sep 2025 10:35:32 +0800 Subject: [PATCH 08/22] FROMLIST: dt-bindings: pci: Add Sophgo SG2042 PCIe host Add binding for Sophgo SG2042 PCIe host controller. Reviewed-by: Rob Herring (Arm) Signed-off-by: Chen Wang Link: https://lore.kernel.org/r/2755f145755b6096247c26852b63671a6fea4dbf.1757643388.git.unicorn_wang@outlook.com Signed-off-by: Han Gao --- .../bindings/pci/sophgo,sg2042-pcie-host.yaml | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml new file mode 100644 index 00000000000000..f8b7ca57fff14c --- /dev/null +++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/sophgo,sg2042-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 PCIe Host (Cadence PCIe Wrapper) + +description: + Sophgo SG2042 PCIe host controller is based on the Cadence PCIe core. + +maintainers: + - Chen Wang + +properties: + compatible: + const: sophgo,sg2042-pcie-host + + reg: + maxItems: 2 + + reg-names: + items: + - const: reg + - const: cfg + + vendor-id: + const: 0x1f1c + + device-id: + const: 0x2042 + + msi-parent: true + +allOf: + - $ref: cdns-pcie-host.yaml# + +required: + - compatible + - reg + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include + + pcie@62000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x62000000 0x00800000>, + <0x48000000 0x00001000>; + reg-names = "reg", "cfg"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>, + <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; + bus-range = <0x00 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + }; From 6a2458318e4af378865bef2ae5a2f18c8453f322 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Fri, 12 Sep 2025 10:36:01 +0800 Subject: [PATCH 09/22] FROMLIST: PCI: cadence: Check pcie-ops before using it ops of struct cdns_pcie may be NULL, direct use will result in a null pointer error. Add checking of pcie->ops before using it for new driver that may not supply pcie->ops. Signed-off-by: Chen Wang Link: https://lore.kernel.org/r/35182ee1d972dfcd093a964e11205efcebbdc044.1757643388.git.unicorn_wang@outlook.com Signed-off-by: Han Gao --- drivers/pci/controller/cadence/pcie-cadence-host.c | 2 +- drivers/pci/controller/cadence/pcie-cadence.c | 4 ++-- drivers/pci/controller/cadence/pcie-cadence.h | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 59a4631de79fe8..fffd63d6665e81 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -531,7 +531,7 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc) cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1); cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1); - if (pcie->ops->cpu_addr_fixup) + if (pcie->ops && pcie->ops->cpu_addr_fixup) cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) | diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c index 70a19573440ee9..61806bbd8aa326 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -92,7 +92,7 @@ void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1); /* Set the CPU address */ - if (pcie->ops->cpu_addr_fixup) + if (pcie->ops && pcie->ops->cpu_addr_fixup) cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) | @@ -123,7 +123,7 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, } /* Set the CPU address */ - if (pcie->ops->cpu_addr_fixup) + if (pcie->ops && pcie->ops->cpu_addr_fixup) cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(17) | diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index a149845d341ae4..3b23ab8cf89f7e 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -488,7 +488,7 @@ static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) static inline int cdns_pcie_start_link(struct cdns_pcie *pcie) { - if (pcie->ops->start_link) + if (pcie->ops && pcie->ops->start_link) return pcie->ops->start_link(pcie); return 0; @@ -496,13 +496,13 @@ static inline int cdns_pcie_start_link(struct cdns_pcie *pcie) static inline void cdns_pcie_stop_link(struct cdns_pcie *pcie) { - if (pcie->ops->stop_link) + if (pcie->ops && pcie->ops->stop_link) pcie->ops->stop_link(pcie); } static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie) { - if (pcie->ops->link_up) + if (pcie->ops && pcie->ops->link_up) return pcie->ops->link_up(pcie); return true; From dbc8e41eac7a828ed8db827b5ca057e9c45eef3c Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Fri, 12 Sep 2025 10:36:31 +0800 Subject: [PATCH 10/22] FROMLIST: PCI: sg2042: Add Sophgo SG2042 PCIe driver Add support for PCIe controller in SG2042 SoC. The controller uses the Cadence PCIe core programmed by pcie-cadence*.c. The PCIe controller will work in host mode only, supporting data rate (16 GT/s) and lanes (x16 or x8). Signed-off-by: Chen Wang Link: https://lore.kernel.org/r/01b0a57cd9dba8bed7c1f2d52997046c2c6f042b.1757643388.git.unicorn_wang@outlook.com Signed-off-by: Han Gao --- drivers/pci/controller/cadence/Kconfig | 10 ++ drivers/pci/controller/cadence/Makefile | 1 + drivers/pci/controller/cadence/pcie-sg2042.c | 138 +++++++++++++++++++ 3 files changed, 149 insertions(+) create mode 100644 drivers/pci/controller/cadence/pcie-sg2042.c diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig index 666e16b6367f14..02a639e55fd8cf 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -42,6 +42,15 @@ config PCIE_CADENCE_PLAT_EP endpoint mode. This PCIe controller may be embedded into many different vendors SoCs. +config PCIE_SG2042_HOST + tristate "Sophgo SG2042 PCIe controller (host mode)" + depends on OF && (ARCH_SOPHGO || COMPILE_TEST) + select PCIE_CADENCE_HOST + help + Say Y here if you want to support the Sophgo SG2042 PCIe platform + controller in host mode. Sophgo SG2042 PCIe controller uses Cadence + PCIe core. + config PCI_J721E tristate select PCIE_CADENCE_HOST if PCI_J721E_HOST != n @@ -67,4 +76,5 @@ config PCI_J721E_EP Say Y here if you want to support the TI J721E PCIe platform controller in endpoint mode. TI J721E PCIe controller uses Cadence PCIe core. + endmenu diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile index 9bac5fb2f13dad..5e23f8539ecc12 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) += pci-j721e.o +obj-$(CONFIG_PCIE_SG2042_HOST) += pcie-sg2042.o diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c new file mode 100644 index 00000000000000..db91c37790b7dd --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-sg2042.c @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * pcie-sg2042 - PCIe controller driver for Sophgo SG2042 SoC + * + * Copyright (C) 2025 Sophgo Technology Inc. + * Copyright (C) 2025 Chen Wang + */ + +#include +#include +#include +#include + +#include "pcie-cadence.h" + +/* + * SG2042 only supports 4-byte aligned access, so for the rootbus (i.e. to + * read/write the Root Port itself, read32/write32 is required. For + * non-rootbus (i.e. to read/write the PCIe peripheral registers, supports + * 1/2/4 byte aligned access, so directly using read/write should be fine. + */ + +static struct pci_ops sg2042_pcie_root_ops = { + .map_bus = cdns_pci_map_bus, + .read = pci_generic_config_read32, + .write = pci_generic_config_write32, +}; + +static struct pci_ops sg2042_pcie_child_ops = { + .map_bus = cdns_pci_map_bus, + .read = pci_generic_config_read, + .write = pci_generic_config_write, +}; + +static int sg2042_pcie_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct pci_host_bridge *bridge; + struct cdns_pcie *pcie; + struct cdns_pcie_rc *rc; + int ret; + + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); + if (!bridge) { + dev_err_probe(dev, -ENOMEM, "Failed to alloc host bridge!\n"); + return -ENOMEM; + } + + bridge->ops = &sg2042_pcie_root_ops; + bridge->child_ops = &sg2042_pcie_child_ops; + + rc = pci_host_bridge_priv(bridge); + pcie = &rc->pcie; + pcie->dev = dev; + + platform_set_drvdata(pdev, pcie); + + pm_runtime_set_active(dev); + pm_runtime_no_callbacks(dev); + devm_pm_runtime_enable(dev); + + ret = cdns_pcie_init_phy(dev, pcie); + if (ret) { + dev_err_probe(dev, ret, "Failed to init phy!\n"); + return ret; + } + + ret = cdns_pcie_host_setup(rc); + if (ret) { + dev_err_probe(dev, ret, "Failed to setup host!\n"); + cdns_pcie_disable_phy(pcie); + return ret; + } + + return 0; +} + +static void sg2042_pcie_remove(struct platform_device *pdev) +{ + struct cdns_pcie *pcie = platform_get_drvdata(pdev); + struct device *dev = &pdev->dev; + struct cdns_pcie_rc *rc; + + rc = container_of(pcie, struct cdns_pcie_rc, pcie); + cdns_pcie_host_disable(rc); + + cdns_pcie_disable_phy(pcie); + + pm_runtime_disable(dev); +} + +static int sg2042_pcie_suspend_noirq(struct device *dev) +{ + struct cdns_pcie *pcie = dev_get_drvdata(dev); + + cdns_pcie_disable_phy(pcie); + + return 0; +} + +static int sg2042_pcie_resume_noirq(struct device *dev) +{ + struct cdns_pcie *pcie = dev_get_drvdata(dev); + int ret; + + ret = cdns_pcie_enable_phy(pcie); + if (ret) { + dev_err(dev, "failed to enable PHY\n"); + return ret; + } + + return 0; +} + +static DEFINE_NOIRQ_DEV_PM_OPS(sg2042_pcie_pm_ops, + sg2042_pcie_suspend_noirq, + sg2042_pcie_resume_noirq); + +static const struct of_device_id sg2042_pcie_of_match[] = { + { .compatible = "sophgo,sg2042-pcie-host" }, + {}, +}; +MODULE_DEVICE_TABLE(of, sg2042_pcie_of_match); + +static struct platform_driver sg2042_pcie_driver = { + .driver = { + .name = "sg2042-pcie", + .of_match_table = sg2042_pcie_of_match, + .pm = pm_sleep_ptr(&sg2042_pcie_pm_ops), + }, + .probe = sg2042_pcie_probe, + .remove = sg2042_pcie_remove, +}; +module_platform_driver(sg2042_pcie_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("PCIe controller driver for SG2042 SoCs"); +MODULE_AUTHOR("Chen Wang "); From 1096f46cf4c45f5b67281bdce7ca84afafd3ad10 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Fri, 12 Sep 2025 10:36:50 +0800 Subject: [PATCH 11/22] FROMLIST: riscv: sophgo: dts: add PCIe controllers for SG2042 Add PCIe controller nodes in DTS for Sophgo SG2042. Default they are disabled. Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Link: https://lore.kernel.org/r/828860951ec4973285fe92fceb4b6f0ecb365a2f.1757643388.git.unicorn_wang@outlook.com Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 88 ++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index 0a31957d69ba16..caad6117845c13 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -264,6 +264,94 @@ #clock-cells = <1>; }; + pcie_rc0: pcie@7060000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x60000000 0x0 0x00800000>, + <0x40 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + + pcie_rc1: pcie@7060800000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x60800000 0x0 0x00800000>, + <0x44 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0xc0400000 0x44 0xc0400000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, + <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, + <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + + pcie_rc2: pcie@7062000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x62000000 0x0 0x00800000>, + <0x48 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <2>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0xc0800000 0x48 0xc0800000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, + <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, + <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + + pcie_rc3: pcie@7062800000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x62800000 0x0 0x00800000>, + <0x4c 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <3>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0xc0c00000 0x4c 0xc0c00000 0x0 0x00400000>, + <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, + <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, + <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, + <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + clint_mswi: interrupt-controller@7094000000 { compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; reg = <0x00000070 0x94000000 0x00000000 0x00004000>; From 881ea07fe3722e54f18e3da309053eed69dae6d0 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Fri, 12 Sep 2025 10:37:13 +0800 Subject: [PATCH 12/22] FROMLIST: riscv: sophgo: dts: enable PCIe for PioneerBox Enable PCIe controllers for PioneerBox, which uses SG2042 SoC. Signed-off-by: Chen Wang Link: https://lore.kernel.org/r/a499a1c17f317ea57de8769032ec65e1e18b4b36.1757643388.git.unicorn_wang@outlook.com Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index 554ec14d58453a..452d5f23b5784a 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -128,6 +128,18 @@ }; }; +&pcie_rc0 { + status = "okay"; +}; + +&pcie_rc2 { + status = "okay"; +}; + +&pcie_rc3 { + status = "okay"; +}; + &sd { pinctrl-0 = <&sd_cfg>; pinctrl-names = "default"; From 468c497c887c8e54aee1f653dd1f9e0fe0aa9d80 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Fri, 12 Sep 2025 10:37:35 +0800 Subject: [PATCH 13/22] FROMLIST: riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X Enable PCIe controllers for Sophgo SG2042_EVB_V1.X board, which uses SG2042 SoC. Signed-off-by: Chen Wang Link: https://lore.kernel.org/r/76d4012e515dc3c3d4e406a237eadc55203f77b6.1757643388.git.unicorn_wang@outlook.com Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts index d447d66177ee5c..bc82afab63da23 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts @@ -164,6 +164,18 @@ }; }; +&pcie_rc0 { + status = "okay"; +}; + +&pcie_rc1 { + status = "okay"; +}; + +&pcie_rc2 { + status = "okay"; +}; + &pinctrl { emmc_cfg: sdhci-emmc-cfg { sdhci-emmc-wp-pins { From 607f95c5e9e4b68584c657bdbe10d644460eb87f Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Fri, 12 Sep 2025 10:37:54 +0800 Subject: [PATCH 14/22] FROMLIST: riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0 Enable PCIe controllers for Sophgo SG2042_EVB_V2.0 board, which uses SG2042 SoC. Signed-off-by: Chen Wang Link: https://lore.kernel.org/r/16831a3277a6c8c19436a17ac199d2f9b80f9ce5.1757643388.git.unicorn_wang@outlook.com Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts index 7001d8ffdc3e04..5df5a37045e6a7 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts @@ -152,6 +152,18 @@ }; }; +&pcie_rc0 { + status = "okay"; +}; + +&pcie_rc1 { + status = "okay"; +}; + +&pcie_rc2 { + status = "okay"; +}; + &pinctrl { emmc_cfg: sdhci-emmc-cfg { sdhci-emmc-wp-pins { From 9548302b2c48918bea0f5e2e893624a804f80524 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Sat, 20 Sep 2025 22:51:42 +0800 Subject: [PATCH 15/22] Revert "FROMLIST: riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V2" This reverts commit 72c3cae82853cfb825b172a4626ed5f0a89d24c6. --- arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts index 5df5a37045e6a7..0cd0dc0f537c14 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts @@ -238,18 +238,6 @@ status = "okay"; }; -&spifmc1 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <100000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -}; - &uart0 { pinctrl-0 = <&uart0_cfg>; pinctrl-names = "default"; From b5274e7fa7525223f9e2dffccca32775dfe69acc Mon Sep 17 00:00:00 2001 From: Han Gao Date: Sat, 20 Sep 2025 22:51:44 +0800 Subject: [PATCH 16/22] Revert "FROMLIST: riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V1" This reverts commit 64b17942b4e990c8f511aa66bcbede12eddfdb1f. --- arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 24 -------------------- 1 file changed, 24 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts index bc82afab63da23..a186d036cf3606 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts @@ -250,30 +250,6 @@ status = "okay"; }; -&spifmc0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <100000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -}; - -&spifmc1 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <100000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -}; - &uart0 { pinctrl-0 = <&uart0_cfg>; pinctrl-names = "default"; From f318fea3424c15a670658cb9dd23d63c7483568b Mon Sep 17 00:00:00 2001 From: Han Gao Date: Sat, 20 Sep 2025 22:51:46 +0800 Subject: [PATCH 17/22] Revert "FROMLIST: riscv: dts: sophgo: Enable SPI NOR node for PioneerBox" This reverts commit b047f5b8944fbc49a2d769c12da1bf070aa64635. --- .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 24 ------------------- 1 file changed, 24 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index 452d5f23b5784a..c4d5f8d7d4ad3f 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -150,30 +150,6 @@ status = "okay"; }; -&spifmc0 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <100000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -}; - -&spifmc1 { - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <100000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -}; - &uart0 { pinctrl-0 = <&uart0_cfg>; pinctrl-names = "default"; From c55e1f49159949b104e1dd52e1a4fc39e8620196 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Sat, 20 Sep 2025 22:51:47 +0800 Subject: [PATCH 18/22] Revert "FROMLIST: riscv: dts: sophgo: Add SPI NOR node for SG2042" This reverts commit d0deeee4ef57bb68c4bae28b63f5693f2bc1f87c. --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 24 ------------------------ 1 file changed, 24 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index caad6117845c13..6ec9fb81af2a75 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -68,30 +68,6 @@ interrupt-parent = <&intc>; ranges; - spifmc0: spi@7000180000 { - compatible = "sophgo,sg2042-spifmc-nor"; - reg = <0x70 0x00180000 0x0 0x1000000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkgen GATE_CLK_AHB_SF>; - interrupt-parent = <&intc>; - interrupts = <108 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstgen RST_SF0>; - status = "disabled"; - }; - - spifmc1: spi@7002180000 { - compatible = "sophgo,sg2042-spifmc-nor"; - reg = <0x70 0x02180000 0x0 0x1000000>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clkgen GATE_CLK_AHB_SF>; - interrupt-parent = <&intc>; - interrupts = <109 IRQ_TYPE_LEVEL_HIGH>; - resets = <&rstgen RST_SF1>; - status = "disabled"; - }; - i2c0: i2c@7030005000 { compatible = "snps,designware-i2c"; reg = <0x70 0x30005000 0x0 0x1000>; From b2102673ca3a96c3de7eb513c156388ef72be829 Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Tue, 16 Sep 2025 21:22:50 +0800 Subject: [PATCH 19/22] FROMLIST: riscv: dts: sophgo: Add SPI NOR node for SG2042 Add SPI NOR controller node for SG2042 Reviewed-by: Chen Wang Tested-by: Chen Wang Signed-off-by: Zixian Zeng Link: https://lore.kernel.org/r/20250916-sfg-spidts-v2-1-b5d9024fe1c8@gmail.com Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index 6ec9fb81af2a75..caad6117845c13 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -68,6 +68,30 @@ interrupt-parent = <&intc>; ranges; + spifmc0: spi@7000180000 { + compatible = "sophgo,sg2042-spifmc-nor"; + reg = <0x70 0x00180000 0x0 0x1000000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkgen GATE_CLK_AHB_SF>; + interrupt-parent = <&intc>; + interrupts = <108 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rstgen RST_SF0>; + status = "disabled"; + }; + + spifmc1: spi@7002180000 { + compatible = "sophgo,sg2042-spifmc-nor"; + reg = <0x70 0x02180000 0x0 0x1000000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkgen GATE_CLK_AHB_SF>; + interrupt-parent = <&intc>; + interrupts = <109 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rstgen RST_SF1>; + status = "disabled"; + }; + i2c0: i2c@7030005000 { compatible = "snps,designware-i2c"; reg = <0x70 0x30005000 0x0 0x1000>; From d34ea9eee520d84c564cfa981b6634ecb5b3cc6f Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Tue, 16 Sep 2025 21:22:51 +0800 Subject: [PATCH 20/22] FROMLIST: riscv: dts: sophgo: Enable SPI NOR node for PioneerBox Enable SPI NOR node for PioneerBox device tree According to PioneerBox schematic, SPI-NOR Flash cannot support QSPI due to hardware design. Thus spi-(tx|rx)-bus-width must be set to 1. Reviewed-by: Chen Wang Tested-by: Chen Wang Signed-off-by: Zixian Zeng Link: https://lore.kernel.org/r/20250916-sfg-spidts-v2-2-b5d9024fe1c8@gmail.com Signed-off-by: Han Gao --- .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index c4d5f8d7d4ad3f..54d8386bf9c0ff 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -150,6 +150,30 @@ status = "okay"; }; +&spifmc0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; + +&spifmc1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; + &uart0 { pinctrl-0 = <&uart0_cfg>; pinctrl-names = "default"; From f056399927b4af6f302c38d4990d4111ad06c5db Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Tue, 16 Sep 2025 21:22:52 +0800 Subject: [PATCH 21/22] FROMLIST: riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V1 Enable SPI NOR node for SG2042_EVB_V1 device tree According to SG2042_EVB_V1 schematic, SPI-NOR Flash cannot support QSPI due to hardware design. Thus spi-(tx|rx)-bus-width must be set to 1. Signed-off-by: Zixian Zeng Link: https://lore.kernel.org/r/20250916-sfg-spidts-v2-3-b5d9024fe1c8@gmail.com Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 24 ++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts index a186d036cf3606..b116dfa904cd98 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts @@ -250,6 +250,30 @@ status = "okay"; }; +&spifmc0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; + +&spifmc1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; + &uart0 { pinctrl-0 = <&uart0_cfg>; pinctrl-names = "default"; From 3ba0b81966f67b1ccb451f1eb69cc6f45671eab2 Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Tue, 16 Sep 2025 21:22:53 +0800 Subject: [PATCH 22/22] FROMLIST: riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V2 Enable SPI NOR node for SG2042_EVB_V2 device tree According to SG2042_EVB_V2 schematic, SPI-NOR Flash cannot support QSPI due to hardware design. Thus spi-(tx|rx)-bus-width must be set to 1. Signed-off-by: Zixian Zeng Link: https://lore.kernel.org/r/20250916-sfg-spidts-v2-4-b5d9024fe1c8@gmail.com Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts index 0cd0dc0f537c14..b2ceae2d8829ec 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts @@ -238,6 +238,18 @@ status = "okay"; }; +&spifmc1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; + &uart0 { pinctrl-0 = <&uart0_cfg>; pinctrl-names = "default";