diff --git a/CMSIS/DoxyGen/RTOS2/src/cmsis_os2.txt b/CMSIS/DoxyGen/RTOS2/src/cmsis_os2.txt
index 646f5598bd..2d30fda2af 100644
--- a/CMSIS/DoxyGen/RTOS2/src/cmsis_os2.txt
+++ b/CMSIS/DoxyGen/RTOS2/src/cmsis_os2.txt
@@ -1272,9 +1272,9 @@ System Control Block (SBC) | To control and setup the processor exceptions inclu
Interrupt Control | The CMSIS-Core functions __disable_irq and __enable_irq to control the interrupt system via the CPSR core register.
The RTX implements interfaces to the processor hardware in following files:
- - %irq_cm0.s defines exception handlers for Cortex-M0/M0+
+ - %irq_armv6m.s defines exception handlers for Cortex-M0/M0+
\if ARMv8M
- - %irq_armv8mbl_common.s defines exception handlers for Cortex-M23
+ - %irq_armv8mbl.s defines exception handlers for Cortex-M23
\endif
- %rtx_core_cm.h defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.
- %os_tick.h is the \ref CMSIS_RTOS_TickAPI that defines the interface functions to the SysTick timer.
@@ -1300,10 +1300,9 @@ NVIC Interface | CMSIS-Core function \b NVIC_GetPriorityGrouping is
LDREX, STREX instructions | Exclusive access instructions \b LDREX and \b STREX are used to implement atomic execution without disabling interrupts.
The interface files to the processor hardware are:
- - %irq_cm3.s defines exception handlers for Cortex-M3 and Cortex-M4/M7 without floating point unit.
- - %irq_cm4f.s defines exception handlers for Cortex-M4/M7 with floating point unit.
+ - %irq_armv7m.s defines exception handlers for Cortex-M3 and Cortex-M4/M7.
\if ARMv8M
- - %irq_armv8mml_common.s defines exception handlers for Cortex-M33/M35P
+ - %irq_armv8mml.s defines exception handlers for Cortex-M33/M35P
\endif
- %rtx_core_cm.h defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.
- %os_tick.h is the \ref CMSIS_RTOS_TickAPI that defines the interface functions to the SysTick timer.
@@ -1323,7 +1322,7 @@ LDREX, STREX instruction | Atomic execution avoids the requirement to disable
Interrupt Controller | An interrupt controller interface is required to setup and control Timer Peripheral interrupt. The interface for Arm GIC (Generic Interrupt Controller) is implemented in %irq_ctrl_gic.c using the IRQ Controller API.
The interface files to the processor hardware are:
- - %irq_ca.s defines SVC, IRQ, Data Abort, Prefetch Abort and Undefined Instruction exception handlers.
+ - %irq_armv7a.s defines SVC, IRQ, Data Abort, Prefetch Abort and Undefined Instruction exception handlers.
- %rtx_core_ca.h defines processor specific helper functions and the interfaces to Core Registers and Core Peripherals.
- %os_tick.h is the \ref CMSIS_RTOS_TickAPI that defines the interface functions to the timer peripheral.
- %irq_ctrl.h is the IRQ Controller API that defines the interface functions to the interrupt controller.
diff --git a/CMSIS/DoxyGen/RTOS2/src/history.txt b/CMSIS/DoxyGen/RTOS2/src/history.txt
index 17657bdbb8..93a46a1c9b 100644
--- a/CMSIS/DoxyGen/RTOS2/src/history.txt
+++ b/CMSIS/DoxyGen/RTOS2/src/history.txt
@@ -103,6 +103,7 @@
- CVE-2021-27431 vulnerability mitigation.
- Added OS Initialization for IAR.
+ - Reorganized IRQ module names.
|
diff --git a/CMSIS/RTOS2/RTX/Source/ARM/irq_cm0.s b/CMSIS/RTOS2/RTX/Source/ARM/irq_armv6m.s
similarity index 91%
rename from CMSIS/RTOS2/RTX/Source/ARM/irq_cm0.s
rename to CMSIS/RTOS2/RTX/Source/ARM/irq_armv6m.s
index c5146b3b81..3911a4b143 100644
--- a/CMSIS/RTOS2/RTX/Source/ARM/irq_cm0.s
+++ b/CMSIS/RTOS2/RTX/Source/ARM/irq_armv6m.s
@@ -1,5 +1,5 @@
;/*
-; * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+; * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -18,7 +18,7 @@
; * -----------------------------------------------------------------------------
; *
; * Project: CMSIS-RTOS RTX
-; * Title: Cortex-M0 Exception handlers
+; * Title: ARMv6-M Exception handlers
; *
; * -----------------------------------------------------------------------------
; */
@@ -44,9 +44,9 @@ SVC_Handler PROC
EXPORT SVC_Handler
IMPORT osRtxUserSVC
IMPORT osRtxInfo
- IF :DEF:MPU_LOAD
+ IF :DEF:MPU_LOAD
IMPORT osRtxMpuLoad
- ENDIF
+ ENDIF
MOV R0,LR
LSRS R0,R0,#3 ; Determine return stack from EXC_RETURN bit 2
@@ -57,7 +57,7 @@ SVC_Number
LDR R1,[R0,#24] ; Load saved PC from stack
SUBS R1,R1,#2 ; Point to SVC instruction
LDRB R1,[R1] ; Load SVC number
- CMP R1,#0
+ CMP R1,#0 ; Check SVC number
BNE SVC_User ; Branch if not SVC 0
PUSH {R0,LR} ; Save SP and EXC_RETURN
@@ -68,7 +68,7 @@ SVC_Number
MOV LR,R3 ; Set EXC_RETURN
SVC_Context
- LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+ LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run
LDMIA R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
BEQ SVC_Exit ; Branch when threads are the same
@@ -78,7 +78,7 @@ SVC_Context
SVC_ContextSave
MRS R0,PSP ; Get PSP
- SUBS R0,R0,#32 ; Calculate SP
+ SUBS R0,R0,#32 ; Calculate SP: space for R4..R11
STR R0,[R1,#TCB_SP_OFS] ; Store SP
STMIA R0!,{R4-R7} ; Save R4..R7
MOV R4,R8
@@ -91,12 +91,12 @@ SVC_ContextSwitch
SUBS R3,R3,#8 ; Adjust address
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
- IF :DEF:MPU_LOAD
+ IF :DEF:MPU_LOAD
PUSH {R2,R3} ; Save registers
MOV R0,R2 ; osRtxMpuLoad parameter
BL osRtxMpuLoad ; Load MPU for next thread
POP {R2,R3} ; Restore registers
- ENDIF
+ ENDIF
SVC_ContextRestore
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
@@ -110,7 +110,7 @@ SVC_ContextRestore
SUBS R0,R0,#32 ; Adjust address
LDMIA R0!,{R4-R7} ; Restore R4..R7
- MOVS R0,#~0xFFFFFFFD
+ MOVS R0,#2 ; Binary complement of 0xFFFFFFFD
MVNS R0,R0 ; Set EXC_RETURN value
BX R0 ; Exit from handler
@@ -151,7 +151,7 @@ PendSV_Handler PROC
BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
POP {R0,R1} ; Restore EXC_RETURN
MOV LR,R1 ; Set EXC_RETURN
- B SVC_Context
+ B SVC_Context ; Branch to context handling
ALIGN
ENDP
@@ -165,7 +165,7 @@ SysTick_Handler PROC
BL osRtxTick_Handler ; Call osRtxTick_Handler
POP {R0,R1} ; Restore EXC_RETURN
MOV LR,R1 ; Set EXC_RETURN
- B SVC_Context
+ B SVC_Context ; Branch to context handling
ALIGN
ENDP
diff --git a/CMSIS/RTOS2/RTX/Source/ARM/irq_ca.s b/CMSIS/RTOS2/RTX/Source/ARM/irq_armv7a.s
similarity index 98%
rename from CMSIS/RTOS2/RTX/Source/ARM/irq_ca.s
rename to CMSIS/RTOS2/RTX/Source/ARM/irq_armv7a.s
index e54c42de3c..daf5fe8372 100644
--- a/CMSIS/RTOS2/RTX/Source/ARM/irq_ca.s
+++ b/CMSIS/RTOS2/RTX/Source/ARM/irq_armv7a.s
@@ -1,5 +1,5 @@
;/*
-; * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+; * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -18,7 +18,7 @@
; * -----------------------------------------------------------------------------
; *
; * Project: CMSIS-RTOS RTX
-; * Title: Cortex-A Exception handlers
+; * Title: ARMv7-A Exception handlers
; *
; * -----------------------------------------------------------------------------
; */
@@ -367,16 +367,16 @@ osRtxContextSave
STMDB R1!, {R2,R12} ; Push FPSCR, maintain 8-byte alignment
VSTMDB R1!, {D0-D15} ; Save D0-D15
- IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
+ IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
VSTMDB R1!, {D16-D31} ; Save D16-D31
- ENDIF
+ ENDIF
LDRB R2, [LR, #TCB_SP_FRAME] ; Load osRtxInfo.thread.run.curr frame info
- IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
+ IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
ORR R2, R2, #4 ; NEON state
- ELSE
+ ELSE
ORR R2, R2, #2 ; VFP state
- ENDIF
+ ENDIF
STRB R2, [LR, #TCB_SP_FRAME] ; Store VFP/NEON state
osRtxContextSave1
@@ -428,9 +428,9 @@ osRtxContextRestore
MCR p15, 0, R2, c1, c0, 2 ; Write CPACR
BEQ osRtxContextRestore1 ; No VFP
ISB ; Sync if VFP was enabled
- IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
+ IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
VLDMIA LR!, {D16-D31} ; Restore D16-D31
- ENDIF
+ ENDIF
VLDMIA LR!, {D0-D15} ; Restore D0-D15
LDR R2, [LR]
VMSR FPSCR, R2 ; Restore FPSCR
diff --git a/CMSIS/RTOS2/RTX/Source/ARM/irq_cm4f.s b/CMSIS/RTOS2/RTX/Source/ARM/irq_armv7m.s
similarity index 74%
rename from CMSIS/RTOS2/RTX/Source/ARM/irq_cm4f.s
rename to CMSIS/RTOS2/RTX/Source/ARM/irq_armv7m.s
index 7d405b7e4e..6b7f366a12 100644
--- a/CMSIS/RTOS2/RTX/Source/ARM/irq_cm4f.s
+++ b/CMSIS/RTOS2/RTX/Source/ARM/irq_armv7m.s
@@ -1,5 +1,5 @@
;/*
-; * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+; * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -18,16 +18,23 @@
; * -----------------------------------------------------------------------------
; *
; * Project: CMSIS-RTOS RTX
-; * Title: Cortex-M4F Exception handlers
+; * Title: ARMv7-M Exception handlers
; *
; * -----------------------------------------------------------------------------
; */
+ IF ({FPU}="FPv4-SP")
+FPU_USED EQU 1
+ ELSE
+FPU_USED EQU 0
+ ENDIF
+
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
TCB_SP_OFS EQU 56 ; TCB.SP offset
TCB_SF_OFS EQU 34 ; TCB.stack_frame offset
+FPCCR EQU 0xE000EF34 ; FPCCR Address
PRESERVE8
THUMB
@@ -45,9 +52,9 @@ SVC_Handler PROC
EXPORT SVC_Handler
IMPORT osRtxUserSVC
IMPORT osRtxInfo
- IF :DEF:MPU_LOAD
+ IF :DEF:MPU_LOAD
IMPORT osRtxMpuLoad
- ENDIF
+ ENDIF
TST LR,#0x04 ; Determine return stack from EXC_RETURN bit 2
ITE EQ
@@ -65,47 +72,56 @@ SVC_Handler PROC
STM R12,{R0-R1} ; Store function return values
SVC_Context
- LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+ LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run
LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
IT EQ
BXEQ LR ; Exit when threads are the same
+ IF FPU_USED != 0
CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted
- TST LR,#0x10 ; Check if extended stack frame
- BNE SVC_ContextSwitch
- LDR R1,=0xE000EF34 ; FPCCR Address
- LDR R0,[R1] ; Load FPCCR
- BIC R0,R0,#1 ; Clear LSPACT (Lazy state)
- STR R0,[R1] ; Store FPCCR
- B SVC_ContextSwitch
+ TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4
+ BNE SVC_ContextSwitch ; Branch if not extended stack frame
+ LDR R3,=FPCCR ; FPCCR Address
+ LDR R0,[R3] ; Load FPCCR
+ BIC R0,R0,#1 ; Clear LSPACT (Lazy state preservation)
+ STR R0,[R3] ; Store FPCCR
+ B SVC_ContextSwitch ; Branch to context switch handling
+ ELSE
+ CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted
+ ENDIF
SVC_ContextSave
STMDB R12!,{R4-R11} ; Save R4..R11
- TST LR,#0x10 ; Check if extended stack frame
- IT EQ
+ IF FPU_USED != 0
+ TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4
+ IT EQ ; If extended stack frame
VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31
- STR R12,[R1,#TCB_SP_OFS] ; Store SP
STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information
+ ENDIF
+ STR R12,[R1,#TCB_SP_OFS] ; Store SP
SVC_ContextSwitch
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
- IF :DEF:MPU_LOAD
+ IF :DEF:MPU_LOAD
PUSH {R2,R3} ; Save registers
MOV R0,R2 ; osRtxMpuLoad parameter
BL osRtxMpuLoad ; Load MPU for next thread
POP {R2,R3} ; Restore registers
- ENDIF
+ ENDIF
SVC_ContextRestore
- LDRB R1,[R2,#TCB_SF_OFS] ; Load stack frame information
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
- ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN
-
- TST LR,#0x10 ; Check if extended stack frame
- IT EQ
+ IF FPU_USED != 0
+ LDRB R1,[R2,#TCB_SF_OFS] ; Load stack frame information
+ ORN LR,R1,#0xFF ; Set EXC_RETURN
+ TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4
+ IT EQ ; If extended stack frame
VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31
+ ELSE
+ MVN LR,#~0xFFFFFFFD ; Set EXC_RETURN value
+ ENDIF
LDMIA R0!,{R4-R11} ; Restore R4..R11
MSR PSP,R0 ; Set PSP
@@ -138,8 +154,8 @@ PendSV_Handler PROC
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
POP {R0,LR} ; Restore EXC_RETURN
- MRS R12,PSP
- B SVC_Context
+ MRS R12,PSP ; Save PSP to R12
+ B SVC_Context ; Branch to context handling
ALIGN
ENDP
@@ -152,8 +168,8 @@ SysTick_Handler PROC
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxTick_Handler ; Call osRtxTick_Handler
POP {R0,LR} ; Restore EXC_RETURN
- MRS R12,PSP
- B SVC_Context
+ MRS R12,PSP ; Save PSP to R12
+ B SVC_Context ; Branch to context handling
ALIGN
ENDP
diff --git a/CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s b/CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s
deleted file mode 100644
index 0a5ed3458a..0000000000
--- a/CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.s
+++ /dev/null
@@ -1,146 +0,0 @@
-;/*
-; * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; *
-; * -----------------------------------------------------------------------------
-; *
-; * Project: CMSIS-RTOS RTX
-; * Title: Cortex-M3 Exception handlers
-; *
-; * -----------------------------------------------------------------------------
-; */
-
-
-I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
-TCB_SP_OFS EQU 56 ; TCB.SP offset
-
-
- PRESERVE8
- THUMB
-
-
- AREA |.constdata|, DATA, READONLY
- EXPORT irqRtxLib
-irqRtxLib DCB 0 ; Non weak library reference
-
-
- AREA |.text|, CODE, READONLY
-
-
-SVC_Handler PROC
- EXPORT SVC_Handler
- IMPORT osRtxUserSVC
- IMPORT osRtxInfo
- IF :DEF:MPU_LOAD
- IMPORT osRtxMpuLoad
- ENDIF
-
- TST LR,#0x04 ; Determine return stack from EXC_RETURN bit 2
- ITE EQ
- MRSEQ R0,MSP ; Get MSP if return stack is MSP
- MRSNE R0,PSP ; Get PSP if return stack is PSP
-
- LDR R1,[R0,#24] ; Load saved PC from stack
- LDRB R1,[R1,#-2] ; Load SVC number
- CBNZ R1,SVC_User ; Branch if not SVC 0
-
- PUSH {R0,LR} ; Save SP and EXC_RETURN
- LDM R0,{R0-R3,R12} ; Load function parameters and address from stack
- BLX R12 ; Call service function
- POP {R12,LR} ; Restore SP and EXC_RETURN
- STM R12,{R0-R1} ; Store function return values
-
-SVC_Context
- LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
- LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
- CMP R1,R2 ; Check if thread switch is required
- IT EQ
- BXEQ LR ; Exit when threads are the same
-
- CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted
-
-SVC_ContextSave
- STMDB R12!,{R4-R11} ; Save R4..R11
- STR R12,[R1,#TCB_SP_OFS] ; Store SP
-
-SVC_ContextSwitch
- STR R2,[R3] ; osRtxInfo.thread.run: curr = next
-
- IF :DEF:MPU_LOAD
- PUSH {R2,R3} ; Save registers
- MOV R0,R2 ; osRtxMpuLoad parameter
- BL osRtxMpuLoad ; Load MPU for next thread
- POP {R2,R3} ; Restore registers
- ENDIF
-
-SVC_ContextRestore
- LDR R0,[R2,#TCB_SP_OFS] ; Load SP
- LDMIA R0!,{R4-R11} ; Restore R4..R11
- MSR PSP,R0 ; Set PSP
-
- MVN LR,#~0xFFFFFFFD ; Set EXC_RETURN value
-
-SVC_Exit
- BX LR ; Exit from handler
-
-SVC_User
- LDR R2,=osRtxUserSVC ; Load address of SVC table
- LDR R3,[R2] ; Load SVC maximum number
- CMP R1,R3 ; Check SVC number range
- BHI SVC_Exit ; Branch if out of range
-
- PUSH {R0,LR} ; Save SP and EXC_RETURN
- LDR R12,[R2,R1,LSL #2] ; Load address of SVC function
- LDM R0,{R0-R3} ; Load function parameters from stack
- BLX R12 ; Call service function
- POP {R12,LR} ; Restore SP and EXC_RETURN
- STR R0,[R12] ; Store function return value
-
- BX LR ; Return from handler
-
- ALIGN
- ENDP
-
-
-PendSV_Handler PROC
- EXPORT PendSV_Handler
- IMPORT osRtxPendSV_Handler
-
- PUSH {R0,LR} ; Save EXC_RETURN
- BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
- POP {R0,LR} ; Restore EXC_RETURN
- MRS R12,PSP
- B SVC_Context
-
- ALIGN
- ENDP
-
-
-SysTick_Handler PROC
- EXPORT SysTick_Handler
- IMPORT osRtxTick_Handler
-
- PUSH {R0,LR} ; Save EXC_RETURN
- BL osRtxTick_Handler ; Call osRtxTick_Handler
- POP {R0,LR} ; Restore EXC_RETURN
- MRS R12,PSP
- B SVC_Context
-
- ALIGN
- ENDP
-
-
- END
diff --git a/CMSIS/RTOS2/RTX/Source/GCC/irq_cm0.S b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv6m.S
similarity index 92%
rename from CMSIS/RTOS2/RTX/Source/GCC/irq_cm0.S
rename to CMSIS/RTOS2/RTX/Source/GCC/irq_armv6m.S
index e261cd066f..3358fdea99 100644
--- a/CMSIS/RTOS2/RTX/Source/GCC/irq_cm0.S
+++ b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv6m.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -18,7 +18,7 @@
* -----------------------------------------------------------------------------
*
* Project: CMSIS-RTOS RTX
- * Title: Cortex-M0 Exception handlers
+ * Title: ARMv6-M Exception handlers
*
* -----------------------------------------------------------------------------
*/
@@ -38,6 +38,7 @@ irqRtxLib:
.thumb
.section ".text"
.align 2
+ .eabi_attribute Tag_ABI_align_preserved, 1
.thumb_func
@@ -56,7 +57,7 @@ SVC_Number:
LDR R1,[R0,#24] // Load saved PC from stack
SUBS R1,R1,#2 // Point to SVC instruction
LDRB R1,[R1] // Load SVC number
- CMP R1,#0
+ CMP R1,#0 // Check SVC number
BNE SVC_User // Branch if not SVC 0
PUSH {R0,LR} // Save SP and EXC_RETURN
@@ -67,7 +68,7 @@ SVC_Number:
MOV LR,R3 // Set EXC_RETURN
SVC_Context:
- LDR R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run
+ LDR R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.thread.run
LDMIA R3!,{R1,R2} // Load osRtxInfo.thread.run: curr & next
CMP R1,R2 // Check if thread switch is required
BEQ SVC_Exit // Branch when threads are the same
@@ -102,7 +103,7 @@ SVC_ContextRestore:
SUBS R0,R0,#32 // Adjust address
LDMIA R0!,{R4-R7} // Restore R4..R7
- MOVS R0,#~0xFFFFFFFD
+ MOVS R0,#2 // Binary complement of 0xFFFFFFFD
MVNS R0,R0 // Set EXC_RETURN value
BX R0 // Exit from handler
@@ -146,7 +147,7 @@ PendSV_Handler:
BL osRtxPendSV_Handler // Call osRtxPendSV_Handler
POP {R0,R1} // Restore EXC_RETURN
MOV LR,R1 // Set EXC_RETURN
- B SVC_Context
+ B SVC_Context // Branch to context handling
.fnend
.size PendSV_Handler, .-PendSV_Handler
@@ -163,7 +164,7 @@ SysTick_Handler:
BL osRtxTick_Handler // Call osRtxTick_Handler
POP {R0,R1} // Restore EXC_RETURN
MOV LR,R1 // Set EXC_RETURN
- B SVC_Context
+ B SVC_Context // Branch to context handling
.fnend
.size SysTick_Handler, .-SysTick_Handler
diff --git a/CMSIS/RTOS2/RTX/Source/GCC/irq_ca.S b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv7a.S
similarity index 97%
rename from CMSIS/RTOS2/RTX/Source/GCC/irq_ca.S
rename to CMSIS/RTOS2/RTX/Source/GCC/irq_armv7a.S
index 9680b66553..f83f6c2e4d 100644
--- a/CMSIS/RTOS2/RTX/Source/GCC/irq_ca.S
+++ b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv7a.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -18,7 +18,7 @@
* -----------------------------------------------------------------------------
*
* Project: CMSIS-RTOS RTX
- * Title: Cortex-A Exception handlers
+ * Title: ARMv7-A Exception handlers
*
* -----------------------------------------------------------------------------
*/
@@ -366,25 +366,25 @@ osRtxContextSave:
MRC p15, 0, R2, c1, c0, 2 // VFP/NEON access enabled? (CPACR)
AND R2, R2, #0x00F00000
CMP R2, #0x00F00000
- BNE osRtxContextSave1 // Continue, no VFP
+ BNE osRtxContextSaveSP // Continue, no VFP
VMRS R2, FPSCR
STMDB R1!, {R2,R12} // Push FPSCR, maintain 8-byte alignment
VSTMDB R1!, {D0-D15} // Save D0-D15
- #if defined(__ARM_NEON) && (__ARM_NEON == 1)
+ #if defined(__ARM_NEON) && (__ARM_NEON == 1)
VSTMDB R1!, {D16-D31} // Save D16-D31
- #endif
+ #endif
LDRB R2, [LR, #TCB_SP_FRAME] // Load osRtxInfo.thread.run.curr frame info
- #if defined(__ARM_NEON) && (__ARM_NEON == 1)
+ #if defined(__ARM_NEON) && (__ARM_NEON == 1)
ORR R2, R2, #4 // NEON state
- #else
+ #else
ORR R2, R2, #2 // VFP state
- #endif
+ #endif
STRB R2, [LR, #TCB_SP_FRAME] // Store VFP/NEON state
-osRtxContextSave1:
+osRtxContextSaveSP:
STR R1, [LR, #TCB_SP_OFS] // Store user sp to osRtxInfo.thread.run.curr
osRtxPostProcess:
@@ -431,17 +431,17 @@ osRtxContextRestore:
ANDEQ R2, R2, #0xFF0FFFFF // VFP/NEON state not stacked, disable VFP/NEON
ORRNE R2, R2, #0x00F00000 // VFP/NEON state is stacked, enable VFP/NEON
MCR p15, 0, R2, c1, c0, 2 // Write CPACR
- BEQ osRtxContextRestore1 // No VFP
+ BEQ osRtxContextRestoreRegs // No VFP
ISB // Sync if VFP was enabled
- #if defined(__ARM_NEON) && (__ARM_NEON == 1)
+ #if defined(__ARM_NEON) && (__ARM_NEON == 1)
VLDMIA LR!, {D16-D31} // Restore D16-D31
- #endif
+ #endif
VLDMIA LR!, {D0-D15} // Restore D0-D15
LDR R2, [LR]
VMSR FPSCR, R2 // Restore FPSCR
ADD LR, LR, #8 // Adjust sp pointer to R4
-osRtxContextRestore1:
+osRtxContextRestoreRegs:
LDMIA LR!, {R4-R11} // Restore R4-R11
ADD R12, LR, #32 // Adjust sp and save it into R12
PUSH {R12} // Push sp onto stack
diff --git a/CMSIS/RTOS2/RTX/Source/GCC/irq_cm4f.S b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S
similarity index 74%
rename from CMSIS/RTOS2/RTX/Source/GCC/irq_cm4f.S
rename to CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S
index e02990956c..b722f9f667 100644
--- a/CMSIS/RTOS2/RTX/Source/GCC/irq_cm4f.S
+++ b/CMSIS/RTOS2/RTX/Source/GCC/irq_armv7m.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+ * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -18,7 +18,7 @@
* -----------------------------------------------------------------------------
*
* Project: CMSIS-RTOS RTX
- * Title: Cortex-M4F Exception handlers
+ * Title: ARMv7-M Exception handlers
*
* -----------------------------------------------------------------------------
*/
@@ -26,10 +26,18 @@
.syntax unified
+ #if (defined(__ARM_FP) && (__ARM_FP > 0))
+ .equ FPU_USED, 1
+ #else
+ .equ FPU_USED, 0
+ #endif
+
.equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset
.equ TCB_SP_OFS, 56 // TCB.SP offset
.equ TCB_SF_OFS, 34 // TCB.stack_frame offset
+ .equ FPCCR, 0xE000EF34 // FPCCR Address
+
.section ".rodata"
.global irqRtxLib // Non weak library reference
irqRtxLib:
@@ -39,6 +47,7 @@ irqRtxLib:
.thumb
.section ".text"
.align 2
+ .eabi_attribute Tag_ABI_align_preserved, 1
.thumb_func
@@ -64,40 +73,49 @@ SVC_Handler:
STM R12,{R0-R1} // Store function return values
SVC_Context:
- LDR R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run
+ LDR R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.thread.run
LDM R3,{R1,R2} // Load osRtxInfo.thread.run: curr & next
CMP R1,R2 // Check if thread switch is required
IT EQ
BXEQ LR // Exit when threads are the same
+ .if (FPU_USED != 0)
CBNZ R1,SVC_ContextSave // Branch if running thread is not deleted
- TST LR,#0x10 // Check if extended stack frame
- BNE SVC_ContextSwitch
- LDR R1,=0xE000EF34 // FPCCR Address
- LDR R0,[R1] // Load FPCCR
- BIC R0,R0,#1 // Clear LSPACT (Lazy state)
- STR R0,[R1] // Store FPCCR
- B SVC_ContextSwitch
+ TST LR,#0x10 // Determine stack frame from EXC_RETURN bit 4
+ BNE SVC_ContextSwitch // Branch if not extended stack frame
+ LDR R3,=FPCCR // FPCCR Address
+ LDR R0,[R3] // Load FPCCR
+ BIC R0,R0,#1 // Clear LSPACT (Lazy state preservation)
+ STR R0,[R3] // Store FPCCR
+ B SVC_ContextSwitch // Branch to context switch handling
+ .else
+ CBZ R1,SVC_ContextSwitch // Branch if running thread is deleted
+ .endif
SVC_ContextSave:
STMDB R12!,{R4-R11} // Save R4..R11
- TST LR,#0x10 // Check if extended stack frame
- IT EQ
+ .if (FPU_USED != 0)
+ TST LR,#0x10 // Determine stack frame from EXC_RETURN bit 4
+ IT EQ // If extended stack frame
VSTMDBEQ R12!,{S16-S31} // Save VFP S16.S31
- STR R12,[R1,#TCB_SP_OFS] // Store SP
STRB LR, [R1,#TCB_SF_OFS] // Store stack frame information
+ .endif
+ STR R12,[R1,#TCB_SP_OFS] // Store SP
SVC_ContextSwitch:
STR R2,[R3] // osRtxInfo.thread.run: curr = next
SVC_ContextRestore:
- LDRB R1,[R2,#TCB_SF_OFS] // Load stack frame information
LDR R0,[R2,#TCB_SP_OFS] // Load SP
- ORR LR,R1,#0xFFFFFF00 // Set EXC_RETURN
-
- TST LR,#0x10 // Check if extended stack frame
- IT EQ
+ .if (FPU_USED != 0)
+ LDRB R1,[R2,#TCB_SF_OFS] // Load stack frame information
+ ORN LR,R1,#0xFF // Set EXC_RETURN
+ TST LR,#0x10 // Determine stack frame from EXC_RETURN bit 4
+ IT EQ // If extended stack frame
VLDMIAEQ R0!,{S16-S31} // Restore VFP S16..S31
+ .else
+ MVN LR,#~0xFFFFFFFD // Set EXC_RETURN value
+ .endif
LDMIA R0!,{R4-R11} // Restore R4..R11
MSR PSP,R0 // Set PSP
@@ -133,8 +151,8 @@ PendSV_Handler:
PUSH {R0,LR} // Save EXC_RETURN
BL osRtxPendSV_Handler // Call osRtxPendSV_Handler
POP {R0,LR} // Restore EXC_RETURN
- MRS R12,PSP
- B SVC_Context
+ MRS R12,PSP // Save PSP to R12
+ B SVC_Context // Branch to context handling
.fnend
.size PendSV_Handler, .-PendSV_Handler
@@ -150,8 +168,8 @@ SysTick_Handler:
PUSH {R0,LR} // Save EXC_RETURN
BL osRtxTick_Handler // Call osRtxTick_Handler
POP {R0,LR} // Restore EXC_RETURN
- MRS R12,PSP
- B SVC_Context
+ MRS R12,PSP // Save PSP to R12
+ B SVC_Context // Branch to context handling
.fnend
.size SysTick_Handler, .-SysTick_Handler
diff --git a/CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S b/CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S
deleted file mode 100644
index 069bc90145..0000000000
--- a/CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * -----------------------------------------------------------------------------
- *
- * Project: CMSIS-RTOS RTX
- * Title: Cortex-M3 Exception handlers
- *
- * -----------------------------------------------------------------------------
- */
-
-
- .syntax unified
-
- .equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset
- .equ TCB_SP_OFS, 56 // TCB.SP offset
-
- .section ".rodata"
- .global irqRtxLib // Non weak library reference
-irqRtxLib:
- .byte 0
-
-
- .thumb
- .section ".text"
- .align 2
-
-
- .thumb_func
- .type SVC_Handler, %function
- .global SVC_Handler
- .fnstart
- .cantunwind
-SVC_Handler:
-
- TST LR,#0x04 // Determine return stack from EXC_RETURN bit 2
- ITE EQ
- MRSEQ R0,MSP // Get MSP if return stack is MSP
- MRSNE R0,PSP // Get PSP if return stack is PSP
-
- LDR R1,[R0,#24] // Load saved PC from stack
- LDRB R1,[R1,#-2] // Load SVC number
- CBNZ R1,SVC_User // Branch if not SVC 0
-
- PUSH {R0,LR} // Save SP and EXC_RETURN
- LDM R0,{R0-R3,R12} // Load function parameters and address from stack
- BLX R12 // Call service function
- POP {R12,LR} // Restore SP and EXC_RETURN
- STM R12,{R0-R1} // Store function return values
-
-SVC_Context:
- LDR R3,=osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run
- LDM R3,{R1,R2} // Load osRtxInfo.thread.run: curr & next
- CMP R1,R2 // Check if thread switch is required
- IT EQ
- BXEQ LR // Exit when threads are the same
-
- CBZ R1,SVC_ContextSwitch // Branch if running thread is deleted
-
-SVC_ContextSave:
- STMDB R12!,{R4-R11} // Save R4..R11
- STR R12,[R1,#TCB_SP_OFS] // Store SP
-
-SVC_ContextSwitch:
- STR R2,[R3] // osRtxInfo.thread.run: curr = next
-
-SVC_ContextRestore:
- LDR R0,[R2,#TCB_SP_OFS] // Load SP
- LDMIA R0!,{R4-R11} // Restore R4..R11
- MSR PSP,R0 // Set PSP
- MVN LR,#~0xFFFFFFFD // Set EXC_RETURN value
-
-SVC_Exit:
- BX LR // Exit from handler
-
-SVC_User:
- LDR R2,=osRtxUserSVC // Load address of SVC table
- LDR R3,[R2] // Load SVC maximum number
- CMP R1,R3 // Check SVC number range
- BHI SVC_Exit // Branch if out of range
-
- PUSH {R0,LR} // Save SP and EXC_RETURN
- LDR R12,[R2,R1,LSL #2] // Load address of SVC function
- LDM R0,{R0-R3} // Load function parameters from stack
- BLX R12 // Call service function
- POP {R12,LR} // Restore SP and EXC_RETURN
- STR R0,[R12] // Store function return value
-
- BX LR // Return from handler
-
- .fnend
- .size SVC_Handler, .-SVC_Handler
-
-
- .thumb_func
- .type PendSV_Handler, %function
- .global PendSV_Handler
- .fnstart
- .cantunwind
-PendSV_Handler:
-
- PUSH {R0,LR} // Save EXC_RETURN
- BL osRtxPendSV_Handler // Call osRtxPendSV_Handler
- POP {R0,LR} // Restore EXC_RETURN
- MRS R12,PSP
- B SVC_Context
-
- .fnend
- .size PendSV_Handler, .-PendSV_Handler
-
-
- .thumb_func
- .type SysTick_Handler, %function
- .global SysTick_Handler
- .fnstart
- .cantunwind
-SysTick_Handler:
-
- PUSH {R0,LR} // Save EXC_RETURN
- BL osRtxTick_Handler // Call osRtxTick_Handler
- POP {R0,LR} // Restore EXC_RETURN
- MRS R12,PSP
- B SVC_Context
-
- .fnend
- .size SysTick_Handler, .-SysTick_Handler
-
-
- .end
diff --git a/CMSIS/RTOS2/RTX/Source/IAR/irq_cm0.s b/CMSIS/RTOS2/RTX/Source/IAR/irq_armv6m.s
similarity index 91%
rename from CMSIS/RTOS2/RTX/Source/IAR/irq_cm0.s
rename to CMSIS/RTOS2/RTX/Source/IAR/irq_armv6m.s
index 3ca51f6701..f32b195990 100644
--- a/CMSIS/RTOS2/RTX/Source/IAR/irq_cm0.s
+++ b/CMSIS/RTOS2/RTX/Source/IAR/irq_armv6m.s
@@ -1,5 +1,5 @@
;/*
-; * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+; * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -18,13 +18,13 @@
; * -----------------------------------------------------------------------------
; *
; * Project: CMSIS-RTOS RTX
-; * Title: Cortex-M0 Exception handlers
+; * Title: ARMv6-M Exception handlers
; *
; * -----------------------------------------------------------------------------
; */
- NAME irq_cm0.s
+ NAME irq_armv6m.s
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
@@ -57,7 +57,7 @@ SVC_Number
LDR R1,[R0,#24] ; Load saved PC from stack
SUBS R1,R1,#2 ; Point to SVC instruction
LDRB R1,[R1] ; Load SVC number
- CMP R1,#0
+ CMP R1,#0 ; Check SVC number
BNE SVC_User ; Branch if not SVC 0
PUSH {R0,LR} ; Save SP and EXC_RETURN
@@ -68,7 +68,7 @@ SVC_Number
MOV LR,R3 ; Set EXC_RETURN
SVC_Context
- LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+ LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run
LDMIA R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
BEQ SVC_Exit ; Branch when threads are the same
@@ -78,7 +78,7 @@ SVC_Context
SVC_ContextSave
MRS R0,PSP ; Get PSP
- SUBS R0,R0,#32 ; Calculate SP
+ SUBS R0,R0,#32 ; Calculate SP: space for R4..R11
STR R0,[R1,#TCB_SP_OFS] ; Store SP
STMIA R0!,{R4-R7} ; Save R4..R7
MOV R4,R8
@@ -103,7 +103,7 @@ SVC_ContextRestore
SUBS R0,R0,#32 ; Adjust address
LDMIA R0!,{R4-R7} ; Restore R4..R7
- MOVS R0,#~0xFFFFFFFD
+ MOVS R0,#2 ; Binary complement of 0xFFFFFFFD
MVNS R0,R0 ; Set EXC_RETURN value
BX R0 ; Exit from handler
@@ -141,7 +141,7 @@ PendSV_Handler
BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
POP {R0,R1} ; Restore EXC_RETURN
MOV LR,R1 ; Set EXC_RETURN
- B SVC_Context
+ B SVC_Context ; Branch to context handling
SysTick_Handler
@@ -152,7 +152,7 @@ SysTick_Handler
BL osRtxTick_Handler ; Call osRtxTick_Handler
POP {R0,R1} ; Restore EXC_RETURN
MOV LR,R1 ; Set EXC_RETURN
- B SVC_Context
+ B SVC_Context ; Branch to context handling
END
diff --git a/CMSIS/RTOS2/RTX/Source/IAR/irq_ca.s b/CMSIS/RTOS2/RTX/Source/IAR/irq_armv7a.s
similarity index 98%
rename from CMSIS/RTOS2/RTX/Source/IAR/irq_ca.s
rename to CMSIS/RTOS2/RTX/Source/IAR/irq_armv7a.s
index 975b30dcd6..9e27930a0e 100644
--- a/CMSIS/RTOS2/RTX/Source/IAR/irq_ca.s
+++ b/CMSIS/RTOS2/RTX/Source/IAR/irq_armv7a.s
@@ -1,5 +1,5 @@
;/*
-; * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+; * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -18,12 +18,13 @@
; * -----------------------------------------------------------------------------
; *
; * Project: CMSIS-RTOS RTX
-; * Title: Cortex-A Exception handlers
+; * Title: ARMv7-A Exception handlers
; *
; * -----------------------------------------------------------------------------
; */
- NAME irq_ca.s
+ NAME irq_armv7a.s
+
MODE_FIQ EQU 0x11
MODE_IRQ EQU 0x12
@@ -352,16 +353,16 @@ osRtxContextSave
STMDB R1!, {R2,R12} ; Push FPSCR, maintain 8-byte alignment
VSTMDB R1!, {D0-D15} ; Save D0-D15
- #ifdef __ARM_ADVANCED_SIMD__
+ #ifdef __ARM_ADVANCED_SIMD__
VSTMDB R1!, {D16-D31} ; Save D16-D31
- #endif
+ #endif
LDRB R2, [LR, #TCB_SP_FRAME] ; Load osRtxInfo.thread.run.curr frame info
- #ifdef __ARM_ADVANCED_SIMD__
+ #ifdef __ARM_ADVANCED_SIMD__
ORR R2, R2, #4 ; NEON state
- #else
+ #else
ORR R2, R2, #2 ; VFP state
- #endif
+ #endif
STRB R2, [LR, #TCB_SP_FRAME] ; Store VFP/NEON state
osRtxContextSave1
@@ -413,9 +414,9 @@ osRtxContextRestore
MCR p15, 0, R2, c1, c0, 2 ; Write CPACR
BEQ osRtxContextRestore1 ; No VFP
ISB ; Sync if VFP was enabled
- #ifdef __ARM_ADVANCED_SIMD__
+ #ifdef __ARM_ADVANCED_SIMD__
VLDMIA LR!, {D16-D31} ; Restore D16-D31
- #endif
+ #endif
VLDMIA LR!, {D0-D15} ; Restore D0-D15
LDR R2, [LR]
VMSR FPSCR, R2 ; Restore FPSCR
diff --git a/CMSIS/RTOS2/RTX/Source/IAR/irq_cm4f.s b/CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s
similarity index 73%
rename from CMSIS/RTOS2/RTX/Source/IAR/irq_cm4f.s
rename to CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s
index 5a956481e8..142c9a93b1 100644
--- a/CMSIS/RTOS2/RTX/Source/IAR/irq_cm4f.s
+++ b/CMSIS/RTOS2/RTX/Source/IAR/irq_armv7m.s
@@ -1,5 +1,5 @@
;/*
-; * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+; * Copyright (c) 2013-2021 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -18,19 +18,27 @@
; * -----------------------------------------------------------------------------
; *
; * Project: CMSIS-RTOS RTX
-; * Title: Cortex-M4F Exception handlers
+; * Title: ARMv7-M Exception handlers
; *
; * -----------------------------------------------------------------------------
; */
- NAME irq_cm4f.s
+ NAME irq_armv7m.s
+#ifdef __ARMVFP__
+FPU_USED EQU 1
+#else
+FPU_USED EQU 0
+#endif
+
I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
TCB_SP_OFS EQU 56 ; TCB.SP offset
TCB_SF_OFS EQU 34 ; TCB.stack_frame offset
+FPCCR EQU 0xE000EF34 ; FPCCR Address
+
PRESERVE8
SECTION .rodata:DATA:NOROOT(2)
@@ -65,40 +73,49 @@ SVC_Handler
STM R12,{R0-R1} ; Store function return values
SVC_Context
- LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+ LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.thread.run
LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
CMP R1,R2 ; Check if thread switch is required
IT EQ
BXEQ LR ; Exit when threads are the same
+ #if (FPU_USED != 0)
CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted
- TST LR,#0x10 ; Check if extended stack frame
- BNE SVC_ContextSwitch
- LDR R1,=0xE000EF34 ; FPCCR Address
- LDR R0,[R1] ; Load FPCCR
- BIC R0,R0,#1 ; Clear LSPACT (Lazy state)
- STR R0,[R1] ; Store FPCCR
- B SVC_ContextSwitch
+ TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4
+ BNE SVC_ContextSwitch ; Branch if not extended stack frame
+ LDR R3,=FPCCR ; FPCCR Address
+ LDR R0,[R3] ; Load FPCCR
+ BIC R0,R0,#1 ; Clear LSPACT (Lazy state preservation)
+ STR R0,[R3] ; Store FPCCR
+ B SVC_ContextSwitch ; Branch to context switch handling
+ #else
+ CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted
+ #endif
SVC_ContextSave
STMDB R12!,{R4-R11} ; Save R4..R11
- TST LR,#0x10 ; Check if extended stack frame
- IT EQ
+ #if (FPU_USED != 0)
+ TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4
+ IT EQ ; If extended stack frame
VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31
- STR R12,[R1,#TCB_SP_OFS] ; Store SP
STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information
+ #endif
+ STR R12,[R1,#TCB_SP_OFS] ; Store SP
SVC_ContextSwitch
STR R2,[R3] ; osRtxInfo.thread.run: curr = next
SVC_ContextRestore
- LDRB R1,[R2,#TCB_SF_OFS] ; Load stack frame information
LDR R0,[R2,#TCB_SP_OFS] ; Load SP
- ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN
-
- TST LR,#0x10 ; Check if extended stack frame
- IT EQ
+ #if (FPU_USED != 0)
+ LDRB R1,[R2,#TCB_SF_OFS] ; Load stack frame information
+ ORN LR,R1,#0xFF ; Set EXC_RETURN
+ TST LR,#0x10 ; Determine stack frame from EXC_RETURN bit 4
+ IT EQ ; If extended stack frame
VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31
+ #else
+ MVN LR,#~0xFFFFFFFD ; Set EXC_RETURN value
+ #endif
LDMIA R0!,{R4-R11} ; Restore R4..R11
MSR PSP,R0 ; Set PSP
@@ -128,8 +145,8 @@ PendSV_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
POP {R0,LR} ; Restore EXC_RETURN
- MRS R12,PSP
- B SVC_Context
+ MRS R12,PSP ; Save PSP to R12
+ B SVC_Context ; Branch to context handling
SysTick_Handler
@@ -139,8 +156,8 @@ SysTick_Handler
PUSH {R0,LR} ; Save EXC_RETURN
BL osRtxTick_Handler ; Call osRtxTick_Handler
POP {R0,LR} ; Restore EXC_RETURN
- MRS R12,PSP
- B SVC_Context
+ MRS R12,PSP ; Save PSP to R12
+ B SVC_Context ; Branch to context handling
END
diff --git a/CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s b/CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s
deleted file mode 100644
index 29fe1b727e..0000000000
--- a/CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.s
+++ /dev/null
@@ -1,130 +0,0 @@
-;/*
-; * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; *
-; * -----------------------------------------------------------------------------
-; *
-; * Project: CMSIS-RTOS RTX
-; * Title: Cortex-M3 Exception handlers
-; *
-; * -----------------------------------------------------------------------------
-; */
-
-
- NAME irq_cm3.s
-
-
-I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset
-TCB_SP_OFS EQU 56 ; TCB.SP offset
-
-
- PRESERVE8
- SECTION .rodata:DATA:NOROOT(2)
-
-
- EXPORT irqRtxLib
-irqRtxLib DCB 0 ; Non weak library reference
-
-
- THUMB
- SECTION .text:CODE:NOROOT(2)
-
-
-SVC_Handler
- EXPORT SVC_Handler
- IMPORT osRtxUserSVC
- IMPORT osRtxInfo
-
- TST LR,#0x04 ; Determine return stack from EXC_RETURN bit 2
- ITE EQ
- MRSEQ R0,MSP ; Get MSP if return stack is MSP
- MRSNE R0,PSP ; Get PSP if return stack is PSP
-
- LDR R1,[R0,#24] ; Load saved PC from stack
- LDRB R1,[R1,#-2] ; Load SVC number
- CBNZ R1,SVC_User ; Branch if not SVC 0
-
- PUSH {R0,LR} ; Save SP and EXC_RETURN
- LDM R0,{R0-R3,R12} ; Load function parameters and address from stack
- BLX R12 ; Call service function
- POP {R12,LR} ; Restore SP and EXC_RETURN
- STM R12,{R0-R1} ; Store function return values
-
-SVC_Context
- LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
- LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next
- CMP R1,R2 ; Check if thread switch is required
- IT EQ
- BXEQ LR ; Exit when threads are the same
-
- CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted
-
-SVC_ContextSave
- STMDB R12!,{R4-R11} ; Save R4..R11
- STR R12,[R1,#TCB_SP_OFS] ; Store SP
-
-SVC_ContextSwitch
- STR R2,[R3] ; osRtxInfo.thread.run: curr = next
-
-SVC_ContextRestore
- LDR R0,[R2,#TCB_SP_OFS] ; Load SP
- LDMIA R0!,{R4-R11} ; Restore R4..R11
- MSR PSP,R0 ; Set PSP
-
- MVN LR,#~0xFFFFFFFD ; Set EXC_RETURN value
-
-SVC_Exit
- BX LR ; Exit from handler
-
-SVC_User
- LDR R2,=osRtxUserSVC ; Load address of SVC table
- LDR R3,[R2] ; Load SVC maximum number
- CMP R1,R3 ; Check SVC number range
- BHI SVC_Exit ; Branch if out of range
-
- PUSH {R0,LR} ; Save SP and EXC_RETURN
- LDR R12,[R2,R1,LSL #2] ; Load address of SVC function
- LDM R0,{R0-R3} ; Load function parameters from stack
- BLX R12 ; Call service function
- POP {R12,LR} ; Restore SP and EXC_RETURN
- STR R0,[R12] ; Store function return value
-
- BX LR ; Return from handler
-
-
-PendSV_Handler
- EXPORT PendSV_Handler
- IMPORT osRtxPendSV_Handler
-
- PUSH {R0,LR} ; Save EXC_RETURN
- BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler
- POP {R0,LR} ; Restore EXC_RETURN
- MRS R12,PSP
- B SVC_Context
-
-
-SysTick_Handler
- EXPORT SysTick_Handler
- IMPORT osRtxTick_Handler
-
- PUSH {R0,LR} ; Save EXC_RETURN
- BL osRtxTick_Handler ; Call osRtxTick_Handler
- POP {R0,LR} ; Restore EXC_RETURN
- MRS R12,PSP
- B SVC_Context
-
-
- END