Add intrinsic support for the SVE multi-vector Advanced Encryption Standard (AES) instructions #411

amilendra · 2025-09-15T14:46:57Z

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main/acle.md

georges-arm · 2025-09-17T14:21:03Z

main/acle.md

+svuint8x2_t    svaesemc[_u8_x2]   (svuint8x2_t op1, svuint64_t op2, uint64_t index);
+svuint8x4_t    svaesemc[_u8_x4]   (svuint8x4_t op1, svuint64_t op2, uint64_t index);
+svuint8x2_t    svaesdimc[_u8_x2]  (svuint8x2_t op1, svuint64_t op2, uint64_t index);
+svuint8x4_t    svaesdimc[_u8_x4]  (svuint8x4_t op1, svuint64_t op2, uint64_t index);


All of these instructions are destructive encodings (the output register is also an input register), so we should have an additional parameter for all of these?

Not sure I understand what you mean about one more parameter:
NAME: Zd, Zd, Zm[index]
Zd = op1
Zm = op2
index=index.
Op1 is input and output.

AESE: https://developer.arm.com/documentation/ddi0602/2025-06/SVE-Instructions/AESE--indexed---Multi-vector-AES-single-round-encryption-
AESD: https://developer.arm.com/documentation/ddi0602/2025-06/SVE-Instructions/AESD--indexed---Multi-vector-AES-single-round-decryption-
AESEMC: https://developer.arm.com/documentation/ddi0602/2025-06/SVE-Instructions/AESEMC--Multi-vector-AES-single-round-encryption-and-mix-columns-
AESDIMC: https://developer.arm.com/documentation/ddi0602/2025-06/SVE-Instructions/AESDIMC--Multi-vector-AES-single-round-decryption-and-inverse-mix-columns-

Nevermind, I had misread that the Zdn register parameters were duplicated!

Is there anything I should do for this or can this be resolved?

AlfieRichardsArm

I think this should use SSVE_AES instead of SSVE_AES2

I believe the two FEATs here are FEAT_SSVE_AES and FEAT_SVE_AES2. FEAT_SSVE_AES2 doesn't exist from what I can see.

main/acle.md

CarolineConcatto · 2025-09-22T10:08:31Z

main/acle.md

+svuint8x2_t    svaesemc[_u8_x2]   (svuint8x2_t op1, svuint64_t op2, uint64_t index);
+svuint8x4_t    svaesemc[_u8_x4]   (svuint8x4_t op1, svuint64_t op2, uint64_t index);
+svuint8x2_t    svaesdimc[_u8_x2]  (svuint8x2_t op1, svuint64_t op2, uint64_t index);
+svuint8x4_t    svaesdimc[_u8_x4]  (svuint8x4_t op1, svuint64_t op2, uint64_t index);


Not sure I understand what you mean about one more parameter:
NAME: Zd, Zd, Zm[index]
Zd = op1
Zm = op2
index=index.
Op1 is input and output.

AESE: https://developer.arm.com/documentation/ddi0602/2025-06/SVE-Instructions/AESE--indexed---Multi-vector-AES-single-round-encryption-
AESD: https://developer.arm.com/documentation/ddi0602/2025-06/SVE-Instructions/AESD--indexed---Multi-vector-AES-single-round-decryption-
AESEMC: https://developer.arm.com/documentation/ddi0602/2025-06/SVE-Instructions/AESEMC--Multi-vector-AES-single-round-encryption-and-mix-columns-
AESDIMC: https://developer.arm.com/documentation/ddi0602/2025-06/SVE-Instructions/AESDIMC--Multi-vector-AES-single-round-decryption-and-inverse-mix-columns-

main/acle.md

…pISA FEAT_SVE_AES2 adds 1) SVE multi-vector Advanced Encryption Standard (AES) instructions Instructions added: AESE, AESD, AESEMC and AESDIMC For each instruction there are two variants a) Two registers variant b) Four registers variant 2) SVE multi-vector 128-bit polynomial multiply long instructions Instructions added: PMULL and PMLAL FEAT_SSVE_AES implements the same instructions but when in streaming mode.

1.__ARM_FEATURE_SSVE_AES2 -> __ARM_FEATURE_SSVE_AES 2. Move the intrinsics to their own section under SVE2

main/acle.md

- __ARM_FEATURE_SVE2_AES2 -> __ARM_FEATURE_SVE_AES2 - Add _lane prefix

CarolineConcatto · 2025-10-16T09:35:41Z

main/acle.md

 and `__ARM_FEATURE_SVE2` are both nonzero.

+In addition, `__ARM_FEATURE_SVE_AES2` is defined to `1` if there is hardware
+support for the SVE2 AES2 (FEAT_SVE_AES2) instructions and if the associated


Why are you saying it is support for SVE2?
I believe it should be SVE AES2.
The description for the instruction does not have sve2, does it?
https://developer.arm.com/documentation/ddi0602/2025-09/SVE-Instructions/AESD--indexed---Multi-vector-AES-single-round-decryption-?lang=en

Typos. Fixed here and some other places as well. Thanks.

kmclaughlin-arm · 2025-10-23T15:12:43Z

main/acle.md

+  svuint8x2_t    svaesemc_lane[_u8_x2]   (svuint8x2_t op1, svuint64_t op2, uint64_t index);
+  svuint8x4_t    svaesemc_lane[_u8_x4]   (svuint8x4_t op1, svuint64_t op2, uint64_t index);
+  svuint8x2_t    svaesdimc_lane[_u8_x2]  (svuint8x2_t op1, svuint64_t op2, uint64_t index);
+  svuint8x4_t    svaesdimc_lane[_u8_x4]  (svuint8x4_t op1, svuint64_t op2, uint64_t index);


Should the parameter names match the symbol names? e.g.

svuint8x4_t svaesdimc_lane[_u8_x4] (svuint8x4_t zdn, svuint64_t zm, uint64_t index);

I think that would make it easier to map the parameters to the respective register names in the ISA doc. However existing AES intrinsics follow the current convention.
https://developer.arm.com/architectures/instruction-sets/intrinsics/#q=aes
@CarolineConcatto , @Lukacma what do you think?

georges-arm reviewed Sep 15, 2025

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amilendra force-pushed the 2025-acle-sve-aes2 branch from a23e878 to 12b0669 Compare September 16, 2025 12:41

georges-arm reviewed Sep 17, 2025

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AlfieRichardsArm reviewed Sep 18, 2025

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CarolineConcatto reviewed Sep 22, 2025

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amilendra force-pushed the 2025-acle-sve-aes2 branch 3 times, most recently from dca98df to 83378b8 Compare October 1, 2025 14:15

amilendra force-pushed the 2025-acle-sve-aes2 branch from 2716761 to e8fb4e7 Compare October 7, 2025 14:11

Fix the AES2 review comments.

4505e29

1.__ARM_FEATURE_SSVE_AES2 -> __ARM_FEATURE_SSVE_AES 2. Move the intrinsics to their own section under SVE2

CarolineConcatto reviewed Oct 10, 2025

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amilendra added 2 commits October 10, 2025 10:02

Add SVE2 AES2 support status (Alpha) to the content

9612674

[PMLAL] Add svuint64x2_t zda which acts as both input/output

1a26687

Lukacma reviewed Oct 13, 2025

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Lukacma reviewed Oct 13, 2025

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Address further AES2 review comments

3909c74

- __ARM_FEATURE_SVE2_AES2 -> __ARM_FEATURE_SVE_AES2 - Add _lane prefix

CarolineConcatto reviewed Oct 16, 2025

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Fix Typos: SVE2 -> SVE

91e71c0

kmclaughlin-arm reviewed Oct 23, 2025

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This was referenced Oct 27, 2025

[AArch64] Add intrinsics for 9.6 crypto instructions llvm/llvm-project#165241

Closed

[AArch64] Add intrinsics for 9.6 crypto instructions llvm/llvm-project#165545

Open

Add intrinsic support for the SVE multi-vector Advanced Encryption Standard (AES) instructions #411

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Add intrinsic support for the SVE multi-vector Advanced Encryption Standard (AES) instructions #411

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amilendra commented Sep 15, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

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